TMC8460-EVAL [TRINAMIC]

Integrated EtherCAT Slave Controller;
TMC8460-EVAL
型号: TMC8460-EVAL
厂家: TRINAMIC MOTION CONTROL GMBH & CO. KG.    TRINAMIC MOTION CONTROL GMBH & CO. KG.
描述:

Integrated EtherCAT Slave Controller

文件: 总145页 (文件大小:4600K)
中文:  中文翻译
下载:  下载PDF数据表文档文件
TMC8460 PRELIMINARY, CONFIDENTIAL TARGET, NON-RELEASE VERSION Datasheet (V014 / 2015-Aug-31)  
TMC8460-BI  
Integrated EtherCAT Slave Controller with  
Enhanced Functionality  
TRINAMIC® Motion Control GmbH & Co. KG  
Hamburg, GERMANY  
www.trinamic.com  
The TMC8460 is an EtherCAT Slave Controller (ESC) used for EtherCAT communicton. It provides he  
interface for data exchange between EtherCAT master and the slave’s local applicaon controller.  
TMC8460 also provides a large set of complex real-time IO features in ardwaith focus on motor  
and motion control applications and systems.  
Focus  
Easiest to use ESC / Simplicity / Industrial  
License-free / requirements for customer  
Robust / Availability / Flexibility / Motor Control / Motion ontrol  
Features  
Standard compliant EtherCAT Slave Controllregister et with 2 MII ports, 6 FMMU, 6 Sync  
Managers, Distributed clocks (64 bit), 1KbytESC RAM size  
External I²C EEPROM  
SPI Process Data Interface (PDI) with up to 30Mbit/s  
SPI interface for Trinamic ulti-Funtion anControl IO Block (MFCIO) with up to 30Mbit/s  
Optional Device Emulation mde  
Trinamic Multi-Function and Conol IO Block (MFCIO)  
o 8 Digital genose I, individually configurable  
o Incrementaer input (ABN), single ended  
o Step & irecoutpuwith internal step rate generator  
o 3-ch PWM blocwith onfigurable frequency, duty cycle, dead times  
o GeneriSPI master interface with up to 4 slaves, e.g., to connect Trinamic ICs  
o Configurle IRQ and event signal  
urablwatchdog for outputs and inputs  
configuration via EEPROM or from MCU  
16MHut, e.g., for MCU or Trinamic ICs or other peripherals  
Operatinoltages: 3V3 and 1V2  
Industrial tmperature range: -40°C to +100°C  
Package: VFGG400, 17mmx17mm Very Fine Pitch Ball Grid Array, 0.8mm pitch  
TMC8460 PRELIMINARY, CONFIDENTIAL TARGET, NON-RELEASE VERSION Datasheet (V014 / 2015-Aug-31)  
Table of Contents  
TABLE OF CONTENTS...........................................................................................................................................................2  
LIST OF FIGURES..................................................................................................................................................................5  
LIST OF TABLES....................................................................................................................................................................6  
1
2
ABBREVIATIONS..........................................................................................................................................................9  
PRINCIPLES OF OPERATION..................................................................................................................................10  
2.1  
KEY CONCEPTS........................................................................................................................................................10  
EtherCAT Slave Controller (ESC).........................................................................................................10  
Trinamic Multi-Function and Control IO Block.............................................................................10  
CONFIGURATION OPTIONS..................................................................................................................................11  
CONTROL INTERFACES.........................................................................................................................................12  
Ethernet Interface.............................................................................................................................12  
Process Data Interface.................................................................................................................12  
Multi-Function and Control IO Block Interface....................................................................12  
SPI Bus Sharing.................................................................................................................................12  
Configuration Inputs .....................................................................................................................12  
EEPROM Interface........................................................................................................................12  
SOFTWARE VIEW....................................................................................................................................12  
2.1.1  
2.1.2  
2.2  
2.3  
2.3.1  
2.3.2  
2.3.3  
2.3.4  
2.3.5  
2.3.6  
2.4  
3
DEVICE USAGE AND HANDLING..........................................................................................................18  
3.1  
SAMPLE BLOCK DIAGRAMS...........................................................................................................................18  
Typical EtherCAT Slave architecture .............................................................................................18  
MFCIO block based Microcontroller Architeture.....................................................................18  
Device Emulation Example..........................................................................................................19  
SAMPLES CIRCUITS..........................................................................................................................................20  
IC supply.........................................................................................................................................20  
PDI interface........................................................................................................................................20  
Miscellaneous signls.....................................................................................................................20  
MII 1 (EtherCAT Input)......................................................................................................................21  
MII 2 (EtherCAT utput).................................................................................................................21  
MFC I/Os................................................................................................................................................22  
PINOUT AND PIN DESCRIPTION .......................................................................................................................23  
ETHERNET PHYS..................................................................................................................................31  
Ethernet Pinterface and MI interface ...............................................................................31  
PHY Cnfition Ps.........................................................................................................................32  
PDI SPI.........................................................................................................................................................32  
SPI otocol description......................................................................................................................33  
Timing xample.......................................................................................................................................36  
SPI ..................................................................................................................................................37  
g example.......................................................................................................................................39  
g Bus Lines with PDI SPI........................................................................................................39  
EEPINTERFACE..............................................................................................................................................40  
VENDOID, ESC TYPE, ESC REVISION AND BUILD HISTORY............................................................................41  
ELECTRICACHARACTERISTICS...............................................................................................................................42  
Operating Conditions.............................................................................................................................42  
External CLK Source................................................................................................................................42  
IO Characteristics....................................................................................................................................42  
Power Consumption..............................................................................................................................43  
Package Thermal Behavior..................................................................................................................43  
3.1.1  
3.1.2  
3.1.3  
3.2  
3.2.1  
3.2.2  
3.2.3  
3.2.4  
3.2.5  
3.2.6  
3.3  
3.4  
3.4.1  
3.4.2  
3.5  
3.5.1  
3.5.2  
3.6  
3.
3.6.2  
3.7  
3.8  
3.9  
3.9.1  
3.9.2  
3.9.3  
3.9.4  
3.9.5  
3.10 MARKING AND ORDER CODES................................................................................................................................44  
3.11 PACKAGE DIMENSIONS...........................................................................................................................................44  
3.12 LAYOUT CONSIDERATIONS.....................................................................................................................................46  
3.12.1  
Example layout of the TMC8460-Eval...............................................................................................47  
3.13 SOLDERING PROFILE...............................................................................................................................................48  
 
TMC8460 PRELIMINARY, CONFIDENTIAL TARGET, NON-RELEASE VERSION Datasheet (V014 / 2015-Aug-31)  
4
5
ETHERCAT ADDRESS SPACE OVERVIEW.............................................................................................................49  
ETHERCAT REGISTER DESCRIPTION....................................................................................................................54  
5.1  
TYPE (0X0000).......................................................................................................................................................54  
REVISION (0X0001)...............................................................................................................................................54  
BUILD (0X0002:0X0003).......................................................................................................................................54  
FMMUS SUPPORTED (0X0004)..............................................................................................................................54  
SYNCMANAGERS SUPPORTED (0X0005)................................................................................................................54  
RAM SIZE (0X0006)..............................................................................................................................................54  
PORT DESCRIPTOR (0X0007).................................................................................................................................55  
ESC FEATURES SUPPORTED (0X0008:0X0009).....................................................................................................55  
CONFIGURED STATION ADDRESS (0X0010:0X0011)............................................................................................56  
5.2  
5.3  
5.4  
5.5  
5.6  
5.7  
5.8  
5.9  
5.10 CONFIGURED STATION ALIAS (0X0012:0X0013)..............................................................................................56  
5.11 WRITE REGISTER ENABLE (0X0020) ..................................................................................................................56  
5.12 WRITE REGISTER PROTECTION (0X0021).........................................................................................................57  
5.13 ESC WRITE ENABLE (0X0030).....................................................................................................................57  
5.14 ESC WRITE PROTECTION (0X0031)...............................................................................................................57  
5.15 ESC RESET ECAT (0X0040)............................................................................................................................58  
5.16 ESC RESET PDI (0X0041)..........................................................................................................................58  
5.17 ESC DL CONTROL (0X0100:0X0103).........................................................................................................58  
5.18 PHYSICAL READ/WRITE OFFSET (0X0108:0X0109)..........................................................................60  
5.19 ESC DL STATUS (0X0110:0X0111).......................................................................................................60  
5.20 AL CONTROL (0X0120:0X0121)..............................................................................................................63  
5.21 AL STATUS (0X0130:0X0131).........................................................................................................................63  
5.22 AL STATUS CODE (0X0134:0X0135)..............................................................................................................64  
5.23 RUN LED OVERRIDE (0X0138)........................................................................................................................64  
5.24 ERR LED OVERRIDE (0X0139).........................................................................................................................64  
5.25 PDI CONTROL (0X0140)...............................................................................................................................65  
5.26 ESC CONFIGURATION (0X0141)......................................................................................................................65  
5.27 PDI INFORMATION (0X014E:0X014F)...........................................................................................................66  
5.28 PDI CONFIGURATION (0X0150:0X01..........................................................................................................66  
5.28.1  
5.28.2  
PDI SPI Slave Configuration...........................................................................................................66  
Sync/Latch[1:0] DI Conguratin....................................................................................................67  
5.29 ECAT EVENT MASK (0X0200X0201................................................................................................................68  
5.30 PDI AL EVENT MASK (0X0204X0207)...........................................................................................................68  
5.31 ECAT EVENT REQUE0210:0211)............................................................................................................69  
5.32 AL EVENT REQUE0:0X0223).................................................................................................................69  
5.33 RX ERROR COUN0300:X0307)................................................................................................................71  
5.34 FORWARDERX ERR COUNER (0X0308:0X030B).........................................................................................71  
5.35 ECAT PRESSING UNIT ERROR COUNTER (0X030C).........................................................................................71  
5.36 PDI ERROR UNTER (0X030D)...........................................................................................................................71  
5.37 ERROR CODE (0X030E)..........................................................................................................................71  
5.38 OUNTER (0X0310:0X0313)................................................................................................................72  
5.39 DIVIDER (0X0400:0X0401)..............................................................................................................72  
5.40 WTIME PDI (0X0410:0X0411) ...........................................................................................................72  
5.41 WATCDOG TIME PROCESS DATA (0X0420:0X0421)..........................................................................................72  
5.42 WATCHDG STATUS PROCESS DATA (0X0440:0X0441).....................................................................................73  
5.43 WATCHDOG COUNTER PROCESS DATA (0X0442).................................................................................................73  
5.44 WATCHDOG COUNTER PDI (0X0443)...................................................................................................................73  
5.45 SII EEPROM INTERFACE (0X0500:0X050F) .......................................................................................................73  
5.45.1  
EEPROM emulation with TMC8460.....................................................................................................77  
5.46 MII MANAGEMENT INTERFACE (0X0510:0X0515)................................................................................................77  
5.47 PARAMETER RAM (0X0580:0X05AB) FOR TMC8460 MFCIO BLOCK CONFIGURATION ...................................82  
5.48 FMMU (0X0600:0X06FF)......................................................................................................................................83  
5.49 SYNCMANAGER (0X0800:0X087F)........................................................................................................................85  
5.50 DISTRIBUTED CLOCKS (0X0900:0X09FF)..............................................................................................................89  
5.50.1  
Receive Times...........................................................................................................................................89  
5.50.2  
Time Loop Control Unit ........................................................................................................................91  
TMC8460 PRELIMINARY, CONFIDENTIAL TARGET, NON-RELEASE VERSION Datasheet (V014 / 2015-Aug-31)  
5.50.3  
5.50.4  
5.50.5  
5.50.6  
Cyclic Unit Control..................................................................................................................................95  
SYNC Out Unit...........................................................................................................................................96  
Latch In unit .............................................................................................................................................99  
SyncManager Event Times.................................................................................................................103  
5.51 ESC SPECIFIC PRODUCT AND VENDOR ID..........................................................................................................104  
5.52 USER RAM (0X0F80:0X0FFF).............................................................................................................................104  
5.53 PROCESS DATA RAM (0X1000:0XFFFF)............................................................................................................105  
5.53.1  
MFCIO Block ECAT Write Data Memory Block (0x4000:0x405F).............................................105  
5.53.2  
MFCIO Block ECAT Read Data Memory Block (0x4800:0x4823)..............................................106  
6
ETHERCAT TECHNOLOGY........................................................................................................................................108  
6.1  
6.2  
6.2.1  
GENERAL INFORMATION ON ETHERCAT..............................................................................................................108  
MAJOR ETHERCAT MECHANISMS......................................................................................................................108  
EtherCAT State Machine (ESM).......................................................................................................108  
EtherCAT Slave Controller RAM / Process Data RAM (PDRAM).........................................109  
Fieldbus Memory Management Unit (FMMU) .....................................................................110  
SyncManagers (SM)........................................................................................................................110  
Distributed Clocks (DC).................................................................................................................110  
TMC8460-SPECIFIC ETHERCAT FEATURES................................................................................................110  
6.2.2  
6.2.3  
6.2.4  
6.2.5  
6.3  
7
MFCIO BLOCK REGISTER AND FUNCTIONAL DESCRIPTION ........................................................111  
7.1  
MFCIO BLOCK GENERAL INFORMATION ..............................................................................................111  
MFCIO BLOCK ADDRESS SPACE OVERVIEW........................................................................................112  
MFCIO BLOCK EEPROM PARAMETER MAP...................................................................................................114  
MFCIO REGISTER CONFIGURATION...............................................................................................................114  
MFCIO EMERGENCY SWITCH INPUT.............................................................................................................116  
MFC INCREMENTAL ENCODER UNIT.................................................................................................................116  
MFC Incremental Encoder Unit Sigals...................................................................................116  
MFC Incremental Encoder Unit Register Se...............................................................................117  
ENC_MODE.........................................................................................................................................117  
ENC_STATUS .....................................................................................................................................118  
ENC_X (W) ............................................................................................................................................118  
ENC_X (R).........................................................................................................................................118  
ENC_CONST .......................................................................................................................................118  
ENC_LATCH.........................................................................................................................................118  
MFC SPI MASTER U...............................................................................................................................120  
MFC SPI Mnit Signals.............................................................................................................120  
MFC SPI MUnit egister Set...................................................................................................120  
SPI_X_DAT.......................................................................................................................................121  
SPIX_DATA ..........................................................................................................................................121  
SPI_CNF..................................................................................................................................................121  
_STATS.............................................................................................................................................121  
ENGTH .............................................................................................................................................121  
ME...................................................................................................................................................121  
xamples..........................................................................................................................................122  
MFC EP DIRECTION UNIT................................................................................................................................124  
MFStep Direction Unit Timing ......................................................................................................124  
MFC Step Direction Unit Signals......................................................................................................125  
MFC Step Direction Unit and Register Set...................................................................................125  
Step Direction Accumulation Constant.........................................................................................126  
Step Counter...........................................................................................................................................127  
Step Target..............................................................................................................................................127  
Step Length.............................................................................................................................................127  
Step-to-Direction Delay.......................................................................................................................127  
Step Direction Unit Configuration ..................................................................................................127  
Interrupt Output Signal......................................................................................................................127  
MFC PWM UNIT.................................................................................................................................................128  
MFC PWM Block Signals......................................................................................................................129  
7.2  
7.3  
7.4  
7.5  
7.6  
7.6.1  
7.6.2  
7.6.3  
7.6.4  
7.6.5  
7.6.6  
7.6.7  
7.6.8  
7.7  
7.7.1  
7.7.2  
7.7.3  
7.7.4  
7.7.5  
7.7.6  
7.7.
7.7.
7.7.9  
7.8  
2.1.1  
2.1.2  
2.1.3  
7.8.1  
7.8.2  
7.8.3  
7.8.4  
7.8.5  
7.8.6  
7.8.7  
7.9  
2.1.4  
TMC8460 PRELIMINARY, CONFIDENTIAL TARGET, NON-RELEASE VERSION Datasheet (V014 / 2015-Aug-31)  
2.1.5  
7.9.1  
7.9.2  
7.9.3  
7.9.4  
7.9.5  
7.9.6  
7.9.7  
7.9.8  
7.9.9  
7.9.10  
7.9.11  
7.9.12  
7.9.13  
MFC PWM Unit and Register Set .....................................................................................................129  
PWM_MAXCNT Configuration Register..........................................................................................132  
PWM_CHOPMODE Configuration Register ....................................................................................132  
PWM_ALIGNMENT Configuration Register....................................................................................133  
POLARITIES Configuration Register...............................................................................................134  
PWM Value Registers...........................................................................................................................134  
PULSE_A Configuration Register......................................................................................................134  
PULSE_B Configuration Register......................................................................................................134  
PULSE_LENGTH Configuration Register..........................................................................................134  
Asymmetric PWM Configuration Registers..................................................................................134  
Brake-Before-Make (BBM) ...................................................................................................................134  
BBM_H Configuration Register.........................................................................................................135  
BBM_L Configuration Registers.....................................................................................................135  
Emergency Switch Input Off-State..............................................................................................135  
7.10 MFC GPIO UNIT.............................................................................................................................................136  
7.10.1  
7.10.2  
7.10.3  
7.10.4  
MFC GPIO Registers......................................................................................................................136  
General purpose Inputs (GPI)..................................................................................................136  
General purpose Outputs (GPO)................................................................................................136  
Emergency Switch Input State...............................................................................................136  
7.11 MFC WATCHDOG UNIT..............................................................................................................................137  
7.11.1  
7.11.2  
General Function................................................................................................................137  
Watchdog Register Set........................................................................................................137  
7.12 MFCIO IRQ UNIT AND REGISTER SET................................................................................................141  
2.1.6  
IRQ MASK Register ..........................................................................................................................141  
2.1.7  
IRQ_FLAGS Register.........................................................................................................................141  
7.13 AL STATE OVERRIDE CONFIGURATION..........................................................................................................142  
ESD SENSITIVE DEVICE...............................................................................................................................143  
DISCLAIMER........................................................................................................................................................143  
REVISION HISTORY........................................................................................................................................144  
8
9
10  
List of Figures  
FIGURE 1: TMCL-IDE WITH DIRECT RESTER ACSS TO THE TMC8460-BI ON ITS EVALUATION BOARD.......................13  
FIGURE 2 - WIZARD START SCREEN..................................................................................................................................14  
FIGURE 3 - WIZARD DEVICE AND ATURE SELECTION.......................................................................................15  
FIGURE 4 - WIZARD REGISTTION AND CONFIGURATION VIEW..............................................................................16  
FIGURE 5 - WIZARD OPUT W WITH EPROM CONFIGURATION STRING AND FIRMWARE C-CODE SNIPPETS............17  
FIGURE 6 - APPLICATON DIAGM USIG ONLY THE LOCAL APPLICATION CONTROLLER TO INTERFACE THE APPLICATION18  
FIGURE 7 - APPLICATN DIAGRAM USING THE MFCIO BLOCK FEATURES TO REDUCE SOFTWARE OVERHEAD AND PROVIDE  
REAL-TIARDWASUPPORT TO THE MCU. OTHER APPLICATION PARTS MAY STILL BE CONNECTED TO THE MCU.  
....................................................................................................................................................................19  
FIGURE N DIAGRAM WITHOUT MCU. THE TMC8460 IS USED IN DEVICE EMULATION MODE. SPI SLAVE  
CHIPS APPLICATION PERIPHERALS CAN BE CONNECTED TO THE MFCIO BLOCK. THE ETHERCAT MASTER  
CAN DIRECONTROL ALL THE APPLICATION FUNCTIONS..........................................................................................19  
FIGURE 9 - MII IERFACE SIGNALS .....................................................................................................................................31  
FIGURE 10 - PDI SPINTERFACE SIGNALS...........................................................................................................................33  
FIGURE 11 - 2 BYTE ADDRESSING MODE.................................................................................................................................34  
FIGURE 12 - 3 BYTE ADDRESSING MODE.................................................................................................................................34  
FIGURE 13 - PDI SPI TIMING EXAMPLE.................................................................................................................................36  
FIGURE 14 - MFC CTRL SPI INTERFACE SIGNALS.................................................................................................................37  
FIGURE 15 - 2-BYTE MFC REGISTER ACCESS...........................................................................................................................37  
FIGURE 16 - 3-BYTE MFC REGISTER ACCESS...........................................................................................................................38  
FIGURE 17 - MFC CONTROL SPI TIMING EXAMPLE................................................................................................................39  
FIGURE 18 - SHARED SPI BUS CONFIGURATION....................................................................................................................40  
FIGURE 19 - EEPROM INTERFACE SIGNALS...........................................................................................................................40  
FIGURE 20 - RECOMMENDED LAND PATTERN MEASUREMENTS.................................................................................................46  
TMC8460 PRELIMINARY, CONFIDENTIAL TARGET, NON-RELEASE VERSION Datasheet (V014 / 2015-Aug-31)  
FIGURE 21 - TOP LAYER (1)....................................................................................................................................................47  
FIGURE 22 - INNER LAYER (2).................................................................................................................................................47  
FIGURE 23 - INNER LAYER (3).................................................................................................................................................47  
FIGURE 24 - INNER LAYER (4).................................................................................................................................................47  
FIGURE 25 - INNER LAYER (5).................................................................................................................................................47  
FIGURE 26 - BOTTOM LAYER (6).............................................................................................................................................47  
FIGURE 27 - SOLDERING PROFILE...........................................................................................................................................48  
FIGURE 28 - ETHERCAT STATE MACHINE..............................................................................................................................108  
FIGURE 29 - TMC8460 RAM STRUCTURE............................................................................................................................110  
FIGURE 30 - MFCIO BLOCK INTERFACES TO ESC PDRAM.................................................................................................112  
FIGURE 31 BLOCK STRUCTURE OF THE INCREMENTAL ENCODER UNIT ...............................................................................116  
FIGURE 32 BLOCK STRUCTURE OF SPI MASTER UNIT ......................................................................................................120  
FIGURE 33: STEP DIRECTION UNIT BLOCK DIAGRAM.......................................................................................................124  
FIGURE 34: STEP-DIRECTION TIMING................................................................................................................................124  
FIGURE 35: PWM BLOCK DIAGRAM.................................................................................................................................128  
FIGURE 36: PWM TIMING (CENTERED PWM)............................................................................................................130  
FIGURE 37: PWM TIMING (LEFT ALIGNED PWM).......................................................................................................130  
FIGURE 38: PWM TIMING (RIGHT ALIGNED PWM)......................................................................................................131  
FIGURE 39: CHOPPER MODES (OFF, LOW SIDE ON, HIGH SIDE ON, LOW SIDE CHOPPR, GH SIDCHOPPER,  
COMPLEMENTARY LOW SIDE AND HIGH SIDE CHOPPER)...................................................................................133  
FIGURE 40: CENTERED PWM WITH PWM#2 SHIFTED FROM CENTER (EXAMPLE)...........................................134  
FIGURE 41: BRAKE BEFORE MAKE (BBM) TIMING (INDIVIDUAL PROGRAMMABLE FOR LOND HIGH SIDE)........135  
FIGURE 7.42 STRUCTURE OF THE WATCHDOG UNIT...............................................................................................139  
List of Tables  
TABLE 1 - MII INTERFACE SIGNAL DESCRIPTION AND CONECTI..................................................................................31  
TABLE 2 - PDI SPI INTERFACE SIGNAL DESCRIPTION ANCONNECON.............................................................................33  
TABLE 3 - PDI-SPI COMMANDS.....................................................................................................................................33  
TABLE 4 - MFC CTRL SPI INTERFACE SIGNAL DSRIPTION ND CONNECTION..................................................................37  
TABLE 5 - ABSOLUTE MAXIMUM RATINGS........................................................................................................................42  
TABLE 6 - RECOMMENDED OPERATIG CONDIONS...........................................................................................................42  
TABLE 7 - TMC8460 POWER CONSUMION.....................................................................................................................43  
TABLE 8 - POWER CONSUMPTION BY RAIL.........................................................................................................................43  
TABLE 9 - TMC8460 PACKAGE AL BEHIOR...............................................................................................................43  
TABLE 10 - SOLDERING PROMETERS......................................................................................................................48  
TABLE 11: TMC8460 ADDREE..................................................................................................................................49  
TABLE 12: REGISTER TE (0X00)......................................................................................................................................54  
TABLE 13: REGISTER VISION (0X0001).................................................................................................................................54  
TABLE 14: REGISTER BUD (0X0002:0X0003)........................................................................................................................54  
TABLE 15: RFMMUSUPPORTED (0X0004)................................................................................................................54  
TABLE 16NCMANAGERS SUPPORTED (0X0005)...................................................................................................54  
TABLE 17: M SIZE (0X0006)...............................................................................................................................54  
TABLE 18: RERT DESCRIPTOR (0X0007)...................................................................................................................55  
TABLE 19: REGISR ESC FEATURES SUPPORTED (0X0008:0X0009)........................................................................................55  
TABLE 20: REGISTER ONFIGURED STATION ADDRESS (0X0010:0X0011)...............................................................................56  
TABLE 21: REGISTER CONFIGURED STATION ALIAS (0X0012:0X0013)....................................................................................56  
TABLE 22: REGISTER WRITE REGISTER ENABLE (0X0020)........................................................................................................56  
TABLE 23: REGISTER WRITE REGISTER PROTECTION (0X0021).................................................................................................57  
TABLE 24: REGISTER ESC WRITE ENABLE (0X0030)................................................................................................................57  
TABLE 25: REGISTER ESC WRITE PROTECTION (0X0031)........................................................................................................57  
TABLE 26: REGISTER ESC RESET ECAT (0X0040)....................................................................................................................58  
TABLE 27: REGISTER ESC RESET PDI (0X0041)......................................................................................................................58  
TABLE 28: REGISTER ESC DL CONTROL (0X0100:0X0103).....................................................................................................58  
TABLE 29: REGISTER PHYSICAL READ/WRITE OFFSET (0X0108:0X0109)................................................................................60  
TABLE 30: REGISTER ESC DL STATUS (0X0110:0X0111)........................................................................................................60  
TABLE 31: DECODING PORT STATE IN ESC DL STATUS REGISTER 0X0111 (TYPICAL MODES ONLY)..........................................62  
TMC8460 PRELIMINARY, CONFIDENTIAL TARGET, NON-RELEASE VERSION Datasheet (V014 / 2015-Aug-31)  
TABLE 32: REGISTER AL CONTROL (0X0120:0X0121)..............................................................................................................63  
TABLE 33: REGISTER AL STATUS (0X0130:0X0131)................................................................................................................63  
TABLE 34: REGISTER AL STATUS CODE (0X0134:0X0135)......................................................................................................64  
TABLE 35: REGISTER RUN LED OVERRIDE (0X0138)...............................................................................................................64  
TABLE 36: REGISTER ERR LED OVERRIDE (0X0139)................................................................................................................64  
TABLE 37: REGISTER PDI CONTROL (0X0140).........................................................................................................................65  
TABLE 38: REGISTER ESC CONFIGURATION (0X0141)..............................................................................................................65  
TABLE 39: REGISTER PDI INFORMATION (0X014E:0X014F)....................................................................................................66  
TABLE 40: REGISTER PDI SPI SLAVE CONFIGURATION (0X0150)............................................................................................66  
TABLE 41: REGISTER PDI SPI SLAVE EXTENDED CONFIGURATION (0X0152:0X0153)..............................................................67  
TABLE 42: REGISTER SYNC/LATCH[1:0] PDI CONFIGURATION (0X0151).................................................................................67  
TABLE 43: REGISTER ECAT EVENT MASK (0X0200:0X0201)...................................................................................................68  
TABLE 44: REGISTER PDI AL EVENT MASK (0X0204:0X0207).............................................................................................68  
TABLE 45: REGISTER ECAT EVENT REQUEST (0X0210:0X0211)............................................................................................69  
TABLE 46: REGISTER AL EVENT REQUEST (0X0220:0X0223)...............................................................................................69  
TABLE 47: REGISTER RX ERROR COUNTER PORT Y (0X0300+Y*2:0X0301+Y*2)..............................................................71  
TABLE 48: REGISTER FORWARDED RX ERROR COUNTER PORT Y (0X0308+Y)...................................................................71  
TABLE 49: REGISTER ECAT PROCESSING UNIT ERROR COUNTER (0X030C).......................................................................71  
TABLE 50: REGISTER PDI ERROR COUNTER (0X030D)....................................................................................................71  
TABLE 51: REGISTER SPI PDI ERROR CODE (0X030E)..................................................................................................71  
TABLE 52: REGISTER LOST LINK COUNTER PORT Y (0X0310+Y)............................................................................72  
TABLE 53: REGISTER WATCHDOG DIVIDER (0X0400:0X0401)..................................................................................72  
TABLE 54: REGISTER WATCHDOG TIME PDI (0X0410:0X0411)...............................................................................72  
TABLE 55: REGISTER WATCHDOG TIME PROCESS DATA (0X0420:0X0421)........................................................................72  
TABLE 56: REGISTER WATCHDOG STATUS PROCESS DATA (0X0440:0X0441........................................................................73  
TABLE 57: REGISTER WATCHDOG COUNTER PROCESS DATA (0X0442)...............................................................................73  
TABLE 58: REGISTER WATCHDOG COUNTER PDI (0X0443).................................................................................................73  
TABLE 59: SII EEPROM INTERFACE REGISTER OVERVIEW ...............................................................................................73  
TABLE 60: REGISTER EEPROM CONFIGURATION (0X0500)................................................................................................74  
TABLE 61: REGISTER EEPROM PDI ACCESS STATE (X050.................................................................................................74  
TABLE 62: REGISTER EEPROM CONTROLSTATUS 00502:0X003)......................................................................................75  
TABLE 63: REGISTER EEPROM ADDRESS (0X0504:0507)...................................................................................................76  
TABLE 64: REGISTER EEPROM DATA 0X0508X050F X0508:0X050B])..........................................................................76  
TABLE 65: REGISTER EEPROM DATA FOEEPROEMULATION RELOAD (0X0508:0X050F).................................................77  
TABLE 66: MII MANAGEMENT INTERFACE RISTER ORVIEW...............................................................................................77  
TABLE 67: REGISTER MII MANACONTRL/STATUS (0X0510:0X0511)........................................................................79  
TABLE 68: REGISTER PHY AD0512).........................................................................................................................80  
TABLE 69: REGISTER PHY READDRS (0X0513).........................................................................................................80  
TABLE 70: REGISTER PY DAT0X0514X0515)................................................................................................................80  
TABLE 71: REGISTER I MANAGEMENT ECAT ACCESS STATE (0X0516)................................................................................80  
TABLE 72: REGISTER MIMANAGEMENT PDI ACCESS STATE (0X0517)..................................................................................81  
TABLE 73: PHY PT Y (PORT NUMBER Y=0 TO 3) STATUS (0X0518+Y)..................................................................81  
TABLE 74TER CONFIGURATION (0X0580+Y)......................................................................................................82  
TABLE 75: TER OVERVIEW....................................................................................................................................83  
TABLE 76: REOGICAL START ADDRESS FMMU Y (0X06Y0:0X06Y3)...........................................................................83  
TABLE 77: REGISR LENGTH FMMU Y (0X06Y4:0X06Y5).......................................................................................................83  
TABLE 78: REGISTER TART BIT FMMU Y IN LOGICAL ADDRESS SPACE (0X06Y6)....................................................................83  
TABLE 79: REGISTER STOP BIT FMMU Y IN LOGICAL ADDRESS SPACE (0X06Y7).....................................................................83  
TABLE 80: REGISTER PHYSICAL START ADDRESS FMMU Y (0X06Y8-0X06Y9).........................................................................84  
TABLE 81: REGISTER PHYSICAL START BIT FMMU Y (0X06YA)................................................................................................84  
TABLE 82: REGISTER TYPE FMMU Y (0X06YB)........................................................................................................................84  
TABLE 83: REGISTER ACTIVATE FMMU Y (0X06YC).................................................................................................................84  
TABLE 84: REGISTER RESERVED FMMU Y (0X06YD:0X06YF)...................................................................................................84  
TABLE 85: SYNCMANAGER REGISTER OVERVIEW.......................................................................................................................85  
TABLE 86: REGISTER PHYSICAL START ADDRESS SYNCMANAGER Y (0X0800+Y*8:0X0801+Y*8).............................................85  
TABLE 87: REGISTER LENGTH SYNCMANAGER Y (0X0802+Y*8:0X0803+Y*8)..........................................................................85  
TABLE 88: REGISTER CONTROL REGISTER SYNCMANAGER Y (0X0804+Y*8)..............................................................................86  
TABLE 89: REGISTER STATUS REGISTER SYNCMANAGER Y (0X0805+Y*8)................................................................................87  
TMC8460 PRELIMINARY, CONFIDENTIAL TARGET, NON-RELEASE VERSION Datasheet (V014 / 2015-Aug-31)  
TABLE 90: REGISTER ACTIVATE SYNCMANAGER Y (0X0806+Y*8).............................................................................................88  
TABLE 91: REGISTER PDI CONTROL SYNCMANAGER Y (0X0807+Y*8).....................................................................................89  
TABLE 92: REGISTER RECEIVE TIME PORT 0 (0X0900:0X0903)...............................................................................................89  
TABLE 93: REGISTER RECEIVE TIME PORT 1 (0X0904:0X0907)...............................................................................................89  
TABLE 94: REGISTER RECEIVE TIME ECAT PROCESSING UNIT (0X0918:0X091F)....................................................................89  
TABLE 95: REGISTER SYSTEM TIME (0X0910:0X0913 [0X0910:0X0917])..............................................................................91  
TABLE 96: REGISTER SYSTEM TIME OFFSET (0X0920:0X0923 [0X0920:0X0927])..................................................................91  
TABLE 97: REGISTER SYSTEM TIME DELAY (0X0928:0X092B).................................................................................................92  
TABLE 98: REGISTER SYSTEM TIME DIFFERENCE (0X092C:0X092F).........................................................................................92  
TABLE 99: REGISTER SPEED COUNTER START (0X0930:0X931)................................................................................................92  
TABLE 100: REGISTER SPEED COUNTER DIFF (0X0932:0X933)................................................................................................92  
TABLE 101: REGISTER SYSTEM TIME DIFFERENCE FILTER DEPTH (0X0934)..............................................................................93  
TABLE 102: REGISTER SPEED COUNTER FILTER DEPTH (0X0935)..........................................................................................93  
TABLE 103: REGISTER RECEIVE TIME LATCH MODE (0X0936)...............................................................................................94  
TABLE 104: REGISTER CYCLIC UNIT CONTROL (0X0980)......................................................................................................95  
TABLE 105: REGISTER ACTIVATION REGISTER (0X0981)...................................................................................................96  
TABLE 106: REGISTER PULSE LENGTH OF SYNCSIGNALS (0X0982:0X983).......................................................................96  
TABLE 107: REGISTER ACTIVATION STATUS (0X0984).......................................................................................................96  
TABLE 108: REGISTER SYNC0 STATUS (0X098E)...........................................................................................................97  
TABLE 109: REGISTER SYNC1 STATUS (0X098F)..........................................................................................................97  
TABLE 110: REGISTER START TIME CYCLIC OPERATION (0X0990:0X0993 [0X0990:0X097])...............................97  
TABLE 111: REGISTER NEXT SYNC1 PULSE (0X0998:0X099B [0X0998:0X099F])..................................................98  
TABLE 112: REGISTER SYNC0 CYCLE TIME (0X09A0:0X09A3)................................................................................98  
TABLE 113: REGISTER SYNC1 CYCLE TIME (0X09A4:0X09A7)..........................................................................................98  
TABLE 114: REGISTER LATCH0 CONTROL (0X09A8)............................................................................................................99  
TABLE 115: REGISTER LATCH1 CONTROL (0X09A9)...........................................................................................................99  
TABLE 116: REGISTER LATCH0 STATUS (0X09AE).............................................................................................................100  
TABLE 117: REGISTER LATCH1 STATUS (0X09AF)..........................................................................................................100  
TABLE 118: REGISTER LATCH0 TIME POSITIVE EDGE (0X090:0X09B[0X09B0:0X09B7])................................................101  
TABLE 119: REGISTER LATCH0 TIME NEGATIVE EDGE 0X098:0X09BB [0X09B8:0X09BF])..............................................101  
TABLE 120: REGISTER LATCH1 TIME POSTIVE ED0X09C0:009C3 [0X09C0:0X09C7])................................................102  
TABLE 121: REGISTER LATCH1 TIME NEGATIVE EDGE X09C8:0X09CB [0X09C8:0X09CF])...............................................102  
TABLE 122: REGISTER ETHERCAT BUER CHAE EVENTIME (0X09F0:0X09F3)..............................................................103  
TABLE 123: REGISTER PDI BUFFER STAEVENT ME (0X09F8:0X09FB)...........................................................................103  
TABLE 124: REGISTER PDI BUFFER CHANGEVENT TE (0X09FC:0X09FF)........................................................................103  
TABLE 125: REGISTER PRODUCT 0E00:00E07)..........................................................................................................104  
TABLE 126: REGISTER VENDOE08:0X0E0F)...........................................................................................................104  
TABLE 127: USER RAM (0X00FFF).........................................................................................................................104  
TABLE 128: PROCESS ATA RA(0X100:0X4FFF) ............................................................................................................105  
TABLE 129: MFCIO CK ECAT WRITE DATA MEMORY BLOCK (0X4000:0X405F)............................................................105  
TABLE 130: PADDING BYS...................................................................................................................................................106  
TABLE 131BLOCK CAT READ DATA MEMORY BLOCK (0X4800:0X4823)..............................................................106  
TABLE 13YTES...................................................................................................................................................107  
TABLE 13ES AND TRANSITIONS......................................................................................................................109  
TABLE 134 : BLOCK REGISTER OVERVIEW..............................................................................................................113  
TABLE 135 : EEPOM PARAMETER MAP & ESC RAM ADDRESS MAPPING FOR TMC8460-BI.......................................114  
TABLE 136 - MFCIREGISTER CONFIGURATION BYTE........................................................................................................115  
TABLE 137 - MFCIO REGISTER SHADOW TRIGGER SOURCE CONFIGURATION....................................................................115  
TABLE 138: AL_STATE_OVERRIDE REGISTER...................................................................................................................142  
TABLE 139: DOCUMENTATION REVISIONS............................................................................................................................145  
TMC8460 PRELIMINARY, CONFIDENTIAL TARGET, NON-RELEASE VERSION Datasheet (V014 / 2015-Aug-31)  
1 Abbreviations  
AL  
BOOT  
CS  
Special boot state of the EtherCAT state machine  
Chip Select (SPI bus signal)  
ECAT  
EEPROM  
EtherCAT (or sometimes used for EtherCAT Master Interface)  
Electrically Erasable Programmable Read Only Memory. Non-volatile memory used to  
store EtherCAT Slave Information (ESI). Connected to the SII  
EtherCAT Network Information file, holds information on the complete EtherCAT bus  
structure and its connected slaves  
ENI  
EoF  
ESC  
ESI  
End of Frame  
EtherCAT Slave Controller  
EtherCAT Slave Information, stored in SII EEPROM, holds slave specific configation  
information  
ETG  
EtherCAT  
FCS  
EtherCAT Technology Group, www.ethercat.org  
Ethernet in Control and Automation Technology  
Frame Check Sequence  
FMMU  
GPI  
Fieldbus Memory Management Unit  
General Purpose Input(s)  
GPO  
I2C  
INIT  
IRQ  
General Purpose Output(s)  
Inter-Integrated Circuit, serial bus used for SII EM conn  
Initial state of the EtherCAT state machine  
Interrupt Request  
MAC  
MCU  
MFCIO  
MI  
Media Access Control layer  
Microcontroller Unit  
Multi Function and Control Input utt  
(PHY) Management Interface  
MII  
OP  
PDI  
Media Independent Interfac: Stdardized nterface between the Ethernet MAC and PHY  
Operational state of the EterCAT stte machine  
Process Data Interface or Psical Devce Interface: an interface that allows  
access to ESC om thprocesside  
PDO  
PHY  
Process Data Objct  
Physical layer devicthat coverts data from the Ethernet controller to electric  
or optical s  
PREOP  
PWM  
RAM  
RX  
Pre-opertate of the EtherCAT state machine  
Pulse WModulion  
Radom Aess Memory. ESC have User RAM and Process Data RAM  
Reive path  
SAFEOP  
SII  
SM  
Safe perational state of the EtherCAT state machine  
erCASlave Information Interface  
Manager  
SoF  
SPI  
of Frame  
Serial Peripheral Interface  
TX  
ransmit path  
µC  
XML  
Extensible Markup Language: Standardized definition language that can be interpreted by  
nearly all parsers.  
S/D  
Step and Direction interface  
Process Data RAM of the ESC  
Memory Block x  
PDRAM  
MBx  
IEC  
ESM  
EtherCAT State Machine  
TMC8460 PRELIMINARY, CONFIDENTIAL TARGET, NON-RELEASE VERSION Datasheet (V014 / 2015-Aug-31)  
2 Principles of Operation  
2.1 Key Concepts  
2.1.1  
EtherCAT Slave Controller (ESC)  
The TMC8460 is a standard-conform dedicated EtherCAT Slave Controller providing EtherCAT MAC layer  
functionality to EtherCAT slaves.  
It connects via standard of-the-shelf Ethernet PHYs to the physical medium and provides a digital control  
interface to a local application controller while also providing the option for standalone operation.  
PHY PHY  
MII  
I2C  
ESC /  
EEPROM  
Main Data Path  
PDI  
PHY  
MAJOR ETHERCAT FEATURES  
Ethernet PHY interface: 2 x MII  
6 FMMUs & 6 Sync Managers  
16 Kbyte Process Data RAM  
64 bit Distributed Clocks  
I²C interface for external EEPROM  
SPI Process Data Interface (PDI) wh up to 3Mbit/s  
Optional Device Emution mde  
2.1.2  
Trinamic Multi-Funcon and ontrol IO Block  
Besides the proven Ethfunconality and the main EtherCAT data path, TMC8460 comes with a  
dedicated hardwablocprovidig a configurable set of complex real-time IO functions to smart  
embedded syste. This IO unctionality is called Multi-Function Control and IO block MFCIO. Its  
special focus is on otor and motion control applications and systems while it is not limited to this  
applicatio
The MFCombines various functional sub-blocks that are helpful in an embedded design to  
reduce cmplify the bill of materials (BOM), and to provide hardware acceleration to compute  
intensive time critical tasks. These functions can be used from the local application controller  
using a dedicd SPI interface or can directly be mapped into the Process Data RAM for direct access  
by the EtherCAT master.  
MII  
I2C  
ESC /  
ain Data Path  
MFCIO Block  
MFC CTRL  
PDI  
 
TMC8460 PRELIMINARY, CONFIDENTIAL TARGET, NON-RELEASE VERSION Datasheet (V014 / 2015-Aug-31)  
GENERAL PURPOSE IOS  
There are up to 8 outputs or up to 8 inputs  
Each IO is individually configurable  
INCREMENTAL ENCODER UNIT  
Incremental encoder inputs (ABN) with configurable counting constant, polarity, N-signal behavior  
and latch on N-signal  
32 bit count register  
STEP & DIRECTION UNIT  
Simple internal step rate generator  
Configurable step pulse width and polarity  
Continuous mode or one-shot mode with configurable step number  
Counter for steps that have been done  
3-CH PWM  
configurable frequency, duty cycle, polarity, dead times, polarity per ch
SPI MASTER INTERFACE  
To directly connect to a TMC driver/controller or othr SPI sves  
Up to 4 slaves  
Configurable speed, mode, datagram width uto 4 bits onger datagrams are possible)  
IRQ / EVENT OUTPUT  
Common IRQ signal to indicate variouevents trigered by the MFCIO block  
Mask register to enable/dable cetain evnt triggers  
WATCHDOG  
Configurable for all nd outpts  
Outputs will be asswith onfigurable level @ watchdog event  
Inputs will triger a tchdog event only  
ECAT SoF anDI SPI Chip Select can be monitored with watchdog as well  
EMERGENCNPUT  
If usonal outputs are set to a configurable safe state when the switch is not actively  
driven
Low activmust be pulled high for normal operation if used.  
2.2 Configuration Options  
The TMC8460 must be configured after power-up for proper operation. The EtherCAT part is automatically  
configured using configuration data from the connected I2C EEPROM.  
The MFCIO block can also be configured using EEPROM configuration data. The EEPROM must therefore  
contain additional configuration data with category ‘1’, which is automatically copied to ESC  
configuration RAM at addresses 0x0580:0x05FF.  
Another way to configure the MFCIO block is to directly write the configuration bits to this RAM area  
using the ECAT or the PDI interface.  
TMC8460 PRELIMINARY, CONFIDENTIAL TARGET, NON-RELEASE VERSION Datasheet (V014 / 2015-Aug-31)  
The MFCIO block can be used directly by a local application controller independent of the EtherCAT data  
path. Therefore, no upfront configuration is required since the MFCIO blocks comes with a dedicated  
SPI interface allowing complete access to its functions and local register set.  
2.3 Control Interfaces  
2.3.1  
Ethernet Interface  
For connection to the Ethernet physical medium and to the EtherCAT master, the TMC8460-BI offers two  
MII ports (media independent interface) and connects to standard 100Mbit/s Ethernet PHYs or 1Gbit/s  
Ethernet PHYs running in 100Mbit/s mode.  
2.3.2  
Process Data Interface  
The Process Data Interface (PDI) is an SPI interface. The TMC8460-BI provides an SPI slave intrface with  
ca. 30Mbit/s to connect to a local MCU or application controller. Typically, the local application ontroller  
contains the EtherCAT slave stack to control the EtherCAT state machine and to procss state change  
requests by the EtherCAT master. Pulling the external configuration pin PDI_EMUTION higsitches  
to Device Emulation mode. In Device Emulation mode, the TMC8460-BI can be usin standalone mode  
without MCU since state change requests by the master are directly forwarded tthe state regters  
inside the TMC8460’s ESC part. The PDI SPI interface remains active ancabe usd by an MCU in  
device emulation state.  
2.3.3  
Multi-Function and Control IO Block Interface  
The MFCIO block of the TMC8460-BI comes with a dedicated PI slae intee to allow direct access  
from a local application controller. It is called MFC CTRL SPI inerface. Thinterface to the MFCIO block’s  
functions is always available even if the EtherCAT state machne is currently not in operational state  
(OP). Protocol structure and timing are identical to the PDSPI.  
2.3.4  
SPI Bus Sharing  
Both SPI interfaces PDI SPI and MFC CTRL SPcan shre the same SPI bus signals using two chip  
select signals. This reduces overall numbeof sials on the PCB and requires only one SPI interface  
on the local MCU. The external onfiguron pin SARED_SPI_BUS needs to be pulled high for bus  
sharing. In this case, the PDI SPI bus is useas shared bus interface together with the chip select line  
of the MFC CTRL SPI interface.  
2.3.5  
Configuration Inputs  
External package pins alloelectin of configuration options that typically do not change during  
operation by directly cothem to 3V3 or ground. These package pins can also be controlled by  
GPIOs of the local applin contller.  
These options arfor emple external EEPROM’s size, PHY addressing and MII TX clock shift  
configuration, polties of the PHYs’ link indicator, device emulation mode and enabling of the 16MHz  
clock output.  
2.3.6  
erface  
An EEPROng boot-up configuration data is required for ESC operation. The EEPROM must come  
with a stanC interface and connects to the PROM interface of the TMC8460. EEPROMs of different  
size can be usd. There is a difference in the I2C protocol when EEPROM parts with >16kbits memory  
size are used.  
2.4 Software View  
As seen from an EtherCAT master system, the TMC8460-BI is part of an EtherCAT slave using the register  
set and functionality according to the EtherCAT standard. It works together with other EtherCAT slaves  
on the same bus and is accessible via the Ethernet physical medium. According to the slave configuration  
(ESI) and network configuration (ENI)  
As seen from the local application controller, the TMC8460-BI is a peripheral SPI slave device with a  
number of control and status registers that are accessible using the PDI SPI interface for the main  
EtherCAT data path or the MFC CTRL SPI interface for the MFCIO block.  
 
TMC8460 PRELIMINARY, CONFIDENTIAL TARGET, NON-RELEASE VERSION Datasheet (V014 / 2015-Aug-31)  
For proper EtherCAT functionality, the local application controller runs the EtherCAT slave stack to  
process master requests regarding state changes in the state machine for example using the PDI SPI  
interface. In device emulation mode the PDI SPI interface is not used since master requests are handled  
inside the ESC.  
The MFCIO block functions can directly be used with the MFC CTRL SPI interface. This can be done even  
without using the EtherCAT slave controller part.  
Trinamic’s TMCL IDE (http://www.trinamic.com/software-tools/tmcl-ide) can be used to access the device  
with the TMC8460-BI evaluation board. All registers are accessible via the two SPI interfaces. The  
configuration memory area for the MFCIO block can be read and modified.  
Figure 1: TMCL-IDE with regiser access to the TMC8460-BI on its evaluation board  
A wizard helps ansimplifies the configuration and setup of the TMC8460-BI to your specific needs and  
provides code exames for your configuration to be used inside you microcontroller firmware and the  
EEPROM fp conguration.  
TMC8460 PRELIMINARY, CONFIDENTIAL TARGET, NON-RELEASE VERSION Datasheet (V014 / 2015-Aug-31)  
Figure 2 - Wizrd Start Screen  
TMC8460 PRELIMINARY, CONFIDENTIAL TARGET, NON-RELEASE VERSION Datasheet (V014 / 2015-Aug-31)  
Figure 3 - Wizard Dice Selection and Feature Selection  
TMC8460 PRELIMINARY, CONFIDENTIAL TARGET, NON-RELEASE VERSION Datasheet (V014 / 2015-Aug-31)  
Figure 4 - Wizard Regster Section and Configuration View  
TMC8460 PRELIMINARY, CONFIDENTIAL TARGET, NON-RELEASE VERSION Datasheet (V014 / 2015-Aug-31)  
Figure 5 - Wizard output view with EEROM cfiguration string and firmware C-code snippets  
TMC8460 PRELIMINARY, CONFIDENTIAL TARGET, NON-RELEASE VERSION Datasheet (V014 / 2015-Aug-31)  
3 Device Usage and Handling  
3.1 Sample Block Diagrams  
The TMC8460 allows for flexible system architectures using a microcontroller running the Slave Stack  
Code (SSC) or using Device Emulation mode without a microcontroller.  
The following examples show typical system architectures using the TMC8460.  
3.1.1  
Typical EtherCAT Slave architecture  
The first application diagram shows the TMC8460 in a typical straightforward architecture. The PHYs  
connect to the TMC8460 using MII interface. Both PHYs and the TMC8460 have the same 25MHz clock  
source (see Section 3.9.2). The I2C EEPROM is connected to the TMC8460 and contains boot-up  
configuration required by the ESC after reset or power-cycling. The EEPROM is optionally conected to  
the µC to allow EEPROM updates via the MCU’s firmware.  
The µC connects to the TMC8460 using an SPI bus interface to the PDI SPI. The loal appliation is  
connected to the µC and is controlled by the application layer inside the µC. The applicatin ierface  
depends on the application and is a generic placeholder in this diagram. In this ample the MFO IO  
block is not used.  
25MHz  
source  
I2C  
EEPROM  
I2C  
100  
Mbit  
ETH PHY  
RXTX  
RXTX  
MII  
µApplication  
Ctroller  
with SlaStack  
Code  
RJ45  
+
PDI SPI  
TMC8460-BI  
MFCIO Block  
Local application  
Transformer  
100  
Mbit  
ETH PHY  
MII  
Figure 6 - Application diagram uing onthe locaapplication controller to interface the application  
3.1.2 MFCIO block based Miocontrller Arhitecture  
The second application diagram sows a imilar architecture with µC but with extensive use of the  
MFCIO block features. The special funtions of the MFCIO block allow relocating functionality from the  
µC to the TMC8460. That compte intense and time-critical functions are moved from software  
to hardware. The applicyer the µC can focus on interfacing to the real-time bus and for high-  
level control tasks the plicatio.  
For example, an rementaencoder can directly be connected to the MFCIO block. The µC only reads  
back the actual posion via the dedicated SPI interface MFC CTRL SPI. Additionally, SPI slave chips are  
directly coed to e MFCIO and not the µC, for example Trinamic’s dedicated smart stepper motor  
drivers, ardware motion controllers, and simple S/D stepper motor drivers. The MFCIO block  
master the PWM functions, the S/D function, and the 16MHz clock output are used in this  
case. The n controller does not need to implement these firmware functions and interfaces  
but uses the ailable resources of the TMC8460 instead. Software development is simplified. Other  
application partnot covered by the MFCIO block still connect to the microcontroller.  
TMC8460 PRELIMINARY, CONFIDENTIAL TARGET, NON-RELEASE VERSION Datasheet (V014 / 2015-Aug-31)  
25MHz  
source  
I2C  
EEPROM  
I2C  
100  
Mbit  
ETH PHY  
RXTX  
RXTX  
MII  
µC / Application  
Controller  
with Slave Stack  
Code  
RJ45  
+
Transformer  
Other application  
parts  
PDI SPI  
SPI  
TMC8460-BI  
MFCIO Block  
100  
Mbit  
ETH PHY  
MII  
TMC  
TMC  
DIGI IO  
nES  
ABN  
SPI  
Motion  
Driver  
Contr.  
16MHz CLK  
Incr.  
Encoder  
Input  
TMC  
Driver  
16MHz CLK  
Figure 7 - Application diagram using the MFCIO block features to reduce softwoverhead and provide  
real-time hardware support to the MCU. Other application parts may stl be ed to the MCU.  
3.1.3  
Device Emulation Example  
The third application diagram shows a more compacarchiteure using evice emulation mode. No µC  
is required. State machine change requests by the EthrCAT mster are directly processed inside the  
ESC. The MFCIO block is the only application interface avilable this architecture and provides the  
features mentioned under Section 2.1.2. For exape, a siple stepper motor slave with hardware  
motion controller and encoder feedback can be et up thout using a µC in the system by only using  
the features provided by the TMC8460. Since hegisters ad functions of the MFCIO block can directly  
be mapped into the PDRAM the EtherCAT master cn control the slave.  
25MH
source  
EEPROM  
I2C  
RXTX  
MII  
PHY  
PHY  
RJ45  
+
Trformer  
PDI_EMULATION = 1'  
TMC8460-BI  
MII  
MFCIO Block  
ABN  
TMC  
Motion  
Contr.  
TMC  
Driver  
SPI  
Incr.  
Encoder  
Input  
16MHz CLK  
Figure 8 - Application diagram without MCU. The TMC8460 is used in device emulation mode. SPI  
slave chips and other application peripherals can be connected to the MFCIO block. The EtherCAT  
master can directly control all the application functions.  
TMC8460 PRELIMINARY, CONFIDENTIAL TARGET, NON-RELEASE VERSION Datasheet (V014 / 2015-Aug-31)  
3.2 Samples Circuits  
3.2.1  
IC supply  
Only a minimal amount of decoupling capacitors is shown here.  
If possible every supply pin (1.2V and 3.3V) should have a separate 100nF capacitor connectebetween  
it and GND as close to the pin as possible.  
Larger capacitor values can be used on the 3.3V and 1.2V supply rails for increased stility.  
3.2.2  
PDI interface  
This is the default configuration for the PDI SPI ierace; boPDI_EMULATION and  
PDI_SHARED_SPI_BUS are tied to GND.  
PDI__EMULATION = 0 means that the procesor nnected the PDI SPI pins has full control over the  
ESC registers, the memory and the EtherCAT state achine.  
PDI_SHARED_SPI_BUS = 0 means that the gnals of te PDI SPI and MFC CTRL SPI buses are  
completely separate.  
The processor can also use the xtra sigals for Start-/End-Of-Frame and the PDI Watchdog.  
3.2.3  
Miscellaneous signals  
CLK_25MHZ is the clock input, which should be the same signal as the clock for both PHYs. The traces  
from the oscillator to the TMC8460 and the PHYs should have approximately the same length to avoid  
timing problems.  
LATCH_IN0, LATCH_IN1, SYNC_OUT0, SYNC_OUT1, NRST_OUT, EN_16MHZ_OUT and CLK_16MHZ_OUT are  
optional signals that can be used depending on the specific use case.  
TMC8460 PRELIMINARY, CONFIDENTIAL TARGET, NON-RELEASE VERSION Datasheet (V014 / 2015-Aug-31)  
Configuration Pins with their setting in this example:  
LINK_POLARITY  
PHY_OFFSET  
PROM_SIZE  
1 (+3.3V) MII_LINK signal from PHYs is high active  
0 (GND) PHY address offset is 0  
1 (+3.3V) EEPROM is 32kbit or larger (4Mbit max.)  
RESET_OUT_POLARITY 0 (GND) The RESET_OUT signal is low active  
External resistors are required on the MDIO line and for four (4) of the reserved pads.  
3.2.4  
MII 1 (EtherCAT Input)  
These are the connections to the first PHY, represenng the put port the EtherCAT device.  
3.2.5  
MII 2 (EtherCAT Output)  
These are the connctions to the second PHY, representing the output port of the EtherCAT device.  
TMC8460 PRELIMINARY, CONFIDENTIAL TARGET, NON-RELEASE VERSION Datasheet (V014 / 2015-Aug-31)  
3.2.6  
MFC I/Os  
The I/Os of the MFC block are shown unconnected here as he tual ctions depend on the  
intended use.  
TMC8460 PRELIMINARY, CONFIDENTIAL TARGET, NON-RELEASE VERSION Datasheet (V014 / 2015-Aug-31)  
3.3 Pinout and Pin Description  
The following table contains the pin description and required pin connections of the TMC8460-BI for  
the Very Fine Ball Pitch Grid Array package VF400.  
Pins not listed in this table are not connected (n.c.) / leave open.  
PKG.  
Pin  
DI  
R
Pin Name / Function  
Functional Description / Comments  
U17  
J7  
NRST  
I
I
Low active system reset input  
25MHz Reference Clock Input, connect to clock ource  
with <25ppm or better, Typically same clock souce as  
used for the PHYs  
CLK_25MHz  
U12  
R12  
CLK_16MHz_OUT  
EN_16MHz_OUT  
O
I
16MHz auxiliary clock output, enableby EN_16MHOUT  
Enable signal for 16 MHz auxiliary clocoutput: 0 = ff,  
1 = on, 16 MHz available at CK_1MHz_OT  
TMC8460 auxiliary output / ctive l defined by  
RESET_OUT_POL, reset by ECAT register 0x0040),  
RESET_OUT has to triggnREShich clears  
RESET_OUT.  
P19  
RESET_OUT  
O
Configures active lvel of the RESET_OUT signal: 0 = low  
active, 1 = hih activ
Signal indicating hat EEPROM has been loaded, 0 = not  
ready, = EEROM laded  
Extel I2C EEOM clock signal, Use 1K pull up  
rsistor o 3.3V  
N16  
R15  
F1  
RESET_OUT_POL  
EEPROM_OK  
PROM_CLK  
I
O
O
Eernal I2EEPROM data signal, Use 1k pull up resistor  
to 33  
G1  
PROM_DATA  
I/O  
elects between two different EEPROM sizes since the  
communication protocol for EEPROM access changes if  
a size > 16k is used (an additional address byte is  
required then). 0 = up to 16K EEPROM, 1 = 32 kbit-4Mbit  
EEPROM  
G2  
PROM_SIZ
I
Distributed Clocks synchronization output 1, Typically  
connect to MCU  
Distributed Clocks synchronization output 1, typically  
connect to MCU  
G4  
H4  
SYC_OUT0  
NC_OT1  
O
O
Latch input 0 for distributed clocks, connect to GND if  
not used.  
Latch input 1 for distributed clocks, Connect to GND if  
not used.  
J17  
CH_IN0  
LTCH_IN1  
I
I
K17  
Error Status LED, connect to red LED (Cathode)  
0 = LED on, 1 = LED off  
F14  
LED_ERR  
O
Link In Port Activity, connect to green LED (Anode)  
0 = LED off, 1 = LED on  
Link Out Port Activity, connect to green LED (Anode)  
0 = LED off, 1 = LED on  
Run Status LED, connect to green LED (Cathode)  
0 = LED on, 1 = LED off  
H15  
G14  
F15  
LED_LINK_IN  
LED_LINK_OUT  
LED_RUN  
O
O
O
 
TMC8460 PRELIMINARY, CONFIDENTIAL TARGET, NON-RELEASE VERSION Datasheet (V014 / 2015-Aug-31)  
Selects between normal operation with state machine  
inside ESC or device emulation mode (no µC required).  
Has weak internal pull down.  
0 = default, no device emulation, µC required  
1 = device emulation  
E3  
F3  
G3  
PDI_EMULATION  
PDI_EOF  
I
O
I
Ethernet End-of-Frame if 1  
Selects between separate SPI busses (SDI, SDO, SCK) or  
one SPI bus with two CS lines for the PDI and MFCIO  
SPI interface: 0 = two separate SPI busses, 1 = one  
shared SPI bus using the PDI_SPI_x bus lines (not the  
PDI_MFC_SPI bus lines)  
PDI_SHARED_SPI_BU  
S
F4  
C1  
PDI_SOF  
O
I
Ethernet Start-of-Frame if 1  
PDI_SPI is the primary process data interface of he  
TMC8460 to the MCU. Connect to MCU SPI master  
interface  
PDI_SPI_CSN  
Interrupt signal for primary process da interface,  
Connect to MCU  
PDI_SPI is the primary proess dterface of the  
TMC8460 to the MCU. Connect SPI master  
interface  
C2  
E2  
PDI_SPI_IRQ  
O
O
PDI_SPI_MISO  
PDI_SPI is the primary procss data interface of the  
TMC8460 to the MC. Connect to MCU SPI master  
interface  
PDI_SPI ithe priary process data interface of the  
TMC840 to te MCUConnect to MCU SPI master  
interfe  
E1  
PDI_SPI_MOSI  
PDI_SPI_SCK  
I
I
D2  
E5  
PDI_WD_STATE  
PDI_WD_TRIGGER  
O
O
Watchdostate, 0: Expired, 1: Not expired  
Wtchdog trigger if 1  
H5  
SPI Cntrol Interface to MFCIO special function block,  
Cnnect to MCU master SPI interface, Weak internal pull  
down  
SPI Control Interface to MFCIO special function block,  
Connect to MCU SPI master interface  
SPI Control Interface to MFCIO special function block,  
Connect to MCU SPI master interface, Has weak internal  
pull down  
H6  
F7  
F6  
MFC_CTRL_SPI_CSN  
MFC_CTRL_SO  
MFC_CL_SPI_MOSI  
I
O
I
SPI Control Interface to MFCIO special function block,  
Connect to MCU master SPI interface, Weak internal pull  
up  
MFCIO block IRQ for configurable events, connect to  
MCU, high active  
G6  
F5  
L_SPI_SCK  
MFCIO_IRQ  
I
O
T15  
T14  
MFC_ABN_A  
MFC_ABN_B  
MFC_ABN_N  
MFC_GPIO[0]  
MFC_GPIO[1]  
MFC_GPIO[2]  
I
I
I
MFCIO block incremental encoder unit input  
MFCIO block incremental encoder unit input  
MFCIO block incremental encoder unit input  
U14  
J15  
K15  
L15  
I/O MFCIO block GPIO port, configurable  
I/O MFCIO block GPIO port, configurable  
I/O MFCIO block GPIO port, configurable  
M15  
N15  
MFC_GPIO[3]  
MFC_GPIO[4]  
I/O MFCIO block GPIO port, configurable  
I/O MFCIO block GPIO port, configurable  
TMC8460 PRELIMINARY, CONFIDENTIAL TARGET, NON-RELEASE VERSION Datasheet (V014 / 2015-Aug-31)  
K16  
MFC_GPIO[5]  
I/O MFCIO block GPIO port, configurable  
L16  
M16  
Y16  
MFC_GPIO[6]  
MFC_GPIO[7]  
I/O MFCIO block GPIO port, configurable  
I/O MFCIO block GPIO port, configurable  
MFC_PWM_HS_0  
MFC_PWM_HS_1  
MFC_PWM_HS_2  
MFC_PWM_LS_0  
MFC_PWM_LS_1  
MFC_PWM_LS_2  
O
O
O
O
O
O
MFCIO block PWM unit high side output  
MFCIO block PWM unit high side output  
MFCIO block PWM unit high side output  
MFCIO block PWM unit low side output  
MFCIO block PWM unit low side output  
MFCIO block PWM unit low side output  
Y15  
W13  
W15  
W14  
Y13  
low active (not) Emergency Stop/Switch/Halt (to bring  
PWM or other outputs into a safe state), he evet  
must be cleared actively, has weak iernal pull wn,  
must be driven high for normal opetion  
PWM Trigger Pulse for e.g. ADC synchrnization,  
MFC_PWM_PULSE_A is confiurabland hih for one  
clock cycle in each PWM cyle  
PWM Trigger Pulse for e.g. ADronization,  
MFC_PWM_PULSE_Acombines _PWM_PULSE_A and  
MFC_PWMPULSE_in one gnal  
PWM Trigger Pulse or e.g. ADC synchronization,  
MFC_PWM_PUL_B is onfigurable and high for one  
clock cycle n each PWM cycle  
PWM Trigger ulse for e.g. ADC synchronization,  
MC_PM_PULSE_C is high for one clock cycle in the  
cnter of ach PWM cycle  
V14  
MFC_nES  
I
U13  
U18  
U11  
W10  
Y10  
MFC_PWM_PULSE_A  
MFC_PWM_PULSE_AB  
MFC_PWM_PULSE_B  
MFC_PWM_PULSE_C  
MFC_PWM_PULSE_
O
O
O
O
O
PM Trigger Pulse for e.g. ADC synchronization,  
MFC_WM_PULSE_S is high for one clock cycle on each  
WM cycle start  
R13  
T13  
F16  
G17  
G16  
H17  
E16  
E17  
M17  
MFC_SD_DIR  
MFC_SD_
MFC_SPI_
MFCSPI_CS
MFC_PI_CS2  
C_SPICS3  
PI_MISO  
SPI_MOSI  
FC_SPI_SCK  
O
O
O
O
O
I
MFCIO block Step/Direction unit output  
MFCIO block Step/Direction unit output  
MFCIO block SPI master unit interface  
MFCIO block SPI master unit interface  
MFCIO block SPI master unit interface  
MFCIO block SPI master unit interface  
MFCIO block SPI master unit interface  
MFCIO block SPI master unit interface  
O
O
MFCIO block SPI master unit interface  
selects polarity of the PHYs link signal:  
0 = low active, 1 = high active  
H16  
LINK_POLARITY  
I
K18  
E20  
H19  
G19  
MII1_LINK  
MII1_RXCLK  
MII1_RXD[0]  
MII1_RXD[1]  
I
I
I
I
MII interface to PHY of link in port  
MII interface to PHY of link in port  
MII interface to PHY of link in port  
MII interface to PHY of link in port  
F20  
F19  
MII1_RXD[2]  
MII1_RXD[3]  
I
I
MII interface to PHY of link in port  
MII interface to PHY of link in port  
TMC8460 PRELIMINARY, CONFIDENTIAL TARGET, NON-RELEASE VERSION Datasheet (V014 / 2015-Aug-31)  
H20  
J19  
MII1_RXDV  
MII1_RXER  
I
I
MII interface to PHY of link in port  
MII interface to PHY of link in port  
Used for clock shift compensation on TX port, Weak  
internal pull down  
Used for clock shift compensation on TX port, Weak  
internal pull down  
J18  
MII1_TX_SHIFT[0]  
MII1_TX_SHIFT[1]  
I
I
G18  
D20  
C20  
C19  
B19  
A20  
A19  
T18  
P20  
U19  
T20  
T19  
MII1_TXCLK  
MII1_TXD[0]  
MII1_TXD[1]  
MII1_TXD[2]  
MII1_TXD[3]  
MII1_TXEN  
I
O
O
O
O
O
I
I
I
I
I
MII interface to PHY of link in port  
MII interface to PHY of link in port  
MII interface to PHY of link in port  
MII interface to PHY of link in port  
MII interface to PHY of link in port  
MII interface to PHY of link in port  
MII interface to PHY of link out port  
MII interface to PHY of link out port  
MII interface to PHY of link out ort  
MII interface to PHY of link out p
MII interface to PHY of link ou
MII2_LINK  
MII2_RXCLK  
MII2_RXD[0]  
MII2_RXD[1]  
MII2_RXD[2]  
R20  
V19  
V20  
MII2_RXD[3]  
MII2_RXDV  
MII2_RXER  
I
I
I
MII interface to PHY of link out port  
MII interface to PHY of link out port  
MII inerface tPHY of link out port  
Ued for clck shift compensation on TX port, weak  
intenal pull down  
R18  
MII2_TX_SHIFT[0]  
I
Used fr clock shift compensation on TX port, Weak  
inrnal pull down  
MII interface to PHY of link out port  
P18  
N20  
MII2_TX_SHIFT[1]  
MII2_TXCL
I
I
N19  
MII_TXD
O
MII interface to PHY of link out port  
M19  
L20  
L19  
J20  
MII2_XD[1]  
2_TXD[2]  
_TXD[3]  
II2_TXEN  
O
O
O
O
I
MII interface to PHY of link out port  
MII interface to PHY of link out port  
MII interface to PHY of link out port  
MII interface to PHY of link out port  
PHY Address Offset: 0 = Offset = 0, 1 = Offset = 1  
PHY management clock,  
P15  
PY_OFFSET  
E18  
MCLK  
O
connect all PHYs to this bus  
PHY management data,  
I/O connect all PHYs to this bus if required,  
F18  
MDIO  
Use 4K7 pull up resistor to 3.3V  
B2  
reserved  
reserved  
reserved  
reserved  
Connect with 240R to GND  
pin must be pulled high, connect with 10K to 3.3V  
D19  
W19  
W20  
I
Pull down with 1K to GND  
Pull down with 1K to GND  
TMC8460 PRELIMINARY, CONFIDENTIAL TARGET, NON-RELEASE VERSION Datasheet (V014 / 2015-Aug-31)  
U16  
H11  
H9  
reserved  
I
Connect to 3.3V  
+1V2 (VCORE)  
+1V2 (VCORE)  
+1V2 (VCORE)  
+1V2 (VCORE)  
+1V2 (VCORE)  
+1V2 (VCORE)  
+1V2 (VCORE)  
+1V2 (VCORE)  
+1V2 (VCORE)  
+1V2 (VCORE)  
+1V2 (VCORE)  
+1V2 (VCORE)  
+1V2 (VCORE)  
+1V2 (VCORE)  
+1V2 (VCORE)  
+1V2 (VCORE)  
+1V2 (VCORE)  
+1V2 (VCORE)  
+1V2 (VCORE)  
+1V2 (VCORE)  
+1V2 (VCORE)  
+1V2 (VCORE)  
+1V2 (VCORE)  
+1V2 (VCORE)  
+3V3 (VCCIO)  
+3V3 (VCC
+3V3 (VC
+3V(VCCI
+3V3 VCCIO)  
V3 (VLL)  
J10  
J12  
K11  
K13  
K9  
L10  
L12  
M11  
M13  
M9  
N10  
N12  
N6  
N8  
P11  
P7  
P9  
R10  
R7  
R8  
T8  
U5  
B20  
E19  
F2  
G15  
G5  
G7  
H14  
H18  
J14  
J8  
(VPLL)  
(VCCIO)  
+3V3 (VPP)  
+3V3 (VCCIO)  
+3V3 (VPP)  
L14  
L17  
M20  
N14  
P14  
P16  
P5  
+3V3 (VCCIO)  
+3V3 (VCCIO)  
+3V3 (VCCIO)  
+3V3 (VPP)  
+3V3 (VCCIO)  
+3V3 (VPP)  
TMC8460 PRELIMINARY, CONFIDENTIAL TARGET, NON-RELEASE VERSION Datasheet (V014 / 2015-Aug-31)  
P6  
R14  
R19  
T11  
T12  
U15  
V18  
W11  
W17  
Y14  
Y17  
A12  
A2  
+3V3 (PLL)  
+3V3 (VCCIO)  
+3V3 (VCCIO)  
+3V3 (VPP)  
+3V3 (VCCIO)  
+3V3 (VCCIO)  
+3V3 (VCCIO)  
+3V3 (VCCIO)  
+3V3 (VPP)  
+3V3 (VCCIO)  
+3V3 (VPP)  
GND  
GND  
B15  
B5  
GND  
GND  
C18  
C8  
GND  
GND  
D1  
GND  
D11  
E14  
E4  
GND  
GND  
GND  
F17  
G11  
G13  
G20  
G9  
GND  
GND  
GND (PLL)  
GND  
GND  
H10  
H12  
H13  
H3  
GND  
GND  
GND  
ND  
H7  
ND (PL)  
ND  
H8  
J11  
J13  
J16  
J9  
GND  
GND  
GND  
GND  
K10  
K12  
K14  
K19  
K8  
GND  
GND  
GND  
GND  
GND  
L11  
GND  
TMC8460 PRELIMINARY, CONFIDENTIAL TARGET, NON-RELEASE VERSION Datasheet (V014 / 2015-Aug-31)  
L13  
L2  
GND  
GND  
GND  
GND  
GND  
GND  
GND  
GND  
GND  
GND  
GND  
GND (PLL)  
GND  
GND  
GND  
GND  
GND  
GND  
GND  
GND  
GND  
GND  
GND  
GND  
GND  
GND  
GND  
GND  
GND  
ND  
GND  
ND  
GND  
GND  
GND  
GND  
GND  
GND  
GND  
GND  
GND  
GND  
L9  
M10  
M12  
M14  
M5  
M8  
N11  
N13  
N18  
N5  
N7  
N9  
P1  
P10  
P12  
P4  
P8  
R6  
R9  
T1  
T10  
T16  
T17  
T2  
T3  
T4  
T5  
T6  
T7  
T9  
U1  
U10  
U2  
U20  
U3  
U4  
U6  
U7  
U8  
U9  
TMC8460 PRELIMINARY, CONFIDENTIAL TARGET, NON-RELEASE VERSION Datasheet (V014 / 2015-Aug-31)  
V1  
V10  
V13  
V2  
GND  
GND  
GND  
GND  
GND  
GND  
GND  
GND  
GND  
GND  
GND  
GND  
GND  
GND  
GND  
GND  
GND  
GND  
GND  
GND  
GND  
GND  
GND  
V3  
V4  
V5  
V6  
V7  
V8  
V9  
W1  
W16  
W3  
W5  
W7  
W9  
Y1  
Y19  
Y3  
Y5  
Y7  
Y9  
TMC8460 PRELIMINARY, CONFIDENTIAL TARGET, NON-RELEASE VERSION Datasheet (V014 / 2015-Aug-31)  
3.4 Ethernet PHYs  
The TMC8460-BI requires Ethernet PHYs with MII interface.  
The MII interface of the TMC8460 is optimized for low additional delays by omitting a transmit FIFO.  
Therefore, additional requirements to Ethernet PHYs exist and not every Ethernet PHY is suited.  
Therefore, please see the Ethernet PHY Selection Guide provided by the ETG:  
http://download.beckhoff.com/download/Document/EtherCAT/Development_products/AN_PHY_Selection_  
GuideV2.3.pdf.  
The TMC8460-BI has been successfully tested in combination with the following Ethernet PHYs so far:  
IC+ IP101GA: http://www.icplus.com.tw/pp-IP101G.html  
Micrel KSZ8721BLI: http://www.micrel.com/_PDF/Ethernet/datasheets/ks8721bl-sl.pdf  
Micrel KSZ8081: http://www.micrel.com/_PDF/Ethernet/datasheets/KSZ8081MNX-RNB.pdf  
The clock source of the PHYs is the same as for the TMC8460-BI (25 MHz).  
3.4.1 Ethernet PHY MII interface and MI interface  
100-Mbit Ethernet PHYs with MII interface are required. In addition, they need to povide a link sgnal  
indicating stable 100Mbit bus connection.  
The following diagram shows the interface pins. The table in Section 3 conthe pin descriptions  
of the interface. TX_CLK is optional. It is used for automatic TX Shift compe
MIIx_LINK  
TMC8460  
MIIx_RXCL
MIIx_RD[3:0]  
MII_RXDV  
MIIx_RXER  
Mx_TXEN  
MIIx_TXCLK  
MIIx_TXD[3:0]  
MCLK  
MDIO  
MIIx_TX_SHIFT[1:0]  
PHY_OFFSET  
LINK_POLARITY  
Figure 9 - MII Interface Signals  
Table 1 - MII interface signal description and connection  
TMC8460 pin  
MIIx_LINK  
Usage/description  
Input signal provided by the PHY if a stable 100 PHY and configuration  
Mbit/s (Full Duplex) link is established. dependent, typically  
MIIx_LINK must be constantly driven with the one of the status LED  
Typical PHY pin name  
configured polarity during operation.  
pins  
MIIx_RXCLK  
MIIx_RXD[3:0]  
MIIx_RXDV  
Receive clock  
Receive data  
Receive data valid  
RX_CLK  
RXD3…RXD0  
RX_DV  
TMC8460 PRELIMINARY, CONFIDENTIAL TARGET, NON-RELEASE VERSION Datasheet (V014 / 2015-Aug-31)  
MIIx_RXER  
MIIx_TXEN  
MIIx_TXCLK  
MIIx_TXD[3:0]  
MCLK  
Receive error  
Transmit enable  
RX_ER  
TX_EN  
TX_CLK  
TXD3…TXD0  
MDC  
Transmit clock (optional for automatic TX shift)  
Transmit data  
Management Interface clock,  
MCLK is driven rail-to-rail, idle value is High.  
Management Interface data,  
MDIO must have a pull-up resistor (4.7 kΩ  
recommended)  
MDIO  
MDIO  
3.4.2  
PHY Configuration Pins  
Besides the standard MII and MI interface signals, the TMC8460 has three configuration pins elated to  
the PHYs.  
LINK_POLARITY: this pin allows configuring the polarity of the link signaof the PHY. PHs of  
different manufacturers may use different polarities at the PHY’s pins. In additio, some PHYs low  
for bootstrap configuration with pull-up and pull-down resistors. This bootrap inrmation is used  
by the PHY at power-up / reset and also influences the polariof triginal pin function.  
Therefore, the link polarity needs to be configurable.  
PHY_OFFSET: The TMC8460 addresses Ethernet PHYs usinlogicport umber plus PHY address  
offset. Typically, the Ethernet PHY addresses shuld cospond withe logical port number, so  
PHY addresses 0 to 1 are used. A PHY address offset of 1 n be applied (PHY_OFFSET = ‘1’) which  
moves the PHY addresses to a range of 1 to 2. The MC846expects logical port 0 to have PHY  
address 0 plus PHY address offset.  
MIIx_TX_SHIFT[1:0]: TMC8460 and EthernHYs sharthe same clock source. Thus, TX_CLK from  
the PHY has a fixed phase relation to he MII nterface TX part of TMC8460. Thus, TX_CLK must not  
be connected and the delay of a TX FO inside e IP Core is saved.  
In order to fulfill the setup/holrequirments of the PHY, the phase shift between TX_CLK and  
MIIx_TX_EN and MIIx_TXD[30] has be cotrolled.  
o Manual TX Shift compnsation with additional delays for MIIx_TXEN/MIIx_TXD[3:0] of 10, 20,  
or 30 ns. Such delaycan be added using the TX Shift feature and applying  
MIIx_TX_SHIFIIx_TX_SHIFT[1:0] determine the delay in multiples of 10 ns for each  
port. Set MIK to zero if manual TX Shift compensation is used.  
o Automaic Tift comensation if the TX Shift feature is selected: connect MIIx_TXCLK and  
the atomatiTX Shift compensation will determine correct shift settings. Set  
MIIx_T_SHIFT[1:0] to 0 in this case.  
3.5
The PDI SPI erface is the interface used to access the ESC registers and the process data RAM from  
an external micrcontroller. The SPI clock frequency can be up to 30 MHz.  
The interface is configurable via the EEPROM. The default configuration (SPI mode 3, low active chip  
select) is recommended. For further details, see the ESC SPI slave configuration registers in Section 5.28.  
The following diagram shows all signals related to the PDI SPI interface.  
TMC8460 PRELIMINARY, CONFIDENTIAL TARGET, NON-RELEASE VERSION Datasheet (V014 / 2015-Aug-31)  
PDI_SPI_SCK  
PDI_SPI_CSN  
PDI_SPI_MOSI  
PDI_SPI_MISO  
TMC8460  
PDI_IRQ  
PDI_SOF  
PDI_EOF  
PDI_EMULATION  
PDI_WD_STATE  
PDI_WD_TRIGGER  
Figure 10 - PDI SPI Interface Signals  
Table 2 - PDI SPI interface signal description and connection  
TMC8460 pin  
PDI_SPI_SCK  
PDI_SPI_CSN  
PDI_SPI_MOSI  
PDI_SPI_MISO  
PDI_IRQ  
Usage/description  
SPI master clock  
SPI chip select for the TMC8460 I  
Master out slave in dta  
Master in slave outa  
Configurable IRfrom DI  
Typical µC pin name  
SCK  
SSx  
MOSI  
MISO  
General purpose IO  
PDI_EMULATION  
0: default modfor compx slaves, state machine General purpose IO or  
changes rocessd in microcontroller firmware connected to either  
(SSC
ground or 3.3V.  
1: devie emulion mode for, e.g., simple slaves,  
state macine chnges directly handled in the ESC  
PDI_SOF  
es srt of an Ethernet/EtherCAT frame General purpose IO  
_RXDV = ‘1’)  
PDI_EOF  
PDI_WD_STATE  
ndicatestart of an Ethernet/EtherCAT frame  
Wachdog expired  
General purpose IO  
General purpose IO  
1: Watchdog not expired  
PDI_WD_TGER  
Watchdog triggered if ‘1’  
General purpose IO  
3.5.1  
Sol description  
Each SPI datam contains a 2- or 3-byte address/command part and a data part. For addresses below  
0x2000, the 2-be addressing mode can be used, the 3 byte addressing mode can be used for all  
addresses.  
Table 3 - PDI-SPI commands  
C2 C1 C0 Command  
0
0
0
0
1
0
0
1
1
0
0
1
0
1
0
NOP (no operation, no following data bytes)  
Reserved  
Read  
Read with wait state byte  
Write  
TMC8460 PRELIMINARY, CONFIDENTIAL TARGET, NON-RELEASE VERSION Datasheet (V014 / 2015-Aug-31)  
1
1
1
0
1
1
1
0
1
Reserved  
Address extension, signaling 3 byte mode  
Reserved  
Address  
Command  
A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0  
C2 C1 C0  
A12 A11 A10 A9 A8 A7 A6 A5  
A4 A3 A2 A1 A0 C2 C1 C0  
Byte 0  
Byte 1  
Figure 11 - 2 byte addressing mode  
Address  
Commad  
A15 A14 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0  
C2 C1 C0  
A12 A11 A10 A9 A8 A7 A6 A5  
A4 A3 A2 A1 A0  
15 A14 C2 C1 C0  
1
1
0
0
0
Add
exnsion  
cmmand  
Reserved  
Byte 0  
Byte 1  
Byte 2  
Figure 12 - 3 byte addressing mode  
Unless highest performance irequird, usinonly the 3-byte addressing mode and the read with wait  
state command is recommendesince reducthe need for special cases in the software.  
During the address/command bytes, he ESC replies with the contents of the event request registers  
(0x0220, 0x0221 and in 3 ressinmode 0x0222).  
COMMAND 0 NOP  
This command cbe used for checking the event request registers and resetting the PDI watchdog  
without a read or wte access.  
Example
Example ontrol event bit is set):  
COMMAND 2
0x00 0x00  
0x01 0x00  
With the read cmmand, an arbitrary amount of data can be read from the device. The first byte read  
is the data from the address given by the address/command bytes. With every read byte, the address  
is incremented. During the data transfer, the SPI master sends 0x00 except for the last byte where a  
0xFF is sent.  
When using this command, a pause of 240ns or more must be included between the address/command  
bytes and the data bytes for the ESC to fetch the requested data.  
Example datagram (Read from address 0x0120 and 0x0121):  
Example reply (Operational State requested):  
0x09 0x02 0x00 0xFF  
0x01 0x00 0x08 0x00  
COMMAND 3 READ WITH WAIT STATE BYTE  
 
TMC8460 PRELIMINARY, CONFIDENTIAL TARGET, NON-RELEASE VERSION Datasheet (V014 / 2015-Aug-31)  
This command is similar to the Read command with an added dummy byte between the  
address/command part and the data part of the datagram. This allows enough time to fetch the data  
in any case.  
Example datagram (Read starting at address 0x3400):  
Example reply (0xXX is undefined data):  
0xA0 0x06 0x2C 0xFF 0x00 0x00 0x00 0xFF  
0x00 0x00 0x00 0xXX 0x44 0x41 0x54 0x41  
COMMAND 4 WRITE  
The write command allows writing of an arbitrary number of bytes to writable ESC registers or the  
process data RAM. It requires no wait state byte or delay after the address/command bytes. After every  
transmitted byte, the address is incremented.  
Example datagram (Write starting at address 0x4200):  
Example reply (0xXX is undefined data):  
0x10 0x06 0x50 0x4C 0x48  
0x00 0x00 0x00 0xXX 0xX
Address 0x4200 now contains 0x4C, Address 0x4201 contains 0x48  
COMMAND 6 ADDRESS EXTENSION  
The address extension command is mainly used for the 3-byte addressing shown in Figure 12.  
For SPI masters that can only process datagrams with an even numer of , it might be necessary  
to pad the datagram. This can be achieved by duplicating the hird byte f the 3-byte address/command  
part and using the address extension command in all but the ast duplicae.  
For example, a SPI master that is only capable of transmiing a multiple of 4 bytes cannot use the  
example datagram for a write access above sincit cotains 5 bytes. With three added padding bytes,  
the master has to transmit two 4-byte groups.  
Example datagram (Write starting at addes 0x4200
Example reply (0xXX is undefined data):  
0x10 0x06 0x58 0x58 0x58 0x50 0x4C 0x48  
0x00 0x00 0x00 0xXX 0xXX 0xXX 0xXX 0xXX  
TMC8460 PRELIMINARY, CONFIDENTIAL TARGET, NON-RELEASE VERSION Datasheet (V014 / 2015-Aug-31)  
3.5.2  
Timing example  
This example shows a generic read access with wait state and 2 byte addressing. All configurable  
options are shown. The delays between the transferred bytes are just to show the byte boundaries and  
are not required.  
Figure 13 - PDI SPI timing example  
TMC8460 PRELIMINARY, CONFIDENTIAL TARGET, NON-RELEASE VERSION Datasheet (V014 / 2015-Aug-31)  
3.6 MFC CTRL SPI  
The MFC Control SPI is a SPI mode 3 slave with low active chip select. It allows an external  
microcontroller to access the MFC registers. The SPI clock frequency can be up to 30MHz.  
The following diagram shows all signals related to the MFC CTRL SPI interface.  
MFC_CTR_SPI_SCK  
MFC_CTRL_SPI_CSN  
MFC_CTRL_SPI_MOSI  
MFC_CTRL_SPI_MISO  
TMC8460  
MFCIO_IRQ  
PDI_SHARED_SPI_BUS  
Figure 14 - MFC CTRL SPI interface signal
Table 4 - MFC CTRL SPI interface signal description and connetion  
TMC8460 pin  
Usage/description  
Typical µC pin name  
MFC_CTRL_SPI_SCK  
MFC_CTRL_SPI_CSN  
MFC_CTRL_SPI_MOSI  
MFC_CTRL_SPI_MISO  
MFCIO_IRQ  
SPI master clock  
SPI chip select for the TC8460  
Master out slave in dta  
Master in slave outa  
Configurable IRfrom FCIO block  
0: separate SPI uses for DI and MFC CTRL  
SCK  
SSx  
MOSI  
MISO  
General purpose IO  
General purpose IO or  
PDI_SHARED_SPI_BUS  
1: shared/ommoSPI bus for PDI and MFC CTRL connected to either  
with 2 CSN gnals uing the PDI SPI bus. The SPI ground or 3.3V.  
bus  
snals  
MFC_CTRL_SPI_SCK,  
MFC_CTRLSPI_MISO, MFC_CTRL_SPI_MOSI can be  
en in is case  
The protocol of thMFC CTSPI is the same as the PDI SPI interface. The addresses for register access  
are calculated usithe register number (from 0 to 44) and the byte number in each register. To  
calculate thddress, he register number is shifted left by 4 bits and the byte number is added as the  
4 lowest
Access byte addressing mode is possible, and can be used when 2 byte mode is not  
implemene PDI SPI but since the highest bits of the address are always 0, accessing the MFC  
Control SPI v2 byte mode is sufficient.  
Register  
Byte  
Command  
R5 R4 R3 R2 R1 R0  
B3 B2 B1 B0  
C2 C1 C0  
R5 R4 R3 R2 R1  
R0 B3 B2 B1 B0 C2 C1 C0  
0
0
0
Byte 0  
Byte 1  
Figure 15 - 2-byte MFC register access  
TMC8460 PRELIMINARY, CONFIDENTIAL TARGET, NON-RELEASE VERSION Datasheet (V014 / 2015-Aug-31)  
Register  
Byte  
Command  
R5 R4 R3 R2 R1 R0  
B3 B2 B1 B0  
C2 C1 C0  
R5 R4 R3 R2 R1  
R0 B3 B2 B1 B0  
C2 C1 C0  
0
0
0
1
1
0
0
0
0
0
0
Address  
extension  
command  
Reserved  
Byte 0  
Byte 1  
Byte 2  
Figure 16 - 3-byte MFC register access  
TMC8460 PRELIMINARY, CONFIDENTIAL TARGET, NON-RELEASE VERSION Datasheet (V014 / 2015-Aug-31)  
3.6.1  
Timing example  
This example shows a generic MFC register read access with wait state. The delays between the  
transferred bytes are just to show the byte boundaries and are not required.  
Figure 17 - MFC Control SPI timing example  
3.6.2  
Sharing Bus Lines with PDI SPI  
To reduce overall number of signals on the PCB or if the local application controller has only one SPI  
interface, the MFC CTRL SPI bus can use the SPI bus signals of the PDI SPI. Therefore, both interfaces  
TMC8460 PRELIMINARY, CONFIDENTIAL TARGET, NON-RELEASE VERSION Datasheet (V014 / 2015-Aug-31)  
are internally switched on the PDI SPI interface. The original MFC CTRL SPI signals (MOSI, MISO, and  
SCK) remain unconnected in this case. Only the MFC_CTRL_SPI_CSN pin/signal must be used if the  
MFCIO block should be accessed.  
To share the SPI bus lines, configuration pin PDI_SHARED_SPI_BUS must be pulled high as  
shown in the figure below.  
3V3  
TMC8460  
PDI_SHARED_SPI_BUS  
SPI BUS  
MUX  
PDI SPI  
PDI SPI  
MISO, MOSI, SCK, CSN  
MISO, MOSI, SCK, CSN  
MFC CTRL SPI  
MFC_CTRL_SPI_CSN  
MISO, MOSI, SCK, CSN  
MFC CTSPI  
MISO, MOSI
Figure 18 - Shared SPI bus conguration  
3.7 EEPROM Interface  
The TMC8460 contains an I2C master interfae h PROM_K and PROM_DATA. Both PROM_CLK and  
PROM_DATA require an external pull-up (4.kΩ recmmended).  
Both 1 byte and 2 byte addressed EEPROMare suppted. The EEPROM size is configurable using the  
PROM_SIZE pin (0 = up to 16EEPRM, 1 = 2 kbit-4Mbit EEPROM).  
The output signal EEPROM_OK inicates at the EEPROM content has been successfully loaded.  
The EEPROM interface is intended tbe a pint-to-point interface between TMC8460 and I2C EEPROM.  
If other I2C masters are reqed to acess the EEPROM using the same I2C bus, the TMC8460 must be  
in reset state. A typical is to (reprogram the EEPROM on the board using the application  
controller.  
PROM_DATA  
PROM_CLK  
PROM_SIZE  
EEPROM_OK  
TMC8460  
Figure 19 - EEPROM Interface signals  
TMC8460 pin  
PROM_DATA  
PROM_CLK  
Usage/description  
I2C data, requires pull-up  
I2C clock, requires pull-up  
PROM_SIZE  
Configures EEPROM size  
EEPROM_OK  
Indicates that EEPROM has be successfully loaded,  
this may be useful for the local application  
controller  
TMC8460 PRELIMINARY, CONFIDENTIAL TARGET, NON-RELEASE VERSION Datasheet (V014 / 2015-Aug-31)  
3.8 Vendor ID, ESC Type, ESC Revision and Build History  
Trinamic owns a dedicated EtherCAT vendor ID and holds a specific ID for Trinamic EtherCAT slave  
controllers to distinguish from other ESC manufacturers.  
hexadecimal  
binary decimal  
286  
D0  
60  
61  
0010 1000 0110  
646  
208  
96  
Trinamic official vendor ID  
Trinamic official ESC type  
TMC8460 ESC revision at 0x0001  
TMC8461 ESC revision at 0x0001  
1101 0000  
0110 0000  
0110 0001  
97  
Revision Register  
at 0x0001  
0x60  
Build Register at  
0x0002:0x0003  
Stepping  
0x0002 TMC8460-BI V10  
0x0010 TMC8461-BI V1
0x61  
TMC8460 PRELIMINARY, CONFIDENTIAL TARGET, NON-RELEASE VERSION Datasheet (V014 / 2015-Aug-31)  
3.9 Electrical Characteristics  
3.9.1  
Operating Conditions  
Stresses beyond those listed in the following table may cause damage to the device. Exposure to  
absolute maximum rating conditions for extended periods may affect device reliability.  
Absolute maximum ratings are stress ratings only. Functional operation of the device at these or  
Table 5 - Absolute Maximum Ratings  
Symbol Parameter  
Min  
-0.3  
-0.3  
-0.3  
Typ  
Max  
1.32  
3.63  
3.63  
3.63  
Unit Notes  
VCORE  
VCCIO  
VPLL  
DC core supply voltage, must always be powered  
IO supply voltage, must always be powered.  
PLL supply voltage, must always be powered.  
-
-
-
-
V
V
V
V
VPP  
Power supply for charge pump, must always be -0.3  
powered.  
TSTG  
TJ  
Storage temperature  
Junction temperature  
-65  
-55  
-
-
50  
25  
°C  
°C  
Table 6 - Recommended Operating Conditions  
Symbol Parameter  
Min  
4  
3.15  
3.15  
T
3.3  
3.3  
3.3  
Max  
1.26  
3.45  
3.45  
3.45  
Unit Notes  
VCORE  
VCCIO  
VPLL  
DC core supply voltage, must always be powered  
IO supply voltage, must always be powered.  
PLL supply voltage, must always be powered.  
V
V
V
V
VPP  
Power supply for charge pump, must alwys be 3.15  
powered.  
TJ  
Operating Junction temperature  
-40  
25  
100  
°C  
3.9.2  
External CLK Source  
Both TMC8460-BI and the external Ethernet HYs mut share the same clock source. For proper operation  
a stable and accurate 25MHz clock source is equired. Te recommended initial accuracy must be at least  
25ppm or better.  
The TMC8460-BI has been used witthe foowing crystal oscillators so far:  
FOX Electronics FOX924CXO, 20MHz, 2.5ppm, 3.3V: http://www.foxonline.com/pdfs/fox924.pdf  
TXC 7M-25.000MAAJ-MHz, 30ppm: http://www.txccrystal.com/images/pdf/7m.pdf  
CTS 636L5C025M00000z, 25pm: http://www.ctscorp.com/components/Datasheets/008-0250-0.pdf  
3.9.3  
IO Charaeristics  
The following table ontains information on the IO characteristics.  
LVCMOS iely usd switching standard and is defined by JEDEC (JESD 8-5).  
The TMCports LVCMOS standard LVCMOS33, which is a general standard for 3V3 applications.  
Symbol eter  
Min  
-
9.9  
9.98  
Typ  
Max  
10  
14.5  
14.9  
-
0.4  
3.45  
0.8  
10  
Unit Notes  
CIN  
Inut capacitance  
pF  
kΩ  
kΩ  
V
V
V
V
µA  
µA  
RPU  
RPD  
Weapull-up at VOH  
Weak pull-down at VOL  
DC output logic high  
DC output logic low  
DC input logic high  
DC input logic low  
Input current high  
Input current low  
VOH  
VOL  
VIH  
VIL  
IIH  
IIL  
VCCIO-0.4  
-
2.0  
-0.3  
-
-
10  
TMC8460 PRELIMINARY, CONFIDENTIAL TARGET, NON-RELEASE VERSION Datasheet (V014 / 2015-Aug-31)  
3.9.4  
Power Consumption  
The values given here are typical values only. The real values depend on configuration, activity, and  
temperature.  
Table 7 - TMC8460 power consumption  
Symbol Parameter  
Min  
Typ  
237  
19  
Max  
Unit  
mW  
mW  
mW  
%
100  
8
Notes  
PS + PD  
PTOTAL  
PS  
Total power consumption  
Static power consumption  
-
-
-
-
-
-
PD  
Dynamic power consumption  
218  
92  
Table 8 - Power consumption by rail  
Symbol Parameter  
Power (mW) Voltage (V) Current (mA) Notes  
Rail VCORE DC core supply voltage, must  
always be powered  
177.921  
46.984  
9.000  
1.200  
3.300  
3.300  
2.500  
148.268  
14.28  
2.727  
Rail VCCIO IO supply voltage, must always  
be powered.  
Rail VPLL PLL supply voltage, must always  
be powered.  
Rail VPP  
Power supply for charge pump,  
must always be powered.  
2.500  
0  
3.9.5  
Package Thermal Behavior  
Dynamic and static power consumption cause the junctiotempeture of the TMC8460 to be higher  
than the ambient, case, or board temperature. Theqations elow show the relationships.  
ꢀ −ꢀ  
ꢀ  
ꢀ −ꢀ  
EQ 1: 푇ℎ푒푡푎퐽퐴  
=
EQ 2: 푇ℎ푡푎퐽퐵  
=
EQ 3: 푇ℎ푒푡푎퐽퐶  
=
ꢃ표ꢄꢅ푙  
ꢃ표ꢄꢅ푙  
ꢃ표ꢄꢅ푙  
Symbols used:  
TJ  
= Junction temperatue  
= Ambient temperature  
= Board temperature measred 1.0mm away from the package  
= Case tempera
TA  
TB  
TC  
ThetaJA = Junction-to-t themal resistance  
ThetaJB = Junctionto-bd thermal resistance  
ThetaJC = Junctin-to-casthermal resistance  
PTOTAL  
= Total pwer consumption  
Table 9 ackage thermal behavior  
Symbol r  
Typ  
Unit Notes  
18.36 °C/W @ Still air  
ThetaJA Junction-to-ambient thermal resistance 14.89 °C/W @ 1.0 m/s  
13.36 °C/W @ 2.5 m/s  
ThetaJB Junction-to-board thermal resistance  
ThetaJC Junction-to-case thermal resistance  
7.12 °C/W  
3.41 °C/W  
TMC8460 PRELIMINARY, CONFIDENTIAL TARGET, NON-RELEASE VERSION Datasheet (V014 / 2015-Aug-31)  
3.10 Marking and Order Codes  
Temperature  
Range  
VFG400 -40°C ... +100°C EtherCAT slave controller  
with enhanced features  
Size  
[mm2]  
17 x 17  
Type  
Code & Marking Package  
Description  
TMC8460-BI  
TMC8460-BI  
TMC8460-EVAL TMC8460-EVAL  
PCB  
PCB  
PCB  
Evaluation board for  
TMC8560-BI EtherCAT slave  
controller  
Baseboard for TMC8460-EVAL 85 x 55  
and further evaluation  
85 x 79  
Landungs-  
bruecke  
Landungs-  
bruecke  
boards.  
Eselsbruecke  
Eselsbruecke  
Connector board for plug-in 61 x 38  
evaluation board system  
3.11 Package Dimensions  
The TMC8460 comes in a Very Fine Ball Pitch Grid Array package with 400 pins (VFG0).  
Ball grid pitch is 0.8mm. Package outline is 17x17mm.  
All dimensions are given in mm.  
TMC8460 PRELIMINARY, CONFIDENTIAL TARGET, NON-RELEASE VERSION Datasheet (V014 / 2015-Aug-31)  
TMC8460 PRELIMINARY, CONFIDENTIAL TARGET, NON-RELEASE VERSION Datasheet (V014 / 2015-Aug-31)  
3.12 Layout Considerations  
The required board area for the TMC8460, EEPROM, PHYs, capacitors and LEDs is below 12.5cm2 on a six-  
layer board.  
For best soldering results, only the BGA pads should be exposed under the TMC8460, while vias, traces  
and ground/power planes should be covered by the soldermask. It is not necessary to use blind or  
buried vias. Use the following guideline for routing to regular vias from the BGA pads. Traces from pads  
on the outermost rows can also be routed directly on the top layer.  
Pad dia.  
0.3mm  
Pad to via  
distance  
56mm  
.
0
Trace width  
0.15mm  
Restring dia.  
0.5mm  
Pad distance  
0.8mm  
Figure 20 - Recommended land paern mesurements  
The routing of the tracetwo PHYs should be as short as possible since these signals are timing  
critical. Since the pads oMII sgnals are all on one side of the TMC8460, most of the signals can  
be routed only on he top ayer wthout the need for vias.  
It is sufficient to tat other traces like SPI or all MFC signals in groups (e.g. the PDI_SPI signals or the  
PWM outputs), wherthe variance in trace length is small for all signals of the same group.  
TMC8460 PRELIMINARY, CONFIDENTIAL TARGET, NON-RELEASE VERSION Datasheet (V014 / 2015-Aug-31)  
3.12.1 Example layout of the TMC8460-Eval  
Figure 21 - Top layer (1)  
Figure 23 - Inner layer
Figure 25 - Inner layer (5)  
Figure 22 - Inner layer (2)  
Figure 24 - Inner layer (4)  
Figure 26 - Bottom layer (6)  
TMC8460 PRELIMINARY, CONFIDENTIAL TARGET, NON-RELEASE VERSION Datasheet (V014 / 2015-Aug-31)  
3.13 Soldering Profile  
The provided reflow soldering profile in accordance to IPC/JEDEC standard J-STD-020 is for reference  
only. Trinamic advises to optimize to the respective board level parameters to get proper reflow  
outcome.  
Figure 27 - Soldering Profe  
Table 10 - Soldering Profile Parameters  
Profile Feature  
Preheat  
Temperature Min (Tsmin  
Sn-Pb Eutectic Assembly Pb-Free Assembly  
)
100°C  
150°C  
Temperature Max (Tsmax  
Time (min to max) (ts)  
Tsmax to Tp  
)
150°C  
60-120 seconds  
200°C  
60-120 seconds  
- Ramp-up Rate  
3°C/second max.  
3°C/second max.  
Time maintained above
- Temperature (TL)  
183°C  
217°C  
- Time (tL)  
Peak package body mperature (Tp)  
60-150 seconds  
235°C  
60-150 seconds  
260°C  
Time (tp) °C of lassification temperature (Tc)20 seconds  
30 seconds  
6°C / second max.  
8 minutes max.  
Ramp-dto Tsmax  
)
6°C / second max.  
Time 25emperature  
6 minutes max.  
TMC8460 PRELIMINARY, CONFIDENTIAL TARGET, NON-RELEASE VERSION Datasheet (V014 / 2015-Aug-31)  
4 EtherCAT Address Space Overview  
An EtherCAT Slave Controller (ESC) has an address space of 64Kbyte. The first block of 4Kbyte  
(0x0000:0x0FFF) is dedicated for ESC- and EtherCAT-relevant configuration and status registers. The PD-  
RAM starts at address 0x1000. The TMC8460-BI has a PD-RAM size of 16 Kbyte.  
The following table lists the standard ESC register set which is also available in the TMC8460-BI.  
Section 5 contains a detailed register description.  
Section 0 lists the specific enabled EtherCAT features of the TMC8460-BI.  
Table 11: TMC8460 address space  
Address1  
Description  
Length  
(Byte)  
ESC Information  
Type  
0x0000  
0x0001  
1
1
2
1
1
1
1
2
Revision  
0x0002:0x0003  
0x0004  
Build  
FMMUs supported  
SyncManagers supported  
RAM Size  
0x0005  
0x0006  
0x0007  
Port Descripto
ESC Features spported  
0x0008:0x0009  
Stn Addss  
0x0010:0x0011  
0x0012:0x0013  
2
2
onfigud Station Address  
onfigured tation Alias  
Write Protection  
0x0020  
0x0021  
0x0030  
0x0031  
1
1
1
Write Register Enable  
Write Register Protection  
ESC Write Enable  
ESC Write Protection  
Data Link Layer  
ESC Reset ECAT  
ESC Reset PDI  
0x40  
1
1
4
2
2
0x004
0x0103  
x0109  
0:0x0111  
ESC DL Control  
Physical Read/Write Offset  
ESC DL Status  
Application Layer  
AL Control  
0x0120:0x0121  
0x0130:0x0131  
0x0134:0x0135  
0x0138  
2
2
2
1
1
AL Status  
AL Status Code  
RUN LED Override  
ERR LED Override  
0x0139  
1
Address areas not listed here are reserved. They are not writable. Read data from reserved addresses  
has to be ignored. Reserved addresses must not be written.  
TMC8460 PRELIMINARY, CONFIDENTIAL TARGET, NON-RELEASE VERSION Datasheet (V014 / 2015-Aug-31)  
Address1  
Description  
Length  
(Byte)  
PDI / ESC Configuration  
PDI Control  
0x0140  
0x0141  
1
1
2
1
1
2
ESC Configuration  
0x014E:0x014F  
0x0150  
PDI Information  
PDI Configuration  
0x0151  
SYNC/LATCH[1:0] PDI Configuration  
Extended PDI Configuration  
0x0152:0x0153  
Interrupts  
0x0200:0x0201  
0x0204:0x0207  
0x0210:0x0211  
0x0220:0x0223  
2
4
2
4
ECAT Event Mask  
PDI AL Event Mask  
ECAT Event Request  
AL Event Request  
Error Counters  
0x0300:0x0307  
0x0308:0x030B  
0x030C  
4x2  
4x1  
1
Rx Error Counter[3:0]  
Forwarded Rx Error counte
ECAT Processig Unit rror Counter  
PDI Error Coter  
0x030D  
1
0x030E  
1
PDI ErroCode  
0x0310:0x0313  
4x1  
Lost Link Conter[3:]  
atchdog
0x0400:0x0401  
0x0410:0x0411  
0x0420:0x0421  
0x0440:0x0441  
0x0442  
2
2
2
2
1
Wchdog Divider  
Watchog Time PDI  
Watchdog Time Process Data  
Watchdog Status Process Data  
Watchdog Counter Process Data  
Watchdog Counter PDI  
0x0443  
SII EEPROM Interface  
EEPROM Configuration  
EEPROM PDI Access State  
EEPROM Control/Status  
EEPROM Address  
0500  
1
1
0x05
:0x053  
x0507  
:0x050F  
2
4
4/8  
EEPROM Data  
MII Management Interface  
MII Management Control/Status  
PHY Address  
0x0510:0x0511  
0x0512  
2
1
1
2
1
1
4
0x0513  
PHY Register Address  
0x0514:0x0515  
0x0516  
PHY Data  
MII Management ECAT Access State  
MII Management PDI Access State  
PHY Port Status  
0x0517  
0x0518:0x051B  
TMC8460 PRELIMINARY, CONFIDENTIAL TARGET, NON-RELEASE VERSION Datasheet (V014 / 2015-Aug-31)  
Address1  
Description  
Length  
(Byte)  
0x0580:0x05FF  
0x0580:0x05AB  
128  
ESC Parameter Ram  
43  
TMC8460 MFCIO block configuration  
Can be written at start-up from EEPROM  
configuration (with category 1) or by ECAT or PDI  
at runtime.  
0x0600:0x06FF  
+0x0:0x3  
+0x4:0x5  
+0x6  
16x16  
FMMU[15:0]  
Logical Start Address  
Length  
4
2
1
1
2
1
1
1
3
Logical Start bit  
Logical Stop bit  
Physical Start Address  
Physical Start bit  
Type  
+0x7  
+0x8:0x9  
+0xA  
+0xB  
+0xC  
Activate  
+0xD:0xF  
Reserved  
TMC8460 PRELIMINARY, CONFIDENTIAL TARGET, NON-RELEASE VERSION Datasheet (V014 / 2015-Aug-31)  
Address1  
Description  
Length  
(Byte)  
0x0800:0x087F  
+0x0:0x1  
+0x2:0x3  
+0x4  
16x2  
SyncManager[15:0]  
Physical Start Address  
Length  
2
2
1
1
1
1
Control Register  
Status Register  
Activate  
+0x5  
+0x6  
+0x7  
PDI Control  
0x0900:0x09FF  
Distributed Clocks (DC)  
DC Receive Times  
Receive Time Port 0  
Receive Time Port 1  
Receive Time Port 2  
Receive Time Port 3  
0x0900:0x0903  
0x0904:0x0907  
0x0908:0x090B  
0x090C:0x090F  
4
4
4
4
DC Time Loop Contrl Un
System Time  
0x0910:0x0917  
0x0918:0x091F  
0x0920:0x0927  
0x0928:0x092B  
0x092C:0x092F  
0x0930:0x0931  
0x0932:0x0933  
0x0934  
4/8  
4/8  
4/8  
4
Receive Time CAT Pressing Unit  
System Time ffset  
System Tme Dely  
4
System TimDifference  
peed unter tart  
2
2
peed Couter Diff  
1
Sysem Time Difference Filter Depth  
Speed Counter Filter Depth  
Receive Time Latch Mode  
0x0935  
1
0x0936  
1
DC Cyclic Unit Control  
0x0980  
Cyclic Unit Control  
DC SYNC Out Unit  
Activation  
0x81  
x0982:0983  
984  
1
2
Pulse Length of SyncSignals  
Activation Status  
1
8E  
1
SYNC0 Status  
98F  
1
SYNC1 Status  
0x990:0x0997  
0x099:0x099F  
0x09A0:0x09A3  
0x09A4:0x09A7  
4/8  
4/8  
4
Start Time Cyclic Operation/Next SYNC0 Pulse  
Next SYNC1 Pulse  
SYNC0 Cycle Time  
4
SYNC1 Cycle Time  
DC Latch In Unit  
Latch0 Control  
Latch1 Control  
Latch0 Status  
0x09A8  
0x09A9  
0x09AE  
0x09AF  
1
1
1
1
Latch1 Status  
TMC8460 PRELIMINARY, CONFIDENTIAL TARGET, NON-RELEASE VERSION Datasheet (V014 / 2015-Aug-31)  
Address1  
Description  
Length  
(Byte)  
0x09B0:0x09B7  
0x09B8:0x09BF  
0x09C0:0x09C7  
0x09C8:0x09CF  
4/8  
4/8  
4/8  
4/8  
Latch0 Time Positive Edge  
Latch0 Time Negative Edge  
Latch1 Time Positive Edge  
Latch1 Time Negative Edge  
DC SyncManager Event Times  
EtherCAT Buffer Change Event Time  
PDI Buffer Start Event Time  
0x09F0:0x09F3  
0x09F8:0x09FB  
0x09FC:0x09FF  
4
4
4
PDI Buffer Change Event Time  
ESC specific  
0x0E00:0x0EFF  
256  
TMC8460 Product and Vendor ID  
User RAM/Extended ESC features  
User RAM  
0x0F80:0x0FFF  
0x0F80:0x0FA0  
128  
33  
Extended ESC features  
Process Data AM  
0x1000:0x4FFF  
0x4000:0x4056  
16 KB  
87  
Process Data AM  
TMC8460 MFCIO Memory Block 0 for ECAT Write  
Data  
0x4800:0x481C  
29  
TMC840 MFCMemory Block 1 for ECAT Read  
ata  
For Registers longer than one byte, the LShas the lowest and MSB the highest address.  
TMC8460 PRELIMINARY, CONFIDENTIAL TARGET, NON-RELEASE VERSION Datasheet (V014 / 2015-Aug-31)  
5 EtherCAT Register Description  
5.1 Type (0x0000)  
Table 12: Register Type (0x0000)  
ECAT  
PDI  
Reset Value  
Bit  
Description  
Trinamic ESC Type: 0xD0  
7:0  
Type of EtherCAT controller  
r/-  
r/-  
5.2 Revision (0x0001)  
Table 13: Register Revision (0x0001)  
ECAT  
PDI  
Rset Value  
Bit  
Description  
TMC80: 0x60  
TMC8461: 0x61  
7:0  
Revision of EtherCAT controller.  
r/-  
r/-  
5.3 Build (0x0002:0x0003)  
Table 14: Register Bld (0x0:0x0003)  
ECAT  
PDI  
Reset Value  
Bit  
Description  
TMC8460:  
0x02 = Version 1.0  
15:0  
Actual build of EtherCAT controller.  
r
r/-  
TMC8461:  
0x10 = Version 1.0  
5.4 FMMUs supported 0x000)  
Tabl15: Regter FMMUs supported (0x0004)  
ECAT PDI  
r/-  
Reset Value  
Bit  
Description  
TMC8460: 6  
TMC8461: 8  
7:0  
Number of ted FMMU channels (or r/-  
entities) f thherCAT Slave Controller.  
5.5 SyncManagrs supported (0x0005)  
Table 16: Register SyncManagers supported (0x0005)  
ECAT  
PDI  
Reset Value  
Bit  
tion  
TMC8460: 6  
TMC8461: 8  
7:0  
Numer of supported SyncManager channels r/-  
(or enties) of the EtherCAT Slave Controller  
r/-  
5.6 RAM Size (0x0006)  
Table 17: Register RAM Size (0x0006)  
 
TMC8460 PRELIMINARY, CONFIDENTIAL TARGET, NON-RELEASE VERSION Datasheet (V014 / 2015-Aug-31)  
ECAT  
PDI  
Reset Value  
Bit  
Description  
TMC8460: 16  
TMC8461: 16  
7:0  
Process Data RAM size supported by the r/-  
EtherCAT Slave Controller in KByte  
r/-  
5.7 Port Descriptor (0x0007)  
Table 18: Register Port Descriptor (0x0007)  
ECAT  
PDI  
Reset Value  
Bit  
Description  
Port configuration:  
00: Not implemented  
01: Not configured (SII EEPROM)  
10: EBUS  
11: MII / RMII / RGMII  
1:0  
3:2  
5:4  
7:6  
r/-  
r/-  
-  
r/-  
Port 0  
Port 1  
Port 2  
Port 3  
r/-  
r/-  
r/-  
r/-  
C846011  
MC8461: 11  
TC8460: 11  
TMC461: 11  
MC8460: 00  
MC8461: 00  
TMC8460: 00  
TMC8461: 11  
5.8 ESC Features supported (0x0008:0x0009)  
Table 19: Register ESC Feaures pporte(0x0008:0x0009)  
CAT  
PDI  
Reset Value  
Bit  
Description  
0
r/-  
r/-  
FMMU Operation:  
TMC8460: 0  
0:  
1:  
Bit oriented  
Byte oriented  
1
2
r/-  
r/-  
Reserved  
r/-  
r/-  
TMC8460: 0  
TMC8460: 1  
Distributed Clocks:  
0:  
1:  
Not avail
Availabl
3
4
5
6
7
r/-  
r/-  
r/-  
r/-  
r/-  
Distribud Clos (widt):  
r/-  
r/-  
r/-  
r/-  
r/-  
TMC8460: 1  
TMC8460: 0  
TMC8460: 0  
TMC8460: 1  
TMC8460: 1  
0:  
3bit  
1:  
64 t  
ter EBS:  
available, standard jitter  
lable, jitter minimized  
Enced Link Detection EBUS:  
0:  
1:  
Not available  
Available  
Enhanced Link Detection MII:  
0:  
Not available  
1:  
Available  
Separate Handling of FCS Errors:  
0:  
1:  
Not supported  
Supported, frames with wrong FCS and  
additional nibble will be counted  
separately in Forwarded RX Error  
Counter  
TMC8460 PRELIMINARY, CONFIDENTIAL TARGET, NON-RELEASE VERSION Datasheet (V014 / 2015-Aug-31)  
ECAT  
PDI  
Reset Value  
Bit  
Description  
8
r/-  
Enhanced DC SYNC Activation  
r/-  
TMC8460: 1  
0:  
1:  
Not available  
Available  
NOTE: This feature refers to registers 0x981[7:3],  
0x0984  
9
r/-  
r/-  
EtherCAT LRW command support:  
r/-  
TMC8460: 0  
TMC8460: 0  
0:  
1:  
Supported  
Not supported  
10  
EtherCAT read/write command support (BRW, r/-  
APRW, FPRW):  
0:  
1:  
Supported  
Not supported  
11  
r/-  
-  
Fixed FMMU/SyncManager configuration  
r/-  
MC8460:
MC8460: 0  
0:  
1:  
Variable configuration  
Fixed configuration (refer to  
documentation of supporting ESCs)  
15:12  
Reserved  
r/-  
5.9 Configured Station Address (0x0010:0x0011)  
Table 20: Register Configured Station Adess (0x0010x0011)  
ECAT  
PDI  
Reset Value  
Bit  
Description  
15:0  
r/-  
0
Address used for node addressing (FPx
commands)  
r/
5.10 Configured Station Alias (0x012:0x013)  
Table 1: Regisr Confured Station Alias (0x0012:0x0013)  
ECAT  
PDI  
Reset Value  
Bit  
Description  
0 until first EEPROM  
load, then EEPROM ADR  
0x0004  
15:0  
r/w  
Alias Address uor nodaddressing (FPxx r/-  
commands).  
The use of ths is ativated by Register  
DL Conol Bit (0x010.24/0x0103.0)  
NOTE: EEROM value is only taken over at first  
EEPROM loafter power-on or reset.  
5.11 Wster Enable (0x0020)  
This register/fuction is not available with TMC8460-BI.  
Table 22: Register Write Register Enable (0x0020)  
TMC8460 PRELIMINARY, CONFIDENTIAL TARGET, NON-RELEASE VERSION Datasheet (V014 / 2015-Aug-31)  
ECAT  
PDI  
Reset Value  
Bit  
Description  
0
If write register protection is enabled, this r/w  
register has to be written in the same Ethernet  
frame (value does not care) before other  
writes to this station are allowed. Write  
protection is still active after this frame (if  
Write Register Protection register is not  
changed).  
r/-  
0
7:1  
r/-  
0
Reserved, write 0  
r/-  
5.12 Write Register Protection (0x0021)  
This register/function is not available with TMC8460-BI.  
Table 23: Register Write Register Protection (0x0021)  
ECAT  
PDI  
Reet Value  
Bit  
Description  
0
r
0
Write register protection:  
r/w  
0:  
1:  
Protection disabled  
Protection enabled  
Registers 0x0000-0x0137, 0x013A-0x0F0F are write  
protected, except for 0x0030.  
7:1  
r/-  
0
Reserved, write 0  
r/-  
5.13 ESC Write Enable (0x0030)  
This register/function is not available with TMC846-BI.  
Tble 24: egister SC Write Enable (0x0030)  
ECAT PDI  
Reset Value  
Bit  
Description  
0
If ESC write pris enaed, this register r/w  
has to be wrthe same Ethernet frame  
(value des ncare) bfore other writes to  
this saon are lowed. ESC write protection  
is still tive after this frame (if ESC Write  
ection egister is not changed).  
r/-  
0
7:1  
, write 0  
r/-  
r/-  
0
5.14 ESC Protection (0x0031)  
This register/funcon is not available with TMC8460-BI.  
Table 25: Register ESC Write Protection (0x0031)  
TMC8460 PRELIMINARY, CONFIDENTIAL TARGET, NON-RELEASE VERSION Datasheet (V014 / 2015-Aug-31)  
ECAT  
PDI  
Reset Value  
Bit  
Description  
0
r/-  
0
Write protect:  
r/w  
0:  
1:  
Protection disabled  
Protection enabled  
All areas are write protected, except for 0x0030.  
Reserved, write 0  
7:1  
r/-  
0
r/-  
5.15 ESC Reset ECAT (0x0040)  
Table 26: Register ESC Reset ECAT (0x0040)  
ECAT PDI  
Reset Valu
Bit  
Write  
7:0  
Description  
A reset is asserted after writing 0x52 (‘R’), 0x45 r/w  
(‘E’) and 0x53 (‘S’) in this register with 3  
consecutive frames.  
r/-  
Read  
1:0  
Progress of the reset procedure:  
01: after writing 0x52  
10: after writing 0x45 (if 0x52 was written  
before)  
-  
0  
0
r/w  
00: else  
7:2  
Reserved, write 0  
r/-  
r/-  
5.16 ESC Reset PDI (0x0041)  
Table 27: Reister SC Reset DI (0x0041)  
ECAT PDI  
Reset Value  
Bit  
Write  
7:0  
Description  
A reset is asserted aftewritin0x52 (‘R’), 0x45 r/-  
(‘E’) and 0x53 (‘S’) in is regter with 3  
consecutive cos.  
r/w  
0
Read  
1:0  
Progress of theset predure:  
01: afr writin0x52  
10: aftwriting 0x45 (if 0x52 was written  
befor
r/w  
00  
0
r/-  
e  
7:2  
write 0  
r/-  
r/-  
5.17 ESC DControl (0x0100:0x0103)  
Table 28: Register ESC DL Control (0x0100:0x0103)  
TMC8460 PRELIMINARY, CONFIDENTIAL TARGET, NON-RELEASE VERSION Datasheet (V014 / 2015-Aug-31)  
ECAT  
PDI  
Reset Value  
Bit  
Description  
0
r/-  
1
Forwarding rule:  
r/w  
0:  
EtherCAT frames are processed,  
Non-EtherCAT frames are forwarded  
without processing  
EtherCAT frames are processed, Non-  
EtherCAT frames are destroyed  
1:  
The source MAC address is changed for every  
frame (SOURCE_MAC[1] is set to 1 locally  
administered address) regardless of the  
forwarding rule.  
1
r/-  
0
Temporary use of settings in Register 0x101:  
r/w  
0:  
1:  
permanent use  
use for about 1 second, then revert to  
previous settings  
7:2  
9:8  
r/-  
r/-  
Reserved, write 0  
r/-  
0
Loop Port 0:  
00: Auto  
r/w*  
01: Auto Close  
10: Open  
11: Closed  
NOTE:  
Loop open means sending/receiving over this port  
is enabled, loop closed means sending/receiving  
is disabled and frames are forwarded to the next  
open port internally.  
Auto: loop closed at link down, opened alink u
Auto Close: loop closed at link down, ned with  
writing 01 again after link up (or reeiving valid  
Ethernet frame at the cloed port
Open: loop open regardless of link ate  
Closed: loop closed gardlesof link ate  
11:10  
13:12  
15:14  
r/-  
r/-  
r/-  
00  
00  
00  
Loop Port 1:  
00: Auto  
01: Auto Clo
10: Open  
r/w*  
r/w*  
r/w*  
11: Cloed  
Loop t 2:  
00: Aut
Auto Cose  
n  
ed  
Lrt 3:  
00: Auto  
01: Ato Close  
10: Open  
11: Closed  
TMC8460 PRELIMINARY, CONFIDENTIAL TARGET, NON-RELEASE VERSION Datasheet (V014 / 2015-Aug-31)  
ECAT  
PDI  
Reset Value  
Bit  
Description  
18:16  
r/-  
7, later EEPROM  
ADR 0x0005[11:9]  
inverted  
RX FIFO Size (ESC delays start of forwarding  
until FIFO is at least half full).  
RX FIFO Size/RX delay reduction** :  
r/w  
Value: EBUS:  
MII:  
0:  
1:  
2:  
3:  
4:  
5:  
6:  
7:  
-50 ns  
-40 ns  
-30 ns  
-20 ns  
-10 ns  
no change no change  
no change no change  
-40 ns  
-40 ns  
-40 ns  
-40 ns  
no change  
default  
default  
NOTE: EEPROM value is only taken over at first  
EEPROM load after power-on or reset  
19  
r/-  
EBUS Low Jitter:  
r/w  
0:  
Normal jitter  
1:  
Reduced jitter  
21:20  
22  
-  
r/-  
later EEPROM  
ADR 0x0005[5:4]  
0, later EEPROM  
ADR 0x0005[6]  
Reserved, write 0  
r/w  
r/w  
EBUS remote link down signaling time:  
0:  
1:  
Default (~660 ms)  
Reduced (~80 µs)  
23  
24  
r/-  
r/-  
0, later EEPROM  
ADR 0x0005[7]  
0
Reserved, write 0  
r/w  
r/w  
Station alias:  
0:  
1:  
Ignore Station Alias  
Alias can be used for all configur
address commantypes (RD, FPW
…)  
31:25  
r/-  
0
Reserved, write 0  
r/-  
* Loop configuration changeayed util the end of a currently received or transmitted frame at the port.  
** The possibility of RX FIreduon depends on the clock source accuracy of the ESC and of every  
connected EtherCAT/Eerneevices (aster, slave, etc.). RX FIFO Size of 7 is sufficient for 100ppm accuracy, FIFO  
Size 0 is possible wih 25ppm ccuray (frame size of 1518/1522 Byte).  
5.18 PhReadWrite Offset (0x0108:0x0109)  
This regisn is not available with TMC8460-BI.  
Table 29: Register Physical Read/Write Offset (0x0108:0x0109)  
ECAT  
PDI  
Reset Value  
Bit  
Description  
15:0  
Offset of R/W Commands (FPRW, APRW) r/w  
between Read address and Write address.  
r/-  
0
RD_ADR = ADR and WR_ADR = ADR + R/W-Offset  
5.19 ESC DL Status (0x0110:0x0111)  
Table 30: Register ESC DL Status (0x0110:0x0111)  
TMC8460 PRELIMINARY, CONFIDENTIAL TARGET, NON-RELEASE VERSION Datasheet (V014 / 2015-Aug-31)  
ECAT  
PDI  
Reset Value  
Bit  
Description  
0
r/-  
0
PDI operational/EEPROM loaded correctly:  
r*/-  
0:  
EEPROM not loaded, PDI not operational  
(no access to Process Data RAM)  
EEPROM loaded correctly, PDI  
operational (access to Process Data  
RAM)  
1:  
1
2
r/-  
r/-  
0
PDI Watchdog Status:  
r*/-  
r*/-  
0:  
1:  
Watchdog expired  
Watchdog reloaded  
TMC8460: 1 until first  
EEPROM loathen  
EEPROM ADR 0000.9 or  
0x0000[15:12]  
Enhanced Link detection:  
0:  
1:  
Deactivated for all ports  
Activated for at least one port  
NOTE: EEPROM value is only taken over at first  
EEPROM load after power-on or reset  
3
4
r/-  
r/-  
0
0
Reserved  
r*/-  
r*/-  
Physical link on Port 0:  
0: No link  
1: Link detected  
5
6
r/-  
r/-  
r/-  
r/-  
r/-  
r/-  
r/-  
0
0
0
0
0
0
0
Physical link on Port 1:  
0: No link  
1: Link detected  
r*/-  
r*/-  
r*/-  
r*/-  
r*/-  
r*/-  
r*/-  
Physical link on Port 2:  
0: No link  
1: Link detected  
7
Physical link on Port 3:  
0: No link  
1: Link detected  
8
Loop Port 0:  
0: Open  
1: Closed  
9
Communication ort 0:  
0: No stable ccation  
1: Communicestabshed  
10  
11  
Loop Pt 1:  
0: Ope
1: Closed  
nicatin on Port 1:  
ble communication  
unication established  
TMC8460 PRELIMINARY, CONFIDENTIAL TARGET, NON-RELEASE VERSION Datasheet (V014 / 2015-Aug-31)  
ECAT  
PDI  
Reset Value  
Bit  
Description  
12  
r/-  
0
Loop Port 2:  
0: Open  
r*/-  
1: Closed  
13  
14  
15  
r/-  
r/-  
r/-  
0
0
0
Communication on Port 2:  
0: No stable communication  
1: Communication established  
r*/-  
r*/-  
r*/-  
Loop Port 3:  
0: Open  
1: Closed  
Communication on Port 3:  
0: No stable communication  
1: Communication established  
* Reading DL Status register from ECAT clears ECAT Event Request 0x0210[2].  
Table 31: Decoding port state in ESC DL Status register 0x0111 (tpicamodes nly)  
Port 2  
(not supported by  
TMC8460)  
Port 1  
rt 0  
Register  
0x0111  
Port 3  
(not supported by  
TMC8460)  
0x55  
0x56  
0x59  
0x5A  
0x65  
0x66  
0x69  
0x6A  
0x95  
0x96  
0x99  
0x9A  
0xA5  
0xA6  
0xA9  
0x
No link, closed  
No link, closed  
No link, closed  
No link, closed  
No link, closed  
No link, closed  
No link, closed  
No link, closed  
Link, open  
No link, closed  
No link, closed  
No link, closed  
No link, closd  
Link, ope
No link, closd  
No nk, closed  
ink, opn  
No link, closed  
Link, open  
No link, closed  
Link, open  
Linopen  
No link, closed  
No link, closed  
Link, open  
No link, closed  
Link, open  
Link, open  
Link, oen  
No link, closed  
Link, open  
Lik, ope
Link, open  
No li, closed  
link, closed  
No link, closed  
No link, closed  
Link, open  
No link, closed  
No link, closed  
Link, open  
No link, closed  
Link, open  
Link, open  
Link, open  
No link, closed  
Link, open  
Link, open  
Link, open  
Linkopen  
No link, closed  
No link, closed  
Link, open  
No link, closed  
Link, open  
Link, pen  
Link, open  
, ope
Link, open  
No link, closed  
Link, open  
pen  
Link, open  
Link, open  
0xD5  
0xD6  
0xD9  
0xDA  
nk, closed  
Linclosed  
Link, closed  
Link, closed  
No link, closed  
No link, closed  
No link, closed  
No link, closed  
No link, closed  
No link, closed  
Link, open  
No link, closed  
Link, open  
No link, closed  
Link, open  
Link, open  
TMC8460 PRELIMINARY, CONFIDENTIAL TARGET, NON-RELEASE VERSION Datasheet (V014 / 2015-Aug-31)  
5.20 AL Control (0x0120:0x0121)  
Table 32: Register AL Control (0x0120:0x0121)  
ECAT  
PDI  
Reset Value  
Bit  
Description  
3:0  
r/  
1
Initiate State Transition of the Device State  
Machine:  
r/(w)  
(w ack)*  
1:  
3:  
2:  
4:  
8:  
Request Init State  
Request Bootstrap State  
Request Pre-Operational State  
Request Safe-Operational State  
Request Operational State  
4
5
r/  
0
0
Error Ind Ack:  
r/(w)  
r/(w)  
r/(w)  
(w ack)*  
0:  
1:  
No Ack of Error Ind in AL status register  
Ack of Error Ind in AL status register  
r/  
Device Identification:  
(w ack)
0:  
1:  
No request  
Device Identification request  
15:6  
r/  
Reserved, write 0  
(w a
NOTE: AL Control register behaves like a mailbox if Device Emulatiois off (0x010.8=0): The PDI has to  
read/write* the AL Control register after ECAT has written it. OtherwisECAT cannot write again to the AL Control  
register. After Reset, AL Control register can be written by ECATRegardg mailbox functionality, both registers  
0x0120 and 0x0121 are equivalent, e.g. reading 0x0121 is sufficient o make this register writeable again.)  
If Device Emulation is on, the AL Control register can lwaybe writtn, its content is copied to the AL Status  
register.  
* PDI register function acknowledge by Write cmmanis disabled: Reading AL Control from PDI clears AL Event  
Request 0x0220[0]. Writing to this rester froPDI is not ossible.  
PDI register function acknowledge by Write cmand is enabled: Writing AL Control from PDI clears AL Event  
Request 0x0220[0]. Writing to this egister om PDs possible; write value is ignored (write 0).  
5.21 AL Status (0x0130:0x011)  
ble 33: egister AL Status (0x0130:0x0131)  
ECAT  
PDI  
Reset Value  
Bit  
Description  
3:0  
r/(w)  
1
Actual ate of tDevice State Machine:  
r*/-  
1:  
IniState  
Requet Bootstrap State  
-Opertional State  
-Operational State  
rational State  
4
r/(w)  
0
ErrInd:  
r*/-  
0:  
evice is in State as requested or Flag  
cleared by command  
1:  
Device has not entered requested State  
or changed State as result of a local  
action  
5
r/(w)  
r/(w)  
0
0
Device Identification:  
r*/-  
r*/-  
0:  
1:  
Device Identification not valid  
Device Identification loaded  
15:6  
Reserved, write 0  
NOTE: AL Status register is only writable from PDI if Device Emulation is off (0x0140.8=0), otherwise AL Status  
register will reflect AL Control register values.  
TMC8460 PRELIMINARY, CONFIDENTIAL TARGET, NON-RELEASE VERSION Datasheet (V014 / 2015-Aug-31)  
* Reading AL Status from ECAT clears ECAT Event Request 0x0210[3].  
5.22 AL Status Code (0x0134:0x0135)  
Table 34: Register AL Status Code (0x0134:0x0135)  
ECAT  
PDI  
Reset Value  
Bit  
Description  
15:0  
AL Status Code  
r/-  
r/w  
0
5.23 RUN LED Override (0x0138)  
This register/function is not available with TMC8460-BI.  
Table 35: Register RUN LED Override (0x0138)  
ECAT  
PDI  
eset Value  
Bit  
Description  
3:0  
LED code: (FSM State  
r/w  
0
r/w  
0x0:  
Off  
(1-Init)  
0x1-0xC: Flash 1x 12x  
(4-SafeOp 1x)  
(2-PreOp)  
(3-Bootrap)  
(8-Op)  
0xD:  
0xE:  
0xF:  
Blinking  
Flickering  
On  
4
Enable Override:  
r/w  
r/w  
0
0
r/w  
r/w  
0:  
1:  
Override disabled  
Override enabled  
7:5  
Reserved, write 0  
NOTE: Changes to AL Status register (0x0130) wivalvalues widisable RUN LED Override (0x0138[4]=0). The  
value read in this register always reflects curret LED ouut.  
5.24 ERR LED Override (00139)  
This register/function is noilable ith TMC8460-BI.  
Tab36: Register ERR LED Override (0x0139)  
ECAT  
PDI  
Reset Value  
Bit  
Descripon  
3:0  
ode:  
r/w  
0
r/w  
Off  
Flash 1x 12x  
0xE
0xF:  
Blinking  
Flickering  
On  
4
Enable Override:  
r/w  
r/w  
0
0
r/w  
r/w  
0:  
1:  
Override disabled  
Override enabled  
7:5  
Reserved, write 0  
NOTE: New error conditions will disable ERR LED Override (0x0139[4]=0). The value read in this register always  
reflects current LED output.  
TMC8460 PRELIMINARY, CONFIDENTIAL TARGET, NON-RELEASE VERSION Datasheet (V014 / 2015-Aug-31)  
5.25 PDI Control (0x0140)  
Table 37: Register PDI Control (0x0140)  
ECAT  
PDI  
Reset Value  
Bit  
Description  
TMC8460: 0x05,  
later EEPROM ADR  
0x0000  
7:0  
r/-  
Process data interface:  
0x00: Interface deactivated (no PDI)  
0x01: 4 Digital Input  
r/-  
0x02: 4 Digital Output  
0x03: 2 Digital Input and 2 Digital Output  
0x04: Digital I/O  
0x05: SPI Slave  
0x06: Oversampling I/O  
0x07: EtherCAT Bridge (port 3)  
0x08: 16 Bit asynchronous Microcontroller  
interface  
0x09: 8 Bit asynchronous Microcontroller  
interface  
0x0A: 16 Bit synchronous Microcontroller  
interface  
0x0B: 8 Bit synchronous Microcontroller  
interface  
0x10: 32 Digital Input and 0 Digital Oput  
0x11: 24 Digital Input and 8 DigitaOutpu
0x12: 16 Digital Input and 16 Dl  
Output  
0x13: 8 Digital Inpuand 24 igital Ouut  
0x14: 0 Digital Input and 32 Diital Output  
0x80: On-chip bus  
Others: Reserved  
5.26 ESC Configurat0141)  
Tabl38: Register ESC Configuration (0x0141)  
ECAT  
PDI  
Reset Value  
Bit  
Descripon  
TMC8460: 1 with  
PDI_EMULATION pin,  
later EEPROM ADR  
0x0000  
0
r/-  
ce emation (control of AL status):  
r/-  
status register has to be set by PDI  
tatus register will be set to value  
ten to AL control register  
0,  
1
2
3
4
r/-  
r/-  
r/-  
r/-  
Ennced Link detection all ports:  
r/-  
r/-  
r/-  
r/-  
later EEPROM ADR  
0x0000  
0:  
1:  
sabled (if bits [7:4]=0)  
enabled at all ports (overrides bits [7:4])  
TMC8460: Depends on  
configuration  
later EEPROM ADR  
0x0000  
Distributed Clocks SYNC Out Unit:  
0:  
1:  
disabled (power saving)  
enabled  
Distributed Clocks Latch In Unit:  
0:  
1:  
disabled (power saving)  
enabled  
0, later EEPROM ADR  
0x0000  
Enhanced Link port 0:  
0:  
1:  
disabled (if bit 1=0)  
enabled  
TMC8460 PRELIMINARY, CONFIDENTIAL TARGET, NON-RELEASE VERSION Datasheet (V014 / 2015-Aug-31)  
ECAT  
PDI  
Reset Value  
Bit  
Description  
5
r/-  
Enhanced Link port 1:  
r/-  
0:  
1:  
disabled (if bit 1=0)  
enabled  
6
7
r/-  
r/-  
Enhanced Link port 2:  
r/-  
r/-  
0:  
disabled (if bit 1=0)  
1:  
enabled  
Enhanced Link port 3:  
0:  
1:  
disabled (if bit 1=0)  
enabled  
5.27 PDI Information (0x014E:0x014F)  
Table 39: Register PDI Information (0x014E:0x014F)  
ECAT  
PDI  
eset Value  
Bit  
Description  
T8460: Depends o
confuration  
r/-  
0
PDI register function acknowledge by write:  
r/-  
0:  
1:  
Disabled  
Enabled  
1
2
r/-  
r/-  
r/-  
r/-  
PDI configured:  
r/-  
r/-  
r/-  
r/-  
0:  
PDI not configured  
1:  
PDI configured (EEPROM loaded)  
PDI active:  
0:  
1:  
PDI not active  
PDI active  
3
PDI configuration invalid:  
0:  
1:  
PDI configuration ok  
PDI configuration invalid  
7:4  
Reserved  
5.28 PDI Configura(0x050:0x0153)  
The PDI configuraon regier 0x050 and the extended PDI configuration registers 0x0152:0x0153  
depend on the selted PDI.  
The Sync/:0] PDconfiguration register 0x0151 is independent of the selected PDI.  
The TMy supports SPI PDI. Thus the PDI number is always 0x05.  
5.28.1 PDI SPSlave Configuration  
Table 40: Register PDI SPI Slave Configuration (0x0150)  
TMC8460 PRELIMINARY, CONFIDENTIAL TARGET, NON-RELEASE VERSION Datasheet (V014 / 2015-Aug-31)  
ECAT  
PDI  
Reset Value  
Bit  
Description  
1:0  
r/-  
TMC8460: 3  
SPI mode:  
r/-  
00: SPI mode 0  
01: SPI mode 1  
10: SPI mode 2  
11: SPI mode 3  
NOTE: SPI mode 3 is recommended for Slave  
Sample Code  
NOTE: SPI status flag is not available in SPI modes  
0 and 2 with normal data out sample.  
3:2  
r/-  
SPI_IRQ output driver/polarity:  
00: Push-Pull active low  
r/-  
01: Open Drain (active low)  
10: Push-Pull active high  
11: Open Source (active high)  
r/-  
-  
4
5
SPI_SEL polarity:  
r/-  
r/-  
0:  
1:  
Active low  
Active high  
Data Out sample mode:  
0:  
Normal sample (SPI_DO and SPI_DI are  
sampled at the same SPI_CLK edge)  
Late sample (SPI_DO and SPI_DI are  
sampled at different SPI_CLK edges)  
1:  
7:6  
r/-  
Reserved, set EEPROM value 0  
r/-  
Table 41: Register PDI SPI lave tended configuration (0x0152:0x0153)  
ECAT  
PDI  
Reset Value  
Bit  
Description  
r/-  
TMC8460: 0  
15:0  
Reserved, set EEPRM value 0  
r/-  
5.28.2 Sync/Latc1:0] PDConfiuration  
Table 42: Register Sync/Latch[1:0] PDI Configuration (0x0151)  
TMC8460 PRELIMINARY, CONFIDENTIAL TARGET, NON-RELEASE VERSION Datasheet (V014 / 2015-Aug-31)  
ECAT  
PDI  
Reset Value  
Bit  
Description  
1:0  
r/-  
TMC8460: 10  
SYNC0 output driver/polarity:  
00: Push-Pull active low  
r/-  
01: Open Drain (active low)  
10: Push-Pull active high  
11: Open Source (active high)  
2
3
r/-  
r/-  
TMC8460: 1  
SYNC0/LATCH0 configuration*:  
r/-  
r/-  
0:  
LATCH0 Input  
1:  
SYNC0 Output  
TMC8460: Depends  
on configuration  
SYNC0 mapped to AL Event Request register  
0x0220.2:  
0:  
1:  
Disabled  
Enabled  
5:4  
r/-  
TMC80: 10  
MC8460: 1  
SYNC1 output driver/polarity:  
00: Push-Pull active low  
01: Open Drain (active low)  
10: Push-Pull active high  
11: Open Source (active high)  
r/-  
6
7
-  
SYNC1/LATCH1 configuration*:  
r/-  
r/-  
0:  
1:  
LATCH1 input  
SYNC1 output  
TMC8460: Depends  
on configuration  
SYNC1 mapped to AL Event Request register  
0x0220.3:  
0:  
1:  
Disabled  
Enabled  
* The TMC8460 has concurrent SYNC[1:0] outputs and ATCH[1:inputs, independent of this configuration.  
5.29 ECAT Event Mask (0x0200:0x001)  
Tabl43: Regter ECAEvent Mask (0x0200:0x0201)  
ECAT  
PDI  
Reset Value  
Bit  
Description  
15:0  
ECAT Event mthe ECT Event Request  
Events for mintECAT event field of  
EtherCAT fram
r/-  
0
r/w  
0:  
Crespondig ECAT Event Request  
regter bit is not mapped  
Corresonding ECAT Event Request  
ister bit is mapped  
5.30 PDI AL Event Mask (0x0204:0x0207)  
Table 44: Register PDI AL Event Mask (0x0204:0x0207)  
TMC8460 PRELIMINARY, CONFIDENTIAL TARGET, NON-RELEASE VERSION Datasheet (V014 / 2015-Aug-31)  
ECAT  
PDI  
Reset Value  
Bit  
Description  
31:0  
AL Event masking of the AL Event Request  
register Events for mapping to PDI IRQ signal:  
r/w  
0x00FF:0xFF0F  
r/-  
0:  
Corresponding AL Event Request register  
bit is not mapped  
1:  
Corresponding AL Event Request register  
bit is mapped  
5.31 ECAT Event Request (0x0210:0x0211)  
Table 45: Register ECAT Event Request (0x0210:0x0211)  
ECAT  
PDI  
Reset Valu
Bit  
Description  
0
r/-  
0
DC Latch event:  
r/-  
0:  
1:  
No change on DC Latch Inputs  
At least one change on DC Latch Inputs  
(Bit is cleared by reading DC Latch event  
times from ECAT for ECAT controlled Latch  
Units, so that Latch 0/1 Status 0x09AE:0x09AF  
indicates no event)  
1
2
r/-  
r/-  
0
0
Reserved  
r/-  
r/-  
DL Status event:  
0:  
1:  
No change in DL Status  
DL Status change  
(Bit is cleared by reading out DL Status  
0x0110:0x0111 from ECAT)  
3
r/-  
r/-  
0
0
AL Status event:  
r/-  
r/-  
0:  
1:  
No change in AL Status  
AL Status change  
(Bit is cleared by reading out AL Status  
0x0130:0x0131 from ECAT)  
Mirrors values of each yncMaager Status:  
4
5
0:  
1:  
0:  
1:  
No Sync Channel 0 ent  
Sync Chavent nding  
No Sync l 1 event  
Sync Chl 1 evet pending  
11  
0:  
NSync Channel 7 event  
1:  
Sync hannel 7 event pending  
15:12  
r/-  
0
d  
r/-  
5.32 AL Event Request (0x0220:0x0223)  
Table 46: Register AL Event Request (0x0220:0x0223)  
TMC8460 PRELIMINARY, CONFIDENTIAL TARGET, NON-RELEASE VERSION Datasheet (V014 / 2015-Aug-31)  
ECAT  
PDI  
Reset Value  
Bit  
Description  
0
r/-  
0
AL Control event:  
r/-  
0:  
1:  
No AL Control Register change  
AL Control Register has been written2  
(Bit is cleared by reading AL Control register  
0x0120:0x0121 from PDI)  
1
r/-  
0
DC Latch event:  
r/-  
0:  
1:  
No change on DC Latch Inputs  
At least one change on DC Latch Inputs  
(Bit is cleared by reading DC Latch event  
times from PDI, so that Latch 0/1 Status  
0x09AE:0x09AF indicates no event. Available if  
Latch Unit is PDI controlled)  
2
3
4
r/-  
r/-  
-  
0
0
0
State of DC SYNC0 (if register 0x0151.3=1):  
(Bit is cleared by reading SYNC0 status  
0x098E from PDI, use only in Acknowledge  
mode)  
r/-  
r/-  
r/-  
State of DC SYNC1 (if register 0x0151.7=1):  
(Bit is cleared by reading of SYNC1 status  
0x098F from PDI, use only in Acknowledge  
mode)  
SyncManager activation register  
(SyncManager register offset 0x6) changed:  
0:  
1:  
No change in any SyncManager  
At least one SyncManager changed  
(Bit is cleared by reading SyncManage
Activation registers 0x0806 etc. from DI)  
5
r/-  
r/-  
r/-  
r/-  
0
0
EEPROM Emulation:  
0:  
1:  
No command pending  
EEPROM command pnding  
(Bit is cleared by ackowledgng the mmand  
in EEPROM command registe0x0502 from  
PDI)  
6
7
Watchdog Proa:  
0:  
1:  
Has not d  
Haexpir
(Bit is leared by reading Watchdog Status  
Process ata 0x0440 from PDI)  
r/-  
r/-  
0
0
ed  
r/-  
r/-  
ger interrupts (SyncManager  
ffset 0x5, bit [0] or [1]):  
8
9
0
1:  
0:  
1:  
No SyncManager 0 interrupt  
SyncManager 0 interrupt pending  
NSyncManager 1 interrupt  
SyncManager 1 interrupt pending  
….  
23  
0:  
No SyncManager 15 interrupt  
1:  
SyncManager 15 interrupt pending  
31:24  
r/-  
0
Reserved  
r/-  
2
AL control event is only generated if PDI emulation is turned off (PDI Control register 0x0140.8=0)  
TMC8460 PRELIMINARY, CONFIDENTIAL TARGET, NON-RELEASE VERSION Datasheet (V014 / 2015-Aug-31)  
5.33 RX Error Counter (0x0300:0x0307)  
Errors are only counted if the corresponding port is enabled.  
Table 47: Register RX Error Counter Port y (0x0300+y*2:0x0301+y*2)  
ECAT  
Description  
Invalid frame counter of Port y (counting is r/  
PDI  
Reset Value  
Bit  
7:0  
r/-  
0
stopped when 0xFF is reached).  
w(clr)  
15:8  
RX Error counter of Port y (counting is stopped r/  
when 0xFF is reached). This is coupled directly w(clr)  
to RX ERR of MII interface/EBUS interface.  
r/-  
0
NOTE: Error Counters 0x0300-0x030B are cleared if one of the RX Error counters 0x0300-0x030B is writte. Write  
value is ignored (write 0).  
5.34 Forwarded RX Error Counter (0x0308:0x030B)  
Table 48: Register Forwarded RX Error Counter Port y (0x0308+y)  
ECAT  
Forwarded error counter of Port y (counting is r/  
stopped when 0xFF is reached). w(clr)  
DI  
Reset Value  
Bit  
Description  
7:0  
r/-  
NOTE: Error Counters 0x0300-0x030B are cleared if one of the RX Errocounters x0300-0x030B is written. Write  
value is ignored (write 0).  
5.35 ECAT Processing Unit Error Counter (0x030C
Table 49: Register ECAT essing UnError Counter (0x030C)  
ECAT  
PDI  
Reset Value  
Bit  
Description  
7:0  
ECAT Processing Unit errocounr (counting r/  
is stopped when xFF is eachedCounts w(clr)  
errors of frames passig the ocessing Unit  
(e.g., FCS is wrong or dagram structure is  
wrong).  
r/-  
0
NOTE: Error Counter 0x030ared ierror counter 0x030C is written. Write value is ignored (write 0).  
5.36 PDI Error ounter (0x030D)  
Table 50: Register PDI Error Counter (0x030D)  
ECAT  
PDI  
Reset Value  
Bit  
on  
7:0  
Pror counter (counting is stopped when r/  
0xFF s reached). Counts if a PDI access has an w(clr)  
interfaerror.  
r/-  
0
NOTE: Error Counter 0x030D and Error Code 0x030E are cleared if error counter 0x030D is written. Write value is  
ignored (write 0).  
5.37 SPI PDI Error Code (0x030E)  
Table 51: Register SPI PDI Error Code (0x030E)  
TMC8460 PRELIMINARY, CONFIDENTIAL TARGET, NON-RELEASE VERSION Datasheet (V014 / 2015-Aug-31)  
ECAT  
PDI  
Reset Value  
Bit  
Description  
SPI access which caused last PDI Error.  
r/-  
r/-  
0
2:0  
Number of SPI clock cycles of whole access  
(modulo 8)  
3
4
Busy violation during read access  
Read termination missing  
5
7:6  
Access continued after read termination byte  
SPI command CMD[2:1]  
NOTE: Error Counter 0x030D and Error Code 0x030E are cleared if error counter 0x030D is written. Write value is  
ignored (write 0).  
5.38 Lost Link Counter (0x0310:0x0313)  
Table 52: Register Lost Link Counter Port y (0x0310+y)  
ECAT  
PDI  
eset Value  
Bit  
Description  
7:0  
Lost Link counter of Port y (counting is r/  
stopped when 0xff is reached). Counts only if w(clr)  
port loop is Auto.  
r/-  
0
NOTE: Only lost links at open ports are counted. Lost Link Counters 0x00x0313 red if one of the Lost  
Link Counters 0x0310-0x0313 is written. Write value is ignored (write ).  
5.39 Watchdog Divider (0x0400:0x0401)  
Table 53: Register Wathdog vider (0400:0x0401)  
CAT  
PDI  
Reset Value  
Bit  
Description  
15:0  
Watchdog divider: Nmber 25 MHz tics r/w  
(minus 2) that represents the bac watchdog  
increment. (Default alue is 00µs = 498)  
r/-  
0x09C2  
5.40 Watchdog Time PDI (0x410:0x0411)  
54: egister Watchdog Time PDI (0x0410:0x0411)  
ECAT  
PDI  
Reset Value  
Bit  
Descripon  
15:0  
Watchdg Time PDI: number or basic r/w  
watchdog ncrements  
r/-  
0x03E8  
t valuwith Watchdog divider 100µs  
0ms Watchdog)  
Watchdog ed if Watchdog time is set to 0x0000. Watchdog is restarted with every PDI access.  
5.41 Watchdog Time Process Data (0x0420:0x0421)  
Table 55: Register Watchdog Time Process Data (0x0420:0x0421)  
TMC8460 PRELIMINARY, CONFIDENTIAL TARGET, NON-RELEASE VERSION Datasheet (V014 / 2015-Aug-31)  
ECAT  
PDI  
Reset Value  
Bit  
Description  
15:0  
Watchdog Time Process Data: number of basic r/w  
watchdog increments  
r/-  
0x03E8  
(Default value with Watchdog divider 100µs  
means 100ms Watchdog)  
There is one Watchdog for all SyncManagers. Watchdog is disabled if Watchdog time is set to 0x0000.  
Watchdog is restarted with every write access to SyncManagers with Watchdog Trigger Enable Bit set.  
5.42 Watchdog Status Process Data (0x0440:0x0441)  
Table 56: Register Watchdog Status Process Data (0x0440:0x0441)  
ECAT  
PDI  
Reset Vale  
Bit  
Description  
0
r/  
0
Watchdog Status of Process Data (triggered  
by SyncManagers)  
r/-  
(w ack)*  
0:  
1:  
Watchdog Process Data expired  
Watchdog Process Data is active or  
disabled  
15:1  
r
0
Reserved  
r/-  
w ack
* PDI register function acknowledge by Write command is disabled: Reg this rrom PDI clears AL  
Event Request 0x0220[6]. Writing to this register from PDI is not posble.  
PDI register function acknowledge by Write command ienable: Writing thiregister from PDI clears AL Event  
Request 0x0220[6]. Writing to this register from PDI is possible; writvalue is ignored (write 0).  
5.43 Watchdog Counter Process Data (0x042)  
Table 57: Register Wachdg Counter rocess Data (0x0442)  
ECAT  
PDI  
Reset Value  
Bit  
Description  
7:0  
Watchdog CounteProcesData ounting is r/  
stopped when 0xFis reahed). ounts if w(clr)  
Process Data Watchdog expires
r/-  
0
NOTE: Watchdog Counters 0x0443 acleared if one of the Watchdog Counters 0x0442-0x0443 is written.  
Write value is ignored (wr
5.44 WatchdoCounter PDI (0x0443)  
Table 58: Register Watchdog Counter PDI (0x0443)  
ECAT  
PDI  
Reset Value  
Bit  
on  
7:0  
g PDI counter (counting is stopped r/  
w0xFF is reached). Counts if PDI w(clr)  
Watdog expires.  
r/-  
0
NOTE: Watchdog Counters 0x0442-0x0443 are cleared if one of the Watchdog Counters 0x0442-0x0443 is written.  
Write value is ignored (write 0).  
5.45 SII EEPROM Interface (0x0500:0x050F)  
Table 59: SII EEPROM Interface Register overview  
Length  
(Byte)  
Register Address  
Description  
0x0500  
0x0501  
1
1
EEPROM Configuration  
EEPROM PDI Access State  
TMC8460 PRELIMINARY, CONFIDENTIAL TARGET, NON-RELEASE VERSION Datasheet (V014 / 2015-Aug-31)  
Length  
(Byte)  
Register Address  
Description  
0x0502:0x0503  
0x0504:0x0507  
0x0508:0x050F  
2
4
EEPROM Control/Status  
EEPROM Address  
EEPROM Data  
4/8  
EtherCAT controls the SSI EEPROM interface if EEPROM configuration register 0x0500.0=0 and EEPROM  
PDI Access register 0x0501.0=0, otherwise PDI controls the EEPROM interface.  
In EEPROM emulation mode, the PDI executes outstanding EEPROM commands. The PDI has access to  
some registers while the EEPROM Interface is busy.  
Table 60: Register EEPROM Configuration (0x0500)  
ECAT  
PDI  
eset Value  
Bit  
Description  
0
r/-  
0
EEPROM control is offered to PDI:  
r/w  
0:  
no  
1:  
yes (PDI has EEPROM control)  
1
r/-  
r/-  
0
Force ECAT access:  
r/w  
r/-  
0:  
1:  
Do not change Bit 501.0  
Reset Bit 501.0 to 0  
7:2  
Reserved, write 0  
Table 61: Register EEPRM PDAccess tate (0x0501)  
CAT  
PDI  
Reset Value  
Bit  
Description  
0
r/(w)  
0
Access to EEPROM:  
r/-  
0:  
1:  
PDI releases EEPROM access  
PDI takes EEPM accs (PDI as  
EEPROM control)  
7:1  
r/-  
0
Reserved, write 0  
r/-  
NOTE: r/(w): write access is sible if 0x0500.0=1 and 0x0500.1=0.  
TMC8460 PRELIMINARY, CONFIDENTIAL TARGET, NON-RELEASE VERSION Datasheet (V014 / 2015-Aug-31)  
Table 62: Register EEPROM Control/Status (0x0502:0x0503)  
ECAT  
PDI  
Reset Value  
Bit  
Description  
ECAT write enable*2:  
r/(w)  
0
r/-  
0
0:  
1:  
Write requests are disabled  
Write requests are enabled  
This bit is always 1 if PDI has EEPROM control.  
4:1  
5
r/-  
r/-  
0
Reserved, write 0  
r/-  
r/-  
TMC8460: 0  
EEPROM emulation:  
0:  
1:  
Normal operation (I²C interface used)  
PDI emulates EEPROM (I²C not used)  
6
7
r/-  
r/-  
0
Supported number of EEPROM read bytes:  
r/-  
0:  
1:  
4 Bytes  
8 Bytes  
Selected EEPROM Algorithm:  
r/-  
TMC860pin  
PROM_SIZE  
0:  
1:  
1 address byte (1KBit 16KBit EEPROMs)  
2 address bytes (32KBit 4 MBit EEPROMs)  
Command register*2:  
Write: Initiate command.  
r/(w)  
10:8  
rw)  
r
Read: Currently executed command  
Commands:  
000: No command/EEPROM idle (clear error bits)  
001: Read  
010: Write  
100: Reload  
Others: Reserved/invalid commands (do ot issue
EEPROM emulation only: after execution, DI writ
command value to indicate operation ady.  
11  
12  
r/-  
r/-  
0
0
Checksum Error at in ESC Configuration rea:  
r/-  
r/-  
0:  
1:  
Checksum ok  
Checksum errr  
EEPROM loading statu
0:  
1:  
EEPROM loaded, dece infomation ok  
EEPROM noded, dvice information not  
availablM loading in progress or  
finished a faile)  
Error Acnowlee/Command*3:  
r/-  
13  
r/-  
r/[w]  
0
0:  
1:  
Nerror  
Missig EEPROM acknowledge or invalid  
mmad  
mulation only: PDI writes 1 if a temporary  
s occurred.  
ErroWrite Enable*3:  
r/-  
r/-  
14  
15  
r/-  
r/-  
0
0
0:  
1:  
Nerror  
Write Command without Write enable  
Busy:  
0:  
1:  
EEPROM Interface is idle  
EEPROM Interface is busy  
NOTE: r/(w): write access depends upon the assignment of the EEPROM interface (ECAT/PDI). Write access is  
generally blocked if EEPROM interface is busy (0x0502.15=1).  
NOTE: r/[w]: EEPROM emulation only: write access is possible if EEPROM interface is busy (0x0502.15=1). PDI  
acknowledges pending commands by writing a 1 into the corresponding command register bits (0x0502[10:8]).  
Errors can be indicated by writing a 1 into the error bit 0x0502.13. Acknowledging clears AL Event Request  
0x0220[5].  
TMC8460 PRELIMINARY, CONFIDENTIAL TARGET, NON-RELEASE VERSION Datasheet (V014 / 2015-Aug-31)  
2
* Write Enable bit 0 is self-clearing at the SOF of the next frame, Command bits [10:8] are self-clearing after the  
command is executed (EEPROM Busy ends). Writing “000” to the command register will also clear the error bits  
[14:13]. Command bits [10:8] are ignored if Error Acknowledge/Command is pending (bit 13).  
3
* Error bits are cleared by writing “000” (or any valid command) to Command Register Bits [10:8].  
Table 63: Register EEPROM Address (0x0504:0x0507)  
ECAT  
PDI  
Reset Value  
Bit  
Description  
31:0  
r/(w)  
0
EEPROM Address  
r/(w)  
0:  
1:  
First word (= 16 bit)  
Second word  
Actually used EEPROM Address bits:  
[9:0]: EEPROM size up to 16 kBit  
[17:0]: EEPROM size 32 kBit 4 Mbit  
[32:0]: EEPROM Emulation  
NOTE: r/(w): write access depends upon the assignment of the EEPROM interface (CAPDI). Wte access is  
generally blocked if EEPROM interface is busy (0x0502.15=1).  
Table 64: Register EEPROM Data (0x0508:0x50F [0x08:0x0B])  
ECT  
PD
Reset Value  
Bit  
Description  
15:0  
r/(w)  
r/[w]  
0
EEPROM Write data (data to be written to  
EEPROM) or  
r/(w)  
EEPROM Read data (data read from EEROM,.  
lower bytes)  
63:16  
r/-  
r/[w]  
EEPROM Read data (data read frm EEPOM,  
higher bytes)  
r/-  
NOTE: r/(w): write access depends pon thassignmnt of the EEPROM interface (ECAT/PDI). Write access is  
generally blocked if EEPROM interfacis busy x0502.15=1).  
NOTE: r/[w]: write access for EEPROM emation if read or reload command is pending. See the following  
information for further deta
TMC8460 PRELIMINARY, CONFIDENTIAL TARGET, NON-RELEASE VERSION Datasheet (V014 / 2015-Aug-31)  
5.45.1 EEPROM emulation with TMC8460  
Write access to EEPROM Data register 0x0508:0x050F is possible if EEPROM interface is busy  
(0x0502.15=1). PDI places EEPROM read data in this register before the pending EEPROM Read  
command is acknowledged (writing to 0x0502[10:8]). For Reload command: place the following  
information in the EEPROM Data register before acknowledging the command. This data is  
automatically transferred to the designated registers when the Reload command is acknowledged:  
Table 65: Register EEPROM Data for EEPROM Emulation Reload (0x0508:0x050F)  
ECAT  
PDI  
Reset Value  
Bit  
Description  
15:0  
r/-  
r/[w]  
0
Configured Station Alias  
(reloaded into 0x0012[15:0])  
16  
r/-  
r/-  
r/-  
r/[w]  
r/[w]  
r/[w]  
0
0
0
Enhanced Link Detection for all ports  
(reloaded into 0x0141[1])  
20:17  
24:21  
Enhanced Link Detection for individual ports  
(reloaded into 0x0141[7:4])  
ESC DL configuration  
(loaded into register 0x0100[23:20])  
NOTE: This value is only taken over at the first  
EEPROM loading  
27:25  
r/[w]  
0
FIFO Size reduction (loaded into register  
0x0100[18:16]:  
r/-  
000: FIFO Size 7  
001: FIFO Size 6  
010: FIFO Size 5  
011: FIFO Size 4  
100: FIFO Size 3  
101: FIFO Size 2  
110: FIFO Size 1  
111: FIFO Size 0  
NOTE: This value is onlaken or at thfirst  
EEPROM loading  
31:28  
r/[w]  
0
Reserved, writ
r/-  
NOTE: r/[w]: write accs foPROM eulation if read or reload command is pending.  
5.46 MII Management Interface (0x0510:0x0515)  
Table 66: MII Management Interface Register Overview  
Length  
(Byte)  
Rr Address  
Description  
0x051:0x0511  
0x0512  
2
1
1
2
1
1
4
MII Management Control/Status  
PHY Address  
0x0513  
PHY Register Address  
PHY Data  
0x0514:0x0515  
0x0516  
MII Management ECAT Access State  
MII Management PDI Access State  
PHY Port Status  
0x0517  
0x0518:0x051B  
TMC8460 PRELIMINARY, CONFIDENTIAL TARGET, NON-RELEASE VERSION Datasheet (V014 / 2015-Aug-31)  
PDI controls the MII management interface if MII Management PDI Access register 0x0517.0=1, otherwise  
EtherCAT controls the MII management interface.  
TMC8460 PRELIMINARY, CONFIDENTIAL TARGET, NON-RELEASE VERSION Datasheet (V014 / 2015-Aug-31)  
Table 67: Register MII Management Control/Status (0x0510:0x0511)  
ECAT  
PDI  
Reset Value  
Bit  
Description  
0
r/(w)  
r/-  
0
Write enable*:  
0:  
1:  
Write disabled  
Write enabled  
This bit is always 1 if PDI has MI control.  
Management Interface can be controlled by  
PDI (registers 0x0516-0 x0517):  
TMC8460: 1  
TMC8460: 0  
1
2
r/-  
r/-  
r/-  
r/-  
0:  
1:  
Only ECAT control  
PDI control possible  
MI link detection (link configuration, link  
detection, registers 0x0518-0x051B):  
0:  
1:  
Not available  
MI link detection active  
MC8460: Depenn  
onfiguration  
7:3  
9:8  
PHY address of port 0  
r/-  
r/-  
Command register*:  
r/(w)  
0
r/(w)  
Write: Initiate command.  
Read: Currently executed command  
Commands:  
00: No command/MI idle (clear error bits)  
01: Read  
10: Write  
Others: Reserved/invalid commands (do not  
issue)  
12:10  
13  
r/-  
0
0
Reserved, write 0  
Read error:  
r/-  
r/(w)  
r/(w)  
0:  
No read error  
1:  
Read error occurrd (PHY register ot  
available)  
Cleared by writing tthis reister.  
14  
15  
r/-  
r/-  
0
0
Command error:  
r/-  
r/-  
0:  
1:  
Last Command was sccessful  
Invalid cor wre command  
without Enabe  
Cleared ith a lid command or by writing  
“00” tommand egister bits [9:8].  
Busy:  
I conol state machine is idle  
control state machine is active  
NOTE: r/ (wess depends on assignment of MI (ECAT/PDI). Write access is generally blocked if  
Management irface is busy (0x0510.15=1).  
* Write enable bit is self-clearing at the SOF of the next frame (or at the end of the PDI access), Command bits  
[9:8] are self-clearing after the command is executed (Busy ends). Writing “00” to the command register will also  
clear the error bits [14:13]. The Command bits are cleared after the command is executed.  
TMC8460 PRELIMINARY, CONFIDENTIAL TARGET, NON-RELEASE VERSION Datasheet (V014 / 2015-Aug-31)  
Table 68: Register PHY Address (0x0512)  
ECAT  
PDI  
Reset Value  
Bit  
4:0  
6:5  
7
Description  
PHY Address  
Reserved, write 0  
Show configured PHY address of port 0-3 in  
register 0x0510[7:3]. Select port x with bits  
[4:0] of this register (valid values are 0-3):  
r/(w)  
r/-  
r/(w)  
r/-  
r/(w)  
0
0
r/(w)  
0:  
1:  
Show address of port 0 (offset)  
Show individual address of port x  
NOTE: r/ (w): write access depends on assignment of MI (ECAT/PDI). Write access is generally blocked if  
Management interface is busy (0x0510.15=1).  
Table 69: Register PHY Register Address (0x0513)  
ECAT  
PDI  
eset Value  
Bit  
Description  
4:0  
Address of PHY Register that shall be r/(w)  
read/written  
r/(w)  
0
7:5  
Reserved, write 0  
r/-  
-  
NOTE: r/ (w): write access depends on assignment of MI (ECAT/PDI). Wrccess illy blocked if  
Management interface is busy (0x0510.15=1).  
Table 70: Register PHY Data (0514:0515)  
ECA
PDI  
Reset Value  
Bit  
Description  
15:0  
PHY Read/Write Data  
/(w)  
r/(w)  
0
NOTE: r/ (w): write access depends oassignnt of MI (AT/PDI). Access is generally blocked if Management  
interface is busy (0x0510.15=1).  
Table 71: Registr MII Management ECAT Access State (0x0516)  
ECAT  
PDI  
Reset Value  
Bit  
Description  
0
r/-  
0
Access to MII nagemnt:  
r/(w)  
0:  
ECT enabs PDI takeover of MII  
magement control  
1:  
ECAT laims exclusive access to MII  
anageent  
7:1  
r/-  
0
write 0  
r/-  
NOTE: r/ (w): ccess is only possible if 0x0517.0=0.  
TMC8460 PRELIMINARY, CONFIDENTIAL TARGET, NON-RELEASE VERSION Datasheet (V014 / 2015-Aug-31)  
Table 72: Register MII Management PDI Access State (0x0517)  
ECAT  
PDI  
Reset Value  
Bit  
Description  
0
r/(w)  
0
Access to MII management:  
r/-  
0:  
1:  
ECAT has access to MII management  
PDI has access to MII management  
1
r/-  
0
Force PDI Access State:  
r/w  
0:  
1:  
Do not change Bit 517.0  
Reset Bit 517.0 to 0  
7:2  
r/-  
0
Reserved, write 0  
r/-  
NOTE: r/ (w): assigning access to PDI (bit 0 = 1) is only possible if 0x0516.0=0 and 0x0517.1=0, and if the SII  
EEPROM is loaded (0x0110[0]=1).  
Table 73: Register PHY Port y (port number y=0 to 3) Status (0x0518y)  
ECAT  
PDI  
set Value  
Bit  
Description  
0
Physical link status (PHY status register 1.2):  
r/-  
r/-  
0
0:  
No physical link  
1:  
Physical link detected  
1
Link status (100 Mbit/s, Full Duplex, r/-  
Autonegotiation):  
r/-  
0
0:  
1:  
No link  
Link detected  
2
3
Link status error:  
r/-  
r/-  
0
0
0:  
1:  
No error  
Link error, link inhibited  
/(w/clr)  
r/(w/clr)  
Read error:  
0:  
1:  
No read error occurred  
A read error has occurred  
Cleared by writing ny valto at ast one of  
the PHY Status Port y registe.  
Link partner error:  
4
5
r/-  
0
0
r/-  
0:  
1:  
No error dd  
Link parr  
r/(w/clr)  
PHY configurupdatd:  
r/(w/clr)  
0:  
No upde  
1:  
HY configuration was updated  
Cleared bwriting any value to at least one  
PHY Stus Port y registers.  
7:6  
r/-  
0
r/-  
NOTE: r/ (w): ccess depends on assignment of MI (ECAT/PDI).  
TMC8460 PRELIMINARY, CONFIDENTIAL TARGET, NON-RELEASE VERSION Datasheet (V014 / 2015-Aug-31)  
5.47 Parameter RAM (0x0580:0x05AB) for TMC8460 MFCIO Block Configuration  
The content of these registers can be automatically loaded from EEPROM after reset/power-up.  
Therefore, the configuration date in the EEPROM must contain a section with category 1 and the  
appropriate configuration vector.  
There are 44 MFCIO registers. Each byte configures one of the MFCIO registers.  
y is in the range of 0 to 43 and is used as offset with respect to address 0x0580.  
Table 74:MFCIO Register Configuration (0x0580+y)  
ECAT  
PDI  
Reset Value  
Bit  
3:0  
4
Description  
Update trigger selection fot  
r/w  
r/w  
Always  
0
0
0: ECAT mapping disabled, general read/write r/w  
access only via MFC CTRL SPI to/from MCU  
1: ECAT mapping enabled, general write access otherwis write  
when ‘1’ read,  
only from ECAT master using configured e  
syncmanager, always readable by MCU via MFC access  
CTRL SPI  
no when ‘0’  
7:5  
reserved  
0
TMC8460 PRELIMINARY, CONFIDENTIAL TARGET, NON-RELEASE VERSION Datasheet (V014 / 2015-Aug-31)  
5.48 FMMU (0x0600:0x06FF)  
Each FMMU entry is described in 16 Bytes from 0x0600:0x060F to 0x06F0:0x06FF.  
y is the FMMU index.  
The TMC8460-BI supports up to 6 FMMUs. Thus TMC8460-BI supports y=0…5.  
Table 75: FMMU Register overview  
Length  
(Byte)  
Register Address Offset  
Description  
+0x0:0x3  
+0x4:0x5  
+0x6  
4
2
1
1
2
1
1
1
3
Logical Start Address  
Length  
Logical Start bit  
Logical Stop bit  
Physical Start Address  
Physical Start bit  
Type  
+0x7  
+0x8:0x9  
+0xA  
+0xB  
+0xC  
Activate  
+0xD:0xF  
Reserved  
Table 76: Register Logical Start address FMMU y 0x06y0:0x06y3)  
ECA
PDI  
Reset Value  
Bit  
Description  
31:0  
Logical start address within ththerCAT /w  
Address Space.  
r/-  
0
Tae 77: Reister Lgth FMMU y (0x06y4:0x06y5)  
ECAT  
PDI  
Reset Value  
Bit  
Description  
15:0  
Offset from thgical MMU Byte to the r/w  
last FMMU Bye.g., f two bytes are used  
then this parer shacontain 2)  
r/-  
0
Tle 78: Register Start bit FMMU y in logical address space (0x06y6)  
ECAT  
PDI  
Reset Value  
Bit  
on  
2:0  
arting bit that shall be mapped (bits r/w  
aunted from least significant bit (=0) to  
mossignificant bit(=7)  
r/-  
0
7:3  
Reservd, write 0  
r/-  
r/-  
0
Table 79: Register Stop bit FMMU y in logical address space (0x06y7)  
ECAT  
PDI  
Reset Value  
Bit  
Description  
2:0  
Last logical bit that shall be mapped (bits are r/w  
counted from least significant bit (=0) to most  
significant bit(=7)  
r/-  
0
7:3  
Reserved, write 0  
r/-  
r/-  
0
 
 
 
 
TMC8460 PRELIMINARY, CONFIDENTIAL TARGET, NON-RELEASE VERSION Datasheet (V014 / 2015-Aug-31)  
Table 80: Register Physical Start address FMMU y (0x06y8-0x06y9)  
ECAT  
PDI  
Reset Value  
Bit  
Description  
15:0  
Physical Start Address (mapped to logical Start r/w  
address)  
r/-  
0
Table 81: Register Physical Start bit FMMU y (0x06yA)  
ECAT  
PDI  
Reset Value  
Bit  
Description  
2:0  
Physical starting bit as target of logical start r/w  
bit mapping (bits are counted from least  
significant bit (=0) to most significant bit(=7)  
r/-  
0
7:3  
Reserved, write 0  
r/-  
r/-  
0
Table 82: Register Type FMMU y (0x06yB)  
ECAT  
PDI  
Ret Value  
Bit  
Description  
0
r
0
0:  
1:  
Ignore mapping for read accesses  
Use mapping for read accesses  
r/w  
1
r/-  
r/-  
0
0
0:  
1:  
Ignore mapping for write accesses  
Use mapping for write accesses  
r/w  
r/-  
7:2  
Reserved, write 0  
Table 83: Register ctivaFMMU (0x06yC)  
CAT  
PDI  
Reset Value  
Bit  
Description  
0
r/-  
0
0:  
1:  
FMMU deactivated  
r/w  
FMMU activated. FMMU ches logical  
addressed bloks to bmapp
according to maping cofigure
7:1  
r/-  
0
Reserved, write 0  
r/-  
able 84Register Reserved FMMU y (0x06yD:0x06yF)  
ECAT  
PDI  
Reset Value  
Bit  
Descrion  
23:0  
Rerved, rite 0  
r/-  
r/-  
0
TMC8460 PRELIMINARY, CONFIDENTIAL TARGET, NON-RELEASE VERSION Datasheet (V014 / 2015-Aug-31)  
5.49 SyncManager (0x0800:0x087F)  
SyncManager registers are mapped from 0x0800:0x0807 to 0x0818:0x087F.  
y specifies the SyncManager number.  
The TMC8460-BI supports up to 6 SyncManagers. Thus TMC8460-BI supports y=0…5.  
Table 85: SyncManager Register overview  
Length  
(Byte)  
Register Address Offset  
Description  
+0x0:0x1  
+0x2:0x3  
+0x4  
2
2
1
1
1
1
Physical Start Address  
Length  
Control Register  
Status Register  
Activate  
+0x5  
+0x6  
+0x7  
PDI Control  
Table 86: Register physical Start Address SyncManagr y x08000801+y*8)  
ET  
PI  
Reset Value  
Bit  
Description  
15:0  
Specifies first byte that will be handled br/(w
SyncManager  
r/-  
0
NOTE r/(w): Register can only be written if SyncManagr is dabled (+x6.0 = 0).  
Table 87: Register Lenh SyncMager y (0x0802+y*8:0x0803+y*8)  
ECAT  
PDI  
Reset Value  
Bit  
Description  
15:0  
Number of bytes assned tSyncManager r/(w)  
(shall be greater 1, otherise SyncManager is  
not activated. to 1only Watchdog  
Trigger is geif configured)  
r/-  
0
NOTE r/(w): Register an onle writteif SyncManager is disabled (+0x6.0 = 0).  
 
 
TMC8460 PRELIMINARY, CONFIDENTIAL TARGET, NON-RELEASE VERSION Datasheet (V014 / 2015-Aug-31)  
Table 88: Register Control Register SyncManager y (0x0804+y*8)  
ECAT  
PDI  
Reset Value  
Bit  
Description  
1:0  
r/-  
00  
Operation Mode:  
r/(w)  
00: Buffered (3 buffer mode)  
01: Reserved  
10: Mailbox (Single buffer mode)  
11: Reserved  
3:2  
r/-  
00  
Direction:  
r/(w)  
00: Read: ECAT read access, PDI write  
access.  
01: Write: ECAT write access, PDI read  
access.  
10: Reserved  
11: Reserved  
4
5
6
7
r/-  
r/
r/-  
r/-  
0
0
0
Interrupt in ECAT Event Request Register:  
r/(w)  
r/(w)  
r/(w
r/-  
0:  
Disabled  
1:  
Enabled  
Interrupt in PDI Event Request Register:  
0:  
1:  
Disabled  
Enabled  
Watchdog Trigger Enable:  
0:  
1:  
Disabled  
Enabled  
Reserved, write 0  
NOTE r/(w): Register can only be written if SyncManagr is dabled (x6.0 = 0).  
TMC8460 PRELIMINARY, CONFIDENTIAL TARGET, NON-RELEASE VERSION Datasheet (V014 / 2015-Aug-31)  
Table 89: Register Status Register SyncManager y (0x0805+y*8)  
ECAT  
PDI  
Reset Value  
Bit  
Description  
0
r/-  
0
Interrupt Write:  
r/-  
1:  
Interrupt after buffer was completely  
and successfully written  
Interrupt cleared after first byte of  
buffer was read  
0:  
NOTE: This interrupt is signaled to the reading  
side if enabled in the SM Control register.  
1
r/-  
0
Interrupt Read:  
r/-  
1:  
Interrupt after buffer was completely  
and successful read  
0:  
Interrupt cleared after first byte of  
buffer was written  
NOTE: This interrupt is signaled to the writing side  
if enabled in the SM Control register.  
2
3
r
-  
0
Reserved  
r/-  
r/-  
Mailbox mode: mailbox status:  
0:  
Mailbox empty  
1:  
Mailbox full  
Buffered mode: reserved  
5:4  
Buffered mode: buffer status (last written  
buffer):  
r/-  
11  
r/-  
00: 1. buffer  
01: 2. buffer  
10: 3. buffer  
11: (no buffer written)  
Mailbox mode: reserved  
6
7
r/-  
r/-  
0
0
Read buffer in use opene
Write buffer in use (oened)  
r/-  
r/-  
TMC8460 PRELIMINARY, CONFIDENTIAL TARGET, NON-RELEASE VERSION Datasheet (V014 / 2015-Aug-31)  
Table 90: Register Activate SyncManager y (0x0806+y*8)  
ECAT  
PDI  
Reset Value  
Bit  
Description  
0
r/  
0
SyncManager Enable/Disable:  
r/w  
(w ack)*  
0:  
Disable: Access to Memory without  
SyncManager control  
1:  
Enable: SyncManager is active and  
controls Memory area set in  
configuration  
1
r/  
0
Repeat Request:  
r/w  
(w ack)*  
A toggle of Repeat Request means that a  
mailbox retry is needed (primarily used in  
conjunction with ECAT Read Mailbox)  
5:2  
6
r/  
0
Reserved, write 0  
r/-  
(w ack)*  
r/  
(w ack)*  
Latch Event ECAT:  
r/w  
0:  
1:  
No  
Generate Latch event if EtherCAT master  
issues a buffer exchange  
7
Latch Event PDI:  
r/w  
(w a
0:  
No  
1:  
Generate Latch events if PDI issues a  
buffer exchange or if PDI accesses  
buffer start address  
* PDI register function acknowledge by Write command is disabd: Readg this register from PDI in all  
SyncManagers which have changed activation clears AL nt Requt 0x0220[4]. Writing to this register from PDI  
is not possible.  
PDI register function acknowledge by Write comnd is enabd: Writing this register from PDI in all  
SyncManagers which have changed activation cars AEvent Request 0x0220[4]. Writing to this register from PDI  
is possible; write value is ignored (wite 0).  
TMC8460 PRELIMINARY, CONFIDENTIAL TARGET, NON-RELEASE VERSION Datasheet (V014 / 2015-Aug-31)  
Table 91: Register PDI Control SyncManager y (0x0807+y*8)  
ECAT  
PDI  
Reset Value  
Bit  
Description  
0
r/w  
0
Deactivate SyncManager:  
Read:  
r/-  
0:  
Normal operation, SyncManager  
activated.  
1:  
SyncManager deactivated and reset  
SyncManager locks access to Memory  
area.  
Write:  
0:  
1:  
Activate SyncManager  
Request SyncManager deactivation  
NOTE: Writing 1 is delayed until the end of a  
frame which is currently processed.  
1
r/w  
-  
Repeat Ack:  
r/-  
r/-  
If this is set to the same value as set by  
Repeat Request, the PDI acknowledges the  
execution of a previous set Repeat request.  
7:2  
Reserved, write 0  
5.50 Distributed Clocks (0x0900:0x09FF)  
5.50.1 Receive Times  
Table 92: Register Receive Port (0x0900:0x0903)  
ECAT  
PDI  
Reset Value  
Bit  
Description  
31:0  
r/-  
Undefined  
Write:  
r/w  
A write access to register 0900 wit
(special  
function)  
BWR or FPWR latchethe lol time of  
the beginning the reeive frme  
(start first bit of pambleat each port.  
Read:  
Local timbeginng of the last  
receive ontaning a write access  
to tis rter.  
NOTE: The time stas cannot be read in the same frame in which this register was written.  
Table 93: Register Receive Time Port 1 (0x0904:0x0907)  
ECAT  
PDI  
Reset Value  
Bit  
tion  
31:0  
r/-  
Undefined  
Locatime of the beginning of a frame (start  
first bit of preamble) received at port 1  
containing a BWR or FPWR to Register  
0x0900.  
r/-  
NOTE: Register 0x0910:0x0913[0x910:0x0917] is described in the next chapter.  
Table 94: Register Receive Time ECAT Processing Unit (0x0918:0x091F)  
 
TMC8460 PRELIMINARY, CONFIDENTIAL TARGET, NON-RELEASE VERSION Datasheet (V014 / 2015-Aug-31)  
ECAT  
PDI  
Reset Value  
Bit  
Description  
63:0  
r/-  
Undefined  
Local time of the beginning of a frame (start  
first bit of preamble) received at the ECAT  
Processing Unit containing a write access to  
Register 0x0900  
r/-  
NOTE: E.g., if port 0 is open, this register reflects  
the Receive Time Port 0 as a 64 Bit value.  
TMC8460 PRELIMINARY, CONFIDENTIAL TARGET, NON-RELEASE VERSION Datasheet (V014 / 2015-Aug-31)  
5.50.2 Time Loop Control Unit  
Time Loop Control unit is usually assigned to ECAT. Write access to Time Loop Control registers by  
PDI (and not ECAT) is only possible with explicit configuration.  
Table 95: Register System Time (0x0910:0x0913 [0x0910:0x0917])  
ECAT  
PDI  
Reset Value  
Bit  
Description  
63:0  
ECAT read access: Local copy of the System r  
Time when the frame passed the reference  
clock (i.e., including System Time Delay).  
Time latched at beginning of the frame  
(Ethernet SOF delimiter)  
-
0
63:0  
31:0  
PDI read access: Local copy of the System -  
Time. Time latched when reading first byte  
(0x0910)  
r
-
Write access: Written value will be compared  
with the local copy of the System time. The  
result is an input to the time control loop.  
(w)  
(special  
function)  
NOTE: written value will be compared at the end  
of the frame with the latched (SOF) local copy of  
the System time if at least the first byte (0x0910)  
was written.  
31:0  
Write access: Written value will be compred  
with Latch0 Time Positive Edge time. The  
result is an input to the time control loop.  
()  
(special  
function)  
-
NOTE: written value will be compared at the
of the access with Latch0 Time Positive Ege  
(0x09B0:0x09B3) if at least the last by0913)  
was written.  
NOTE: Write access to this register depens upon SC configuration (typically ECAT). The TMC8460-BI is not  
configured for this option.  
Table er Sysm Time Offset (0x0920:0x0923 [0x0920:0x0927])  
ECAT  
PDI  
Reset Value  
Bit  
Description  
63:0  
Differene betwen lcal time and System r/(w)  
Time. Oet is added to the local time.  
r/(w)  
0
NOTE: Writo thiegister depends upon ESC configuration (typically ECAT, PDI only with explicit ESC  
configuraTime PDI controlled). Reset internal system time difference filter and speed counter filter by  
writing SStart (0x0930:0x0931) after changing this value.  
TMC8460 PRELIMINARY, CONFIDENTIAL TARGET, NON-RELEASE VERSION Datasheet (V014 / 2015-Aug-31)  
Table 97: Register System Time Delay (0x0928:0x092B)  
ECAT  
PDI  
Reset Value  
Bit  
Description  
31:0  
Delay between Reference Clock and the ESC  
r/(w)  
r/(w)  
0
NOTE: Write access to this register depends upon ESC configuration (typically ECAT, PDI only with explicit ESC  
configuration: System Time PDI controlled). Reset internal system time difference filter and speed counter filter by  
writing Speed Counter Start (0x0930:0x0931) after changing this value.  
Table 98: Register System Time Difference (0x092C:0x092F)  
ECAT  
PDI  
Reset Value  
Bit  
Description  
30:0  
r/-  
0
Mean difference between local copy of  
System Time and received System Time  
values  
r/-  
31  
r/-  
0
0:  
Local copy of System Time greater than  
or equal received System Time  
Local copy of System Time smaller than  
received System Time  
r/-  
1:  
Table 99: Register Speed Counter Start (0x0930:0x931
ECA
PDI  
Reset Value  
Bit  
Description  
14:0  
Bandwidth for adjustment of local copof r()  
System Time (larger values smaller  
bandwidth and smoother adjustment)  
rw)  
0x1000  
A write access resets System Time Diffeence  
(0x092C:0x092F) and Speed Couner Df  
(0x0932:0x0933).  
Minimum value: 0x0080 to 0x3FFF  
15  
Reserved, write 0  
r/-  
r/-  
0
NOTE: Write access to this registdepenupon C configuration (typically ECAT, PDI only with explicit ESC  
configuration: System Time PDI conolled).  
100: Register Speed Counter Diff (0x0932:0x933)  
ECAT  
PDI  
Reset Value  
Bit  
Descripon  
15:0  
Represtation of the deviation between local r/-  
clock perid and Reference Clock’s clock period  
entatn: two’s complement)  
r/-  
0x0000  
Speed Counter Start 0x7F)  
NOTE: Calcuock deviation after System Time Difference has settled at a low value as follows:  
Speed Counter Diff  
Deviation  
(Speed Counter Start Speed Counter Diff 2)(Speed Counter Start Speed Counter Diff 2)  
TMC8460 PRELIMINARY, CONFIDENTIAL TARGET, NON-RELEASE VERSION Datasheet (V014 / 2015-Aug-31)  
Table 101: Register System Time Difference Filter Depth (0x0934)  
ECAT  
PDI  
Reset Value  
Bit  
Description  
3:0  
Filter depth for averaging the received System r/(w)  
r/(w)  
4
Time deviation  
TMC8460:  
A write access resets System Time Difference  
(0x092C:0x092F)  
7:4  
Reserved, write 0  
r/-  
r/-  
0
NOTE: Write access to this register depends upon ESC configuration (typically ECAT, PDI only with explicit ESC  
configuration: System Time PDI controlled).  
Table 102: Register Speed Counter Filter Depth (0x0935)  
ECAT  
PDI  
Rset lue  
Bit  
Description  
3:0  
Filter depth for averaging the clock period r/(w)  
r/(w)  
2  
deviation  
TMC8460:  
A write access resets the internal speed  
counter filter.  
7:4  
Reserved, write 0  
r/-  
r/-  
0
NOTE: Write access to this register depends upon ESC configuration ypically CAT, PDI only with explicit ESC  
configuration: System Time PDI controlled) .  
TMC8460 PRELIMINARY, CONFIDENTIAL TARGET, NON-RELEASE VERSION Datasheet (V014 / 2015-Aug-31)  
Table 103: Register Receive Time Latch Mode (0x0936)  
ECAT  
PDI  
Reset Value  
Bit  
Description  
0
Receive Time Latch Mode:  
r/-  
0
r/w  
0:  
Forwarding mode (used if frames are  
entering the ESC at port 0 first):  
Receive time stamps of ports 1-3 are  
enabled after the write access to  
0x0900, so the following frame at ports  
1-3 will be time stamped (this is  
typically the write frame to 0x0900  
coming back from the network behind  
the ESC).  
1:  
Reverse mode (used if frames are  
entering ESC at port 1-3 first):  
Receive time stamps of ports 1-3 are  
immediately taken over from the  
internal hidden time stamp registers, so  
the previous frame entering the ESC at  
ports 1-3 will be time stamped when  
the write frame to 0x0900 enters port 0  
(the previous frame at ports 1-3 is  
typically the write frame to 0x0900  
coming from the master, which will  
enable time stamping at the ESC once it  
enters port 0).  
7:1  
Reserved  
r
r/-  
0
NOTE: There should not be frames traveling around te netwobefore and after the time stamps are taken,  
otherwise these frames might get time stamped, nnot the wre frame to 0x0900.  
TMC8460 PRELIMINARY, CONFIDENTIAL TARGET, NON-RELEASE VERSION Datasheet (V014 / 2015-Aug-31)  
5.50.3 Cyclic Unit Control  
Table 104: Register Cyclic Unit Control (0x0980)  
ECAT  
PDI  
Reset Value  
Bit  
Description  
0
r/-  
0
SYNC out unit control:  
r/w  
0:  
1:  
ECAT controlled  
PDI controlled  
3:1  
4
r/-  
r/-  
0
0
Reserved, write 0  
Latch In unit 0:  
r/-  
r/w  
0:  
1:  
ECAT controlled  
PDI controlled  
NOTE: Always 1 (PDI controlled) if System Time is  
PDI controlled. Latch interrupt is routed to  
ECAT/PDI depending on this setting  
5
r/-  
r/-  
0
Latch In unit 1:  
r/w  
r/-  
0:  
1:  
ECAT controlled  
PDI controlled  
NOTE: Latch interrupt is routed to ECAT/PDI  
depending on this setting  
7:6  
Reserved, write 0  
TMC8460 PRELIMINARY, CONFIDENTIAL TARGET, NON-RELEASE VERSION Datasheet (V014 / 2015-Aug-31)  
5.50.4 SYNC Out Unit  
Table 105: Register Activation register (0x0981)  
ECAT  
PDI  
Reset Value  
Bit  
Description  
0
r/(w)  
0
Sync Out Unit activation:  
r/(w)  
0:  
1:  
Deactivated  
Activated  
1
2
3
r/(w)  
r/(w)  
r/(w)  
0
0
0
SYNC0 generation:  
r/(w)  
r/(w)  
r/(w)  
0:  
1:  
Deactivated  
SYNC0 pulse is generated  
SYNC1 generation:  
0:  
1:  
Deactivated  
SYNC1 pulse is generated  
Auto-activation by writing Start Time Cyclic  
Operation (0x0990:0x0997):  
0:  
1:  
Disabled  
Auto-activation enabled. 0x0981.0 is set  
automatically after Start Time is written.  
4
5
(w)  
r/(w)  
0
Extension of Start Time Cyclic Operation  
(0x0990:0x0993):  
r/(w)  
r/(w)  
0:  
1:  
No extension  
Extend 32 bit written Start Time to 64  
bit  
Start Time plausibility check:  
0:  
Disabled. SyncSignal generation if trt  
Time is reached.  
1:  
Immediate SyncSignal genertiif  
Start Time is outside near uture (e  
0x0981.6)  
6
7
r/(w)  
r/(w)  
0
0
Near future configation (pprox.)
0:  
1:  
r/(w)  
r/(w)  
½ DC width fute (231 nor 263 s)  
~2.1 sec. future (23s)  
SyncSignal debse (Valy bit):  
0:  
1:  
Deactiva
Immedigenere one ping only on  
SYC0-1 aording to 0x0981[2:1] for  
dugging  
This bit is self-clearing, always read 0.  
NOTE: Wrgister depends upon setting of 0x0980.0.  
Table 106: Register Pulse Length of SyncSignals (0x0982:0x983)  
ECAT  
PDI  
Reset Value  
Bit  
Description  
TMC8460: Depends on  
configuration, later  
EEPROM ADR 0x0002  
15:0  
Pulse length of SyncSignals (in Units of 10ns)  
r/-  
r/-  
0:  
Acknowledge mode: SyncSignal will be  
cleared by reading SYNC[1:0] Status  
register  
Table 107: Register Activation Status (0x0984)  
TMC8460 PRELIMINARY, CONFIDENTIAL TARGET, NON-RELEASE VERSION Datasheet (V014 / 2015-Aug-31)  
ECAT  
PDI  
Reset Value  
Bit  
Description  
0
r/-  
0
SYNC0 activation state:  
r/-  
0:  
1:  
First SYNC0 pulse is not pending  
First SYNC0 pulse is pending  
1
2
r/-  
r/-  
0
0
SYNC1 activation state:  
r/-  
r/-  
0:  
First SYNC1 pulse is not pending  
1:  
First SYNC1 pulse is pending  
Start Time Cyclic Operation (0x0990:0x0997)  
plausibility check result when Sync Out Unit  
was activated:  
0:  
1:  
Start Time was within near future  
Start Time was out of near future  
(0x0981.6)  
7:3  
Reserved  
r/-  
r/-  
0
Table 108: Register SYNC0 Status (0x098E)  
ECAT  
DI  
set Value  
Bit  
Description  
0
SYNC0 state for Acknowledge mode.  
SYNC0 in Acknowledge mode is cleared by  
reading this register from PDI, use only in  
Acknowledge mode  
r/-  
r/  
0
(w ac
7:1  
Reserved  
r/-  
r/  
0
(w ack)*  
* PDI register function acknowledge by Write commad is disaled: Reading this register from PDI clears AL  
Event Request 0x0220[2]. Writing to this register rom DI is not ssible.  
PDI register function acknowledge by Write ommans enabled: Writing this register from PDI clears AL Event  
Request 0x0220[2]. Writing to this register from PDI is posble; write value is ignored (write 0).  
Tabe 109: Rgister SYNC1 Status (0x098F)  
ECAT  
PDI  
Reset Value  
Bit  
Description  
0
SYNC1 state nowdge mode.  
SYNC1 Ackwledge mode is cleared by  
readinthis regier from PDI, use only in  
Acknowldge mode  
r/-  
r/  
0
(w ack)*  
7:1  
ed  
r/-  
r/  
0
(w ack)*  
* PDI regisacknowledge by Write command is disabled: Reading this register from PDI clears AL  
Event Reques20[3]. Writing to this register from PDI is not possible.  
PDI register fction acknowledge by Write command is enabled: Writing this register from PDI clears AL Event  
Request 0x0220[3]. riting to this register from PDI is possible; write value is ignored (write 0).  
Table 110: Register Start Time Cyclic Operation (0x0990:0x0993 [0x0990:0x0997])  
TMC8460 PRELIMINARY, CONFIDENTIAL TARGET, NON-RELEASE VERSION Datasheet (V014 / 2015-Aug-31)  
ECAT  
PDI  
Reset Value  
Bit  
Description  
63:0  
Write: Start time (System time) of cyclic r/(w)  
operation in ns  
r/(w)  
0
Read: System time of next SYNC0 pulse in ns  
NOTE: Write to this register depends upon setting of 0x0980.0. Only writable if 0x0981.0=0.  
Auto-activation (0x0981.3=1): upper 32 bits are automatically extended if only lower 32 bits are written within one  
frame.  
Table 111: Register Next SYNC1 Pulse (0x0998:0x099B [0x0998:0x099F])  
ECAT  
PDI  
Reset Vale  
Bit  
Description  
63:0  
System time of next SYNC1 pulse in ns  
r/-  
r/-  
0
Table 112: Register SYNC0 Cycle Time (0x09A0:0x09A3)  
ECAT  
PDI  
Reet Value  
Bit  
Description  
31:0  
Time between two consecutive SYNC0 pulses  
in ns.  
rw)  
0
r/(w)  
0:  
Single shot mode, generate only one  
SYNC0 pulse.  
NOTE: Write to this register depends upon setting of 0x0980.0.  
Table 113: Register SYN1 CyTime x09A4:0x09A7)  
CAT  
PDI  
Reset Value  
Bit  
Description  
31:0  
Time between SYNC1 pulses anSYNC0 ulse r/(w)  
in ns  
r/(w)  
0
NOTE: Write to this register depenupon tting o0x0980.0.  
TMC8460 PRELIMINARY, CONFIDENTIAL TARGET, NON-RELEASE VERSION Datasheet (V014 / 2015-Aug-31)  
5.50.5 Latch In unit  
Table 114: Register Latch0 Control (0x09A8)  
ECAT  
PDI  
Reset Value  
Bit  
Description  
0
r/(w)  
0
Latch0 positive edge:  
r/(w)  
0:  
1:  
Continuous Latch active  
Single event (only first event active)  
1
r/(w)  
0
0
Latch0 negative edge:  
r/(w)  
0:  
1:  
Continuous Latch active  
Single event (only first event active)  
7:2  
r/-  
Reserved, write 0  
r/-  
NOTE: Write access depends upon setting of 0x0980.4.  
Table 115: Register Latch1 Control (0x09A9)  
ECAT  
PDI  
eset Value  
Bit  
Description  
0
r/(w)  
r/(w
r/-  
0
Latch1 positive edge:  
r/(w)  
0:  
1:  
Continuous Latch active  
Single event (only first event active)  
1
0
0
Latch1 negative edge:  
r/(w)  
r/-  
0:  
1:  
Continuous Latch active  
Single event (only first event active)  
7:2  
Reserved, write 0  
NOTE: Write access depends upon setting of 0x0980.5.  
TMC8460 PRELIMINARY, CONFIDENTIAL TARGET, NON-RELEASE VERSION Datasheet (V014 / 2015-Aug-31)  
Table 116: Register Latch0 Status (0x09AE)  
ECAT  
PDI  
Reset Value  
Bit  
Description  
0
r/-  
r/-  
0
Event Latch0 positive edge.  
0:  
Positive edge not detected or  
continuous mode  
Positive edge detected in single event  
mode only.  
1:  
Flag cleared by reading out Latch0 Time  
Positive Edge.  
1
r/-  
r/-  
0
Event Latch0 negative edge.  
0:  
Negative edge not detected or  
continuous mode  
1:  
Negative edge detected in single event  
mode only.  
Flag cleared by reading out Latch0 Time  
Negative Edge.  
Latch0 pin state  
Reserved  
2
7:3  
r/-  
r/-  
r/-  
r/
0
0
Table 117: Register Latch1 Status (AF)  
ECT  
PI  
Reset Value  
Bit  
Description  
0
r/-  
r/-  
0
Event Latch1 positive edge.  
0:  
Positive edge not detected or  
continuous mode  
1:  
Positive edge detected in single event  
mode only.  
Flag cleared by reading out Latch1 Time  
Positive Edge.  
1
r/-  
r/-  
0
Event Latch1 negave edg
0:  
Negative edge nt deteced or  
continuous mode  
1:  
Negative eddetectin single event  
mode o
Flag cleared readig out Latch1 Time  
NegativEdge
Latch1 n state  
Reserved  
2
7:3  
r/-  
r/-  
r/-  
r/-  
0
0
TMC8460 PRELIMINARY, CONFIDENTIAL TARGET, NON-RELEASE VERSION Datasheet (V014 / 2015-Aug-31)  
Table 118: Register Latch0 Time Positive Edge (0x09B0:0x09B3 [0x09B0:0x09B7])  
ECAT  
PDI  
Reset Value  
Bit  
Description  
63:0  
Register captures System time at the positive r(ack)/-  
edge of the Latch0 signal.  
r/  
0
(w ack)*  
NOTE: Register bits [63:8] are internally latched (ECAT/PDI independently) when bits [7:0] are read, which  
guarantees reading a consistent value. Reading this register from ECAT clears Latch0 Status 0x09AE[0] if  
0x0980.4=0. Writing to this register from ECAT is not possible.  
* PDI register function acknowledge by Write command is disabled: Reading this register from PDI if 0x0980.4=1  
clears Latch0 Status 0x09AE[0]. Writing to this register from PDI is not possible.  
PDI register function acknowledge by Write command is enabled: Writing this register from PDI if 0x0980.4=1  
clears Latch0 Status 0x09AE[0]. Writing to this register from PDI is possible; write value is ignored (write 0).  
Table 119: Register Latch0 Time Negative Edge (0x09B8:0x09BB [0x09B8:0x09BF]
ECAT  
PDI  
eset Value  
Bit  
Description  
63:0  
Register captures System time at the negative r(ack)/-  
edge of the Latch0 signal.  
r/  
0
(w ack)
NOTE: Register bits [63:8] are internally latched (ECAT/PDI independently) when bits [ead, which  
guarantees reading a consistent value. Reading this register from ECAT clears Latch0x09AE[1] if  
0x0980.4=0. Writing to this register from ECAT is not possible.  
* PDI register function acknowledge by Write command is disable: eading thregister from PDI if 0x0980.4=1  
clears Latch0 Status 0x09AE[1]. Writing to this register from PDI is nopossible.  
PDI register function acknowledge by Write command is enled: Wrng this register from PDI if 0x0980.4=1  
clears Latch0 Status 0x09AE[1]. Writing to this register from PDI is possiblwrite value is ignored (write 0).  
TMC8460 PRELIMINARY, CONFIDENTIAL TARGET, NON-RELEASE VERSION Datasheet (V014 / 2015-Aug-31)  
Table 120: Register Latch1 Time Positive Edge (0x09C0:0x09C3 [0x09C0:0x09C7])  
ECAT  
PDI  
Reset Value  
Bit  
Description  
63:0  
Register captures System time at the positive r(ack)/-  
edge of the Latch1 signal.  
r/  
0
(w ack)*  
NOTE: Register bits [63:8] are internally latched (ECAT/PDI independently) when bits [7:0] are read, which  
guarantees reading a consistent value. Reading this register from ECAT clears Latch0 Status 0x09AF[0] if  
0x0980.5=0. Writing to this register from ECAT is not possible.  
* PDI register function acknowledge by Write command is disabled: Reading this register from PDI if 0x0980.5=1  
clears Latch0 Status 0x09AF[0]. Writing to this register from PDI is not possible.  
PDI register function acknowledge by Write command is enabled: Writing this register from PDI if 0x0980.5=1  
clears Latch0 Status 0x09AF[0]. Writing to this register from PDI is possible; write value is ignored (write 0).  
Table 121: Register Latch1 Time Negative Edge (0x09C8:0x09CB [0x09C8:0x09CF])  
ECAT  
PDI  
eset Value  
Bit  
Description  
63:0  
Register captures System time at the negative r(ack)/-  
edge of the Latch1 signal.  
r/  
0
(w ack)
NOTE: Register bits [63:8] are internally latched (ECAT/PDI independently) when bits [ead, which  
guarantees reading a consistent value. Reading this register from ECAT clears Latch0x09AF[1] if  
0x0980.5=0. Writing to this register from ECAT is not possible.  
* PDI register function acknowledge by Write command is disable: eading thregister from PDI if 0x0980.5=1  
clears Latch0 Status 0x09AF[1]. Writing to this register from PDI is nopossible.  
PDI register function acknowledge by Write command is enled: Wrng this register from PDI if 0x0980.5=1  
clears Latch0 Status 0x09AF[1]. Writing to this register from PDI is possiblwrite value is ignored (write 0).  
TMC8460 PRELIMINARY, CONFIDENTIAL TARGET, NON-RELEASE VERSION Datasheet (V014 / 2015-Aug-31)  
5.50.6 SyncManager Event Times  
Table 122: Register EtherCAT Buffer Change Event Time (0x09F0:0x09F3)  
ECAT  
PDI  
Reset Value  
Bit  
Description  
31:0  
Register captures local time of the beginning r/-  
of the frame which causes at least one  
SyncManager to assert an ECAT event  
r/-  
0
NOTE: Register bits [31:8] are internally latched (ECAT/PDI independently) when bits [7:0] are read, which  
guarantees reading a consistent value.  
Table 123: Register PDI Buffer Start Event Time (0x09F8:0x09FB)  
ECAT  
PDI  
ResValue  
Bit  
Description  
31:0  
Register captures local time when at least one r/-  
SyncManager asserts an PDI buffer start event  
r/-  
NOTE: Register bits [31:8] are internally latched (ECAT/PDI independently) when bits [7:re read, which  
guarantees reading a consistent value.  
Table 124: Register PDI Buffer Chnge EvnTime (0x0FC:0x09FF)  
ECAT  
PDI  
Reset Value  
Bit  
Description  
31:0  
Register captures local time when at least one r
SyncManager asserts an PDI buffer chane  
event  
r/-  
0
NOTE: Register bits [31:8] are internally latched CAT/PDI inependently) when bits [7:0] are read, which  
guarantees reading a consistent alue.  
TMC8460 PRELIMINARY, CONFIDENTIAL TARGET, NON-RELEASE VERSION Datasheet (V014 / 2015-Aug-31)  
5.51 ESC Specific Product and Vendor ID  
Table 125: Register Product ID (0x0E00:0x0E07)  
ECAT  
PDI  
Reset Value  
Bit  
Description  
TMC8460:  
0x0000 0000 0100 8460  
63:0  
Product ID  
r/-  
r/-  
Table 126: Register Vendor ID (0x0E08:0x0E0F)  
ECAT  
PDI  
Reset Value  
Bit  
Description  
TMC8460:  
0x0000 0286  
31:0  
r/-  
r/-  
Vendor ID:  
NOTE: Test Vendor IDs have [31:28]=0xE  
63:32  
Reserved  
r/-  
r/-  
5.52 User RAM (0x0F80:0x0FFF)  
Table 127: User RAM (0x0F80:00FFF)  
ET  
PD
Reset Value  
Bit  
Description  
TMC8460:  
Random/undefined  
----  
Application specific information  
r/w  
r/w  
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5.53 Process Data RAM (0x1000:0xFFFF)  
The Process Data RAM starts at address 0x1000. The TMC8460 Process Data RAM has a size of 16kBytes.  
Table 128: Process Data RAM (0x1000:0x4FFF)  
ECAT  
PDI  
Reset Value  
Bytes Description  
---- Process Data RAM  
(r/w)  
(r/w)  
Random/undefined  
NOTE (r/w): Process Data RAM is only accessible if EEPROM was correctly loaded (register 0x0110.0 = 1).  
Two constant memory blocks are used for data to and from the MFCIO block when at least one register  
is enabled.  
The first block from 0x4000 to 0x405F contains the data to be written into the MFCIO block, thsecond  
block from 0x4800 to 0x4823 contains data read from the MFCIO block.  
For compatibility, 2 byte registers are placed at even addresses, 4 and 8 byte rgisters are plaed at  
addresses 0x…0, 0x…4, 0x…8 or 0x…C. To match these offsets, padding bytes are aded in a few pces.  
Data written to these padding bytes in the first memory block are ignoredhe pading bytes the  
second block read 0x00.  
To use this data, SyncManagers (SM) should be set up. For simplicity, one be set up for each  
memory area to span the whole area. In case only a few registeare usSM can span just the  
area that is actually used.  
Examples for SM using only smaller memory chunks are showin the net two segments  
5.53.1 MFCIO Block ECAT Write Data Memory lock 0x4000x405F)  
Data in this memory block is written by the ECAmaster to the MFCIO block.  
Table 129: MFCIO Block ECT Write Da Memory Block (0x4000:0x405F)  
Se  
(bytes
Start  
Address  
0x4000  
MFCIO Register Name  
2
4
8
2
1
1
4
4
2
2
1
2
2
1
1
2
2
ENC_MODE  
ENC_X  
0x4004  
0x4008  
0x40C  
0x40
4016  
7  
1C  
0020  
0x4022  
0x4024  
0x4026  
0x4028  
0x402A  
0x402B  
0x402C  
0x402E  
ENC_CONST  
SPI_TX_DATA  
SPI_CONF  
SPI_LENGTH  
SPI_TIME  
SD_SR  
SD_ST  
SD_SL  
SD_DLY  
SD_CFG  
PWM_MAXCNT  
PWM_CHOPMODE  
PWM_ALIGNMENT  
PWM_POLARITIES  
PWM_VALUE_0  
PWM_VALUE_1  
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Size  
(bytes)  
Start  
Address  
0x4030  
0x4032  
0x4034  
0x4036  
0x4038  
MFCIO Register Name  
2
2
2
2
2
2
1
1
1
2
1
2
4
1
8
4
4
PWM_VALUE_2  
PWM_CNTRSHIFT_0  
PWM_CNTRSHIFT_1  
PWM_CNTRSHIFT_2  
PWM_PULSE_A  
PWM_PULSE_B  
PWM_PULSE_LENGTH  
PWM_BBM_H  
PWM_BBM_L  
0x403A  
0x403C  
0x403D  
0x403E  
0x4040  
0x4042  
0x4044  
0x4048  
0x404C  
0x4050  
0x4058  
0x405C  
GPO_OUT_VAL  
GPIO_CONFIG  
IRQ_CFG  
WD_TIME  
WD_CFG  
WD_OUT_MASK_POL  
WD_OE_POL  
WD_IN_MASK_POL  
Table 130: Padding byte
Number
paddig byte
Start  
Address  
0x4002  
0x4025  
0x403F  
0x4043  
0x4046  
0x4D  
2
1
1
1
2
3
Example:  
To use only the PWM ualler SM can be set up with a start address of 0x4026 and a size of 25  
bytes.  
5.53.2 MFCIO BlocECAT Read Data Memory Block (0x4800:0x4823)  
Data in y block is written by the MFCIO block and read by the ECAT master.  
Table 131: MFCIO Block ECAT Read Data Memory Block (0x4800:0x4823)  
Size  
(bytes)  
Start  
Aress  
0x4800  
MFCIO Register Name  
1
ENC_STATUS  
0x4804  
0x4808  
0x480C  
0x4814  
0x4818  
0x481C  
0x481E  
0x4820  
4
4
8
1
4
1
2
4
ENC_X  
ENC_LATCH  
SPI_RX_DATA  
SPI_STATUS  
SD_SC  
GPI_IN_VAL  
IRQ_FLAGS  
WD_MAX  
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Table 132: Padding bytes  
Number of  
padding bytes  
Start  
Address  
0x4801  
0x4815  
0x481D  
3
3
1
Example:  
When only the encoder position (ENC_X) is required via EtherCAT, a SyncManager starting at 0x4804 with  
a length of 4 bytes can be set up.  
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6 EtherCAT Technology  
This section briefly describes some aspects of the EtherCAT technology. For detailed information on the  
EtherCAT technology, its core mechanisms, and major features we refer to the official standards,  
documentations, and guidelines available from ETG (www.ethercat.org, ETG.1000), IEC (http://www.iec.ch,  
standard numbers see below), and Beckhoff (http://www.beckhoff.de, technical specification).  
6.1 General Information on EtherCAT  
EtherCAT (Ethernet in Control and Automation Technology) has been developed and patented by  
Beckhoff. It was introduced 2003 at the Hannover Messe, Germany.  
EtherCAT is an Ethernet-based technology for data transmission in real time. All process data for all  
nodes are transmitted in a single frame. All nodes connected to the bus interpret, process, nd modify  
their data „on the fly“. Ethernet frames are not buffered inside but are directly forwarded with minimum  
additional delay inside a node. A single frame spans multiple or all nodes at the ame tie. Data  
exchange is done via mail boxes mechanisms and PDOs (Process Data Objects) hile a stict aster-  
slave communication is maintained.  
To ensure real-time behavior the frame processing and forwarding requirs secial hadware. It cnnot  
be done in software on typical microcontrollers. This special hardwais caESC (EtherCAT Slave  
Controller) like the Trinamic TMC8460, TMC8461, or TMC8462.  
EtherCAT does not require software interaction for data transmission insilaves. EtherCAT only  
defines the MAC layer (similar to CAN). Higher layer protcols e imented in software on  
microcontrollers connected to the ESC.  
The ETG takes care for standardization activities and conormantesting. EtherCAT is integrated into  
the following major standards: IEC 61158 (protocols and seices), IC 61784-2 (communication profiles  
for devices), IEC 61800-7 (drive profiles and comunicion), SMI standard E54.20 (since 2007).  
6.2 Major EtherCAT Mechanisms  
6.2.1  
EtherCAT State Machine ESM)  
The ESM is used for control and coordination of the application on master side and slave side. The ECAT  
master requests state changes which re cheed and processed by the local application controller.  
Especially at startup, certain costraints and requirements must be fulfilled before switching to  
Operation state (OP).  
In device emulation moter reuests are directly acknowledged and applied within the ESC  
without being verified application controller. The following diagram shows the possible state  
machine transitions.  
Init  
(IB)  
(BI)  
(IP)  
(SI)  
(PI)  
Bootstrap /  
optional  
Pre-Operational  
(OI) (OP)  
(PS)  
Safe-Operational  
(SP)  
(OS)  
(SO)  
Operational  
Figure 28 - EtherCAT state machine  
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Each state and state transition has a specific function, requirements and constraints as shown in the  
next table.  
Table 133 - ESM states and transitions  
State / Transition  
Description  
INIT  
No communication on Application Layer  
Master has access to the DL-Information registers  
Master configures registers, at least:  
INIT TO PREOP  
- DL Address register  
- SyncManager channels for Mailbox communication  
Master initializes DC clock synchronization  
Master requests „Pre-Operationalstate  
- Master sets AL Control register  
Wait for AL Status register confirmation  
Mailbox communication on the Application Layer  
No Process Data communication  
PREOP  
PREOP TO SAFEOP  
Master configures parameters using the Mailbox:  
- e.g., Process Data Mapping  
Master configures DL Register:  
- SyncManager channels for Process Data commnica
- FMMU channels  
Master requests „Safe-Operationalstat
Wait for AL Status register confirmatio
Mailbox communication on the Applicatn Layer  
Process Data communication, but nly Inpts are evaluated –  
Outputs remain in „Safestate  
SAFEOP  
SAFEOP TO OP  
Master sends valid Outpus  
Master requests „Operainalstate AL Control/Status)  
Wit for AL Status reister cnfirmation  
Inputs and Outputre valid  
OP  
BOOT  
Optional, but ecommnded if firmware updates are necessary.  
State chnges oy from and to INIT  
No Process Data comunication  
Mailbox communication on Application Layer, only FoE protocol available  
Spilbox onfiguration possible  
Important ESM regsters arhighlghted below. For details, see section 5.  
Register  
Name  
Description  
0x0120:
0x013
0x0134:0
0x0140.8  
AL Control  
AL Status  
AL Status Code  
PDI Control  
Requested state by the master  
AL Status of the slave application  
Error codes from the slave application  
Device emulation configuration  
6.2.2  
EtherCAT Slave Controller RAM / Process Data RAM (PDRAM)  
An ESC has an address space of up to 64Kbyte which is divided into 4 Kbyte used for configuration and  
control registers primarily and up to 60Kbyte used as Process Data RAM. See Section 5 for details on  
the ESC registers.  
The TMC8460 has an internal PDRAM of 16KBytes. The PDRAM is used for all data exchanged between  
the EtherCAT master and the local slave application.  
For reasons of data consistency, synchronized communication, and address mapping additional  
mechanisms like SyncManagers and FMMUs apply.  
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110  
0x0000  
ESC  
Registers  
0x0FFF  
0x1000  
ESC Process  
Data RAM  
0x4FFFF  
Figure 29 - TMC8460 RAM Structure  
6.2.3  
Fieldbus Memory Management Unit (FMMU)  
A single EtherCAT bus has a logical 4 Gbyte address space (process image) which is shared by all  
devices/slaves connected to this bus. Since a slave has only a 4 Kbyte address space a mapping is  
required. So-called FMMUs map addresses from the global ogical ddress space to the local physical  
address space of a single slave. The EtherCAT mater cnfigurFMMUs after startup. FMMUs cannot be  
programmed by the EEPROM configuration data. he FMMconfiguration registers are described in detail  
in section 5.48.  
Each ESC supports a certain number of indpendent FMMUs channels. TMC8460 supports 6 FMMUs for  
example, TMC8461 and TMC842 suppt 8 FMUs.  
6.2.4  
SyncManagers (SM)  
Since the PDRAM of an shared medium provisions are required to control data read and write  
operations. SyncManagemechnisms used to ensure reliable consistent and secure data exchange  
between EtherCAT master nd slavdevices.  
SMs can be confied in various ways: communication direction, mode, size. The master configures all  
SMs at startup similto FMMU configuration. The SM configuration registers are described in detail in  
section 5.
6.2.5  
Clocks (DC)  
The concept Distributed Clocks is the most powerful mechanism of the EtherCAT technology to  
support real-time behavior for an application, especially when multiple slaves are connected to the  
EtherCAT bus.  
All DC configuration registers are described in detail in section 5.50.  
6.3 TMC8460-specific EtherCAT Features  
The TMC8460 is based on the proven EtherCAT engine available with Beckhoff IP cores. For detailed  
information on EtherCAT features such as the EtherCAT protocol, FMMUs, SyncManagers, Distributed  
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Clocks, Watchdog, and other we refer to the official EtherCAT technology and IP core documentation  
available at Beckhoff (http://www.beckhoff.de/default.asp?ethercat/ec_ipcore_overview.htm).  
The TMC8460 comes with a specific set of enabled/disabled EtherCAT-related features and registers. The  
following list provides information on this.  
2 MII ports  
o
o
o
o
o
Lost link counters enabled (see registers 0x0310:0x0313)  
MII management interface enabled (see register 0x0510)  
Enable enhanced link detection for MII enabled  
PDI support for MII management interface enabled  
Automatic MII TX shift enabled (to use automatic TX shift set all external MII_TX_SHIFT inputs to  
zero)  
o
Link detection and configuration for MII disabled  
6 FMMU  
6 Sync Managers  
64 bit Distributed Clocks  
o DC sync units enabled  
o DC latch units enabled  
o Cyclic pulse length is 20ns  
o The SYNC0 and SYNC1 signals can be mapped to the PDI_IQ si
LEDs  
o RUN led enabled  
o STATE led enabled  
o ERR led enabled  
o LINK/ACT leds per MII port enabled  
16 Kbyte ESC RAM size  
External I²C EEPROM  
o Configurable EEPROM size enabled (sing pin ROM_SIZE)  
o
Parameter loading to 0x0580 enaled (rquired for MFCIO block configuration data)  
SPI PDI interface  
o Configurable SPI modes enabled  
7 MFCIO Block Register and Functional Description  
7.1 MFCIO Block Gl Information  
The MFCIO block ia sepate indpendent function block next to the main ESC data path. It connects  
to the ESC via a cofiguration interface and a memory bridge. It comes with its own SPI interface (MFC  
CTRL SPI) to connect o an application controller. Detailed information on the SPI interface protocol and  
characteriven isection 2.3.  
Besideration interface and the memory bridge the MFCIO block uses various status and  
control sing from the ESC.  
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0x0000  
0x0580-0x05FF  
Standard ESC  
Registers  
Register 0  
Register 1  
Register 2  
ABN  
PWM  
SPI  
Config  
0x0FFF  
0x1000  
Configurable  
from:  
EEPROM,  
PDI, ECAT  
Memory Bridge  
ESC Procs  
Data RAM  
Memory Block 0  
starting @ 0x4000  
Watch-  
dog  
Memory Block 1  
starting @ 0x4800  
System  
CTRL  
Register X  
EC  
Block  
MFC IO  
Block  
Register Bank  
0x4FFFF  
PDI SPI  
MFC CTRL SPI  
Figure 30 - MFCIO block interfaces tESC PDRA
The MFCIO block and its functions are based on the register sesummarized in 7.2.  
Which functional unit is used and which not depends on he appcation. All functions have dedicated  
IO pins on the TMC8460 and can be used at in parel.  
The MFCIO block can be accessed by the Ethermaster ad by a local MCU at the same time. However,  
a single register of the MFCIO block can baccesed either only by the ECAT interface or only by the  
MFC CTRL SPI interface.  
The access rights as well as the updae triggr source for all registers are configurable on a per register  
base. The configuration of the FCIO aess rigts and update trigger sources is located in the ESC RAM  
at addresses 0x0580:0x05FF (ESC Pameter RAM). This configuration data is made available to the MFCIO  
block using the configuration interfae.  
If an MFCIO register is ced to be accessed by the ECAT interface, it is directly mapped to a fixed  
position in a memoy blin the DRAM using the memory bridge.  
Two memory blocs (MB0 d MB) are defined in the PDRAM one for writable registers and one for  
read-only registers to have continuous memory regions for which SyncManagers can be configured  
to care for, e.g., data onsistency.  
The MFontents of all readable registers that can be accessed from ECAT interface are only  
updated il state of the EtherCAT state machine is SAFEOP or OP.  
The MFCIO rter contents of all writable registers that can be accessed from ECAT interface are only  
updated if the tual state of the EtherCAT state machine is OP.  
All functional output signals of the MFCIO block are linked to the OP state of the EtherCAT state machine.  
As long as the actual state is not OP, all functional output states are not driven but in high impedance  
state.  
7.2 MFCIO Block Address Space Overview  
The MFCIO block provides functionality useful in an embedded system with focus on motor and motion  
control.  
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Table 134 : MFCIO Block Register Overview  
Memory  
Block 0  
Address  
Memory  
Block 1  
Address  
Configuration Configuration  
Reg.  
no.  
Data  
size  
Register name  
MFC block R/W  
address  
address  
(EEPROM)  
(PDRAM)  
(PDRAM) (PDRAM)  
0
1
2
3
4
5
6
7
ENC_MODE  
ENC_STATUS  
ENC_X  
ENC_X  
ENC_CONST  
W
R
W
R
W
R
R
W
W
R
W
W
W
R
W
W
W
W
W
W
W
W
W
W
W
W
W
W
W
W
W
W
W
R
W
W
R
W
W
W
W
W
R
0x0084  
0x0085  
0x0086  
0x0087  
0x0088  
0x0089  
0x008A  
0x008B  
0x008C  
0x008D  
0x008E  
0x008F  
0x0090  
0x0091  
0x0092  
0x0093  
0x0094  
0x0095  
0x0096  
0x0097  
0x098  
0x0099  
0x009A  
009B  
0x00
0x009D  
0x009E  
009F  
0x00A0  
0x00A1  
0x00A2  
0x00A3  
0x00A4  
0x00A5  
0x00A6  
0x00A7  
0x00A8  
0x00A9  
0x00AA  
0x00AB  
0x00AC  
0x00AD  
0x00AE  
0x00AF  
-
0x0580  
0x0581  
0x0582  
0x0583  
0x0584  
0x0585  
0x0586  
0x0587  
0x0588  
0x0589  
0x058A  
0x058B  
0x058C  
0x058D  
0x058E  
0x058F  
0x059
0x0591  
592  
0x05
0x0594  
0x0595  
0596  
0x0597  
0x0598  
0x0599  
0x059A  
0x059B  
0x059C  
0x059D  
0x059E  
0x059F  
0x05A0  
0x05A1  
0x05A2  
0x05A3  
0x05A4  
0x05A5  
0x05A6  
0x05A7  
0x05A8  
0x05A9  
0x05AA  
0x05AB  
-
0x4000  
-
0x4004  
-
0x4008  
-
-
2
1
4
4
4
4
8
8
2
1
1
1
4
4
4
2
2
1
2
2
1
1
2
2
2
2
2
2
2
2
1
1
1
2
1
1
2
2
4
1
8
4
4
4
1
0x4800  
-
ABN-  
Decoder  
0x4804  
-
ENC_LATCH  
0x4808  
0x480C  
SPI_RX_DATA  
SPI_TX_DATA  
SPI_CONF  
SPI_STATUS  
SPI_LENGTH  
SPI_TIME  
-
0x400C  
0x4014  
-
0x4016  
0x40
0x08  
-
-
-
8
9
SPI-  
Master  
0x481
10  
11  
12  
13  
14  
15  
16  
17  
18  
19  
20  
21  
22  
23  
24  
25  
26  
27  
28  
29  
30  
31  
32  
33  
34  
35  
36  
37  
38  
39  
40  
41  
42  
43  
44  
-
-
SD_SR  
SD_SC  
SD_ST  
SD_SL  
SD_DLY  
SD_CFG  
0x4818  
0x401C  
020  
2  
4  
26  
0x4028  
0x402A  
0x402B  
0x402C  
0x402E  
0x4030  
0x4032  
0x4034  
0x4036  
0x4038  
0x403A  
0x403C  
0x403D  
0x403E  
0x4040  
-
0x4042  
0x4044  
-
0x4048  
0x404C  
0x4050  
0x4058  
0x405C  
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
Step/Dir-  
Generator  
PWM_MAXCNT  
PWM_CHOPMODE  
PWM_ALIGNMENT  
PWM_POLARITIES  
PWM_VALUE_0  
PWM_VALUE_1  
PWM_VALUE_2  
PWM_CNTRSHIFT_0  
PWM_CNTRSHIFT_1  
PWM_CNTRSHIFT_2  
PWM_PULSE_A  
PWM_PULSE_B  
PWM_PULSE_LENGTH  
PWM_BBM_H  
PWM_BBM_L  
GPO_OUT_VAL  
GPI_IN_VAL  
GPIO_CFIG  
IR_FG  
3-ch PWM  
-
-
-
-
GPI
0x481C  
-
-
MIO-  
IRQ  
IRQ_FGS  
WD_TIM
CFG  
0x481E  
-
-
-
-
GPIO-  
Watch-  
dog  
SK_POL  
POL  
WASK_POL  
D_MAX  
-
0x4820  
-
AL_STATEOVERRIDE  
Override  
W
-
The table above gives an overview of all MFCIO block registers. Read-only registers are marked blue,  
registers that are writable (write-only via EtherCAT) are marked red.  
The register number (Reg. No.) is required for addressing registers via the MFC CTRL SPI interface. When  
using EtherCAT access, this is not necessary.  
The column Configuration address (EEPROM) shows the location where each registers configuration byte  
is stored in the EEPROM. For the full EEPROM map, see 7.3.  
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On startup, the EEPROM configuration is copied into the PDRAM, starting at address 0x0580. The address  
for each register is shown in the column Configuration address (PDRAM). The configuration for a register  
can be changed in this address space. If no configuration is stored in the EEPROM, the MCU or the  
EtherCAT master can set the configuration.  
The data to be written to the registers and the data read from the registers can be found at the  
addresses given in the Memory Block x Address (PDRAM) columns. These addresses are used for EtherCAT  
access. When accessing the PDRAM, the MFCIO block has the same behavior as an external MCU, so  
when SyncManagers are set up on the two memory blocks, an MCU does not have access to these  
regions using the PDI SPI interface.  
All registers can be read at any time via the MFC CTRL SPI, if EtherCAT access for a writable register is  
disabled, this register can also be written via the MFC CTRL SPI.  
The register 44 (AL_STATE_OVERRIDE) has a special function and can only be accesd via MC CRL SPI.  
Usually the outputs of the MFCIO block are only active when the EtherCAT slave iin operational state.  
With this register they can be activated regardless of the EtherCAT state.  
The base addresses of the two memory blocks are fix and this portion f the AM can only be used  
for MFCIO data when MFCIO registers are configured for ECAT access.  
The memory blocks should be managed by SyncManagers, which must be red separately using  
the ESC’s configuration options.  
7.3 MFCIO Block EEPROM Parameter Map  
The configuration data for the MFCIO block registern be stred in the I2C EEPROM to be automatically  
loaded into the ESC after power-up or after rese.  
This configuration category must be the first e EEPROlocated at address 0x0080 (word 0x40). The  
category type must be 1 so that the TMC8460 loadthe configuration into the memory area starting at  
0x0580.  
This section describes the part of thEEPRM content and XML/ESI file that is used to configure the  
MFCIO block registers.  
Table 135 : EEPROM Paramap & SC RAM Address Mapping for TMC8460-BI  
EEPROM Address  
Fnction  
Value  
GneraategorInformation (Values must not be changed)  
0x0080:0x0081  
0x0082:0x0083  
Ctegory Type  
Category Data Size  
0x0001  
0x002C  
MFCIO Register Configuration  
0x008
0x00
0x0090:
0x0096:0x04  
0x00A5:0x00A
0x00A8:0x00A9  
0x00AA:0x00AF  
Encoder Unit Registers  
SPI Unit Registers  
Step/Direction Unit Registers  
PWM Unit Registers  
Depends on the required configuration,  
0x00 for unused registers.  
See sections 7.4 for details  
General Purpose I/O Unit Registers  
MFCIO IRQ Registers  
MFCIO Watchdog Registers  
7.4 MFCIO Register Configuration  
Each register of the MFCIO block can be configured using an 8-bit EEPROM entry. Sections 7.2 and 7.3  
provide information on the individual EEPROM addresses for configuring each MFCIO block register.  
The following parameters and syntax are used for every MFCIO register for configuration.  
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Table 136 - MFCIO register configuration byte  
bit  
7
6
5
4
3
2
1
0
function  
Unused / reserved  
Enable  
ECAT  
Shadow trigger source  
access  
MFCIO block registers have 2 stages a bank of shadow registers and the main registers.  
When writing or reading data to/from the MFCIO block register there is always a shadow register in  
between. The shadow registers always hold the latest data written by the MFCIO block or by the ECAT  
interface. The content of the shadow registers is copied to the main register depending upon  
configurable trigger sources.  
Bits 3..0 define the when the transfer between a shadow register and the main register of e MFCIO  
unit happens. For write registers the data is copied from the shadow register into the FC unit egister,  
for read registers, the data is copied from the MFC unit register into the shadow rister. Eah MC unit  
register has a corresponding shadow register.  
For write registers, Bit 4 determines whether the register will be accessed from thECAT master ) or  
from the MFC CTRL SPI interface (0). Only one interface can write.  
For read registers, Bit 4 determines whether the register is also copid to PM to be read by the  
ECAT master.  
! Read access (not write) from the MFC CTRL SPI interface is lways possibboth for read and write  
registers.  
Table 137 - MFCIO register Shadow trigger source congurati
Bits 3..0 Decimal value  
Trigger source  
0000  
0001  
0010  
0011  
0100  
0101  
0110  
0111  
1000  
1001  
1010  
1011  
1100  
1101  
1110  
1111  
0
1
2
3
4
5
6
7
Always triggeed  
SYNC0 signa
YNC1 gnal  
LACH0 sial  
LATC1 signa
Start Of rame (SOF)  
Of Frae (EOF)  
DI-SChip Select  
8
9
PDI-SI Chip Deselect  
FC-CTRL-SPI Chip Select  
MFC-CTRL-SPI Chip Deselect  
Before shadow register handling cycle  
After shadow register handling cycle  
Trigger at start of MFC PWM cycle  
Trigger when data value changes  
Always triggered  
10  
15  
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7.5 MFCIO Emergency Switch Input  
The Emergency Switch input is called MFC_nES since it is low acrive.  
The ES input has impact on the following functional units and outputs:  
PWM high side and low side gate outputs are set to a defined safe off state  
All GPIO ports that are configured as outputs are set to a defined safe off state  
SD step output and internal step counter (freezes)  
The MFCIO_IRQ signal will be triggered  
The Emergency Switch input is only active if it is masked in the MFCIO IRQ MASK register. Otherwise it  
is ignored.  
A microcontroller or another circuit must actively drive high the MFC_nES input for normal operation.  
If MFC_nES is triggered (set to low), the outputs take their configured safe values.  
The internal Emergency Switch signal/flag remains set even when the external pin/port is alreay driven  
high again.  
The emergency flag can only be unset be either doing a reset or by actively wring 2 timeo the  
MFCIO_IRQ_MASK register at bit position 15. Thereby, the existing IRQ mask at b15 must first set  
to zero and then set back to 1 again. This way, the internal emergency flag is unse
7.6 MFC Incremental Encoder Unit  
The incremental encoder unit allows the decoding of ABN quadre sigth zero pulse up to a  
high speed without CPU load. The parameters for the unit are congurable to fit a wide range of  
quadrature encoders. The internal accumulator workas a 48 it fixed pont value with a 32 bit integer  
part which is visible through the encoder position regter ana 16 bit fractional part which is only  
used internally.  
ENC_CONST  
Up  
Down  
A
Accuator  
Decoder  
X_ENC  
B
N Event  
Detector  
ENC_L
C_MOD
NC_SATUS  
N
Figure 31 ucture of the incremental encoder unit  
The basic configration requires the register ENC_CONST to be set to a value matching the encoder.  
Advanced configuration options are available in the ENC_MODE register for encoders requiring an  
encoder constant with a decimal fraction and to configure the N event detector and the actions taken  
at a N event.  
7.6.1  
MFC Incremental Encoder Unit Signals  
Signal  
I/O  
In  
In  
Function  
Quadrature encoder signal A  
Quadrature encoder signal B  
A
B
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N
In  
Encoder zero pulse N  
7.6.2  
MFC Incremental Encoder Unit Register Set  
Configuration of incremental encoder unit  
Bit 15: clear_status  
Bit 10: enc_sel_decimal  
Bit 8: clr_enc_x  
Bit 7: neg_edge  
Bit 6: pos_edge  
Bit 5: clr_once  
Clears the status flag when written to 1  
Fractional part of ENC_CONST is decimal  
ENC_X is set to 0 at N event  
N event is generated when N input becomes inactive  
N event is generated when N input becomes active  
N event is generated only once  
ENC_MODE W 16 bit  
when all conditions are met  
Bit 4: clr_cont  
N event is generated every time  
all conditions are met  
Bit 3: ignore_AB  
Bit 2: pol_N  
Bit 1: pol_B  
N event is generated regardless f A and B gns  
Active polarity for N input  
Required B input polarity for N ent  
Required B input polaritr N even
Bit 0: pol_A  
Status flag showing that N event was geneated  
Bit 0: Status bit  
ENC_STATUS  
R
8 bit  
X_ENC (W)  
X_ENC (R)  
W 32 bit Register to set a new encoder position  
32 bit Encoder position  
R
ENC_CONST W 32 bit Encoder constant in 16 bit integeand 16 it fractional part  
ENC_LATCH 32 bit Latched encoder position  
R
7.6.3  
ENC_MODE  
clear_status (Bit 15)  
The status flag is not cleared by reading ENC_STUS but neds to be reset by writing this bit to 1.  
enc_sel_decimal (Bit 10)  
With this bit set to 0, the encoer conant is terpreted as a fixed point binary number with the lower  
16 bits representing the fractionpart.  
Whis this bit set to 1, the lower 1bits of he encoder constant represent 1/10000th step. The range  
for the fractional part in tse is <= x <= 9999 and should not be set higher. A fractional part of  
10000 equals an additioer part of 1.  
clr_enc_x (Bit 8)  
If this bit is set t, the encoder counter (ENC_X) is reset to 0 in case of an N event.  
Regardless of this bithe value of the encoder counter is always transferred to the ENC_LATCH register  
at an N e
The N evrated when some configurable conditions are met:  
-
-
If the N matches the pol_N bit (Bit 2) the input signal is considered active.  
If both p_edge (Bit 6) and neg_edge (Bit 7) are 0, the whole active signal is considered as an  
event, if posedge is 1, an event is generated on the inactive->active transition of the signal, if  
neg_edge is 1, an event is generated at the active->inactive transition. Two events are generated if  
pos_edge and neg_edge are both 1.  
-
-
If ignore_AB (Bit 3) is 0, the event is only passed through when the A and B inputs match the pol_A  
(Bit 0) and pol_B (Bit 1) bits. If ignore_AB is 1, the event is always passed through.  
Finally, either clr_once (Bit 5) or clr_cont (Bit 4) needs to be set to either pass through only the  
next event or all following events.  
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7.6.4  
ENC_STATUS  
Only Bit 0 is used in this register, the set status bit indicates that an N event occurred. ENC_STATUS is  
not clear-on-read but must be cleared by setting Bit 15 of ENC_MODE.  
7.6.5  
ENC_X (W)  
Writing a value to this register loads the internal position accumulator to this value.  
7.6.6  
ENC_X (R)  
This register contains the encoder position  
7.6.7  
ENC_CONST  
The encoder constant is a 32-bit fixed-point value that is added to or subtracted from the internal  
accumulator. Depending on the bit enc_sel_decimal in the ENC_MODE register, the fractioal part is  
interpreted differently:  
When enc_sel_decimal is 0:  
(ENC_CONST_INT+(ENC_CONST_FRACT/65536)) is added to or subtracted from the acmulato
When enc_sel_decimal is 1:  
(ENC_CONST_INT+(ENC_CONST_FRACT/10000)) is added to or subtracted from the acmulator  
7.6.8  
ENC_LATCH  
The encoder position X_ENC is latched into this register on each N event.  
Encoder Configuration Example:  
ENC_MODE = 0x001c  
Everytime while N is active (high), generate an N event rgardlesof the A and B inputs. Only latch  
the value, do not clear X_ENC.  
clr_enc_x  
neg_edge  
pos_edge  
clr_once  
clr_cont  
ignore_AB  
pol_N  
= 0  
= 0  
= 0  
= 0  
= 1  
= 1  
= 1  
= 0  
= 0  
pol_B  
pol_A  
ENC_CONST = 0x0001000536)  
Encoder constant = 1.0 (each qadrature signal change counts either up or down)  
Encoder constant exmples for different encoders on a motor with 200 fullsteps/revolution and 256  
microstepp (510 microsteps/revolution) to match encoder position and microstep position:  
Encod
resolut
200  
quired  
coder factor  
56  
ENC_CONST Comment  
0x01000000 No fractional part  
360  
142.2222  
9320675.5555 /  
2^16  
0x008E38E4 No exact match possible. Since the absolute error  
of the binary representation is smaller, this value  
should be used.  
= 1422222.2222 /  
10000  
500  
102.4  
= 6710886.4 /  
2^16  
0x00660FA0 Exact match with decimal setting  
enc_sel_decimal = 1  
= 1024000 /  
10000  
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= 102 +  
(4000/10000)  
1000  
51.2  
= 51 +  
0x003307D0 Exact match with decimal setting  
enc_sel_decimal = 1  
(2000/10000)  
1024  
4000  
50  
12.8  
= 12 +  
0x00320000 No fractional part  
0x000C1F40 Exact match with decimal setting  
enc_sel_decimal = 1  
(8000/10000)  
4096  
12.5  
0x000C8000 Binary fractional part  
0x00032000 Binary fractional part  
= 12 + (2^15/2^16)  
3.125  
16384  
= 3 + (2^13/2^16)  
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7.7 MFC SPI Master Unit  
The SPI Master Unit provides an interface for up to four SPI slaves with a theoretically unlimited  
datagram length using multiple accesses.  
trigger signals  
SPI_CONF  
SPI_CS0  
SPI_CS1  
SPI_CS2  
Control  
SPI_STATUS  
SPI_CS3  
SPI_LENGTH  
Clock  
generation  
SPI_TIME  
SPI_SCK  
SPI_MOSI  
SPI_MISO  
SPI_TX_DATA  
SPI_RX_DATA  
Data shift register  
Figure 32 Block structure of SPI Master Unit  
The basic configuration requires setting the SPI frequency/bt ength, thdatagram length and the SPI  
mode (clock polarity and phase). Extended settings are a specistart-of-transmission trigger linked to  
the PWM unit, the bit order, selection of one of the four PI slavs and datagram length extension.  
7.7.1  
MFC SPI Master Unit Signals  
Signal  
SPI_CS0…SPI_CS3  
SPI_SCK  
SPI_MOSI  
SPI_MISO  
I/O  
Out  
Out  
Ot  
In  
Function  
Chielect lin0..3  
SPI clk output  
SI data utput (Master Out Slave In)  
SPI ata input (Master In Slave Out)  
7.7.2  
SPI_RX_DATA  
MFC SPI Master t Regiser Set  
64 bit Receved data from last SPI transfer  
R
SPI_TX_DATA W 64 bit Data to transmit on next SPI transfer  
SPI Master configuration and control  
Bit 15:  
Start transfer once when this bit is set and trigger  
config is set to 7  
Bits 10..8:  
Trigger config for transmission start values  
000: Start when data is written into TX register  
001: Start on beginning of PWM cycle  
010: Start on center of PWM cycle  
011: Start on PWM A mark  
SPI_CONF  
W 16 bit  
100: Start on PWM B mark  
101: Start on PWM A&B marks  
111: Start on single trigger (Bit 15)  
SPI clock polarity  
Bit 6:  
Bit 5:  
SPI clock phase  
Bit 4:  
Bit 3:  
Bits 1..0:  
LSB first  
Keep CS low after transfer for transfers over 64bit  
Selection of SPI slave  
SPI_STATUS  
R
8 bit  
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SPI_LENGTH  
SPI_TIME  
W
W
8 bit  
8 bit  
7.7.3  
SPI_RX_DATA  
For SPI transfers with less than 64 bit, the upper bits of this register are unused.  
7.7.4  
SPI_TX_DATA  
For SPI transfers with less than 64 bit, the upper bits of this register are unused.  
Unless configured differently in SPI_CONF Bits 10..8, writing to this register starts the SPI transfer.  
7.7.5  
SPI_CONF  
Bits 10..8 allow a configuration when the data transmission should start, they are interpreted s a 3 bit  
number:  
-
In the reset configuration 0, the transmission always starts when data is witten to he SPI_TX  
register.  
-
The settings 1 to 5 link the start of the transmission to the PWM unit, allowng synchronizion  
between the PWM cycle and for example a SPI ADC for current meaureent. Thtrigger sources  
are the five PWM_PULSE signals that are also available as external signallease refer to Section  
7.9 for details about these pulses.  
-
Setting 7 is a single shot trigger that starts only one transmission wh5 is written to 1.  
Bit 6 and 5 define the clock polarity and phase of the SPI sinals whidefine what the idle state of  
the SCK signal is and when output data is changed and when nput data is sampled.  
Clock  
Clock SPI  
MOSI  
MISO  
polarity phase mode change  
smple  
0
0
1
1
0
1
0
1
0
1
2
3
SCK falling edge K rising dge  
SCK rising edgSCfalling edge  
SCK sing edSCK fling edge  
SCK fallig edgSCK rising edge  
Bit 4 reverses the bit order in te transmission, the least significant bit of SPI_TX_DATA (Bit 0) is  
transmitted first, the least significanbit of SPI_RX_DATA is the first received bit, the most significant  
bit of SPI_TX_DATA is tranlast anthe most significant bit of SPI_RX_DATA is the last bit received.  
Bit 3 can be used fr dams loger than 64 bit. With this bit set, the chip select line is held low  
after the transmisson, alloing more transmissions in the same datagram. Before the last transmission,  
this bit must be seto 0 again so that the chip select line goes high afterwards, ending the datagram.  
Bits 1 ane whih chip select line (which slave) is used for the next transmission.  
7.7.6  
S  
Bit 0 of this ister is the Ready indicator for the SPI master unit. When this bit is set, a new transfer  
can be started. hen this bit is 0 and the start of a new transfer is triggered, the trigger is ignored, the  
currently active trnsfer is finished but the new transfer is not started.  
7.7.7  
SPI_LENGTH  
This register defines the SPI datagram length in bits. Any length from 1 to 64 bits is possible.  
The value of this register is the number of bits minus 1.  
7.7.8  
SPI_TIME  
This register defines the bit length and thus the SPI clock frequency.  
The duration of one SPI clock cycle can be calculated as t_SCK = (4+(2*SPI_TIME))/25MHz, the SPI clock  
frequency is f_SCK = 25MHz/(4+(2*SPI_TIME)).  
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The delay between the falling edge of CSN (becoming active) and the first SCK edge and the last SCK  
edge and the rising edge of CSN is always a half SCK clock cycle (t_SCK/2).  
7.7.9  
SPI Examples  
TMC262 ON SPI CHANNEL 0  
This example shows the configuration of the SPI master unit for a TMC262 as SPI slave 0 and the  
transfer of data to the TMC262’s DRVCONF register.  
Use 3.125 MHz SPI clock (25MHz/(4+(2*2))) = (25MHz/8)  
SPI_TIME <= 0x02  
Use 20 bit datagrams  
SPI_LENGTH <= 0x13  
Start on TX write, SPI-Mode 3, MSB first, Single datagrams, Slave 0)  
SPI_CONF <= 0x0060  
Wait until SPI-Master is ready  
while (SPI_STATUS & 0x01 != 0x01)  
Write Data into TX register (e.g. TMC262 DRVCONF register, all 64bit are swn)  
SPI_TX_DATA <= 0x00000000000EF010  
Wait until SPI-Master is ready  
while (SPI_STATUS & 0x01 != 0x01)  
Read Data from RX register  
rxdatagram = SPI_RX_DATA  
CHAIN OF 10 74XX595 SHIFT REGISTERS USED AS DIGITAL 80 OUTPUTOOD EXAME)  
This example shows the transmission of a longer datagrm, in tis case 80 bits that are shifted into a  
chain of 74xx595 shift registers. The NCS of the SPI interfae can e used as the storage clock of the  
74xx595 to transfer the contents of the shift regiter io the orage register. The data that should be  
sent is 0x5555AAAA5555AAAA55AA.  
It is recommended to split the data into twchuks of 40 bits each: 0x5555AAAA55 and 0x55AAAA55AA.  
Configuration and first transmissin  
Use 6.25 MHz SPI cloc(25MH(4+(2*0) = (25MHz/4)  
SPI_TIME <= 0x00  
Use a 40 bit datagram  
SPI_LENGTx28  
Start on TX writode 3, MSB first, Keep CS low, Slave 0)  
SPI_CON0x006
Wait until PI-Mar is redy  
wle (SPI_STATUS & 0x01 != 0x01)  
Write Data fr the first 64 outputs into TX register  
PI_TXATA <= 0x5555AAAA55  
PI-Master is ready  
e (SPI_STATUS & 0x01 != 0x01)  
Stawrite, SPI-Mode 3, MSB first, Drive CS high at the end, Slave 0)  
SPI_CONF <= 0x0060  
Write Dafor the last 16 outputs into TX register  
SPI_TX_DATA <= 0x55AAAA55AA  
Wait until SPI-Master is ready  
while (SPI_STATUS & 0x01 != 0x01)  
Next transmission with inverted data  
Start on TX write, SPI-Mode 3, MSB first, Keep CS low, Slave 0)  
SPI_CONF <= 0x0068  
Wait until SPI-Master is ready  
while (SPI_STATUS & 0x01 != 0x01)  
Write Data for the first 64 outputs into TX register  
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SPI_TX_DATA <= 0xAAAA5555AA  
Wait until SPI-Master is ready  
while (SPI_STATUS & 0x01 != 0x01)  
Start on TX write, SPI-Mode 3, MSB first, Drive CS high at the end, Slave 0)  
SPI_CONF <= 0x0060  
Write Data for the last 16 outputs into TX register  
SPI_TX_DATA <= 0xAA5555AA55  
Wait until SPI-Master is ready  
while (SPI_STATUS & 0x01 != 0x01)  
CHAIN OF 10 74XX595 SHIFT REGISTERS USED AS DIGITAL 80 OUTPUTS (BAD EXAMPLE)  
This bad example is the same as the previous one but with the non-recommended datagram split of 64  
bits + 16 bit. This requires more communication since not only the SPI_CONF register neds to be  
changed between the SPI_TX_DATA writes but also the SPI_LENGTH register changes very tim.  
Configuration and first transmission  
Use 6.25 MHz SPI clock (25MHz/(4+(2*0))) = (25MHz/4)  
SPI_TIME <= 0x00  
Use a 64 bit datagram  
SPI_LENGTH <= 0x3F  
Start on TX write, SPI-Mode 3, MSB first, Keep CS low, Slave 0)  
SPI_CONF <= 0x0068  
Wait until SPI-Master is ready  
while (SPI_STATUS & 0x01 != 0x01)  
Write Data for the first 64 outputs into TX regist
SPI_TX_DATA <= 0x5555AAAA5555AAAA  
Wait until SPI-Master is ready  
while (SPI_STATUS & 0x01 != 0x01)  
Use a 16 bit datagram (remaining output)  
SPI_LENGTH <= 0x0F  
Start on TX write, SPI-Mode 3, MSB rst, Drive CS high at the end, Slave 0)  
SPI_CONF <= 00060  
Write Data for the last 1outputinto TX register  
SPI_TX_DATA <= 0x5AA  
Wait until SPI-Masready  
while (SUS & 0x01 != 0x01)  
Next transmissith inerted data  
Use a 64 bdatam  
S_LENGTH <= 0x3F  
Start on TX rite, SPI-Mode 3, MSB first, Keep CS low, Slave 0)  
PI_COF <= 0x0068  
PI-Master is ready  
e (SPI_STATUS & 0x01 != 0x01)  
Wrifor the first 64 outputs into TX register  
SPI_TX_DATA <= 0xAAAA5555AAAA5555  
Wait untSPI-Master is ready  
while (SPI_STATUS & 0x01 != 0x01)  
Use a 16 bit datagram (remaining outputs)  
SPI_LENGTH <= 0x0F  
Start on TX write, SPI-Mode 3, MSB first, Drive CS high at the end, Slave 0)  
SPI_CONF <= 0x0060  
Write Data for the last 16 outputs into TX register  
SPI_TX_DATA <= 0xAA55  
Wait until SPI-Master is ready  
while (SPI_STATUS & 0x01 != 0x01)  
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7.8 MFC Step Direction Unit  
The MFC is equipped with a step-direction unit. Programming of the step pulse frequency occurs by  
writing an accumulation constant to a register. Toggle of the MSB of the accumulation register value  
generates an internal step pulse of one internal clock cycle. The direction signal is the MSB of the  
accumulation constant. Therefore, the sign of the accumulation constant defines the direction signal  
polarity. The step-to-direction timer (STP2DIR) takes care of possible external signal delay paths by  
programmable delay of the first step after write of accumulation constant. The pulse stretcher forms  
step and direction pulses of programmable length for adaption to external signal paths. The step  
direction unit can either run in free running mode just generating step pulses with programmed  
frequency. Alternatively, is can generate a defined number of step pulses with programmed frequency.  
An interrupt output signal IRQ_TARGET_REACHED indicates the reached target count of step pulses.  
REGISTER_IO (internal)  
ACCUMULATION  
CONSTANT  
COMPARE  
VALUE  
ARGET_REACHED  
COMPARE  
UNIT  
CNT  
UP / DTEP  
INHIBIT  
COUNTER  
ACCU  
REGISTER  
STEP  
DIR  
STE
STP  
DIR  
SIR  
TIME
PULSE  
STRETCHER  
DDLY  
Figure 33: Step Direction Unit Block Diagra
2.1.1 MFC Step Direction Unit iming  
Write to the accumulatioant reister starts step pulse generation. The first step pulse occurs  
after a time tSTEP1st. Fostep pulses come after each tSTEP. The pulse length of the step pulses  
is iSTEP_PULSE. On chandirectn by writing the accumulation constant with a constant of different  
sign, the first step pulse aer writoccurs after tSTP2DIR.  
STEP1st  
WRregiste
tSTEP_PULSE  
STP  
tSTEP  
tSTP2DIR  
DIR  
Figure 34: Step-Direction Timing  
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2.1.2  
MFC Step Direction Unit Signals  
Signal  
I/O  
Out  
Out  
Out  
Function  
STP  
DIR  
Step Pulse Output  
Direction Signal Output  
IRQ_TARGET_REACHED  
Interrupt Request Output indicating target reached condition  
2.1.3  
MFC Step Direction Unit and Register Set  
StepDirection accumulation constant  
31 … 0  
Signed accumulation constant,  
this accumulation contant  
determines thtime tSEP  
between to succesivteps  
rate resphe step frequecy,  
the Sign (MB) of this  
SD_CH_SR  
acumlation onstant is used  
or thection signal output  
(DIR_N); the  
acon constant c is 2th  
comment (section 7.8.1)  
ep counter, counting  
Step counter  
… 0  
SD_CH_SC  
up/down depending on step  
direction, the direction is  
programmed via sign (2th  
complement) of SD_CH_SRs  
(section 7.8.2)  
steps to be done (section 0)  
Step pulse length in terms of  
CLK25MHz cycles, with tSTP = …  
(section 7.8.4)  
Step target  
Step Length  
31 ... 0  
15 … 0  
SD_CH_ST  
SD_CH_SL  
StepDirection lay  
15 … 0  
7 … 0  
Delay between change of  
direction and first step pulse,  
delay is … (section 7.8.5)  
7: -  
SD_CH_DLY  
SD_CFG  
Stetion Cnfiguration  
6: -  
5: 0 : stp pulse / 1 toggle  
4: 0 - / 1 clears step count  
3: dir signal polarity  
2: step pulse polarity  
1: 0=n pulses / 1=continuous  
0: 0=disable / 1=enable  
CH = channel (in ase of more than one step direction unit)  
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Parameter  
fCLK[Hz]  
Value  
Description / Function  
Comment  
clock frequency of the  
step direction unit  
25 MHz clock frequency of step direction unit  
tCLK[s]  
fSTEP[Hz]  
40 ns  
clock period length  
fSTEP[Hz] = (fCLK[Hz]/2^32)*(SD_CH#_SR)  
tCLK[s] = 1 / fCLK[Hz]  
step frequency,  
programmed via step rate  
accumulation constant  
SD_CH#_SR  
Max. fSTEP[Hz]  
12.5  
MHz  
Theoretical maximum value  
for fStep. Usable step  
frequency dependon step  
pulse length configration.  
time betweesteps  
step pue length be  
lower an time betwen  
step pulss!  
tSTEP[s]  
tSTEP_PULSE[s]  
tSTEP = 1 / fSTEP[Hz]  
tSTEP_PULSE[s] = (STP_LEN_I+1) / fCLK[Hz]  
tSTULSE[s] < tSTEP[s]  
dsignal, depending  
rate (SR) parameter,  
DIR  
DIR = 0 positive direction,  
DIR = 1 negative direction,  
direction is depending on sign of step raDIR = 0 if SR > 0 or SR = 0,  
DIR = 1 if SR < 0  
register SD_CH#_SR where the tep rate  
register is 2th complemet  
tSTEP1st[s]  
Time between write until  
the first step pulse occurs  
time to 1st step pulse since WR=0 with  
tSTEP1st[s] = 2^32 STP_R_I * tCLK[s]  
+ STP_DLYI + 1 ) *  
tCLK[s]  
+ ( 2 * CLK[s] );  
tSTEP1stWR[s]  
SD_CH_SR  
Internal processing adds  
an delay  
tie to 1t step ulse since WR=0 step  
delaplus 1 internal clock plus 2 clock  
cycles tpulse length  
ng SCH_SR = 0 clears the step  
cu register step_accu_ff and stops  
step plse generation.  
7.8.1  
StrectioAccumulation Constant  
The step ccumulation constant determines the time tSTEP between two successive step pulses  
the stEach internal PWM clock accumulates an accumulator according to a = a + c with  
the accumstant c. Toggle of the MSB of the accumulator register a triggers a step pulse. With  
this principle, e step frequency is smarter adjustable compared to a simple frequency divider. Writing  
c = 0 clears the ccumulator and stops the step pulse generation. The step pulse frequency fSTEP[Hz]  
= ( fCLK[Hz] / 2^32 ) * c. To calculate the accumulation c one just have to calculate  
c = int( 2^32 * ( fSTEP[Hz] / fSTEP[Hz] ) ) = int ( 4294967296 * ( fSTEP[Hz] / fSTEP[Hz] )  
TIME TO FIRST STEP  
Due to internal processing, the time to the first step since write register write is  
tSTEP1st[s] = 2^32 / SD_SR * tCLK[s] + (STP_SDY_I + 1 ) * tCLK[s] + ( 2 * tCLK[s] )  
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7.8.2  
Step Counter  
The step counter counts the number of steps, taking the direction into account. This is a read only  
register. For initialization to zero a configuration bit within the step direction configuration register hast  
to be written.  
7.8.3  
Step Target  
The step target defines the number of steps to be made for the step mode until stop. This register can  
be overwritten at any time. When the number of steps has been made, the unit stops outputting S/D  
pulses. When read, it gives the remaining numbers that must still be made.  
7.8.4  
Step Length  
The duration of the step pulse the step length (SL) - signal is programmable for adaption to external  
power stages.  
MAXIMUM STEP LENGTH  
The step pulse length tSTEP_PULSE[s] must be lower than the time tSTEP[s] beween step es to  
have step pulses. The condition tSTEP_PULSE[s] < tSTEP[s] must be ensured by thapplication.  
7.8.5  
Step-to-Direction Delay  
The delay between the first step pulse after a change of the direction progable for adaption to  
external power stages to take external delay paths into account.  
7.8.6  
Step Direction Unit Configuration  
The step direction configuration defines the mode f operaon (continous or finite number of step  
pulses), polarity of step pulse signal and direction signl. One it is for zeroing of step pulse counter.  
On bit is for enabling and disabling of the step pulse unit
7.8.7  
Interrupt Output Signal  
A signal IRQ_TAR_REACHED of a single cocpulse lenth indicated indicates that a TARGET  
position is reached in terms of step counts.  
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7.9 MFC PWM Unit  
The MFC is equipped with a tripe pulse width modulation (PWM) block including programmable brake  
before make (BBM) unit. Both high side and low side control signals are available as separate outputs.  
A single PWM counter generates three synchronous PWM signals. Setting the maximum count as limit  
defines the PWM frequency. Left aligned PWM, Centered PWM, and right aligned PWM is selectable. The  
BBM take care concerning the BBM timing. The BBM timing is individually programmable for high side  
and low side. Fixed pulses are available for triggering of ADCs or triggering interrupts of a CPU.  
Programmable trigger output signals are available. The position and the duration of two theses pulses  
is programmable. The pulse PULSE_ZERO indicating the beginning of a PWM cycle and the pulse  
PULSE_CENTER indicating the center of the PWM are fixed. The two programmable signals PULSE_A and  
PULSE_B are for advanced ADC triggering. The trigger signal output PULSE_AB is the logical or of PULSE_A  
and PULSE_B. The polarities of the output signals of the PWM unit is programmable. An iput signal  
OVC_I with programmable active polarity disables the PWM signals.  
REGISTER_IO (internal)  
PWM1_H  
PWM_1  
PWM_2  
PW3  
PWM1_L  
PWM2_H  
PWM2_L  
BBM  
PWM3_H  
PWM3_L  
OVC_I  
OVC_O  
PULSE_ZERO  
PULSE_CENTER  
PULSE_A  
PWM counter  
PULSE_B  
PULSE_AB  
Figure 35: PWM Block Diagram  
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2.1.4  
MFC PWM Block Signals  
Signal  
I/O  
In  
Function  
nES  
Emergency Switch Input  
PULSE_ZERO  
PULSE_A  
PULSE_CENTER  
PULSE_B  
PULSE_AB  
OVC_CNTL_O  
PWM0_H  
PWM0_L  
PWM1_H  
PWM1_L  
PWM2_H  
Out  
Out  
Out  
Out  
Out  
Out  
Out  
Out  
Out  
Out  
Out  
Out  
Pulse indicating the beginning of a new PWM cycle  
Pulse with programmable positon within the PWM period  
Pulse indicating the middle of the PWM cycle  
Pulse with programmable positon within the PWM period  
Logical or of PULSE_A and PULSE_B  
Over Current output, control signal to disable the power stage  
High side control output of PWM unit 0  
Low side control output of PWM unit 0  
High side control output of PWM unit 1  
Low side control output of PWM unit 1  
High side control output of PWM unit 2  
Low side control output of PWM unit 2  
PWM2_L  
2.1.5  
MFCIO  
MFC PWM Unit and Register Set  
Function  
MFCR  
R/W  
MFCR  
Size  
direct  
Access  
Address  
[Bytes]  
PWM_MAXCNT  
PWM_CHOPMODE  
PWM_ALIGNMENT  
POLARITIES  
PWM0  
PWM1  
PWM2  
PWM0_CNTRSHFT  
PWM1_CNTRS
PWM2_CNT
PULSE_
W
W
W
W
W
W
W
W
W
W
W
W
W
2
2
1
1
2
2
2
2
2
2
2
1
1
1
PLSE_B  
PULSLENGTH  
BBMH  
BM_L  
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CENTERED PWM  
tMAXCNT  
PWM#1  
PWM#2  
tPWM#1  
tPWM#2  
tPWM#3  
PWM#3  
PULSE_ZERO  
PULSE_CENTER  
tPULSE_LENGTH  
tPULSE_LENGTH  
tPULSE_A  
PULSE_A  
PULSE_B  
PULSE_AB  
tPULSE_LENGTH  
tPULSE_B  
tPULSE_LENGTH  
tPULSE_LENGTH  
Figure 36: PWM Timing (centered PWM)  
LEFT ALIGNEWM  
tMAXCNT  
PWM#1  
PWM#2  
tPWM#1  
tP2  
PWM#3  
PWM#3  
PULSE_ZERO  
PULSE_CENTER  
tPULSE_LENGTH  
tPULSE_LENGTH  
tPULSE_A  
PULSE_A  
PULS
tPULSE_LENGTH  
tPULSE_B  
tPULSE_LENGTH  
PUL
tPULSE_LENGTH  
Figure 37: PWM Timing (left aligned PWM)  
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RIGHT ALIGNED PWM  
tMAXCNT  
PWM#1  
PWM#2  
tPWM#1  
tPWM#2  
PWM#3  
tPWM#3  
PULSE_ZERO  
PULSE_CENTER  
tPULSE_LENGTH  
tPULSE_LENGTH  
tPULSE_A  
PULSE_A  
PULSE_B  
PULSE_AB  
tPULSE_LENGTH  
tPULSE_B  
tPULSE_LENGTH  
tPULSE_LENGTH  
Figure 38: PWM Timing (right aligned PWM)  
PWM counter length  
PWM chopper mode  
11 …
This parameter determines the  
duration of the PWM period  
resp. the PWM frequency  
This parameter defines the  
chopper mode (no chopper, high  
side chopper, low side chopper,  
complementary chopper) for the  
three PWM units (section 7.9.2),  
each PWM unit can be  
PWM_MAXCNT  
10:8  
64  
2:0  
PWM_CHOPMODE  
configured seperately  
alignent  
LEFT, CENTERED, RIGHT  
1 ... 0  
This parameter defines the  
alignment of the PWM: 00 = off,  
10 = left, 01 = right, 11 =  
centered (7.9.3)  
pulse_zero <= polarities(6)  
PWM_ALIGNMENT  
PWM_POLARITIS  
PWM HS and LS polarity  
6 … 0  
pulse_a  
<= polarities(5)  
pulse_centerf <= polarities(4)  
pulse_b  
pulse_ab  
<= polarities(3)  
<= polarities(2)  
pwm_high_sides<= polarities(1)  
pwm_low_sides<= polarities(0)  
These three registers define the  
PWM duty cycle (on time) for  
each PWM output  
PWM duty cycle value  
11 … 0  
PWM#0  
PWM#1  
PWM#2  
PWM#0CNTRSHFT  
PWM#1CNTRSHFT  
PWM#2CNTRSHFT  
PWM time shift parameter  
11 … 0  
These three registers define the  
shift time for the PWM units, it  
is intended to create a time gap  
between PWM edges for phases  
current measurements (section  
7.9.9)  
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T of trigger pulse (e.g. for  
ADC sample)  
T of trigger pulse (e.g. for  
ADC sample)  
Length of (ADC) trigger  
pulses A & B  
11 … 0  
11 … 0  
7 … 0  
This is a programmable ADC  
trigger pulse A (section 7.9.6)  
This is a programmable ADC  
trigger pulse B (section 7.9.7)  
This register represents the  
programmable pulse length of  
the trigger pulses A and B and  
pwm_start and pwm_center  
(section 7.9.8)  
PULSE_A  
PULSE_B  
PULSE_LENGTH  
Brake before make length  
high side  
7 … 0  
7 … 0  
This parameter is the brake  
before make time in terms of  
clock cycles for the high side  
MOS-FET control (sectin 7.9.11)  
This parameter is the bake  
before make timin ters of  
clock cycles or the hih de  
MOS-FET ctrols (section 79.12)  
BBM_H  
BBM_L  
Brake before make length  
low side  
Parameter  
fCLK[Hz]  
tCLK[s]  
Value  
Description / Function  
Cmmen
100 MHz clock frequency of PWM unit  
10 ns  
40,96us  
fCLK[HtCLK[s]  
tCLK[fCLK[Hz]  
aximum tPWM with maximum  
PWresolution of 12 bit.  
Minimal PWM frequency with  
maximum PWM resolution of 12  
bit.  
clock period length  
Length of PWM period  
tPWM = tCLK * (1 + PM_MANT)  
PWM frequency = 1 / tPWM  
max. tPWM[s]  
min. fPWM[Hz]  
24.414  
kHz  
Length of thAtrigger lses  
with tPULS_LENGH =  
PULSE_LENTH * tCL
Brake efore ake time tBBM with Individually programmable for  
tBM_H BBM_H * tCLK  
pulse length is adjustable to  
trigger external ADCs  
tCLK = 10ns  
tPULSE_LENGTH  
tBBM  
high side and low side due to  
different timing requirements,  
especially when using PMOS @  
High Side and NMOS @ Low  
Side  
tBB_L = BM_L * tCLK  
7.9.1  
PWM_MAXCT Configuration Register  
This regismmony defines the number of counts per PWM cycle for three PWM units. This  
determinth tPWM of each PWM cycle resp. the PWM frequency fPWM. It is programmable for  
adjustmWM frequency fPWM.  
7.9.2  
PWMHOPMODE Configuration Register  
This Register comonly selects the chopper mode of the three PWM units. The following table gives  
the available chopper modes.  
Pwm0 chopmode = PWM_CHOPMODE(2:0)  
Pwm1 chopmode = PWM_CHOPMODE(6:4)  
Pwm2 chopmode = PWM_CHOPMODE(10:8)  
Selection Chopper High Side (HS) Low Side (LS)  
Function  
no chopper, all off  
no chopper, LS permanent on  
%000  
%001  
no  
no  
off  
off  
off  
on  
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%010  
%011  
%100  
%101  
%110  
%111  
no  
no  
no  
yes  
yes  
Yes  
no  
off  
off  
off  
PWM  
PWM  
off  
off  
off  
no chopper, HS permanent on  
no chopper, all off, not used  
no chopper, all off, not used  
chopper LS, HS off  
PWM  
Off  
not PWM  
chopper HS, LS off  
chopper HS and LS complementary,  
brake-before-make is handled by  
programmable BBB unit  
PWM cycle  
tMAXCNT  
PWM  
CHOPPSELECTION  
PWM_H  
PWM_L  
%000, %011100  
PWM_H  
PWM_L  
%001  
%010  
%101  
%110  
%111  
PWM_H  
PWM_L  
PWM_H  
PWM_L  
PWM_H  
PWM_L  
PWM_H  
PWM_L  
Figure 39: Chopper Modes (OFF, LoSide N, High Side ON, Low Side Chopper, High Side Chopper,  
Complementary Low Side h SidChopper)  
7.9.3  
PWM_ALNMENT Cnfiguration Register  
This register commnly determines the alignment of the three PWM units. The alignment can be  
programmalignd, centered, or right aligned (pls. refer Figure 36, Figure 37, and Figure 38).  
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CENTERED PWM  
tMAXCNT  
PWM#1  
PWM#2  
PWM#3  
tPWM#1  
tPWM#2  
tPWM#3  
CENTERED PWM SHIFT PWM#2  
tMAXCNT  
PWM#1  
PWM#2  
PWM#3  
tPWM#1  
PWM_CNTRSHFT#2  
tPWM#2  
tPWM#3  
Figure 40: Centered PWM with PWM#2 shifted from Center (Example)  
7.9.4  
POLARITIES Configuration Register  
The PWM signals of the three are of positive logic. So, logical one evel meand logical zero level  
means OFF. Depending on the MOS-FET drivers, switching on a MS-FET might require an inverted  
logical level. The polarities configuration register deerminehe switchg polarities for the high side  
MOS-FETs and switching polarities for the low side MOS-FETs.  
7.9.5  
PWM Value Registers  
Together with the programmed PWM counter length, te PWM values determine the PWM duty cycle.  
The PWM duty cycle is individually programme for eacof the three PWM units. Programming the  
three PWM values sets up a vector of effecive thre voltages.  
7.9.6  
PULSE_A Configuration Regiter  
The position of the trigger pue A is programable within the PWM cycle. A second trigger pulse  
within the PWM cycle is programable inividually. This pulse is intended to trigger an ADC.  
7.9.7  
PULSE_B Configuegist
The position of the trilse B is programmable within the PWM cycle. A second trigger pulse  
within the PWM cyce is grammble individually. This pulse is intended to trigger an ADC.  
7.9.8  
PULSE_LENTH Configuration Register  
To take the tming odifferent ADCs into account, the length of PULSE_A and PULSE_B and the fixed  
trigger ped PLSE_CENTER and PULSE_ZERO, is commonly programmable in terms of clock  
cycles er.  
7.9.9  
Asyetric PWM Configuration Registers  
To open a widtime window between PWM switching events that are close to each other PWM an  
asymmetric PWM hift can be programmed individually for each PWM unit. This leaves the PWM duty  
cycles unchanged. It is useful for current measurement with sense resistors at the bottom of the MOS-  
FET half bridges. In contrast to current sensing with differential sense amplifiers or with hall sensor  
bases current sensors within the current phase, this feature has no advantage.  
7.9.10 Brake-Before-Make (BBM)  
To avoid cross conduction, of the half bridges, the brake before make (BBM) timing is programmable.  
In most cases, the same BBM time is sufficient for both, low side and high side. The BBM time should  
be programmed as short as possible and as long as necessary. A too long BBM time causes conduction  
of the bulk diodes of the power MOS-FETs and that causes higher power dissipation and less motor  
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performance concerning current regulation. In case of using PMOS-FETs for high and NMOS-FETs for low  
side with asymmetric switching characteristics, it might be advantageous to program different BBM_H  
time and BBM_L time.  
7.9.11 BBM_H Configuration Register  
This register programs the time from switch off the low side to switch on the high side in terms of  
clock cycles. The BBM_H is common for all three high side power MOS-FETs.  
7.9.12 BBM_L Configuration Registers  
This register programs the time from switch off the high side to switch on the low side in terms of  
clock cycles. The BBM_L is common for all three high side power MOS-FETs.  
PWM cycle  
tMAXCNT  
PWM  
PWM_H  
PWM_L  
PWM_H_BBM  
PWM_L_BBM  
tPWM_BBM_H  
WM_BBM
Figure 41: Brake Before Make (BBM) Timing (individul progrmable foLow Side and High Side)  
7.9.13 Emergency Switch Input Off-State  
The emergency switch input MFC_nES of the TMC860-can bconfigured to disable the MOSFET power  
stage immediately, e.g., under control of an extenal ovecurrent comparator (or similar trigger).  
nES is thereby used as external trigger. It is low ctive and ontains an internal pull down resistor. For  
normal operation it must be actively pullehigh eernally.  
When pulled to ground, MFCnES terinates he actual PWM cycle and brings the low side and high  
side gate outputs into off-state. he offtate is defined by the PWM_POLARITIES register using bits 0  
(low sides) and bit 1 (high sides).  
PWM_POLARITIES(0) = = off / 1 = on  
PWM_POLARITIES(0) = 1 = f / 0 = on  
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7.10 MFC GPIO Unit  
The MFC GPIO Unit handles the general-purpose inputs and outputs.  
Eight (8) independent GPIO ports are available.  
Each GPIO is configurable either as input or as output.  
7.10.1 MFC GPIO Registers  
Three registers are required for MFC GPIO configuration:  
GPO_OUT_VAL defines the output values of the outputs.  
GPI_IN_VAL is read only and contains the actual input values.  
GPIO_CONFIG allows to configure the GPIO direction.  
MFCIO  
direct  
Register Name MFCR  
R/W  
MFCR  
Size  
Function  
Access  
Address  
[Bytes]  
7:0 : GPO output values  
15:8 : GPO safe state (when FC_nES = ‘0’)  
33  
GPO_OUT_VAL  
W
2
34  
35  
GPI_IN_VAL  
GPIO_CONFIG  
R
W
1
1
7:0 : GPI input values  
7:0 : GPIO direction (0 = iut, 1 = output)  
7.10.2 General purpose Inputs (GPI)  
If configured as input, each GPI value can be read from the GPIIN_L frorespective bit position.  
7.10.3 General purpose Outputs (GPO)  
If configured as output, each GPO takes the value definein GP_OUT_VAL[7:0].  
For output data to be visible on the output signas, tfollong conditions have to be met:  
ESC must be in OP state  
Your output data must be written to thregter  
MFC_nES must be driven high external
7.10.4 Emergency Switch Iut Stae  
The external emergency switch iput MF_nES (imasked/enabled) brings all GPIOs currently  
configured as outputs into a configrable sfe state.  
The GPO_OUT_VAL register byte (its 15:8) defines the safe state.  
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7.11 MFC Watchdog Unit  
7.11.1 General Function  
The watchdog timer allows monitoring of external signals, or monitoring of ETHERCAT activity. A certain  
condition can be chosen for retriggering the watchdog, i.e. a certain input signal constellation. In case  
this constellation does not occur at least once within a pre-programmable time period, the watchdog  
timer will expire and will trigger a certain watchdog action. To avoid static reset of the watchdog, the  
watchdog input condition is edge sensitive, i.e. it becomes reset when the condition goes active  
respectively goes inactive. Once the watchdog expires, the watchdog safety circuitry becomes active.  
This action can bring I/O lines into a certain state, in order to allow the system to return to a known,  
safe condition. Therefore, all I/O lines are directly mapped to the GPIO ports of the chip, so that they  
perform independently of the actually configured peripheral configuration. The watchdog action can be  
chosen to remain active continuously, until it becomes reset by a watchdog re-configuratio, or it can  
be programmed to return to normal operation state, once the selected condition becomes tre again.  
In an optional use case, the watchdog timer can be used to measure the maximm delay bween  
of the occurrence of certain input conditions, in between of SPI frames, etc.  
7.11.2 Watchdog Register Set  
Once initialized, the watchdog timer monitors the application for actity allows setting of pre-  
programmed I/O patterns, in case the time limit is expired without actiity. r to allow tuning of  
this time limit, the maximum time between two trigger events becomes d. This function also  
allows delay time measurement for input channels (i.e. whn no atchdaction is chosen). The  
watchdog timeout counter starts from zero up to WD_TIMEWhen it rches WD_TIME, it triggers the  
watchdog action.  
The selected watchdog event resets the timeout counter. As igger sources, the internal ETHERCAT start  
of frame, the two SPI chip select signals as welas ancombiation of I/O lines can be used. For the  
I/O lines, the polarity and edge are programable. Whn using a GPIO programmed to output as  
watchdog trigger, the watchdog circuitry will moitor the real output by checking the polarity of the  
output signal. This way, also a short circconditiowill be detected. The chip select signals respond  
to a rising edge (i.e. when the SPI interfacloads the SPI shift register data into the corresponding  
registers).  
MFCIO  
direct  
Register  
Name  
R/W  
ize  
[Bys]  
Function  
Access  
Address  
Watchdog time 32 bit, unsigned  
38  
39  
WD_TME W/R  
4
1
0 =  
Time =  
Watchdog off  
Number of 25MHz clocks  
cfg_persistent  
0 The watchdog action ends when the  
next trigger event occurs  
1 A timeout situation can only be cleared  
by rewriting WD_TIME  
Bit 0  
cfg_pdi_csn_enable  
Bit 1 1 Retrigger by positive edge on  
PDI_SPI_CSN  
WD_CFG  
W/R  
cfg_mfc_csn_enable  
Bit 2 1 Retrigger by positive edge on  
MFC_CTRL_SPI_CSN  
cfg_sof_enable  
1 Retrigger by ETHERCAT start of frame  
Bit 3  
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cfg_in_edge  
0 Retrigger by input condition becoming  
Bit 4  
Bit 7  
false  
1 Retrigger by input condition becoming  
true  
cfg_wd_active  
R
1 Signals an active watchdog timeout  
Mask for outputs to be affected by watchdog  
action  
31:0 : WD_OUT_POL, polarity for outputs affected  
by watchdog action  
32 bit, each bit corresponds to one output ine  
The polarity describes the output level desird  
upon watchdog action  
WD_OUT_  
MASK_POL  
40  
W/R  
8
63:32: WD_OUT_MASK, each bit coresponds to ne  
output line  
0
1
Output is not affeted  
Output [i] becomes sD_OUT_POL[i]  
upon wathdog action  
See Table xxx blow for the detailed signal  
mapping / ndices of WD_OUT_MASK_POL  
I/O Oput eable level for outputs affected by  
watchdoaction  
3bit, each bit corresponds to one output line  
The olarity describes the OE setting desired upon  
watchdog action (1= output, 0= input)  
election of input signals for watchdog  
retriggering  
WD_OE_  
POL  
41  
W/R  
4
15:0 : WD_IN_POL, Input signal levels for  
watchdog retriggering  
16 bit, each bit corresponds to one input line  
The polarity describes the input level for signals  
selected by WD_IN_MASK required to re-  
trigger the watchdog timer  
_IN_  
POL  
42  
W/R  
4
31:16 : WD_IN_MASK, each bit corresponds to one  
input line  
0
1
Input is not selected  
Input I/O[i] must reach polarity WD_IN_POL[i]  
to re-trigger the watchdog timer  
See Table xxx below for the detailed signal  
mapping / indices of WD_IN_MASK_POL  
32 Bit peak value reached by watchdog timeout  
counter  
43  
WD_MAX  
R
4
Reset to 0 by writing to WD_TIME  
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GPIO Input  
Lines  
Input Signal  
Polarity  
Input Trigger  
Condition  
Watchdog  
timer counter  
Output Signal GPIO Output  
Logic Lines  
MFC_GPIO_0  
MFC_GPIO_1  
MFC_GPIO_2  
=
WD_IN_POL.0  
WD_IN_POL.1  
WD_IN_POL.2  
WD_IN_MASK.0  
WD_IN_MASK.1  
WD_IN_MASK.2  
25MHz  
=
=
Port function  
WD_OUT_POL.i  
WD_OUT_MASK.i  
MFC_GPIO_i  
cfg_in_edge  
Watchdog Timer  
(Count up to  
WD_TIME)  
RESET  
WD_TIME exceeded  
Port function.OE  
WD_OUT_OE.i  
PDI_SPI_CSN  
cfg_pdi_csn_enable  
cfg_mfc_csn_enable  
WD_MAX  
read out  
MFC_CTRL_SPI_CSN  
Ethercat SOF  
cfg_sof_enable  
Figure 7.42 Structure of the watchdog unit  
The following table contains the assignments of ports/signals to the configuration bts in the  
WD_OUT_MASK_POL register.  
Bit # Signal  
Description  
Bit # Signal  
Description  
0
1
2
3
4
5
6
7
GPO0  
GPO1  
GPO2  
GPO3  
GPO4  
GPO5  
GPO6  
GPO7  
PWM_LS0  
PWM_LS1  
PWM_LS2  
PWM_HS0  
PWM_HS1  
PWM_HS2  
PWM_PULSE_AB  
PWM_PULS_B  
PWM_PUE_CENTE
PWM_PULS_A  
PULSE_SART  
SP
SPI_C
SPI_CS1  
SPI_CS0  
SPI_SDI  
SPI_SCK  
reserved  
reserved  
reserved  
reserved  
reserved  
32  
33  
34  
36  
37  
3
39  
40  
41  
42  
43  
44  
45  
46  
47  
48  
49  
50  
51  
52  
53  
54  
55  
56  
57  
58  
59  
60  
61  
62  
63  
GPO
GPO1  
GPO2  
GO3  
GPO4  
GPO5  
GPO6  
GPO7  
PWM_LS0  
PWM_LS1  
PWM_LS2  
PWM_HS0  
PWM_HS1  
PWM_HS2  
PWM_PULSE_AB  
PWM_PULSE_B  
PWM_PULSE_CENTER  
PWM_PULSE_A  
PWM_PULSE_START  
SD_DIR  
SD_STP  
SPI_CS3  
SPI_CS2  
SPI_CS1  
SPI_CS0  
SPI_SDI  
SPI_SCK  
reserved  
reserved  
reserved  
reserved  
reserved  
8
9
10  
11  
12  
13  
14  
15  
16  
17  
18  
19  
20  
21  
22  
23  
24  
25  
26  
27  
28  
29  
30  
31  
W_OUT_POL  
WD_OUT_MASK  
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The following table contains the assignments of ports/signals to the configuration bits in the  
WD_IN_MASK_POL register.  
Bit # Signal  
Description  
Bit # Signal  
Description  
0
1
2
3
4
5
6
7
GPI0  
GPI1  
GPI2  
GPI3  
GPI4  
GPI5  
GPI6  
GPI7  
SPI_SDO  
ABN_N  
ABN_B  
ABN_A  
reserved  
reserved  
reserved  
reserved  
16  
17  
18  
19  
20  
21  
22  
23  
24  
25  
26  
27  
28  
29  
30  
31  
GPI0  
GPI1  
GPI2  
GPI3  
GPI4  
GPI5  
GPI6  
GPI7  
SPI_SDO  
ABN_N  
ABN_B  
ABN_A  
reserved  
reserve
reserve
reserved  
WD_IN_POL  
WD_I_MASK  
8
9
10  
11  
12  
13  
14  
15  
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7.12 MFCIO IRQ Unit and Register Set  
MFCIO  
direct  
Register  
Name  
R/W  
Size  
[Bytes]  
Function  
Access  
Address  
Masking / Enabling of the required IRQ sources  
which are or-ed to set the MFCIO_IRQ output  
signal  
Status register to read the IRQ flags of the masked  
IRQ sources  
36  
37  
IRQ MASK  
IRQ Flags  
W
R
2
2
It is used as IRQ signal indicating various events of the MFCIO block.  
Two 16bit registers are used.  
-----------------------------------------------------------------------------  
-- MFCIO IRQ selection block  
-----------------------------------------------------------------------------  
IRQ_SOURCE(0) <= ABN_N;  
-- encoder unit N-event  
IRQ_SOURCE(1) <= IRQ_SD_TAR_REACHED0; -- SD0 target reached  
IRQ_SOURCE(2) <= IRQ_SPI_NEW_DATA; -- SPI IRQ new data available  
IRQ_SOURCE(3) <= wd_timeout;  
IRQ_SOURCE(4) <= PULSE_ZERO;  
IRQ_SOURCE(5) <= PULSE_CENTER;  
IRQ_SOURCE(6) <= PULSE_A;  
IRQ_SOURCE(7) <= PULSE_B;  
-- Watchdog unit timeot  
-- PWM Cycle Start Triger  
IRQ_SOURCE(14:8)  
IRQ_SOURCE(15) <= MFC_nES; -  
2.1.6  
IRQ MASK Register  
The IRQ mask register allows o enab/disabcertain IRQ trigger events of the MFCIO block.  
This may be required to reduce IRQ loawhen certain functional MFCIO sub blocks are used at the  
same time or are not needed.  
2.1.7  
IRQ_FLAGS Reg
This register can bread ut after the IRQ was set to identify the IRQ source (especially when more  
than 1 IRQ sourcwas enabled).  
Reading tsters cears all individual IRQ source bits.  
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7.13 AL State Override Configuration  
All functional output signals of the MFCIO block are linked to the OP state of the EtherCAT state machine.  
As long as the actual state is not OP, all functional output states are not driven but in high impedance  
state.  
The AL_STATE_OVERRIDE register allows overriding this behavior.  
The AL_STATE_OVERRIDE register can only be accessed from MFC CTRL SPI interface. It cannot be  
accessed from ECAT interface or from PDI SPI interface.  
Each bit in the AL_STATE_OVERRIDE register controls override configuration of a specific MFCIO sub-  
block regarding the output ports availability.  
If a bit is set to ‘1’, the AL status register (0x0130:0x0131) is ignored and the output ports of tis MFCIO  
sub-block are fully available using the MFC CTRL SPI interface.  
The incremental encoder block, IRQ configuration, and the watchdog block are not affeced y the  
AL_STATE_OVERRIDE register since they only have input ports.  
Table 138: AL_STATE_OVERRIDE regisr  
ECAT  
PDI SPI  
MFC CTRL SP
et Value  
Bit  
0
Description  
SPI block  
-/-  
-/-  
rw  
0
1
2
3
7:4  
S/D block  
PWM block  
GPIO block  
Reserved  
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8 ESD Sensitive Device  
The TMC8460 is an ESD sensitive CMOS device sensitive to electrostatic discharge. Take special care to  
use adequate grounding of personnel and machines in manual handling. After soldering the devices to  
the board, ESD requirements are more relaxed. Failure to do so can result in defect or decreased  
reliability.  
9 Disclaimer  
TRINAMIC Motion Control GmbH & Co. KG does not authorize or warrant any of its products for use in  
life support systems, without the specific written consent of TRINAMIC Motion Conol GmbH  
& Co. KG. Life support systems are equipment intended to support or sustain life, d  
whose failure to perform, when properly used in accordance with instructions provied, can e  
reasonably expected to result in personal injury or death.  
Information given in this data sheet is believed to be accurate and reliable. Howevr no responsility  
is assumed for the consequences of its use nor for any infringement of patnts or other  
rights of third parties which may result from its use.  
Specifications are subject to change without notice.  
All trademarks used are property of their respective owners
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10 Revision History  
Version  
Date  
Author  
SK= Stephan Kubisch  
Description  
V001  
V002  
V003  
2013-DEZ-19  
2014-FEB-26  
2014-APR-23  
SK  
SK  
SK  
Initial Document  
spec details added  
MFCIO Configuration Table added  
More information on the MFCIO block added  
V004  
V005  
2014-MAY-16  
2014-MAY-27  
SK  
SK  
Added firs info on S/D Unit Registers  
Changed Address Map to even number staaddresses  
Added more information on MFCIO sub blocs  
V006  
2014-JUN-04  
SK  
Updates on GPIO Watchdog block, auxilry clk output  
and MFCIO IRQ Event register cofiguration;  
Added section for Die Pad List;  
IPCORE_REV = 0 and IP_OREBLD = until 2014-JULY-30;  
V007rev1bld1 2014-JUL-30  
2014-SEP-05  
LL  
LL  
Beginning with updad veccording to changed  
register mapping model vextension (instead of direct  
mapping of ESristers he ESC memory range);  
IPCORE_REV pdated 1 and IP_CORE_BLD updated to 1  
for VHDL veron of 2014-JULY-30;  
MFC R/W & SIZE added to Memory Map Tables;  
VL commnts of StepDirection & PWM Units added;  
PWM Dscription, Registers; StpDir Description, Registers;  
V008  
V009  
2014 Sep 09  
2014 Sep 15  
SK  
SK  
rst information on Digital design top level pins  
Sectn for base slave controller registers added  
Section for general device description added  
Section on Actuator Testboard moved to dedicated  
document  
Sections on MFC Block divided into two sections: One  
section for configuration and access. One section for  
functionality and handling.  
Additional Information on Watchdogs and GPIO block  
registers added  
Added first package drawing and package pin list.  
Added Sections for Applications and Block Diagrams and  
Design Support.  
V009  
V009  
V009  
V009  
2014 Sep 18  
204 Sep 30  
2014 Oct 17  
2014 Oct 17  
LL  
PWM & StpDir register description updated  
SK, SL  
LL  
Added comments from SL on MFCIO Configuration  
PWM parameters updates; S/D parameters updated;  
LL  
Hint to SD_CH#_SR 2th complement and DIR added for  
step-direction unit;  
V009  
V009  
V009  
V009  
2014 Dec 10  
2015 Feb 04  
2015-Feb-06  
2015-Feb-09  
SK  
SK  
BD  
LL  
Separated datasheets for individual product  
Updated and completed pin out table  
Chapter on watchdog timer  
PWM Timing Diagrams added; PWM Timing w/ shift added;  
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Step-Direction (StpDir) Timing Diagrams added  
V009  
V009  
V009  
2015-Feb-10  
2015-Feb-11  
2015-Feb-12  
LL  
LL  
LL  
PWM drawings with 3 PWM channels inserted  
Textual description of PWM  
Textual description of PWM updated, PWM block diagram  
added, table with input and output signals added, block  
diagram of Step Direction unit added, description of step  
direction registers  
V009  
2015-Feb-13  
LL, SK  
OVC at PWM updated; textual description of StpDir unit;  
SK: renamed OVC-Input to nES since it will have impact on  
all output signals  
SK: removed OVC config inputs (will be configured internally  
via registers)  
V010  
2015-Mar-17  
SL  
Updated MFC memory addresses (0x10nn -> 0x40nn; 0x20nn -  
> 0x48nn), also updated/corrected Address sace table  
BBM 0..255 changed to 0ns..2.55µs, BM=0 <=> BBM off  
GPIO Polarity removed, register ddresses uded.  
Watchdog Table with signal asnments added
Updated Vxx and GND pins in pin able.  
Improved Structure and Regiers froBeckhoff added (must  
still be modified and reducwhat is really existent in  
our IC)  
V010  
V010  
2015-Mar-17  
2015-Apr-01  
SL, LL  
SL, SK  
V010  
V011  
2015-Apr-17  
2015-Apr-27  
SK  
SK  
MFCIO configuron regable bits moved from bit 7  
to 4.  
ESC registeadapted actual configuration and TMC8460  
specifics.  
V011  
V011  
2015-Jul-27  
2015-Aug-11  
SL  
SK  
Shadow egister rigger source table updated  
Son “Priciples of Operation” refined and updated  
Sectio“DevicUsage and Handling” updated  
Added Setion for Abbreviations  
Sction 4 & 5 updated  
Collcted many information as screenshots from related  
documents (must still be transformed to text)  
Extended Sections on PDI SPI, MFC CTRL SPI, MFC ABN block,  
and MFC Master SPI block added.  
V012  
2015-Aug-15  
K, SL  
LED description updated.  
EEPROM interface and Ethernet PHY section updated.  
V013  
V014  
2015-Au
201Aug-31  
SK, L  
SK, SL  
Electrical Characteristics updated.  
Layout considerations updated.  
Example circuits updated.  
MFCIO section streamlined and updated with more content  
EtherCAT Register description some updates  
Added additional port/pin figures and tables  
Table 13tation Revisions  
Copyright © 2015 TRINAMIC Motion Control GmbH & Co. KG  

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