TMC8461-BA_技术文档

INTEGRATED CIRCUITS

EtherCAT Slave Controller for

TMC8461 Datasheet

Document Revision V1.4 • 2018-Oct-05

The TMC8461 is a complete EtherCAT^®Slave Controller optimized for real time. It comprises all

blocks required for an EtherCAT slave including two switch regulator power supplies and 24V ca-

pable high voltage I/Os for industrial environments. Timer, watchdog, PWM and SPI/IIC master

units allow for enhanced capabilities either in device emulation mode or in combination with an

external CPU.

Features

•

Standard compliant EtherCAT^®Slave

2 MII Interfaces for external Ether-

net PHY

• SPI Process Data Interface (PDI)

•

IO Block with 24 Multi-Function I/Os

Internal 3.3V plus free 5V-24V switch

regulator

•

8 High Voltage I/Os (up to 35V, 100mA)

Multifunction block comprises Watch-

dog, 4 PWM outputs and Step/Dir

generator

•

Direct EtherCAT access to external

ADCs, stepper motor controllers, etc.

EtherCAT-P compatible voltage range

Applications

• Factory Automation

• Process Automation

• Communication Modules

• Industrial IoT

• Industry 4.0

• Sensors & Encoders

• Robotics

• Industrial Motion Control

• Building Automation

Simpliﬁed Block Diagram

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Contents

1

2

3

Product Features

5

6

7

8

9

Order Codes

Principles of Operation / Key Concepts

3.1 General Device Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3.2 EtherCAT Slave Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3.3 Multi-Function and Control IO Block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3.4 Analog and High Voltage Block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3.5 Interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

3.6 Software- and Tool-Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

4

5

Device Pin Deﬁnitions

15

4.1 Pinout and Pin Coordinates of TMC8461-BA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

4.2 Signal Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

Device Usage and Handling

23

5.1 Process Data Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

5.1.1 SPI protocol description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

5.1.2 Timing example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

5.2 MFC IO Control Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

5.2.1 SPI Protocol description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

5.2.2 Timing example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

5.2.3 Sharing Bus Lines with the PDI SPI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

5.3 Ethernet Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

5.3.1 Ethernet PHYs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

5.4 External Circuitry and Applications Examples . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

5.4.1 Device Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

5.4.2 Supply Filtering for PLL Supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

5.4.3 External Circuit for Fixed Switching Regulator 0 . . . . . . . . . . . . . . . . . . . . . . . 34

5.4.4 External Circuit for Adjustable Switching Regulator 1 . . . . . . . . . . . . . . . . . . . . 35

5.4.5 Minimum External Supply Circuit for Single 3.3V Supply . . . . . . . . . . . . . . . . . . 36

5.4.6 Minimum External Supply Circuit for Single 5V Supply . . . . . . . . . . . . . . . . . . . 37

5.4.7 Minimum External Supply Circuit for Single Supply >5V . . . . . . . . . . . . . . . . . . 38

5.4.8 Typical Power Supply Chain Using Both Buck Converters . . . . . . . . . . . . . . . . . 39

5.4.9 Status LED Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39

5.4.10 SII EEPROM Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40

6

EtherCAT Slave Controller Description

41

6.1 General EtherCAT Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41

6.2 Overview of Available Chip Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42

6.3 EtherCAT Register Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44

6.4 EtherCAT Register Set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50

6.4.1 ESC Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50

6.4.2 Station Address . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54

6.4.3 Write Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55

6.4.4 Data Link Layer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57

6.4.5 Application Layer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62

6.4.6 PDI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65

6.4.7 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69

6.4.8 Error Counters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72

6.4.9 Watchdogs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75

6.4.10 SII EEPROM Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78

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6.4.11 ESC Parameter RAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82

6.4.12 MII Management Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83

6.4.13 FMMUs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87

6.4.14 SyncManagers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90

6.4.15 Distributed Clocks Receive Times . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94

6.4.16 Distributed Clocks Time Loop Control Unit . . . . . . . . . . . . . . . . . . . . . . . . . . 95

6.4.17 Distributed Clocks Cyclic Unit Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99

6.4.18 Distributed Clocks SYNC Out Unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100

6.4.19 Distributed Clocks LATCH In Unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104

6.4.20 Distributed Clocks SyncManager Event Times . . . . . . . . . . . . . . . . . . . . . . . . 108

6.4.21 ESC Speciﬁc . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109

6.4.22 Process Data RAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110

7

MFC IO Block Description

111

7.1 General Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111

7.2 MFC IO Register Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113

7.3 MFC IO Register Set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116

7.3.1 Incremental Encoder Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116

7.3.2 SPI Master Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119

7.3.3 I2C Master Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121

7.3.4 Step and Direction Signal Generator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123

7.3.5 PWM Unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129

7.3.6 General Purpose I/Os . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133

7.3.7 DAC Unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134

7.3.8 IRQ Control Block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135

7.3.9 Watchdog . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137

7.3.10 High Voltage Status and General Control . . . . . . . . . . . . . . . . . . . . . . . . . . . 140

7.3.11 Application Layer Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 144

7.4 SII EEPROM MFC IO Block Parameter Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 145

7.5 SII EEPROM MFC IO Crossbar Mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 149

7.6 SII EEPROM MFC IO High Voltage IO (HVIO) Conﬁguration . . . . . . . . . . . . . . . . . . . . . 153

7.7 SII EEPROM MFC IO Switching Regulator Conﬁguration . . . . . . . . . . . . . . . . . . . . . . . 154

7.8 SII EEPROM MFC IO Memory Block Mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 156

7.9 SII EEPROM MFC IO Register Conﬁguration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 157

7.10 MFC IO ESI/XML Conﬁguration Block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 158

7.11 MFC IO Incremental Encoder Block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 159

7.12 MFC IO SPI Master Block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 161

7.12.1 SPI Examples . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 162

7.13 MFC IO I2C Master Block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 166

7.13.1 I2C Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 168

7.14 MFC IO Step and Direction Block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 170

7.15 MFC IO PWM Block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 173

7.16 MFC IO DAC Block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 179

7.17 MFC IO General Purpose IO Block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 180

7.18 MFC IO IRQ Block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 181

7.19 MFC IO Watchdog Block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 182

7.20 MFC IO Emergency Switch Input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 186

7.21 MFC IO Analog and High Voltage Block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 187

7.21.1 Multi Voltage High Current I/O Lines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 187

7.21.2 Switching Regulators . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 188

7.21.3 Analog Block Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 189

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8

Electrical Ratings

191

8.1 Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 191

8.2 Operational Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 192

8.3 DC Characteristics and Timing Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . 192

8.3.1 High Voltage I/O Block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 192

8.3.2 Switching Regulators . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 193

8.3.3 Digital IOs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 194

9

Manufacturing Data

195

9.1 Package Dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 195

9.2 Marking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 197

9.3 Board and Layout Considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 197

10 Abbreviations

11 Figures Index

12 Tables Index

198

200

201

204

13 Revision History

13.1 IC Revision . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 204

13.2 Document Revision . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 204

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1 Product Features

TMC8461 is an advanced EtherCAT Slave Controller device used for EtherCAT communication. It provides

the interface for data exchange between EtherCAT master and the slave’s local application controller. In

addition, TMC8461 provides complex IO functions paired with high voltage features.

Advantages:

• Fully standard compliant and proven EtherCAT engine

• Highly integrated with highest feature count vs. package size

• License-free & royalty-free

• High Voltage & robust

• Saves board space & reduces BOM

• Long-term availability

Major Features:

•

EtherCAT Slave Controller with 2 MII ports, 8 FMMU & 8 Sync Managers, Distributed clocks (64

bit), 16KByte ESC RAM size, external I2C EEPROM, SPI Process Data Interface (PDI), optional device

emulation

•

TRINAMIC Multi-Function Control and IO block with 24 conﬁgurable IO ports for complex real-time IO

functions (GPIOs, PWM, Step/Direction, I2C, SPI, DAC, incremental encoder, and high voltage IOs)

TRINAMIC high voltage block with 8 short circuit protected push-/pull or open drain high voltage IOs

for up to 24V and 100mA drive current

Two integrated 500mA step down switching voltage regulators with one being ﬁxed at 3.3V and one

being programmable between 5V and 24V

Simple conﬁguration of EtherCAT Slave Controller and Multi-Function Control and IO block via

SII EEPROM

• Single supply voltage depending on application: 3.3V only or 5V to 35V (5V, 12V, or 24V typical)

• Industrial Temperature Range -40°C to +85°C

• Integrated temperature measurement and over-temperature shutdown

• Package: 10mm x10mm BGA packge with 144 pins and 0.8mm pitch

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2 Order Codes

Order Code

TMC8461-BA

Description

Size

TMC8461 Advanced EtherCAT^®Slave Controller in 144 pin BGA 10mm x 10mm

package with 0.8mm pitch

TMC8461-EVAL Evaluation Board for TMC8461-BA, RJ45 TPC interface, +5V...+24V

79mm x 85mm

Table 1: TMC8461 order codes

Trademark and Patents

EtherCAT^®is a registered trademark and patented technology, licensed by Beckhoﬀ Automation GmbH,

Germany.

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3 Principles of Operation / Key Concepts

TMC8461 is a highly integrated ASIC providing the interface between the Ethernet-based EtherCAT real-time

ﬁeld bus and the local application. Its extended digital and high voltage feature set provides additional

functions to the EtherCAT slave.

3.1 General Device Architecture

Figure 1 shows the general device architecture and major connections of TMC8461. The three func-

tion blocks EtherCAT Slave Controller, Multi-Function Control and IO, and Analog and High Voltage are

introduced in the following sub-sections.

For operation, a stable 100MHz clock source, an IIC EEPROM, and power supply for IO and high voltage

operation are required (if the high voltage features are used). An application controller, which also runs

the EtherCAT slave stack, connects to the SPI interfaces. The application and onboard peripherals can be

controlled by the application controller or the Multi-Function Control and IO block.

Figure 1: General device architecture

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3.2 EtherCAT Slave Controller

TMC8461 contains a standard-conform EtherCAT Slave Controller (ESC) providing real-time EtherCAT MAC

layer functionality to EtherCAT slaves. It connects via MII interface to standard Ethernet PHYs and provides

a digital control interface to a local application controller while also providing the option for standalone

operation.

The ESC part of TMC8461 provides the following EtherCAT-related features. More information is available

in Section 6.

• Two Media Independent Interface (MII) to external Ethernet PHYs

• Eight Fieldbus Memory Management Units (FMMU)

• Eight Sync Managers (SM)

• 16 KByte of Process Data RAM (PDRAM)

• 64B bit Distributed Clocks support

• I2C interface for external EEPROM for ESC conﬁguration

• SPI Process Data Interface (PDI) with 30Mbit/s

• Proven EtherCAT State Machine (ESM)

• Device Emulation Mode

3.3 Multi-Function and Control IO Block

In addition to the EtherCAT functionality, the TMC8461 comes with a dedicated function block providing a

conﬁgurable set of complex real-time IO functionality for smart (embedded) EtherCAT slave systems. This

IO functionality is called Multi-Function Control and IO block (MFC IO). Its special focus is on motor and

motion control while it is not limited to this application area.

The MFC IO block combines various functional sub blocks that are helpful in an embedded design to

reduce complexity, to simplify bill of materials (BOM), and to provide hardware acceleration to compute

intensive or time critical tasks. More information is available in Section 7.

Conﬁgurable IO Ports The whole MFC IO block provides in total 24 IO ports that can be conﬁgured and

assigned to any of the available functional units inside the MFC IO block. If not used, each IO port can be

tristated.

General Purpose IOs Up to sixteen (16) general purpose IOs are available. Each IO can be conﬁgured

either as input or as output. For the outputs, a safe state can be conﬁgured which is used in case of

emergency event.

Incremental Encoder Interface Conﬁgurable incremental encoder interface with 32 bit position regis-

ters, single-ended or diﬀerential inputs, conﬁgurable counting constant for diﬀerent resolutions, conﬁg-

urable polarity and N-signal behavior.

Step/Direction Generator Block The step and direction unit provides upt to 3 independent channels.

Various conﬁguration options and modes allow for example for continuous or one-shot mode, reading of

the internal total step counters, pre-loading the next step frequency to be used at a certain counter value.

The step and direction outputs signals can be single-ended or diﬀerential.

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PWM Block The integrated PWM block provides up to 4 PWM channels. PWM frequency and duty cycle

as well as polarities and dead times are conﬁgurable. The outputs can be conﬁgured for a safe state in

case of emergency.

Generic SPI Master Interface The TMC8461 provides a generic SPI master interface to connect to on-

or oﬀ-board SPI slave peripherals like ADCs, sensors, or motor drivers. The SPI master interface is fully

conﬁgurable and oﬀers 4 slave select lines.

Generic I2C Master Interface A generic I2C master interface is also available in TMC8461 to connect to

I2C slaves. The I2C bus speed is conﬁgurable.

Digital DAC A simple digital 16 bit DAC channel is available which requires an external RC circuit for

operation.

Safety Functions The following safety functions are available with the TMC8461

•

Conﬁgurable watchdog functionality for the MFC IO block to monitor internal and external signals as

well as EtherCAT activity. This block is fully conﬁgurable.

A general emergency switch input can be activated. For critical outputs, a safe state can be conﬁgured

which is used when the emergency switch triggers.

A common IRQ signal is available at the MFC IO block which can be mapped to various events of the

MFC IO block. The IRQ events can be processed by a local application controller.

3.4 Analog and High Voltage Block

TMC8461 has an integrated powerful high voltage sub block that provides analog functions and high

voltage support to your EtherCAT slave. The integrated high voltage capabilities allow for BOM reduction

and save board space. More information is available in Section 7.21.

High Voltage Ports 8 of the 24 conﬁgurable IO ports of the MFC IO block are high voltage IO ports. For

pure digital systems operating at 3.3V or 5V these ports can simply be used as standard IO ports. When

using a higher supply voltage at the VIOx inputs the high voltage ports can be used at up to 35V (5V, 12V,

24V typical). The 8 high voltage ports are grouped into 3 groups with 2, 3, and 3 ports. Each group can be

used a diﬀerent supply voltage level using VIO1, VIO2, and VIO3 inputs.

Each high voltage port has a short circuit protected push-/pull or open drain output stage with 100mA

drive (ca. 200mA short time) and can be combined with any signal of the MFC IO block functions. The

outputs’ slope can be controlled. An optional input ﬁlter is selectable as well as pull downs or pull ups with

100µA.

The high voltage ports have an over-temperature shutdown.

When driving inductive loads a freewheeling diode must be provided to the high

voltage I/O pins to prevent from latch-up.

WARNING

Switching Regulators Two switching regulators (buck regulators) are integrated into TMC8461 – SW0

and SW1. Both are capable of driving up to 500mA.

SW0 generates a ﬁxed 3.3V rail for internal and external logic supply. SW1 is programmable between 3.3V

and VS (up to 24V) and can be used for peripheral supply, e.g, to generate a 5V encoder supply.

Each switching regulator comes with a separate over-temperature shutdown.

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Single Supply Operation TMC8461 is designed to work with a single external power supply rail. All

required supply voltages are generated internally. The required external supply rail depends on the

application scenario (between 3.3V and 24V).

3.5 Interfaces

ESC Process Data Interface The ESC part can be accessed via the so-called Process Data Interface (PDI).

TMC8461 comes with an SPI PDI. Besides the standard SPI bus lines additional control signals belong to

the SPI PDI, which are further described in Section 5.1..

MFC IO Control Interface The MFC IO block of TMC8461 can be accessed from EtherCAT master side

or from the local application controller. For connection to the local application controller, a second SPI

interface – the MFC IO SPI – is provided. The protocol used nearly identical to the SPI PDI interface.

Additional information on the MFC IO SPI is given in Section 5.2.

Ethernet PHY Connection TMC8461 provides 2 communication ports and connects to 100Mbit Ethernet

PHYs via MII running at 25MHz.

In addition, each PHY can be connected to the PHY Management Interface (MI) for functions like link state

detection when not using dedicated LINK signals.

EEPROM Interface The EEPROM interface is intended to be a point-to-point interface between TMC8461

and EEPROM with TMC8461 being the master. If other I2C masters are required to access the I2C bus,

TMC8461 must be held in reset state, for example for in-circuit-programming of the EEPROM. During

operation, the application controller must tristate its I2C interface. Depending on the EEPROM size the

addressing mode must be properly set using the PROM_SIZE conﬁguration pin.

Conﬁguration Inputs Hard-wired conﬁguration pins are available at the TMC8461, which are used to

conﬁgure various options related to the hardware conﬁguration and application scenario and which will not

change. These pins are PROM_SIZE, MII_TX_SHIFT[x], PHY_OFFSET, LINK_POLARITY, PDI_SHARED_SPI_BUS,

and DEVICE_EMULATION.

More information on these conﬁguration pins and signals is given in Section 4.2 and Section 5.

3.6 Software- and Tool-Support

TRINAMIC’s EtherCAT Slave Controller family comes with extensive hardware and software tool support to

get started quickly.

Evaluation Board An evaluation board is available for the TMC8461. The evaluation board comes with

on-board 100-Mbit Ethernet PHYs and standard RJ45 connectors and transformers for interfacing twisted

pair copper (TPC) media.

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Figure 2: TMC8461 Evaluation Board

The complete board design ﬁles are available for download and can be used as reference. All information

is available for download from the evaluation board section on TRINAMIC’s website at

https://www.trinamic.com/support/eval-kits/.

Breakout Board (BOB) Besides the Evaluation board another smaller breakout board is available. It

allows for easy integration into own systems or connection to a prototyping platform. The breakout

board provides the bus interface along with the ESC and requires an appropriate supply and controller

connection. The BOB comes with standard RJ45 connectors to connect to TPC using the TMC8462 ESC

with integrated Ethernet PHYs. TMC8462 is functionally equal to the TMC8461. The diﬀerence is in using

external PHYs vs. integrated PHYs. The complete board design ﬁles are available for download and can

be used as reference. All information is available for download from the evaluation board section on

TRINAMIC’s website at

https://www.trinamic.com/support/eval-kits/.

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Figure 3: TMC8462 breakout board for RJ45 and TPC

TRINAMIC Technology Access Package In addition, a comprehensive source code and software package

– TRINAMIC Technology Access Package (TTAP) – is available for download to get started quickly with own

code.

The TTAP is available at https://www.trinamic.com/support/software/access-package/.

TMCL-IDE The TMCL-IDE is TRINAMIC’s primary tool (for Windows PCs) to control TRINAMIC modules and

evaluation boards. Besides, it provides feature like remote ﬁrmware updates, module monitoring options,

and speciﬁc Wizard support. The TMCL-IDE can be used along with TRINAMICs modular evaluation board

system.

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Figure 4: TMCL-IDE

The latest version and additional information is available for download from TRINAMIC’s website at

http://www.trinamic.com/software-tools/tmcl-ide.

EtherCAT Slave Conﬁguration Conﬁguration of the EtherCAT Slave Controller is done during boot time

with conﬁguration information read from the SII EEPROM after reset or power cycling. This information

must be (pre)programmed into the SII EEPROM. This can be done via the EtherCAT master using a so-called

EtherCAT Slave Information (ESI) ﬁle in standardized XML format. The SII EEPROM can also be (re)written

using the local application controller.

Wizard The TMCL-IDE contains a wizard to assist users with the conﬁguration of the TMC8461 various

MFC IO functions. The wizard shows available and allowed options and provides XML code snippets for

the ESI ﬁle for the SII EEPROM as well as generic C-Code blocks. These can be used as starting point for

own ﬁrmware development for the application controller.

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Figure 5: Conﬁguration wizard example – MFC IO block conﬁguration

Figure 6: Conﬁguration wizard example – SII EEPROM content and C-code output

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4 Device Pin Deﬁnitions

4.1 Pinout and Pin Coordinates of TMC8461-BA

1

2

3

4

5

6

7

8

9

10 11 12

A

B

C

D

E

F

G

H

J

K

L

M

Figure 7: TMC8461-BA Pinout top view

4.2 Signal Descriptions

Name

J8

Type (I,O,PU,PD) Function

General Signals

NRESET

I/O

Low active system reset. NRESET is an I/O

pin. Connected to VCCIO via a 10K resistor and

to GND via a 10nF capacitor if no other reset

source for proper power-on reset is used. For

more information see Section 5.4.1.

REF_CLK100_IN

M4

H8

I

100MHz Reference clock input, connect to a

clock source <25ppm.

CLK16_OUT

O

16.6MHz auxiliary clock output. Not available

during reset.

EN_CLK16_OUT

CLK25_OUT0

CLK25_OUT1

G10

E3

I

Enable signal for CLK16_OUT: 0 = oﬀ, 1 = on

25MHz clock output, e.g., for IN port PHY

25MHz clock output, e.g., for OUT port PHY

O

H3

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Name

K8

Type (I,O,PU,PD) Function

RESET_OUT

O

This high-active reset output is activated via

EtherCAT register 0x0040), therefore RESET_OUT

has to trigger the NRESET input, which clears

RESET_OUT. This connection incl. changing the

polarity has to be made externally .

EEPROM IOs

PROM_INIT

J7

J5

J6

E9

O

I/O

I

Signal indicating that EEPROM has been loaded,

0 = not ready, 1 = EEPROM loaded

PROM_CLK

PROM_DATA

PROM_SIZE

External I2C EEPROM clock signal, use 1K pull

up resistor to 3.3V

External I2C EEPROM data signal, use 1K pull

up resistor to 3.3V

Selects between two diﬀerent EEPROM sizes

since the communication protocol for EEPROM

access changes if a size > 16k is used (an addi-

tional address byte is required then). 0 = up to

16K EEPROM, 1 = 32 kbit-4Mbit EEPROM

DC Synchronization IOs

SYNC_OUT0

D8

O

Distributed Clocks synchronization output 0,

Typically connect to MCU

SYNC_OUT1

E8

Distributed Clocks synchronization output 1, typ-

ically connect to MCU

LATCH_IN0

LATCH_IN1

C8

C7

I

Latch input 0 for distributed clocks, connect to

GND if not used.

Latch input 1 for distributed clocks, Connect to

GND if not used.

LEDs

LED_RUN

C5

C4

D4

D5

O

Run Status LED, connect to green LED (Anode) 0

= LED oﬀ, 1 = LED on

LED_ERR

Error Status LED, connect to red LED (Anode) 0

= LED oﬀ, 1 = LED on

LINK_ACT0

LINK_ACT1

Link In Port Activity, connect to green LED (An-

ode) 0 = LED oﬀ, 1 = LED on

Link Out Port Activity, connect to green LED (An-

ode) 0 = LED oﬀ, 1 = LED on

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Name

Type (I,O,PU,PD) Function

Process Data Interface IOs to/from MCU

PDI_SOF

L4

O

I

Ethernet Start-of-Frame if 1

Ethernet End-of-Frame if 1

PDI_EOF

K4

M5

L5

PDI_SPI_CSN

PDI_SPI_SCK

PDI_SPI_MOSI

Chip select signal of the process data interface

Serial clock signal of the process data interface

I

M6

I

Serial data out signal of the process data inter-

face

PDI_SPI_MISO

PDI_SPI_IRQ

L6

K5

O

Serial data in signal of the process data interface

Interrupt signal for primary process data inter-

face, Connect to MCU

PDI_WDSTATE

H7

H6

H9

O

I

Watchdog state, 0: Expired, 1: Not expired

Watchdog trigger if 1

PDI_WDTRIGGER

PDI_EMULATION

Selects between PDI interface (SPI) or stan-

dalone operation with state machine emulation

inside ESC. Has weak internal pull down. 0 =

default, PDI interface active, 1 = standalone op-

eration, state machine emulation

MFC IO Control Interface IOs

MFC_CTRL_SPI_CSN

MFC_CTRL_SPI_SCK

D6

E4

I

Chip select signal of the MFC IO control interface

Serial clock signal of the MFC IO control interface

MFC_CTRL_SPI_MOSI D7

Serial data out signal of the MFC IO control in-

terface

MFC_CTRL_SPI_MISO E5

O

Serial data in signal of the MFC IO control inter-

face

MFC_IRQ

E6

C6

MFCIO block IRQ for conﬁgurable events, con-

nect to MCU, high active

MFC_NES

I

low active (not) Emergency Stop/Switch/Halt (to

bring PWM or other outputs into a safe state),

the event must be cleared actively, has weak in-

ternal pull down, must be driven high for normal

operation

PDI_SHARED_BUS

F10

I

Selects between separate SPI buses (MISO,

MOSI, SCK) or one SPI bus with two CS lines

for the PDI and MFC CTRL SPI interface: 0 = two

separate SPI buses, 1 = one shared SPI bus using

the PDI_SPI_x bus lines

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Name

Type (I,O,PU,PD) Function

MFC IOs

MFCIO00

MFCIO01

MFCIO02

MFCIO03

MFCIO04

MFCIO05

MFCIO06

MFCIO07

MFCIO08

MFCIO09

MFCIO10

MFCIO11

MFCIO12

MFCIO13

MFCIO14

MFCIO15

K9

I/O

MFCIO block low voltage I/O

K10

K11

K12

J9

MFCIO block low voltage I/O

J10

J11

J12

D9

D10

D11

D12

C9

C10

C11

C12

MFC High Voltage IOs

MFC_HV0 (MFCIO16) A5

MFC_HV1 (MFCIO17) A6

MFC_HV2 (MFCIO18) A7

MFC_HV3 (MFCIO19) A8

MFC_HV4 (MFCIO20) A9

MFC_HV5 (MFCIO21) A10

MFC_HV6 (MFCIO22) A11

MFC_HV7 (MFCIO23) A12

I/O

MFCIO block high voltage I/O

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Name

Type (I,O,PU,PD) Function

MFC High Voltage IO Supplies

VIO1

B6

I

MFCHVIO block 1 supply voltage

VIO2

B8

MFCHVIO block 2 supply voltage

MFCHVIO block 3 supply voltage

VIO3

B10

B7

GNDIO1

GNDIO2

GNDIO3

MFCHVIO block 1 ground, connect to GND

MFCHVIO block 2 ground, connect to GND

MFCHVIO block 3 ground, connect to GND

B9

B11

MII Interface to external PHY (EtherCAT IN Port)

MII_LINK0

C1

C2

A2

A1

B2

B1

B3

A3

D2

D1

E2

E1

F2

F1

I

Link indication input

Receive clock

MII_RX_CLK0

MII_RXD0[0]

MII_RXD0[1]

MII_RXD0[2]

MII_RXD0[3]

MII_RX_DV0

MII_RX_ERR0

MII_TX_CLK0

MII_TXD0[0]

MII_TXD0[1]

MII_TXD0[2]

MII_TXD0[3]

MII_TX_ENA0

I

Receive data bit 0

Receive data bit 1

Receive data bit 2

Receive data bit 3

Receive data valid signal

Receive error signal

Transmit clock

I

O

Transmit data bit 0

Transmit data bit 1

Transmit data bit 2

Transmit data bit 3

Transmit enable

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Name

Type (I,O,PU,PD) Function

MII Interface to external PHY (EtherCAT OUT Port)

MII_LINK1

K2

K1

H1

H2

J1

I

Link indication input

Receive clock

MII_RX_CLK1

MII_RXD1[0]

MII_RXD1[1]

MII_RXD1[2]

MII_RXD1[3]

MII_RX_DV1

MII_RX_ERR1

MII_TX_CLK1

MII_TXD1[0]

MII_TXD1[1]

MII_TXD1[2]

MII_TXD1[3]

MII_TX_ENA1

I

Receive data bit 0

Receive data bit 1

Receive data bit 2

Receive data bit 3

Receive data valid signal

Receive error signal

Transmit clock

I

J2

I

G2

G1

L1

I

L2

O

Transmit data bit 0

Transmit data bit 1

Transmit data bit 2

Transmit data bit 3

Transmit enable

M1

M2

L3

M3

PHY Interface Conﬁguration Pins and Management Interface

LINK_POLARITY

MII_TX_SHIFT[0]

MII_TX_SHIFT[1]

H10

H12

G12

I

selects polarity of the PHYs link signal: 0 = low

active, 1 = high active

Used for clock shift compensation on TX port,

Weak internal pull down

Used for clock shift compensation on TX port,

Weak internal pull down

PHY_OFFSET

MCLK

E10

F3

I

PHY Address Oﬀset: 0 = Oﬀset = 0, 1 = Oﬀset =

1

O

I/O

PHY management clock, connect all PHYs to this

bus

MDIO

G3

PHY management data, connect all PHYs to this

bus if required, use 4K7 pull up resistor to VC-

CIO (3.3V)

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Name

Type (I,O,PU,PD) Function

Device Supply and Ground

VS

B12

I

Supply voltage, use a 100nF ﬁlter capacitor

VCCIO

C3, D3,

I/O supply voltage, use a 100nF ﬁlter capacitor

per pin

E11, F11,

G11, H11,

J3, K3

VCC_CORE

E7, F6, F7,

I

Core supply voltage, connect to VDD1V8_OUT,

use a 100nF ﬁlter capacitor per pin

G6, G7

L7

PLLCLK_VCCIO

TSTCLK_SELECT

GND

I

PLL supply voltage, connect to VCCIO through

a ﬁlter (R/L/C)

K6

Test input, always connect to VCCIO for nor-

mal operation

B4, F4,

F5, F8,

F9, G4,

G5, G8,

G9, J4

K7

Supply Ground

PLLCLK_GND

I

PLL supply ground, connect to GND

Voltage Regulator IOs

VDD1V8_OUT

F12

E12

O

Output of internal 1.8V regulator, use a 100nF

ﬁlter capacitor

VDD5_OUT

Output of internal 5V regulator, use a 100nF

ﬁlter capacitor if VS≥5V

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Name

Type (I,O,PU,PD) Function

Switching Regulator 0 IOs

VS0

M8

I

Switching regulator 0 supply voltage, Switching

regulator 0 provides a ﬁxed 3.3V output.

GND0

M10

M9

L8

I

Switching regulator 0 ground, connect to GND

Switching regulator 0 output, ﬁxed 3.3V

SW0

O

I

SW_DIODE

Switching regulator 0 internal diode, connect

to SW0 only if VS0 is at or below 5V

GND_DIODE

L9

I

Switching regulator 0 internal diode ground,

connect to GND

Switching Regulator 1 IOs

VS1

M12

I

Switching regulator 1 supply voltage, Switching

regulator 1 provides an adjustable output volt-

age.

GND1

SW1

L10

M11

L11

I

Switching regulator 1 ground, connect to GND

O

I

Switching regulator 1 output, adjustable

VOUT

Switching regulator 1 inductor ringing suppres-

sion feedback

VOUT_FB

L12

I

Switching regulator 1 feedback voltage, 1.2V typ-

ically

Test Pins only

TST_MODE

TST_ANA

H4

H5

M7

I

Test mode enable, connect to GND

Analog Test output, leave open

100MHz clock output

O

CLKO_100

Unused Pins

–

A4, B5

–

not connected, can be connected to ground or

other signal for better layout

Table 2: Pin and Signal description for TMC8461-BA

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5 Device Usage and Handling

5.1 Process Data Interface

The Process Data Interface (PDI) is an SPI interface with a clock frequency of up to 30 MHz. The ESC

registers and the process data RAM can be accessed from an external microcontroller using this interface.

The interface can be conﬁgured via the EEPROM, however it is recommended to use the default conﬁgura-

tion – SPI mode 3, low active chip select). For further details, see the ESC SPI slave conﬁguration registers

in Section 6.

Additionally some signals are available that can be evaluated by the application controller.

Figure 8: PDI control signals

TMC8461 pin

PDI_SPI_CSN

PDI_SPI_SCK

PDI_SPI_MOSI

PDI_SPI_MISO

PDI_SPI_IRQ

Description

Typical pin on a MCU

SPI chip select for the TMC8461 PDI

SPI master clock

SSx

SCK

Master out slave in data

Master in slave out data

Conﬁgurable IRQ from PDI

MOSI

MISO

General purpose Input

PDI_EMULATION

0: default mode for complex slaves, state

machine changes processed in microcontroller

ﬁrmware; 1: device emulation mode for, e.g.,

simple slaves, state machine changes directly

handled in the ESC

General purpose Output

or connected to either

ground or 3.3V.

PDI_SOF

PDI_EOF

Indicates start of an Ethernet/EtherCAT frame

Indicates end of an Ethernet/EtherCAT frame

General purpose Input

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TMC8461 pin

Description

Typical pin on a MCU

PDI_WDSTATE

PDI_WDTRIGGER

0: Watchdog expired; 1: Watchdog not expired

Watchdog triggered if ’1’

General purpose Input

Table 3: PDI signal description

5.1.1 SPI protocol description

Each SPI datagram contains a 2- or 3-byte address/command part and a data part. For addresses below

0x2000, the 2-byte addressing mode can be used, the 3 byte addressing mode can be used for all addresses.

C2 C1 C0 Command

0

1

0

1

0

1

0

1

0

1

0

1

0

1

NOP (no operation, no following data bytes)

Reserved

Read

Read with wait state byte

Write

Reserved

Address extension, signaling 3 byte mode

Reserved

Table 4: PDI SPI commands

Address

Command

A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0

C2 C1 C0

A12 A11 A10 A9 A8 A7 A6 A5

A4 A3 A2 A1 A0 C2 C1 C0

Byte 0

Byte 1

Figure 9: PDI SPI 2 byte addressing

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Address

Command

A15 A14 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0

C2 C1 C0

A12 A11 A10 A9 A8 A7 A6 A5

A4 A3 A2 A1 A0

A15 A14 A13 C2 C1 C0

1

0

Address

extension

command

Reserved

Byte 0

Byte 1

Byte 2

Figure 10: PDI SPI 3 byte addressing

Unless highest performance is required, using only the 3-byte addressing mode and the read with wait

state command is recommended since it reduces the need for special cases in the software. During the

address/command bytes, the ESC replies with the contents of the event request registers (0x0220

and in 3 byte addressing mode 0x0222).

, 0x0221

Command 0 - NOP

This command can be used for checking the event request registers and resetting the PDI watchdog

without a read or write access.

Example datagram:

0x00 0x00

Example reply (AL Control event bit is set): 0x01 0x00

Command 2 - READ

With the read command, an arbitrary amount of data can be read from the device. The ﬁrst byte read is

the data from the address given by the address/command bytes. With every read byte, the address is

incremented. During the data transfer, the SPI master sends 0x00 except for the last byte where a 0xFF is

sent.

When using this command, a pause of 240ns or more must be included between the address/command

bytes and the data bytes for the ESC to fetch the requested data.

Example datagram (Read from address 0x0120 and 0x0121): 0x09 0x02 0x00 0xFF

Example reply (Operational State requested):

0x01 0x00 0x08 0x00

Command 3 - READ WITH WAIT STATE BYTE

This command is similar to the Read command with an added dummy byte between the address/command

part and the data part of the datagram. This allows enough time to fetch the data in any case.

Example datagram (Read starting at address 0x3400): 0xA0 0x06 0x2C 0xFF 0x00 0x00 0x00 0xFF

Example reply (0xXX is undeﬁned data):

0x00 0x00 0x00 0xXX 0x44 0x41 0x54 0x41

Command 4 - WRITE

The write command allows writing of an arbitrary number of bytes to writable ESC registers or the process

data RAM. It requires no wait state byte or delay after the address/command bytes. After every transmitted

byte, the address is incremented.

Example datagram (Write starting at address 0x4200): 0x10 0x06 0x50 0x4C 0x48

Example reply (0xXX is undeﬁned data):

0x00 0x00 0x00 0xXX 0xXX

Address 0x4200 now contains 0x4C, Address 0x4201 contains 0x48

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Command 6 - ADDRESS EXTENSION

The address extension command is mainly used for the 3-byte addressing mode as shown in Figure 10.

For SPI masters that can only process datagrams with an even number of bytes, it might be necessary to

pad the datagram to an even number of bytes. This can be achieved by duplicating the third byte of the

3-byte address/command part and using the address extension command in all but the last duplicate.

For example, a SPI master that is only capable of transmitting a multiple of 4 bytes cannot use the example

datagram for a write access above since it contains 5 bytes. With three added padding bytes, the master

has to transmit two 4-byte groups.

Example datagram (Write starting at address 0x4200): 0x10 0x06 0x58 0x58 0x58 0x50 0x4C 0x48

Example reply (0xXX is undeﬁned data):

0x00 0x00 0x00 0xXX 0xXX 0xXX 0xXX 0xXX

5.1.2 Timing example

This example shows a generic read access with wait state and 2 byte addressing. All conﬁgurable options

are shown. The delays between the transferred bytes are just to show the byte boundaries and are not

required.

CSN active low

CSN active high

SCK mode 0

SCK mode 1

SCK mode 2

SCK mode 3

A

9

A

8

A

7

A

6

A

5

A

4

A

3

A

2

A

1

A

0

C

2

C

1

C

0

MOSI

12 11 10

MISO mode 0/2

normal sample

I

7

I

6

I

5

I

4

I

3

I

2

I

1

I

0

I

9

I

8

D

7

D

6

D

5

D

4

D

3

D

2

D

1

D

0

D

9

D

8

15 14 13 12 11 10

MISO mode 0/2

late sample

I

7

I

6

I

5

I

4

I

3

I

2

I

1

I

0

I

9

I

8

D

7

D

6

D

5

D

4

D

3

D

2

D

1

D

0

D

9

D

8

S

15 14 13 12 11 10

MISO mode 1/3

normal sample

I

7

I

6

I

5

I

4

I

3

I

2

I

1

I

0

I

9

I

8

D

7

D

6

D

5

D

4

D

3

D

2

D

1

D

0

D

9

D

8

S

15 14 13 12 11 10

MISO mode 1/3

late sample

I

7

I

6

I

5

I

4

I

3

I

2

I

1

I

0

I

9

I

8

D

7

D

6

D

5

D

4

D

3

D

2

D

1

D

0

D

9

D

8

S

15 14 13 12 11 10

Figure 11: SPI timing example

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5.2 MFC IO Control Interface

The MFC IO block of the TMC8461 comes with a dedicated SPI slave interface to allow direct access from

a local application controller. It is called MFC CTRL SPI interface. This interface to the MFC IO block’s

functions is always available, even if the EtherCAT state machine is currently not in operational state (OP).

Protocol structure and timing are identical to the PDI SPI.

The MFC Control SPI is a SPI mode 3 slave with low active chip select. The SPI clock frequency can be up to

30MHz. The following diagram shows all signals related to the MFC CTRL SPI interface.

Figure 12: MFC control signals

TMC8461 pin

Description

Typical pin on a MCU

MFC_CTRL_SPI_CSN

MFC_CTRL_SPI_SCK

MFC_CTRL_SPI_MOSI

MFC_CTRL_SPI_MISO

MFC_IRQ

SPI chip select for the TMC8461 PDI

SPI master clock

SSx

SCK

Master out slave in data

Master in slave out data

Conﬁgurable IRQ from MFCIO block

MOSI

MISO

General purpose Input

PDI_SHARED_BUS

0: separate SPI buses for PDI and MFC CTRL; 1:

shared/common SPI bus for PDI and MFC CTRL

General purpose Output

or connected to either

with 2 CSN signals using the PDI SPI bus. The SPI ground or 3.3V.

bus signals MFC_CTRL_SPI_SCK,

MFC_CTRL_SPI_MISO, MFC_CTRL_SPI_MOSI can

be left open in this case

Table 5: MFC CTRL SPI signal description

5.2.1 SPI Protocol description

The protocol of the MFC CTRL SPI is the same as the PDI SPI interface (see section 5.1.1) The addresses for

register access are calculated using the register number and the byte number in each register. To calculate

the address, the register number is shifted left by 4 bits and the byte number is added as the 4 lowest bits.

Access using the 3 byte addressing mode is possible, and can be used when 2 byte mode is not imple-

mented for the PDI SPI but since the highest bits of the address are always 0, accessing the MFC Control

SPI via 2 byte mode is suﬃcient.

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6

Figure 13: MFC CTRL SPI 2 byte addressing

6

Figure 14: MFC CTRL SPI 3 byte addressing

5.2.2 Timing example

This example shows a generic MFC register read access with wait state. The delays between the transferred

bytes are just to show the byte boundaries and are not required.

Figure 15: MFC SPI timing example

5.2.3 Sharing Bus Lines with the PDI SPI

To reduce the number of signals on the PCB or if the local application controller has only one SPI interface,

the MFC CTRL SPI bus can share the SPI bus signals of the PDI SPI, requiring only separate chip select

signals. In this case, both interfaces are internally switched to the PDI SPI interface pins. The original MFC

CTRL SPI signals (MOSI, MISO, and SCK) remain unconnected in this case. Only the MFC_CTRL_SPI_CSN

pin/signal must be used if the MFCIO block is accessed.

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To share the SPI bus lines, conﬁguration pin PDI_SHARED_BUS must be pulled high as shown in the ﬁgure

below.

Figure 16: SPI bus sharing

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5.3 Ethernet Interface

For connection to the Ethernet physical medium and to the EtherCAT master, the TMC8461 oﬀers two

MII ports (media independent interface) and connects to standard 100Mbit/s Ethernet PHYs or 1Gbit/s

Ethernet PHYs running in 100Mbit/s mode.

Figure 17: MII pins

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TMC8461 pin

Description

MII_LINKx

Active link input signal, active high/active low determined by

LINK_POLARITY pin

MII_RX_CLKx

MII_RXDx[3:0]

MII_RX_DVx

MII_RX_ERRx

MII_TX_ENAx

MII_TX_CLKx

MII_TXDx[3:0]

MCLK

Receive clock input

Receive data inputs (4 bit wide)

Receive data valid input

Receive error input

Transmit enable output

Transmit clock input, optional for automatic phase compensation

Transmit data output (4 bit wide)

PHY conﬁguration clock output

MDIO

PHY conﬁguration data in-/output

MII_TX_SHIFT[1:0]

PHY_OFFSET

LINK_POLARITY

Phase compensation of MII TX signals, tie either to GND or VCCIO

PHY Address Oﬀset, tie either to GND or VCCIO

Active level of MII_LINKx signal, tie either to GND or VCCIO

Table 6: MII signal description

LINK_POLARITY

This pin allows conﬁguring the polarity of the link signal of the PHY. PHYs of diﬀerent manufacturers may

use diﬀerent polarities at the PHY’s pins.

In addition, some PHYs allow for bootstrap conﬁguration with pull-up and pull-down resistors. This boot-

strap information is used by the PHY at power-up/reset and also inﬂuences the polarity of the original pin

function.

PHY_OFFSET The TMC8461 addresses Ethernet PHYs using logical port number plus PHY address oﬀset.

Typically, the Ethernet PHY addresses should correspond with the logical port number, so PHY addresses 0

to 1 are used.

A PHY address oﬀset of 1 can be applied (PHY_OFFSET = ’1’) which moves the PHY addresses to a range of

1 to 2. The TMC8461 expects logical port 0 to have PHY address 0 plus PHY address oﬀset.

MII_TX_SHIFT[1:0] TMC8461 and Ethernet PHYs share the same clock source. TX_CLK from the PHY has a

ﬁxed phase relation to the MII interface TX part of TMC8461. Thus, TX_CLK must not be connected and the

delay of the TX FIFO is saved. In order to fulﬁll the setup/hold requirements of the PHY, the phase shift

between TX_CLK and MII_TX_ENAx and MII_TXDx[3:0] has to be controlled.

•

Manual TX Shift compensation with additional delays for MII_TX_ENAx/MII_TXDx[3:0] of 10, 20,

or 30 ns. Such delays can be added using the TX Shift feature and applying MII_TX_SHIFT[1:0].

MII_TX_SHIFT[1:0] determine the delay in multiples of 10 ns for each port. Set MII_TX_CLKx to zero if

manual TX Shift compensation is used.

•

Automatic TX Shift compensation if the TX Shift feature is selected: connect MII_TX_CLKx and the

automatic TX Shift compensation will determine correct shift settings. Set MII_TX_SHIFT[1:0] to 0 in

this case.

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5.3.1 Ethernet PHYs

The TMC8461 requires Ethernet PHYs with MII interface.

The MII interface of the TMC8461 is optimized for low additional delays by omitting a transmit FIFO.

Therefore, additional requirements to Ethernet PHYs exist and not every Ethernet PHY is suited.

Please see the Ethernet PHY Selection Guide provided by the ETG: https://download.beckhoff.com/

download/Document/io/ethercat-development-products/an_phy_selection_guidev2.3.pdf

The TMC8461 has been successfully tested in combination with the following Ethernet PHYs:

• IC+ IP101GA

• Micrel KSZ8721BLI

• Micrel KSZ8081

For best performance, the PHYs should be clocked using the 25MHz clock outputs CLK_25MHz_OUT_x of

TMC8461.

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5.4 External Circuitry and Applications Examples

5.4.1 Device Reset

The NRESET signal should at least be connected to VCCIO via a 10K resistor and to GND via a 10nF capacitor

if no other controlled reset source for proper power-on behavior and reset is used.

VCCIO (3.3V)

TMC8461

10kΩ

NRESET

10nF

Figure 18: Minimum external circuit for power-on reset

5.4.2 Supply Filtering for PLL Supply

The internal PLL is supplied with the same 3.3V as used for VCCIO. An R/L/C ﬁlter structure as shown in the

circuit diagram is used. PLLCLK_GND is connected to common ground.

VCCIO (3.3V)

TMC8461

TSTCLK_SELECT

PLLCLK_VCCIO

600 Ω @100MHz

1 Ω

100nF

PLLCLK_GND

Figure 19: PLL supply ﬁlter

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5.4.3 External Circuit for Fixed Switching Regulator 0

Switching regulator 0 is an internal buck switching regulator and generates a ﬁxed 3.3V supply with approx-

imately 500mA. This 3.3V supply shall be used to power VCCIO and PLLCLK_VCCIO. This regulator comes

with an integrated Schottky diode which minimizes part count, when an external 5V supply is available.

This 3.3V can also be used to power other on-board devices, e.g., EEPROM or LEDs. The 3.3V rail is available

at switching regulator 0 output SW0.

More information on the switching regulators is given in Section 7.21.

VS=5V

TMC8461

VS0

SW0

22µH

3.3V out

SW_DIODE

GND_DIODE

22µF

47µF

GND0

Figure 20: External circuit for switching regulator 0 with VS0 = 5V

VS>5V

TMC8461

VS0

SW0

22µH

3.3V out

SW_DIODE

GND_DIODE

22µF

47µF

GND0

Figure 21: External circuit for switching regulator 0 with VS0 > 5V

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5.4.4 External Circuit for Adjustable Switching Regulator 1

Switching regulator 1 is an internal buck switching regulator and generates an adjustable supply rail with

approximately 500mA. The voltage at SW1 can be adjusted using a resistor network in the switching

regulator’s feedback path at VOUT_FB. VOUT_FB should be at 1.2V using a resistor divider. SW1 can be

used to power the high voltage IOs using VIO1, VIO2, VIO3 as well as switching regulator 0 input VS0 (which

generates a ﬁxed 3.3V rail). SW1 can also be used to power other peripheral devices, e.g., Hall signals of a

BLDC motor or external encoders.

More information on the switching regulators is given in Section 7.21.

VS

TMC8461

VS1

22µH

adj. out

SW1

100kΩ

22µF

47µF

VOUT

4.7kΩ

VOUT_FB

GND1

Figure 22: External circuit for adjustable buck regulator

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5.4.5 Minimum External Supply Circuit for Single 3.3V Supply

The diagram shows the minimum external circuit when using a single 3.3V supply only.

Both internal switching regulators are not used in this example. Therefore, both supply ports VS0 and VS1

are not connected.

The high voltage IOs are also not used in this example. Therefore, the three high voltage IO supply ports

VIO1, VIO2, and VIO3 are not connected.

VS=3.3V

TMC8461 Supply

VDD5_OUT

VS

100nF

VS0

VS1

SW1

VOUT

4x VCCIO

VOUT_FB

4x100nF

GND1

600 Ω @100MHz

1 Ω

PLLCLK_VCCIO

VDD1V8_OUT

SW0

SW_DIODE

GND_DIODE

100nF

1.8V

GND0

100nF

10x GND

4x VCC_CORE

PLLCLK_GND

4x100nF

VIO1/2/3

GNDIO1/2/3

Figure 23: Minimum external supply circuit for single 3.3V supply

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5.4.6 Minimum External Supply Circuit for Single 5V Supply

The diagram shows the minimum external circuit when using a single 5V supply only.

Switching regulator 0 is used to generate the 3.3V for VCCIO and PLLCLK_VCCIO.

Switching regulator 1 is not used in this example. Therefore, supply port VS1 is not connected.

The high voltage IOs are also not used in this example. Therefore, the three high voltage IO supply ports

VIO1, VIO2, and VIO3 are not connected.

VS=5V

TMC8461 Supply

VDD5_OUT

VS

100nF

SW1

VOUT

VS0

VOUT_FB

VS1

GND1

3.3V

1.8V

3.3V

4x VCCIO

22µH

22µF

4x100nF

SW0

SW_DIODE

GND_DIODE

1 Ω

600 Ω @100MHz

47µF

PLLCLK_VCCIO

VDD1V8_OUT

4x VCC_CORE

VIO1/2/3

100nF

GND0

100nF

10x GND

PLLCLK_GND

4x100nF

GNDIO1/2/3

Figure 24: Minimum external supply circuit for single 5V supply

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5.4.7 Minimum External Supply Circuit for Single Supply >5V

To connect TMC8461 to a single supply greater than 5V the circuit is very similar to Figure 24. The main

diﬀerence is that an additional external diode (MSS1P6) is required at output SW0. The pin SW_DIODE is

open.

VS>5V

TMC8461 Supply

VDD5_OUT

VS

100nF

SW1

VOUT

VS0

VOUT_FB

VS1

3.3V

1.8V

GND1

4x VCCIO

3.3V

4x100nF

22µH

1 Ω

SW0

SW_DIODE

GND_DIODE

600 Ω @100MHz

PLLCLK_VCCIO

22µF

47µF

100nF

GND0

VDD1V8_OUT

4x VCC_CORE

VIO1/2/3

100nF

10x GND

PLLCLK_GND

4x100nF

GNDIO1/2/3

Figure 25: Minimum external supply circuit for single supply >5V

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5.4.8 Typical Power Supply Chain Using Both Buck Converters

VS

VS, VS1, VIO1, VIO2, VIO3

5V. . . 24V

Adj. buck converter

5V. . . 24V, <VS

VS0, VIO1, VIO2, VIO3

VCCIO

3.3V buck converter

3.3V

1.8V linear converter

1.8V

VCC_CORE

Figure 26: Typical power supply chain using both buck converters

5.4.9 Status LED Circuit

The TMC8461has 4 status LED outputs. All outputs are supplied from VCCIO (3.3V), and drive a LED with

current limiting resistor to GND. The use of low current LED is recommended to keep supply current low

and to stay within the current limit of 10mA per pin. The appropriate resistor value must be chosen for the

selected LED’s forward voltage.

For a 2V forward voltage at 2mA, a value of 680 Ohm is a reasonable value.

The LED colors are deﬁned by ETG.1300 (available on www.ethercat.org).

TMC8461 LED outputs

680 Ω

LED_RUN

680 Ω

LED_ERR

680 Ω

LINK_ACT0

680 Ω

LINK_ACT1

Figure 27: Status LED circuit

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5.4.10 SII EEPROM Circuit

An I²C EEPROM is required for operation with the SII interface. Its size can be up to 4MBit. While the

access protocol of the I²C EEPROMs is standardized, the addressing procedure changes from one address

byte up to 16kBit to two address bytes from 32kBit. Up to 16kBit the PROM_SIZE pin must be tied to GND,

above that, it must be tied to VCCIO (3.3V).

3.3V

SII EEPROM

VCC

1k Ω

TMC8461 SII EEPROM signals

WP

PROM_SIZE

PROM_CLK

GND or 3.3V

Signal to uC

SCL

SDA

A2

A1

100nF

A0

PROM_INIT

PROM_DATA

GND

Figure 28: SII EEPROM circuit (shown for EEPROMs >32kBit)

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6 EtherCAT Slave Controller Description

6.1 General EtherCAT Information

TMC8461 contains a standard-conform EtherCAT Slave Controller (ESC) providing real-time EtherCAT

MAC layer functionality to EtherCAT slave devices. The ESC part of TMC8461 provides the following

EtherCAT-related features:

•

16 KByte of Process Data RAM (PDRAM): The PDRAM is a dual ported RAM, which allows exchange of

data between the EtherCAT master and the local application.

•

Eight Sync Managers (SM): Sync Managers are used to control and secure the data exchange via the

PDRAM in terms of data consistency, data security, and synchronized read/write operations on the

data objects. Two modes –buﬀered mode and mailbox mode – are available.

•

Eight Fieldbus Memory Management Units (FMMU): FMMUs are used for mapping of logical addresses

to physical addresses. The EtherCAT master uses logical addressing for data than spans multiple

slaves. An FMMU can map such a logical address range to a continuous local physical address range.

64 bit Distributed Clock support (DC): DC is the base of the real-time capability of EtherCAT. Their

underlying algorithms compute delay times between the master and the slaves and between slaves

and update a common time stamp in all slaves. This way, synchronized time stamps (LATCH0/1) and

synchronized trigger signals (SYNC0/1) are available in every slave and to the master.

•

IIC interface for external SII EEPROM for ESC conﬁguration: After reset and at power up, the ESC

requires reading basic (and advanced) conﬁguration data from an external SII EEPROM to properly

conﬁgure interfaces, operation modes, and and feature availability. The SII EEPROM may be read and

written by the master or the local application controller as well.

SPI Process Data Interface (PDI): The PDI is the interface between the local application controller

and the ESC. Application-speciﬁc process data and EtherCAT control and status information for the

EtherCAT State Machine (ESM) is exchanged via this interface.

• Device Emulation Mode: This mode is a special mode of operation where no ESM in the application

controller is required. The slave’s operation states are simply directly set by the master without

control of an ESM. This is beneﬁcial for small and simple slaves, for example simple IO devices.

To manufacture own slaves devices, a registration with the EtherCAT Technology Group (ETG) is required.

More information and resources on the EtherCAT technology and the EtherCAT standard are available

here:

• EtherCAT Technology Group (ETG) (http://www.ethercat.org/)

• EtherCAT is standardized by the IEC (http://www.iec.ch/) and ﬁled as IEC-Standard 61158.

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6.2 Overview of Available Chip Features

The following table shows EtherCAT chip features available in TRINAMIC’s EtherCAT slave controller solu-

tions.

Chip Feature / Description

Domain

Register

Extended DL control register 0x0102:0x0103 enabled

AL Status code register 0x0134:0x0135 enabled

ECAT interrupt mask 0x0200:0x0201 enabled

Conﬁgured station alias 0x0012:0x0013 enabled

General purpose inputs 0x0F18:0x0F1F enabled

General purpose outputs 0x0F10:0x0F17 enabled

AL event mask 0x0204:0x0207 enabled

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

Physical RD/WR oﬀset 0x0108:0x0109 enabled

Bridge port PDI (0x07) enabled

Writable Watchdog divider 0x0400:0x0401 and Watchdog PDI Watchdog

0x0410:0x0411 enabled

Watchdog counters 0x0442:0x0444 enabled

ECAT write protection 0x0020:0x0031 enabled

Reset registers 0x0040:0x0041 enabled

FPGA update at 0x0E00 enabled

Watchdog

1

0

1

0

1

0

1

0

1

0

1

0

Ext. Function

DC Sync event times enabled

ECAT processing unit and PDI error counters/PDI error code Ext. Function

0x030C:0x030E enabled

User RAM disabled

Ext. Functions

PHY Layer

PHY layer

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1: POR Values, 0: VENDOR ID

EEPROM control by PDI enabled

Lost link counters 0x0310:0x0313 enabled

MII management interface 0x0510 enabled

Enhanced link detection for MII enabled

Link detection and conﬁguration for MII enabled

PDI support for MII management interface enabled

Automatic MII TX shift enabled

PHY layer

Extended RX Error counter registers 0x0314:0x0317 and PHY layer

0x0320:0x0327 enabled

RUN LED enabled

LEDs

1

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Chip Feature / Description

Domain

LEDs

PDI

Link/activity LEDs enabled

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

Port error LEDs enabled

0

1

0

1

0

RUN/ERR LED override registers 0x0138:0x0139 enabled

Conﬁgurable SPI PDI modes enabled

Digital IO output register 0x0F00:0x0F03 disabled

PDI user mode registers 0x0158/0x015C enabled

DC Latch unit enabled

PDI

DC

External DC speed counter diﬀ direct control register 0x0938 DC

enabled

DC Sync unit enabled

DC

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

DC time loop control by PDI enabled

DC with external local clock enabled

EEPROM emulation enabled

DC

EEPROM

Removable PDI (socket communication) enabled

EEPROM RAM/ROM instead of I2C/emulation enabled

Parameter loading to 0x0580 enabled

EEPROM streaming support enabled

8 Byte EEPROM read data enabled

Conﬁgurable EEPROM SIZE enabled

Extended ESC conﬁguration register 0x0142:0x0143 (EEPROM EEPROM

word 5) enabled

Table 7: Available EtherCAT Chip Features (0 = not available/disabled, 1 = available/enabled

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6.3 EtherCAT Register Overview

TMC8461 has an address space of 20 KByte. The ﬁrst block of 4KByte (0x0000:0x0FFF) is reserved for the

standard ESC- and EtherCAT-relevant conﬁguration and status registers. The Process Data RAM (PDRAM)

starts at address 0x1000. TMC8461 has a Process Data RAM of 16 Kbyte.

Address

Length

(Byte)

Description

ESC Information

Type

0x0000

1

2

1

2

0x0001

Revision

0x0002:0x0003

0x0004

Build

FMMUs supported

SyncManagers supported

RAM Size

0x0005

0x0006

0x0007

Port Descriptor

ESC Features supported

0x0008:0x0009

Station Address

0x0010:0x0011

0x0012:0x0013

2

Conﬁgured Station Address

Conﬁgured Station Alias

Write Protection

0x0020

0x0021

0x0030

0x0031

1

Write Register Enable

Write Register Protection

ESC Write Enable

ESC Write Protection

Data Link Layer

ESC Reset ECAT

0x0040

1

4

2

0x0041

ESC Reset PDI

0x0100:0x0103

0x0108:0x0109

0x0110:0x0111

ESC DL Control

Physical Read/Write Oﬀset

ESC DL Status

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Address

Length

(Byte)

Description

Application Layer

AL Control

0x0120:0x0121

0x0130:0x0131

0x0134:0x0135

0x0138

2

1

AL Status

AL Status Code

RUN LED Override

ERR LED Override

0x0139

PDI

0x0140

1

4

PDI Control

0x0141

ESC Conﬁguration

0x014E:0x014F

0x0150

PDI Information

PDI SPI Slave Conﬁguration

SYNC/LATCH PDI Conﬁguration

Extended PDI SPI Slave Conﬁguration

0x0151

0x0152:0x0153

Interrupts

0x0200:0x0201

0x0204:0x0207

0x0210:0x0211

0x0220:0x0223

2

4

2

4

ECAT Event Mask

AL Event Mask

ECAT Event Request

AL Event Request

Error Counters

0x0300:0x0307

0x0308:0x030B

0x030C

4x2

4x1

1

RX Error Counter[3:0]

Forward RX Error Counter[3:0]

ECAT Processing Unit Error Counter

PDI Error Counter

0x030D

1

0x030E

1

PDI Error Code

0x0310:0x0313

4x1

Lost Link Counter[3:0]

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Address

Length

(Byte)

Description

Watchdogs

0x0400:0x0401

0x0410:0x0411

0x0420:0x0421

0x0440:0x0441

0x0442

2

1

Watchdog Divider

Watchdog Time PDI

Watchdog Time Process Data

Watchdog Status Process Data

Watchdog Counter Process Data

Watchdog Counter PDI

0x0443

SII EEPROM Interface

EEPROM Conﬁguration

EEPROM PDI Access State

EEPROM Control/Status

EEPROM Address

0x0500

1

0x0501

0x0502:0x0503

0x0504:0x0507

0x0508:0x050F

2

4

4/8

EEPROM Data

MII Management Interface

MII Management Control/Status

PHY Address

0x0510:0x0511

0x0512

2

1

2

1

4

0x0513

PHY Register Address

0x0514:0x0515

0x0516

PHY Data

MII Management ECAT Access State

MII Management PDI Access State

PHY Port Status

0x0517

0x0518:0x051B

0x0580:0x05FF

128

ESC Parameter RAM

0x0580:0x05FF

128 max. TMC8xxx MFC IO Block Conﬁguration

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Address

Length

(Byte)

Description

0x0600:0x06FF

+0x0:0x3

+0x4:0x5

+0x6

16x16

FMMU[15:0]

Logical Start Address

Length

4

2

1

2

1

3

Logical Start bit

Logical Stop bit

Physical Start Address

Physical Start bit

Type

+0x7

+0x8:0x9

+0xA

+0xB

+0xC

Activate

+0xD:0xF

Reserved

0x0800:0x087F

+0x0:0x1

+0x2:0x3

+0x4

16x8

SyncManager[15:0]

Physical Start Address

Length

2

1

Control Register

Status Register

Activate

+0x5

+0x6

+0x7

PDI Control

0x0900:0x09FF

Distributed Clocks (DC)

DC Receive Times

Receive Time Port 0

Receive Time Port 1

Receive Time Port 2

Receive Time Port 3

0x0900:0x0903

0x0904:0x0907

0x0908:0x090B

0x090C:0x090F

4

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Address

Length

(Byte)

Description

DC Time Loop Control Unit

System Time

0x0910:0x0917

0x0918:0x091F

0x0920:0x0927

0x0928:0x092B

0x092C:0x092F

0x0930:0x0931

0x0932:0x0933

0x0934

4/8

4

Receive Time ECAT Processing Unit

System Time Oﬀset

System Time Delay

4

System Time Diﬀerence

Speed Counter Start

2

Speed Counter Diﬀ

1

System Time Diﬀerence Filter Depth

Speed Counter Filter Depth

0x0935

1

DC Cyclic Unit Control

0x0980

1

Cyclic Unit Control

DC SYNC Out Unit

Activation

0x0981

1

2

0x0982:0x0983

0x0984

Pulse Length of SYNC signals

Activation Status

SYNC0 Status

1

0x098E

1

0x098F

1

SYNC1 Status

0x0990:0x0997

4/8

Start Time Cyclic Operation / Next

SYNC0 Pulse

0x0998:0x099F

0x09A0:0x09A3

0x09A4:0x09A7

4/8

4

Next SYNC1 Pulse

SYNC0 Cycle Time

SYNC1 Cycle Time

4

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Address

Length

(Byte)

Description

DC LATCH In Unit

0x09A8

1

Latch0 Control

0x09A9

Latch1 Control

0x09AE

1

Latch0 Status

0x09AF

1

Latch1 Status

0x09B0:0x09B7

0x09B8:0x09BF

0x09C0:0x09C7

0x09C8:0x09CF

4/8

Latch0 Time Positive Edge

Latch0 Time Negative Edge

Latch1 Time Positive Edge

Latch1 Time Negative Edge

DC SyncManager Event Times

EtherCAT Buﬀer Change Event Time

PDI Buﬀer Start Event Time

0x09F0:0x09F3

0x09F8:0x09FB

0x09FC:0x09FF

4

PDI Buﬀer Change Event Time

0x0E00:0x0EFF

0x0E00:0x0E07

0x0E08:0x0E0F

256

8

ESC Speciﬁc

Product ID

Vendor ID

8

0x0F80:0x0FFF

128

20

User RAM

0x0F80:0x0FFF

reserved

Process Data RAM

0x1000:0xFFFF

1-60KB

Process Data RAM

Table 8: TMC8461 EtherCAT Registers

For Registers longer than one byte, the LSB has the lowest and MSB the highest address.

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6.4 EtherCAT Register Set

6.4.1 ESC Information

6.4.1.1 Type (0x0000)

Bit

Description

ECAT

PDI

Reset Value

7:0

Type of EtherCAT controller

r/-

TMC8460: 0xD0

TMC8461: 0xD0

TMC8462: 0xD0

TMC8670: 0xD0

Table 9: Register 0x0000 (Type)

6.4.1.2 Revision (0x0001)

Bit

Description

Revision of EtherCAT controller

ECAT

PDI

Reset Value

7:0

r/-

TMC8460: 0x60

TMC8461: 0x61

TMC8462: 0x61

TMC8670: 0x70

Table 10: Register 0x0001 (Revision)

6.4.1.3 Build (0x0002:0x0003)

Bit

Description

ECAT

PDI

r/-

Reset Value

15:0

Actual build of EtherCAT controller,

minor version, maintenance version

r/-

TMC8460: 0x10

TMC8461: 0x11

TMC8462: 0x11

TMC8670: 0x10

Table 11: Register 0x0002 (Build)

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6.4.1.4 FMMUs supported (0x0004)

Bit

Description

ECAT

PDI

Reset Value

7:0

Number of supported FMMU channels (or enti- r/-

ties) of the EtherCAT slave controlller.

r/-

TMC8460: 6

TMC8461: 8

TMC8462: 8

TMC8670: 4

Table 12: Register 0x0004 (FMMUs)

6.4.1.5 SyncManagers supported (0x0005)

Bit

Description

ECAT

PDI

Reset Value

7:0

Number of supported SyncManager channels r/-

(or entities) of the EtherCAT Slave Controller

r/-

TMC8460: 6

TMC8461: 8

TMC8462: 8

TMC8670: 4

Table 13: Register 0x0005 (SMs)

6.4.1.6 RAM Size (0x0006)

Bit

Description

ECAT

PDI

Reset Value

7:0

Process Data RAM size supported by the Ether- r/-

CAT Slave Controller in KByte

r/-

TMC8460: 16

TMC8461: 16

TMC8462: 16

TMC8670: 4

Table 14: Register 0x0006 (RAM Size)

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6.4.1.7 Port Descriptor (0x0007)

Bit

Description

ECAT

PDI

Reset Value

Port conﬁguration:

00: Not implemented

01: Not conﬁgured (SII EEPROM)

10: EBUS

11: MII RMII RGMII

1:0

3:2

7:4

Port 0

r/-

TMC8460: 11

TMC8461: 11

TMC8462: 11

TMC8670: 11

Port 1

TMC8460: 11

TMC8461: 11

TMC8462: 11

TMC8670: 11

not supported

0

Table 15: Register 0x0007 (Port Descriptor)

6.4.1.8 ESC Features supported (0x0008:0x0009)

Bit

Description

ECAT

PDI

Reset Value

0

FMMU Operation:

0: Bit oriented

1: Byte oriented

r/-

1

2

Reserved

r/-

Distributed Clocks:

0: Not available

1: Available

3

4

Distributed Clocks (width):

0: 32 bit

r/-

1: 64 bit

Low Jitter EBUS:

0: Not available, standard jitter

1: Available, jitter minimized

0

5

6

Enhanced Link Detection EBUS:

0: Not available

1: Available

r/-

Enhanced Link Detection MII

0: Not available

1: Available

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Bit

Description

ECAT

PDI

Reset Value

7

Separate Handling of FCS Errors:

0: Not supported

r/-

1: Supported, frames with wrong FCS and ad-

ditional nibble will be counted separately in

Forwarded RX Error Counter

8

Enhanced DCSYNC Activation

0: Not available

1: Available

r/-

NOTE: This feature refers to registers

0x981.(7:3), 0x0984

9

EtherCAT LRW command support:

0: Supported

r/-

1: Not Supported

10

11

EtherCAT read/write command support

0: Supported

1: Not Supported

Fixed FMMU/SyncManager conﬁguration

0: Variable conﬁguration

1: Fixed conﬁguration (refer to documentation

of supporting ESCs)

15:12 Reserved

r/-

Table 16: Register 0x0008:0x0009 (ESC Features)

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6.4.2 Station Address

6.4.2.1 Conﬁgured Station Address (0x0010:0x0011)

Bit

Description

ECAT

PDI

Reset Value

15:0

Address used for node addressing (FPxx com- r/w

mands)

r/-

Table 17: Register 0x0010:0x0011 (Station Addr)

6.4.2.2 Conﬁgured Station Alias (0x0012:0x0013)

Bit

Description

ECAT

PDI

Reset Value

15:0

Alias Address used for node addressing

(FPxx commands)

r/-

r/w

The use of this alias is activated by Register

DL Control Bit 24 (0x0100.24/0x0103.0)

NOTE: EEPROM value is only taken over

at ﬁrst EEPROM load after power- on reset.

Table 18: Register 0x0012:0x0013 (Station Alias)

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6.4.3 Write Protection

6.4.3.1 Write Register Enable (0x0020)

Bit

Description

ECAT

PDI

Reset Value

0

If write register protection is enabled, this reg- r/w

ister has to be written in the same Ethernet

frame (value does not care) before other writes

to this station are allowed. Write protection

is still active after this frame (if Write Register

Protection register is not changed).

r/-

7:1

Reserved, wirte 0

r/-

Table 19: Register 0x0020 (Write Register Enable)

6.4.3.2 Write Register Protection (0x0021)

Bit

Description

ECAT

PDI

Reset Value

0

Write register protection:

0: Protection disabled

1: Protection enabled

Registers 0x0000-0x0137

r/w

r/-

,

0x013A-0x0F0F are

write protected, except for 0x0030

7:1

Reserved, write 0

r/-

Table 20: Register 0x0021 (Write Register Prot.)

6.4.3.3 ESC Write Enable (0x0030)

Bit

Description

ECAT

PDI

Reset Value

0

If ESC write protection is enabled, this register r/w

has to be written in the same Ethernet frame

(value does not care) before other writes to this

station are allowed. ESC write protection is still

active after this frame (if ESC Write Protection

register is not changed).

r/-

7:1

Reserved, write 0

r/-

Table 21: Register 0x0030 (ESC Write Enable)

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6.4.3.4 ESC Write Protection (0x0031)

Bit

Description

ECAT

PDI

Reset Value

15:0

Write protect:

r/w

r/-

0: Protection disabled

1: Protection enabled

All areas are write protected, except for 0x0030

.

7:1

Reserved, write 0

r/-

Table 22: Register 0x0031 (ESC Write Prot.)

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6.4.4 Data Link Layer

6.4.4.1 ESC Reset ECAT (0x0040)

Bit

Description

ECAT

PDI

Reset Value

Write

7:0

Reset is asserted after writing 0x52 (’R’), 0x45 r/w

(’E’), 0x53 (’S’) in this register with 3 consecutive

frames.

r/-

Read

1:0

Progress of the reset procedure:

01: after writing 0x52

10: after writing 0x45 (if 0x52 was written)

00: else

r/w

r/-

7:2

Reserved, write 0

r/-

Table 23: Register 0x0040 (ESC Reset ECAT)

6.4.4.2 ESC Reset PDI (0x0041)

Bit

Description

ECAT

PDI

Reset Value

Write

7:0

Reset is asserted after writing 0x52 (’R’), 0x45 r/-

(’E’), 0x53 (’S’) in this register with 3 consecutive

commands.

r/w

Read

1:0

Progress of the reset procedure:

01: after writing 0x52

10: after writing 0x45 (if 0x52 was written)

00: else

r/-

r/w

r/-

7:2

Reserved, write 0

r/-

Table 24: Register 0x0041 (ESC Reset PDI)

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6.4.4.3 ESC DL Control (0x0100:0x0103)

Bit

Description

ECAT

PDI

Reset Value

0

Forwarding rule:

r/-

0: EtherCAT frames are processed,

Non-EtherCAT frames are forwarded without

processing

1: EtherCAT frames are processed, Non-

EtherCAT frames are destroyed

The source MAC address is changed for every

frame (SOURCE_MAC[1] is set to 1 - locally ad-

ministered address) regardless of the forward-

ing rule.

1

Temporary use of settings in Register 0x101:

0: permanent use

r/-

1: use for about 1 second, then revert to previ-

ous settings

7:2

9:8

Reserved, write 0

r/-

Loop Port 0:

r/w*

00: Auto

01: Auto Close

10: Open

11: Closed

Note Loop open means sending/receiving over

this port is enabled, loop closed means send-

ing/receiving is disabled and frames are for-

warded to the next open port internally. Auto:

loop closed at link down, opened at link up

Auto Close: loop closed at link down, opened

with writing 01 again after link up (or receiving

a valid Ethernet frame at the closed port) Open:

loop open regardless of link state Closed: loop

closed regardless of link state

11:10 Loop Port 1:

00: Auto

r/w*

r/-

01: Auto Close

10: Open

11: Closed

13:12 Loop Port 2:

00: Auto

01: Auto Close

10: Open

11: Closed

15:14 Loop Port 3:

00: Auto

01: Auto Close

10: Open

11: Closed

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Bit

Description

ECAT

PDI

Reset Value

18:16 RX FIFO Size (ESC delays start of forwarding r/w

r/-

until FIFO is at least half full). RX FIFO Size/RX

delay reduction** :

Value (for MII):

0: -40 ns

1: -40 ns

2: -40 ns

3: -40 ns

4: no change

5: no change

6: no change

7: default default

NOTE: EEPROM value is only taken over

at ﬁrst EEPROM load after power-on or reset

19

EBUS Low Jitter:

r/w

r/-

0

0: Normal jitter / 1: Reduced jitter

21:20 Reserved, write 0

r/w

r/-

22

EBUS remote link down signaling time:

0: Default (≈660 ms)

1: Reduced (≈80 µs)

23

24

Reserved, write 0

r/w

r/-

Station alias:

0: Ignore Station Alias

1: Alias can be used for all conﬁgured address

command types (FPRD, FPWR, . . . )

31:25 Reserved, write 0

r/-

Table 25: Register 0x0100:0x0103 (DL Control)

* Loop conﬁguration changes are delayed until end of currently received or transmitted frame at the port.

** The possibility of RX FIFO Size reduction depends on the clock source accuracy of the ESC and of every

connected EtherCAT/Ethernet devices (master, slave, etc.). RX FIFO Size of 7 is suﬃcient for 100ppm

accuracy, FIFO Size 0 is possible with 25ppm accuracy (frame size of 1518/1522 Byte).

6.4.4.4 Physical Read/Write Oﬀset (0x0108:0x0109)

Bit

Description

ECAT

PDI

Reset Value

15:0

Oﬀset of R/W Commands (FPRW, APRW) r/w

between Read address and Write address.

RD_ADR = ADR and WR_ADR = ADR + R/W-

Oﬀset 0

r/-

Table 26: Register 0x0108:0x0109 (R/W Oﬀset)

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6.4.4.5 ESC DL Status (0x0110:0x0111)

Bit

Description

ECAT

PDI

Reset Value

0

PDI operational/EEPROM loaded correctly:

0: EEPROM not loaded, PDI not operational (no

access to Process Data RAM)

r*/-

r/-

1: EEPROM loaded correctly, PDI operational

(access to Process Data RAM)

1

2

PDI Watchdog Status:

0: Watchdog expired

1: Watchdog reloaded

r*/-

r/-

Enhanced Link detection:

0: Deactivated for all ports

1: Activated for at least one port

NOTE: EEPROM value is only taken over at ﬁrst

EEPROM load after power-on or reset

3

4

Reserved

r*/-

r/-

Physical link on Port 0:

0: No link

1: Link detected

5

Physical link on Port 1:

0: No link

r*/-

r/-

1: Link detected

6

Physical link on Port 2:

0: No link

1: Link detected

7

Physical link on Port 3:

0: No link

1: Link detected

8

Loop Port 0:

0: Open

1: Closed

9

Communication on Port 0:

0: No stable communication

1: Communication established

10

11

12

13

Loop Port 1:

0: Open

1: Closed

Communication on Port 1:

0: No stable communication

1: Communication established

Loop Port 2:

0: Open

1: Closed

Communication on Port 2:

0: No stable communication

1: Communication established

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Bit

Description

ECAT

PDI

Reset Value

14

Loop Port 3:

0: Open

1: Closed

r*/-

r/-

15

Communication on Port 3:

0: No stable communication

1: Communication established

r*/-

r/-

Table 27: Register 0x0110:0x0111 (DL Status)

* Reading DL Status register from ECAT clears ECAT Event Request 0x0210.2.

Register Port 3

Port2

Port1

Port 0

No link, closed

0x0111

0x55

0x56

0x59

0x5A

0x65

0x66

0x69

0x6A

0x95

0x96

0x99

0x9A

0xA5

0xA6

0xA9

0xAA

0xD5

0xD6

0xD9

0xDA

No link, closed

Link, open

No link, closed

Link, open

No link, closed

Link, open

No link, closed

Link, open

No link, closed

Link, open

No link, closed

Link, open

No link, closed

Link, open

No link, closed

Link, open

No link, closed

Link, open

No link, closed

Link, open

No link, closed

Link, open

No link, closed

Link, open

No link, closed

Link, open

No link, closed

Link, open

Link, closed

No link, closed

Link, open

No link, closed

Link, open

No link, closed

Link, open

Table 28: Decoding port state in ESC DL Status register 0x0111 (typical modes only)

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6.4.5 Application Layer

6.4.5.1 AL Control (0x0120:0x0121)

Bit

Description

ECAT

PDI

Reset Value

3:0

Initiate State Transition of the Device State Ma- r/(w)

chine:

1: Request Init State

r/

(wack)*

3: Request Bootstrap State

2: Request Pre-Operational State

4: Request Safe-Operational State

8: Request Operational State

4

Error Ind Ack:

0: No Ack of Error Ind in AL status register

1: Ack of Error Ind in AL status register

r/(w)

r/

(wack)*

4

Device Identiﬁcation:

0: No request

1: Device Identiﬁcation request

r/

(wack)*

15:6

Reserved, write 0

r/

(wack)*

Table 29: Register 0x0120:0x0121 (AL Cntrl)

Note

AL Control register behaves like a mailbox if Device Emulation is oﬀ (0x0140.8=0):

The PDI has to read/write* the AL Control register after ECAT has written it.

Otherwise ECAT cannot write again to the AL Control register. After Reset, AL

Control register can be written by ECAT. (Regarding mailbox functionality, both

registers 0x0120 and 0x0121 are equivalent, e.g. reading 0x0121 is suﬃcient to

make this register writeable again.)

If Device Emulation is on, the AL Control register can always be written,

its content is copied to the AL Status register.

* PDI register function acknowledge by Write command is disabled: Reading AL

Control from PDI clears AL Event Request 0x0220.0. Writing to this register from

PDI is not possible.

PDI register function acknowledge by Write command is enabled: Writing AL

Control from PDI clears AL Event Request 0x0220.0. Writing to this register from

PDI is possible; write value is ignored (write 0).

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6.4.5.2 AL Status (0x0130:0x0131)

Bit

Description

ECAT

PDI

Reset Value

3:0

Actual State of the Device State Machine:

1: Init State

r*/-

r/(w)

3: Request Bootstrap State

2: Pre-Operational State

4: Safe-Operational State

8: Operational State

4

Error Ind:

r*/-

r/(w)

0: Device is in State as requested or Flag

cleared by command

1: Device has not entered requested State or

changed State as result of a local action

5

Device Identiﬁcation:

0: Device Identiﬁcation not valid

1: Device Identiﬁcation loaded

r*/-

r/(w)

15:6

Reserved, write 0

Table 30: Register 0x0130:0x0131 (AL Status)

Note

AL Status register is only writable from PDI if Device Emulation is oﬀ (0x0140.8=0),

otherwise AL Status register will reﬂect AL Control register values.

* Reading AL Status from ECAT clears ECAT Event Request 0x0210.3.

6.4.5.3 AL Status Code (0x0134:0x0135)

Bit

Description

ECAT

PDI

Reset Value

15:0

AL Status Code

r/-

r/w

Table 31: Register 0x0134:0x0135 (AL Status Code)

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6.4.5.4 RUN LED Override (0x0138)

Bit

Description

ECAT

PDI

Reset Value

3:0

LED code: (FSM State)

0x0: Oﬀ (1-Init)

r/w

0x1-0xC: Flash 1x - 12x (4-SafeOp 1x)

0xD: Blinking (2-PreOp)

0xE: Flickering (3-Bootrap)

0xF: On

4

Enable Override:

0: Override disabled

1: Override enabled

r/w

7:5

Reserved, write 0

Table 32: Register 0x0138 (RUN LED Override)

Note

Changes to AL Status register (0x0130) with valid values will disable RUN LED

Override (0x0138.4=0). The value read in this register always reﬂects current LED

output.

6.4.5.5 ERR LED Override (0x0139)

Bit

Description

ECAT

PDI

Reset Value

3:0

LED code:

0x0: Oﬀ

r/w

0x1-0xC: Flash 1x - 12x

0xD: Blinking

0xE: Flickering

0xF: On

4

Enable Override:

0: Override disabled

1: Override enabled

r/w

7:5

Reserved, write 0

Table 33: Register 0x0139 (ERR LED Override)

Note

New error conditions will disable ERR LED Override (0x0139.4=0). The value read

in this register always reﬂects current LED output.

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6.4.6 PDI

6.4.6.1 PDI Control (0x0140)

Bit

Description

ECAT

PDI

Reset Value

7:0

Process data interface:

r/-

TMC8460, TMC8461,

TMC8462, TMC8670: 0x00

0x00: Interface deactivated (no PDI)

. . .

later EEPROM ADR 0x0000

0x05: SPI Slave

. . .

0x80: On-chip bus

only SPI Slave (0x05) is

supported in the hardware

Others: Reserved

Table 34: Register 0x0140 (PDI Control)

6.4.6.2 ESC Conﬁguration (0x0141)

Bit

Description

ECAT

PDI

Reset Value

0

Device emulation (control of AL status):

0: AL status register has to be set by PDI

1: AL status register will be set to value written

to AL control register

r/w

r/-

1

Enhanced Link detection all ports:

0: disabled (if bits [7:4]=0)

1: enabled at all ports (overrides bits [7:4])

r/-

2

3

4

5

6

7

Distributed Clocks SYNC Out Unit:

r/-

0: disabled (power saving) / 1: enabled

Distributed Clocks Latch In Unit:

0: disabled (power saving) / 1: enabled

Enhanced Link port 0:

0: disabled (if bit 1=0) / 1: enabled

Enhanced Link port 1:

0: disabled (if bit 1=0) / 1: enabled

Enhanced Link port 2:

0: disabled (if bit 1=0) / 1: enabled

Enhanced Link port 3:

0: disabled (if bit 1=0) / 1: enabled

Table 35: Register 0x0141 (ESC Conﬁg)

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6.4.6.3 PDI Information (0x014E:0x014F)

Bit

Description

ECAT

PDI

Reset Value

0

PDI register function acknowledge by write:

r/w

r/-

Depends on conﬁguration

0: Disabled

1: Enabled

1

PDI conﬁgured:

r/w

r/-

0

0: PDI not conﬁgured

1: PDI conﬁgured (EEPROM loaded)

2

3

PDI active:

0: PDI not active

1: PDI active

r/w

r/-

0

PDI conﬁguration invalid:

0: PDI conﬁguration ok

1: PDI conﬁguration invalid

7:4

Reserved

r/w

r/-

0

Table 36: Register 0x014E (PDI Information))

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6.4.6.4 PDI SPI Slave Conﬁguration (0x0150)

The PDI conﬁguration register 0x0150 and the extended PDI conﬁguration registers 0x0152:0x0153 depend

on the selected PDI. The Sync/Latch[1:0] PDI conﬁguration register 0x0151 is independent of the selected

PDI. The TMC8460, TMC8461, TMC8462, and TMC8670 devices support SPI Slave PDI only.

Bit

Description

ECAT

PDI

Reset Value

1:0

SPI mode:

r/-

00: SPI mode 0

01: SPI mode 1

10: SPI mode 2

11: SPI mode 3

NOTE: SPI mode 3 is recommended for Slave

Sample Code

NOTE: SPI status ﬂag is not available in SPI

modes 0 and 2 with normal data out sample.

3:2

SPI_IRQ output driver/polarity:

00: Push-Pull active low

r/-

01: Open Drain (active low)

10: Push-Pull active high

11: Open Source (active high)

4

5

SPI_CSNL polarity:

0: Active low

r/-

1: Active high

Data Out sample mode:

0: Normal sample (SPI_MISO and SPI_MOSI are

sampled at the same SPI_CLK edge)

1: Late sample (SPI_MISO and SPI_MOSI are

sampled at diﬀerent SPI_CLK edges)

7:6

Reserved, set EEPROM value 0

r/-

Table 37: Register 0x0150 (PDI SPI CFG)

6.4.6.5 SYNC/LATCH Conﬁguration (0x0151)

Bit

Description

ECAT

PDI

Reset Value

1:0

SYNC0 output driver/polarity:

00: Push-Pull active low

r/-

TMC8461: 10

TMC8462: 10

01: Open Drain (active low)

10: Push-Pull active high

11: Open Source (active high)

2

3

SYNC0/LATCH0 conﬁguration:

0: LATCH0 Input

r/-

TMC8461: 1

TMC8462: 1

1: SYNC0 Output

SYNC0 mapped to AL Event Request register r/-

TMC8461, TMC8462: de-

pends on conﬁguration

0x0220.2:

0: Disabled

1: Enabled

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Bit

Description

ECAT

PDI

Reset Value

5:4

SYNC1 output driver/polarity:

00: Push-Pull active low

r/-

TMC8461: 10

TMC8462: 10

01: Open Drain (active low)

10: Push-Pull active high

11: Open Source (active high)

6

7

SYNC1/LATCH1 conﬁguration*:

0: LATCH1 input

r/-

TMC8461: 1

TMC8462: 1

1: SYNC1 output

SYNC1 mapped to AL Event Request register r/-

TMC8461, TMC8462: de-

pends on conﬁguration

0x0220.3:

0: Disabled

1: Enabled

Table 38: Register 0x0151 (SYNC/LATCH CFG)

6.4.6.6 PDI SPI Slave Extended Conﬁguration (0x0152:0x0153)

Bit

Description

ECAT

PDI

Reset Value

15:0

Reserved, set EEPROM value 0

r/-

TMC8461: 0

TMC8462: 0

Table 39: Register 0x0152:0x0153 (PDI SPI extCFG)

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6.4.7 Interrupts

6.4.7.1 ECAT Event Mask (0x0200:0x0201)

Bit

Description

ECAT

PDI

Reset Value

15:0

ECAT Event masking of the ECAT Event Request r/w

Events for mapping into ECAT event ﬁeld of

EtherCAT frames:

r/-

0: Corresponding ECAT Event Request register

bit is not mapped

1: Corresponding ECAT Event Request register

bit is mapped

Table 40: Register 0x0200:0x0201 (ECAT Event M.)

6.4.7.2 AL Event Mask (0x0204:0x0207)

Bit

Description

ECAT

PDI

Reset Value

31:0

AL Event masking of the AL Event Request reg- r/-

ister Events for mapping to PDI IRQ signal:

0: Corresponding AL Event Request register bit

is not mapped

r/w

1: Corresponding AL Event Request register bit

is mapped

Table 41: Register 0x0204:0x0207 (AL Event Mask)

6.4.7.3 ECAT Event Request (0x0210:0x0211)

Bit

Description

ECAT

PDI

Reset Value

0

DC Latch event:

r/-

0: No change on DC Latch Inputs

1: At least one change on DC Latch Inputs (Bit is

cleared by reading DC Latch event times from

ECAT for ECAT controlled Latch Units, so that

Latch 0/1 Status 0x09AE:0x09AF indicates no

event)

1

2

Reserved

r/-

DL Status event:

0: No change in DL Status

1: DL Status change

(Bit is cleared by reading out DL Status

0x0110:0x0111 from ECAT)

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Bit

Description

ECAT

PDI

Reset Value

3

AL Status event:

r/-

0: No change in AL Status

1: AL Status change

(Bit is cleared by reading out AL Status

0x0130:0x0131 from ECAT)

Mirrors values of each SyncManager Status:

0: No Sync Channel 0 event

1: Sync Channel 0 event pending

0: No Sync Channel 1 event

1: Sync Channel 1 event pending

. . .

r/w

r/-

4

5

...

0: No Sync Channel 7 event

1: Sync Channel 7 event pending

15:12 Reserved

r/-

Table 42: Register 0x0210:0x0211 (ECAT Event R.)

6.4.7.4 AL Event Request (0x0220:0x0223)

Bit

Description

ECAT

PDI

Reset Value

0

AL Control event:

r/-

0: No AL Control Register change

1

1: AL Control Register has been written

(Bit is cleared by reading AL Control register

0x0120:0x0121 from PDI)

1

DC Latch event:

0: No change on DC Latch Inputs

r/-

1: At least one change on DC Latch Inputs

(Bit is cleared by reading DC Latch event

times from PDI, so that Latch 0/1 Status

0x09AE:0x09AF indicates no event. Available

if Latch Unit is PDI controlled)

2

3

State of DC SYNC0 (if register 0x0151.3=1):

(Bit is cleared by reading SYNC0 status 0x098E

from PDI, use only in Acknowledge mode)

r/-

State of DC SYNC1 (if register 0x0151.7=1):

(Bit is cleared by reading of SYNC1 status

0x098F from PDI, use only in Acknowledge

mode)

1

AL control event is only generated if PDI emulation is turned oﬀ (PDI Control register 0x0140.8=0)

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Bit

Description

ECAT

PDI

Reset Value

4

SyncManager activation register (SyncManager r/-

register oﬀset 0x6) changed:

0: No change in any SyncManager

r/-

1: At least one SyncManager changed

(Bit is cleared by reading SyncManager Activa-

tion registers 0x0806 etc. from PDI)

5

6

7

EEPROM Emulation:

r/-

0: No command pending

1: EEPROM command pending

(Bit is cleared by acknowledging the command

in EEPROM command register 0x0502 from PDI)

Watchdog Process Data:

0: Has not expired

1: Has expired

(Bit is cleared by reading Watchdog Status Pro-

cess Data 0x0440 from PDI)

Reserved

r/-

SyncManager interrupts (SyncManager register r/-

oﬀset 0x5, bit [0] or [1]):

8

9

0: No SyncManager 0 interrupt

1: SyncManager 0 interrupt pending

0: No SyncManager 1 interrupt

1: SyncManager 1 interrupt pending

. . .

0: No SyncManager 15 interrupt

1: SyncManager 15 interrupt pending

...

23

31:24 Reserved

r/-

Table 43: Register 0x0220:0x0223 (AL Event R.)

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6.4.8 Error Counters

Errors are only counted if the corresponding port is enabled.

6.4.8.1 RX Error Counter[3:0] (0x0300:0x0307)

Bit

Description

ECAT

PDI

Reset Value

7:0

Invalid frame counter of Port y (counting is r/

r/-

stopped when 0xFF is reached).

w(clr)

15:8

RX Error counter of Port y (counting is stopped r/

when 0xFF is reached). This is coupled directly w(clr)

to RX ERR of MII interface.

r/-

Table 44: Register 0x0300:0x0307 (RX Err Cnt)

6.4.8.2 Forward RX Error Counter[3:0] (0x0308:0x030B)

Bit

Description

ECAT

PDI

Reset Value

7:0

Forwarded error counter of Port y (counting is r/

stopped when 0xFF is reached). w(clr)

r/-

Table 45: Register 0x0308:0x030B (FW RX Err Cnt)

Note

Error Counters 0x0300

-0x030B are cleared if one of the RX Error counters 0x0300-

0x030B is written. Write value is ignored (write 0).

6.4.8.3 ECAT Processing Unit Error Counter (0x030C)

Bit

Description

ECAT

PDI

Reset Value

7:0

ECAT Processing Unit error counter (counting is r/

stopped when 0xFF is reached). Counts errors w(clr)

of frames passing the Processing Unit (e.g., FCS

is wrong or datagram structure is wrong).

r/-

Table 46: Register 0x030C (Proc. Unit Err Cnt)

Note

Error Counter 0x030C is cleared if error counter 0x030C is written. Write value is

ignored (write 0).

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6.4.8.4 PDI Error Counter (0x030D)

Bit

Description

ECAT

PDI

Reset Value

7:0

PDI Error counter (counting is stopped when r/

0xFF is reached). Counts if a PDI access has an w(clr)

interface error.

r/-

Table 47: Register 0x030D (PDI Err Cnt)

Note

Error Counter 0x030D and Error Code 0x030E are cleared if error counter 0x030D

is written. Write value is ignored (write 0).

6.4.8.5 PDI Error Code (0x030E)

Bit

Description

ECAT

PDI

Reset Value

SPI access which caused last PDI Error.

Cleared if register 0x030D is written.

r/-

2:0

Number of SPI clock cycles of whole access r/-

(modulo 8)

r/-

3

Busy violation during read access

Read termination missing

r/-

4

5

Access continued after read termination byte

SPI command CMD[2:1]

7:6

Table 48: Register 0x030E (PDI Err Code)

Note

Error Counter 0x030D and Error Code 0x030E are cleared if error counter 0x030D

is written. Write value is ignored (write 0).

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6.4.8.6 Lost Link Counter[3:0] (0x0310:0x0313)

Bit

Description

ECAT

PDI

Reset Value

7:0

Lost Link counter of Port y (counting is stopped r/w(clr) r/-

when 0xff is reached). Counts only if port loop

is Auto.

Table 49: Register 0x0310:0x0313 (LL Counter)

Note

Only lost links at open ports are counted. Lost Link Counters 0x0310

-

0x0313 are

cleared if one of the Lost Link Counters 0x0310-0x0313 is written. Write value is

ignored (write 0).

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6.4.9 Watchdogs

6.4.9.1 Watchdog Divider (0x0400:0x0401)

Bit

Description

ECAT

PDI

Reset Value

15:0

Watchdog Time PDI: number or basic watch- r/w

dog increments (Default value with Watchdog

divider 100µs means 100ms Watchdog)

r/-

Table 50: Register 0x0400:0x0401 (WD Divider)

6.4.9.2 Watchdog Time PDI (0x0410:0x0411)

Bit

Description

ECAT

PDI

Reset Value

15:0

Watchdog Time PDI: number or basic watch- r/w

dog increments (Default value with Watchdog

divider 100µs means 100ms Watchdog)

r/-

Table 51: Register 0x0410:0x0411 (WD Time PDI)

Note

Watchdog is disabled if Watchdog time is set to 0x0000. Watchdog is restarted

with every PDI access.

6.4.9.3 Watchdog Time Process Data (0x0420:0x0421)

Bit

Description

ECAT

PDI

Reset Value

15:0

Watchdog Time Process Data: number of basic r/w

watchdog increments

r/-

(Default value with Watchdog divider 100

µ

s

means 100ms Watchdog)

Table 52: Register 0x0420:0x0421 (WD Time PD)

Note

There is one Watchdog for all SyncManagers. Watchdog is disabled if Watchdog

time is set to 0x0000. Watchdog is restarted with every write access to SyncMan-

agers with Watchdog Trigger Enable Bit set.

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6.4.9.4 Watchdog Status Process Data (0x0440:0x0441)

Bit

Description

ECAT

PDI

Reset Value

15:0

Watchdog Status of Process Data (triggered by r/-

SyncManagers)

r/

(w

0: Watchdog Process Data expired

1: Watchdog Process Data is active or disabled

ack)*

0

Reserved

r/-

r/

(w

ack)*

Table 53: Register 0x0440:0x0441 (WD Status PD)

* PDI register function acknowledge by Write command is disabled: Reading this register from PDI clears

AL Event Request 0x0220.6. Writing to this register from PDI is not possible.

PDI register function acknowledge by Write command is enabled: Writing this register from PDI clears AL

Event Request 0x0220.6. Writing to this register from PDI is possible; write value is ignored (write 0).

6.4.9.5 Watchdog Counter Process Data (0x0442)

Bit

Description

ECAT

PDI

Reset Value

7:0

Watchdog Counter Process Data (counting is r/

stopped when 0xFF is reached). Counts if Pro- w(clr)

cess Data Watchdog expires.

r/-

Table 54: Register 0x0442 (WD Counter PD)

Note

Watchdog Counters 0x0442

-0x0443 are cleared if one of the Watchdog Counters

0x0442-0x0443 is written. Write value is ignored (write 0).

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6.4.9.6 Watchdog Counter PDI (0x0443)

Bit

Description

ECAT

PDI

Reset Value

7:0

Watchdog PDI counter (counting is stopped r/

when 0xFF is reached). Counts if PDI Watch- w(clr)

dog expires.

r/-

Table 55: Register 0x0443 (WD Counter PDI)

Note

Watchdog Counters 0x0442

& 0x0443 are cleared if one of the Watchdog Counters

0x0442 & 0x0443 is written. Write value is ignored (write 0).

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6.4.10 SII EEPROM Interface

Address

Length

(Byte)

Description

SII EEPROM Interface

EEPROM Conﬁguration

EEPROM PDI Access State

EEPROM Control/Status

EEPROM Address

0x0500

1

0x0501

0x0502:0x0503

0x0504:0x0507

0x0508:0x050F

2

4

4/8

EEPROM Data

Table 56: SII EEPROM Interface Register Overview

6.4.10.1 EEPROM Conﬁguration (0x0500)

Bit

Description

ECAT

PDI

Reset Value

0

EEPROM control is oﬀered to PDI:

0: no

1: yes (PDI has EEPROM control)

r/w

r/-

1

Force ECAT access:

0: Do not change Bit 0x0501.0

1: Reset Bit 0x0501.0 to 0

r/w

r/-

7:2

Reserved, write 0

Table 57: Register 0x0500 (PROM Conﬁg)

6.4.10.2 EEPROM PDI Access State (0x0501)

Bit

Description

ECAT

PDI

Reset Value

0

Access to EEPROM:

r/-

r/(w)

0: PDI releases EEPROM access

1: PDI takes EEPROM access (PDI has EEPROM

control)

7:1

Reserved, write 0

r/-

Table 58: Register 0x0501 (PROM PDI Access)

Note

r/(w): write access is only possible if 0x0500.0=1 and 0x0500.1=0.

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6.4.10.3 EEPROM Control/Status (0x0502:0x0503)

Bit

Description

ECAT

PDI

Reset Value

0

ECAT write enable^∗2:

r/(w)

r/-

0: Write requests are disabled

1: Write requests are enabled

This bit is always 1 if PDI has EEPROM control.

4:1

5

Reserved, write 0

r/-

EEPROM emulation:

0: Normal operation (I2C interface used)

1: PDI emulates EEPROM (I2C not used)

6

Supported number of EEPROM read bytes:

r/-

0: 4 Bytes

1: 8 Bytes

7

Selected EEPROM Algorithm:

r/-

0: 1 address byte (1KBit . . . 16KBit EEPROMs)

1: 2 address bytes (32KBit . . . 4 MBit EEPROMs)

r/[w]

10:8

Command register^∗1:

r/(w)

r/[w]

Write: Initiate command.

Read: Currently executed command

Commands:

000: No command/EEPROM idle (clear error

bits)

001: Read

010: Write

100: Reload

Others: Reserved/invalid commands (do not

issue)

EEPROM emulation only: after execution, PDI

writes command value to indicate operation is

ready.

11

12

Checksum Error at in ESC Conﬁguration Area:

0: Checksum ok

r/-

1: Checksum error

EEPROM loading status:

0: EEPROM loaded, device information ok

1: EEPROM not loaded, device information not

available (EEPROM loading in progress or ﬁn-

ished with a failure)

13

Error Acknowledge/Command^∗2:

0: No error

r/-

r/[w]

1: Missing EEPROM acknowledge or invalid

command

EEPROM emulation only: PDI writes 1 if a tem-

porary failure has occurred.

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Bit

Description

ECAT

PDI

Reset Value

14

Error Write Enable^∗2:

r/-

0: No error

1: Write Command without Write enable

15

Busy:

r/-

0: EEPROM Interface is idle

1: EEPROM Interface is busy

Table 59: Register 0x0502:0x0503 (PROM Cntrl)

Note

r/(w): write access depends upon the assignment of the EEPROM interface

(ECAT/PDI). Write access is generally blocked if EEPROM interface is busy

(0x0502.15=1).

r/[w]: EEPROM emulation only: write access is possible if EEPROM interface is

busy (0x0502.15=1). PDI acknowledges pending commands by writing a 1 into

the corresponding command register bits (0x0502.10:8).

Errors can be indicated by writing a 1 into the error bit 0x0502.13. Acknowledging

clears AL Event Request 0x0220.5.

*1 Write Enable bit 0 is self-clearing at the SOF of the next frame, Command bits [10:8] are self-clearing

after the command is executed (EEPROM Busy ends). Writing "‘000"’ to the command register will also clear

the error bits [14:13]. Command bits [10:8] are ignored if Error Acknowledge/Command is pending (bit 13).

*2 Error bits are cleared by writing "‘000"’ (or any valid command) to Command Register Bits [10:8].

6.4.10.4 EEPROM Address (0x0504:0x0507)

Bit

Description

ECAT

PDI

Reset Value

31:0

EEPROM Address

r/(w)

0: First word (= 16 bit)

1: Second word

. . .

Actually used EEPROM Address bits:

[9:0]: EEPROM size up to 16 kBit

[17:0]: EEPROM size 32 kBit . . . 4 Mbit

[32:0]: EEPROM Emulation

Table 60: Register 0x0504:0x0507 (PROM Address)

Note

r/(w): write access depends upon the assignment of the EEPROM interface

(ECAT/PDI). Write access is generally blocked if EEPROM interface is busy

(0x0502.15=1).

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6.4.10.5 EEPROM Data (0x0508:0x050F)

Bit

Description

ECAT

PDI

Reset Value

15:0

EEPROM Write data (data to be written to EEP- r/(w)

ROM) or

r/[w]

EEPROM Read data (data read from EEPROM,.

lower bytes)

63:16 EEPROM Read data (data read from EEPROM, r/-

r/-

r[w]

higher bytes)

Table 61: Register 0x0508:0x050F (PROM Data)

Note

r/(w): write access depends upon the assignment of the EEPROM interface

(ECAT/PDI). Write access is generally blocked if EEPROM interface is busy

(0x0502.15=1).

r/[w]: write access for EEPROM emulation if read or reload command is pending.

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6.4.11 ESC Parameter RAM

6.4.11.1 MFC IO Block Conﬁguration (0x0580:0x05E1)

Byte

Description

ECAT

PDI

Reset Value

Bytes MFC IO block conﬁguration vector for

96...0 - crossbar mapping and IO signal assignment

- High voltage IO (HVIO) conﬁguration

- Switching regulator conﬁguration

r/w

- Memory block mapping

- and MFC IO block register conﬁguration

Table 62: Register 0x0580:0x05E1 (MFC IO Conﬁg)

The content of this address block in the ESC Parameter RAM can be automatically loaded from the SII EEP-

ROM after reset/power-up as a conﬁguration vector that is written to addresses 0x0580:0x05E1 in the ESC’s

memory space.

The respective data in the SII EEPROM must be of Category 1!

Nevertheless, MFC IO conﬁguration data can also be written and updated online by the EtherCAT Master

via the ECAT interface or from a local application controller via the PDI interface by directly accessing

addresses 0x0580:0x05E1 in the ESC’s memory space.

More information on the individual conﬁguration bytes in this conﬁguration vector is given in Section 7.4 –

SII EEPROM MFC IO Block Parameter Map and its following sections.

Example conﬁgurations are given in Section 7.10.

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6.4.12 MII Management Interface

Address

Length

(Byte)

Description

MII Management Interface

MII Management Control/Status

PHY Address

0x0510:0x0511

0x0512

2

1

2

1

4

0x0513

PHY Register Address

0x0514:0x0515

0x0516

PHY Data

MII Management ECAT Access State

MII Management PDI Access State

PHY Port Status

0x0517

0x0518:0x051B

Table 63: MII Management Interface Register Overview

6.4.12.1 MII Management Control/Status (0x0510:0x0511)

Bit

Description

ECAT

PDI

Reset Value

0

Write enable*:

r/(w)

r/-

0: Write disabled

1: Write enabled

This bit is always 1 if PDI has MI control.

1

2

Management Interface can be controlled by r/-

PDI (registers 0x0516:0x0517):

0: Only ECAT control

r/-

1: PDI control possible

MI link detection (link conﬁguration, link detec- r/-

tion, registers 0x0518:0x051B):

0: Not available

1: MI link detection active

7:3

9:8

PHY address of port 0

r/-

Command register*:

r/(w)

Write: Initiate command.

Read: Currently executed command

Commands:

00: No command/MI idle (clear error bits)

01: Read

10: Write

Others: Reserved/invalid commands (do not

issue)

12:10 Reserved, write 0

r/-

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Bit

Description

ECAT

PDI

Reset Value

13

Read error:

0: No read error

r/(w)

1: Read error occurred (PHY or register not

available)

Cleared by writing to this register.

14

15

Command error:

r/-

0: Last Command was successful

1: Invalid command or write command without

Write Enable

Cleared with a valid command or by writing

"‘00"’ to Command register bits [9:8].

Busy:

0: MI control state machine is idle

1: MI control state machine is active

Table 64: Register 0x0510:0x0511 (MI Cntrl/State)

Note

r/ (w): write access depends on assignment of MI (ECAT/PDI). Write access is

generally blocked if Management interface is busy (0x0510.15=1).

* Write enable bit 0 is self-clearing at the SOF of the next frame (or at the end of the PDI access), Command

bits [9:8] are self-clearing after the command is executed (Busy ends). Writing "‘00"’ to the command

register will also clear the error bits [14:13]. The Command bits are cleared after the command is executed.

6.4.12.2 PHY Address (0x0512)

Bit

0:4

6:5

7

Description

ECAT

r/(w)

r/-

PDI

r/(w)

r/-

Reset Value

PHY Address

Reserved, write 0

Show conﬁgured PHY address of port 0-3 in r/(w)

register 0x0510.7:3. Select port x with bits [4:0]

of this register (valid values are 0-3):

0: Show address of port 0 (oﬀset)

1: Show individual address of port x

r/(w)

Table 65: Register 0x0512 (PHY Address)

Note

r/ (w): write access depends on assignment of MI (ECAT/PDI). Write access is

generally blocked if Management interface is busy (0x0510.15=1).

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6.4.12.3 PHY Register Address (0x0513)

Bit

Description

ECAT

PDI

Reset Value

4:0

Address of PHY Register that shall be read/writ- r/(w)

ten

r/(w)

7:5

Reserved, write 0

r/(w)

Table 66: Register 0x0513 (PHY Register Address)

Note

r/ (w): write access depends on assignment of MI (ECAT/PDI). Write access is

generally blocked if Management interface is busy (0x0510.15=1).

6.4.12.4 PHY Data (0x0514:0x0515)

Bit

Description

ECAT

PDI

Reset Value

15:0

PHY Read/Write Data

r/(w)

Table 67: Register 0x0514:0x0515 (PHY Data)

Note

r/ (w): write access depends on assignment of MI (ECAT/PDI). Access is generally

blocked if Management interface is busy (0x0510.15=1).

6.4.12.5 MII Management ECAT Access State (0x0516)

Bit

Description

ECAT

PDI

Reset Value

31:0

Access to MII management:

0: ECAT enables PDI takeover of MII manage-

ment control

r/(w)

r/-

1: ECAT claims exclusive access to MII manage-

ment

31:0

Reserved, write 0

r/-

Table 68: Register 0x0516 (MI ECAT State)

Note

r/ (w): write access is only possible if 0x0517.0=0.

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6.4.12.6 MII Management PDI Access State (0x0517)

Bit

Description

ECAT

PDI

Reset Value

0

Access to MII management:

r/-

r/(w)

0: ECAT has access to MII management

1: PDI has access to MII management

1

Force PDI Access State:

0: Do not change Bit 0x0517.0

1: Reset Bit 0x0517.0 to 0

r/w

r/-

7:2

Reserved, write 0

Table 69: Register 0x0517 (MI PDI State)

6.4.12.7 PHY Port Status (0x0518:0x051B)

Bit

Description

ECAT

PDI

Reset Value

0

Physical link status (PHY status register 1.2):

0: No physical link / 1: Physical link detected

r/-

1

2

3

Link status (100 Mbit/s, Full Duplex, Autonego- r/-

tiation):

r/-

r/

0: No link / 1: Link detected

Link status error:

0: No error

1: Link error, link inhibited

r/-

Read error:

r/

0: No read error occurred

1: A read error has occurred

Cleared by writing any value to at least one of

the PHY Status Port registers.

(w/clr) (w/clr)

4

5

Link partner error:

r/-

r/

r/-

r/

0: No error detected / 1: Link partner error

PHY conﬁguration updated:

0: No update

(w/clr) (w/clr)

1: PHY conﬁguration was updated

Cleared by writing any value to at least one of

the PHY Status Port registers.

31:0

Reserved

r/-

Table 70: Register 0x0518+y (PHY Port Status)

Note

r/(w): write access depends on assignment of MI (ECAT/PDI).

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6.4.13 FMMUs

Address

Length

(Byte)

Description

0x0600:0x06FF

+0x0:0x3

+0x4:0x5

+0x6

16x16

FMMU[15:0]

Logical Start Address

Length

4

2

1

2

1

3

Logical Start bit

Logical Stop bit

Physical Start Address

Physical Start bit

Type

+0x7

+0x8:0x9

+0xA

+0xB

+0xC

Activate

+0xD:0xF

Reserved

Table 71: FMMU Register Overview

For the following registers use y as FMMU number.

See the device features on how many FMMUs are supported in a speciﬁc ESC device.

6.4.13.1 Logical Start Address (+0x0:0x3)

Bit

Description

ECAT

PDI

Reset Value

31:0

Logical start address within the EtherCAT Ad- r/w

dress Space.

r/-

Table 72: Register 0x06y0:0x06y3 (Log Start Addr)

6.4.13.2 Length (+0x4:0x5)

Bit

Description

ECAT

PDI

Reset Value

15:0

Oﬀset from the ﬁrst logical FMMU Byte to the r/w

last FMMU Byte + 1 (e.g., if two bytes are used

then this parameter shall contain 2)

r/-

Table 73: Register 0x06y4:0x06y5 (FMMU Length)

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6.4.13.3 Logical Start bit (+0x6)

Bit

Description

ECAT

PDI

Reset Value

2:0

Logical starting bit that shall be mapped (bits r/w

are counted from least signiﬁcant bit (=0) to

most signiﬁcant bit(=7)

r/-

7:3

Reserved, write 0

r/-

Table 74: Register 0x06y6 (Log. Start Bit)

6.4.13.4 Logical Stop bit (+0x7)

Bit

Description

ECAT

PDI

Reset Value

2:0

Last logical bit that shall be mapped (bits are r/w

counted from least signiﬁcant bit (=0) to most

signiﬁcant bit(=7)

r/-

7:3

Reserved, write 0

r/-

Table 75: Register 0x06y7 (Log. Stop Bit))

6.4.13.5 Physical Start Address (+0x8:0x9)

Bit

Description

ECAT

PDI

Reset Value

Physical Start Address (mapped to logical Start r/w

address)

r/-

Table 76: Register 0x06y8:0x06y9 (Phy. Start Addr

6.4.13.6 Physical Start bit (+0xA)

Bit

Description

ECAT

PDI

Reset Value

2:0

Physical starting bit as target of logical start bit r/w

mapping (bits are counted from least signiﬁ-

cant bit (=0) to most signiﬁcant bit(=7)

r/-

7:3

Reserved, write 0

r/-

Table 77: Register 0x06yA (Phy. Start Bit)

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6.4.13.7 Type (+0xB)

Bit

Description

ECAT

PDI

Reset Value

0

0: Ignore mapping for read accesses

1: Use mapping for read accesses

r/w

r/-

1

0: Ignore mapping for write accesses

r/w

r/-

1: Use mapping for write accesses

7:2

Reserved, write 0

Table 78: Register 0x06yB (FMMU Type)

6.4.13.8 Activate (+0xC)

Bit

Description

ECAT

PDI

Reset Value

0

0: FMMU deactivated

r/w

r/-

1: FMMU activated. FMMU checks logical ad-

dressed blocks to be mapped according to

mapping conﬁgured

7:1

Reserved, write 0

r/-

Table 79: Register 0x06yC (FMMU Activate)

6.4.13.9 Reserved (+0xD:0xF)

Bit

Description

ECAT

PDI

Reset Value

23:0

Reserved, write 0

r/-

Table 80: Register 0x06yD:0x06yF (Reserved)

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6.4.14 SyncManagers

Address

Length

(Byte)

Description

0x0800:0x087F

+0x0:0x1

+0x2:0x3

+0x4

16x8

SyncManager[15:0]

Physical Start Address

Length

2

1

Control Register

Status Register

Activate

+0x5

+0x6

+0x7

PDI Control

Table 81: SyncManager Register Overview

For the following registers use y as SM number.

See the device features on how many SMs are supported in a speciﬁc ESC device.

6.4.14.1 Physical Start Address (+0x0:0x1)

Bit

Description

ECAT

PDI

Reset Value

15:0

Speciﬁes ﬁrst byte that will be handled by Sync- r/(w)

Manager

r/-

Table 82: Register 0x0800+y*8:0x0801+y*8 (Phy. Start Addr)

Note

r/(w): Register can only be written if SyncManager is disabled (+0x6.0 = 0).

6.4.14.2 Length (+0x2:0x3)

Bit

Description

ECAT

PDI

Reset Value

15:0

Number of bytes assigned to SyncManager r/(w)

(shall be greater 1, otherwise SyncManager is

not activated. If set to 1, only Watchdog Trigger

is generated if conﬁgured)

r/-

Table 83: Register 0x0802+y*8:0x0803+y*8 (SM Length)

Note

r/(w): Register can only be written if SyncManager is disabled (+0x6.0 = 0).

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6.4.14.3 Control Register (+0x4)

Bit

Description

ECAT

PDI

Reset Value

1:0

Operation Mode:

r/(w)

r/-

00: Buﬀered (3 buﬀer mode)

01: Reserved

10: Mailbox (Single buﬀer mode)

11: Reserved

3:2

Direction:

r/(w)

r/-

00: Read: ECAT read access, PDI write access.

01: Write: ECAT write access, PDI read access.

10: Reserved

11: Reserved

4

5

6

7

Interrupt in ECAT Event Request Register:

0: Disabled

1: Enabled

r/(w)

r/w

r/-

Interrupt in PDI Event Request Register:

0: Disabled

1: Enabled

Watchdog Trigger Enable:

0: Disabled

1: Enabled

Reserved, write 0

r/-

Table 84: Register 0x0804+y*8 (SM Control)

Note

r/(w): Register can only be written if SyncManager is disabled (+0x6.0 = 0).

6.4.14.4 Status Register (+0x5)

Bit

Description

ECAT

PDI

Reset Value

0

Interrupt Write:

r/-

1: Interrupt after buﬀer was completely and

successfully written

0: Interrupt cleared after ﬁrst byte of buﬀer

was read

NOTE: This interrupt is signaled to the reading

side if enabled in the SM Control register.

1

Interrupt Read:

r/-

1: Interrupt after buﬀer was completely and

successful read

0: Interrupt cleared after ﬁrst byte of buﬀer

was written

NOTE: This interrupt is signaled to the writing

side if enabled in the SM Control register.

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Bit

2

Description

ECAT

r/-

PDI

r/-

Reset Value

Reserved

3

Mailbox mode: mailbox status:

0: Mailbox empty

r/-

1: Mailbox full

Buﬀered mode: reserved

5:4

Buﬀered mode: buﬀer status (last written r/-

r/-

buﬀer):

00: 1. buﬀer

01: 2. buﬀer

10: 3. buﬀer

11: (no buﬀer written)

Mailbox mode: reserved

6

7

Read buﬀer in use (opened)

Write buﬀer in use (opened)

r/-

Table 85: Register 0x0805+y*8 (SM Status)

6.4.14.5 Activate (+0x6)

Bit

Description

ECAT

PDI

Reset Value

0

SyncManager Enable/Disable:

0: Disable: Access to Memory without Sync-

Manager control

r/w

r/

(w

ack)*

1: Enable: SyncManager is active and controls

Memory area set in conﬁguration

1

Repeat Request:

r/w

r/-

A toggle of Repeat Request means that a mail-

box retry is needed (primarily used in conjunc-

tion with ECAT Read Mailbox)

5:2

6

Reserved, write 0

r/-

r/

(w

ack)*

Latch Event ECAT:

0: No

1: Generate Latch event if EtherCAT master

issues a buﬀer exchange

r/w

r/

(w

ack)*

7

Latch Event PDI: 0: No 1: Generate Latch events r/w

if PDI issues a buﬀer exchange or if PDI ac-

cesses buﬀer start address

r/

(w

ack)*

Table 86: Register 0x0806+y*8 (SM Activate)

* PDI register function acknowledge by Write command is disabled: Reading this register from PDI in all

SMs which have changed activation clears AL Event Request 0x0220.4. Writing to this register from PDI is

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not possible.

PDI register function acknowledge by Write command is enabled: Writing this register from PDI in all

SMs which have changed activation clears AL Event Request 0x0220.4. Writing to this register from PDI is

possible; write value is ignored (write 0).

6.4.14.6 PDI Control (+0x7)

Bit

Description

ECAT

PDI

Reset Value

0

Deactivate SyncManager:

Read:

r/-

r/w

0: Normal operation, SyncManager activated.

1: SyncManager deactivated and reset Sync-

Manager locks access to Memory area.

Write:

0: Activate SyncManager

1: Request SyncManager deactivation

NOTE: Writing 1 is delayed until the end of a

frame which is currently processed.

1

Repeat Ack:

r/-

r/w

r/-

If this is set to the same value as set by Repeat

Request, the PDI acknowledges the execution

of a previous set Repeat request.

7:2

Reserved, write 0

Table 87: Register 0x0807+y*8 (SM PDI Control)

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6.4.15 Distributed Clocks Receive Times

Depending on the available width of the Distributed Clocks feature the time stamp registers are either 32

bit (4 bytes) or 64 bits (8 bytes) wide. Please check the feature summary of the respective TRINAMIC ESC

device.

6.4.15.1 Receive Time Port 0 (0x0900:0x0903)

Bit

Description

ECAT

PDI

Reset Value

31:0

Write:

r/w

r/-

A write access to register 0x0900 with BWR or (special

FPWR latches the local time of the beginning of func-

the receive frame (start ﬁrst bit of preamble) at tion)

each port.

Read:

Local time of the beginning of the last receive

frame containing a write access to this register.

Table 88: Register 0x0900:0x0903 (Rcv Time P0)

Note

The time stamps cannot be read in the same frame in which this register was

written.

6.4.15.2 Receive Time Port 1 (0x0904:0x0907)

Bit

Description

ECAT

PDI

Reset Value

31:0

Local time of the beginning of a frame (start r/-

ﬁrst bit of preamble) received at port 1 contain-

ing a BWR or FPWR to Register 0x0900.

r/-

Table 89: Register 0x0904:0x0907 (Rcv Time P1)

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6.4.16 Distributed Clocks Time Loop Control Unit

Time Loop Control unit is usually assigned to ECAT. Write access to Time Loop Control registers by PDI

(and not ECAT) depends on explicit hardware conﬁguration and on the used ESC type. Check the device

features for availability.

6.4.16.1 System Time (0x0910:0x0917)

Bit

Description

ECAT

PDI

Reset Value

0:63

ECAT read access: Local copy of System Time

when frame passed the reference clock (i.e.,

including System Time Delay). Time latched at

beginning of the frame (Ethernet SOF delimiter)

r

-

63:0

31:0

PDI read access: Local copy of the System Time.

Time latched when reading ﬁrst byte (0x0910)

-

r

Write access: Written value will be compared (w)

with the local copy of the System time. The (spe-

result is an input to the time control loop.

r/-

cial

NOTE: written value will be compared at the func-

end of the frame with the latched (SOF) local tion)

copy of the System time if at least the ﬁrst byte

(0x0910) was written.

31:0

Write access: Written value will be compared

with Latch0 Time Positive Edge time. The result

is an input to the time control loop.

-

(w)

(spe-

cial

NOTE: written value will be compared at the

end of the access with Latch0 Time Positive

Edge (0x09B0:0x09B3) if at least the last byte

(0x0913) was written.

func-

tion)

Table 90: Register 0x0910:0x0917 (System Time)

Note

Write access to this register depends upon ESC conﬁguration (typically ECAT, PDI

only with explicit ESC conﬁguration: System Time PDI controlled).

6.4.16.2 Receive Time ECAT Processing Unit (0x0918:0x091F)

Bit

Description

ECAT

PDI

Reset Value

63:0

Local time of the beginning of a frame (start r/-

ﬁrst bit of preamble) received at the ECAT Pro-

cessing Unit containing a write access to Regis-

ter 0x0900

r/-

NOTE: E.g., if port 0 is open, this register reﬂects

the Receive Time Port 0 as a 64 Bit value.

Table 91: Register 0x0918:0x091F (Rcv Time EPU)

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6.4.16.3 System Time Oﬀset (0x0920:0x0927)

Bit

Description

ECAT

PDI

Reset Value

63:0

Diﬀerence between local time and System r/(w)

Time. Oﬀset is added to the local time.

r/(w)

Table 92: Register 0x0920:0x0927 (Sys Time Oﬀset)

Note

Write access to this register depends upon ESC conﬁguration (typically ECAT, PDI

only with explicit ESC conﬁguration: System Time PDI controlled). Reset internal

system time diﬀerence ﬁlter and speed counter ﬁlter by writing Speed Counter

Start (0x0930:0x0931) after changing this value.

6.4.16.4 System Time Delay (0x0928:0x092B)

Bit

Description

ECAT

PDI

Reset Value

31:0

Delay between Reference Clock and the ESC

r/(w)

Table 93: Register 0x0928:0x092B (Sys Time Delay)

Note

Write access to this register depends upon ESC conﬁguration (typically ECAT, PDI

only with explicit ESC conﬁguration: System Time PDI controlled). Reset internal

system time diﬀerence ﬁlter and speed counter ﬁlter by writing Speed Counter

Start (0x0930:0x0931) after changing this value.

6.4.16.5 System Time Diﬀerence (0x092C:0x092F)

Bit

Description

ECAT

PDI

Reset Value

30:0

Mean diﬀerence between local copy of System r/-

Time and received System Time values

r/-

31

0: Local copy of System Time greater than or r/-

equal received System Time

r/-

1: Local copy of System Time smaller than re-

ceived System Time

Table 94: Register 0x092C:0x092F (Sys Time Diﬀ)

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6.4.16.6 Speed Counter Start (0x0930:0x0931)

Bit

Description

ECAT

PDI

Reset Value

14:0

Bandwidth for adjustment of local copy of Sys- r/(w)

r/(w)

tem Time (larger values smaller bandwidth

→

and smoother adjustment)

A write access resets System Time Diﬀer-

ence (0x092C:0x092F) and Speed Counter Diﬀ

(

0x0932:0x0933). Minimum value: 0x0080 to

0x3FFF

15

Reserved, write 0

r/(w)

r/-

Table 95: Register 0x0930:0x931 (Speed Cnt Start)

Note

Write access to this register depends upon ESC conﬁguration (typically ECAT, PDI

only with explicit ESC conﬁguration: System Time PDI controlled).

6.4.16.7 Speed Counter Diﬀ (0x0932:0x0933)

Bit

Description

ECAT

PDI

Reset Value

15:0

Representation of the deviation between local r/-

clock period and reference clock’s clock period

(representation: two’s complement) Range:

±(Speed Counter Start - 0x7F)

r/-

Table 96: Register 0x0932:0x0933 (Speed Cnt Diﬀ)

Note

Calculate the clock deviation after System Time Diﬀerence has settled at a low

value as follows:

SpeedCntDiff

Deviation

=

5∗(SpeedCntStart+SpeedCntDiff+2)∗(SpeedCntStart−SpeedCntDiff+2)

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6.4.16.8 System Time Diﬀerence Filter Depth (0x0934)

Bit

Description

ECAT

PDI

Reset Value

3:0

Filter depth for averaging the received System r/(w)

Time deviation.

r/(w)

A write access resets System Time Diﬀerence

(0x092C:0x092F)

7:4

Reserved, write 0

r/-

Table 97: Register 0x0934 (Sys Time Diﬀ Filter)

Note

Write access to this register depends upon ESC conﬁguration (typically ECAT, PDI

only with explicit ESC conﬁguration: System Time PDI controlled).

6.4.16.9 Speed Counter Filter Depth (0x0935)

Bit

Description

ECAT

PDI

Reset Value

3:0

Filter depth for averaging the clock period devi- r/(w)

ation. A write access resets the internal speed

counter ﬁlter.

r/(w)

7:4

Reserved, write 0

r/-

Table 98: Register 0x0935 (Speed Cnt Filter Depth)

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6.4.17 Distributed Clocks Cyclic Unit Control

6.4.17.1 Cyclic Unit Control (0x0980)

Bit

Description

ECAT

PDI

Reset Value

0

SYNC out unit control:

0: ECAT controlled

1: PDI controlled

r/w

r/-

3:1

4

Reserved, write 0

r/-

Latch In unit 0:

r/w

0: ECAT controlled

1: PDI controlled

NOTE: Always 1 (PDI controlled) if System Time

is PDI controlled. Latch interrupt is routed to

ECAT/PDI depending on this setting

5

Latch In unit 1:

r/w

r/-

0: ECAT controlled

1: PDI controlled

NOTE: Latch interrupt is routed to ECAT/PDI

depending on this setting

7:6

Reserved, write 0

Table 99: Register 0x0980 (Cyclic Unit Cntrl)

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6.4.18 Distributed Clocks SYNC Out Unit

6.4.18.1 SYNC Out Activation (0x0981)

Bit

Description

ECAT

PDI

Reset Value

0

Sync Out Unit activation:

0: Deactivated

1: Activated

r/(w)

0

1

2

3

SYNC0 generation:

0: Deactivated

r/(w)

0

1: SYNC0 pulse is generated

SYNC1 generation:

0: Deactivated

1: SYNC1 pulse is generated

Auto-activation by writing Start Time Cyclic Op- r/(w)

eration (0x0990:0x0997):

0: Disabled

1: Auto-activation enabled. 0x0981.0 is set au-

tomatically after Start Time is written.

4

5

Extension of Start Time Cyclic Operation r/(w)

(0x0990:0x0993):

r/(w)

0

0: No extension

1: Extend 32 bit written Start Time to 64 bit

Start Time plausibility check:

r/(w)

0: Disabled. SyncSignal generation if Start Time

is reached.

1: Immediate SyncSignal generation if Start

Time is outside near future (see 0x0981.6)

6

7

Near future conﬁguration (approx.):

0: 1/2 DC width future (2³¹ns or 2⁶³ns)

1: 2.1 sec. future (2³¹ns)

r/(w)

0

SyncSignal debug pulse (Vasily bit):

0: Deactivated

1: Immediately generate one ping only on

SYNC0-1 according to 0x0981.(2:1) for debug-

ging

This bit is self-clearing, always read 0.

Table 100: Register 0x0981 (SYNC Out Activation)

Note

Write to this register depends upon setting of 0x0980.0.

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6.4.18.2 Pulse Length of SYNC signals (0x0982:0x0983)

Bit

Description

ECAT

PDI

Reset Value

0

Pulse length of SyncSignals (in Units of 10ns)

0: Acknowledge mode: SyncSignal will be

cleared by reading SYNC[1:0] Status register

r/-

0, later EEPROM ADR

0x0002

Table 101: Register 0x0982:0x0983 (SYNC Pulse Length)

6.4.18.3 Activation Status (0x0984)

Bit

Description

ECAT

PDI

Reset Value

0

SYNC0 activation state:

r/-

0

0: First SYNC0 pulse is not pending

1: First SYNC0 pulse is pending

1

2

SYNC1 activation state:

0: First SYNC1 pulse is not pending

1: First SYNC1 pulse is pending

r/-

0

Start Time Cyclic Operation (0x0990:0x0997

)

plausibility check result when Sync Out Unit

was activated:

0: Start Time was within near future

1: Start Time was out of near future (0x0981.6

)

7:3

Reserved

r/-

0

Table 102: Register 0x0984 (Activation Status)

6.4.18.4 SYNC0 Status (0x098E)

Bit

Description

ECAT

PDI

Reset Value

0

SYNC0 activation state:

0: First SYNC0 pulse is not pending

1: First SYNC0 pulse is pending

r/-

r/

0

(w

ack)*

7:1

Reserved

r/-

r/

0

(w

ack)*

Table 103: Register 0x098E (SYNC0 Status)

* PDI register function acknowledge by Write command is disabled: Reading this register from PDI clears

AL Event Request 0x0220.2. Writing to this register from PDI is not possible.

PDI register function acknowledge by Write command is enabled: Writing this register from PDI clears AL

Event Request 0x0220.2. Writing to this register from PDI is possible; write value is ignored (write 0).

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6.4.18.5 SYNC1 Status (0x098F)

Bit

Description

ECAT

PDI

Reset Value

0

SYNC1 activation state:

0: First SYNC1 pulse is not pending

1: First SYNC1 pulse is pending

r/-

r/

0

(w

ack)*

7:1

Reserved

r/-

r/

0

(w

ack)*

Table 104: Register 0x098F (SYNC1 Status)

* PDI register function acknowledge by Write command is disabled: Reading this register from PDI clears

AL Event Request 0x0220.3. Writing to this register from PDI is not possible.

PDI register function acknowledge by Write command is enabled: Writing this register from PDI clears AL

Event Request 0x0220.3. Writing to this register from PDI is possible; write value is ignored (write 0).

6.4.18.6 Start Time Cyclic Operation / Next SYNC0 Pulse (0x0990:0x0997)

Bit

Description

ECAT

PDI

Reset Value

63:0

Write: Start time (System time) of cyclic opera- r/(w)

tion in ns

Read: System time of next SYNC0 pulse in ns

r/(w)

0

Table 105: Register 0x0990:0x0997 (Start Time Cyclic Operation)

Note

Write to this register depends upon setting of 0x0980.0

.

Only writable if

0x0981.0=0. Auto-activation (0x0981.3=1): upper 32 bits are automatically ex-

tended if only lower 32 bits are written within one frame.

6.4.18.7 Next SYNC1 Pulse (0x0998:0x099F)

Bit

Description

ECAT

PDI

Reset Value

63:0

System time of next SYNC1 pulse in ns

r/-

0

Table 106: Register 0x0998:0x099F (Next SYNC1)

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6.4.18.8 SYNC0 Cycle Time (0x09A0:0x09A3)

Bit

Description

ECAT

PDI

Reset Value

31:0

WTime between two consecutive SYNC0 pulses r/(w)

in ns.

r/(w)

0

0: Single shot mode, generate only one SYNC0

pulse.

Table 107: Register 0x09A0:0x09A3 (SYNC0 Cycle Time)

Note

Write to this register depends upon setting of 0x0980.0.

6.4.18.9 SYNC1 Cycle Time (0x09A4:0x09A7)

Bit

Description

ECAT

PDI

Reset Value

31:0

Time between SYNC1 pulses and SYNC0 pulse r/(w)

in ns

r/(w)

0

Table 108: Register 0x09A4:0x09A7 (SYNC1 Cycle Time)

Note

Write to this register depends upon setting of 0x0980.0.

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6.4.19 Distributed Clocks LATCH In Unit

6.4.19.1 Latch0 Control (0x09A8)

Bit

Description

ECAT

PDI

Reset Value

0

Latch0 positive edge:

r/(w)

0

0: Continuous Latch active

1: Single event (only ﬁrst event active)

1

Latch0 negative edge:

0: Continuous Latch active

1: Single event (only ﬁrst event active)

r/(w)

r/-

r/(w)

r/-

0

7:2

Reserved, write 0

Table 109: Register 0x09A8 (Latch0 Control)

Note

Write access depends upon setting of 0x0980.4.

6.4.19.2 Latch1 Control (0x09A9)

Bit

Description

ECAT

PDI

Reset Value

0

Latch1 positive edge:

r/(w)

0

0: Continuous Latch active

1: Single event (only ﬁrst event active)

1

Latch01 negative edge:

0: Continuous Latch active

1: Single event (only ﬁrst event active)

r/(w)

r/-

r/(w)

r/-

0

7:2

Reserved, write 0

Table 110: Register 0x09A9 (Latch1 Control)

Note

Write access depends upon setting of 0x0980.5.

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6.4.19.3 Latch0 Status (0x09AE)

Bit

Description

ECAT

PDI

Reset Value

0

Event Latch0 positive edge.

r/-

0

0: Positive edge not detected or continuous

mode

1: Positive edge detected in single event mode

only.

Flag cleared by reading out Latch0 Time Posi-

tive Edge.

1

Event Latch0 negative edge.

r/-

0

0: Negative edge not detected or continuous

mode

1: Negative edge detected in single event mode

only.

Flag cleared by reading out Latch0 Time Nega-

tive Edge.

2

Latch0 pin state

Reserved

r/-

0

7:3

Table 111: Register 0x09AE (Latch0 Status)

6.4.19.4 Latch1 Status (0x09AF)

Bit

Description

ECAT

PDI

Reset Value

0

Event Latch1 positive edge.

r/-

0

0: Positive edge not detected or continuous

mode

1: Positive edge detected in single event mode

only.

Flag cleared by reading out Latch1 Time Posi-

tive Edge.

1

Event Latch1 negative edge.

r/-

0

0: Negative edge not detected or continuous

mode

1: Negative edge detected in single event mode

only.

Flag cleared by reading out Latch1 Time Nega-

tive Edge.

2

Latch1 pin state

Reserved

r/-

0

7:3

Table 112: Register 0x09AF (Latch1 Status)

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6.4.19.5 Latch0 Time Positive Edge (0x09B0:0x09B7)

Bit

Description

ECAT

PDI

Reset Value

63:0

Register captures System time at the positive r(ack)/- r/

0

edge of the Latch0 signal. (w

ack)*

Table 113: Register 0x09B0:0x09B7 (Latch0 Time Pos Edge)

Note

Register bits [63:8] are internally latched (ECAT/PDI independently) when bits [7:0]

are read, which guarantees reading a consistent value. Reading this register from

ECAT clears Latch0 Status 0x09AE.0 if 0x0980.4=0. Writing to this register from

ECAT is not possible.

* PDI register function acknowledge by Write command is disabled: Reading this register from PDI if

0x0980.4=1 clears Latch0 Status 0x09AE.0. Writing to this register from PDI is not possible.

PDI register function acknowledge by Write command is enabled: Writing this register from PDI if

0x0980.4=1 clears Latch0 Status 0x09AE.0. Writing to this register from PDI is possible; write value is

ignored (write 0).

6.4.19.6 Latch0 Time Negative Edge (0x09B8:0x09BF)

Bit

Description

ECAT

PDI

Reset Value

63:0

Register captures System time at the negative r(ack)/- r/

0

edge of the Latch0 signal. (w

ack)*

Table 114: Register 0x09B8:0x09BF (Latch0 Time Neg Edge)

Note

Register bits [63:8] are internally latched (ECAT/PDI independently) when bits [7:0]

are read, which guarantees reading a consistent value. Reading this register from

ECAT clears Latch0 Status 0x09AE.1 if 0x0980.4=0. Writing to this register from

ECAT is not possible.

* PDI register function acknowledge by Write command is disabled: Reading this register from PDI if

0x0980.4=1 clears Latch0 Status 0x09AE.1. Writing to this register from PDI is not possible.

PDI register function acknowledge by Write command is enabled: Writing this register from PDI if

0x0980.4=1 clears Latch0 Status 0x09AE.1. Writing to this register from PDI is possible; write value is

ignored (write 0).

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6.4.19.7 Latch1 Time Positive Edge (0x09C0:0x09C7)

Bit

Description

ECAT

PDI

Reset Value

63:0

Register captures System time at the positive r(ack)/- r/

0

edge of the Latch1 signal. (w

ack)*

Table 115: Register 0x09C0:0x09C7 (Latch1 Time Pos Edge)

Note

Register bits [63:8] are internally latched (ECAT/PDI independently) when bits [7:0]

are read, which guarantees reading a consistent value. Reading this register from

ECAT clears Latch1 Status 0x09AF.0 if 0x0980.5=0. Writing to this register from

ECAT is not possible.

* PDI register function acknowledge by Write command is disabled: Reading this register from PDI if

0x0980.5=1 clears Latch1 Status 0x09AF.0. Writing to this register from PDI is not possible.

PDI register function acknowledge by Write command is enabled: Writing this register from PDI if

0x0980.5=1 clears Latch1 Status 0x09AF.0. Writing to this register from PDI is possible; write value is

ignored (write 0).

6.4.19.8 Latch1 Time Negative Edge (0x09C8:0x09CF)

Bit

Description

ECAT

PDI

Reset Value

63:0

Register captures System time at the negative r(ack)/- r/

0

edge of the Latch1 signal. (w

ack)*

Table 116: Register 0x09C8:0x09CF (Latch1 Time Neg Edge)

Note

Register bits [63:8] are internally latched (ECAT/PDI independently) when bits [7:0]

are read, which guarantees reading a consistent value. Reading this register from

ECAT clears Latch1 Status 0x09AF.0 if 0x0980.5=0. Writing to this register from

ECAT is not possible.

* PDI register function acknowledge by Write command is disabled: Reading this register from PDI if

0x0980.5=1 clears Latch1 Status 0x09AF.1. Writing to this register from PDI is not possible.

PDI register function acknowledge by Write command is enabled: Writing this register from PDI if

0x0980.5=1 clears Latch1 Status 0x09AF.1. Writing to this register from PDI is possible; write value is

ignored (write 0).

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6.4.20 Distributed Clocks SyncManager Event Times

6.4.20.1 EtherCAT Buﬀer Change Event Time (0x09F0:0x09F3)

Bit

Description

ECAT

PDI

Reset Value

31:0

Register captures local time of the beginning r/-

of the frame which causes at least one SM to

assert an ECAT event

r/-

0

Table 117: Register 0x09F0:0x09F3 (ECAT Buﬀer Change Event Time)

Note

Register bits [31:8] are internally latched (ECAT/PDI independently) when bits [7:0]

are read, which guarantees reading a consistent value.

6.4.20.2 PDI Buﬀer Start Event Time (0x09F8:0x09FB)

Bit

Description

ECAT

PDI

Reset Value

31:0

Register captures local time when at least one r/-

SyncManager asserts an PDI buﬀer start event

r/-

0

Table 118: Register 0x09F8:0x09FB (PDI Buﬀer Start Event Time)

Note

Register bits [31:8] are internally latched (ECAT/PDI independently) when bits [7:0]

are read, which guarantees reading a consistent value.

6.4.20.3 PDI Buﬀer Change Event Time (0x09FC:0x09FF)

Bit

Description

ECAT

PDI

Reset Value

31:0

Register captures local time when at least one r/-

SyncManager asserts an PDI buﬀer start event

r/-

0

Table 119: Register 0x09FC:0x09FF (PDI Buﬀer Change Event Time)

Note

Register bits [31:8] are internally latched (ECAT/PDI independently) when bits [7:0]

are read, which guarantees reading a consistent value.

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6.4.21 ESC Speciﬁc

6.4.21.1 Product ID (0x0E00:0x0E07)

Bit

Description

ECAT

PDI

Reset Value

63:0

Product ID

r/-

TMC8460: 0x0000000001008460

TMC8461: 0x0000000001108461

TMC8462: 0x0000000001108461

TMC8670: 0x0000000001008670

Table 120: Register 0x0E00:0x0E07 (Product ID)

6.4.21.2 Vendor ID (0x0E08:0x0E0F)

Bit

Description

ECAT

PDI

Reset Value

63:0

Vendor ID:

r/-

TMC8460: 0x0000000100000286

TMC8461: 0x0000000100000286

TMC8462: 0x0000000100000286

TMC8670: 0x0000000100000286

[23:0] Company

[31:24] Department

NOTE: Test Vendor IDs [31:28]=0xE

Table 121: Register 0x0E08:0x0E0F (Vendor ID)

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6.4.22 Process Data RAM

6.4.22.1 Process Data RAM (0x1000:0xFFFF)

The Process Data RAM starts at address 0x1000.

The size of the Process Data RAM depends on the device.

Bytes Description

ECAT

PDI

Reset Value

- - -

Process Data RAM

(r/w)

Random/undeﬁned

Table 122: Process Data RAM (0x1000:0xFFFF)

Note

(r/w): Process Data RAM is only accessible if EEPROM was correctly loaded (register

0x0110.0 = 1).

Device

Process Data RAM Size

Upper RAM Address

0x4FFF

TMC8460 16kBytes

TMC8461 16kBytes

TMC8462 16kBytes

TMC8670 4kBytes

0x4FFF

0x1FFF

Table 123: Process Data RAM Size

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7 MFC IO Block Description

7.1 General Information

The MFC IO block includes a set of functions realized as dedicated hardware blocks.

The MFC IO block oﬀers 24 fully conﬁgurable IOs that can be used with any function of the MFC IO block.

16 low voltage IOs capable of 3.3V or 5V and 8 high voltage IOs capable of up to 24V are available.

The MFC IO block functions can be used either via the MFC IO control interface (see section 5.2) or via

EtherCAT data objects mapped as registers to the Process Data Memory.

When using the MFC IO control interface the microcontroller has full control over the MFC IO block and its

hardware functions. This allows for oﬄoading some ﬁrmware tasks towards the TMC8461, to do system

level control, or to extend the microcontroller’s IO capabilities.

When accessing the MFC IO block via EtherCAT data objects, centralized control from the EtherCAT master

is enabled. It it also possible to use the TMC8461 in device emulation mode without any microcontroller

connected while still using the dedicated hardware blocks and functions of the MFC IO block. For example,

the SPI master interface of the MFC IO block can be used to connected to a position sensor, which is read

out by the EtherCAT master.

Conﬁguration of the MFC IO block is done via the SII EEPROM at startup or by the EtherCAT master or

microcontroller after startup.

SII EEPROM conﬁguration data must be of category 1 and is automatically loaded at startup and written

into the ESC Parameter Ram section of the EtherCAT Register Set starting at address 0x0580 (see Section

6.4.11.1).

The ESC Parameter RAM section can also be written by the EtherCAT master or the local microcontroller

for direct conﬁguration or to modify conﬁguration after startup.

The block diagram in Figure 29 shows the general approach for the MFC IO block conﬁguration.

Note

Even if the MFC IO block is only accessed from the microcontroller and the

EtherCAT access feature is not used, it is recommended to store at least the

crossbar conﬁguration (section 7.5), the HVIO conﬁguration (section 7.6) and the

switching regulator conﬁguration (section 7.7) in the SII EEPROM.

By doing this, the settings are loaded faster than having to write them from the

microcontroller and it also reduces the memory usage on the microcontroller

itself.

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Figure 29: MFC IO Block Conﬁguration using the ESC Parameter RAM

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7.2 MFC IO Register Overview

The MFC IO block contains a range of registers dedicated to the speciﬁc sub-blocks.

The registers can always be read by a microcontroller via the MFC IO Control SPI Interface.

The registers can only be exclusively written by either the microcontroller via the MFC IO Control SPI

Interface or by the EtherCAT master via a mapping in the ESC’s DPRAM.

The analog and high voltage block can also be conﬁgured using dedicated registers of the MFC IO block.

Register Function

Write/Read

Size (Byte) Padding Bytes (see section

7.8)

0

ENC_MODE

W

R

2

1

4

8

2

1

4

2

3

0

2

3

0

1

ENC_STATUS

2

X_ENC

W

R

3

X_ENC

4

ENC_CONST

W

R

5

ENC_LATCH

6

SPI_RX_DATA

R

7

SPI_TX_DATA

W

R

8

SPI_CONF

9

SPI_STATUS

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

SPI_LENGTH

W

R

SPI_TIME

I2C_TIMEBASE

I2C_CONTROL

I2C_STATUS

I2C_ADDRESS

I2C_DATA_R

W

R

I2C_DATA_W

W

R

SD_CH0_STEPRATE

SD_CH1_STEPRATE

SD_CH2_STEPRATE

SD_CH0_STEPCOUNT

SD_CH1_STEPCOUNT

SD_CH2_STEPCOUNT

SD_CH0_STEPTARGET

SD_CH1_STEPTARGET

SD_CH2_STEPTARGET

SD_CH0_COMPARE

R

W

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Register Function

SD_CH1_COMPARE

Write/Read

Size (Byte) Padding Bytes (see section

7.8)

28

29

30

31

32

33

34

35

36

37

38

39

40

41

42

43

44

45

46

47

48

49

50

51

52

53

54

55

56

57

58

59

60

W

R

4

6

3

8

2

4

1

4

2

3

4

1

8

4

8

4

0

2

1

0

2

0

3

0

2

1

0

3

0

SD_CH2_COMPARE

SD_CH0_NEXTSR

SD_CH1_NEXTSR

SD_CH2_NEXTSR

SD_STEPLENGTH

SD_DELAY

SD_CFG

PWM_CFG

PWM1

PWM2

PWM3

PWM4

PWM1_CNTRSHFT

PWM2_CNTRSHFT

PWM3_CNTRSHFT

PWM4_CNTRSHFT

PWM_PULSE_B_PULSE_A

PWM_PULSE_LENGTH

GPO

GPI

GPIO_CONFIG

DAC_VAL

W

R

MFCIO_IRQ_CFG

MFCIO_IRQ_FLAGS

WD_TIME

W

R

WD_CFG

WD_OUT_MASK_POL

WD_OE_POL

WD_IN_MASK_POL

WD_MAX

HV_ANA_STATUS

unused/reserved

R

-

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Register Function

Write/Read

Size (Byte) Padding Bytes (see section

7.8)

61

62

63

64

65

66

unused/reserved

-

0

4

2

1

0

2

3

SYNC1_SYNC0_EVENT_CNT R (ECAT only)

HVIO_CFG

W

BUCK_CONV_CFG

AL_OVERRIDE

Table 124: MFC IO Register Overview for TMC8461-BA

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7.3 MFC IO Register Set

7.3.1 Incremental Encoder Interface

7.3.1.1 Register 0 – ENC_MODE

Bit

Description

ECAT

PDI

Range [Unit]

0

pol_A

r/w

Required A polarity for an N channel event (0: neg., 1: pos.)

1

2

3

pol_B

r/w

Required B polarity for an N channel event (0: neg., 1: pos.)

pol_N

Deﬁnes active polarity of N (0: neg., 1: pos.)

ignore_AB

0: An N event occurs only when polarities given by pol_N,

pol_A and pol_B match.

1: Ignore A and B polarity for N channel event

4

clr_cont

r/w

1: Always latch or latch and clear X_ENC upon an N event

(once per revolution, it is recommended to combine this

setting with edge sensitive N event)

5

clr_once

r/w

1: Latch or latch and clear X_ENC on the next N event fol-

lowing the write access

7:6

neg_edge bit n & pos_edge bit p

n p: N channel event sensitivity

0 0: N channel event is active during an active N event level

0 1: N channel is valid upon active going N event

1 0: N channel is valid upon inactive going N event

1 1: N channel is valid upon active going and inactive going

N event

8

9

clr_enc_x

r/w

0: On N event, X_ENC becomes latched to ENC_LATCH only

1: Latch & additionally clear X_ENC at N-event

latch_x_act

1: Also latch XACTUAL position together with X_ENC. Allows

latching the ramp generator position upon an N channel

event as selected by pos_edge and neg_edge.

10

enc_sel_decimal

0: Encoder prescaler divisor binary mode: Counts

ENC_CONST(fractional part) / 65536

1: Encoder prescaler divisor decimal mode: Counts in

ENC_CONST(fractional part) / 10000

r/w

-/-

15:11 Reserved

-/-

Table 125: MFC IO Register 0 – ENC_MODE

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7.3.1.2 Register 1 – ENC_STATUS

Bit

Description

ECAT

PDI

Range [Unit]

0

n_event

r+c/-

1: Encoder N event detected. Status bit is

cleared on read: Read (R) + clear (C)

This event can also be ORed into the interrupt

output signal. See Register 51 and 52.

7:1

Reserved

r/-

Table 126: MFC IO Register 1 – ENC_STATUS

7.3.1.3 Register 2 – X_ENC (write)

Bit

Description

ECAT

PDI

Range [Unit]

31:0

Actual encoder position (signed)

r/w

−2³¹. . . +(2³¹) − 1

Table 127: MFC IO Register 2 – X_ENC (write)

7.3.1.4 Register 3 – X_ENC (read)

Bit

Description

ECAT

PDI

Range [Unit]

31:0

Actual encoder position (signed)

r/-

−2³¹. . . +(2³¹) − 1

Table 128: MFC IO Register 3 – X_ENC (read)

7.3.1.5 Register 4 – ENC_CONST

Bit

Description

ECAT

PDI

Range [Unit]

31:0

Accumulation constant (signed) 16 bit integer r/w

part, 16 bit fractional part

r/w

binary:

±[µsteps/2¹⁶]

±(0 . . . 32767.9999847)

X_ENC accumulates

decimal:

ENC_CONST

±

(binary)

±(0 . . . 32767.9999)

16

∗X_ENC)

or⁽²

reset default =

65536)

1.0(=

ENC_CONST

(10⁴∗X_ENC)

±

(decimal)

ENC_MODE bit enc_sel_decimal switches be-

tween decimal and binary setting. Use the sign,

to match rotation direction!

Table 129: MFC IO Register 4 – ENC_CONST

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7.3.1.6 Register 5 – ENC_LATCH

Bit

Description

ECAT

PDI

Range [Unit]

31:0

Encoder position X_ENC latched on N event

r/-

−2³¹. . . +(2³¹) − 1

Table 130: MFC IO Register 5 – ENC_LATCH

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7.3.2 SPI Master Interface

7.3.2.1 Register 6 – SPI_RX_DATA

Bit

Description

ECAT

PDI

Range [Unit]

63:0

Received data from last SPI transfer

For SPI transfers with less than 64 bit, the upper

bits of this register are unused

r/-

Table 131: MFC IO Register 6 – SPI_RX_DATA

7.3.2.2 Register 7 – SPI_TX_DATA

Bit

Description

ECAT

PDI

Range [Unit]

63:0

Data to transmit on next SPI transfer

For SPI transfers with less than 64 bit, the upper

bits of this register are unused

-/w

Table 132: MFC IO Register 7 – SPI_TX_DATA

Note

Unless conﬁgured otherwise in the SPI_CONF register (bits 10:8), writing data

into this register automatically starts transmission as soon as the highest byte

(according to SPI_LENGTH conﬁguration) has been written.

All bytes to be transmitted must be written to the register within a single access

(via MFC IO Control SPI or from the DPRAM) to ensure data consistency.

7.3.2.3 Register 8 – SPI_CONF

Bit

1:0

2

Description

ECAT

r/w

PDI

r/w

Range [Unit]

Selection of SPI slave

reserved

r/w

3

Keep CS low after transfer for transfers greater r/w

than 64bit

4

5

6

7

transmit LSB ﬁrst

SPI clock phase

SPI clock polarity

reserved

r/w

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Bit

Description

ECAT

PDI

Range [Unit]

10:8

Trigger conﬁguration for transmission start

000₂: Start when data is written into TX register

001₂: Start on beginning of PWM cycle

010₂: Start on center of PWM cycle

011₂: Start on PWM A mark

r/w

0₁₀. . . 7₁₀

100₂: Start on PWM B mark

101₂: Start on PWM A&B marks

110₂: reserved

111₂: Start on single trigger (Bit 15)

14:11 reserved

r/w

15

Start transfer once when this bit is set and trig- r/w

ger conﬁguration is set to 111₂

Table 133: MFC IO Register 8 – SPI_CONF

7.3.2.4 Register 9 – SPI_STATUS

Bit

0

Description

ECAT

r/-

PDI

r/-

Range [Unit]

SPI transfer done, ready for next transfer

7:1

unused

r/-

0

Table 134: MFC IO Register 9 – SPI_STATUS

7.3.2.5 Register 10 – SPI_LENGTH

Bit

Description

ECAT

PDI

Range [Unit]

5:0

SPI datagram length

-/w

0₁₀. . . 63₁₀[bit]

Example: 000111₂= 8 bit datagram

Example: 111111₂= 64 bit datagram

7:6

unused

-/w

0

Table 135: MFC IO Register 10 – SPI_LENGTH

7.3.2.6 Register 11 – SPI_TIME

Bit

Description

ECAT

PDI

Range [Unit]

7:0

SPI_BIT_DURATION

-/w

0₁₀. . . 255₁₀

25MHz

f_{SP I}

=

(4+(2∗SP I_BIT _DURAT ION))

Table 136: MFC IO Register 11 – SPI_TIME

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7.3.3 I2C Master Interface

7.3.3.1 Register 12 – I2C_TIMEBASE

Bit

Description

ECAT

PDI

Range [Unit]

7:0

I2C_BIT_DURATION

-/w

0₁₀. . . 255₁₀[µs]

0 = oﬀ

1 . . . 255 = 1µs . . . 255µs = 250kbit/s . . . 980bit/s

Table 137: MFC IO Register 12 – I2C_TIMEBASE

7.3.3.2 Register 13 – I2C_CONTROL

Bit

0

Description

ECAT

-/w

PDI

-/w

Range [Unit]

receive Data and send NACK

receive Data and send ACK

Send Data (content of data I2C_DATA_W)

1

-/w

2

-/w

3

Send Address (content of address register -/w

I2C_ADDRESS), incl. R/nW bit

4

Send Stop Condition

-/w

5

Send Start Condition (also Repeated Start)

unused

7:6

Table 138: MFC IO Register 13 – I2C_CONTROL

7.3.3.3 Register 14 – I2C_STATUS

Bit

0

Description

ECAT

r/-

PDI

r/-

Range [Unit]

St - Start condition sent

1

RSt - Repeated Start condition sent

ADR - Transmit Address mode

RX - Read from Slave mode

TX - Write to slave mode

ACK - Acknowledge received/sent

NAK - Not Acknowledge received/sent

ERR - Error Flag

r/-

2

r/-

3

r/-

4

r/-

5

r/-

6

r/-

7

r/-

Table 139: MFC IO Register 14 – I2C_STATUS

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7.3.3.4 Register 15 – I2C_ADDRESS

Bit

0

Description

R/nW bit

ECAT

-/w

PDI

-/w

Range [Unit]

7:1

Address

-/w

Table 140: MFC IO Register 15 – I2C_ADDRESS

7.3.3.5 Register 16 – I2C_DATA_R

Bit

Description

ECAT

PDI

Range [Unit]

7:0

Received data

r/-

Table 141: MFC IO Register 16 – I2C_DATA_R

7.3.3.6 Register 17 – I2C_DATA_W

Bit

Description

ECAT

PDI

Range [Unit]

7:0

Transmit data

-/w

Table 142: MFC IO Register 17 – I2C_DATA_W

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7.3.4 Step and Direction Signal Generator

7.3.4.1 Register 18 – SD_CH0_STEPRATE

Bit

Description

ECAT

PDI

Range [Unit]

31:0

Signed accumulation constant c for SD_CH0.

This accumulation constant determines the

time tSTEP between two successive steps and

thereby the step frequency.

-/w

0. . . +(2³²) − 1

The Sign (MSB) of this accumulation constant is

used for the direction signal output (D0, D0n).

The accumulation constant c is 2th comple-

ment.

(see also Section 7.14)

Table 143: MFC IO Register 18 – SD_CH0_STEPRATE

7.3.4.2 Register 19 – SD_CH1_STEPRATE

Bit

Description

ECAT

PDI

Range [Unit]

31:0

Signed accumulation constant c for SD_CH1.

This accumulation constant determines the

time tSTEP between two successive steps and

thereby the step frequency.

-/w

0. . . +(2³²) − 1

The Sign (MSB) of this accumulation constant is

used for the direction signal output (D1, D1n).

The accumulation constant c is 2th comple-

ment.

(see also Section 7.14)

Table 144: MFC IO Register 19 – SD_CH1_STEPRATE

7.3.4.3 Register 20 – SD_CH2_STEPRATE

Bit

Description

ECAT

PDI

Range [Unit]

31:0

Signed accumulation constant c for SD_CH2.

This accumulation constant determines the

time tSTEP between two successive steps and

thereby the step frequency.

-/w

0. . . +(2³²) − 1

The Sign (MSB) of this accumulation constant is

used for the direction signal output (D2, D2n).

The accumulation constant c is 2th comple-

ment.

(see also Section 7.14)

Table 145: MFC IO Register 20 – SD_CH2_STEPRATE

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7.3.4.4 Register 21 – SD_CH0_STEPCOUNT

Bit

Description

ECAT

PDI

Range [Unit]

31:0

Step counter for SD_CH0.

Counting up/down depending on step direc-

tion.

r/-

−2³¹. . . +(2³¹) − 1

Table 146: MFC IO Register 21 – SD_CH0_STEPCOUNT

7.3.4.5 Register 22 – SD_CH1_STEPCOUNT

Bit

Description

ECAT

PDI

Range [Unit]

31:0

Step counter for SD_CH1.

Counting up/down depending on step direc-

tion.

r/-

−2³¹. . . +(2³¹) − 1

Table 147: MFC IO Register 22 – SD_CH1_STEPCOUNT

7.3.4.6 Register 23 – SD_CH2_STEPCOUNT

Bit

Description

ECAT

PDI

Range [Unit]

31:0

Step counter for SD_CH2.

Counting up/down depending on step direc-

tion.

r/-

−2³¹. . . +(2³¹) − 1

Table 148: MFC IO Register 23 – SD_CH2_STEPCOUNT

7.3.4.7 Register 24 – SD_CH0_STEPTARGET

Bit

Description

ECAT

PDI

Range [Unit]

31:0

Steps pulses (= distance) to be made for -/w

SD_CH0.

Can be overwritten at any time.

-/w

0. . . +(2³²) − 1

When zero, no more step pulses are generated

at output S0 or S0n,

Reading the register returns the remaining

number of step pulses to be generated.

Table 149: MFC IO Register 24 – SD_CH0_STEPTARGET

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7.3.4.8 Register 25 – SD_CH1_STEPTARGET

Bit

Description

ECAT

PDI

Range [Unit]

31:0

Steps pulses (= distance) to be made for -/w

SD_CH1.

Can be overwritten at any time.

-/w

0. . . +(2³²) − 1

When zero, no more step pulses are generated

at output S1 or S1n,

Reading the register returns the remaining

number of step pulses to be generated.

Table 150: MFC IO Register 25 – SD_CH1_STEPTARGET

7.3.4.9 Register 26 – SD_CH2_STEPTARGET

Bit

Description

ECAT

PDI

Range [Unit]

31:0

Steps pulses (= distance) to be made for -/w

SD_CH2.

Can be overwritten at any time.

-/w

0. . . +(2³²) − 1

When zero, no more step pulses are generated

at output S2 or S2n,

Reading the register returns the remaining

number of step pulses to be generated.

Table 151: MFC IO Register 26 – SD_CH2_STEPTARGET

7.3.4.10 Register 27 – SD_CH0_COMPARE

Bit

Description

ECAT

PDI

Range [Unit]

31:0

Comparison value to compare with actual value -/w

of SD_CH0_STEPCOUNT.

-/w

−2³¹. . . +(2³¹) − 1

When both are equal and bit 6 in SD_CFG

is set, the next step rate as conﬁgured in

SD_CH0_NEXTSR will be assigned and used for

SD_CH0_SR.

Table 152: MFC IO Register 27 – SD_CH0_COMPARE

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7.3.4.11 Register 28 – SD_CH1_COMPARE

Bit

Description

ECAT

PDI

Range [Unit]

31:0

Comparison value to compare with actual value -/w

of SD_CH1_STEPCOUNT.

-/w

−2³¹. . . +(2³¹) − 1

When both are equal and bit 6 in SD_CFG

is set, the next step rate as conﬁgured in

SD_CH1_NEXTSR will be assigned and used for

SD_CH1_SR.

Table 153: MFC IO Register 28 – SD_CH1_COMPARE

7.3.4.12 Register 29 – SD_CH2_COMPARE

Bit

Description

ECAT

PDI

Range [Unit]

31:0

Comparison value to compare with actual value -/w

of SD_CH2_STEPCOUNT.

-/w

−2³¹. . . +(2³¹) − 1

When both are equal and bit 6 in SD_CFG

is set, the next step rate as conﬁgured in

SD_CH2_NEXTSR will be assigned and used for

SD_CH2_SR.

Table 154: MFC IO Register 29 – SD_CH2_COMPARE

7.3.4.13 Register 30 – SD_CH0_NEXTSR

Bit

Description

ECAT

PDI

Range [Unit]

31:0

Next accumulation constant that will be written -/w

to SD_CH0_STEPRATE at compare event.

-/w

0. . . +(2³²) − 1

Table 155: MFC IO Register 30 – SD_CH0_NEXTSR

7.3.4.14 Register 31 – SD_CH1_NEXTSR

Bit

Description

ECAT

PDI

Range [Unit]

31:0

Next accumulation constant that will be written -/w

to SD_CH1_STEPRATE at compare event.

-/w

0. . . +(2³²) − 1

Table 156: MFC IO Register 31 – SD_CH1_NEXTSR

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7.3.4.15 Register 32 – SD_CH2_NEXTSR

Bit

Description

ECAT

PDI

Range [Unit]

31:0

Next accumulation constant that will be written -/w

to SD_CH2_STEPRATE at compare event.

-/w

0. . . +(2³²) − 1

Table 157: MFC IO Register 32 – SD_CH2_NEXTSR

7.3.4.16 Register 33 – SD_STEPLENGTH

Bit

Description

ECAT

PDI

Range [Unit]

15:0

Conﬁgurable step pulse length for SD_CH0 in -/w

terms of 25MHz clock cycles.

-/w

0. . . +(2¹⁶) − 1

31:16 Conﬁgurable step pulse length for SD_CH1 in -/w

-/w

0. . . +(2¹⁶) − 1

terms of 25MHz clock cycles.

47:32 Conﬁgurable step pulse length for SD_CH2 in -/w

terms of 25MHz clock cycles.

Table 158: MFC IO Register 33 – SD_STEPLENGTH

Note

Maximum step length: The individual step pulse length t_{ST EP _P ULSE}[s] must be

lower than the time t_{ST EP}[s] between step pulses to actually see step pulses. The

condition t_{ST EP _P ULSE}< t_{ST EP}must be ensured by the application.

Also refer to Section 7.14 for more details and formulas for calculation.

7.3.4.17 Register 34 – SD_DELAY

Bit

Description

ECAT

PDI

Range [Unit]

15:0

Conﬁgurable step-to-direction delay for -/w

SD_CH0 in terms of 25MHz clock cycles.

-/w

0. . . +(2¹⁶) − 1

31:16 Conﬁgurable step-to-direction delay for -/w

-/w

0. . . +(2¹⁶) − 1

SD_CH1 in terms of 25MHz clock cycles.

47:32 Conﬁgurable step-to-direction delay for -/w

SD_CH2 in terms of 25MHz clock cycles.

Table 159: MFC IO Register 34 – SD_DELAY

Note

Step-to-direction delay is the delay between the ﬁrst step pulse after a change of

the direction.

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7.3.4.18 Register 35 – SD_CFG

Bit

0

Description

ECAT

PDI

-/w

Range [Unit]

0/1 = disable/enable SD_CH0

-/w

1

0

=

generate

N

pulses based on -/w

SD_CH0_STEPTARGET register value

1 = continuous mode

2

3

4

5

6

S0 and S0n step pulse signal polarity

D0 and D0n direction signal polarity

1 = clears SD_CH0_STEPCOUNT

reserved

-/w

use SD_CH0_NEXTSR for SD_CH0_STEPRATE on -/w

compare event

7

8

9

reserved

-/w

0/1 = disable/enable SD_CH1

0

=

generate

N

pulses based on -/w

SD_CH1_STEPTARGET register value

1 = continuous mode

10

11

12

13

14

S1 and S1n step pulse signal polarity

D1 and D1n direction signal polarity

1 = clears SD_CH1_STEPCOUNT

reserved

-/w

use SD_CH1_NEXTSR for SD_CH1_STEPRATE on -/w

compare event

15

16

17

reserved

-/w

0/1 = disable/enable SD_CH2

0

=

generate

N

pulses based on -/w

SD_CH2_STEPTARGET register value

1 = continuous mode

18

19

20

21

22

S2 and S2n step pulse signal polarity

D2 and D2n direction signal polarity

1 = clears SD_CH2_STEPCOUNT

reserved

-/w

use SD_CH2_NEXTSR for SD_CH2_STEPRATE on -/w

compare event

23

reserved

-/w

Table 160: MFC IO Register 35 – SD_CFG

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7.3.5 PWM Unit

7.3.5.1 Register 36 – PWM_CFG

Bit

Description

ECAT

-/w

PDI

-/w

Range [Unit]

0. . . +(2¹²) − 1

11:0

PWM max count

15:12 unused

-/w

18:16 PWM ch0 chopper mode

-/w

See Section 7.15 for more details.

19

unused

-/w

22:20 PWM ch1 chopper mode

See Section 7.15 for more details.

unused

26:24 PWM ch2 chopper mode

See Section 7.15 for more details.

unused

30:28 PWM ch3 chopper mode

See Section 7.15 for more details.

unused

23

-/w

27

-/w

31

-/w

33:32 PWM alignment for all PWM channels

39:34 unused

47:40 Signal Polarities for all PWM channels

Bit 40 = PWM low sides polarity

Bit 41 = PWM high sides polarity

Bit 42 = PWM AB pulses polarity

Bit 43 = PWM B pulses polarity

Bit 44 = PWM Center pulses polarity

Bit 45 = PWM A pulses polarity

Bit 46 = PWM Zero pulses polarity

47

unused

-/w

55:48 BBM low sides.

0. . . +(2⁸) − 1

Brake before make time in terms of 100MHz

clock cycles for low side MOSFET control

63:56 BBM high sides.

-/w

Brake before make time in terms of 100MHz

clock cycles for high side MOSFET control

Table 161: MFC IO Register 36 – PWM_CFG

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7.3.5.2 Register 37 – PWM1

Bit

Description

ECAT

-/w

PDI

-/w

Range [Unit]

0. . . +(2¹²) − 1

11:0

PWM duty cycle (on time) for PWM1

15:12 unused

-/w

Table 162: MFC IO Register 37 – PWM1

7.3.5.3 Register 38 – PWM2

Bit

Description

ECAT

-/w

PDI

Range [Unit]

0. . . +(2¹²) − 1

11:0

PWM duty cycle (on time) for PWM2

-/w

15:12 unused

-/w

Table 163: MFC IO Register 38 – PWM2

7.3.5.4 Register 39 – PWM3

Bit

Description

ECAT

-/w

PDI

Range [Unit]

0. . . +(2¹²) − 1

11:0

PWM duty cycle (on time) for PWM3

-/w

15:12 unused

-/w

Table 164: MFC IO Register 39 – PWM3

7.3.5.5 Register 40 – PWM4

Bit

Description

ECAT

-/w

PDI

Range [Unit]

0. . . +(2¹²) − 1

11:0

PWM duty cycle (on time) for PWM4

-/w

15:12 unused

-/w

Table 165: MFC IO Register 40 – PWM4

7.3.5.6 Register 41 – PWM1_CNTRSHFT

Bit

Description

ECAT

PDI

Range [Unit]

11:0

Shift value for PWM1 to shift PWM1 high side -/w

and low side signal edges with respect to the

aligned PWM counter.

-/w

0. . . +(2¹²) − 1

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Bit

Description

ECAT

PDI

Range [Unit]

15:12 unused

-/w

Table 166: MFC IO Register 41 – PWM1_CNTRSHFT

7.3.5.7 Register 42 – PWM2_CNTRSHFT

Bit

Description

ECAT

PDI

Range [Unit]

11:0

Shift value for PWM2 to shift PWM2 high side -/w

and low side signal edges with respect to the

aligned PWM counter.

-/w

0. . . +(2¹²) − 1

15:12 unused

-/w

Table 167: MFC IO Register 42 – PWM2_CNTRSHFT

7.3.5.8 Register 43 – PWM3_CNTRSHFT

Bit

Description

ECAT

PDI

Range [Unit]

11:0

Shift value for PWM3 to shift PWM3 high side -/w

and low side signal edges with respect to the

aligned PWM counter.

-/w

0. . . +(2¹²) − 1

15:12 unused

-/w

Table 168: MFC IO Register 43 – PWM3_CNTRSHFT

7.3.5.9 Register 44 – PWM4_CNTRSHFT

Bit

Description

ECAT

PDI

Range [Unit]

11:0

Shift value for PWM4 to shift PWM4 high side -/w

and low side signal edges with respect to the

aligned PWM counter.

-/w

0. . . +(2¹²) − 1

15:12 unused

-/w

Table 169: MFC IO Register 44 – PWM4_CNTRSHFT

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7.3.5.10 Register 45 – PWM_PULSE_B_PULSE_A

Bit

Description

ECAT

PDI

Range [Unit]

11:0

Programmable trigger pulse A value with re- -/w

spect to the common PWM counter.

-/w

0. . . +(2¹²) − 1

15:12 unused

-/w

27:16 Programmable trigger pulse B value with re- -/w

0. . . +(2¹²) − 1

spect to the common PWM counter.

31:28 unused

-/w

Table 170: MFC IO Register 45 – PWM_PULSE_B_PULSE_A

7.3.5.11 Register 46 – PWM_PULSE_LENGTH

Bit

Description

ECAT

PDI

Range [Unit]

7:0

Programmable pulse length for trigger pulse A, -/w

B, PWM start, and PWM center.

-/w

0. . . +(2⁸) − 1

Table 171: MFC IO Register 46 – PWM_PULSE_LENGTH

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7.3.6 General Purpose I/Os

7.3.6.1 Register 47 – GPO

Bit

Description

ECAT

PDI

-/w

Range [Unit]

15:0

GPOx output values

-/w

31:16 GPOx safe state (when emergency input pin -/w

MFC_NES = ’0’)

Table 172: MFC IO Register 47 – GPO

Note

Bits [31:24] are not available in -ES sample devices.

7.3.6.2 Register 48 – GPI

Bit

Description

ECAT

PDI

Range [Unit]

15:0

GPIx input values

r/-

Table 173: MFC IO Register 48 – GPI

7.3.6.3 Register 49 – GPIO_CONFIG

Bit

Description

ECAT

PDI

Range [Unit]

15:0

Output enable conﬁguration for the GPOx sig- -/w

-/w

nals

Disabled = tristated.

Table 174: MFC IO Register 49 – GPIO_CONFIG

Note

GPIO_CONFIG is not available in -ES sample devices.

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7.3.7 DAC Unit

7.3.7.1 Register 50 – DAC_VAL

Bit

Description

ECAT

PDI

Range [Unit]

15:0

16 bit DAC value which is converted to a pseu- -/w

dorandom binary sequence at the DAC output

-/w

Table 175: MFC IO Register 50 – DAC_VAL

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7.3.8 IRQ Control Block

7.3.8.1 Register 51 – MFCIO_IRQ_CFG

Bit

0

Description

ECAT

-/w

PDI

-/w

Range [Unit]

ABN encoder unit N-channel event

SD_CH0 target reached event

SD_CH1 target reached event

SD_CH2 target reached event

SD_CH0 compare value event

SD_CH1 compare value event

SD_CH2 compare value event

SPI new data available event

I2C new data available event

I2C transmit complete event

1

2

3

4

5

6

7

8

9

10

I2C new data available event OR I2C transmit -/w

complete event

11

12

13

14

15

16

17

18

19

Watchdog Timeout event

PWM zero pulse event

-/w

PWM center pulse event

PWM A pulse event

PWM B pulse event

HV_OT_FLAG has been set

BVOUT_OT_FLAG has been set

BVOUT_SC_FL has been set

B3V3_SC_FLAG has been set

22:20 unused/reserved

23

emergency input pin MFC_NES event

Table 176: MFC IO Register 51 – MFCIO_IRQ_CFG

Note

This register is used for masking / enabling the diﬀerent IRQ sources, which are

or-ed together to set the common MFCIO_IRQ output signal. The MFCIO_IRQ is a

dedicated package pin of TMC8461, which can be connected to a local application

controller.

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7.3.8.2 Register 52 – MFCIO_IRQ_FLAGS

Bit

0

Description

ECAT

r/-

PDI

r/-

Range [Unit]

ABN encoder unit N-channel event ﬂag

SD_CH0 target reached event ﬂag

SD_CH1 target reached event ﬂag

SD_CH2 target reached event ﬂag

SD_CH0 compare value event ﬂag

SD_CH1 compare value event ﬂag

SD_CH2 compare value event ﬂag

SPI new data available event ﬂag

I2C new data available event ﬂag

I2C transmit complete event ﬂag

1

r/-

2

r/-

3

r/-

4

r/-

5

r/-

6

r/-

7

r/-

8

r/-

9

r/-

10

I2C new data available event OR I2C transmit r/-

complete event ﬂag

11

12

13

14

15

16

17

18

19

Watchdog Timeout event ﬂag

PWM zero pulse event ﬂag

PWM center pulse event ﬂag

PWM A pulse event ﬂag

PWM B pulse event ﬂag

HV_OT_FLAG

r/-

-/-

r/-

-/-

r/-

BVOUT_OT_FLAG

BVOUT_SC_FL

B3V3_SC_FLAG

22:20 unused/reserved

23

emergency input pin MFC_NES event ﬂag

Table 177: MFC IO Register 52 – MFCIO_IRQ_FLAGS

Reading this registers clears all ﬂags.

Note

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7.3.9 Watchdog

7.3.9.1 Register 53 – WD_TIME

Bit

Description

ECAT

PDI

Range [Unit]

31:0

Watchdog time 32 bit/unsigned

0 = Watchdog oﬀ,

> 0 = number of 25MHz clock cycles

-/w

0 . . . + (2³²) − 1

Table 178: MFC IO Register 53 – WD_TIME

7.3.9.2 Register 54 – WD_CFG

Bit

Description

ECAT

PDI

Range [Unit]

0

cfg_persistent

-/w

0 = The watchdog action ends when the next

trigger event occurs

1 = A timeout situation can only be cleared by

rewriting WD_TIME

1

2

cfg_pdi_csn_enable

-/w

1 = Retrigger by positive edge on PDI_SPI_CSN

cfg_mfc_csn_enable

1

=

Retrigger by positive edge on

MFC_CTRL_SPI_CSN

3

4

cfg_sof_enable

-/w

1 = Retrigger by ETHERCAT start of frame

cfg_in_edge

0 = Retrigger by input condition becoming false

1 = Retrigger by input condition becoming true

6:5

7

unused/reserved

-/-

cfg_wd_active

1 = Signals an active watchdog timeout

-/w

Table 179: MFC IO Register 54 – WD_CFG

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7.3.9.3 Register 55 – WD_OUT_MASK_POL

Bit

Description

ECAT

PDI

Range [Unit]

23:0

WD_OUT_POL,

-/w

Polarity for outputs aﬀected by watchdog ac-

tion.

each bit corresponds to one output line.

The polarity describes the output level desired

upon watchdog event.

31:24 unused/reserved

55:32 WD_OUT_MASK,

-/-

-/w

Each bit corresponds to one output line.

0 = Output is not aﬀected

1 = Output [i] becomes set to WD_OUT_POL[i]

upon watchdog event.

63:56 unused/reserved

-/-

Table 180: MFC IO Register 55 – WD_OUT_MASK_POL

Note

See Section 7.19 for the detailed signal mapping of WD_OUT_MASK_POL.

7.3.9.4 Register 56 – WD_OE_POL

Bit

Description

ECAT

PDI

Range [Unit]

31:0

I/O Output enable level for outputs aﬀected by -/w

watchdog action.

-/w

Each bit corresponds to one output line.

The polarity describes the OE setting desired

upon watchdog action (1 = output, 0 = input).

Table 181: MFC IO Register 56 – WD_OE_POL

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7.3.9.5 Register 57 – WD_IN_MASK_POL

Bit

Description

ECAT

PDI

Range [Unit]

23:0

WD_IN_POL,

-/w

Input signal levels for watchdog re-triggering.

Each bit corresponds to one input line.

The polarity describes the input level for signals

selected by WD_IN_MASK required to re-trigger

the watchdog timer.

31:24 unused/reserved

55:32 WD_IN_MASK,

-/-

-/w

Each bit corresponds to one input line.

0 = Input is not selected

1

=

Input I/O[i] must reach polarity

WD_IN_POL[i] to re-trigger the watchdog

timer.

63:56 unused/reserved

-/-

Table 182: MFC IO Register 57 – WD_IN_MASK_POL

Note

See Section 7.19 for the detailed signal mapping of WD_IN_MASK_POL.

7.3.9.6 Register 58 – WD_MAX

Bit

Description

ECAT

PDI

Range [Unit]

31:0

Peak value reached by watchdog timeout r/-

counter.

Reset to 0 by writing to WD_TIME.

r/-

0 . . . + (2³²) − 1

Table 183: MFC IO Register 58 – WD_MAX

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7.3.10 High Voltage Status and General Control

7.3.10.1 Register 59 – HV_ANA_STATUS

Bit

Description

ECAT

PDI

Range [Unit]

7:0

HVIO_OUTPUT_HV_DETECT,

bit[i] = 1 = high voltage detected at HV output [i]

r/-

15:8

HV_SHORT2GND_DETECT,

r/-

bit[i] = 1 = short to ground detected at HV IO [i-8]

23:16 HV_SHORT2VS_DETECT,

bit[i] = 1 = high voltage detected at HV IO [i-16]

24

25

26

27

HV_OT_FLAG

r/-

B3V3_SC_FLAG

BVOUT_SC_FLAG

BVOUT_OT_FLAG

31:28 unused/reserved

Table 184: MFC IO Register 59 – HV_ANA_STATUS

7.3.10.2 Register 63 – SYNC1_SYNC0_EVENT_CNT

Bit

Description

ECAT

r/-

PDI

r/-

Range [Unit]

15:0

SYNC_OUT0 event counter value

0 . . . + (2¹⁶) − 1

31:16 SYNC_OUT1 event counter value

r/-

Table 185: MFC IO Register 63 – SYNC1_SYNC0_EVENT_CNT

Note

Reading does not clear counters. Counters are running all the time and wrap

when maximum count is reached.

Register 63 can only be read when mapped to the ECAT Process Data RAM. It

cannot be read from the MCF CTRL SPI interface.

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7.3.10.3 Register 64 – HVIO_CFG

Bit

Description

ECAT

PDI

Range [Unit]

7:0

HV_SLOPE_SLOW

-/w

With these option bits set to 1, the output slope

of the MFC_HV[i] pin can be slowed down.

15:8

HV_WEAK_HIGH

-/w

With these option bits set to 1, the high level

driver strength of the MFC_HV[i-8] pin can be

reduced.

23:16 HV_WEAK_LOW

With these option bits set to 1, the low level

driver strength of the MFC_HV[i-16] pin can be

reduced.

27:24 HV_DIFF_INPUT_EN

With these option bits set to 1, two of the

MFC_HV inputs can be combined to a diﬀer-

ential input pair.

Bit 24 = 1 = MFC_HV3 & MFC_HV0

Bit 25 = 1 = MFC_HV4 & MFC_HV1

Bit 26 = 1 = MFC_HV5 & MFC_HV2

Bit 27 = 1 = MFC_HV7 & MFC_HV6

31:28 unused/reserved

-/-

Table 186: MFC IO Register 64 – HVIO_CFG

Note

This register can only be accessed from MFC CTRL SPI interface.

It cannot directly be accessed from ECAT master interface.

Nevertheless, the register content can be preloaded from SII EEPROM at startup.

Therefore, see Section 7.4.

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7.3.10.4 Register 65 – BUCK_CONV_CFG

Bit

Description

ECAT

PDI

Range [Unit]

1:0

B3V3_SAW_FREQ

3.3V switching regulator switching frequency

-/w

(nominal values)

0 : 250kHz

1 : 125kHz

2 : 500kHz

3 : 1MHz

3:2

5:4

6

B3V3_FB_AMPL

-/w

3.3V switching regulator voltage error feedback

ampliﬁcation

0 : 100%

1 : 150%

2 : 200%

3 : 50%

B3V3_FB_CAP

3.3V switching regulator dampening of voltage

error feedback

0 : 100%

1 : 150%

2 : 200%

3 : 50%

B3V3_SC_DISABLE

3.3V switching regulator disable cycle-to-cycle

overcurrent protection

0 : Protection enabled

1 : No protection

7

unused/reserved

-/w

9:8

BVOUT_SAW_FREQ

Adjustable switching regulator switching fre-

quency (nominal values)

0 : 250kHz

1 : 125kHz

2 : 500kHz

3 : 1MHz

11:10 BVOUT_FB_AMPL

Adjustable switching regulator voltage error

-/w

feedback ampliﬁcation

0 : 100%

1 : 150%

2 : 200%

3 : 50%

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Bit

Description

ECAT

PDI

Range [Unit]

13:12 BVOUT_FB_CAP

-/w

Adjustable switching regulator dampening of

voltage error feedback

0 : 100%

1 : 150%

2 : 200%

3 : 50%

14

15

BVOUT_SC_DISABLE

-/w

Adjustable switching regulator disable cycle-to-

cycle overcurrent protection

0 : Protection enabled

1 : No protection

BVOUT_DISABLE

Disable adjustable switching regulator

0 : Switching regulator enabled

1 : Switching regulator disabled

Table 187: MFC IO Register 65 – BUCK_CONV_CFG

Note

This register can only be accessed from MFC CTRL SPI interface.

It cannot directly be accessed from ECAT master interface.

Nevertheless, the register content can be preloaded from SII EEPROM at startup.

Therefore, see Section 7.4.

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7.3.11 Application Layer Control

7.3.11.1 Register 66 – AL_OVERRIDE

Bit

Description

ECAT

PDI

Range [Unit]

0

0 = no override

1 = override AL state

-/w

7:1

unused/reserved

-/-

Table 188: MFC IO Register 66 – AL_OVERRIDE

Note

The bit controls override conﬁguration of the 24 MFC IO output ports regarding

the output port availability with respect to the actual EtherCAT Slave Controller’s

AL state.

Typically, in an EtherCAT slave the output ports are only available/active when AL

state = "‘OP"’ (operational). If the override bit is set, the AL state is ignored and

the MFC IO ports are fully available via the MFC IO Control Interface.

The ABN functional block, IRQ conﬁguration, Watchdog block are not aﬀected by

this conﬁguration option since they only have input ports/signals.

! This register can only be accessed from MFC IO Control Interface. It cannot be

accessed from ECAT master side.

The input ports are always readable via the MFC IO Control Interface.

When an input port is conﬁgured to be accessed by the EtherCAT master, it can

only be read when the EtherCAT state machine is in safe-operational state or

operational state.

When an output port/value is conﬁgured to be controlled by the EtherCAT master,

this is only possible when the EtherCAT state machine is in operational state

because. This is deﬁned in the EtherCAT standard.

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7.4 SII EEPROM MFC IO Block Parameter Map

This section describes the part of the EEPROM content and XML/ESI ﬁle that is used to conﬁgure the MFC

IO block.

MFC IO conﬁguration data is automatically loaded at startup from EEPROM to the ESC Parameter RAM start-

ing at address 0x0580 of the the ESC register set. Therefore, this conﬁguration data has to be of Category 1

.

When a Category 1 block is present in the EEPROM at address 0080_h, the EEPROM conﬁguration is auto-

matically loaded at power up of the TMC8461. It is used for setting up the basic TMC8461 EtherCAT related

features.

The conﬁguration can later be changed via SPI access to the TMC8461 memory, the memory at address

0580_hcorresponds to the beginning of the category data at EEPROM address 0084_h.

It can also be used to set up the features of the MFCIO block available via the process data ram. Typically,

the EEPROM content is unique to a speciﬁc slave application and does not change. The required MFCIO

functional blocks and their parameters are conﬁgured into the slave controllers RAM for use along with

Sync Managers.

Note

The EEPROM content starting at address 0084_hto address 0103_h(128 bytes) will

be loaded into the EtherCAT slave controllers parameter memory at address

range 0580_hto 05FF_h.

If the category is shorter than 128 bytes, only the amount of data speciﬁed by

’Category data size’ is copied with the remaining bytes being reset to 0.

Address

in EEPROM

Address in

ESC RAM

Group

Function

0080_h

-

Category header (Lo)

01_h

00_h

0081_h

0082_h

-

Category header (Hi)

Category data size in words (Lo)

31_h(for the full MFCIO block conﬁg-

uration vector)

0083_h

0084_h

-

Category data size in words (Hi)

00_h

0580_h

Crossbar conﬁguration

MFCIO00 Conﬁguration (See Section

7.5)

0085_h

0086_h

0087_h

0088_h

0089_h

008A_h

008B_h

008C_h

008D_h

0581_h

0582_h

0583_h

0584_h

0585_h

0586_h

0587_h

0588_h

0589_h

Crossbar conﬁguration

MFCIO01 Conﬁguration

MFCIO02 Conﬁguration

MFCIO03 Conﬁguration

MFCIO04 Conﬁguration

MFCIO05 Conﬁguration

MFCIO06 Conﬁguration

MFCIO07 Conﬁguration

MFCIO08 Conﬁguration

MFCIO09 Conﬁguration

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008E_h

008F_h

0090_h

0091_h

0092_h

0093_h

0094_h

0095_h

0096_h

0097_h

0098_h

0099_h

009A_h

009B_h

009C_h

009D_h

009E_h

009F_h

00A0_h

058A_h

058B_h

058C_h

058D_h

058E_h

058F_h

0590_h

0591_h

0592_h

0593_h

0594_h

0595_h

0596_h

0597_h

0598_h

0599_h

059A_h

059B_h

059C_h

Crossbar conﬁguration

HVIO conﬁguration

MFCIO10 Conﬁguration

MFCIO11 Conﬁguration

MFCIO12 Conﬁguration

MFCIO13 Conﬁguration

MFCIO14 Conﬁguration

MFCIO15 Conﬁguration

MFC_HV0 Conﬁguration

MFC_HV1 Conﬁguration

MFC_HV2 Conﬁguration

MFC_HV3 Conﬁguration

MFC_HV4 Conﬁguration

MFC_HV5 Conﬁguration

MFC_HV6 Conﬁguration

MFC_HV7 Conﬁguration

Slow Slope (See section 7.6)

Weak High

HVIO conﬁguration

Weak Low

HVIO conﬁguration

Diﬀerential input

Switching Regulator conﬁguration 3.3V switching regulator (See sec-

tion 7.7)

00A1_h

00A2_h

059D_h

059E_h

Switching Regulator conﬁguration Adjustable switching regulator

Memory block conﬁguration

Memory block 0 start address Low

Byte (See section 7.8)

00A3_h

00A4_h

00A5_h

059F_h

05A0_h

05A1_h

Memory block 0 start address High

Byte

Memory block 1 start address Low

Byte

Memory block 1 start address High

Byte

00A6_h

00A7_h

00A8_h

00A9_h

00AA_h

00AB_h

05A2_h

05A3_h

05A4_h

05A5_h

05A6_h

05A7_h

MFC register conﬁguration

ENC_MODE (W)

ENC_STATUS (R)

X_ENC (W)

X_ENC (R)

ENC_CONST (W)

ENC_LATCH (R)

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00AC_h

00AD_h

00AE_h

00AF_h

00B0_h

00B1_h

00B2_h

00B3_h

00B4_h

00B5_h

00B6_h

00B7_h

00B8_h

00B9_h

00BA_h

00BB_h

00BC_h

00BD_h

00BE_h

00BF_h

00C0_h

00C1_h

00C2_h

00C3_h

00C4_h

00C5_h

00C6_h

00C7_h

00C8_h

00C9_h

00CA_h

00CB_h

00CC_h

05A8_h

05A9_h

05AA_h

05AB_h

05AC_h

05AD_h

05AE_h

05AF_h

05B0_h

05B1_h

05B2_h

05B3_h

05B4_h

05B5_h

05B6_h

05B7_h

05B8_h

05B9_h

05BA_h

05BB_h

05BC_h

05BD_h

05BE_h

05BF_h

05C0_h

05C1_h

05C2_h

05C3_h

05C4_h

05C5_h

05C6_h

05C7_h

05C8_h

MFC register conﬁguration

SPI_RX_DATA (R)

SPI_TX_DATA (W)

SPI_CONF (W)

SPI_STATUS (R)

SPI_LENGTH (W)

SPI_TIME (W)

I2C_TIMEBASE (W)

I2C_CONTROL (W)

I2C_STATUS (R)

I2C_ADDRESS (W)

I2C_DATA_R (R)

I2C_DATA_W (W)

SD_CH0_STEPRATE (W)

SD_CH1_STEPRATE (W)

SD_CH2_STEPRATE (W)

SD_CH0_STEPCOUNT (R)

SD_CH1_STEPCOUNT (R)

SD_CH2_STEPCOUNT (R)

SD_CH0_STEPTARGET (W)

SD_CH1_STEPTARGET (W)

SD_CH2_STEPTARGET (W)

SD_CH0_COMPARE (W)

SD_CH1_COMPARE (W)

SD_CH2_COMPARE (W)

SD_CH0_NEXTSR (W)

SD_CH1_NEXTSR (W)

SD_CH2_NEXTSR (W)

SD_STEPLENGTH (W)

SD_DELAY (W)

SD_CFG (W)

PWM_CFG (W)

PWM1 (W)

PWM2 (W)

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00CD_h

00CE_h

00CF_h

00D0_h

00D1_h

00D2_h

00D3_h

00D4_h

00D5_h

00D6_h

00D7_h

00D8_h

00D9_h

00DA_h

00DB_h

00DC_h

00DD_h

00DE_h

00DF_h

00E0_h

00E1_h

00E2_h

00E3_h

00E4_h

00E5_h

05C9_h

05CA_h

05CB_h

05CC_h

05CD_h

05CE_h

05CF_h

05D0_h

05D1_h

05D2_h

05D3_h

05D4_h

05D5_h

05D6_h

05D7_h

05D8_h

05D9_h

05DA_h

05DB_h

05DC_h

05DD_h

05DE_h

05DF_h

05E0_h

05E1_h

MFC register conﬁguration

Unused

PWM3 (W)

PWM4 (W)

PWM1_CNTRSHFT (W)

PWM2_CNTRSHFT (W)

PWM3_CNTRSHFT (W)

PWM4_CNTRSHFT (W)

PWM_PULSE_B_PULSE_A (W)

PWM_PULSE_LENGTH (W)

GPO (W)

GPI (R)

GPIO_CONFIG (W)

DAC_VAL (W)

MFCIO_IRQ_CFG (W)

MFCIO_IRQ_FLAGS (R)

WD_TIME (W)

WD_CFG (W)

WD_OUT_MASK_POL (W)

WD_OE_POL (W)

WD_IN_MASK_POL (W)

WD_MAX (R)

HV_ANA_STATUS (R)

Unused

MFC register conﬁguration

SYNC1_SYNC0_EVENT_CNT (R)

Table 189: EEPROM Parameter Map

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7.5 SII EEPROM MFC IO Crossbar Mapping

The TMC8461 contains a full crossbar.

The 24 MFC IO pins (16x Low Voltage 3.3V MFC IO pins and 8x High Voltage MFC IO pins) of the TMC8461

can be freely assigned to any signal coming from or going to the MFC IO functional blocks.

Without initialization from the SII EEPROM on power up or later via PDI SPI/ECAT memory access during

operation, all IOs are tri-stated.

Note

Certain output signals (e.g. PWM signals, DAC, ...) generate very short pulses

(down to 10ns) which are faster than the slew rate of the HVIO output drivers.

It is still possible to use this conﬁguration, so that the user can evaluate if the

application speciﬁc conditions allow to work directly with the HVIO outputs.

Otherwise external signal conditioning is required.

One output signal can be mapped to multiple IO pins, for example to combine the driver strength of

multiple pins. The conﬁguration also allows a mapping of multiple pins to one input signal, but usually

there is no reason for this conﬁguration. When multiple pins are mapped to the same input signal, a logical

OR operation is applied to all input pins.

Each IO pin has a dedicated conﬁguration byte in the SII EEPROM and in the ESC’s memory space within

the ESC Parameter RAM to select the functional MFC IO block signal connected to the physical IO pin:

• MFCIO00 to MFCIO15: SII EEPROM 0084_hto 0093_h/ ESC Parameter RAM from 0580_hto 058F_h

2

• MFC_HV0 to MFC_HV7 : SII EEPROM: 0094_hto 009B_h/ ESC Parameter RAM from 0590_hto 0597_h

An overview over all conﬁgurable MFC IO block signals is given in Table 190.

Name

Function block Description

Direction Value dec. Value

hex.

ZERO

LOW

HGH

TRI

A

none

Disabled

-

0

00_h

01_h

02_h

03_h

04_h

05_h

06_h

07_h

08_h

09_h

0A_h

0B_h

0C_h

0D_h

none

Static LOW output

Static HIGH output

Static tristate (Z) output

ABN_A signal

output

-

1

none

2

none

3

ABN decoder

SPI

input

4

An

ABN_An signal (for diﬀerential inputs)

ABN_B signal

5

B

6

Bn

ABN_Bn signal (for diﬀerential inputs) input

ABN_N signal input

ABN_Nn signal (for diﬀerential inputs) input

7

N

8

Nn

9

SCK

SDI

SDO

CS0

SPI SCK signal

SPI SDI signal

SPI SDO signal

SPI CS0 signal

output

input

10

11

12

13

SPI

output

SPI

2

MFC_HV0 to MFC_HV7 ≡ MFCIO16 to MFCIO23

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CS1

CS2

CS3

SCL

SPI

I²C

SPI CS1 signal

SPI CS2 signal

SPI CS3 signal

I²C SCL signal

I²C SDA signal

output

in/out

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

29

30

31

32

33

34

35

36

37

38

72

73

74

75

76

39

40

41

0E_h

0F_h

10_h

11_h

12_h

13_h

14_h

15_h

16_h

17_h

18_h

19_h

1A_h

1B_h

1C_h

1D_h

1E_h

1F_h

20_h

21_h

22_h

23_h

24_h

25_h

26_h

48_h

49_h

4A_h

4B_h

4C_h

27_h

28_h

29_h

SDA

S0

Step/Direction Step output channel 0

output

D0

Step/Direction Direction output channel 0

Step/Direction Step output channel 1

S1

D1

Step/Direction Direction output channel 1

Step/Direction Step output channel 2

S2

D2

Step/Direction Direction output channel 2

Step/Direction Inverted Step output channel 0

Step/Direction Inverted Direction output channel 0

Step/Direction Inverted Step output channel 1

Step/Direction Inverted Direction output channel 1

Step/Direction Inverted Step output channel 2

Step/Direction Inverted Direction output channel 2

S0n

D0n

S1n

D1n

S2n

D2n

HS0

LS0

PWM

Channel 0 Highside signal

Channel 0 Lowside signal

Channel 1 Highside signal

Channel 1 Lowside signal

Channel 2 Highside signal

Channel 2 Lowside signal

Channel 3 Highside signal

Channel 3 Lowside signal

PWM counter position A pulse

PWM counter center position pulse

PWM counter position B pulse

HS1

LS1

HS2

LS2

HS3

LS3

PULSE_A

PULSE_C

PULSE_B

PULSE_AB PWM

PWM counter position A and B pulses output

PULSE_Z

GPI0

PWM

GPIO

PWM counter Zero position pulse

General purpose input 0 signal

General purpose input 1 signal

General purpose input 2 signal

output

input

GPI1

GPI2

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GPI3

GPIO

DAC

General purpose input 3 signal

General purpose input 4 signal

General purpose input 5 signal

General purpose input 6 signal

General purpose input 7 signal

General purpose input 8 signal

General purpose input 9 signal

General purpose input 10 signal

General purpose input 11 signal

General purpose input 12 signal

General purpose input 13 signal

General purpose input 14 signal

General purpose input 15 signal

General purpose output 0 signal

General purpose output 1 signal

General purpose output 2 signal

General purpose output 3 signal

General purpose output 4 signal

General purpose output 5 signal

General purpose output 6 signal

General purpose output 7 signal

General purpose output 8 signal

General purpose output 9 signal

General purpose output 10 signal

General purpose output 11 signal

General purpose output 12 signal

General purpose output 13 signal

General purpose output 14 signal

General purpose output 15 signal

Pseudorandom 1-bit DAC signal

input

42

43

44

45

46

47

48

49

50

51

52

53

54

55

56

57

58

59

60

61

62

63

64

65

66

67

68

69

70

71

2A_h

2B_h

2C_h

2D_h

2E_h

2F_h

30_h

31_h

32_h

33_h

34_h

35_h

36_h

37_h

38_h

39_h

3A_h

3B_h

3C_h

3D_h

3E_h

3F_h

40_h

41_h

42_h

43_h

44_h

45_h

46_h

47_h

GPI4

input

GPI5

input

GPI6

input

GPI7

input

GPI8

input

GPI9

input

GPI10

GPI11

GPI12

GPI13

GPI14

GPI15

GPO0

GPO1

GPO2

GPO3

GPO4

GPO5

GPO6

GPO7

GPO8

GPO9

GPO10

GPO11

GPO12

GPO13

GPO14

GPO15

DAC0

input

output

Table 190: Crossbar conﬁguration values

The following Figure 30 shows the crossbar with an example conﬁguration. All input signals to the MFC IO

Incremental Encoder Block are connected via external pins. In this case the ﬁrst 6 low voltage MFC IOs are

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used as inputs. No other functional MFC IO block is used in this example. The curly braces behind each

MFC IO number contain the required conﬁguration value in decimal numbers according to Table 190.

Figure 30: MFC IO Crossbar Example Conﬁguration

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7.6 SII EEPROM MFC IO High Voltage IO (HVIO) Conﬁguration

The 8 HVIO pins have additional conﬁguration options which can be set on power up from the SII EEPROM

or later by SPI access to the memory.

The ﬁrst three conﬁguration bytes (Slope Slow, Weak High, Weak Low) each have one bit corresponding to

one HV output:

Bit

0

Output

MFC_HV0

MFC_HV1

MFC_HV2

MFC_HV3

MFC_HV4

MFC_HV5

MFC_HV6

MFC_HV7

1

2

3

4

5

6

7

Table 191: Slope Slow/Weak High/WeakLow conﬁg

Slope Slow - 0598_h(SII EEPROM: 009C_h)

With this option set to 1, the output slope of the HVIO pins can be slowed down.

Weak High - 0599_h(SII EEPROM: 009D_h)

With this option set to 1, the high level driver strength of the HVIO pins can be reduced.

Weak Low - 059A_h(SII EEPROM: 009E_h)

With this option set to 1, the low level driver strength of the HVIO pins can be reduced.

Diﬀerential Input Enable - 059B_h(SII EEPROM: 009F_h)

With this option set to 1, two of the HVIO inputs can be combined to a diﬀerential input pair. Only the

lower 4 bits are used to enable four speciﬁc pairs:

Bit

0

Positive input

MFC_HV3

Negative input

MFC_HV0

1

MFC_HV4

MFC_HV1

2

MFC_HV5

MFC_HV2

3

MFC_HV7

MFC_HV6

Table 192: Diﬀerential HV input conﬁguration

The crossbar settings of MFC_HV3, MFC_HV4, MFC_HV5 and MFC_HV7 are ignored when they are used as a

diﬀerential input.

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7.7 SII EEPROM MFC IO Switching Regulator Conﬁguration

3.3V switching regulator - 059C_h(SII EEPROM: 00A0_h)

Bit

Output

1:0

SAW_FREQ - Switching frequency (nominal values)

0 : 250kHz

1 : 125kHz

2 : 500kHz

3 : 1MHz

3:2

5:4

6

FB_AMPL - Voltage error feedback ampliﬁcation

0 : 100%

1 : 150%

2 : 200%

3 : 50%

FB_CAP - Dampening of voltage error feedback

0 : 100%

1 : 150%

2 : 200%

3 : 50%

SC_DISABLE - Disable cycle-to-cycle overcurrent protection

0 : Protection enabled

1 : No protection

Table 193: Conﬁguration bits for 3.3V switching regulator

Adjustable switching regulator - 059D_h(SII EEPROM: 00A1_h)

Bit

Output

1:0

SAW_FREQ - Switching frequency (nominal values)

0 : 250kHz

1 : 125kHz

2 : 500kHz

3 : 1MHz

3:2

5:4

6

FB_AMPL - Voltage error feedback ampliﬁcation

0 : 100%

1 : 150%

2 : 200%

3 : 50%

FB_CAP - Dampening of voltage error feedback

0 : 100%

1 : 150%

2 : 200%

3 : 50%

SC_DISABLE - Disable cycle-to-cycle overcurrent protection

0 : Protection enabled

1 : No protection

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Bit

Output

7

DISABLE - Disable Switching regulator

0 : Switching regulator enabled

1 : Switching regulator disabled

Table 194: Conﬁguration bits for adjustable switching regulator

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7.8 SII EEPROM MFC IO Memory Block Mapping

The MFC registers can be mapped to speciﬁc memory areas to allow EtherCAT access, so that the data is

directly copied between each register and the assigned memory location. This allows the operation with a

less powerful application processor or even without an application processor at all in Device Emulation

mode.

The registers are dynamically mapped to one of two memory blocks:

• Memory Block 0 is used for write-registers (data direction: EtherCAT master -> MFC register)

• Memory Block 1 is used for read-registers (data direction: MFC register -> EtherCAT master).

The start address of each memory block can be conﬁgured to be anywhere in the process data RAM (1000_h

to (4FFF_h-blocksize)).

The length of each block depends on the selected registers that are mapped into the block. Extra care

should be taken that the blocks do not overlap each other, that they do not overlap with other process

data in the DPRAM, and that the memory blocks’ start addresses are not too close at 4FFF_h.

Memory Block 0 base address 059F_h:059E_h(SII EEPROM: 00A3_h:00A2_h)

The start address of the block that all write registers of the MFC are mapped into.

Address 059F_hcontains the upper byte of the start address. Allowed values: 10_h...4F_h

Address 059E_hcontains the lower byte of the start address. Allowed values: 00_h...FF_h

Memory Block 1 base address 05A1_h:05A0_h(SII EEPROM: 00A5_h:00A4_h)

The start address of the block that all read registers of the MFC are mapped into.

Address 059F_hcontains the upper byte of the start address. Allowed values: 10_h...4F_h

Address 059E_hcontains the lower byte of the start address. Allowed values: 00_h...FF_h

When a register is mapped to the RAM for EtherCAT transfer, its memory address depends on the other

enabled registers with a lower register number.

The start address of any enabled register will be a multiple of 4 bytes from the start address of the memory

block. Between registers that are not a multiple of 4 bytes, a padding gap is left that is not transferred.

For example if a 2 byte register, a 8 byte register a 1 byte register and a 4 byte register are enabled in a

memory block starting at 2000_h, the memory is used as shown in this table:

Register

Reg. 1 (2 byte) 2001_h

Padding 2003_h

End Address Start Address

2000_h

2002_h

2004_h

200C_h

200D_h

2010_h

Reg. 2 (8 byte) 200B_h

Reg. 3 (1 byte) 200C_h

Padding

200F_h

Reg. 4 (4 byte) 2013_h

Table 195: Register mapping example

For the actual register sizes please refer to Table 124 in Section 7.2.

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7.9 SII EEPROM MFC IO Register Conﬁguration

All MFC registers are accessible via the MFC IO Control SPI Interface. Alternatively they can be mapped into

the ESC’s Process Data RAM to allow access via EtherCAT. In this case the mapped registers can only be

written by the EtherCAT master. But they can still be read via MFC IO Control SPI Interface.

The transfer of all enabled registers is performed in one access. To enable the data update at certain

times only, a shadow register is used for every MFC register. The exact point in time when the actual data

transfer occurs (from the shadow register into a write register or from a read register into the shadow

register) is based on the chosen trigger source.

There is one conﬁguration byte in the SII EEPROM (and ESC Parameter RAM respectively) for each MFC

block register. The conﬁguration for all registers has the same options:

Bit

3:0

4

Description

Trigger Source

Enable RAM transfer

0 : disabled, register access only from MCU via MFC CTRL SPI

1 : enabled, read and write access via EtherCAT, readable by MCU via MFC CTRL SPI

7:5

Unused

Table 196: Register conﬁguration byte

Trigger

Source hex.

Trigger Source Name

Description

0_h

1_h

2_h

3_h

4_h

5_h

6_h

7_h

8_h

9_h

A_h

B_h

C_h

D_h

E_h

F_h

Trigger always

shadow register is transparent

SYNC0 signal

distributed clocks sync pulse 0 (0->1)

distributed clocks sync pulse 1 (0->1)

distributed clocks latch input 0 (0->1)

distributed clocks latch input 1 (0->1)

Start of frame on EtherCAT bus

SYNC1 signal

LATCH0 signal

LATCH1 signal

EtherCAT start of frame (SOF)

EtherCAT end of frame (EOF)

PDI SPI nCS=0 (Chip Select)

PDI SPI nCS=1 (Chip Deselect)

MFC SPI nCS=0 (Chip Select)

MFC SPI nCS=1 (Chip Deselect)

End of frame on EtherCAT bus

Falling edge on PDI_SPI_CSN pin

Rising edge on PDI_SPI_CSN pin

Falling edge on MFC_CTRL_SPI_CSN pin

Rising edge on MFC_CTRL_SPI_CSN pin

Trigger before register is handled Before data is copied to/from RAM by Memory Bridge

Trigger after register was handled After data is copied to/from RAM by Memory Bridge

Trigger on PWM counter = 0

Trigger never

Transfer at the zero pulse of the MFC PWM unit

no data is transferred, can be used for debugging

shadow register is transparent

Trigger always

Table 197: Trigger source descriptions

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7.10 MFC IO ESI/XML Conﬁguration Block

This example shows the part of the ESI/XML conﬁguration ﬁle for EtherCAT slaves used to conﬁgure the

MCF IO block directly out of the EEPROM (at power-up or reset). Therefore, the conﬁguration block must

be classiﬁed as category 1 information within the EEPROM.

Another way to conﬁgure the MFC IO block is to directly write via PDI or ECAT interface to the EtherCAT

registers at 0x0580 to 0x05E1 (ESC Parameter RAM).

An easy way to generate the conﬁguration data string that is used in this XML structure is to use the wizard

included in the TMCL-IDE. See also section ESI Conﬁguration Wizard.

1

3

ConfigData >0000000000000000000... </ConfigData >

5

7

9

<!-- during EEPROM loading at startup.

-->

11

13

15

17

19

<Data >00000000000000000000000000000000000000000000000

00000000000000000000000000000000000000000000000

00000000

</Data >

</Category >

</Eeprom >

Figure 31: MFC IO ESI/XML Conﬁguration Block

Note

The zeros in the example above are just placeholders and must be adapted to

the respective conﬁguration.

See the available application notes and examples on www.trinamic.com for more

information.

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7.11 MFC IO Incremental Encoder Block

This function block provides input pins for incremental encoder signals (two quadrature signals and one

index signal) with diﬀerential option. It has a large range of resolution settings, allowing the use of many

diﬀerent encoders without requiring extra calculations.

Figure 32: MFC IO Incremental Encoder Unit

Encoder Block Conﬁguration Conﬁguration of the Incremental Encoder Block is done via the ENC_MODE

register. Polarities, index event handling, clear and latch options, and prescaler mode can be conﬁgured.

N Event Flag The LSB in the ENC_STATUS register shows that an N event has occurred since the last read

access to this register. The ﬂag is cleared on a read access.

Encoder Constant The encoder constant ENC_CONST is added to or subtracted from the encoder

counter on each polarity change of the quadrature signals AB of the incremental encoder. The encoder

constant ENC_CONST represents a signed ﬁxed point number (16.16) to facilitate the generic adaption

between motors and encoders. In decimal mode, the lower 16 bits represent a number between 0 and

9999. For stepper motors equipped with incremental encoders the ﬁxed number representation allows

very comfortable parametrization. Additionally, mechanical gearing can easily be taken into account.

Negating the sign of ENC_CONST allows inversion of the counting direction to match motor and encoder

direction.

The encoder constant can be conﬁgured in the ENC_CONST register.

Examples:

• Encoder factor of 1.0:

ENC_CONST = 0x0001.0x0000 = FACTOR.FRACTION

• Encoder factor of -1.0:

ENC_CONST = 0xFFFF.0x0000

This is the two’s complement of 0x00010000. It equals (2¹⁶-(FACTOR+1)).(2¹⁶-FRACTION)

• Decimal mode encoder factor 25.6:

ENC_CONST = 00025.6000 = 0x0019.0x1770 = FACTOR.DECIMALS

• Decimal mode encoder factor -25.6:

ENC_CONST = 0xFFE6.4000 = 0xFFE6.0x0FAO.

This equals (2¹⁶-(FACTOR+1)).(10000-DECIMALS)

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Encoder Position The encoder counter ENC_X holds the current encoder position ready for read out.

Diﬀerent modes concerning handling of the signals A, B, and N take into account active low and active high

signals as found with diﬀerent types of encoders.

The current encoder position can be read from MFC IO register 3.

The encoder position can also be overwritten and set to a speciﬁc value. The current encoder position can

be written to MFC IO register 2.

Latched Encoder Position When either clr_cont or clr_once are set in the ENC_MODE register, the

current encoder position from ENC_X is latched into MFC IO register 5 on an active N event.

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7.12 MFC IO SPI Master Block

The SPI Master Unit provides an interface for up to four SPI slaves with a theoretically unlimited datagram

length using multiple accesses.

Figure 33: Block structure of SPI Master Unit

The basic conﬁguration requires setting the SPI frequency/bit length, the datagram length and the SPI

mode (clock polarity and phase). Extended settings are a special start-of-transmission trigger linked to the

PWM unit, the bit order, selection of one of the four SPI slaves and datagram length extension.

SPI_RX_DATA – Received Data This register contains the received datagram after an SPI transfer.

For SPI transfers with less than 64 bit, the upper bits of this register are unused.

SPI_TX_DATA – Data to transmit The data to be sent is written to this register. Unless conﬁgured diﬀer-

ently in SPI_CONF Bits 10..8, writing to this register starts the SPI transfer.

For SPI transfers with less than 64 bit, the upper bits of this register are unused.

SPI_CONF – SPI block conﬁguration

• Bit 15 is the trigger bit that can be selected as transmission start trigger (see below).

•

Bits 10..8 allow a conﬁguration when the data transmission should start, they are interpreted as a 3

bit number:

–

In the reset conﬁguration 0, the transmission always starts when data is written to the SPI_TX

register.

–

The settings 1 to 5 link the start of the transmission to the PWM unit, allowing synchronization

between the PWM cycle and for example a SPI ADC for current measurement. The trigger

sources are the ﬁve PWM_PULSE signals that are also available on the MFCIO crossbar. Please

refer to Section 7.15 for details about these pulses.

–

Setting 7 is a single shot trigger that starts only one transmission when Bit 15 of SPI_CONF is

written to 1.

•

Bit 6 and 5 deﬁne the clock polarity and phase of the SPI signals which deﬁne what the idle state of

the SCK signal is and when output data is changed and when input data is sampled.

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Clock polarity Clock phase SPI mode MOSI change

MISO sample

0

1

0

1

0

1

0

1

2

3

SCK falling edge SCK rising edge

SCK rising edge

SCK falling edge

SCK falling edge SCK rising edge

Table 198: SPI mode conﬁguration

•

Bit 4 reverses the bit order in the transmission, the least signiﬁcant bit of SPI_TX_DATA (Bit 0) is

transmitted ﬁrst, the least signiﬁcant bit of SPI_RX_DATA is the ﬁrst received bit, the most signiﬁcant

bit of SPI_TX_DATA is transmitted last and the most signiﬁcant bit of SPI_RX_DATA is the last bit

received.

Bit 3 can be used for datagrams longer than 64 bit. With this bit set, the chip select line is held

low after the transmission, allowing more transmissions in the same datagram. Before the last

transmission, this bit must be set to 0 again so that the chip select line goes high afterwards, ending

the datagram.

• Bits 1 and 0 deﬁne which chip select line (which slave) is used for the next transmission.

SPI_STATUS – SPI transfer status Bit 0 of this register is the Ready indicator for the SPI master unit.

When this bit is set, a new transfer can be started. When this bit is 0 and the start of a new transfer

is triggered, the trigger is ignored, the currently active transfer is ﬁnished but the new transfer is not started.

SPI_LENGTH – SPI datagram length This register deﬁnes the SPI datagram length in bits. Any length from

1 to 64 bits is possible.

SPI datagram length (bits) = SPI_LENGTH+1

SPI_TIME – SPI bit duration This register deﬁnes the bit length and thus the SPI clock frequency.

The duration of one SPI clock cycle can be calculated as t_SCK= (4+(2*SPI_TIME))/25MHz = (4+(2*SPI_TIME))*40ns,

the SPI clock frequency is f_SCK= 25MHz/(4+(2*SPI_TIME)).

The delay between the falling edge of CSN (becoming active) and the ﬁrst SCK edge and the last SCK edge

and the rising edge of CSN is always a half SCK clock cycle (t_SCK/2).

7.12.1 SPI Examples

TMC262 on SPI channel 0

This example shows the conﬁguration of the SPI master unit for a TMC262 as SPI slave 0 and the transfer

of data to the TMC262’s DRVCONF register.

1. Use 3.125 MHz SPI clock (25MHz/(4+(2*2))) = (25MHz/8)

SPI_TIME <= 0x02

2. Use 20 bit datagrams

SPI_LENGTH <= 0x13

3. Start on TX write, SPI-Mode 3, MSB ﬁrst, single datagrams, Slave 0)

SPI_CONF <= 0x0060

4. Wait until SPI-Master is ready

while (SPI_STATUS & 0x01 != 0x01)

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5. Write Data into TX register (e.g. TMC262 DRVCONF register, all 64bit are shown)

SPI_TX_DATA <= 0x00000000000EF010

6. Wait until SPI-Master is ready

while (SPI_STATUS & 0x01 != 0x01)

7. Read Data from RX register

rxdatagram = SPI_RX_DATA

Chain of 10 74xx595 shift registers used as 80 digital outputs (good example)

This example shows the transmission of a longer datagram, in this case 80 bits that are shifted into a chain

of 74xx595 shift registers. The NCS of the SPI interface can be used as the storage clock of the 74xx595

to transfer the contents of the shift register into the storage register. The data that should be sent is

0x5555AAAA5555AAAA55AA.

It is recommended to split the data into two chunks of 40 bits each: 0x5555AAAA55 and 0x55AAAA55AA.

Conﬁguration and ﬁrst transmission

1. Use 6.25 MHz SPI clock (25MHz/(4+(2*0))) = (25MHz/4)

SPI_TIME <= 0x00

2. Use a 40 bit datagram

SPI_LENGTH <= 0x28

3. Start on TX write, SPI-Mode 3, MSB ﬁrst, Keep CS low, Slave 0)

SPI_CONF <= 0x0068

4. Wait until SPI-Master is ready

while (SPI_STATUS & 0x01 != 0x01)

5. Write Data for the ﬁrst 64 outputs into TX register

SPI_TX_DATA <= 0x5555AAAA55

6. Wait until SPI-Master is ready

while (SPI_STATUS & 0x01 != 0x01)

7. Start on TX write, SPI-Mode 3, MSB ﬁrst, Drive CS high at the end, Slave 0)

SPI_CONF <= 0x0060

8. Write Data for the last 16 outputs into TX register

SPI_TX_DATA <= 0x55AAAA55AA

9. Wait until SPI-Master is ready

while (SPI_STATUS & 0x01 != 0x01)

Next transmission with inverted data

1. Start on TX write, SPI-Mode 3, MSB ﬁrst, Keep CS low, Slave 0)

SPI_CONF <= 0x0068

2. Wait until SPI-Master is ready

while (SPI_STATUS & 0x01 != 0x01)

3. Write Data for the ﬁrst 40 outputs into TX register

SPI_TX_DATA <= 0xAAAA5555AA

4. Wait until SPI-Master is ready

while (SPI_STATUS & 0x01 != 0x01)

5. Start on TX write, SPI-Mode 3, MSB ﬁrst, Drive CS high at the end, Slave 0)

SPI_CONF <= 0x0060

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6. Write Data for the last 40 outputs into TX register

SPI_TX_DATA <= 0xAA5555AA55

7. Wait until SPI-Master is ready

while (SPI_STATUS & 0x01 != 0x01)

Chain of 10 74xx595 shift registers used as 80 digital outputs (bad example)

This bad example is the same as the previous one but with the non-recommended datagram split of 64

bits + 16 bit. This requires more communication since not only the SPI_CONF register needs to be changed

between the SPI_TX_DATA writes but also the SPI_LENGTH register changes every time.

Conﬁguration and ﬁrst transmission

1. Use 6.25 MHz SPI clock (25MHz/(4+(2*0))) = (25MHz/4)

SPI_TIME <= 0x00

2. Use a 64 bit datagram

SPI_LENGTH <= 0x3F

3. Start on TX write, SPI-Mode 3, MSB ﬁrst, Keep CS low, Slave 0)

SPI_CONF <= 0x0068

4. Wait until SPI-Master is ready

while (SPI_STATUS & 0x01 != 0x01)

5. Write Data for the ﬁrst 64 outputs into TX register

SPI_TX_DATA <= 0x5555AAAA5555AAAA

6. Wait until SPI-Master is ready

while (SPI_STATUS & 0x01 != 0x01)

7. Use a 16 bit datagram (remaining outputs)

SPI_LENGTH <= 0x0F

8. Start on TX write, SPI-Mode 3, MSB ﬁrst, Drive CS high at the end, Slave 0)

SPI_CONF <= 0x0060

9. Write Data for the last 16 outputs into TX register

SPI_TX_DATA <= 0x55AA

10. Wait until SPI-Master is ready

while (SPI_STATUS & 0x01 != 0x01)

Next transmission with inverted data

1. Use a 64 bit datagram

SPI_LENGTH <= 0x3F

2. Start on TX write, SPI-Mode 3, MSB ﬁrst, Keep CS low, Slave 0)

SPI_CONF <= 0x0068

3. Wait until SPI-Master is ready

while (SPI_STATUS & 0x01 != 0x01)

4. Write Data for the ﬁrst 64 outputs into TX register

SPI_TX_DATA <= 0xAAAA5555AAAA5555

5. Wait until SPI-Master is ready

while (SPI_STATUS & 0x01 != 0x01)

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6. Use a 16 bit datagram (remaining outputs)

SPI_LENGTH <= 0x0F

7. Start on TX write, SPI-Mode 3, MSB ﬁrst, Drive CS high at the end, Slave 0)

SPI_CONF <= 0x0060

8. Write Data for the last 16 outputs into TX register

SPI_TX_DATA <= 0xAA55

9. Wait until SPI-Master is ready

while (SPI_STATUS & 0x01 != 0x01)

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7.13 MFC IO I2C Master Block

The TMC8461 I2C master allows accessing I2C slaves by writing and reading control and data registers

instead of needing to take care of timing or even bit-banging through the GPIO block.

Figure 34: Block structure of SPI Master Unit

I2C_TIMEBASE – Bit duration in µs

This register determines the I2C clock frequency by setting the duration of a single bit. A setting of 0

disables communication, a setting of 1 results in bit duration of 1

in a bit duration of 255 µs.

µs, the maximum setting of 255 results

I2C_CONTROL – Command register

There are 6 commands that allow full control of the I2C master block. Each command is represented by a

single bit in this register.

Command byte Bit in register Command

0x20

0x10

0x08

0x04

0x02

0x01

5

4

3

2

1

0

Send Start Condition (also Repeated Start)

Send Stop Condition

Send Address (Content of Address register), incl. R/nW Bit

Send Data (Content of Data register)

receive Data and send ACK

receive Data and send NACK

Table 199: I2C control commands

I2C_STATUS – Status register

The status bits show the current transmission status either alone or in a combination of multiple bits.

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Status bit Description

7

6

5

4

3

2

1

0

Error Flag

Not Acknowledge received/sent

Acknowledge received/sent

Write to slave mode

Read from Slave mode

Transmit Address mode

Repeated Start condition sent

Start condition sent

Table 200: I2C status register bits

Bits 0 and 1 are set after command 0x20 was successfully executed, either if the I2C bus was idle or a start

condition already has been sent.

A combination of Bits 2 to 6 indicates completion of an address or data cycle.

Bit 7 indicates an error during transmission. A stop condition should be sent to return to the idle state.

Status byte Status

0x00

0x01

0x02

0x34

0x2C

0x54

0x4C

0xE4

0x48

0x28

0x30

0x50

0xF0

0xFF

Idle

Start sent

Repeated Start sent

Write Address ACK

Read Address ACK

Write Address NACK

Read Address NACK

Address Error

Read Data ACK sent

Read Data NACK sent

Write Data ACK

Write Data NACK

Write Data Error

General Error

Table 201: I2C status overview

I2C_ADDR – Address register with R/nW bit

This register contains the 7 bit address of the I2C slave and the single R(ead)/n(ot)W(rite) bit.

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Bit

7

6

5

4

3

2

1

0

Function A6 A5 A4 A3 A2 A1 A0 R/nW

Table 202: I2C Addres register

I2C_DATA_R – Data register for received data

After a read command, this register contains the last read data byte.

I2C_DATA_W – Data register for data to transmit

The data byte that should be sent with the next write command is written to this register.

Basic usage An usual communication cycle is done by the following steps

1. Set the bit duration in µs in the I2C_TIMEBASE register (only required as conﬁguration after reset or if

a diﬀerent speed is required).

2. Write 0x20 (Send Start Condition) to the I2C_CONTROL register.

3. Write the slave address and the R/nW bit to the I2C_ADDR register.

4. Write 0x80 (Send Address) to the I2C_CONTROL register.

5. Depending on the R/nW bit, either

•

Write 0x01 (Receive Data and send NACK) or 0x02 (Receive Data and send ACK) to I2C_CONTROL

to receive data and send NACK or ACK.

• Read the data from the I2C_DATA_R register.

or

• Write data to the I2C_DATA_W register.

• Write 0x04 (Send Data)to I2C_CONTROL to send the data.

This can be repeated as long as it is necessary.

6. Write 0x10 (Send Stop Condition) to the I2C_CONTROL register.

A repeated start condition, as it is required for slaves like EEPROMs, can be sent like the regular start

condition by writing 0x20 to the I2C_CONTROL register at any required time.

7.13.1 I2C Example

This Example shows reading from an 24LC64 I2C EEPROM. The standard I2C address is conﬁgurable from

0x50 to 0x57 with 3 address pins. The address 0x50 is used for this example. The memory uses 13 bit

addresses, so two memory address bytes are used. The memory address 0x1234 is used for this example.

1. Set I2C clock to 100kHz (10µs)

I2C_TIMEBASE <= 0x0A

2. Send Start Condition

I2C_CONTROL <= 0x20

3. Write the slave address and the nW bit ((0x50 « 1) + 0 = 0xA0)

I2C_ADDR <= 0xA0

4. Send Address

I2C_CONTROL <= 0x80

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5. Write upper byte of the memory address

I2C_DATA_W <= 0x12

6. Send Data

I2C_CONTROL <= 0x04

7. Write lower byte of the memory address

I2C_DATA_W <= 0x34

8. Send Data

I2C_CONTROL <= 0x04

9. Send Repeated-Start Condition

I2C_CONTROL <= 0x20

10. Write the slave address and the R bit ((0x50 « 1) + 1 = 0xA1)

I2C_ADDR <= 0xA1

11. Command: Receive Data and send ACK

I2C_CONTROL <= 0x02

12. Read the data

databyte <= I2C_DATA_R

The last two steps can be repeated as long as it is necessary, for the last byte send a NACK instead:

13. Command: Receive Data and send NACK

I2C_CONTROL <= 0x01

14. Read the data

databyte <= I2C_DATA_R

15. Write 0x10 (Send Stop Condition) to the I2C_CONTROL register.

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7.14 MFC IO Step and Direction Block

The MFC IO step & direction block allows for generation of deﬁned step pulse frequencies along with a

direction signal.

This is done by writing an accumulation constants to a register. Toggle of the MSB of the accumulation

register value generates an internal step pulse of one internal clock cycle.

The direction signal is the MSB of the accumulation constant. Therefore, the sign of the accumulation

constant deﬁnes the direction signal polarity. The step-to-direction timer (STP2DIR) takes care of possible

external signal delay paths by programmable delay of the ﬁrst step after write of accumulation constant.

The pulse stretcher forms step and direction pulses of programmable length for adaption to external

signal paths.

The step direction unit can either run in free running mode just generating step pulses with programmed

frequency. Alternatively, is can generate a deﬁned number of step pulses with programmed frequency. An

interrupt output signal IRQ TARGET_REACHED indicates the reached target count of step pulses.

TMC8461 has three independent step and direction channels.

Figure 35: Block structure of the MFC IO Step and Direction Block

Step & Direction Signal Timing Write to the accumulation constant register starts step pulse generation.

The ﬁrst step pulse occurs after a time t_{ST EP 1st}. Following step pulses come after each t_{ST EP}. The pulse

length of the step pulses is t_{ST EP _P ULSE}. On change of direction by writing the accumulation constant

with a constant of diﬀerent sign, the ﬁrst step pulse after write occurs after t_{ST P 2DIR}

.

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Figure 36: Step & Direction Signal Timing

Parameter

Value

Description / Function

Comment

f_CLK[Hz]

25 MHz

clock frequency of step direction unit

clock frequency of the step

direction unit

t_CLK[s]

40 ns

clock period length

t_CLK= 1/f_CLK

f_{ST EP}[Hz]

f_{ST EP}

=

step

frequency,

pro-

(f_CLK/2³²) ∗ (SD_CHx_STEPRATE)

grammed via step rate

accumulation

SD_CHx_STEPRATE

constant

Max. f_{ST EP}12.5 MHz

[Hz]

Theoretical maximum value

for f_{ST EP}. Usable step fre-

quency depends on step

pulse length conﬁguration.

t_{ST EP}[s]

t_{ST EP}= 1/f_{ST EP}

t_{ST EP _P ULSE}

(SD_STEP_LENGTH + 1)/f_CLK

time between steps

t_{ST EP _P ULSE}

[s]

=

step pulse length must be

lower than time between

step pulses!

t_{ST EP _P ULSE}< t_{ST EP}

DIR

DIR = 0 –> positive direction,

DIR = 1 –> negative direction,

direction signal, depending

of step rate (SR) parameter,

direction is depending on sign of step rate DIR = 0 if SR > 0 or SR = 0,

register SD_CHx_STEPRATE where the step DIR = 1 if SR < 0

rate register is 2th complement

t_{ST EP 1st}[s]

time to 1st step pulse since WR=0 with

Time between write until

the ﬁrst step pulse occurs

t_{ST EP 1st}

=

2³²/SD_CHx_STEPRATE ∗ t_CLK

+(SD_DELAY + 1) ∗ t_CLK+ (2 ∗ t_CLK

)

t_{ST EP 1stW R}

[s]

time to ﬁrst step pulse since WR=0 step delay Internal processing adds an

plus 1 internal clock plus 2 clock cycles to delay

pulse length

Table 203: Step and direction unit parameters

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Step Rate Accumulation Constant The step direction accumulation constant determines the time

t_{ST EP}between two successive step pulses – this is actually the step rate. Each internal PWM clock

accumulates an accumulator according to

a

=

a

+

c

with the accumulator constant

c

. Toggle of the MSB

of the accumulator register a triggers a step pulse. With this principle, the step frequency is smarter

adjustable compared to a simple frequency divider. Writing = 0 clears the accumulator and stops the

c

step pulse generation. The step pulse frequency calculates as f_{ST EP}= (f_CLK/2³²) ∗ c.

Step Counter The step counter counts the number of steps, taking the direction into account. This is

a read only register. For initialization to zero a conﬁguration bit within the step direction conﬁguration

register hast to be written.

Step Target The step target deﬁnes the number of steps to be made for the step mode until stop.

This register can be overwritten at any time. When the number of steps has been made, the unit stops

outputting S/D pulses. When read, it gives the remaining numbers that must still be made.

Step Compare This register holds a compare value in numbers of step pulses. In target mode, the

number of steps to be made is conﬁgured in this register. Depending on the motor’s pole count and the

microstep resolution, the numbers of steps represent a certain distance.

Next Step Rate The next step rate register contains a value of the same format as the step rate register.

This value is automatically written into the step rate register after a successful compare of the step compare

value and the actual step counter. This way, simple motion proﬁles can be realized.

Step Length The duration of the step pulse – the step length – signal is programmable for adaption to

external power stages.

Note

Maximum step length: The step pulse length t_{ST EP _P ULSE}must be lower than

the time t_{ST EP}between step pulses to actually see step pulses at the outputs.

The condition t_{ST EP _P ULSE}< t_{ST EP}must be ensured by the application.

Step-to-Direction Delay The delay between the ﬁrst step pulse after a change of the direction is pro-

grammable for adaption to external power stages to take external delay paths into account.

Step Direction Unit Conﬁguration The step direction conﬁguration deﬁnes the mode of operation

(continuous or ﬁnite number of step pulses), polarity of step pulse signal and direction signal. One bit is

for zeroing of step pulse counter. On bit is for enabling and disabling of the step pulse unit and compare

mode.

Interrupt Output Signal An IRQ signal TARGET_REACHED of a single clock pulse length indicates that a

certain target position has been reached reached in terms of step counts.

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7.15 MFC IO PWM Block

The MFC IO block of TMC8461 oﬀers a 4-channel pulse width modulation (PWM) block including a pro-

grammable brake before make (BBM) unit and selection of diﬀerent PWM modes.

Both high side and low side control signals are available as separate outputs. A single PWM counter gener-

ates the four synchronous PWM signals. The conﬁgurable maximum count deﬁnes the PWM frequency.

Left aligned PWM, centered PWM, and right aligned PWM is selectable. The BBM timing is individually

programmable for high side and low side. Fixed pulses are available for triggering of ADCs or triggering

interrupts of a CPU. Additional programmable trigger output signals are available. Signal PULSE_ZERO

indicates a start of a new PWM cycle and PULSE_CENTER the center of a PWM cycle. Both are ﬁxed.

The two programmable signals PULSE_A and PULSE_B are for advanced ADC triggering. The signal

PULSE_AB is the logical or of PULSE_A and PULSE_B.

The polarities of the high side, low side, and trigger signals of the PWM unit are programmable.

Figure 37: Block structure of the MFC IO PWM Block

Parameter

f_CLK[Hz]

t_CLK[s]

Value

Description / Function

clock frequency of PWM unit

clock period length

Comment

100 MHz

10 ns

f_CLK= 1/t_CLK

t_CLK= 1/f_CLK

max. t_{P W M}[s]

40.96 us

Length of PWM period

Maximum t_{P W M}with maxi-

mum PWM resolution of 12

bit.

tPWM

=

t_CLK

∗

(1+PWM_MAXCNT

)

min.

[Hz]

f_{P W M}24.414 kHz PWM frequency = 1/t_{P W M}

Minimal PWM frequency

with maximum PWM resolu-

tion of 12 bit.

t_{P ULSE_LENGT H}

Length of trigger pulses with pulse length is adjustable

t_{P ULSE_LENGT H}

PULSE_LENGTH ∗ t_CLK= 10ns

t_CLK

=

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t_BBM

Brake Before Make time t_BBMwith

Individually programmable

for high side and low side

due to diﬀerent timing

tBBM_H = BBM_H ∗ t_CLK

tBBM_L = BBM_L ∗ t_CLK

requirements,

especially

when using PMOS @ High

Side and NMOS @ Low Side

Table 204: PWM unit parameters

PWM_MAXCNT Conﬁguration This conﬁguration can be found in the PWM_CFG register. It deﬁnes the

number of counts per PWM cycle for three PWM units. This determines the length t_{P W M}of each PWM

cycle respectively the PWM frequency f_{P W M}. It is programmable for adjustment of the PWM frequency

f_{P W M}

.

PWM_CHOPMODE Conﬁguration This conﬁguration can be found in the PWM_CFG register. It selects

the chopper mode of the 4 PWM channels. Each channel can be conﬁgured individually. The following

table gives the available chopper modes.

Selection Chopper High Side Low Side Function

000

001

010

011

100

101

110

111

no

oﬀ

no chopper, all oﬀ

no

oﬀ

on

no chopper, LS permanent on

no chopper, HS permanent on

no chopper, all oﬀ, not used

chopper LS, HS oﬀ

no

oﬀ

no

oﬀ

no

oﬀ

yes

Yes

oﬀ

PWM

Oﬀ

PWM

chopper HS, LS oﬀ

not PWM chopper HS and LS complementary, brake-before-make

is handled by programmable BBM unit

Table 205: PWM modes

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Figure 38: PWM chopper modes

PWM Alignment Conﬁguration This conﬁguration can be found in the PWM_CFG register. It determines

the alignment of the 4 PWM units. The alignment can be programmed left aligned, centered, or right

aligned. All 4 channels use the same conﬁguration.

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Figure 39: PWM Timing (centered PWM)

Figure 40: PWM Timing (left aligned PWM)

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Figure 41: PWM Timing (right aligned PWM)

PWM Polarity Conﬁguration This conﬁguration can be found in the PWM_CFG register.

The PWM signals of the 4 channels are of positive logic. Logical one level means ON and logical zero

level means OFF. Depending on the MOSFET drivers, switching on a MOSFET might require an inverted

logical level. The polarity conﬁguration determines the switching polarities for the high side MOSFETs and

switching polarities for the low side MOSFETs.

BBM Conﬁguration This conﬁguration can be found in the PWM_CFG register.

To avoid cross conduction of the half bridges the brake before make (BBM) timing is programmable. In

most cases the same BBM time is suﬃcient for both low side and high side. The BBM time should be

programmed as short as possible and as long as necessary. A too long BBM time causes conduction of the

bulk diodes of the power MOSFETs and that causes higher power dissipation. In case of using PMOSFETs

for high and NMOSFETs for low side with asymmetric switching characteristics, it might be advantageous

to program diﬀerent BBM_H and BBM_L times.

The BBM_L is the time from switch oﬀ the high side to switch on the low side in terms of clock cycles. The

BBM_L is common for all 4 high side power MOSFETs.

The BBM_H is the time from switch oﬀ the low side to switch on the high side in terms of clock cycles. The

BBM_H is common for all 4 low side power MOSFETs.

Figure 42: PWM BBM Timing

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PWM Value Together with the programmed PWM counter length, the PWM values determine the PWM

duty cycle. The PWM duty cycle is individually programmable for each of the 4 PWM channels.

Trigger Pulses A and B Conﬁguration The positions of the trigger pulses A and B are programmable

within the PWM cycle. These pulses can be used for diﬀerent purpose, e.g., to trigger ADC sampling at a

speciﬁc point in time.

Trigger Pulse Length Conﬁguration The length of PULSE_A and PULSE_B and the ﬁxed trigger pulses

PULSE_CENTER and PULSE_ZERO is programmable in terms of clock cycles.

Asymmetric PWM Conﬁguration To realize a wider time window between PWM switching events that

are close to each other, an asymmetric PWM shift can be programmed individually for each PWM channel.

This leaves the PWM duty cycles unchanged. It is useful for current measurement with sense resistors at

the bottom of the MOSFET half bridges.

Figure 43: Centered PWM with PWM channel 2 shifted from center (example showing only 3 PWM channels)

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7.16 MFC IO DAC Block

The DAC block generates a digital signal based on a 16 bit pseudo random number generator (PRNG). A

pseudo random number (PRN) is compared to the desired output value and a the output is set to 1 if the

PRN is lower than the output value. The PRN generator is clocked with 100MHz, which results in a period

length of 655.36µs. The output signal can be ﬁltered with a simple RC lowpass.

10kΩ

MFCIO[x]

out

100nF

Figure 44: RC ﬁlter for DAC output with example values

Note

The high voltage outputs are not able to output this signal properly as their

slew rate does not allow 10ns pulses. This will lead to voltage levels that don’t

correspond with the set value. It is recommended to use the DAC block only with

the low voltage outputs.

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7.17 MFC IO General Purpose IO Block

TMC8461 has 16 general purpose IO lines that can be freely conﬁgured and used via the 24 MFC IO low

voltage and high voltage pins. The general purpose IO signals can be used for indicator LEDs, switch inputs,

and even for relays or small DC motors on the HVIO pins.

When conﬁgured as an output signal, a safe state for each signal is available that is set on the pin in case

the emergency state is triggered using MFC_NES.

Figure 45: Block structure of GPIO Unit

After reset, all signals are conﬁgured as an input and present a Hi-Z state on the GPIO pin they are mapped

to. When a signal should be used as an input signal, no further conﬁguration is required after reset, the

signal state can be read directly from the GPI register (7.3.6.2).

To conﬁgure a signal as an output, a 1 bit must be written to the signal position in the GPIO_CONFIG

register (7.3.6.3). Afterwards, the signal can be controlled via the lower 16 bits of the GPO register (7.3.6.1).

The upper 16 bits of the GPO register represent the state in case the emergency state is triggered.

GPO (31..16) GPO (15..0) GPIO_CONFIG MFC_NES GPO signal Comment

X

0

1

X

0

1

X

0

1

X

1

0

Hi-Z

0

Reset state

Normal operation

1

Normal operation

0

Emergency State safe output

1

Table 206: GPO signal output states

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7.18 MFC IO IRQ Block

The MFC_IRQ output signal is driven by the MFC IO IRQ block and can be used to indicate various events of

the MFC IO block. The IRQ unit uses two registers to conﬁgure certain IRQ trigger events and to check the

IRQ source when the MFC_IRQ has been triggered.

Figure 46: Block structure of the MFC IO IRQ Block

IRQ MASK Register The IRQ mask register allows to enable/disable certain IRQ trigger events of the

MFCIO block.

IRQ FLAGS Register This register can be read out after the IRQ was set to identify the IRQ source

(especially when more than one IRQ source was masked). Reading out clears this register.

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7.19 MFC IO Watchdog Block

General Function The watchdog timer allows monitoring of external signals, or monitoring of EtherCAT

activity. A certain condition can be chosen for retriggering the watchdog, i.e. a certain input signal

constellation. In case this constellation does not occur at least once within a pre-programmable time

period, the watchdog timer will expire and will trigger a certain watchdog action.

To avoid static reset of the watchdog, the watchdog input condition is edge sensitive, i.e. it becomes reset

when the condition goes active respectively goes inactive. Once the watchdog expires, the watchdog safety

circuitry becomes active. This action can bring I/O lines into a certain state, in order to allow the system to

return to a known, safe condition. Therefore, all I/O lines are directly mapped to the GPIO ports of the

chip, so that they perform independently of the actually conﬁgured peripheral conﬁguration.

The watchdog action can be chosen to remain active continuously, until it becomes reset by a watchdog

re-conﬁguration, or it can be programmed to return to normal operation state, once the selected condition

becomes true again.

In an optional use case, the watchdog timer can be used to measure the maximum delay in between of

the occurrence of certain input conditions, in between of SPI frames, etc.

The watchdog unit ﬁnds itself between the MFC IO crossbar and the IO pads as shown in Figure 47. Thus,

the watchdog monitors the 24 MFCIOxx signals. Depending on the crossbar mapping these signals are

either inputs or outputs. Their logical function depends on the crossbar mapping to/from the MFC IO

functional sub-blocks.

Figure 47: Logical position of the MFC IO watchdog unit between crossbar and MFCIOxx pins

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Watchdog Register Set Once initialized, the watchdog timer monitors the application for activity and

allows setting of pre-programmed I/O patterns, in case the time limit is expired without activity.

In order to allow tuning of this time limit, the maximum time between two trigger events becomes

measured. This function also allows delay time measurement for input channels (i.e. when no watchdog

action is chosen). The watchdog timeout counter starts from zero up to WD_TIME. When it reaches

WD_TIME, it triggers the watchdog action.

The selected watchdog event resets the timeout counter. As trigger sources, the internal EtherCAT start

of frame (PDI_SOF), the two SPI chip select signals (PDI_SPI_CSN and MFC_CTRL_SPI_CSN) as well as any

combination of I/O lines can be used. For the I/O lines (MFCIO00 to MFCIO23), the polarity and edge are

programmable.

When using an MFCIOxx pin programmed as output and as watchdog trigger, the watchdog circuitry will

monitor the real output by checking the polarity of the output signal. This way, also a short circuit condition

will be detected. The chip select signals respond to a rising edge (i.e. when the SPI interface loads the SPI

shift register data into the corresponding registers).

Figure 48: Structure of the MFC IO watchdog unit

Watchdog Output Port Conﬁguration The following table contains the assignments of ports/signals

to the conﬁguration bits in the WD_OUT_MASK_POL register. An MFCIOxx pin programmed as output is

called MFCOxx.

Bit #

Signal

Bit #

32

Signal

0

1

2

3

4

5

6

7

8

MFCO00 polarity

MFCO01 polarity

MFCO02 polarity

MFCO03 polarity

MFCO04 polarity

MFCO05 polarity

MFCO06 polarity

MFCO07 polarity

MFCO08 polarity

MFCO00 mask

MFCO01 mask

MFCO02 mask

MFCO03 mask

MFCO04 mask

MFCO05 mask

MFCO06 mask

MFCO07 mask

MFCO08 mask

33

34

35

36

37

38

39

40

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Bit #

9

Signal

Bit #

41

42

43

44

45

46

47

48

49

50

51

52

53

54

55

56

57

58

59

60

61

62

63

Signal

MFCO09 polarity

MFCO10 polarity

MFCO11 polarity

MFCO12 polarity

MFCO13 polarity

MFCO14 polarity

MFCO15 polarity

MFCO16 polarity

MFCO17 polarity

MFCO18 polarity

MFCO19 polarity

MFCO20 polarity

MFCO21 polarity

MFCO22 polarity

MFCO23 polarity

unused/reserved

MFCO09 mask

MFCO10 mask

MFCO11 mask

MFCO12 mask

MFCO13 mask

MFCO14 mask

MFCO15 mask

MFCO16 mask

MFCO17 mask

MFCO18 mask

MFCO19 mask

MFCO20 mask

MFCO21 mask

MFCO22 mask

MFCO23 mask

unused/reserved

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

29

30

31

Table 207: MFC IO watchdog WD_OUT_MASK_POL signal/port assignment

Watchdog Input Port Conﬁguration The following table contains the assignments of ports/signals to

the conﬁguration bits in the WD_IN_MASK_POL register. An MFCIOxx pin programmed as input is called

MFCIxx.

Bit #

Signal

Bit #

32

Signal

0

1

2

3

4

MFCI00 polarity

MFCI01 polarity

MFCI02 polarity

MFCI03 polarity

MFCI04 polarity

MFCI00 mask

MFCI01 mask

MFCI02 mask

MFCI03 mask

MFCI04 mask

33

34

35

36

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Bit #

5

Signal

Bit #

37

38

39

40

41

42

43

44

45

46

47

48

49

50

51

52

53

54

55

56

57

58

59

60

61

62

63

Signal

MFCI05 polarity

MFCI06 polarity

MFCI07 polarity

MFCI08 polarity

MFCI09 polarity

MFCI10 polarity

MFCI11 polarity

MFCI12 polarity

MFCI13 polarity

MFCI14 polarity

MFCI15 polarity

MFCI16 polarity

MFCI17 polarity

MFCI18 polarity

MFCI19 polarity

MFCI20 polarity

MFCI21 polarity

MFCI22 polarity

MFCI23 polarity

unused/reserved

MFCI05 mask

MFCI06 mask

MFCI07 mask

MFCI08 mask

MFCI09 mask

MFCI10 mask

MFCI11 mask

MFCI12 mask

MFCI13 mask

MFCI14 mask

MFCI15 mask

MFCI16 mask

MFCI17 mask

MFCI18 mask

MFCI19 mask

MFCI20 mask

MFCI21 mask

MFCI22 mask

MFCI23 mask

unused/reserved

6

7

8

9

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

29

30

31

Table 208: MFC IO watchdog WD_IN_MASK_POL signal/port assignment

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7.20 MFC IO Emergency Switch Input

The MFC IO block oﬀers a dedicated emergency switch input called MFC_NES. It is low active.

It is used to set speciﬁc MFCIOxx outputs to a a conﬁgurable safe state in case of emergency.

The MFC_NES pin has weak internal pull-down resistor. A microcontroller or another circuit must actively

drive a high level at MFC_NES for normal operation.

The emergency switch input MFC_NES is only active if it is masked in the MFCIO_IRQ_CFG register at bit 23.

Otherwise it is ignored.

If MFC_NES triggers (low level), the respective outputs take their conﬁgured safe values. The internal

emergency switch ﬂag remains set in register MFCIO_IRQ_FLAGS even when the external pin MFC_NES is

already driven high again.

MFC_NES has impact on the following functional units and outputs:

•

MFC IO PWM block: the PWM high and low side gate outputs are set to a deﬁned conﬁgurable safe

oﬀ-state.

•

MFC IO GPIO block: all GPIOs that are conﬁgured as output ports via the crossbar are set to a deﬁned

conﬁgurable safe oﬀ-state.

• MFC IO Step and Direction block: the step outputs and internal step counters freeze.

• The MFCIO_IRQ signal will be triggered.

Note

The emergency ﬂag can only be unset be either doing a reset or by actively

writing 2 times into the MFCIO_IRQ_CFG register at bit position 23. Thereby, the

existing IRQ mask at bit 23 must ﬁrst be set to zero and then set back to 1 again.

This way, the internal emergency ﬂag is unset. This can be done either by the

local application controller or by the EtherCAT master if it has access to register

MFCIO_IRQ_CFG.

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7.21 MFC IO Analog and High Voltage Block

7.21.1 Multi Voltage High Current I/O Lines

MFC_HVy

1/2 VIOx

differential

SLOPE

HV or slow

slope

INx

Q

S

R

MFCIOx.slope

Input control

block

MFCIOx.differential

17/40 VIOx

1µs

low voltage &

fast slope

0.3V hyst.

1.2V

VIOx

5.5V

VIOx

MFCIOx.hv_on

SLOPE

100µA

Slope

controlled

driver

Level

shifter

10

MOSFET

Weak high

Level

shifter

OUTx

OEx

Output

MFC_HVx

MFCIOx.weak_h

MFCIOx.weak_l

control block

Weak low

10µA ||

1.5M

Slope

controlled

driver

5

MOSFET

100µA

GNDIO

SLOPE

MFCIOx.slowslope

OUTx

MFCIOx.short2VS

Short

protection

MFCIOx.short2GND

Figure 49: Schematic of multi voltage I/O port

Output Characteristics The multi voltage I/O lines allow direct driving of loads like lamps, LEDs or

solenoids with up to 100mA output current (200mA short time peak). They can be operated in a push / pull

mode, or in low current mode by using an internal pullup / pulldown resistor / current source combination.

The eight multi-voltage I/Os are grouped into three groups, which allow the use at the same, or diﬀerent

supply voltages.

In case inductive loads are driven, or loads with long interconnection cables, Schottky protection diodes

shall be added in order to avoid exceeding the respective supply voltage limits.

A slope limited mode allows reducing electromagnetic emission by using slower switching slopes. Additional

ﬁlter capacitors (up to 1nF recommended) may be placed on the output lines in this mode to eliminate any

HF noise.

The outputs provide a short to GND and short to supply protection. When an overcurrent condition is

detected, the respective MOSFET remains switched oﬀ for the period of constant polarity. The short circuit

detection features a current dependent activation time. The lower activation threshold is about 150mA.

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Upon exceeding the activation threshold, a time proportional to the excess current is required to switch oﬀ

the output. This way, short time peak currents can safely be switched, e.g. when long cables or capacitive

loads are attached.

An interrupt ﬂag informs about an active overcurrent condition. The short condition will be cleared once

the output polarity is toggled.

Input Characteristics The inputs automatically adapt to the supply voltage range. In low voltage range

(up to 5V operation), a fast digital Schmitt trigger is used for evaluation of the input logic levels. It provides

a TTL compatible input level.

In the high voltage range, the input path switches to a threshold voltage just at half supply voltage range.

Both modes add a hysteresis in order to avoid oscillation with slow transitions on the inputs. When

switching to slow slope operation, the input lines become ﬁltered in order to eliminate reaction to short

voltage spikes. In this mode, the half level comparator is always used. A minimum pull down current of

10µA is always drawn in order to ensure a deﬁned level on an open input.

The inputs allow a diﬀerential mode between each two combined inputs (see combination table). It is

important to set both inputs to the same slope setting in this case. Both input lines deliver a comparison

result using each one voltage comparator. This allows direct attachment of diﬀerential voltage sources

like encoders. The addition of input protection resistor networks is recommended in case long cables are

used.

When driving inductive loads a freewheeling diode must be provided to the high

voltage I/O pins to prevent from latch-up.

WARNING

Diﬀerential input pair Input 1

Input 2

A

B

C

D

MFC_HV0 MFC_HV3

MFC_HV1 MFC_HV4

MFC_HV2 MFC_HV5

MFC_HV6 MFC_HV7

Table 209: Diﬀerential input combination table

The inputs are read via Input 1 result.

7.21.2 Switching Regulators

The TMC8461 integrates a programmable and a ﬁxed buck switching regulator designed for up to 500mA

of output current.

The ﬁxed regulator has a ﬁxed output voltage of 3.3V. Its main purpose is to supply the TMC8461 I/Os

and the digital part via the 1.8V linear regulators. This regulator comes with an integrated 800mA 5.5V

Schottky diode which minimizes part count, when an external 5V supply is available. In case of a higher

supply voltage, use an external Schottky diode instead.

The second regulator can be programmed to any output voltage ranging from 1.2V up to the supply voltage

level. It can be used to generate an additional 3.3V supply or any additional voltage like 5V, 12V or 24V

required for operation of peripheral circuits or the high voltage I/O lines. An integrated common linear 5V

regulator starts up the switch regulators. Cascading of both switch regulators also is possible.

Both regulators support a wide range of L and C components. This is enabled by a programmable current

feedback loop gain and compensation capacity. Both switching regulators provide optional dampening of

the coil oscillations to reduce electromagnetic emission.

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+VS

Undervolt

1.2V Ref

VS

Bandgap

and 5V

auxiliary

regulator

100nF

VDD5_OUT

470nF

Regulator 1 /

Switch reg supply

3.3V Regulator

VDD5_INx

VSx

SC_DETECT

100nF

IMAX

SC_DISABLE

Set

PMOS

Driver

1

S

R

Q

MOSFET

Dutycycle limit

SAW_FREQ[1..0]

SWx

SAW

SWx_IN

oscillator

+

-

L_SW

Dampening

Circuit

Sum

Amplifier

Compa-

rator

&

Reg. 1 only

VOUT1_DAMP

SW0_DIODE

SW regulator output

+VIO

0.8A Schottky

CSW

CSWE

GND0_DIODE

VREG3V3_FB

53k

92k

R_FB

C_FB

R_V1

VOUT1_FB

Reg. 1 only

250k

R_V2

VOUT_DISABLE

0→

1.2V

1.2V Ref

Soft Start

Circuit

VOUT_DISABLE (Reg. 1)

Overtemp (3.3V Reg.)

/

Disable

UV

Figure 50: Internal schematic and external components for both switching regulators

Input voltage Output voltage L_SW

C_SW

5V

3.3V

15µH 22µF

68µH 47µF

24V

35V

3.3V to 12V

3.3V to 25V

Table 210: Switching regulator component selection for L and C

The capacitor can either be a ceramic type, or an electrolytic low-ESR capacitor in

parallel to a 1µF or larger ceramic capacitor.

Info

7.21.3 Analog Block Status Register

MFC IO Register 59 HV_ANA_STATUS provides various status ﬂags on the actual state of the analog block.

This includes:

• short to ground and short to supply detection for the HV IOs

• high voltage detection ﬂags for the HV IOs

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• over-temperature detection for the HV IO circuit

• short circuit/over-current detection for the switching regulators

• over-temperature detection for the adjustable switching regulator

Please refer to Table 184 for more details.

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8 Electrical Ratings

8.1 Absolute Maximum Ratings

Note

The maximum ratings may not be exceeded under any circumstances. Operating

the circuit at or near more than one maximum rating at a time for extended

periods shall be avoided by application design.

Parameter

Symbol

V_VS, V_VIOx

V_VIO

Min

Max

40

Unit

V

Supply and HV IO supply voltage with T_J= 0°C *)

Supply and HV IO supply voltage max. with T_Jfull range *)

Maximum voltage on HV IO pins

35

V

-0.6

V_VIOx+0.6

V

Peak current into HV IO input protection diodes (100ms)

Digital I/O supply voltage

I_HVIOPEAK

V_VIO

-100 +100

mA

V

3.6

1.98

3.6

10

Digital VCC supply voltage (if not supplied by internal regulator)

Logic input voltage

V_VCC

V

V_I

V

Maximum current to / from digital pins and analog low voltage I_IO

I/Os

mA

1.8V regulator output current (internal plus external load)

Switching regulator repetitive short time output current

Schottky diode reverse voltage

I_VOUT18

mA

V

I_VOUTSW

V_SDR

I_SD

800

7

Schottky diode repetitive short time forward current

Junction temperature

800

mA

°C

T_J

-40

-55

175

Storage temperature

T_STG

V_ESDAP

V_ESD

150

°C

ESD-Protection for interface pins (Human body model, HBM)

ESD-Protection for handling (Human body model, HBM)

4 (tbd.)

1 (tbd.)

kV

Table 211: Absolute Maximum Ratings for TMC8461-BA

*) Stray inductivity of GND and VS connections will lead to ringing of the supply voltage when driving

load. This ringing results from the fast switching slopes of the driver outputs in combination with reverse

recovery of the body diodes of the output driver MOSFETs. Even small trace inductivities as can easily

generate a few volts of ringing leading to temporary voltage overshoot. This should be considered when

working near the maximum voltage.

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8.2 Operational Ratings

Parameter

Symbol

T_J

Min Max Unit

Junction temperature

-40

125

°C

V

High voltage supply voltage

V_VS,VS0,VS14.75 34

V_VCCIO3.15 3.45

V_VIOx

Digital I/O 3.3V supply voltage

I/O supply voltage (high voltage mode)

I/O Supply voltage (low voltage mode)

Continuous output current single high voltage I/O

V

6.0

3.0

34

V

V_VIOx

5.5

100

200

500

5.5

V

I_OUT,HVIO

mA

V

Continuous current into / from any high voltage I/O supply or GND pin I_IN,HVIO

Switching regulator DC output current

I_OUT,SW

3.3V Switching regulator supply voltage when using internal Schottky

diode

4

Core supply voltage

V_{VCC_CORE}1.65 1.95

V

Table 212: Operational Ratings for TMC8461-BA

8.3 DC Characteristics and Timing Characteristics

DC characteristics contain the spread of values guaranteed within the speciﬁed supply voltage range

unless otherwise speciﬁed. Typical values represent the average value of all parts measured at +25 C.

°

Temperature variation also causes stray to some values. A device with typical values will not leave Min/Max

range within the full temperature range.

8.3.1 High Voltage I/O Block

When driving inductive loads a freewheeling diode must be provided to the high

voltage I/O pins to prevent from latch-up.

WARNING

Parameter

Symbol

Conditions

Min

Typ

90

Max

140

Unit

µA

HV supply current per high volt- I_VHVIO

age I/O pad

No current driven,

static mode

R_DSonlow side

R_ONL

R_ONH

I_PD

T_J=25 °C

6

10

Ω

R_DSonhigh side

V_VIOx=5 V; T_J=25 °C

V_VIOx=3.3 V; T_J=25 °C

10

13

63

110

76

15

Ω

R_DSonhigh side

20

Ω

Weak pull down current

Weak pull up current

37

66

50

115

210

150

µA

I_PU

V_VIOx=5 V; T_J=25 °C

V_VIOx=3.3 V; T_J=25 °C

I_PU

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Parameter

Symbol

Conditions

Min

Typ

Max

Unit

Over-current protection activa- I_OCH

tion threshold sourcing

Output sourcing cur- -100 -150

rent

-500 mA

Over-current protection activa- I_OCL

Output sinking cur- 100

rent

150

500

mA

µs

tion threshold sinking

200mA sink current capability t_OCL200

time limit

Output sinking cur- 10

rent

Switching slope (slow) rising

Switching slope (slow) falling

Switching slope (fast) rising

Switching slope (fast) falling

Input ﬁlter time constant

Input threshold (LV mode)

t_HVOLH

t_HVOHL

t_HVOLH

t_HVOHL

t_HVIF

10% to 90%

100

200

20

500

ns

90% to 10%

10% to 90%

90% to 10%

20

Slow slope setting

750

1000

1500 ns

V

V_HVILLL

Input

going

low, 0.8

V_VIOx=5.5 V

Input threshold (LV mode)

V_HVIHLL

Input going high,

V_VIOx=5.5 V

1.6

V

Input hysteresis (LV mode)

Input threshold (HV mode)

Input hysteresis (HV mode)

V_HVIHYSTLV_VIOx=5.5 V

V_HVIHLHInput going high

V_HVILLHInput going low

0.1

0.3

V

0.5 V_VIO

0.43 V_VIO

0.075 V_VIO

0

V

V_HVIHYSTH

V

Diﬀerential mode input oﬀset V_HVID

voltage (LV mode and fast slope)

Common mode volt- -10

age >=0.5 V

+10

mV

Diﬀerential mode input oﬀset V_HVID

voltage (HV mode or slow slope

setting)

Common mode volt- -150

age >=2 V

0

+150 mV

Input delay (300mV step)

Diﬀerential

mode,

100

50

ns

µA

fast slope

Input current per high voltage I_HVIOH

I/O pad (HV mode)

V_HVIO= V_VIOx= 24 V

26

10

Input current per high voltage I_HVIOH

I/O pad (LV mode)

V_HVIO= V_VIOx= 3.0 V to

5 V

15

Table 213: High Voltage I/O Block DC Characteristics

8.3.2 Switching Regulators

Parameter

Symbol

Conditions

Min Typ

90

Max

140

Unit

µA

HV supply current per high voltage I/O pad

I_VHVIO

No

current

driven, static

mode

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Parameter

Symbol

R_ON

Conditions

T_J=25 °C

Min Typ

1

Max

1.5

Unit

R_DSonpower switch

Ω

Over-current protection activation threshold I_OCH

sourcing

Output sourc- 800 1200 1600 mA

ing current

Oscillator frequency

f_OSC

Setting 00 (de-

fault)

240

kHz

Setting 01

Setting 10

Setting 11

130

470

890

83

Duty cycle limit

dl

%

Schottky diode forward voltage

Soft startup time

V_SDF

I=350mA

0.60

1

0.80

5.25

V

ms

V

5V auxiliary voltage regulator output voltage V_{VDD5_OUT}

4.75

5

5V auxiliary voltage regulator output current I_{VDD5_OUT}

limit

10

mV

Table 214: Switching Regulator DC Characteristics

8.3.3 Digital IOs

All I/O lines include Schmitt-Trigger inputs to enhance noise margin.

Parameter

Symbol Conditions

Min

-0.3

2.3

5

Typ

30

Max Unit

Input voltage low level

Input voltage high level

Input with pull-down

V_INL

V_INH

V_VCCIO= 3.3V

V_IN= 3.3V

V_IN= 0V

0.8

3.6

110

-5

V

µA

V

Input with pull-up

-110 -30

-10

Input low current

V_IN= 0V

10

Input high current

V_IN= V_DD

-10

10

Output voltage low level

Output voltage high level

Output driver strength standard

Output driver strength LED outputs

Driver strength NRESET I/O pin

V_OUTL

V_VCCIO= 3.3V

0.4

V_OUTH

2.64

4

V

I_{OUT_DRV}

I_{OUT_LED}

mA

µA

8

I_{OUT_RST}Driven by internal un- ±5

dervoltage detectors

High/Low

±30

Table 215: Digital IOs DC Characteristics

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9 Manufacturing Data

9.1 Package Dimensions

Figure 51: TMC8461-BA package outline drawing

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Symbol

Min

—

Normal

—

Max

Total thickness

Stand oﬀ

A

A1

A2

A3

D

1.0

0.26

REF

BSC

0.16

—

Substrate thickness

Mold thickness

Body size

0.21

0.45

10

Body size

E

10

Ball diameter

0.3

Ball Opening

0.275

—

Ball width

b

e

0.27

0.37

BSC

Ball pitch

0.8

Ball count

n

144

8.8

Edge ball center to center

Body center to contact ball

Package edge tolerance

Mold ﬂatness

D1

E1

BSC

8.8

SD

SE

0.4

aaa

bbb

ddd

eee

ﬀf

0.1

Coplanarity

0.08

0.15

0.08

Ball oﬀset (package)

Ball oﬀset (ball)

Table 216: Dimensions of TMC8461-BA

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9.2 Marking

The device marking is shown below.

Pin 1 location is highlighted with a dot.

YYWW = date code.

LLLLL = Lot number.

Figure 52: TMC8461-BA device marking

9.3 Board and Layout Considerations

•

Example part libraries for diﬀerent CAD tools are available as downloads on the respective IC product

page on the TRINAMIC website at https://www.trinamic.com/products/integrated-circuits/.

Package drawings, recommended land patterns, and soldering proﬁles for all TRINAMIC IC packages

are available online at https://www.trinamic.com/support/help-center/ic-packages/

TRINAMIC’s evaluation boards are fully available as layout examples and recommendations and

are free for download. Design data, Gerber data, and additional information is available at https:

//www.trinamic.com/support/eval-kits/.

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10 Abbreviations

198 / 204

Abbreviation Description

MCU

AL

Microcontroller unit, application controller

Application Layer

ASIC

CoE

Application Speciﬁc Integrated Circuit

CAN application protocol over EtherCAT

Common Anode or common cathode

Central Processing Unit

COMM

CPU

DC

Distributed Clocks

DPRAM

ECAT

ENI

Dual Ported Random Access Memory

EtherCAT

EtherCAT Network Information (Information on Network conﬁguration in XML format)

End of Frame

EOF

ESC

EtherCAT Slave Controller

ESI

EtherCAT Slave Information (device description/conﬁguration data in XML format)

EtherCAT State Machine

ESM

ETG

EtherCAT Technology Group

EtherCAT

FMMU

FoE

Ethernet for Control Automation Technology

Fieldbus Memory Management Unit

File Access over EtherCAT

GPIO

GPI

General Purpose I/O

General Purpose Input

GPO

IDE

General Purpose Output

Integrated Development Environment

International Electrotechnical Commission

Interrupt Request

IEC

IRQ

LED

Light Emitting Diode

MI

(PHY) Management Interface

MII

Media Independent Interface

Master In - Slave Out

MISO

MOSI

PDI

Master Out - Slave In

Process Data Interface

PDO

PDRAM

Process Data Object

Process Data Random Access Memory

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POF

RMS

SII

Passive Optical Fiber

Root Mean Square value

Slave Information Interface

SyncManager

SM

SOF

SPI

Start of Frame

Serial Peripheral Interface

TRINAMIC Motion Control Language

(Shielded) Twisted Pair Copper

Transistor Transistor Logic

Universal Asynchronous Receiver Transmitter

Universal Serial Bus

TMCL

(S)TPC

TTL

UART

USB

XML

Extended Mark-up Language

Table 217: Abbreviations used in this Manual

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11 Figures Index

1

2

3

General device architecture . . . . . .

TMC8461 Evaluation Board . . . . . . 11

TMC8462 breakout board for RJ45 and

7

27 Status LED circuit . . . . . . . . . . . . 39

28 SII EEPROM circuit (shown for EEP-

ROMs >32kBit) . . . . . . . . . . . . . . 40

29 MFC IO Block Conﬁguration using the

ESC Parameter RAM . . . . . . . . . . 112

30 MFC IO Crossbar Example Conﬁguration152

31 MFC IO ESI/XML Conﬁguration Block . 158

32 MFC IO Incremental Encoder Unit . . 159

33 Block structure of SPI Master Unit . . 161

34 Block structure of SPI Master Unit . . 166

35 Block structure of the MFC IO Step and

Direction Block . . . . . . . . . . . . . 170

36 Step & Direction Signal Timing . . . . 171

37 Block structure of the MFC IO PWM

Block . . . . . . . . . . . . . . . . . . . 173

38 PWM chopper modes . . . . . . . . . 175

39 PWM Timing (centered PWM) . . . . . 176

40 PWM Timing (left aligned PWM) . . . . 176

41 PWM Timing (right aligned PWM) . . . 177

42 PWM BBM Timing . . . . . . . . . . . . 177

43 Centered PWM with PWM channel 2

shifted from center (example showing

TPC . . . . . . . . . . . . . . . . . . . . 12

TMCL-IDE . . . . . . . . . . . . . . . . . 13

4

5

Conﬁguration wizard example

MFC IO block conﬁguration . . . . . . 14

Conﬁguration wizard example

–

6

–

SII EEPROM content and C-code output 14

TMC8461-BA Pinout top view . . . . . 15

PDI control signals . . . . . . . . . . . 23

PDI SPI 2 byte addressing . . . . . . . 24

7

8

9

10 PDI SPI 3 byte addressing . . . . . . . 25

11 SPI timing example . . . . . . . . . . . 26

12 MFC control signals . . . . . . . . . . . 27

13 MFC CTRL SPI 2 byte addressing . . . 28

14 MFC CTRL SPI 3 byte addressing . . . 28

15 MFC SPI timing example . . . . . . . . 28

16 SPI bus sharing . . . . . . . . . . . . . 29

17 MII pins . . . . . . . . . . . . . . . . . . 30

18 Minimum external circuit for power-

on reset . . . . . . . . . . . . . . . . . . 33

19 PLL supply ﬁlter . . . . . . . . . . . . . 33

20 External circuit for switching regulator

0 with VS0 = 5V . . . . . . . . . . . . . 34

21 External circuit for switching regulator

0 with VS0 > 5V . . . . . . . . . . . . . 34

22 External circuit for adjustable buck

regulator . . . . . . . . . . . . . . . . . 35

23 Minimum external supply circuit for

single 3.3V supply . . . . . . . . . . . . 36

24 Minimum external supply circuit for

single 5V supply . . . . . . . . . . . . . 37

25 Minimum external supply circuit for

single supply >5V . . . . . . . . . . . . 38

26 Typical power supply chain using both

buck converters . . . . . . . . . . . . . 39

only 3 PWM channels) . . . . . . . . . 178

44 RC ﬁlter for DAC output with example

values . . . . . . . . . . . . . . . . . . . 179

45 Block structure of GPIO Unit . . . . . 180

46 Block structure of the MFC IO IRQ Block181

47 Logical position of the MFC IO watch-

dog unit between crossbar and MF-

CIOxx pins . . . . . . . . . . . . . . . . 182

48 Structure of the MFC IO watchdog unit 183

49 Schematic of multi voltage I/O port

. 187

50 Internal schematic and external com-

ponents for both switching regulators 189

51 TMC8461-BA package outline drawing 195

52 TMC8461-BA device marking . . . . . 197

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12 Tables Index

1

2

TMC8461 order codes . . . . . . . . .

Pin and Signal description for

6

49 Register 0x0310:0x0313 (LL Counter)

50 Register 0x0400:0x0401 (WD Divider)

74

75

TMC8461-BA . . . . . . . . . . . . . . . 22

PDI signal description . . . . . . . . . 24

PDI SPI commands . . . . . . . . . . . 24

MFC CTRL SPI signal description . . . 27

MII signal description . . . . . . . . . . 31

Available EtherCAT Chip Features (0

51 Register 0x0410:0x0411 (WD Time PDI) 75

52 Register 0x0420:0x0421 (WD Time PD) 75

53 Register 0x0440:0x0441 (WD Status PD) 76

54 Register 0x0442 (WD Counter PD) . . 76

55 Register 0x0443 (WD Counter PDI) . . 77

56 SII EEPROM Interface Register Overview 78

57 Register 0x0500 (PROM Conﬁg) . . . . 78

58 Register 0x0501 (PROM PDI Access) . 78

59 Register 0x0502:0x0503 (PROM Cntrl) 80

60 Register 0x0504:0x0507 (PROM Address) 80

3

4

5

6

7

= not available/disabled, 1 = avail-

able/enabled . . . . . . . . . . . . . . . 43

TMC8461 EtherCAT Registers . . . . . 49

Register 0x0000 (Type) . . . . . . . . . 50

8

9

10 Register 0x0001 (Revision) . . . . . . . 50

11 Register 0x0002 (Build) . . . . . . . . . 50

12 Register 0x0004 (FMMUs) . . . . . . . 51

13 Register 0x0005 (SMs) . . . . . . . . . 51

14 Register 0x0006 (RAM Size) . . . . . . 51

15 Register 0x0007 (Port Descriptor) . . 52

16 Register 0x0008:0x0009 (ESC Features) 53

17 Register 0x0010:0x0011 (Station Addr) 54

18 Register 0x0012:0x0013 (Station Alias) 54

19 Register 0x0020 (Write Register Enable) 55

20 Register 0x0021 (Write Register Prot.) 55

61 Register 0x0508:0x050F (PROM Data)

81

62 Register 0x0580:0x05E1 (MFC IO Conﬁg) 82

63 MII Management Interface Register

Overview . . . . . . . . . . . . . . . . . 83

64 Register 0x0510:0x0511 (MI Cntrl/State) 84

65 Register 0x0512 (PHY Address) . . . . 84

66 Register 0x0513 (PHY Register Address) 85

67 Register 0x0514:0x0515 (PHY Data)

.

85

68 Register 0x0516 (MI ECAT State) . . . 85

69 Register 0x0517 (MI PDI State) . . . . 86

70 Register 0x0518+y (PHY Port Status) . 86

71 FMMU Register Overview . . . . . . . 87

72 Register 0x06y0:0x06y3 (Log Start Addr) 87

73 Register 0x06y4:0x06y5 (FMMU Length) 87

74 Register 0x06y6 (Log. Start Bit) . . . . 88

75 Register 0x06y7 (Log. Stop Bit)) . . . . 88

21 Register 0x0030 (ESC Write Enable)

.

55

22 Register 0x0031 (ESC Write Prot.) . . . 56

23 Register 0x0040 (ESC Reset ECAT) . . 57

24 Register 0x0041 (ESC Reset PDI) . . . 57

25 Register 0x0100:0x0103 (DL Control) . 59

26 Register 0x0108:0x0109 (R/W Oﬀset)

59

Register 0x06y8:0x06y9 (Phy. Start Addr 88

76

27 Register 0x0110:0x0111 (DL Status) . 61

28 Decoding port state in ESC DL Status

register 0x0111 (typical modes only) . 61

29 Register 0x0120:0x0121 (AL Cntrl) . . 62

77 Register 0x06yA (Phy. Start Bit) . . . . 88

78 Register 0x06yB (FMMU Type) . . . . . 89

79 Register 0x06yC (FMMU Activate) . . . 89

80 Register 0x06yD:0x06yF (Reserved)

.

89

30 Register 0x0130:0x0131 (AL Status)

.

63

81 SyncManager Register Overview . . . 90

82 Register 0x0800+y*8:0x0801+y*8 (Phy.

Start Addr) . . . . . . . . . . . . . . . . 90

83 Register 0x0802+y*8:0x0803+y*8 (SM

Length) . . . . . . . . . . . . . . . . . . 90

84 Register 0x0804+y*8 (SM Control) . . 91

85 Register 0x0805+y*8 (SM Status) . . . 92

86 Register 0x0806+y*8 (SM Activate) . . 92

87 Register 0x0807+y*8 (SM PDI Control) 93

88 Register 0x0900:0x0903 (Rcv Time P0) 94

89 Register 0x0904:0x0907 (Rcv Time P1) 94

90 Register 0x0910:0x0917 (System Time) 95

91 Register 0x0918:0x091F (Rcv Time EPU) 95

92 Register 0x0920:0x0927 (Sys Time Oﬀ-

set) . . . . . . . . . . . . . . . . . . . . 96

93 Register 0x0928:0x092B (Sys Time De-

lay) . . . . . . . . . . . . . . . . . . . . 96

94 Register 0x092C:0x092F (Sys Time Diﬀ) 96

95 Register 0x0930:0x931 (Speed Cnt Start) 97

31 Register 0x0134:0x0135 (AL Status Code) 63

32 Register 0x0138 (RUN LED Override) . 64

33 Register 0x0139 (ERR LED Override) . 64

34 Register 0x0140 (PDI Control) . . . . . 65

35 Register 0x0141 (ESC Conﬁg) . . . . . 65

36 Register 0x014E (PDI Information)) . . 66

37 Register 0x0150 (PDI SPI CFG) . . . . . 67

38 Register 0x0151 (SYNC/LATCH CFG)

.

68

39 Register 0x0152:0x0153 (PDI SPI extCFG) 68

40 Register 0x0200:0x0201 (ECAT Event M.) 69

41 Register 0x0204:0x0207 (AL Event Mask) 69

42 Register 0x0210:0x0211 (ECAT Event R.) 70

43 Register 0x0220:0x0223 (AL Event R.)

71

44 Register 0x0300:0x0307 (RX Err Cnt) . 72

45 Register 0x0308:0x030B (FW RX Err Cnt) 72

46 Register 0x030C (Proc. Unit Err Cnt) . 72

47 Register 0x030D (PDI Err Cnt) . . . . . 73

48 Register 0x030E (PDI Err Code) . . . . 73

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96 Register 0x0932:0x0933 (Speed Cnt Diﬀ) 97

97 Register 0x0934 (Sys Time Diﬀ Filter) . 98

98 Register 0x0935 (Speed Cnt Filter Depth) 98

99 Register 0x0980 (Cyclic Unit Cntrl) . . 99

100 Register 0x0981 (SYNC Out Activation) 100

101 Register 0x0982:0x0983 (SYNC Pulse

Length) . . . . . . . . . . . . . . . . . . 101

102 Register 0x0984 (Activation Status) . . 101

103 Register 0x098E (SYNC0 Status) . . . . 101

104 Register 0x098F (SYNC1 Status) . . . . 102

105 Register 0x0990:0x0997 (Start Time

Cyclic Operation) . . . . . . . . . . . . 102

106 Register 0x0998:0x099F (Next SYNC1) 102

107 Register 0x09A0:0x09A3 (SYNC0 Cycle

Time) . . . . . . . . . . . . . . . . . . . 103

108 Register 0x09A4:0x09A7 (SYNC1 Cycle

Time) . . . . . . . . . . . . . . . . . . . 103

109 Register 0x09A8 (Latch0 Control) . . . 104

110 Register 0x09A9 (Latch1 Control) . . . 104

111 Register 0x09AE (Latch0 Status) . . . . 105

112 Register 0x09AF (Latch1 Status) . . . . 105

113 Register 0x09B0:0x09B7 (Latch0 Time

Pos Edge) . . . . . . . . . . . . . . . . . 106

114 Register 0x09B8:0x09BF (Latch0 Time

Neg Edge) . . . . . . . . . . . . . . . . 106

115 Register 0x09C0:0x09C7 (Latch1 Time

Pos Edge) . . . . . . . . . . . . . . . . . 107

116 Register 0x09C8:0x09CF (Latch1 Time

Neg Edge) . . . . . . . . . . . . . . . . 107

117 Register 0x09F0:0x09F3 (ECAT Buﬀer

Change Event Time) . . . . . . . . . . . 108

118 Register 0x09F8:0x09FB (PDI Buﬀer

Start Event Time) . . . . . . . . . . . . 108

119 Register 0x09FC:0x09FF (PDI Buﬀer

Change Event Time) . . . . . . . . . . . 108

120 Register 0x0E00:0x0E07 (Product ID) . 109

121 Register 0x0E08:0x0E0F (Vendor ID) . 109

122 Process Data RAM (0x1000:0xFFFF) . . 110

123 Process Data RAM Size . . . . . . . . . 110

124 MFC IO Register Overview for

TMC8461-BA . . . . . . . . . . . . . . . 115

125 MFC IO Register 0 – ENC_MODE . . . 116

126 MFC IO Register 1 – ENC_STATUS . . . 117

127 MFC IO Register 2 – X_ENC (write) . . 117

128 MFC IO Register 3 – X_ENC (read) . . . 117

129 MFC IO Register 4 – ENC_CONST . . . 117

130 MFC IO Register 5 – ENC_LATCH . . . 118

131 MFC IO Register 6 – SPI_RX_DATA . . . 119

132 MFC IO Register 7 – SPI_TX_DATA . . . 119

133 MFC IO Register 8 – SPI_CONF . . . . . 120

134 MFC IO Register 9 – SPI_STATUS . . . . 120

135 MFC IO Register 10 – SPI_LENGTH . . 120

136 MFC IO Register 11 – SPI_TIME . . . . 120

137 MFC IO Register 12 – I2C_TIMEBASE . 121

138 MFC IO Register 13 – I2C_CONTROL . 121

139 MFC IO Register 14 – I2C_STATUS . . . 121

140 MFC IO Register 15 – I2C_ADDRESS . . 122

141 MFC IO Register 16 – I2C_DATA_R . . . 122

142 MFC IO Register 17 – I2C_DATA_W . . 122

143 MFC IO Register 18 – SD_CH0_STEPRATE123

144 MFC IO Register 19 – SD_CH1_STEPRATE123

145 MFC IO Register 20 – SD_CH2_STEPRATE123

146 MFC IO Register 21 – SD_CH0_STEPCOUNT124

147 MFC IO Register 22 – SD_CH1_STEPCOUNT124

148 MFC IO Register 23 – SD_CH2_STEPCOUNT124

149 MFC IO Register 24 – SD_CH0_STEPTARGET124

150 MFC IO Register 25 – SD_CH1_STEPTARGET125

151 MFC IO Register 26 – SD_CH2_STEPTARGET125

152 MFC IO Register 27 – SD_CH0_COMPARE125

153 MFC IO Register 28 – SD_CH1_COMPARE126

154 MFC IO Register 29 – SD_CH2_COMPARE126

155 MFC IO Register 30 – SD_CH0_NEXTSR 126

156 MFC IO Register 31 – SD_CH1_NEXTSR 126

157 MFC IO Register 32 – SD_CH2_NEXTSR 127

158 MFC IO Register 33 – SD_STEPLENGTH 127

159 MFC IO Register 34 – SD_DELAY . . . . 127

160 MFC IO Register 35 – SD_CFG . . . . . 128

161 MFC IO Register 36 – PWM_CFG . . . . 129

162 MFC IO Register 37 – PWM1 . . . . . . 130

163 MFC IO Register 38 – PWM2 . . . . . . 130

164 MFC IO Register 39 – PWM3 . . . . . . 130

165 MFC IO Register 40 – PWM4 . . . . . . 130

166 MFC IO Register 41 – PWM1_CNTRSHFT 131

167 MFC IO Register 42 – PWM2_CNTRSHFT 131

168 MFC IO Register 43 – PWM3_CNTRSHFT 131

169 MFC IO Register 44 – PWM4_CNTRSHFT 131

170 MFC IO Register 45 – PWM_PULSE_B_PULSE_A132

171 MFC IO Register 46 – PWM_PULSE_LENGTH132

172 MFC IO Register 47 – GPO . . . . . . . 133

173 MFC IO Register 48 – GPI . . . . . . . . 133

174 MFC IO Register 49 – GPIO_CONFIG . 133

175 MFC IO Register 50 – DAC_VAL . . . . 134

176 MFC IO Register 51 – MFCIO_IRQ_CFG 135

177 MFC IO Register 52 – MFCIO_IRQ_FLAGS136

178 MFC IO Register 53 – WD_TIME . . . . 137

179 MFC IO Register 54 – WD_CFG . . . . . 137

180 MFC IO Register 55 – WD_OUT_MASK_POL138

181 MFC IO Register 56 – WD_OE_POL . . 138

182 MFC IO Register 57 – WD_IN_MASK_POL139

183 MFC IO Register 58 – WD_MAX . . . . 139

184 MFC IO Register 59 – HV_ANA_STATUS 140

185 MFC IO Register 63 – SYNC1_SYNC0_EVENT_CNT140

186 MFC IO Register 64 – HVIO_CFG . . . . 141

187 MFC IO Register 65 – BUCK_CONV_CFG 143

188 MFC IO Register 66 – AL_OVERRIDE

. 144

189 EEPROM Parameter Map . . . . . . . . 148

190 Crossbar conﬁguration values . . . . 151

191 Slope Slow/Weak High/WeakLow conﬁg153

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192 Diﬀerential HV input conﬁguration . . 153

193 Conﬁguration bits for 3.3V switching

regulator . . . . . . . . . . . . . . . . . 154

194 Conﬁguration bits for adjustable

switching regulator . . . . . . . . . . . 155

195 Register mapping example . . . . . . 156

196 Register conﬁguration byte . . . . . . 157

197 Trigger source descriptions . . . . . . 157

198 SPI mode conﬁguration . . . . . . . . 162

199 I2C control commands . . . . . . . . . 166

200 I2C status register bits . . . . . . . . . 167

201 I2C status overview . . . . . . . . . . . 167

202 I2C Addres register . . . . . . . . . . . 168

207 MFC IO watchdog WD_OUT_MASK_POL

signal/port assignment . . . . . . . . . 184

208 MFC IO watchdog WD_IN_MASK_POL

signal/port assignment . . . . . . . . . 185

209 Diﬀerential input combination table . 188

210 Switching regulator component selec-

tion for L and C . . . . . . . . . . . . . 189

211 Absolute Maximum Ratings for

TMC8461-BA . . . . . . . . . . . . . . . 191

212 Operational Ratings for TMC8461-BA 192

213 High Voltage I/O Block DC Characteris-

tics . . . . . . . . . . . . . . . . . . . . . 193

214 Switching Regulator DC Characteristics 194

215 Digital IOs DC Characteristics . . . . . 194

216 Dimensions of TMC8461-BA . . . . . . 196

217 Abbreviations used in this Manual . . 199

218 IC Revision . . . . . . . . . . . . . . . . 204

219 Document Revision . . . . . . . . . . . 204

203 Step and direction unit parameters

. 171

204 PWM unit parameters . . . . . . . . . 174

205 PWM modes . . . . . . . . . . . . . . . 174

206 GPO signal output states . . . . . . . . 180

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TMC8461 Datasheet • Document Revision V1.4 • 2018-Oct-05

204 / 204

13 Revision History

13.1 IC Revision

Version Date

Author

Description

V1.0

V1.1

V1.11

01.07.2016 SK, SL, BD, HS Silicon V1.0

01.09.2017 SK, SL, BD, HS Silicon V1.1

01.11.2017 SK, SL, BD, HS Silicon V1.11

Table 218: IC Revision

13.2 Document Revision

Version Date

Author

Description

V1.00

V1.10

V1.20

V1.30

V1.40

01.09.2017 SK, SL, BD Initial release version

01.12.2017 SK, SL, BD Updated for ﬁnal product version

14.03.2018 SK, BD

13.04.2018 SK, OK

05.10.2018 SK

Added latch-up warning for high voltage IOs

Intra-document references ﬁxed

Added info on unused package pins to pin table

Table 219: Document Revision

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型号：	TMC8461-BA
厂家：	TRINAMIC MOTION CONTROL GMBH & CO. KG.
描述：	2 MII Interfaces for external Ethernet PHY
文件：	总204页 (文件大小：11880K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

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