TS1101-50EG6TP [TOUCHSTONE]
A 1uA, +2V to +25V Bidirectional Precision Current-Sense Amplifier; 一个1uA的， + 2V至+ 25V双向高精度电流检测放大器
| 型号： | TS1101-50EG6TP |
| 厂家： | 
TOUCHSTONE SEMICONDUCTOR INC |
| 描述： | A 1uA, +2V to +25V Bidirectional Precision Current-Sense Amplifier |
| 文件： | 总11页 (文件大小：1048K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
TS1101
A 1µA, +2V to +25V Bidirectional Precision Current-Sense Amplifier
DESCRIPTION
FEATURES
The bi-directional, voltage-output TS1101 current-
sense amplifiers are the lowest-power and most
accurate current-sense amplifiers available today.
Consuming a very low 1μA supply current, the
TS1101 high-side current-sense amplifiers exhibit a
100-µV (max) VOS and a 0.6% (max) gain error, both
specifications optimized for any precision current
measurement. For all high-side bidirectional current-
sensing applications, the TS1101s are self-powered
and feature a wide input common-mode voltage
range from 2V to 25V. A SIGN comparator digital
output is also provided that indicates the direction of
current flow depending on the external connections to
the TS1101’s RS+ and RS- input terminals.
♦ Ultra-Low Supply Current: 1μA
♦ Wide Input Common Mode Range: +2V to +25V
♦ Low Input Offset Voltage: 100μV (max)
♦ Low Gain Error: 0.6% (max)
♦ Voltage Output
♦ SIGN Comparator Output: No “Dead Zone”
at ILOAD Switchover
♦ Four Gain Options Available:
TS1101-25: Gain = 25V/V
TS1101-50: Gain = 50V/V
TS1101-100: Gain = 100V/V
TS1101-200: Gain = 200V/V
♦ 6-Lead SOT23 Packaging
APPLICATIONS
The SOT23 package makes the TS1101 an ideal
choice for pcb-area-critical, supply-current-conscious,
high-accuracy current-sense applications in all
battery-powered and portable instruments.
Notebook Computers
Power Management Systems
Portable/Battery-Powered Systems
Smart Chargers
Smart Phones
All TS1101s are specified for operation over the
-40°C to +105°C extended temperature range.
TYPICAL APPLICATION CIRCUIT
SIGN Comparator’s Symmetric ILOAD Switchover
PA`RT
GAIN OPTION
25 V/V
TS1101-25
TS1101-50
TS1101-100
TS1101-200
50 V/V
100 V/V
200 V/V
The Touchstone Semiconductor logo is a registered
trademark of Touchstone Semiconductor, Incorporated.
Page 1
© 2012 Touchstone Semiconductor, Inc. All rights reserved.
TS1101
ABSOLUTE MAXIMUM RATINGS
RS+, RS- to GND..............................................-0.3V to +27V
VDD, OUT, SIGN to GND.......................................-0.3V to +6
RS+ to RS-..................................................................... ±27V
Short-Circuit Duration: OUT to GND .................... Continuous
Continuous Input Current (Any Pin) ............................ ±20mA
Continuous Power Dissipation (TA = +70°C)
Operating Temperature Range .................... -40°C to +105°C
Junction Temperature ................................................ +150°C
Storage Temperature Range ....................... -65°C to +150°C
Lead Temperature (Soldering, 10s) ........................... +300°C
Soldering Temperature (Reflow) ............................ +260°C
6-Lead SOT23 (Derate at 4.5mW/°C above +70°C)
............................................................................... 360mW
Electrical and thermal stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These
are stress ratings only and functional operation of the device at these or any other condition beyond those indicated in the operational sections
of the specifications is not implied. Exposure to any absolute maximum rating conditions for extended periods may affect device reliability and
lifetime.
PACKAGE/ORDERING INFORMATION
ORDER NUMBER
TS1101-25EG6TP
TS1101-25EG6T
TS1101-50EG6TP
TS1101-50EG6T
TS1101-100EG6TP
TS1101-100EG6T
TS1101-200EG6TP
TS1101-200EG6T
PART MARKING CARRIER QUANTITY
Tape & Reel
Tape & Reel
Tape & Reel
Tape & Reel
Tape & Reel
Tape & Reel
Tape & Reel
Tape & Reel
-----
3000
-----
TADN
TADP
TADQ
TADR
3000
-----
3000
-----
3000
Lead-free Program: Touchstone Semiconductor supplies only lead-free packaging.
Consult Touchstone Semiconductor for products specified with wider operating temperature ranges.
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TS1101
ELECTRICAL CHARACTERISTICS
VRS+ = 3.6V; VSENSE = (VRS+ - VRS-) = 0V; COUT = 47nF; VDD = 1.8V; TA = -40°C to +105°C, unless otherwise noted.
Typical values are at TA = +25°C. See Note 1.
PARAMETER
SYMBOL
ICC
CONDITIONS
TA = +25°C
MIN
TYP
0.68
MAX
0.85
1.0
1.0
1.2
UNITS
μA
Supply Current (Note 2)
Common-Mode Input Range
TA = +25°C
VRS+ = 25V
VCM
Guaranteed by CMRR
2
25
V
CURRENT SENSE AMPLIFIER PARAMETERS
Common-Mode Rejection Ratio
Input Offset Voltage (Note 3)
VOS Hysteresis (Note 4)
CMRR
2V < VRS+ < 25V
TA = +25°C
120
150
±30
dB
μV
µV
±100
±200
VOS
VHYS
TA = +25°C
TS1101-25
TS1101-50
TS1101-100
TS1101-200
TA = +25°C
10
25
50
100
200
±0.2
Gain
G
V/V
±0.6
±1.0
±0.6
±1
13.2
26.4
5
Gain Error (Note 5)
GE
GM
%
%
TA = +25°C
±0.2
Gain Match (Note 5)
Output Resistance (Note 6)
TS1101-25/50/100
TS1101-200
Gain = 25
7.0
14.0
10
20
ROUT
kΩ
Gain = 50
Gain = 100
10
20
OUT Low Voltage
VAOL
mV
Gain = 200
40
OUT High Voltage (Note 7)
Output Settling Time
VAOH
tS
VOH = VRS- - VOUT
TS1101-25/50/100
TS1101-200
0.05
2.2
4.3
0.2
V
ms
ms
1% final value, VOUT = 3V
SIGN COMPARATOR PARAMETERS
VDD Supply Voltage Range
VDD Supply Current
VDD
IDD
1.25
5.5
0.2
V
μA
0.02
VDD = 1.25V, ISINK = 5µA
VDD = 1.8V, ISINK = 35µA
VDD = 1.25V, ISOURCE = 5µA
VDD = 1.8V, ISOURCE = 35µA
VSENSE = ±1mV
Output Low Voltage
Output High Voltage
Propagation Delay
VCOL
VCOH
tPD
0.2
V
V
VDD – 0.2
3
0.4
ms
VSENSE = ±10mV
Note 1: All devices are 100% production tested at TA = +25°C. All temperature limits are guaranteed by product
characterization.
Note 2: Extrapolated to VOUT = 0. ICC is the total current into the RS+ and the RS- pins.
Note 3: Input offset voltage VOS is extrapolated from a VOUT+ measurement with VSENSE set to +1mV and a VOUT- measurement
with VSENSE set to -1mV; vis-a-viz,
ꢁ
ꢀ - V
OꢀT+
ꢂ
V
OꢀT-
Average VOS
=
ꢁ x GAIN
Note 4: Amplitude of VSENSE lower or higher than VOS required to cause the comparator to switch output states.
Note 5: Gain error applies to current flow in either direction and is calculated by applying two values for VSENSE and then
calculating the error of the actual slope vs. the ideal transfer characteristic:
For GAIN = 25, the applied VSENSE is 20mV and 120mV.
For GAIN = 50, the applied VSENSE is 10mV and 60mV.
For GAIN = 100, the applied VSENSE is 5mV and 30mV.
For GAIN = 200, the applied VSENSE is 2.5mV and 15mV.
Note 6: The device is stable for any capacitive load at VOUT
.
Note 7: VOH is the voltage from VRS- to VOUT with VSENSE = 3.6V/GAIN.
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TS1101
TYPICAL PERFORMANCE CHARACTERISTICS
VRS+ = VRS- = 3.6V; TA = +25°C, unless otherwise noted.
Input Offset Voltage Histogram
Gain Error Histogram
35
30
25
20
15
35
30
25
20
15
10
5
10
5
0
0
20
30 40
50 60
-0.6
-0.2
0
0.4 0.6
-10 10
-0.4
0.2
GAIN ERROR - %
INPUT OFFSET VOLTAGE - µV
Input Offset Voltage vs Common-Mode Voltage
Supply Current vs Temperature
40
1
0.8
35
30
25
20
25V
2V
0.6
0.4
3.6V
0.2
0
-40 -15
110
25
SUPPLY VOLTAGE - Volt
10
35
60
85
0
5
10
15
20
30
TEMPERATURE - °C
Supply Current vs Common-Mode Voltage
Input Offset Voltage vs Temperature
80
60
40
1
0.8
0.6
0.4
20
0
0.2
0
-20
-40
-40 -15
110
20
25
10
35
60
85
0
5
10
15
30
SUPPLY VOLTAGE - Volt
TEMPERATURE - °C
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TS1101
TYPICAL PERFORMANCE CHARACTERISTICS
VRS+ = VRS- = 3.6V; TA = +25°C, unless otherwise noted.
Gain Error vs Common-Mode Voltage
Gain Error vs. Temperature
0.4
0.3
0.2
0.1
0
0.3
0.2
0.1
0
-0.1
-0.2
-0.3
0
5
15
20
25
30
-40
-15
60
TEMPERATURE - °C
85
110
10
10
35
SUPPLY VOLTAGE - Volt
VOUT vs VSENSE @ Supply = 3.6V
G = 100
VOUT vs VSENSE @ Supply = 2V
4
3.5
3
2
1.8
1.6
1.4
1.2
G = 100
G = 50
2.5
2
1.0
0.8
0.6
0.4
0.2
0
G = 50
G = 25
1.5
1
G = 25
0.5
0
0
50
100
VSENSE- mV
150
0
20
40
VSENSE- mV
60
80
100
Common-Mode Rejection vs Frequency
Small-Signal Gain vs Frequency
5
0
0
-20
G = 50
G = 50, 100
-5
-40
G = 100
G = 25
-10
-15
-20
-25
-60
G =25
-80
-100
-120
-140
-30
-35
0.001 0.01 0.1
1
10 100 1000
0.001 0.01 0.1
1
10
100 1000
FREQUENCY - kHz
FREQUENCY - kHz
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RTFDS
TS1101
TYPICAL PERFORMANCE CHARACTERISTICS
VRS+ = VRS- = 3.6V; COUT = 0pF; TA = +25°C, unless otherwise noted.
Large-Signal Pulse Response, Gain = 50
Small-Signal Pulse Response, Gain = 50
200µs/DIV
200µs/DIV
Large-Signal Pulse Response, Gain = 25
Small-Signal Pulse Response, Gain = 25
200µs/DIV
200µs/DIV
Large-Signal Pulse Response, Gain = 100
Small-Signal Pulse Response, Gain = 100
200µs/DIV
200µs/DIV
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TS1101
PIN FUNCTIONS
PIN LABEL
FUNCTION
Ground. Connect this pin to analog ground.
Comparator Output, push-pull; SIGN is HIGH for (VRS+ > VRS-) and LOW for (VRS- > VRS+).
Output Voltage. VOUT is proportional to VSENSE = (VRS+ - VRS-) or (VRS- - VRS+).
External Sense Resistor Load-Side Connection
1
2
3
4
5
6
GND
SIGN
OUT
RS-
VDD
RS+
SIGN Comparator External Power Supply Pin; Connect this pin to system’s logic VDD supply.
External Sense Resistor Power-Side Connection
BLOCK DIAGRAM
DESCRIPTION OF OPERATION
The internal configuration of the TS1101 – a
bidirectional high-side, current-sense amplifier – is a
variation of the TS1100 uni-directional current-sense
amplifier. In the design of the TS1101, the input
amplifier was reconfigured for fully differential
input/output operation and a second low-threshold p-
channel FET (M2) was added where the drain
terminal of M2 is also connected to ROUT.
Therefore, the behavior of the TS1101 for when
resistor that is used to measure current. At the non-
inverting input of the TS1101 (the RS- terminal), the
applied voltage is ILOAD x RSENSE. Since the RS-
terminal is the non-inverting input of the internal op
amp, op amp feedback action forces the inverting
input of the internal op amp to the same potential
(ILOAD x RSENSE). Therefore, the voltage drop
across RSENSE (VSENSE = VRS+ - VRS-) and the
voltage drop across RGAINA (at the RS+ terminal)
are equal. Necessary for gain ratio match, both
RGAINA and RGAINB are the same value.
VRS- > VRS+ is identical for when VRS+ > VRS-
.
Referring to the typical application circuit on Page 1,
the inputs of the TS1101’s differential input/output
amplifier are connected across an external RSENSE
Since p-channel M1’s source is connected to the
inverting input of the internal op amp and since the
voltage drop across RGAINA is the same as the
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TS1101
external VSENSE, op amp feedback action drives the
gate of M1 such that M1’s drain-source current is
equal to:
indicates the magnitude of the load current, the
TS1101’s SIGN output indicates the load current’s
direction. The SIGN output is a logic high when M1
is conducting current (VRS+ > VRS-). Alternatively, the
SIGN output is a logic low when M2 is conducting
current (VRS+ < VRS-). The SIGN comparator’s
transfer characteristic is illustrated in Figure 1.
Unlike other current-sense amplifiers that implement
a OUT/SIGN arrangement, the TS1101 exhibits no
“dead zone” at ILOAD switchover.
VSꢅNSꢅ
ꢃIDSꢂM1ꢃ
ꢄ
RGAINA
or
ILOADꢃx RSꢅNSꢅ
IDSꢂM1ꢃ
ꢄ
RGAINA
Since M1’s drain terminal is connected to ROUT, the
output voltage of the TS1101 at the OUT terminal is,
therefore;
ROꢀT
VOꢀTꢃꢄꢃILOADꢃx RSꢅNSꢅꢃxꢃ
RGAINA
When the voltage at the RS- terminal is greater than
the voltage at the RS+ terminal, the external
VSENSE voltage drop is impressed upon RGAINB.
The voltage drop across RGAINB is then converted
into a current by M2 that then produces an output
voltage across ROUT. In this design, when M1 is
conducting current (VRS+ > VRS-ꢃ, the TS1101’s
internal amplifier holds M2 OFF. When M2 is
conducting current (VRS- > VRS+), the internal
amplifier holds M1 OFF. In either case, the disabled
FET does not contribute to the resultant output
voltage.
The current-sense amplifier’s gain accuracy is
therefore the ratio match of ROUT to RGAIN[A/B].
For each of the four gain options available, Table 1
lists the values for ROUT and RGAIN[A/B]. The
TS1101’s output stage is protected against input
overdrive by use of an output current-limiting circuit
of 3mA (typical) and a 7V internal clamp protection
circuit.
Figure 1: TS1101's SIGN Comparator Transfer
Characteristic.
100
10
1
Table 1: Internal Gain Setting Resistors (Typical
Values)
GAIN (V/V) RGAIN[A/B] (Ω) ROUT (Ω) Part Number
25
50
100
200
400
200
100
100
10k
10k
10k
20k
TS1101-25
TS1101-50
TS1101-100
TS1101-200
0.1
The SIGN Comparator Output
0.1
1
10
VSENSE (│VRS+ - VRS-│) - mV
Figure 2: SIGN Comparator Propagation Delay vs VSENSE
100
As shown in the TS1101’s block diagram, the design
of the TS1101 incorporated one additional feature –
an analog comparator the inputs of which monitor
the internal amplifier’s differential output voltage.
While the voltage at the TS1101’s OꢀT terminal
.
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TS1101
The other attribute of the SIGN comparator’s
behavior is its propagation delay as a function of
applied VSENSE [(VRS+ - VRS-) or (VRS- - VRS+)]. As
shown in Figure ꢁ, the SIGN comparator’s
propagation delay behavior is symmetric regardless
of current-flow direction and is inversely proportional
to VSENSE
.
APPLICATIONS INFORMATION
Choosing the Sense Resistor
minimum power supply voltage is higher than 3.6V,
each of the four full-scale VSENSEs above can be
increased.
Selecting the optimal value for the external RSENSE
is based on the following criteria and for each
commentary follows:
3) Total Load Current Accuracy
1) RSENSE Voltage Loss
In
the
TS1101’s
linear
region
where
2) VOUT Swing vs. Applied Input Voltage at VRS+
and Desired VSENSE
3) Total ILOAD Accuracy
4) Circuit Efficiency and Power Dissipation
5) RSENSE Kelvin Connections
VOUT < VOUT(max), there are two specifications related
to the circuit’s accuracy: aꢃ the TS1101’s input offset
voltage (VOS(max) = 100μVꢃ and b) its gain error
(GE(max) = 0.6%). An expression for the TS1101’s
total error is given by:
1) RSENSE Voltage Loss
VOUT = [GAIN x (1 ± GE) x VSENSE] ± (GAIN x VOS)
For lowest IR power dissipation in RSENSE, the
smallest usable resistor value for RSENSE should
be selected.
A large value for RSENSE permits the use of smaller
load currents to be measured more accurately
because the effects of offset voltages are less
significant when compared to larger VSENSE
voltages. Due care though should be exercised as
previously mentioned with large values of RSENSE.
2) VOUT Swing vs. Applied Input Voltage at VRS+
and Desired VSENSE
As there is no separate power supply pin for the
TS1101, the circuit draws its power from the voltage
at its RS+ and RS- terminals. Therefore, the signal
voltage at the OUT terminal is bounded by the
minimum voltage applied at the RS+ terminal.
4) Circuit Efficiency and Power Dissipation
IR losses in RSENSE can be large especially at high
load currents. It is important to select the smallest,
usable RSENSE value to minimize power dissipation
and to keep the physical size of RSENSE small. If
the external RSENSE is allowed to dissipate
significant power, then its inherent temperature
coefficient may alter its design center value, thereby
reducing load current measurement accuracy.
Precisely because the TS1101’s input stage was
designed to exhibit a very low input offset voltage,
small RSENSE values can be used to reduce power
dissipation and minimize local hot spots on the pcb.
Therefore,
VOUT(max) = VRS+(min) - VSENSE(max) – VOH(max)
and
V
OꢀTꢃꢁmaxꢂ
RSꢅNSꢅ
ꢄ
GAIN ꢆ ILOADꢁmaxꢂ
5) RSENSE Kelvin Connections
where the full-scale VSENSE should be less than
VOUT(MAX)/GAIN at the application’s minimum RS+
terminal voltage. For best performance with a 3.6V
power supply, RSENSE should be chosen to
generate a VSENSE of: a) 120mV (for the 25V/V GAIN
option), b) 60mV (for the 50V/V GAIN option), c)
30mV (for the 100V/V GAIN option), or d) 15mV (for
the 200V/V GAIN option) at the full-scale ILOAD
current in each application. For the case where the
For optimal VSENSE accuracy in the presence of large
load currents, parasitic pcb track resistance should
be minimized. Kelvin-sense pcb connections
between RSENSE and the TS1101’s RS+ and RS-
terminals are strongly recommended. The drawing in
Figure 3 illustrates the connections between
TS1101DS r1p0
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RTFDS
TS1101
the current-sense amplifier and the current-sense
resistor. The pcb layout should be balanced and
symmetrical to minimize wiring-induced errors. In
addition, the pcb layout for RSENSE should include
good thermal management techniques for optimal
RSENSE power dissipation.
rectification of noise signals occurs because all
amplifier input stages are constructed with
transistors that can behave as high-frequency signal
detectors in the same way pn-junction diodes were
used as RF envelope detectors in early radio
designs. Against common-mode injected noise, the
amplifier’s internal common-mode rejection is
usually sufficient.
To counter the effects of externally-injected noise, it
has always been good engineering practice to add
external low-pass filters in series with the inputs of a
current-sense amplifier. In the design of discrete
current-sense amplifiers, resistors used in the
external low-pass filters were incorporated into the
circuit’s overall design so errors because of any
input-bias current-generated offset voltage errors
and gain errors were compensated.
Figure 3: Making PCB Connections to RSENSE.
With the advent of monolithic current-sense
amplifiers, like the TS1101, the addition of external
low-pass filters in series with the current-sense
amplifier’s inputs only introduces additional offset
voltage and gain errors. To minimize or eliminate
altogether the need for external low-pass filters and
to maintain low input offset voltage and gain errors,
the TS1101 incorporates a 50-kHz (typ), 2nd-order
differential low-pass filter as shown in the TS1101’s
Block Diagram.
6) RSENSE Composition
Current-shunt resistors are available in metal film,
metal strip, and wire-wound constructions. Wire-
wound current-shunt resistors are constructed with
wire spirally wound onto a core. As a result, these
types of current shunt resistors exhibit the largest
self inductance. In applications where the load
current contains high-frequency transients, metal
film or metal strip current sense resistors are
recommended.
Output Filter Capacitor
If the TS1101 is part of a signal acquisition system
where its OUT terminal is connected to the input of
an ADC with an internal, switched-capacitor track-
and-hold circuit, the internal track-and-hold’s
Internal Noise Filter
In power management and motor control
applications, current-sense amplifiers are required to
measure load currents accurately in the presence of
both externally-generated differential and common-
mode noise. An example of differential-mode noise
that can appear at the inputs of a current-sense
amplifier is high-frequency ripple. High-frequency
ripple – whether injected into the circuit inductively
or capacitively - can produce a differential-mode
voltage drop across the external current-shunt
resistor (RSENSE). An example of externally-
generated, common-mode noise is the high-
frequency output ripple of a switching regulator that
can result in common-mode noise injection into both
inputs of a current-sense amplifier.
sampling capacitor can cause voltage droop at VOUT
.
A 22nF to 100nF good-quality ceramic capacitor
from the OUT terminal to GND forms a low-pass
filter with the TS1101’s ROUT and should be used to
minimize voltage droop (holding VOUT constant
during the sample interval. Using a capacitor on the
OUT terminal will also reduce the TS1101’s small-
signal bandwidth as well as band-limiting amplifier
noise.
PC Board Layout and Power-Supply Bypassing
For optimal circuit performance, the TS1101 should
be in very close proximity to the external current-
sense resistor and the pcb tracks from RSENSE to
the RS+ and the RS- input terminals of the TS1101
should be short and symmetric. Also recommended
are a ground plane and surface mount resistors and
capacitors.
Even though the load current signal bandwidth is
DC, the input stage of any current-sense amplifier
can rectify unwanted, out-of-band noise that can
result in an apparent error voltage at its output. This
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TS1101DS r1p0
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TS1101
PACKAGE OUTLINE DRAWING
6-Pin SOT23 Package Outline Drawing
(N.B., Drawings are not to scale)
Note:
Dimension are exclusive of mold flash and gate burr.
2. Dimension are exclusive of solder plating.
2.80 - 3.00
3. The foot length measuring is based on the gauge plane method.
4. Package is surface to be matte finish VDI 11~13.
5. Dimensions and tolerances are as per ANSI Y14.5M, 1982.
6. This part is compliant with EIAJ specification SC74A and JEDEC MO-178 AB spec.
7. Die is facing up for mold, Die is facing down for trim/form, ie. reverse trim/form.
8. All dimensions are in mm.
0.950
TYP.
0.950
TYP.
0.300(MIN)
0.500(MAX)
10° TYP.
(2 Plcs)
10° TYP.
(2 Plcs)
1.50 – 1.75
0.60 - 0.80
0.50 -0.70
0.09 – 0.127
0.25
0° ~ 8°
Guage
Plane
0.30 - 0.55
10° TYP.
(2 Plcs)
10° TYP.
(2 Plcs)
0.050(MIN)
0.15(MAX)
Information furnished by Touchstone Semiconductor is believed to be accurate and reliable. However, Touchstone Semiconductor does not
assume any responsibility for its use nor for any infringements of patents or other rights of third parties that may result from its use, and all
information provided by Touchstone Semiconductor and its suppliers is provided on an AS IS basis, WITHOUT WARRANTY OF ANY KIND.
Touchstone Semiconductor reserves the right to change product specifications and product descriptions at any time without any advance
notice. No license is granted by implication or otherwise under any patent or patent rights of Touchstone Semiconductor. Touchstone
Semiconductor assumes no liability for applications assistance or customer product design. Customers are responsible for their products and
applications using Touchstone Semiconductor components. To minimize the risk associated with customer products and applications,
customers should provide adequate design and operating safeguards. Trademarks and registered trademarks are the property of their
respective owners.
Touchstone Semiconductor, Inc.
Page 11
630 Alder Drive, Milpitas, CA 95035
+1 (408) 215 - 1220 ▪ www.touchstonesemi.com
TS1101DS r1p0
RTFDS
相关型号：
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This change is considered a minor change which does not affect form, fit, function, quality, or reliability.
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This change is considered a minor change which does not affect form, fit, function, quality, or reliability.
SILICON
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This change is considered a minor change which does not affect form, fit, function, quality, or reliability.
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