TS1102-100EG5 [SILICON]
High Side Bidirectional and Unidirectional Current Sense Amplifier;
| 型号： | TS1102-100EG5 |
| 厂家： | 
SILICON |
| 描述： | High Side Bidirectional and Unidirectional Current Sense Amplifier |
| 文件： | 总20页 (文件大小：1563K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
TS1100/01/02/03 Data Sheet
TS1100/01/02/03 Uni- and Bidirectional Current-Sense Amplifiers
KEY FEATURES
The TS1100/01/02/03 Unidirectional and Bidirectional Current Sense Amplifiers con-
sume a very low 0.68 µA supply current.
• Low Supply Current
• Current Sense Amplifier: 0.68 µA
The TS1100 and TS1101 high-side current sense amplifiers (CSA) combine a 100 µV
(max) input offset voltage (VOS) and a 0.6% (max) gain error (GE), with both specifica-
tions optimized for any precision current measurement.
• I
: 0.02 µA
VDD
• High Side Bidirectional and Unidirectional
Current Sense Amplifier
• Wide CSA Input Common Mode Range: +2
V to +27 V
The TS1102 and TS1103 CSAs combine a 200 µV (max) VOS and a 0.6% (max) GE for
cost-sensitive applications.
• Low CSA Input Offset Voltage: 100 µV
(max) (TS1100 and TS1101 Only)
For all high-side current sensing applications, the TS1100/01/02/03 CSAs are self-pow-
ered and feature a wide input common-mode voltage range from 2 to 27 V.
• Low Gain Error: 0.6% (max)
• Four Gain Options Available:
• 25 V/V
For the bidirectional CSAs, TS1101 and TS1103, a SIGN comparator digital output is
provided that indicates the direction of current flow. All CSAs are specified for operation
over the –40 °C to +105 °C temperature range.
• 50 V/V
• 100 V/V
• 200 V/V
Applications
• 5-Lead and 6-Lead SOT23 Packaging
• Power Management Systems
• Portable/Battery-Powered Systems
• Smart Chargers
• Battery Monitoring
• Overcurrent and Undercurrent Detection
• Remote Sensing
• Industrial Control
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TS1100/01/02/03 Data Sheet
Ordering Information
1. Ordering Information
Ordering Number1
TS1100-25EG5
TS1100-50EG5
TS1100-100EG5
TS1100-200EG5
TS1101-25EG6
TS1101-50EG6
TS1101-100EG6
TS1101-200EG6
TS1102-25EG5
TS1102-50EG5
TS1102-100EG5
TS1102-200EG5
TS1101-25EG6
TS1101-50EG6
TS1101-100EG6
TS1101-200EG6
Part Marking
Description
Gain V/V
25
TADJ
TADK
TADL
TADM
TADN
TADP
TADQ
TADR
TADS
TADT
TADU
TADV
TADW
TADX
TADY
TADZ
50
Unidirectional current sense amplifier (VOS(MAX) = 200 µV)
100
200
25
50
Bidirectional current sense amplifier (VOS(MAX) = 200 µV)
Unidirectional current sense amplifier (VOS(MAX) = 300 µV)
Bidirectional current sense amplifier (VOS(MAX) = 300 µV)
100
200
25
50
100
200
25
50
100
200
Note:
1. Adding the suffix, "T", to the part number (e.g., TS1101-25EG6T) denotes tape and reel.
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TS1100/01/02/03 Data Sheet
System Overview
2. System Overview
2.1 Typical Application Circuits
Figure 2.1. TS1100 and TS1102 Typical Application Circuit
Figure 2.2. TS1101 and TS1103 Typical Application Circuit
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TS1100/01/02/03 Data Sheet
System Overview
2.2 Theory of Operation
The internal configuration of the TS1100/02 (a unidirectional high-side, current-sense amplifier) is based on a common operational am-
plifier circuit used for measuring load currents (in one direction) in the presence of high common-mode voltages. In the general case, a
current-sense amplifier monitors the voltage caused by a load current through an external sense resistor and generates an output volt-
age as a function of that load current.
The internal configuration of the TS1101/03 (a bidirectional high-side, current-sense amplifier) is a variation of the TS1100/02 unidirec-
tional current-sense amplifier. In the design of the TS1101/03, the input amplifier was reconfigured for fully differential input/output oper-
ation and a second low-threshold p-channel FET (M2) was added where the drain terminal of M2 is also connected to ROUT. Therefore,
the behavior of the TS1101/03 for when VRS– > VRS+ is identical for when VRS+ > VRS–
.
Referring to the typical application circuit, the inputs of the op-amp based circuit are connected across an external RSENSE resistor that
is used to measure load current. At the non-inverting input of the current-sense amplifier (the RS+ terminal), the applied voltage is
ILOAD × RSENSE. Since the RS– terminal is the non-inverting input of the internal op-amp, op-amp feedback action forces the inverting
input of the internal op-amp to the same potential. Therefore, the voltage drop across RSENSE (VSENSE) and the voltage drop across
RGAINA (at the RS+ terminal) are equal. Necessary for gain ratio matched, both RGAINA and RGAINB are the same value.
Since p-channel M1’s source is connected to the inverting input of the internal op amp and since the voltage drop across RGAINA is the
same as the external VSENSE, op amp feedback action drives the gate of M1 such that M1’s drain-source current is equal to:
V
SENSE
I
=
DS(M 1)
R
GAINA
or
I
× R
LOAD
SENSE
GAINA
I
=
DS(M 1)
R
Since M1’s drain terminal is connected to ROUT, the output voltage of the current-sense amplifier at the OUT terminal is, therefore:
R
OUT
V
= I
× R
×
OUT
LOAD
SENSE
R
GAINA
For the TS1101 and TS1103, when the voltage at the RS– terminal is greater than the voltage at the RS+ terminal, the external
VSENSE voltage drop is impressed upon RGAINB. The voltage drop across RGAINB is then converted into a current by M2 that then
produces an output voltage across ROUT. In this design, when M1 is conducting current (VRS+ > VRS–), the TS1101/03’s internal amplifi-
er holds M2 OFF. When M2 is conducting current (VRS– > VRS+), the internal amplifier holds M1 OFF. In either case, the disabled FET
does not contribute to the resultant output voltage.
The current-sense amplifier’s gain accuracy is therefore the ratio match of ROUT to RGAIN[A/B]. For each of the four gain options availa-
ble, Table 1 lists the values for ROUT and RGAIN[A/B]. The TS1101’s output stage is protected against input overdrive by use of an output
current-limiting circuit of 3 mA (typical) and a 7 V internal clamp protection circuit.
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TS1100/01/02/03 Data Sheet
System Overview
2.3 SIGN Comparator Output
As shown in the TS1101/03’s block diagram, the design of the TS1101/03 incorporated one additional feature: an analog comparator
whose inputs monitor the internal amplifier’s differential output voltage. While the voltage at the TS1101/03’s OUT terminal indicates the
magnitude of the load current, the TS1101/03’s SIGN output indicates the load current’s direction. The SIGN output is a logic high when
M1 is conducting current (VRS+ > VRS–). Alternatively, the SIGN output is a logic low when M2 is conducting current (VRS+ < VRS–). The
SIGN comparator’s transfer characteristic is illustrated in the figure below. Unlike other current-sense amplifiers that implement a OUT/
SIGN arrangement, the TS1101/03 exhibits no “dead zone” at ILOAD switchover. The other attribute of the SIGN comparator’s behavior
is its propagation delay as a function of applied VSENSE [(VRS+ – VRS–) or (VRS– – VRS+)]. As shown below, the SIGN comparator’s
propagation delay behavior is symmetric regardless of current-flow direction and is inversely proportional to VSENSE
.
Figure 2.3. SIGN Comparator Transfer Characteristic and Propagation Delay
Figure 2.4. SIGN Comparator Propagation Delay vs. VSENSE
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TS1100/01/02/03 Data Sheet
System Overview
2.4 Choosing the Sense Resistor
Selecting the optimal value for the external RSENSE is based on the following criteria and for each commentary follows:
1. RSENSE Voltage Loss
2. VOUT Swing vs. Applied Input Voltage at VRS+ and Desired VSENSE
3. Total ILOAD Accuracy
4. Circuit Efficiency and Power Dissipation
5. RSENSE Kelvin Connections
2.4.1 RSENSE Voltage Loss
For the lowest IR power dissipation in RSENSE, the smallest usable resistor value for RSENSE should be selected.
2.4.2 VOUT Swing vs. Applied Input Voltage at VRS+ and Desired VSENSE
As there is no separate power supply pin for the current-sense amplifiers, the circuit draws its power from the voltage at its RS+ and
RS- terminals. Therefore, the signal voltage at the OUT terminal is bounded by the minimum voltage applied at the RS+ terminal.
Therefore:
V
= V
− V
− V
SENSE(max ) OH (max )
OUT (max )
RS+(min )
and
V
OUT (max )
R
<
SENSE
GAIN × I
LOAD(max )
where the full-scale VSENSE should be less than VOUT(MAX)/GAIN at the application’s minimum RS+ terminal voltage. For best perform-
ance with a 3.6 V power supply, RSENSE should be chosen to generate a VSENSE of: a) 120 mV (for the 25 V/V GAIN option), b) 60 mV
(for the 50 V/V GAIN option), c) 30 mV (for the 100 V/V GAIN option), or d) 15 mV (for the 200 V/V GAIN option) at the full-scale ILOAD
current in each application. For the case where the minimum power supply voltage is higher than 3.6 V, each of the four full-scale
VSENSEs above can be increased.
2.4.3 Total Load Current Accuracy
In the current-sense amplifiers’ linear region where VOUT < VOUT(max), there are two specifications related to the circuit’s accuracy: a)
the input offset voltage and b) gain error (GE(max) = 0.6%). An expression for the current sense amplifiers’ total error is given by:
V
= GAIN × 1 ± GE × V
± GAIN × V
SENSE OS
(
)
(
)
OUT
A large value for RSENSE permits the use of smaller load currents to be measured more accurately because the effects of offset voltag-
es are less significant when compared to larger VSENSE voltages. Due care though should be exercised as previously mentioned with
large values of RSENSE
.
2.4.4 Circuit Efficiency and Power Dissipation
IR losses in RSENSE can be large especially at high load currents. It is important to select the smallest, usable RSENSE value to mini-
mize power dissipation and to keep the physical size of RSENSE small. If the external RSENSE is allowed to dissipate significant power,
then its inherent temperature coefficient may alter its design center value, thereby reducing load current measurement accuracy. Pre-
cisely because the current-sense amplifiers input stages were designed to exhibit a very low input offset voltage, small RSENSE values
can be used to reduce power dissipation and minimize local hot spots on the PCB.
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TS1100/01/02/03 Data Sheet
System Overview
2.4.5 RSENSE Kelvin Connections
For optimal VSENSE accuracy in the presence of large load currents, parasitic PCB track resistance should be minimized. Kelvin-sense
PCB connections between RSENSE and the current-sense amplifier’s RS+ and RS– terminals are strongly recommended. The drawing
below illustrates the connections between the current-sense amplifier and the current-sense resistor. The PCB layout should be bal-
anced and symmetrical to minimize wiring-induced errors. In addition, the pcb layout for RSENSE should include good thermal manage-
ment techniques for optimal RSENSE power dissipation.
Figure 2.5. Making PCB Connections to RSENSE
2.4.6 RSENSE Composition
Current-shunt resistors are available in metal film, metal strip, and wire-wound constructions. Wire-wound current-shunt resistors con-
sist of a wire spirally wound onto a core. As a result, these types of current shunt resistors exhibit the largest self inductance. In applica-
tions where the load current contains high-frequency transients, metal film or metal strip current-sense resistors are recommended.
2.4.7 Internal Noise Filter
In power management and motor control applications, current-sense amplifiers are required to measure load currents accurately in the
presence of both externally-generated differential and common-mode noise. An example of differential-mode noise that can appear at
the inputs of a current-sense amplifier is high-frequency ripple. High-frequency ripple (whether introduced into the circuit inductively or
capacitively) can produce a differential-mode voltage drop across the external current-shunt resistor (RSENSE). An example of external-
ly-generated, common-mode noise is the high-frequency output ripple of a switching regulator that can result in the injection of com-
mon-mode noise into both inputs of a current-sense amplifier.
Even though the load current signal bandwidth is dc, the input stage of any current-sense amplifier can rectify unwanted out-of-band
noise that can result in an apparent error voltage at its output. This rectification of noise signals occurs because all amplifier input
stages are constructed with transistors that can behave as high-frequency signal detectors in the same way P–N junction diodes were
used as RF envelope detectors in early radio designs. The amplifier’s internal common-mode rejection is usually sufficient to defeat
injected common-mode noise.
To counter the effects of externally-injected noise, it has always been good engineering practice to add external low-pass filters in ser-
ies with the inputs of a current-sense amplifier. In the design of discrete current-sense amplifiers, resistors used in the external low-
pass filters were incorporated into the circuit’s overall design to compensate for any input-bias-current-generated offset voltage and
gain errors.
With the advent of monolithic current-sense amplifiers, the addition of external low-pass filters in series with the current-sense amplifi-
er’s inputs only introduces additional offset voltage and gain errors. To minimize or altogether eliminate the need for external low-pass
filters and to maintain low input offset voltage and gain errors, the current-sense amplifiers incorporate a 50 kHz (typ) 2nd-order differ-
ential low-pass filter as shown in the Block Diagrams.
2.4.8 Output Filter Capacitor
If the current-sense amplifiers are a part of a signal acquisition system in which their OUT terminal is connected to the input of an ADC
with an internal, switched-capacitor track-and-hold circuit, the internal track-and-hold’s sampling capacitor can cause voltage droop at
VOUT. A good-quality 22 to 100 nF ceramic capacitor from the OUT terminal to GND forms a low-pass filter with the current-sense am-
plifier’s ROUT and should be used to minimize voltage droop (holding VOUT constant during the sample interval. Using a capacitor on
the OUT terminal will also reduce the small-signal bandwidth as well as band-limiting amplifier noise.
2.4.9 PC Board Layout and Power Supply Bypassing
For optimal circuit performance, the current-sense amplifiers should be in very close proximity to the external current-sense resistor,
and the PCB tracks from RSENSE to the RS+ and the RS– input terminals should be short and symmetric. Also recommended are a
ground plane and surface mount resistors and capacitors.
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TS1100/01/02/03 Data Sheet
Electrical Characteristics
3. Electrical Characteristics
Table 3.1. Recommended Operating Conditions1
Parameter
Symbol
Conditions
Min
Typ
Max
Units
System Specifications
Operating Voltage Range
Common-Mode Input Range
Note:
VDD
VCM
1.25
2
5.5
27
V
V
VRS+, Guaranteed by CMRR
1. All devices 100% production tested at TA = +25 °C. Limits over Temperature are guaranteed by design and characterization.
Table 3.2. DC Characteristics1
Parameter
Symbol
Conditions
Min
Typ
Max
Units
System Specifications
No Load Input Supply Current
2
TA = +25 °C
—
—
—
—
—
0.68
—
0.85
1.0
1.0
1.2
0.2
µA
IRS+ + IRS–
VRS+ = 25 V
TA = +25 °C
—
—
IVDD
0.02
Current Sense Amplifier
Common Mode Rejection Ratio
CMRR
VOS
2 V < VRS+ < 27 V
120
—
130
±30
—
—
dB
µV
Input Offset Voltage3
TS1100 and
TS1101
TA = +25 °C
–40 °C < TA < +85 °C
TA = +25 °C
±100
±200
±200
±300
—
—
TS1102 and
TS1103
—
±30
—
–40 °C < TA < + 85 °C
TA = +25 °C
—
VOS Hysteresis4
Gain
VHYS
G
—
10
µV
TS1100,
TS1101,
TS1102,
TS1103
TS110x-25
TS110x-50
—
—
25
50
—
—
V/V
TS110x-100
TS110x-200
TA = +25 °C
—
100
200
±0.1
—
—
—
Gain Error5
GE
GM
—
±0.6
±1
%
%
–40 °C < TA < +85 °C
TA = +25 °C
—
Gain Match5
—
±0.2
±0.6
±1
%
–40 °C < TA < +85 °C
TS110x-25/50/100
TS110x-200
—
%
Output Resistance6
ROUT
28.0
14.0
40.0
20.0
52
kΩ
26.4
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TS1100/01/02/03 Data Sheet
Electrical Characteristics
Parameter
OUT Low Voltage
Symbol
Conditions
Gain = 25
Min
—
—
—
—
—
—
—
—
—
Typ
—
Max
5
Units
VAOL
TS1100 and
TS1101
mV
Gain = 50
Gain = 100
Gain = 200
Gain = 25
Gain = 50
Gain = 100
Gain = 200
—
10
20
40
7.5
15
30
60
0.2
—
—
TS1102 and
TS1103
—
—
—
—
OUT High Voltage
VAOH
VOH = VRS– – VOUT
0.05
V
V
V
Sign Comparator Parameters (TS1106 Only)
Output Low Voltage
Output High Voltage
Notes:
VCOL
VDD = 1.25 V, ISINK = 5 µA
VDD = 1.8 V, ISINK = 35 µA
VDD = 1.25 V, ISOURCE = 5 µA
VDD = 1.8 V, ISOURCE = 35 µA
—
—
0.2
—
—
—
VCOH
VDD – 0.2
—
—
1. VRS+ = 3.6 V; VSENSE = (VRS+ – VRS–) = 0 V; COUT = 47 nF; VDD = 1.8 V; TA = –40 °C to +105 °C, unless otherwise noted.
Typical values are at TA = +25 °C.
2. Extrapolated to VOUT=0V. IRS++IRS- is the total current into the RS+ and the RS– pins.
3. Input offset voltage VOS is extrapolated from a VOUT(+) measurement with VSENSE set to +1 mV and a VOUT(–) measurement with
VSENSE set to -1mV; vis-a-viz, Average VOS = (VOUT(–) – VOUT(+))/(2 x GAIN).
4. Amplitude of VSENSE lower or higher than VOS required to cause the comparator to switch output states.
5. Gain error is calculated by applying two values for VSENSE and then calculating the error of the actual slope vs. the ideal transfer
characteristic. TS1100 and TS1102 only applies positive VSENSE values.
For GAIN = 25, the applied VSENSE is 20 mV and 120 mV.
For GAIN = 50, the applied VSENSE is 10 mV and 60 mV.
For GAIN = 100, the applied VSENSE is 5 mV and 30 mV.
For GAIN = 200, the applied VSENSE is 2.5 mV and 15 mV.
6. The device is stable for any capacitance load at VOUT
.
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TS1100/01/02/03 Data Sheet
Electrical Characteristics
Table 3.3. AC Characteristics1
Conditions
Parameter
Symbol
Min
Typ
Max
Units
Current Sense Amplifier
Output Settling time
tOUT_s
1% Final value,
VOUT = 3 V
Gain = 25, 50, 100
Gain = 200
—
—
2.2
4.3
—
—
msec
msec
Sign Comparator Parameters (TS1101 and TS1103 Only)
Propagation Delay
tSIGN_PD
VSENSE = ±1 mV
VSENSE = ±10 mV
—
—
3
—
—
msec
msec
0.4
Notes:
1. VRS+ = 3.6 V; VSENSE = (VRS+ – VRS–) = 0 V; COUT = 47 nF; VDD = 1.8 V; TA = –40 °C to +105 °C, unless otherwise noted.
Typical values are at TA = +25 °C.
Table 3.4. Thermal Conditions
Parameter
Symbol
Conditions
Min
Typ
Max
Units
Operating Temperature Range
TOP
–40
—
+105
°C
Table 3.5. Absolute Maximum Limits
Parameter
RS+ Voltage
Symbol
Conditions
Min
Typ
Max
27
27
6
Units
VRS+
VRS–
–0.3
–0.3
–0.3
–0.3
–0.3
—
—
—
—
—
—
—
—
—
—
—
—
—
V
V
V
V
V
V
RS– Voltage
Supply Voltage
VDD
OUT Voltage
VOUT
6
SIGN Voltage (TS1106 Only)
RS+ to RS– Voltage
VSIGN
6
VRS+ – VRS–
28
Short Circuit Duration: OUT to GND
Continuous Input Current (Any Pin)
Junction Temperature
Storage Temperature Range
Lead Temperature (Soldering, 10 s)
Soldering Temperature (Reflow)
ESD Tolerance
—
Continuous
20
–20
—
mA
°C
°C
°C
°C
150
–65
—
150
300
—
260
Human Body Model
—
—
—
—
2000
200
V
V
Machine Model
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TS1100/01/02/03 Data Sheet
Electrical Characteristics
For the following graphs, VRS+ = VRS– = 3.6 V; TA = +25 C unless otherwise noted.
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TS1100/01/02/03 Data Sheet
Electrical Characteristics
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TS1100/01/02/03 Data Sheet
Electrical Characteristics
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TS1100/01/02/03 Data Sheet
Pin Descriptions
4. Pin Descriptions
Table 4.1. Pin Descriptions
Pin
Part Number
TS1100
TS1101
TS1102
TS1103
TS1100
TS1102
TS1101
TS1103
TS1100
TS1101
TS1102
TS1103
TS1100
TS1101
TS1102
TS1103
TS1100
TS1102
TS1101
TS1103
TS1100
TS1102
TS1101
TS1103
Label
Function
1
GND
Ground. Connect this pin to analog ground.
2
3
4
5
6
GND
SIGN
OUT
Ground. Connect this pin to analog ground.
Comparator Output, push-pull; SIGN is HIGH for (VRS+ > VRS–) and LOW for (VRS– > VRS+).
Output Voltage. VOUT is proportional to VSENSE = (VRS+ – VRS–) or (VRS– – VRS+).
RS–
External Sense Resistor Load-Side Connection
RS+
VDD
N/A
External Sense Resistor Power-Side Connection
SIGN Comparator External Power Supply Pin; Connect this pin to system’s logic VDD supply.
N/A
RS+
External Sense Resistor Power-Side Connection
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TS1100/01/02/03 Data Sheet
Packaging
5. Packaging
5.1 TS1100 and TS1102 Package Dimensions
Figure 5.1. TS1100 and TS1102 Package Diagram
Table 5.1. TS1100 and TS1102 Package Dimensions
Dimension
Min
Max
1.45
0.15
1.30
0.50
0.20
A
A1
A2
b
—
0.00
0.90
0.30
c
0.09
D
2.90 BSC
2.80 BSC
1.60 BSC
0.95 BSC
1.90 BSC
0.30
E
E1
e
e1
L
0.60
8°
L2
θ
0.25 BSC
0°
aaa
bbb
ccc
ddd
0.15
0.20
0.10
0.20
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TS1100/01/02/03 Data Sheet
Packaging
Dimension
Min
Max
Note:
1. All dimensions shown are in millimeters (mm) unless otherwise noted.
2. Dimensioning and Tolerancing per ANSI Y14.5M-1994.
3. Recommended card reflow profile is per the JEDEC/IPC J-STD-020D specification for Small Body Components.
4. This drawing conforms to the JEDEC Solid State Outline MO-178, Variation AA.
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TS1100/01/02/03 Data Sheet
Packaging
5.2 TS1101 and TS1103 Package Dimensions
Figure 5.2. TS1101 and TS1103 Package Diagram
Table 5.2. TS1101 and TS1103 Package Dimensions
Dimension
Min
Max
0.15
1.30
0.50
A1
A2
b
0.06
1.00
0.35
c
0.127
D
2.80
2.90
3.00
1.70
E
2.60
E1
e1
L
1.50
0.950 TYP
0.35
0.55
3°
L2
θ1
θ2
0.20 BSC
0°
10° TYP
Note:
1. All dimensions shown are in millimeters (mm) unless otherwise noted.
2. Dimensioning and Tolerancing per ANSI Y14.5M-1994.
3. Recommended card reflow profile is per the JEDEC/IPC J-STD-020D specification for Small Body Components.
4. This drawing conforms to the JEDEC Solid State Outline MO-178, Variation AA.
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TS1100/01/02/03 Data Sheet
Top and Bottom Marking: 5 and 6-Pin Packages
6. Top and Bottom Marking: 5 and 6-Pin Packages
Mark Method:
Font Size:
Laser
0.60 mm (24 mils)
Device Identifier
Line 1 Mark Format:
TADT
Manufacturing Code from the Assembly Pur-
chase Order Form
Line 5 Backside:
TTTT = Mfg Code
Mark Method:
Font Size:
Laser
0.60 mm (24 mils)
Device Identifier
Line 1 Mark Format:
TADT
Manufacturing Code from the Assembly Pur-
chase Order Form
Line 5 Backside:
TTTT = Mfg Code
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Rev. 1.0 | 17
Table of Contents
1. Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
2. System Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
2.1 Typical Application Circuits . . . . . . . . . . . . . . . . . . . . . . . . . 2
2.2 Theory of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
2.3 SIGN Comparator Output . . . . . . . . . . . . . . . . . . . . . . . . . . 4
2.4 Choosing the Sense Resistor. . . . . . . . . . . . . . . . . . . . . . . . . 5
2.4.1 R
2.4.2 V
Voltage Loss. . . . . . . . . . . . . . . . . . . . . . . . . . . 5
SENSE
Swing vs. Applied Input Voltage at V
and Desired V
. . . . . . . . . . . 5
SENSE
OUT
RS+
2.4.3 Total Load Current Accuracy . . . . . . . . . . . . . . . . . . . . . . . . 5
2.4.4 Circuit Efficiency and Power Dissipation . . . . . . . . . . . . . . . . . . . . 5
2.4.5 R
2.4.6 R
Kelvin Connections . . . . . . . . . . . . . . . . . . . . . . . . 6
Composition . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
SENSE
SENSE
2.4.7 Internal Noise Filter . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
2.4.8 Output Filter Capacitor . . . . . . . . . . . . . . . . . . . . . . . . . . 6
2.4.9 PC Board Layout and Power Supply Bypassing . . . . . . . . . . . . . . . . . . 6
3. Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
4. Pin Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
5. Packaging . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
5.1 TS1100 and TS1102 Package Dimensions . . . . . . . . . . . . . . . . . . . .14
5.2 TS1101 and TS1103 Package Dimensions . . . . . . . . . . . . . . . . . . . .16
6. Top and Bottom Marking: 5 and 6-Pin Packages . . . . . . . . . . . . . . . . . 17
Table of Contents 18
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using or intending to use the Silicon Laboratories products. Characterization data, available modules and peripherals, memory sizes and memory addresses refer to each specific
device, and "Typical" parameters provided can and do vary in different applications. Application examples described herein are for illustrative purposes only. Silicon Laboratories
reserves the right to make changes without further notice and limitation to product information, specifications, and descriptions herein, and does not give warranties as to the accuracy
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