TC55V8512J-15 [TOSHIBA]
TOSHIBA MOS DIGITAL INTEGRATED CIRCUIT SILICON GATE CMOS; 东芝MOS数字集成电路硅栅CMOS
| 型号： | TC55V8512J-15 |
| 厂家： | 
TOSHIBA |
| 描述： | TOSHIBA MOS DIGITAL INTEGRATED CIRCUIT SILICON GATE CMOS |
| 文件： | 总10页 (文件大小：163K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
TC55V8512J/FT-12,-15
TOSHIBA MOS DIGITAL INTEGRATED CIRCUIT SILICON GATE CMOS
524,288-WORD BY 8-BIT CMOS STATIC RAM
DESCRIPTION
The TC55V8512J/FT is a 4,194,304-bit high-speed static random access memory (SRAM) organized as 524,288
words by 8 bits. Fabricated using CMOS technology and advanced circuit techniques to provide high speed, it
operates from a single 3.3 V power supply. Chip enable (CE ) can be used to place the device in a low-power mode,
and output enable ( OE ) provides fast memory access. This device is well suited to cache memory applications
where high-speed access and high-speed storage are required. All inputs and outputs are directly LVTTL
compatible. The TC55V8512J/FT is available in plastic 36-pin SOJ and 44-pin TSOP with 400mil width for high
density surface assembly.
FEATURES
•
•
•
•
•
Single power supply voltage of 3.3 V 0.3 V
Fully static operation
•
Fast access time (the following are maximum values)
TC55V8512J/FT-12:12 ns
All inputs and outputs are LVTTL compatible
Output buffer control using OE
Package:
TC55V8512J/FT-15:15 ns
•
Low-power dissipation
(the following are maximum values)
SOJ36-P-400-1.27 (J)
(Weight: 1.35 g typ)
(Weight: 0.45 g typ)
Cycle Time
12
15
20
25
ns
TSOP II44-P-400-0.80 (FT)
Operation (max) 170 140 130 110 mA
Standby:4 mA (both devices)
PIN ASSIGNMENT (TOP VIEW)
36 PIN SOJ 44 PIN TSOP
PIN NAMES
A0 to A18
Address Inputs
NC
NC
A17
A3
1
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
NC
NC
NC
A4
A5
A6
A7
2
I/O1 to I/O8 Data Inputs/Outputs
3
4
CE
WE
OE
Chip Enable Input
Write Enable Input
Output Enable Input
Power (+3.3 V)
Ground
A17
1
2
3
4
5
6
7
8
9
36 NC
35 A4
34 A5
33 A6
32 A7
A2
5
A3
A2
A1
A0
A1
A0
6
7
8
CE
I/O1
I/O2
VDD
GND
I/O3
I/O4
OE
9
I/O8
I/O7
GND
VDD
I/O6
I/O5
A8
31
10
11
12
13
14
15
16
17
18
19
20
21
22
CE
OE
I/O1
30 I/O8
29 I/O7
28 GND
27 VDD
26 I/O6
25 I/O5
24 A8
V
DD
I/O2
VDD
GND
NC
GND 10
I/O3 11
I/O4 12
WE
A16
A15
A14
A13
A18
NC
No Connection
Not Usable (Input)
A9
13
A10
A11
A12
NU
WE
NU
A16 14
A15 15
A14 16
A13 17
A18 18
23 A9
22 A10
21 A11
20 A12
19 NU
NC
NC
NC
(TC55V8512J)
(TC55V8512FT)
2001-12-19 1/10
TC55V8512J/FT-12,-15
BLOCK DIAGRAM
A0
A1
A4
A8
A9
A12
A14
A15
A16
A17
V
DD
GND
MEMORY CELL ARRAY
512 × 1,024 × 8
(4,194,304)
CE
I/O1
I/O2
I/O3
I/O4
I/O5
I/O5
I/O7
I/O8
SENSE AMP
COLUMN DECODER
CE
COLUMN ADDRESS BUFFER
CLOCK
GENERATOR
A2 A3 A5 A6 A7 A10 A11A13 A18
WE
OE
CE
CE
MAXIMUM RATINGS
SYMBOL
RATING
VALUE
UNIT
V
V
V
P
Power Supply Voltage
−0.5 to 4.6
V
V
DD
IN
Input Terminal Voltage
Input/Output Terminal Voltage
Power Dissipation
−0.5* to 4.6
−0.5* to V
+ 0.5**
DD
V
I/O
D
1.4
W
°C
°C
°C
T
T
T
Soldering Temperature (10s)
Storage Temperature
260
solder
stg
opr
−65 to 150
−10 to 85
Operating Temperature
*: −1.5 V with a pulse width of 20%･t
min (4 ns max)
RC
**: V
+ 1.5 V with a pulse width of 20%･t
min (4 ns max)
RC
DD
DC RECOMMENDED OPERATING CONDITIONS (Ta = 0° to 70°C)
SYMBOL
PARAMETER
Power Supply Voltage
MIN
TYP
MAX
3.6
UNIT
V
V
V
3.0
2.0
3.3
V
V
V
DD
Input High Voltage
Input Low Voltage
V
+ 0.3**
DD
IH
IL
−0.3*
0.8
*: −1.0 V with a pulse width of 20%･t
min (4 ns max)
RC
**: V
+ 1.0 V with a pulse width of 20%･t
min (4 ns max)
RC
DD
2001-12-19 2/10
TC55V8512J/FT-12,-15
DC CHARACTERISTICS (Ta = 0° to 70°C, V = 3.3 V 0.3 V)
DD
SYMBOL
PARAMETER
TEST CONDITION
MIN
TYP MAX UNIT
Input Leakage Current
(Except NU pin)
I
I
V
= 0 to V
DD
−1
1
1
µA
µA
IL
IN
Output Leakage
Current
CE = V or WE = V or OE = V
,
IH
IL
IH
−1
LO
V
V
V
= 0 to V
OUT
DD
= 0 to 0.8 V
= 0 to 0.2 V
= −2 mA
−1
−1
20
1
IN
IN
Input Current
(NU pin)
I
µA
I (NU)
I
I
I
I
2.4
OH
OH
OL
OL
V
V
Output High Voltage
Output Low Voltage
OH
OL
= −100 µA
= 2 mA
V
− 0.2
DD
V
0.4
0.2
170
140
130
110
50
= 100 µA
t
t
t
t
= 12 ns
= 15 ns
= 20 ns
= 25 ns
cycle
cycle
cycle
cycle
CE = V , I
= 0 mA,
IL OUT
I
Operating Current
Standby Current
mA
mA
OE = V
,
DDO
IH
Other Input = V /V
IH IL
I
I
CE = V , Other Input = V or V
DDS1
DDS2
IH
IH
IL
CE = V
− 0.2 V, Other Input = V − 0.2 V or 0.2 V
4
DD
DD
CAPACITANCE (Ta = 25°C, f = 1 .0 MHz)
SYMBOL
PARAMETER
Input Capacitance
Input/Output Capacitance
TEST CONDITION
MAX
UNIT
C
C
V
V
= GND
6
8
pF
pF
IN
IN
= GND
I/O
I/O
Note: This parameter is periodically sampled and is not 100% tested.
OPERATING MODE
MODE
CE
OE
WE
I/O1 to I/O8
POWER
Read
Write
L
L
L
*
H
L
Output
Input
I
I
I
DDO
DDO
DDO
Outputs Disable
Standby
L
H
*
H
*
High Impedance
High Impedance
H
I
DDS
* : Don’t care
Note: The NU pin must be left unconnected or tied to GND or a voltage level of less than 0.8 V.
You must not apply a voltage of more than 0.8 V to the NU.
2001-12-19 3/10
TC55V8512J/FT-12,-15
(See Note 1)
AC CHARACTERISTICS (Ta = 0° to 70°C
, V = 3.3 V 0.3 V)
DD
READ CYCLE
TC55V8512J/FT
SYMBOL
PARAMETER
UNIT
-12
-15
MIN
MAX
MIN
15
4
MAX
15
15
8
t
t
t
t
t
t
t
t
t
Read Cycle Time
12
3
12
12
6
RC
Address Access Time
ACC
CO
Chip Enable Access Time
Output Enable Access Time
OE
ns
Output Data Hold Time from Address Change
Output Enable Time from Chip Enable
Output Enable Time from Output Enable
Output Disable Time from Chip Enable
Output Disable Time from Output Enable
7
8
OH
3
4
COE
OEE
COD
ODO
1
1
7
8
WRITE CYCLE
TC55V8512J/FT
SYMBOL
PARAMETER
UNIT
-12
-15
MIN
12
8
MAX
MIN
15
9
MAX
8
t
t
t
t
t
t
t
t
t
t
Write Cycle Time
7
WC
WP
CW
AW
Write Pulse Width
Chip Enable to End of Write
Address Valid to End of Write
Address Setup Time
10
10
0
12
12
0
AS
ns
Write Recovery Time
0
0
WR
DS
Data Setup Time
7
8
Data Hold Time
0
0
DH
Output Enable Time from Write Enable
Output Disable Time from Write Enable
1
1
OEW
ODW
AC TEST CONDITIONS
Fig.1
3.3 V
PARAMETER
TEST CONDITION
1200 Ω
870 Ω
Z
= 50 Ω
Input Pulse Level
3.0 V/ 0.0 V
2 ns
0
I/O pin
I/O pin
Input Pulse Rise and Fall Time
R
= 50 Ω
L
Input Timing Measurement
Reference Level
C
L
= 30 pF
C = 5 pF
L
1.5 V
V
= 1.5 V
L
(For t
, t
, t
and t
,
COE OEE COD
Output Timing Measurement
Reference Level
1.5 V
Fig.1
t
, t
)
ODO OEW
ODW
Output Load
2001-12-19 4/10
TC55V8512J/FT-12,-15
TIMING DIAGRAMS
(See Note 2)
READ CYCLE
t
RC
Address
CE
t
t
OH
ACC
t
CO
(See Note 6)
t
OE
t
COD
OE
(See Note 6)
(See Note 6)
t
OEE
t
ODO
(See Note 6)
t
COE
D
Hi-Z
VALID DATA OUT
Hi-Z
INDETERMINATE
OUT
INDETERMINATE
(See Note 5)
WE
WRITE CYCLE 1 (
CONTROLLED)
t
WC
t
AW
Address
WE
t
t
t
WR
AS
WP
t
CW
CE
(See Note 6)
(See Note 6)
t
t
OEW
ODW
D
OUT
(See Note 3)
INDETERMINATE
Hi-Z
(See Note 4)
INDETERMINATE
t
t
DH
DS
D
IN
VALID DATA IN
2001-12-19 5/10
TC55V8512J/FT-12,-15
(See Note 5)
CE
WRITE CYCLE 2 (
CONTROLLED)
t
WC
t
AW
Address
WE
t
t
t
WR
AS
WP
t
CW
CE
(See Note 6)
t
ODW
(See Note 6)
t
COE
D
OUT
Hi-Z
Hi-Z
INDETERMINATE
t
t
DH
DS
D
IN
VALID DATA IN
2001-12-19 6/10
TC55V8512J/FT-12,-15
Note:
(1)
Operating temperature (Ta) is guaranteed for transverse air flow exceeding 400 linear feet per minute.
WE remains HIGH for the Read Cycle.
(2)
(3)
(4)
If CE goes LOW coincident with or after WE goes LOW, the outputs will remain at high impedance.
If CE goes HIGH coincident with or before WE goes HIGH, the outputs will remain at high
impedance.
(5)
(6)
If OE is HIGH during the write cycle, the outputs will remain at high impedance.
The parameters specified below are measured using the load shown in Fig.1.
･････････････････
(A)
(B)
t
, t
, t
, t
Output Enable Time
Output Disable Time
COE OEE OEW
････････････････
t
, t
COD ODO ODW
CE , OE
WE
(A)
(B)
0.2 V
Hi-Z
0.2 V
0.2 V
0.2 V
D
OUT
Hi-Z
VALID DATA OUT
INDETERMINATE
INDETERMINATE
2001-12-19 7/10
TC55V8512J/FT-12,-15
PACKAGE DIMENSIONS
Weight: 1.35 g (typ)
2001-12-19 8/10
TC55V8512J/FT-12,-15
PACKAGE DIMENSIONS
Weight: 0.45 g (typ)
2001-12-19 9/10
TC55V8512J/FT-12,-15
RESTRICTIONS ON PRODUCT USE
000707EBA
• TOSHIBA is continually working to improve the quality and reliability of its products. Nevertheless, semiconductor
devices in general can malfunction or fail due to their inherent electrical sensitivity and vulnerability to physical
stress. It is the responsibility of the buyer, when utilizing TOSHIBA products, to comply with the standards of
safety in making a safe design for the entire system, and to avoid situations in which a malfunction or failure of
such TOSHIBA products could cause loss of human life, bodily injury or damage to property.
In developing your designs, please ensure that TOSHIBA products are used within specified operating ranges as
set forth in the most recent TOSHIBA products specifications. Also, please keep in mind the precautions and
conditions set forth in the “Handling Guide for Semiconductor Devices,” or “TOSHIBA Semiconductor Reliability
Handbook” etc..
• The TOSHIBA products listed in this document are intended for usage in general electronics applications
(computer, personal equipment, office equipment, measuring equipment, industrial robotics, domestic appliances,
etc.). These TOSHIBA products are neither intended nor warranted for usage in equipment that requires
extraordinarily high quality and/or reliability or a malfunction or failure of which may cause loss of human life or
bodily injury (“Unintended Usage”). Unintended Usage include atomic energy control instruments, airplane or
spaceship instruments, transportation instruments, traffic signal instruments, combustion control instruments,
medical instruments, all types of safety devices, etc.. Unintended Usage of TOSHIBA products listed in this
document shall be made at the customer’s own risk.
• The products described in this document are subject to the foreign exchange and foreign trade laws.
• The information contained herein is presented only as a guide for the applications of our products. No
responsibility is assumed by TOSHIBA CORPORATION for any infringements of intellectual property or other
rights of the third parties which may result from its use. No license is granted by implication or otherwise under
any intellectual property or other rights of TOSHIBA CORPORATION or others.
• The information contained herein is subject to change without notice.
2001-12-19 10/10
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