TC55VBM316AFTN [TOSHIBA]
TENTATIVE TOSHIBA MOS DIGITAL INTEGRATED CIRCUIT SILICON GATE CMOS; 暂定东芝MOS数字集成电路硅栅CMOS
| 型号： | TC55VBM316AFTN |
| 厂家： | 
TOSHIBA |
| 描述： | TENTATIVE TOSHIBA MOS DIGITAL INTEGRATED CIRCUIT SILICON GATE CMOS |
| 文件： | 总15页 (文件大小：217K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
TC55VBM316AFTN/ASTN40,55
TENTATIVE TOSHIBA MOS DIGITAL INTEGRATED CIRCUIT SILICON GATE CMOS
524,288-WORD BY 16-BIT/1,048,576-WORD BY 8-BIT FULL CMOS STATIC RAM
DESCRIPTION
The TC55VBM316AFTN/ASTN is a 8,388,608-bit static random access memory (SRAM) organized as 524,288
words by 16 bits/1,048,576 words by 8 bits. Fabricated using Toshiba's CMOS Silicon gate process technology, this
device operates from a single 2.3 to 3.6 V power supply. Advanced circuit technology provides both high speed and
low power at an operating current of 3 mA/MHz and a minimum cycle time of 40 ns. It is automatically placed in
low-power mode at 0.7 µA standby current (at VDD = 3 V, Ta = 25°C, typical) when chip enable (CE1 ) is asserted
high or (CE2) is asserted low. There are three control inputs. CE1 and CE2 are used to select the device and for
data retention control, and output enable (OE ) provides fast memory access. Data byte control pin ( LB , UB )
provides lower and upper byte access. This device is well suited to various microprocessor system applications
where high speed, low power and battery backup are required. And, with a guaranteed operating extreme
temperature range of −40° to 85°C, the TC55VBM316AFTN/ASTN can be used in environments exhibiting extreme
temperature conditions. The TC55VBM316AFTN/ASTN is available in a plastic 48-pin thin-small-outline package
(TSOP).
FEATURES
•
Access Times (maximum):
TC55VBM316AFTN/ASTN
•
Low-power dissipation
Operating: 9 mW/MHz (typical)
•
•
•
•
•
•
Single power supply voltage of 2.3 to 3.6 V
Power down features usingCE1 and CE2
Data retention supply voltage of 1.5 to 3.6 V
Direct TTL compatibility for all inputs and outputs
Wide operating temperature range of −40° to 85°C
Standby Current (maximum):
40
55
Access Time
40 ns
40 ns
40 ns
25 ns
55 ns
55 ns
55 ns
30 ns
CE1 Access Time
CE2 Access Time
OE Access Time
3.6 V
10 µA
3.0 V
5 µA
•
Package:
TSOPⅠ48-P-1220-0.50 (AFTN) (Weight:0.51 g typ)
TSOPⅠ48-P-1214-0.50 (ASTN) (Weight:0.36 g typ)
PIN ASSIGNMENT (TOP VIEW)
PIN NAMES
48 PIN TSOP
A0~A18
A-1~A18
CE1 , CE2
R/W
Address Inputs (Word Mode)
Address Inputs (Byte Mode)
Chip Enable
1
48
25
Read/Write Control
Output Enable
OE
LB , UB
Data Byte Control
I/O1~I/O16 Data Inputs/Outputs
24
BYTE
Byte (×8 mode) Enable
Power
(Normal)
V
DD
GND
NC
Ground
No Connection
Option
OP*
*: OP pin must be open or connected to GND.
Pin No.
Pin Name
Pin No.
1
2
3
4
5
6
7
8
9
10
NC R/W CE2 OP
26 27 28 29
CE1 GND OE
42 43 44
11
12
13
14
UB
30
15
LB
31
16
A18
32
A15 A14 A13 A12 A11 A10
A9
23
A2
39
A8
24
A1
40
NC
25
A0
41
17
A17
33
18
A7
34
19
A6
35
20
A5
36
21
A4
37
22
A3
38
Pin Name
Pin No.
I/O1 I/O9 I/O2 I/O10
45
46
47
48
I/O16
/A-1
Pin Name
I/O3 I/O11 I/O4 I/O12
V
I/O5 I/O13 I/O6 I/O14 I/O7 I/O15 I/O8
GND
A16
BYTE
DD
2002-08-05 1/15
TC55VBM316AFTN/ASTN40,55
BLOCK DIAGRAM
CE
A6
A7
V
DD
A8
GND
A9
A10
A11
A12
A13
A14
A15
A17
A18
MEMORY CELL ARRAY
4,096 × 128 × 16
(8,388,608)
I/O1
I/O2
I/O3
I/O4
I/O5
I/O6
I/O7
I/O8
SENSE AMP
I/O9
I/O10
I/O11
I/O12
I/O13
I/O14
I/O15
I/O16
COLUMN ADDRESS
DECODER
COLUMN ADDRESS
REGISTER
COLUMN ADDRESS
BUFFER
CLOCK
GENERATOR
CE
A-1
A1
A3
A5
A0
A2
A4
A16
CE1
CE2
CE
LB
UB
R/W
OE
BYTE
2002-08-05 2/15
TC55VBM316AFTN/ASTN40,55
OPERATING MODE
MODE
CE1 CE2 OE R/W BYTE LB UB
I/O1~I/O8
Output
I/O9~I/O15
High-Z
I/O16
POWER
L
L
L
L
L
L
L
L
L
L
L
L
H
*
H
H
H
H
H
H
H
H
H
H
H
H
*
L
L
L
L
*
H
H
H
H
L
L
*
L
H
L
*
*
L
L
H
*
A-1
I
I
I
I
I
I
I
I
I
I
I
I
DDO
DDO
DDO
DDO
DDO
DDO
DDO
DDO
DDO
DDO
DDO
DDO
H
Output
High-Z
Output
Input
Output
Output
High-Z
High-Z
Input
Output
Output
High-Z
A-1
Read
H
H
L
*
L
H
L
H
L
*
L
L
H
*
Input
Input
Write
*
L
H
High-Z
Input
Input
Input
*
L
H
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
A-1
H
H
H
H
*
H
H
H
H
*
L
H
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
L
H
L
*
L
L
H
*
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
Output Deselect
Standby
H
H
H or L
H or L
H
I
I
I
DDS
DDS
DDS
L
*
*
*
*
*
*
*
*
H
H
* = don't care
H = logic high
L = logic low
MAXIMUM RATINGS
SYMBOL
RATING
VALUE
UNIT
V
V
V
V
P
Power Supply Voltage
Input Voltage
−0.3~4.2
DD
IN
−0.3*~4.2
V
Input/Output Voltage
Power Dissipation
−0.5~V
+ 0.5
V
I/O
D
DD
0.6
W
T
T
T
Soldering Temperature (10s)
Storage Temperature
260
°C
°C
°C
solder
stg
opr
−55~150
−40~85
Operating Temperature
*: −2.0 V when measured at a pulse width of 20ns
DC RECOMMENDED OPERATING CONDITIONS (Ta = −40° to 85°C)
SYMBOL
PARAMETER
Power Supply Voltage
MIN
TYP
MAX
3.6
UNIT
V
V
V
2.3
2.0
DD
V
V
= 2.3 V~2.7 V
= 2.7 V~3.6 V
DD
DD
Input High Voltage
V
+ 0.3
DD
V
IH
2.2
V
V
Input Low Voltage
−0.3*
1.5
V
× 0.24
DD
V
V
IL
Data Retention Supply Voltage
3.6
DH
*: −2.0 V when measured at a pulse width of 20ns
2002-08-05 3/15
TC55VBM316AFTN/ASTN40,55
DC CHARACTERISTICS (Ta = −40° to 85°C, V = 2.3 to 3.6 V)
DD
SYMBOL
PARAMETER
TEST CONDITION
MIN TYP MAX UNIT
Input Leakage
Current
I
V
= 0 V~V
1.0
µA
IL
IN
DD
I
I
Output High Current
Output Low Current
V
V
= V − 0.5 V
DD
−0.5
mA
mA
OH
OL
OH
OL
= 0.4 V
2.1
Output Leakage
Current
CE1 = V or CE2 = V or LB = UB = V or
IH IL IH
I
1.0
35
8
µA
LO
R/W = V or OE = V , V
= 0 V~V
IL
IH OUT
DD
CE1 = V and CE2 = V and
IL
IH
MIN
1 µs
MIN
1 µs
R/W = V , LB = UB = V ,
IH
IL
l
l
t
t
mA
DDO1
cycle
cycle
I
= 0 mA,
OUT
Other Input = V /V
IH IL
Operating Current
CE1 = 0.2 V and CE2 = V
− 0.2 V and
DD
30
3
R/W = V
− 0.2 V, LB = UB = 0.2 V,
DD
mA
mA
DDO2
I
= 0 mA,
OUT
Other Input = V
− 0.2 V/0.2 V
DD
1) CE1 = V or CE2 = V (at BYTE ≥ V − 0.2 V or ≤ 0.2 V)
DD
IH
IL
I
1
10
2
DDS1
2) LB = UB = V (at BYTE ≥ V
− 0.2 V)
IH
DD
V
=
1) CE1 = V
− 0.2 V, CE2 =
DD
DD
Ta = −40~85°C
Ta = 25°C
3.3 V 0.3 V
V
− 0.2 V (at BYTE ≥ V
DD
DD
− 0.2 V or ≤ 0.2 V)
Standby Current
0.7
2) CE2 = 0.2 V (at BYTE ≥ V
− 0.2 V or ≤ 0.2 V)
DD
I
µA
DDS2
V
= 3.0 V
Ta = −40~40°C
Ta = −40~85°C
DD
3) LB
=
UB = V
− 0.2 V,
DD
CE1 = 0.2 V, CE2 = V
− 0.2
DD
5
V (at BYTE ≥ V
− 0.2 V)
DD
CAPACITANCE (Ta = 25°C, f = 1 MHz)
SYMBOL
PARAMETER
Input Capacitance
Output Capacitance
TEST CONDITION
MAX
UNIT
C
C
V
V
= GND
10
10
pF
pF
IN
OUT
IN
= GND
OUT
Note: This parameter is periodically sampled and is not 100% tested.
2002-08-05 4/15
TC55VBM316AFTN/ASTN40,55
AC CHARACTERISTICS AND OPERATING CONDITIONS
(Ta = −40° to 85°C, V = 2.7 to 3.6 V)
DD
READ CYCLE
TC55VBM316AFTN/ASTN
40 55
SYMBOL
PARAMETER
UNIT
MIN
MAX
MIN
MAX
t
t
t
t
t
t
t
t
t
t
t
t
t
Read Cycle Time
40
5
40
40
40
25
40
20
20
20
55
5
55
55
55
30
55
25
25
25
RC
Address Access Time
ACC
CO1
CO2
OE
Chip Enable( CE1 ) Access Time
Chip Enable(CE2) Access Time
Output Enable Access Time
Data Byte Control Access Time
Chip Enable Low to Output Active
Output Enable Low to Output Active
Data Byte Control Low to Output Active
Chip Enable High to Output High-Z
Output Enable High to Output High-Z
Data Byte Control High to Output High-Z
Output Data Hold Time
BA
ns
COE
OEE
BE
0
0
5
5
10
10
OD
ODO
BD
OH
WRITE CYCLE
TC55VBM316AFTN/ASTN
40 55
SYMBOL
PARAMETER
UNIT
MIN
MAX
MIN
MAX
t
t
t
t
t
t
t
t
t
t
Write Cycle Time
Write Pulse Width
40
30
35
35
0
20
55
40
45
45
0
25
WC
WP
CW
BW
AS
Chip Enable to End of Write
Data Byte Control to End of Write
Address Setup Time
ns
Write Recovery Time
0
0
WR
ODW
OEW
DS
R/W Low to Output High-Z
R/W High to Output Active
Data Setup Time
0
0
20
0
25
0
Data Hold Time
DH
Note:
t
, t
, t
and t
are specified in time when an output becomes high impedance, and are not judged depending on
ODW
OD ODO BD
an output voltage level.
2002-08-05 5/15
TC55VBM316AFTN/ASTN40,55
AC CHARACTERISTICS AND OPERATING CONDITIONS
(Ta = −40° to 85°C, V = 2.3 to 3.6 V)
DD
READ CYCLE
TC55VBM316AFTN/ASTN
40 55
SYMBOL
PARAMETER
UNIT
MIN
MAX
MIN
MAX
t
t
t
t
t
t
t
t
t
t
t
t
t
Read Cycle Time
55
5
55
55
55
30
55
25
25
25
70
5
70
70
70
35
70
30
30
30
RC
Address Access Time
ACC
CO1
CO2
OE
Chip Enable( CE1 ) Access Time
Chip Enable(CE2) Access Time
Output Enable Access Time
Data Byte Control Access Time
Chip Enable Low to Output Active
Output Enable Low to Output Active
Data Byte Control Low to Output Active
Chip Enable High to Output High-Z
Output Enable High to Output High-Z
Data Byte Control High to Output High-Z
Output Data Hold Time
BA
ns
COE
OEE
BE
0
0
5
5
10
10
OD
ODO
BD
OH
WRITE CYCLE
TC55VBM316AFTN/ASTN
40 55
SYMBOL
PARAMETER
UNIT
MIN
MAX
MIN
MAX
t
t
t
t
t
t
t
t
t
t
Write Cycle Time
Write Pulse Width
55
40
45
45
0
25
70
50
55
55
0
30
WC
WP
CW
BW
AS
Chip Enable to End of Write
Data Byte Control to End of Write
Address Setup Time
ns
Write Recovery Time
0
0
WR
ODW
OEW
DS
R/W Low to Output High-Z
R/W High to Output Active
Data Setup Time
0
0
25
0
30
0
Data Hold Time
DH
Note:
t
, t
, t
and t
are specified in time when an output becomes high impedance, and are not judged depending on
ODW
OD ODO BD
an output voltage level.
2002-08-05 6/15
TC55VBM316AFTN/ASTN40,55
AC TEST CONDITIONS
PARAMETER
TEST CONDITION
Input pulse level
t , t
0.2 V, V
× 0.7 V + 0.2 V
DD
1V / ns(Fig.1)
R
F
Timing measurements
Reference level
Output load
V
V
× 0.5
× 0.5
DD
DD
30 pF + 1 TTL Gate(Fig.2)
Fig.1 : Input rise and fall time
Fig.2 : Output load
V
TM
V
Typ
R1
R2
DD
90%
90%
10%
Dout
10%
1 V/ns
GND
R1 = 810 Ω
R2 = 1610 Ω
1 V/ns
t
t
F
R
30 pF
V
= 2.3 V
TM
BYTE
FUNCTION
SYMBOL
PARAMETER
MIN
MAX
UNIT
t
t
BYTE Setup Time
5
5
ms
ms
BS
BR
BYTE Recovery Time
TIMING DIAGRAMS
BYTE
CE2
CE1
t
t
BR
BS
BYTE
2002-08-05 7/15
TC55VBM316AFTN/ASTN40,55
(See Note 1)
READ CYCLE
t
RC
Address
A0~A18 (Word Mode)
A-1~A18 (Byte Mode)
t
t
OH
ACC
t
CO1
CE1
CE2
t
CO2
t
t
OD
OE
OE
t
t
ODO
BA
UB , LB
t
t
BE
BD
t
OEE
D
OUT
I/O1~16 (Word Mode)
Hi-Z
VALID DATA OUT
Hi-Z
I/O1~8 (Byte Mode)
t
COE
(See Note 4)
WRITE CYCLE 1 (R/W CONTROLLED)
t
WC
Address
A0~A18 (Word Mode)
A-1~A18 (Byte Mode)
t
t
t
WR
AS
WP
R/W
CE1
t
t
t
CW
CW
BW
CE2
UB , LB
t
t
OEW
ODW
D
OUT
I/O1~16 (Word Mode)
I/O1~8 (Byte Mode)
(See Note 2)
Hi-Z
(See Note 3)
(See Note 5)
t
t
DH
DS
D
IN
I/O1~16 (Word Mode)
(See Note 5)
VALID DATA IN
I/O1~8 (Byte Mode)
2002-08-05 8/15
TC55VBM316AFTN/ASTN40,55
(See Note 4)
CE1
WRITE CYCLE 2 (
CONTROLLED)
t
WC
Address
A0~A18 (Word Mode)
A-1~A18 (Byte Mode)
t
t
t
WR
AS
WP
R/W
CE1
t
t
CW
CW
CE2
t
BW
UB , LB
t
t
ODW
BE
D
OUT
I/O1~16 (Word Mode)
Hi-Z
Hi-Z
t
COE
I/O1~8 (Byte Mode)
t
t
DH
DS
D
IN
I/O1~16 (Word Mode)
I/O1~8 (Byte Mode)
VALID DATA IN
(See Note 5)
(See Note 4)
WRITE CYCLE 3 (CE2 CONTROLLED)
t
WC
Address
A0~A18 (Word Mode)
A-1~A18 (Byte Mode)
t
t
t
WR
AS
WP
R/W
CE1
t
t
CW
CW
CE2
t
BW
UB , LB
t
t
ODW
BE
D
OUT
I/O1~16 (Word Mode)
I/O1~8 (Byte Mode)
Hi-Z
Hi-Z
t
COE
t
t
DH
DS
D
IN
I/O1~16 (Word Mode)
(See Note 5)
VALID DATA IN
I/O1~8 (Byte Mode)
2002-08-05 9/15
TC55VBM316AFTN/ASTN40,55
(See Note 4)
UB LB
CONTROLLED)
WRITE CYCLE 4 (
,
t
WC
Address
A0~A18 (Word Mode)
t
t
t
WR
AS
WP
R/W
CE1
t
t
CW
CW
CE2
t
BW
UB , LB
t
t
ODW
BE
D
OUT
I/O1~16 (Word Mode)
Hi-Z
Hi-Z
t
COE
t
t
DH
DS
D
IN
(See Note 5)
VALID DATA IN
I/O1~16 (Word Mode)
Note:
(1)
(2)
R/W remains HIGH for the read cycle.
If CE1 (or UB or LB ) goes LOW(or CE2 goes HIGH) coincident with or after R/W goes LOW, the
outputs will remain at high impedance.
(3)
If CE1 (or UB or LB ) goes HIGH(or CE2 goes LOW) coincident with or before R/W goes HIGH, the
outputs will remain at high impedance.
(4)
(5)
If OE is HIGH during the write cycle, the outputs will remain at high impedance.
Because I/O signals may be in the output state at this time, input signals of reverse polarity must not be
applied.
2002-08-05 10/15
TC55VBM316AFTN/ASTN40,55
DATA RETENTION CHARACTERISTICS (Ta = −40° to 85°C)
SYMBOL
PARAMETER
MIN
TYP
MAX
UNIT
V
V
I
Data Retention Supply Voltage
1.5
0
3.6
10
2
DH
V
= 3.6 V Ta = −40~85°C
DH
DH
Standby Current
µA
Ta = −40~40°C
= 3.0 V
DDS2
V
Ta = −40~85°C
5
t
t
Chip Deselect to Data Retention Mode Time
Recovery Time
ns
CDR
R
5
ms
(See Note 1)
CE1
CONTROLLED DATA RETENTION MODE
V
DD
V
DATA RETENTION MODE
DD
2.3 V
(See Note 2)
(See Note 2)
V
IH
t
t
R
CDR
V
− 0.2 V
DD
CE1
GND
(See Note 3)
CE2 CONTROLLED DATA RETENTION MODE
V
DD
V
DATA RETENTION MODE
DD
2.3 V
CE2
V
IH
t
t
R
CDR
V
IL
0.2 V
GND
(See Note 4)
UB LB
,
CONTROLLED DATA RETENTION MODE
V
DD
V
DATA RETENTION MODE
DD
2.3 V
(See Note 5)
(See Note 5)
V
IH
t
t
R
CDR
V
− 0.2 V
DD
UB , LB
GND
2002-08-05 11/15
TC55VBM316AFTN/ASTN40,55
Note:
(1)
In CE1 controlled data retention mode, minimum standby current mode is entered when CE2 ≤ 0.2 V or
CE2 ≥ V
DD
− 0.2 V.
(2)
When CE1 is operating at the V (min.) level, the operating current is given by I
IH
during the
DDS1
transition of V
DD
from 2.3(2.7) to 2.2V(2.4 V).
(3)
(4)
In CE2 controlled data retention mode, minimum standby current mode is entered when CE2 ≤ 0.2 V.
In UB (or LB ) controlled data retention mode, minimum standby current mode is entered when CE1
≤ 0.2 V or CE1 ≥ V
DD
− 0.2 V, CE2 ≤ 0.2 V or CE2 ≥ V
− 0.2 V.
DD
(5)
When UB (or LB ) is operating at the V (min.) level, the operating current is given by I
IH
during
DDS1
the transition of V
DD
from 2.3(2.7) to 2.2V(2.4 V).
2002-08-05 12/15
TC55VBM316AFTN/ASTN40,55
PACKAGE DIMENSIONS
TSOPⅠ48-P-1220-0.50
Unit:mm
1
48
24
25
18.4 0.1
20.0 0.2
1.0 0.1
1.2max
0.1 0.05
0.5 0.1
Weight:0.51 g (typ)
2002-08-05 13/15
TC55VBM316AFTN/ASTN40,55
PACKAGE DIMENSIONS
TSOPⅠ48-P-1214-0.50
Unit:mm
1
48
24
25
12.4 0.1
14.0 0.2
1.0 0.1
1.2max
0.1 0.05
0.5 0.1
Weight:0.36 g (typ)
2002-08-05 14/15
TC55VBM316AFTN/ASTN40,55
RESTRICTIONS ON PRODUCT USE
000707EBA
• TOSHIBA is continually working to improve the quality and reliability of its products. Nevertheless, semiconductor
devices in general can malfunction or fail due to their inherent electrical sensitivity and vulnerability to physical
stress. It is the responsibility of the buyer, when utilizing TOSHIBA products, to comply with the standards of
safety in making a safe design for the entire system, and to avoid situations in which a malfunction or failure of
such TOSHIBA products could cause loss of human life, bodily injury or damage to property.
In developing your designs, please ensure that TOSHIBA products are used within specified operating ranges as
set forth in the most recent TOSHIBA products specifications. Also, please keep in mind the precautions and
conditions set forth in the “Handling Guide for Semiconductor Devices,” or “TOSHIBA Semiconductor Reliability
Handbook” etc..
• The TOSHIBA products listed in this document are intended for usage in general electronics applications
(computer, personal equipment, office equipment, measuring equipment, industrial robotics, domestic appliances,
etc.). These TOSHIBA products are neither intended nor warranted for usage in equipment that requires
extraordinarily high quality and/or reliability or a malfunction or failure of which may cause loss of human life or
bodily injury (“Unintended Usage”). Unintended Usage include atomic energy control instruments, airplane or
spaceship instruments, transportation instruments, traffic signal instruments, combustion control instruments,
medical instruments, all types of safety devices, etc.. Unintended Usage of TOSHIBA products listed in this
document shall be made at the customer’s own risk.
• The products described in this document are subject to the foreign exchange and foreign trade laws.
• The information contained herein is presented only as a guide for the applications of our products. No
responsibility is assumed by TOSHIBA CORPORATION for any infringements of intellectual property or other
rights of the third parties which may result from its use. No license is granted by implication or otherwise under
any intellectual property or other rights of TOSHIBA CORPORATION or others.
• The information contained herein is subject to change without notice.
2002-08-05 15/15
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