TC51WKM516AXGN70 [TOSHIBA]
IC 2M X 16 PSEUDO STATIC RAM, 70 ns, PBGA48, 6 X 7 MM, 0.75 MM PITCH, PLASTIC, TFBGA-48, Static RAM;
| 型号： | TC51WKM516AXGN70 |
| 厂家： | 
TOSHIBA |
| 描述： | IC 2M X 16 PSEUDO STATIC RAM, 70 ns, PBGA48, 6 X 7 MM, 0.75 MM PITCH, PLASTIC, TFBGA-48, Static RAM |
| 文件： | 总11页 (文件大小：196K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
TC51WKM516AXGN65,70
TENTATIVE TOSHIBA MOS DIGITAL INTEGRATED CIRCUIT SILICON GATE CMOS
2,097,152-WORD BY 16-BIT CMOS PSEUDO STATIC RAM
DESCRIPTION
The TC51WKM516AXGN is a 33,554,432-bit pseudo static random access memory(PSRAM) organized as
2,097,152 words by 16 bits. Using Toshiba’s CMOS technology and advanced circuit techniques, it provides high
density, high speed and low power. The device uses dual power supplies(2.6 to 3.1 V for core and 1.7 to 2.2 V for
output buffer). The device also features SRAM-like W/R timing whereby the device is controlled by CE1 , OE , and
WE on asynchronous. The device has the page access operation. Page size is 8 words. The device also supports
deep power-down mode, realizing low-power standby.
•
Access Times:
FEATURES
•
•
Organized as 2,097,152 words by 16 bits
Dual power supplies(2.6 to 3.1 V for core and
1.7 to 2.2 V for output buffer)
TC51WKM516AXGN
65
70
•
•
•
Direct TTL compatibility for all inputs and outputs
Deep power-down mode: Memory cell data invalid
Page operation mode:
Access Time
CE1 Access Time
OE Access Time
Page Access Time
Package:
65 ns
65 ns
25 ns
30 ns
70 ns
70 ns
25 ns
30 ns
Page read operation by 8 words
•
•
Logic compatible with SRAM R/W ( WE ) pin
Standby current
Standby
70 µA
5 µA
•
Deep power-down standby
P-TFBGA48-6mm × 7mm 0.75mm pitch
typ.)
PIN ASSIGNMENT (TOP VIEW)
PIN NAMES
1
2
3
4
5
6
A0 to A20
A0 to A2
Address Inputs
Page Address Inputs
A
B
C
D
E
F
LB
OE
UB
A0
A3
A5
A1
A4
A2
CE2
I/O1
I/O3
I/O1 to I/O16 Data Inputs/Outputs
I/O9
CE1
I/O2
I/O4
I/O5
I/O6
CE1
CE2
Chip Enable Input
Chip select Input
I/O10 I/O11
A6
V
I/O12 A17
I/O13 NC
A7
V
DD
SS
WE
Write Enable Input
Output Enable Input
Data Byte Control Inputs
Power Supply for Core
Power Supply for Output Buffer
Ground
V
A16
A15
A13
A10
V
DDQ
SS
OE
I/O15 I/O14 A14
I/O7
LB , UB
G
H
I/O16 A19
A18 A8
A12
A9
WE I/O8
A11 A20
V
DD
V
DDQ
(FBGA48)
GND
NC
No Connection
2002-03-05 1/11
TC51WKM516AXGN65,70
BLOCK DIAGRAM
CE
A9
A10
A11
A12
A13
A14
A15
A16
A17
A18
A19
A20
V
DD
GND
MEMORY CELL ARRAY
4,096 × 512 × 16
(33,554,432)
I/O1
I/O2
I/O3
I/O4
I/O5
I/O6
I/O7
I/O8
SENSE AMP
I/O9
I/O10
I/O11
I/O12
I/O13
I/O14
I/O15
I/O16
COLUMN ADDRESS
DECODER
COLUMN ADDRESS
BUFFER
REFRESH
ADDRESS
COUNTER
REFRESH
CONTROL
A0 A1 A2 A3 A4 A5 A6 A7 A8
CONTROL SIGNAL
GENERATOR
CE
WE
OE
UB
LB
CE1
CE
CE2
OPERATION MODE
MODE
CE1
CE2
OE
WE
LB
UB
Add
I/O1 to I/O8
I/O9 to I/O16
POWER
Read(Word)
L
L
L
L
L
L
L
H
H
H
H
H
H
H
H
H
H
L
L
L
H
H
H
L
L
L
L
H
L
X
X
X
X
X
X
X
X
X
D
D
D
I
I
I
I
I
I
I
OUT
OUT
DDO
DDO
DDO
DDO
DDO
DDO
DDO
Read(Lower Byte)
Read(Upper Byte)
Write(Word)
High-Z
OUT
L
H
L
High-Z
D
OUT
X
X
X
H
X
X
L
D
D
D
IN
IN
IN
Write(Lower Byte)
Write(Upper Byte)
Outputs Disabled
Standby
L
L
H
L
Invalid
L
H
X
X
X
Invalid
High-Z
High-Z
High-Z
D
IN
H
X
X
X
X
X
High-Z
High-Z
High-Z
I
DDS
Deep Power-down Standby
I
DDSD
Notes: L = Low-level Input(V ), H = High-level Input(V ), X = V or V , High-Z = High-impedance
IL
IH
IH
IL
2002-03-05 2/11
TC51WKM516AXGN65,70
ABSOLUTE MAXIMUM RATINGS (See Note 1)
SYMBOL
RATING
VALUE
UNIT
V
V
V
V
Power Supply Voltage
−1.0 to 3.6
V
V
DD
Output Buffer Power Supply Voltage
Input Voltage for Address and Control Pins
Input/Output Voltage for I/O Pins
Operating Temperature
−1.0 to V
+ 0.5 (3.6 V Max)
DD
DDQ
IN
−1.0 to 3.6
V
−1.0 to V
+ 0.5
V
I/O
DDQ
T
T
T
−25 to 85
°C
°C
°C
W
mA
opr.
strg.
solder
Storage Temperature
−55 to 150
Soldering Temperature (10 s)
Power Dissipation
260
0.6
50
P
D
I
Short Circuit Output Current
OUT
DC RECOMMENDED OPERATING CONDITIONS (Ta = −25°C to 85°C)
SYMBOL
PARAMETER
Power Supply Voltage
MIN
TYP.
MAX
UNIT
V
V
2.6
1.7
2.75
1.8
3.1
2.2
DD
Output Buffer Power Supply Voltage
Input High Voltage for Address and Control Pins
Input High Voltage for I/O Pins
Input Low Voltage
DDQ
IH
1.6
V
+ 0.3*
DD
V
V
1.6
V
+ 0.3*
DDQ
V
V
−0.3*
2.6
0.4
3.1
+1.0 V with 10 ns pulse width
IL
Data Retention Supply Voltage
DH
* : V (Max) V +1.0 V/ V
IH
DD
DDQ
V (Min) -1.0 V with 10 ns pulse width
IL
DC CHARACTERISTICS (Ta = −25°C to 85°C, V = 2.6 to 3.1 V, V
= 1.7 to 2.2 V)
DD
DDQ
(See Note 3 to 4)
SYMBOL
PARAMETER
TEST CONDITION
= 0 V to V
MIN
TYP. MAX UNIT
I
Input Leakage Current
Output Leakage Current
Output High Voltage
Output Low Voltage
V
−1.0
−1.0
− 0.2
+1.0
+1.0
µA
µA
V
IL
IN
DD
I
Output disable, V
= 0 V to V
OUT DD
LO
V
V
I
I
= − 100 µA
= 100 µA
V
OH
OL
OH
OL
DDQ
0.2
V
CE1 = V
IL
I
I
Operating Current
t
t
= min
= min
40
25
mA
mA
DDO1
DDO2
RC
PC
CE2 = V , I
= 0 mA
IH OUT
CE1 = V , CE2 = V
,
IH
IL
Page Access Operating Current
Standby Current(MOS)
Page add. cycling, I
= 0 mA
OUT
I
I
CE1 = V
− 0.2 V, CE2 = V − 0.2 V
DD
70
5
µA
µA
DDS
DD
Deep Power-down Standby Current CE2 = 0.2 V
DDSD
CAPACITANCE (Ta = 25°C, f = 1 MHz)
SYMBOL
PARAMETER
TEST CONDITION
= GND
MAX
UNIT
C
C
Input Capacitance
Output Capacitance
V
10
10
pF
pF
IN
IN
V
OUT
= GND
OUT
Note: This parameter is sampled periodically and is not 100% tested.
2002-03-05 3/11
TC51WKM516AXGN65,70
AC CHARACTERISTICS AND OPERATING CONDITIONS
(Ta = −25°C to 85°C, V = 2.6 to 3.1 V, V = 1.7 to 2.2 V) (See Note 5 to 11)
DD
DDQ
TC51WKM516AXGN
SYMBOL
PARAMETER
UNIT
65
70
MIN
65
10
0
MAX
10000
65
MIN
70
10
0
MAX
10000
70
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
Read Cycle Time
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
µs
ms
ns
µs
RC
Address Access Time
ACC
CO
Chip Enable ( CE1 ) Access Time
Output Enable Access Time
65
70
25
25
OE
Data Byte Control Access Time
Chip Enable Low to Output Active
Output Enable Low to Output Active
Data Byte Control Low to Output Active
Chip Enable High to Output High-Z
Output Enable High to Output High-Z
25
25
BA
COE
OEE
BE
0
0
10
65
30
10
65
50
60
60
0
20
10
70
30
10
70
50
60
60
0
20
OD
20
20
ODO
BD
Data Byte Control High to Output High-Z
Output Data Hold Time
Page Mode Time
20
20
OH
10000
10000
PM
Page Mode Cycle Time
Page Mode Address Access Time
Page Mode Output Data Hold Time
Write Cycle Time
PC
30
30
AA
AOH
WC
WP
CW
BW
AS
10000
10000
Write Pulse Width
Chip Enable to End of Write
Data Byte Control to End of Write
Address Set-up Time
Write Recovery Time
0
0
WR
ODW
OEW
DS
WE Low to Output High-Z
WE High to Output Active
Data Set-up Time
0
20
0
20
30
0
30
0
Data Hold Time
DH
CE2 Set-up Time
0
0
CS
CE2 Hold Time
300
10
0
300
10
0
CH
CE2 Pulse Width
DPD
CHC
CHP
CE2 Hold from CE1
CE2 Hold from Power On
30
30
AC TEST CONDITIONS
PARAMETER
CONDITION
Output load
30 pF + 1 TTL Gate
− 0.2 V, 0.2 V
Input pulse level
Timing measurements
Reference level
V
DD
V
× 0.5
× 0.5
DD
V
DD
t , t
R
5 ns
F
2002-03-05 4/11
TC51WKM516AXGN65,70
TIMING DIAGRAMS
READ CYCLE
t
RC
Address
A0 to A20
t
t
ACC
OH
t
CO
CE1
Fix-H
CE2
OE
t
t
OD
OE
t
ODO
WE
t
BA
UB , LB
t
BE
t
BD
t
OEE
D
OUT
Hi-Z
VALID DATA OUT
Hi-Z
t
COE
I/O1 to I/O16
INDETERMINATE
PAGE READ CYCLE (8 words access)
t
PM
Address
A0 to A2
t
t
t
t
PC
RC
PC
PC
Address
A3 to A20
CE1
Fix-H
CE2
OE
WE
UB , LB
t
t
OD
OE
D
t
BD
t
BA
t
t
t
AOH
AOH
AOH
t
t
OEE
OH
t
BE
D
OUT
D
OUT
D
OUT
D
Hi-Z
Hi-Z
OUT
OUT
I/O1 to I/O16
t
COE
t
t
t
t
t
ODO
CO
AA
AA
AA
t
ACC
* Maximum 8 words
2002-03-05 5/11
TC51WKM516AXGN65,70
(See Note 8)
WE
WRITE CYCLE 1 (
CONTROLLED)
t
WC
Address
A0 to A20
t
t
t
WR
AS
WP
WE
t
t
CW
CE1
t
CH
CE2
BW
UB , LB
t
t
OEW
ODW
D
OUT
(See Note 10)
Hi-Z
(See Note 11)
(See Note 9)
I/O1 to I/O16
t
t
DH
DS
D
IN
(See Note 9)
VALID DATA IN
I/O1 to I/O16
(See Note 8)
CE
WRITE CYCLE 2 (
CONTROLLED)
t
WC
Address
A0 to A20
t
t
t
WR
AS
WP
WE
t
CW
CE1
t
CH
CE2
t
BW
UB , LB
t
t
ODW
BE
D
OUT
Hi-Z
Hi-Z
I/O1 to I/O16
t
COE
t
t
DH
DS
D
IN
(See Note 9)
VALID DATA IN
I/O1 to I/O16
2002-03-05 6/11
TC51WKM516AXGN65,70
(See Note 8)
UB LB
CONTROLLED)
WRITE CYCLE 3 (
,
t
WC
Address
A0 to A20
t
t
t
WR
AS
WP
WE
t
t
CW
CW
CE1
t
CH
CE2
t
BW
UB , LB
t
t
ODW
BE
D
OUT
Hi-Z
Hi-Z
I/O1 to I/O16
t
COE
t
t
DH
DS
D
IN
(See Note 9)
VALID DATA IN
I/O1 to I/O16
2002-03-05 7/11
TC51WKM516AXGN65,70
Deep Power-down Timing
CE1
t
DPD
CE2
t
t
CH
CS
Power-on Timing
V
min
DD
V
DD
CE1
t
CHC
CE2
t
CH
t
CHP
Provisions of Address Skew
Read
If multiple invalid address cycles shorter than t min sustain over 10µs, as least one valid address cycle over
RC
t min must be needed during 10µs.
RC
over 10µs
CE1
WE
Address
t
min
RC
Write
If multiple invalid address cycles shorter than t min sustain over 10µs, as least one valid address cycle over
WC
t min with t min must be needed during 10µs.
WC
WP
over 10µs
CE1
WE
t min
WP
Address
t min
WC
2002-03-05 8/11
TC51WKM516AXGN65,70
Notes:
(1)
Stresses greater than listed under “Absolute Maximum Ratings” may cause permanent damage to the
device.
(2)
(3)
(4)
(5)
(6)
All voltages are reference to GND.
I
I
depends on the cycle time.
depends on output loading. Specified values are defined with the output open condition.
DDO
DDO
AC measurements are assumed t , t = 5 ns.
R
F
Parameters t , t
, t
and t define the time at which the output goes the open condition and
ODW
OD ODO BD
are not output voltage reference levels.
(7)
(8)
(9)
Data cannot be retained at deep power-down stand-by mode.
If OE is high during the write cycle, the outputs will remain at high impedance.
During the output state of I/O signals, input signals of reverse polarity must not be applied.
(10)
If CE1 or LB / UB goes LOW coincident with or after WE goes LOW, the outputs will remain at high
impedance.
(11)
If CE1 or LB / UB goes HIGH coincident with or before WE goes HIGH, the outputs will remain at
high impedance.
2002-03-05 9/11
TC51WKM516AXGN65,70
PACKAGE DIMENSIONS
9.0
SB
0.20
8.9 0.05
4
0.15
4-C0.4
S
0.1
S
S
0.1
B
A
B C D E F G H
1
2
3
4
5
6
A
0.8
1.7
0.4
(
)
5.6
Weight:
g (typ)
2002-03-05 10/11
TC51WKM516AXGN65,70
RESTRICTIONS ON PRODUCT USE
000707EBA
• TOSHIBA is continually working to improve the quality and reliability of its products. Nevertheless, semiconductor
devices in general can malfunction or fail due to their inherent electrical sensitivity and vulnerability to physical
stress. It is the responsibility of the buyer, when utilizing TOSHIBA products, to comply with the standards of
safety in making a safe design for the entire system, and to avoid situations in which a malfunction or failure of
such TOSHIBA products could cause loss of human life, bodily injury or damage to property.
In developing your designs, please ensure that TOSHIBA products are used within specified operating ranges as
set forth in the most recent TOSHIBA products specifications. Also, please keep in mind the precautions and
conditions set forth in the “Handling Guide for Semiconductor Devices,” or “TOSHIBA Semiconductor Reliability
Handbook” etc..
• The TOSHIBA products listed in this document are intended for usage in general electronics applications
(computer, personal equipment, office equipment, measuring equipment, industrial robotics, domestic appliances,
etc.). These TOSHIBA products are neither intended nor warranted for usage in equipment that requires
extraordinarily high quality and/or reliability or a malfunction or failure of which may cause loss of human life or
bodily injury (“Unintended Usage”). Unintended Usage include atomic energy control instruments, airplane or
spaceship instruments, transportation instruments, traffic signal instruments, combustion control instruments,
medical instruments, all types of safety devices, etc.. Unintended Usage of TOSHIBA products listed in this
document shall be made at the customer’s own risk.
• The products described in this document are subject to the foreign exchange and foreign trade laws.
• The information contained herein is presented only as a guide for the applications of our products. No
responsibility is assumed by TOSHIBA CORPORATION for any infringements of intellectual property or other
rights of the third parties which may result from its use. No license is granted by implication or otherwise under
any intellectual property or other rights of TOSHIBA CORPORATION or others.
• The information contained herein is subject to change without notice.
2002-03-05 11/11
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