TC51WKM516BXGN75 [TOSHIBA]
IC 2M X 16 PSEUDO STATIC RAM, 75 ns, PBGA48, 6 X 7 MM, 0.75 MM PITCH, LEAD FREE, PLASTIC, TFBGA-48, Static RAM;
| 型号： | TC51WKM516BXGN75 |
| 厂家： | 
TOSHIBA |
| 描述： | IC 2M X 16 PSEUDO STATIC RAM, 75 ns, PBGA48, 6 X 7 MM, 0.75 MM PITCH, LEAD FREE, PLASTIC, TFBGA-48, Static RAM |
| 文件： | 总10页 (文件大小：282K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
TC51WKM516BXGN75
TOSHIBA MOS DIGITAL INTEGRATED CIRCUIT SILICON GATE CMOS
Lead-Free
2,097,152-WORD BY 16-BIT CMOS PSEUDO STATIC RAM
DESCRIPTION
The TC51WKM516BXGN is a 33,554,432-bit pseudo static random access memory(PSRAM) organized as
2,097,152 words by 16 bits. Using Toshiba’s CMOS technology and advanced circuit techniques, it provides high
density, high speed and low power. The device uses dual power supplies(2.6 to 3.3 V for core and 1.7 to 2.2 V for
output buffer). The device also features SRAM-like W/R timing whereby the device is controlled by CE1 , OE , and
WE on asynchronous. The device has the page access operation. Page size is 8 words. The device also supports
deep power-down mode, realizing low-power standby.
•
Access Times:
Access Time
FEATURES
•
•
Organized as 2,097,152 words by 16 bits
Dual power supplies(2.6 to 3.3 V for core and
1.7 to 2.2 V for output buffer)
75 ns
75 ns
25 ns
30 ns
CE1 Access Time
OE Access Time
Page Access Time
Package:
•
•
•
Direct TTL compatibility for all inputs and outputs
Deep power-down mode: Memory cell data invalid
Page operation mode:
Page read operation by 8 words
•
•
•
•
Logic compatible with SRAM R/W ( WE ) pin
Standby current
Standby
P-TFBGA48-0607-0.75AZ (Weight:0.085 g typ.)
Lead-Free
100 μA
5 μA
Deep power-down standby
PIN ASSIGNMENT (TOP VIEW)
PIN NAMES
1
2
3
4
5
6
A0 to A20
A0 to A2
Address Inputs
Page Address Inputs
A
B
C
D
E
F
LB
OE
UB
A0
A3
A5
A1
A4
A2
CE2
I/O1
I/O3
I/O1 to I/O16 Data Inputs/Outputs
I/O9
CE1
I/O2
I/O4
CE1
CE2
Chip Enable Input
Chip select Input
I/O10 I/O11
A6
GND I/O12 A17
I/O13 NC
A7
V
DD
WE
Write Enable Input
Output Enable Input
Data Byte Control Inputs
Power Supply for Core
Power Supply for Output Buffer
Ground
V
A16
A15
A13
A10
I/O5 GND
I/O6 I/O7
WE I/O8
A11 A20
DDQ
OE
I/O15 I/O14 A14
LB , UB
G
H
I/O16 A19
A18 A8
A12
A9
V
DD
V
DDQ
(FBGA48)
GND
NC
No Connection
2006-02-03 1/10
TC51WKM516BXGN75
BLOCK DIAGRAM
CE
A9
A10
A11
A12
A13
A14
A15
A16
A17
A18
A19
A20
V
DD
GND
MEMORY CELL ARRAY
4,096 × 512 × 16
(33,554,432)
I/O1
I/O2
I/O3
I/O4
I/O5
I/O6
I/O7
I/O8
SENSE AMP
I/O9
I/O10
I/O11
I/O12
I/O13
I/O14
I/O15
I/O16
COLUMN ADDRESS
DECODER
COLUMN ADDRESS
BUFFER
REFRESH
ADDRESS
COUNTER
REFRESH
CONTROL
A0 A1 A2 A3 A4 A5 A6 A7 A8
CONTROL SIGNAL
GENERATOR
CE
WE
OE
UB
LB
CE1
CE
CE2
OPERATION MODE
MODE
CE1
CE2
OE
WE
LB
UB
Add
I/O1 to I/O8
I/O9 to I/O16
POWER
Read(Word)
L
L
L
L
L
L
L
H
H
H
H
H
H
H
H
H
H
L
L
L
H
H
H
L
L
L
L
H
L
X
X
X
X
X
X
X
X
X
D
D
D
I
I
I
I
I
I
I
OUT
OUT
OUT
DDO
DDO
DDO
DDO
DDO
DDO
DDO
Read(Lower Byte)
Read(Upper Byte)
Write(Word)
High-Z
L
H
L
High-Z
D
OUT
X
X
X
H
X
X
L
D
D
D
IN
IN
Write(Lower Byte)
Write(Upper Byte)
Outputs Disabled
Standby
L
L
H
L
Invalid
IN
L
H
X
X
X
Invalid
High-Z
High-Z
High-Z
D
IN
H
X
X
X
X
X
High-Z
High-Z
High-Z
I
DDS
Deep Power-down Standby
I
DDSD
Notes: L = Low-level Input(V ), H = High-level Input(V ), X = V or V , High-Z = High-impedance
IL IH IH IL
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TC51WKM516BXGN75
ABSOLUTE MAXIMUM RATINGS (See Note 1)
SYMBOL
RATING
VALUE
UNIT
V
V
V
V
Power Supply Voltage
−1.0 to 3.6
V
V
DD
Output Buffer Power Supply Voltage
Input Voltage for Address and Control Pins
Input/Output Voltage for I/O Pins
Operating Temperature
−1.0 to V
+ 0.5 (3.6 V Max)
DD
DDQ
IN
−1.0 to 3.6
V
−1.0 to V
+ 0.5
V
I/O
DDQ
T
opr.
T
strg.
T
solder
−25 to 85
°C
°C
°C
W
mA
Storage Temperature
−55 to 150
Soldering Temperature (10 s)
Power Dissipation
260
0.6
50
P
D
I
Short Circuit Output Current
OUT
DC RECOMMENDED OPERATING CONDITIONS (Ta = −25°C to 85°C)
SYMBOL
PARAMETER
Power Supply Voltage
MIN
TYP.
MAX
UNIT
V
V
2.6
1.7
2.75
1.8
⎯
3.3
2.2
DD
Output Buffer Power Supply Voltage
Input High Voltage for Address and Control Pins
Input High Voltage for I/O Pins
Input Low Voltage
DDQ
IH
V
1.6
V
+ 0.3*
DD
V
V
1.6
⎯
V
+ 0.3*
DDQ
−0.3*
⎯
0.4
IL
* : V (Max) V +1.0 V/ V
IH DD
+1.0 V with 10 ns pulse width
DDQ
V (Min) -1.0 V with 10 ns pulse width
IL
DC CHARACTERISTICS (Ta = −25°C to 85°C, V = 2.6 to 3.3 V, V
= 1.7 to 2.2 V)
DD
DDQ
(See Note 3 to 4)
SYMBOL
PARAMETER
TEST CONDITION
MIN
TYP. MAX UNIT
I
Input Leakage Current
Output Leakage Current
Output High Voltage
Output Low Voltage
V
= 0 V to V
DDQ
−1.0
−1.0
− 0.2
⎯
⎯
⎯
⎯
+1.0
+1.0
⎯
μA
μA
V
IL
IN
I
Output disable, V
= 0 V to V
OUT DD
LO
V
V
I
I
= − 100 μA
= 100 μA
V
OH
OL
OH
DDQ
⎯
⎯
0.2
V
OL
CE1 = V
IL
CE2 = V , I
I
I
Operating Current
t
t
= min
= min
⎯
⎯
40
25
mA
mA
DDO1
RC
= 0 mA
IH OUT
CE1 = V , CE2 = V
IL
Page add. cycling, I
,
IH
Page Access Operating Current
Standby Current(MOS)
⎯
DDO2
PC
= 0 mA
OUT
I
I
CE1 = V
− 0.2 V, CE2 = V
− 0.2 V
⎯
⎯
⎯
⎯
100
5
μA
μA
DDS
DD
DD
Deep Power-down Standby Current CE2 = 0.2 V
DDSD
CAPACITANCE (Ta = 25°C, f = 1 MHz)
SYMBOL
PARAMETER
TEST CONDITION
= GND
MAX
UNIT
C
C
Input Capacitance
Output Capacitance
V
IN
10
10
pF
pF
IN
V
OUT
= GND
OUT
Note: This parameter is sampled periodically and is not 100% tested.
2006-02-03 3/10
TC51WKM516BXGN75
AC CHARACTERISTICS AND OPERATING CONDITIONS
(Ta = −25°C to 85°C, V = 2.6 to 3.3 V, V
= 1.7 to 2.2 V) (See Note 5 to 11)
DD
DDQ
SYMBOL
PARAMETER
MIN
MAX
UNIT
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
Read Cycle Time
75
⎯
⎯
⎯
⎯
10
0
10000
75
75
25
25
⎯
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
μs
ms
ns
μs
RC
Address Access Time
ACC
CO
Chip Enable ( CE1 ) Access Time
Output Enable Access Time
OE
Data Byte Control Access Time
Chip Enable Low to Output Active
Output Enable Low to Output Active
Data Byte Control Low to Output Active
Chip Enable High to Output High-Z
Output Enable High to Output High-Z
BA
COE
OEE
BE
⎯
0
⎯
⎯
⎯
⎯
5
20
20
20
⎯
OD
ODO
BD
Data Byte Control High to Output High-Z
Output Data Hold Time
Page Mode Time
OH
75
30
⎯
5
10000
⎯
PM
Page Mode Cycle Time
Page Mode Address Access Time
Page Mode Output Data Hold Time
Write Cycle Time
PC
30
⎯
AA
AOH
WC
WP
CW
BW
AW
AS
75
50
75
60
60
0
10000
⎯
Write Pulse Width
Chip Enable to End of Write
Data Byte Control to End of Write
Address Valid to End of Write
Address Set-up Time
⎯
⎯
⎯
⎯
Write Recovery Time
0
⎯
WR
CEH
WEH
ODW
OEW
DS
Chip Enable High Pulse Width
Write Enable High Pulse Width
WE Low to Output High-Z
WE High to Output Active
Data Set-up Time
10
15
⎯
0
⎯
⎯
20
⎯
30
0
⎯
Data Hold Time
⎯
DH
CE2 Set-up Time
0
⎯
CS
CE2 Hold Time
300
10
0
⎯
CH
CE2 Pulse Width
⎯
DPD
CHC
CHP
CE2 Hold from CE1
⎯
CE2 Hold from Power On
30
⎯
AC TEST CONDITIONS
PARAMETER
CONDITION
Output load
30 pF + 1 TTL Gate
Input pulse level
Timing measurements
Reference level
1.6 V, 0.2 V
V
× 0.5
× 0.5
DDQ
V
DDQ
t , t
5 ns
R
F
2006-02-03 4/10
TC51WKM516BXGN75
TIMING DIAGRAMS
READ CYCLE
t
RC
Address
A0 to A20
t
t
ACC
OH
t
CO
CE1
Fix-H
CE2
OE
t
t
OD
OE
t
ODO
WE
t
BA
UB , LB
t
BE
t
BD
t
OEE
D
OUT
Hi-Z
VALID DATA OUT
Hi-Z
t
COE
I/O1 to I/O16
INDETERMINATE
PAGE READ CYCLE (8 words access)
t
PM
Address
A0 to A2
t
t
t
t
PC
PC
PC
RC
Address
A3 to A20
CE1
Fix-H
CE2
OE
WE
UB , LB
t
t
OD
OE
t
BD
t
BA
t
t
t
AOH
AOH
AOH
t
t
OEE
OH
t
BE
D
OUT
D
OUT
D
OUT
D
OUT
D
OUT
Hi-Z
Hi-Z
I/O1 to I/O16
t
COE
t
t
t
t
t
ODO
CO
AA
AA
AA
* Maximum 8 words
t
ACC
2006-02-03 5/10
TC51WKM516BXGN75
(See Note 8)
WE
WRITE CYCLE 1 (
CONTROLLED)
t
WC
Address
A0 to A20
t
t
WEH
AW
t
t
WP
t
AS
WR
WE
t
t
CW
WR
CE1
t
CH
CE2
t
t
BW
WR
UB , LB
t
t
OEW
ODW
D
OUT
(See Note 10)
Hi-Z
(See Note 11)
I/O1 to I/O16
t
t
DH
DS
D
IN
(See Note 9)
VALID DATA IN
(See Note 9)
I/O1 to I/O16
(See Note 8)
CE
WRITE CYCLE 2 (
CONTROLLED)
t
WC
Address
A0 to A20
t
AW
t
t
WP
t
AS
WR
WE
t
CEH
t
t
CW
WR
CE1
CE2
t
CH
t
t
BW
WR
UB , LB
t
t
ODW
BE
D
OUT
Hi-Z
Hi-Z
I/O1 to I/O16
t
COE
t
t
DH
DS
D
IN
(See Note 9)
VALID DATA IN
I/O1 to I/O16
2006-02-03 6/10
TC51WKM516BXGN75
Deep Power-down Timing
CE1
t
DPD
CE2
t
t
CH
CS
Power-on Timing
V
min
DD
V
DD
CE1
t
CHC
CE2
t
CH
t
CHP
Provisions of Address Skew
Read
In case, multiple invalid address cycles shorter than t min sustain over 10μs in a active status, as least one
RC
valid address cycle (with address change of any pins of A3-20) over t min must be needed during 10μs.
RC
over 10μs
CE1
WE
Address
t min
RC
Write
In case, multiple invalid address cycles shorter than t min sustain over 10μs in a active status, as least one
WC
valid address cycle (with address change of any pins of A3-20) over t min with t min must be needed during
WC
WP
10μs.
over 10μs
CE1
WE
t min
WP
Address
t min
WC
2006-02-03 7/10
TC51WKM516BXGN75
Notes:
(1)
Stresses greater than listed under “Absolute Maximum Ratings” may cause permanent damage to the
device.
(2)
(3)
(4)
(5)
(6)
All voltages are reference to GND.
I
I
depends on the cycle time.
DDO
DDO
depends on output loading. Specified values are defined with the output open condition.
AC measurements are assumed t , t = 5 ns.
R
F
Parameters t , t
, t
and t
define the time at which the output goes the open condition and
OD ODO BD
ODW
are not output voltage reference levels.
(7)
(8)
Data cannot be retained at deep power-down stand-by mode.
If OE is high during the write cycle, the outputs will remain at high impedance.
During the output state of I/O signals, input signals of reverse polarity must not be applied.
(9)
(10)
If CE1 or LB / UB goes LOW coincident with or after WE goes LOW, the outputs will remain at high
impedance.
(11)
If CE1 or LB / UB goes HIGH coincident with or before WE goes HIGH, the outputs will remain at
high impedance.
2006-02-03 8/10
TC51WKM516BXGN75
PACKAGE DIMENSIONS
P-TFBGA48-0607-0.75AZ
Unit:mm
7.0
SB
0.2
4
0.15
S
0.1
S
S
0.1
0.43 0.05
B
M SAB
φ0.08
A
B
C
D
E
F
G
H
1
2
3
4
5
6
A
0.375
0.75
(5.25)
0.875
Weight:0.085 g (typ)
2006-02-03 9/10
TC51WKM516BXGN75
2006-02-03 10/10
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