T14L1024A-10D [TMT]
128K X 8 HIGH SPEED CMOS STATIC RAM; 128K ×8高速CMOS静态RAM
| 型号： | T14L1024A-10D |
| 厂家： | 
TAIWAN MEMORY TECHNOLOGY |
| 描述： | 128K X 8 HIGH SPEED CMOS STATIC RAM |
| 文件： | 总12页 (文件大小：87K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
TE
tmCH
Preliminary T14L1024A
128K X 8 HIGH SPEED
CMOS STATIC RAM
SRAM
FEATURES
GENERAL DESCRIPTION
The T14L1024A is a one-megabit density, fast
static random access memory organized as 131,072
words by 8 bits. It is designed for use in high
performance memory applications such as main
memory storage and high speed communication
buffers. Fabricated using high performance CMOS
technology, access times down to 10ns are achieved.
Memory expansion by banking is easily
• Fast Address Access Times : 10/12/15ns
• Single 3.3V ±0.3V power supply
• Low Power Consumption : 110/105/100mA
• TTL I/O compatible
• 2.0V data retention mode
• Automatic power-down when deselected
• Available packages :
accomplished using the chip enable pins CE1 and
CE2. This device is packaged in a standard 32-pin
300 mil DIP/SOJ and 32-pin SOP/TSOP-I.
32-pin 300 mil DIP/SOJ & 32-pin SOP/TSOP-I
• Industry Standard Pin Assignment
BLOCK DIAGRAM
Vcc
Vss
PIN CONFIGURATION
CORE
ARRAY
A0
DECODER
.
.
.
NC
A10
A9
1
2
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
Vcc
A11
CE2
WE
A12
A13
A14
A15
OE
.
A16
3
CE1
CE2
A8
4
I/O0
5
A7
.
.
.
DIP
/
SOJ
/
SOP
6
A6
DATA I/O
WE
OE
7
A5
I/O7
A4
8
A3
9
PIN DESCRIPTION
A2
10
11
12
13
14
15
16
A16
CE1
I/O7
I/O6
I/O5
I/O4
I/O3
SYMBOL
DESCRIPTION
A1
A0 - A16
Address Inputs
A0
I/O0 - I/O7
/CE1,CE2
/WE
Data Inputs/Outputs
Chip Select Inputs
Write Enable
I/O0
I/O1
I/O2
Vss
/OE
Vcc
Vss
Output Enable
Power Supply
Ground
A15
A14
A13
A12
WE
CE2
A11
VCC
NC
A10
A9
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
OE
A16
CE1
I/O7
I/O6
I/O5
I/O4
I/O3
VSS
I/O2
I/O1
I/O0
A0
PART NUMBER EXAMPLES
PACKAGE
SPEED
10ns
T14L1024A-10P TSOP-I 8x13.4mm 10ns
TSOP-I
T14L1024A-10J
SOJ 300mil
A8
A7
A6
A5
T14L1024A-10H
T14L1024A-10N
T14L1024A-10D
TSOP-I 8x20mm 10ns
A1
A2
A3
DIP 300mil
SOP
10ns
10ns
A4
TM Technology, Inc. reserves the right
to change products or specifications without notice.
P. 1
Publication Date: SEP. 2002
Revision:0.F
TE
tmCH
Preliminary T14L1024A
DC CHARACTERISTICS ABSOLUTE MAXIMUM RATINGS
PARAMETER
Power Supply Voltage
Input Voltage
SYM
Vcc
VIN
RATING
-0.5 to 4.6
-0.5 to Vcc+0.5
-0.5 to Vcc+0.5
0 to +70
UNIT
V
V
VOUT
TOPR
TSTG
PD
Output Voltage
V
Operating Temperatrue
Storage Temperature
Power Dissipation
°C
°C
W
-55 to +150
1.0
IOUT
Short Circuit Output Current
50
mA
TRUTH TABLE
CE2
X
MODE
I/O0- I/O7
High-Z
Vcc
ISB, ISB1
CE1
H
OE
X
WE
X
Not Selected
Not Selected
Output Disable
Read
ISB, ISB1
X
L
X
X
High-Z
L
H
H
H
High-Z
Icc
Icc
Icc
L
H
L
H
Data Out
Data In
L
H
X
L
Write
OPERATING CHARACTERISTICS
(Vcc = 3.3V ±0.3V, Ta = 0 to 70°C)
PARAMETER
Power Supply Voltage
Input Low Voltage
SYM.
Vcc
VIL
TEST CONDITIONS
MIN.
MAX.
UNIT
V
3.0
-0.5
2.1
-
3.6
0.8
V
VIH
ILI
Input High Voltage
Input Leakage Current
Vcc+0.3
5
V
VIN =Vss to Vcc
uA
VIN=Vss to Vcc , CE1 = VIH or CE2
= VIL or OE = VIH or WE = VIL
ILO
Output Leakage Current
-
5
uA
VOL
VOH
Icc
I
I
OL = 4.0 mA
OH =-2.0 mA
Output Low Voltage
Output High Voltage
Operating Power
Supply Current
-
2.4
-
0.4
-
V
V
CE1 =V
CE2 = VIH ;f=max
IO = 0mA
10ns
12ns
15ns
110
105
100
25
mA
mA
mA
mA
mA
IL
-
-
ISB
Standby Power
Supply Current
CE1 =V , CE2 = VIL, IO = 0mA
-
IH
ISB1
Vcc = max; CE1 > Vcc-0.2V or CE2<
Vss+0.2V; f=0mhz; IO = 0mA
-
5
Note: Typical characteristics are at Vcc = 3.3V, Ta = 25°C
TM Technology, Inc. reserves the right
to change products or specifications without notice.
P. 2
Publication Date: SEP. 2002
Revision:0.F
TE
tmCH
Preliminary T14L1024A
RECOMMENDED OPERATING CONDITIONS
PARAMETER
Supply Voltage
SYM
MIN
Typ-0.3
-0.3
TYP
MAX
Typ+0.3
0.8
UNIT
V
Vcc
3.3
V
Input Voltage, low
Input Voltage, high
Ambient Temperature
-
-
-
V
IL
V
2.1
Vcc+0.3
70
V
IH
TA
0
°C
CAPACITANCE
PARAMETER
Input Capacitance
SYMBOL
CONDITION
MAX.
UNIT
pF
CIN
CI/O
V
= 0V
6
8
IN
V
OUT= 0V
Input/ Output Capacitance
pF
Note: These parameters are sampled but not 100% tested.
AC TEST CONDITIONS
PARAMETER
Input Pulse Levels
CONDITIONS
0V to 3V
Input Rise and Fall Times
Input and Output Timing Reference Level
Output Load
3.0 ns
1.5V
CL =30pF,IOH /IOL = -2mA/4mA
AC TEST LOADS AND WAVEFORM
R1 319 ohm
3.3V
RL=50 ohm
Vt=1.5V
30pF
OUTPUT
OUTPUT
5pF
R2
353 ohm
Zo=50 ohm
Including
Jig and
Scope
(For TCLZ, TOLZ, TCHZ, TOHZ, TWHZ, TOW
)
TM Technology, Inc. reserves the right
to change products or specifications without notice.
P. 3
Publication Date: SEP. 2002
Revision:0.F
TE
tmCH
Preliminary T14L1024A
AC CHARACTERISTICS
(V =3.3V ±0.3V, Vss = 0V, Ta = 0 to 70°C)
cc
(1) READ CYCLE
T14L1024A-10 T14L1024A-12 T14L1024A-15
UNIT
PARAMETER
Read Cycle Time
SYM.
MIN. MAX. MIN. MAX. MIN. MAX.
10
-
-
10
10
6
12
-
-
12
12
7
15
-
-
15
15
7
tRC
tAA
ns
ns
ns
ns
ns
ns
ns
ns
ns
Address Access Time
Chip Enable Access Time
-
-
-
tACS
tAOE
tCLZ*
tOLZ*
tCHZ*
tOHZ*
tOH
Output Enable to Output Valid
Chip Enable to Output in Low Z
Output Enable to Output in Low Z
Chip Disable to Output in High Z
Output Disable to Output in High Z
Output Hold from Address Change
-
-
-
3
0
-
-
3
0
-
-
3
0
-
-
-
-
-
5
6
7
-
5
-
6
-
7
3
-
3
-
3
-
* These parameters are sampled but not 100% tested.
(2)WRITE CYCLE
T14L1024A-10 T14L1024A-12 T14L1024A-15
MIN. MAX. MIN. MAX. MIN. MAX.
PARAMETER
Write Cycle Time
SYM.
UNIT
10
8
8
0
8
0
6
0
-
-
-
12
10
10
0
-
-
15
11
11
0
-
-
tWC
tCW
tAW
tAS
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Chip Enable to End of Write
Address Valid to End of Write
Address Setup Time
-
-
-
-
-
-
Write Pulse Width
-
10
0
-
11
0
-
tWP
Write Recovery Time
-
-
-
tWR
tDW
tDH
tWHZ*
tOHZ*
tOW
Data Valid to End of Write
Data Hold from End of Write
Write to Output in High Z
Output Disable to Output in High Z
Output Active from End of Write
-
8
-
8
-
-
0
-
0
-
5
5
-
-
6
6
-
-
6
7
-
-
-
-
0
0
0
* These parameters are sampled but not 100% tested.
TM Technology, Inc. reserves the right
to change products or specifications without notice.
P. 4
Publication Date: SEP. 2002
Revision:0.F
TE
tmCH
Preliminary T14L1024A
TIMING WAVEFORMS
READ CYCLE 1
(Address
Controlled)
tRC
Address
tAA
tOH
tOH
Dout
READ CYCLE 2
(Chip Enable Controlled)
tRC
Address
OE
tAA
t
AOE
tOH
t
OLZ
CE1
CE2
Dout
t
t
ACS
OHZ
t
t
CLZ
CHZ
DON'T CARE
UNDEFINED
TM Technology, Inc. reserves the right
to change products or specifications without notice.
P. 5
Publication Date: SEP. 2002
Revision:0.F
TE
tmCH
Preliminary T14L1024A
WRITE CYCLE 1 (OE CLOCK)
t W
C
A d d r e s s
O E
t C
t W
W
R
t A W
C E 1
C E 2
t A S
t W
P
W E
t O
H
Z
D
D
o u t
t D
t D
H
W
I N
WRITE CYCLE 2 (OE = V
IL
Fixed)
t W
C
A d d r e s s
t C
t W
W
R
t A
W
C E 1
C E 2
W E
t A
t W
S
P
t W
t O
H
H
Z
t O
W
( 1 , 4 )
( 2 )
( 3 )
D
o u t
t D
t D
H
W
D
IN
D O N 'T C A R E
U N D E F I N E D
TM Technology, Inc. reserves the right
to change products or specifications without notice.
P. 6
Publication Date: SEP. 2002
Revision:0.F
TE
tmCH
Preliminary T14L1024A
Notes: 1. During this period, I/O pins are in the output state, so input signals of opposite phase to the
outputs should not be applied.
2. The data output from DOUT are the same as the data written to DIN during the write cycle.
3. DOUT provides the read data for the next address.
4. Transition is measured ± 500 mV from steady state with CL = 5pF. This parameter is
guaranteed but not 100% tested.
5. If OE is low during a WE controlled write cycle, the write pulse width must be the larger of
t
or (t
+ t ) to allow the I/O drivers to turn off and data to be placed on the bus for the
WHZ DW
WP
required t If OE is high during a WE controlled write cycle, this requirement does
.
DW
not apply and the write pulse can be as short as the specified t
.
WP
TM Technology, Inc. reserves the right
to change products or specifications without notice.
P. 7
Publication Date: SEP. 2002
Revision:0.F
TE
tmCH
Preliminary T14L1024A
PACKAGE DIMENSIONS
32-LEAD SOJ (300 mil)
SYMBOL
DIMENSIONS IN INCHES
DIMENSIONS IN MM
3.556(MAX)
0.660(MIN)
A
A1
A2
B
0.140(MAX)
0.026(MIN)
0.100±0.005
0.018(TYP)
0.028(TYP)
0.008(TYP)
0.823±0.005
0.335±0.010
0.300±0.005
0.050(TYP)
0.086±0.010
0.003(MAX)
2.540±0.127
0.457(TYP)
B1
C
0.711(TYP)
0.203(TYP)
D
20.904±0.127
8.509±0.254
7.620±0.127
1.270(TYP)
E
E1
e
L
2.184±0.254
0.076(MAX)
y
TM Technology, Inc. reserves the right
to change products or specifications without notice.
P. 8
Publication Date: SEP. 2002
Revision:0.F
TE
tmCH
Preliminary T14L1024A
PACKAGE DIMENSIONS
32-LEAD TSOP-I (8x20mm)
H D
C
1
3 2
b
E
e
1 6
1 7
A 2
A
A 1
"A "
S e a tin g p la n e
y
D
S e a tin g p la n e
D e ta il "A "
L
L 1
SYMBOL
DIMENSIONS IN INCHES
DIMENSIONS IN MM
MIN
-
NOM
-
MAX
0.047
0.006
0.041
0.011
0.008
MIN
NOM
-
MAX
A
A1
A2
b
-
1.20
0.15
1.05
0.27
0.21
0.002
0.035
0.007
0.004
-
0.05
0.90
0.17
0.10
-
0.040
1.00
0.008
0.20
C
0.006
0.15
HD
D
0.787 TYP
0.724 TYP
0.315 TYP
0.020 TYP
0.024
20.00 TYP
18.40 TYP
8.00 TYP
0.50 TYP
0.60
E
e
L
0.020
0.028
0.50
0.70
L1
θ
0.032 TYP
3°
0.813 TYP
3°
0°
5°
0°
5°
TM Technology, Inc. reserves the right
to change products or specifications without notice.
P. 9
Publication Date: SEP. 2002
Revision:0.F
TE
tmCH
Preliminary T14L1024A
PACKAGE DIMENSIONS
32-LEAD TSOP-I (8x13.4mm)
H D
C
1
3 2
b
E
e
1 6
1 7
A 2
A
A 1
"A "
S e a tin g p la n e
y
D
S e a tin g p la n e
D e ta il "A "
L
L 1
SYMBOL
DIMENSIONS IN INCHES
DIMENSIONS IN MM
MIN
-
NOM
-
MAX
0.047
0.006
0.041
0.011
0.008
MIN
NOM
-
MAX
A
A1
A2
b
-
1.20
0.15
1.05
0.27
0.21
0.002
0.035
0.007
0.004
-
0.05
0.90
0.17
0.10
-
0.040
1.00
0.008
0.20
C
0.006
0.15
HD
D
0.528 TYP
0.465 TYP
0.315 TYP
0.020 TYP
0.024
13.40 TYP
11.80 TYP
8.00 TYP
0.50 TYP
0.60
E
e
L
0.020
0.028
0.50
0.7
L1
θ
0.032TYP
3°
0.813 TYP
3°
0°
5°
0°
5°
TM Technology, Inc. reserves the right
to change products or specifications without notice.
P. 10
Publication Date: SEP. 2002
Revision:0.F
TE
tmCH
Preliminary T14L1024A
PACKAGE DIMENSIONS
32-LEAD DIP (300 mil)
A
32
17
A1
1
16
B4
D
B2
B3
B
B1
C2
C1
C
D1
0
Dimension in mm
Dimension in inch
Nom
Symbol
Min
-
7.26
-
Nom
40.64
7.36
-
3.30
3.81
-
Max
41.15
7.46
5.08
3.56
3.94
-
1.65
2.79
0.56
1.63
8.50
11.94
15°
Min
-
Max
1.62
A
A1
B
B1
B2
B3
B4
C
C1
C2
D
D1
θ
1.60
0.290
-
0.130
0.150
-
0.286
-
0.120
0.145
0.015
-
0.090
0.016
0.58
0.295
0.430
0°
0.294
0.200
0.140
0.155
-
0.065
0.110
0.022
0.64
3.05
3.68
0.38
-
2.29
0.41
1.47
7.49
10.92
0°
-
-
2.54
0.46
1.52
8.00
11.43
-
0.100
0.018
0.60
0.315
0.450
-
0.335
0.470
15°
TM Technology, Inc. reserves the right
to change products or specifications without notice.
P. 11
Publication Date: SEP. 2002
Revision:0.F
TE
tmCH
Preliminary T14L1024A
PACKAGE DIMENSIONS
32-LEAD SOP
e1
32
17
E HE
Detail F
L
1
16
b
e1
D
C
A2
A1
A
S
e
LE
y
See Detail F
Seating Plane
Dimension in inches
Dimension in mm
max min. typ. max.
Symbol
Notes :
min.
-
typ.
1. Dimensions D max. & S
include mold flash or tie bar
burrs.
-
-
0.118
-
-
-
3.00
-
A
A1
A2
b
0.004
0.10
-
2. Dimension b does not include
dambar protrusion / intrusion.
3. Dimensions D & E include
mold mismatch and determined
at the mold parting line.
4. controlling dimension : inches
5. general appearance spec should
be based on final visual
inspection spec.
0.101 0.106 0.111 2.57
0.014 0.016 0.020 0.36
0.006 0.008 0.012 0.15
2.69
0.41
0.20
2.82
0.51
0.31
C
-
0.805 0.817
0.440 0.445 0.450 11.18 11.30 11.43
0.044 0.050 0.056 1.12 1.27 1.42
0.546 0.556 0.556 13.87 14.12 14.38
-
20.45 20.75
D
E
e
HE
L
0.023 0.031 0.039 0.58
0.047 0.055 0.063 1.19
0.79
0.99
1.60
0.91
0.10
10°
1.40
LE
S
-
-
-
-
-
0.036
0.004
10°
-
-
-
-
-
y
•
0°
0°
TM Technology, Inc. reserves the right
to change products or specifications without notice.
P. 12
Publication Date: SEP. 2002
Revision:0.F
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