T14L1024N-10P [TMT]
128K X 8 HIGH SPEED CMOS STATIC RAM; 128K ×8高速CMOS静态RAM型号: | T14L1024N-10P |
厂家: | TAIWAN MEMORY TECHNOLOGY |
描述: | 128K X 8 HIGH SPEED CMOS STATIC RAM |
文件: | 总13页 (文件大小:89K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
TE
tmCH
T14L1024N
128K X 8 HIGH SPEED
CMOS STATIC RAM
SRAM
FEATURES
GENERAL DESCRIPTION
The T14L1024N is a one-megabit density, fast
static random access memory organized as
131,072 words by 8 bits. It is designed for
use in high performance memory applications
such as main memory storage and high speed
communication buffers. Fabricated using high
performance CMOS technology, access times
down to 10ns are achieved.
• Fast Address Access Times : 10/12/15ns
• Single 3.3V ±0.3V power supply
• Center power/ground pin configuration
• Low Power Consumption : 110/105/100mA
• TTL I/O compatible
• 2.0V data retention mode
• Automatic power-down when deselected
• Available packages :
BLOCK DIAGRAM
- 32-pin 300 mil and 400 mil SOJ
Vcc
Vss
- 32-pin TSOP 8x13.4mm and 8x20mm
- 36-Ball CSP (8x10mm)
CORE
ARRAY
A0
DECODER
.
.
.
PART NUMBER EXAMPLES
.
PACKAGE
SOJ 300mil
SPEED
A16
T14L1024N-10J
10ns
10ns
10ns
10ns
10ns
T14L1024N-10W SOJ 400 mil
T14L1024N-10P TSOP 8x13.4mm
T14L1024N-10H TSOP 8x20mm
T14L1024N-10C 36-Ball CSP
CE
I/O0
.
.
.
DATA I/O
WE
OE
I/O7
PIN DESCRIPTION
SYMBOL
A0 - A16
DESCRIPTION
Address Inputs
I/O0 - I/O7
Data Inputs/Outputs
Chip Select Inputs
CE
Write Enable
Output Enable
WE
OE
Vcc
Vss
Power Supply
Ground
TM Technology Inc. reserves the right
to change products or specifications without notice.
P. 1
Publication Date: APR. 2002
Revision: C
TE
tmCH
T14L1024N
PIN CONFIGURATION
A0
A1
1
2
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
A16
A15
A14
A13
OE
A2
3
A3
4
CE
I/O0
I/O1
Vcc
Vss
I/O2
I/O3
WE
A4
5
6
I/O7
I/O6
Vss
Vcc
I/O5
I/O4
A12
A11
A10
A9
7
SOJ
8
9
10
11
12
13
14
15
16
A5
A6
A7
A8
A0
A1
A2
A3
CE
I/O0
I/O1
VCC
VSS
I/O2
I/O3
WE
A4
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
A16
A15
A14
A13
OE
I/O7
I/O6
VSS
VCC
I/O5
I/O4
A12
A11
A10
A9
TSOP
A5
A6
A7
A8
1
2
3
4
5
6
A 0
I/O
A 1
A 2
N C
W E
N C
A 3
A 4
A 5
A 6
A 7
A 8
A
B
C
D
E
4
5
I/O
0
1
I/O
I/O
V ss
V cc
V ss
V cc
I/O
I/O
6
I/O
I/O
2
N C
C E
N C
A 1 6
A 1 2
F
7
3
O E
A 1 5
A 1 3
G
H
A 9
A 1 0
A 1 1
A 1 4
36-Ball CSP TOP VIEW (Ball Down)
TM Technology Inc. reserves the right
to change products or specifications without notice.
P. 2
Publication Date: APR. 2002
Revision: C
TE
tmCH
T14L1024N
DC CHARACTERISTICS ABSOLUTE MAXIMUM RATINGS
PARAMETER
Power Supply Voltage
Input Voltage
SYM
Vcc
VIN
RATING
-0.5 to 4.6
-0.5 to Vcc+0.5
-0.5 to Vcc+0.5
0 to +70
UNIT
V
V
VOUT
TOPR
TSTG
PD
Output Voltage
V
Operating Temperatrue
Storage Temperature
Power Dissipation
°C
°C
W
-55 to +150
1.0
IOUT
Short Circuit Output Current
50
mA
TRUTH TABLE
MODE
I/O0- I/O7
High-Z
Vcc
ISB, ISB1
CE
H
X
L
OE
X
WE
X
Not Selected
Not Selected
Output Disable
Read
ISB, ISB1
X
X
High-Z
H
H
High-Z
Icc
Icc
Icc
L
L
H
Data Out
Data In
L
X
L
Write
OPERATING CHARACTERISTICS
(Vcc = 3.3V ±0.3V, Ta = 0 to 70°C)
PARAMETER
Power Supply Voltage
Input Low Voltage
SYM.
Vcc
VIL
TEST CONDITIONS
MIN.
MAX.
3.6
UNIT
V
3.0
-0.5
2.1
-
0.8
V
VIH
ILI
Input High Voltage
Input Leakage Current
Vcc+0.3
5
V
VIN =Vss to Vcc
uA
VIN=Vss to Vcc , CE = VIH
ILO
Output Leakage Current
-
5
uA
OE = VIH or WE = VIL
VOL
VOH
Icc
I
I
OL = 4.0 mA
OH =-2.0 mA
Output Low Voltage
Output High Voltage
Operating Power
Supply Current
-
2.4
-
0.4
-
V
V
CE =V
10ns
12ns
15ns
110
105
100
25
mA
mA
mA
mA
mA
IL
f=max
-
IO = 0mA
-
ISB
Standby Power
Supply Current
CE =V , IO = 0mA
-
IH
ISB1
Vcc = max; CE ≥ Vcc-0.2V; f=0mhz;
-
5
IO = 0mA
Note: Typical characteristics are at Vcc = 3.3V, Ta = 25°C
TM Technology Inc. reserves the right
to change products or specifications without notice.
P. 3
Publication Date: APR. 2002
Revision: C
TE
tmCH
T14L1024N
RECOMMENDED OPERATING CONDITIONS
PARAMETER
Supply Voltage
SYM
MIN
Typ-0.3
-0.3
TYP
MAX
Typ+0.3
0.8
UNIT
V
Vcc
3.3
V
Input Voltage, low
Input Voltage, high
Ambient Temperature
-
-
-
V
IL
V
2.1
Vcc+0.3
70
V
IH
TA
0
°C
CAPACITANCE
PARAMETER
Input Capacitance
SYMBOL
CONDITION
MAX.
UNIT
pF
CIN
CI/O
V
= 0V
6
8
IN
V
OUT= 0V
Input/ Output Capacitance
pF
Note: These parameters are sampled but not 100% tested.
AC TEST CONDITIONS
PARAMETER
Input Pulse Levels
CONDITIONS
0V to 3V
Input Rise and Fall Times
Input and Output Timing Reference Level
Output Load
3.0 ns
1.5V
CL =30pF,IOH /IOL = -2mA/4mA
AC TEST LOADS AND WAVEFORM
R1 319 ohm
3.3V
RL=50 ohm
Vt=1.5V
30pF
OUTPUT
OUTPUT
5pF
R2
353 ohm
Zo=50 ohm
Including
Jig and
Scope
(For TCLZ, TOLZ, TCHZ, TOHZ, TWHZ, TOW
)
TM Technology Inc. reserves the right
to change products or specifications without notice.
P. 4
Publication Date: APR. 2002
Revision: C
TE
tmCH
T14L1024N
AC CHARACTERISTICS
(V =3.3V ±0.3V, Vss = 0V, Ta = 0 to 70°C)
cc
(1) READ CYCLE
T14L1024N-10 T14L1024N-12 T14L1024N-15
PARAMETER
Read Cycle Time
SYM.
UNIT
MIN. MAX. MIN. MAX. MIN. MAX.
10
-
-
10
10
6
12
-
-
12
12
7
15
-
-
15
15
7
tRC
tAA
ns
ns
ns
ns
ns
ns
ns
ns
ns
Address Access Time
Chip Enable Access Time
-
-
-
tACS
tAOE
tCLZ*
tOLZ*
tCHZ*
tOHZ*
tOH
Output Enable to Output Valid
Chip Enable to Output in Low Z
Output Enable to Output in Low Z
Chip Disable to Output in High Z
Output Disable to Output in High Z
Output Hold from Address Change
-
-
-
3
0
-
-
3
0
-
-
3
0
-
-
-
-
-
5
6
7
-
5
-
6
-
7
3
-
3
-
3
-
* These parameters are sampled but not 100% tested.
(2)WRITE CYCLE
T14L1024N-10 T14L1024N-12 T14L1024N-15
MIN. MAX. MIN. MAX. MIN. MAX.
PARAMETER
Write Cycle Time
SYM.
UNIT
10
8
8
0
8
0
6
0
-
-
-
12
10
10
0
-
-
15
11
11
0
-
-
tWC
tCW
tAW
tAS
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Chip Enable to End of Write
Address Valid to End of Write
Address Setup Time
-
-
-
-
-
-
Write Pulse Width
-
10
0
-
11
0
-
tWP
Write Recovery Time
-
-
-
tWR
tDW
tDH
tWHZ*
tOHZ*
tOW
Data Valid to End of Write
Data Hold from End of Write
Write to Output in High Z
Output Disable to Output in High Z
Output Active from End of Write
-
8
-
8
-
-
0
-
0
-
5
5
-
-
6
6
-
-
6
7
-
-
-
-
0
0
0
* These parameters are sampled but not 100% tested.
TM Technology Inc. reserves the right
to change products or specifications without notice.
P. 5
Publication Date: APR. 2002
Revision: C
TE
tmCH
T14L1024N
TIMING WAVEFORMS
READ CYCLE 1
(Address
Controlled)
t
R
C
A
d d r e s s
t
A
A
t
O
H
t
O
H
D
O
U T
READ CYCLE 2
(Chip Enable Controlled)
t
RC
A d d r e s s
t
AA
O E
C E
t
t
OH
AOE
t
OLZ
t
t
t
t
ACS
OHZ
CLZ
CHZ
D
O U T
DON'T CARE
UNDEFINED
TM Technology Inc. reserves the right
to change products or specifications without notice.
P. 6
Publication Date: APR. 2002
Revision: C
TE
tmCH
T14L1024N
WRITE CYCLE 1 (OE CLOCK)
t
W C
Ad d r es s
t
W R
OE
t
CW
CE
t
t
AW
WP
W E
t
AS
t
OHZ
(1, 4)
D
OUT
t
t
DH
DW
D
I N
WRITE CYCLE 2 (OE = V
IL
Fixed)
t
W C
CW
Ad d r es s
t
t
WR
CE
t
t
AW
WP
W E
t
t
OH
AS
t
W HZ
t
OW
(1, 4)
(2)
(3)
D
OUT
t
t
DH
DW
D
I N
DON'T CARE
UNDEFINED
TM Technology Inc. reserves the right
to change products or specifications without notice.
P. 7
Publication Date: APR. 2002
Revision: C
TE
tmCH
T14L1024N
Notes: 1. During this period, I/O pins are in the output state, so input signals of opposite phase to the
outputs should not be applied.
2. The data output from DOUT are the same as the data written to DIN during the write cycle.
3. DOUT provides the read data for the next address.
4. Transition is measured ± 500 mV from steady state with CL = 5pF. This parameter is
guaranteed but not 100% tested.
5. If OE is low during a WE controlled write cycle, the write pulse width must be the larger of
t
or (t
+ t ) to allow the I/O drivers to turn off and data to be placed on the bus for the
WHZ DW
WP
required t If OE is high during a WE controlled write cycle, this requirement does
.
DW
not apply and the write pulse can be as short as the specified t
.
WP
TM Technology Inc. reserves the right
to change products or specifications without notice.
P. 8
Publication Date: APR. 2002
Revision: C
TE
tmCH
T14L1024N
PACKAGE DIMENSIONS
32-LEAD SOJ (300 mil)
SYMBOL
DIMENSIONS IN INCHES
DIMENSIONS IN MM
A
A1
A2
B
0.140(MAX)
0.026(MIN)
0.100±0.005
0.018(TYP)
0.028(TYP)
0.008(TYP)
0.823±0.005
0.335±0.010
0.300±0.005
0.050(TYP)
0.086±0.010
0.003(MAX)
3.556(MAX)
0.660(MIN)
2.540±0.127
0.457(TYP)
0.711(TYP)
0.203(TYP)
20.904±0.127
8.509±0.254
7.620±0.127
1.270(TYP)
2.184±0.254
0.076(MAX)
B1
C
D
E
E1
e
L
y
TM Technology Inc. reserves the right
to change products or specifications without notice.
P. 9
Publication Date: APR. 2002
Revision: C
TE
tmCH
T14L1024N
PACKAGE DIMENSIONS
32-LEAD SOJ (400 mil)
SYMBOL
DIMENSIONS IN INCHES
DIMENSIONS IN MM
A
A1
A2
B
0.140(MAX)
0.026(MIN)
0.100±0.005
0.018(TYP)
0.028(TYP)
0.008(TYP)
0.823±0.005
0.440±0.010
0.400±0.005
0.050(TYP)
0.086±0.010
0.003(MAX)
3.556(MAX)
0.660(MIN)
2.540±0.127
0.457(TYP)
0.711(TYP)
0.203(TYP)
20.904±0.127
11.17±0.254
10.16±0.127
1.270(TYP)
2.184±0.254
0.076(MAX)
B1
C
D
E
E1
e
L
y
TM Technology Inc. reserves the right
to change products or specifications without notice.
P. 10
Publication Date: APR. 2002
Revision: C
TE
tmCH
T14L1024N
PACKAGE DIMENSIONS
32-LEAD TSOP-I (8x13.4mm)
SYMBOL Dimension in inches
Dimension in mm
1.10(MAX)
0.05±0.05
1.02(MAX)
0.20±0.10
0.15±0.02
11.8±0.2
0.044(MAX)
0.004±0.002
0.041(MAX)
0.008±0.004
0.006±0.001
0.465±0.008
0.315±0.004
0.528±0.008
0.020(TYP.)
0.020±0.004
0.031±0.008
0.002(MAX)
0° ~ 5°
A
A1
A2
b
C
D
8.0±0.1
E
13.4±0.2
HD
e
0.5(TYP.)
0.5±0.1
L
0.8±0.2
L1
y
0.05(MAX)
0° ~ 5°
θ
TM Technology Inc. reserves the right
to change products or specifications without notice.
P. 11
Publication Date: APR. 2002
Revision: C
TE
tmCH
T14L1024N
PACKAGE DIMENSIONS
32-LEAD TSOP (8x20mm)
SYMBOL
DIMENSIONS IN INCHES
DIMENSIONS IN MM
MIN
NOM
-
MAX
MIN
-
NOM
-
MAX
1.20
0.15
1.05
0.27
0.21
A
A1
A2
b
--
0.047
0.006
0.041
0.011
0.008
0.002
0.035
0.007
0.004
-
0.05
0.90
0.17
0.10
-
0.040
1.00
0.008
0.20
C
0.006
0.15
D
0.787 TYP
0.724 TYP
0.315 TYP
0.024
20.00 TYP
18.40 TYP
8.00 TYP
0.610
Db
E
L
0.020
0.028
0.598
0.622
L1
θ
0.032 TYP
0°~12°
0.813 TYP
0°~12°
TM Technology Inc. reserves the right
to change products or specifications without notice.
P. 12
Publication Date: APR. 2002
Revision: C
TE
tmCH
T14L1024N
PACKAGE DIMENSIONS
36-Ball CSP (8x10mm)
6
5
4
3
2
1
A
B
C
D
E
e
D
D1
F
G
H
e
E
E1
A2
A
SEATING PLANE
A1
Dimension in mm
Symbol
Min
Nom
Max
A
A1
A2
D
D1
E
1.00
0.24
0.60
9.90
-
-
-
-
-
1.35
0.30
-
10.10
5.25 TYP
-
3.75 TYP
0.75 TYP
-
7.90
-
8.10
E1
e
-
-
-
TM Technology Inc. reserves the right
to change products or specifications without notice.
P. 13
Publication Date: APR. 2002
Revision: C
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