UCC3913NG4 [TI]
1-CHANNEL POWER SUPPLY SUPPORT CKT, PDIP8, GREEN, PLASTIC, DIP-8;型号: | UCC3913NG4 |
厂家: | TEXAS INSTRUMENTS |
描述: | 1-CHANNEL POWER SUPPLY SUPPORT CKT, PDIP8, GREEN, PLASTIC, DIP-8 信息通信管理 光电二极管 |
文件: | 总21页 (文件大小:708K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
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SLUS274A – JANUARY 1999 – REVISED APRIL 2003
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FEATURES
DESCRIPTION
D
D
D
D
D
D
D
D
D
Precision Fault Threshold
The UCCx913 family of negative voltage circuit
breakers provides complete power management,
hot-swap, and fault handling capability. The
device is referenced to the negative input voltage
and is driven through an external resistor
connected to ground, which is essentially a
current drive as opposed to the traditional voltage
drive. The on-board 10-V shunt regulator protects
the device from excess voltage and serves as a
reference for programming the maximum
allowable output sourcing current during a fault. In
the event of a constant fault, the internal timer
limits the on-time from less than 0.1% to a
maximum of 3%. The duty cycle modulates
depending on the current into the PL pin, which is
a function of the voltage across the FET, and limits
average power dissipation in the FET. The fault
level is fixed at 50 mV across the current-sense
resistor to minimize total dropout. The fault current
level is set with an external current sense resistor.
The maximum allowable sourcing current is
programmed with a voltage divider from VDD to
generate a fixed voltage on the IMAX pin. The
current level, when the output appears as a
Programmable Average Power Limiting
Programmable Linear Current Control
Programmable Overcurrent Limit
Programmable Fault Time
Fault Output Indicator
Shutdown Control
Undervoltage Lockout
8-Pin SOIC
APPLICATIONS
D
D
D
–48-V Distributed Power Systems
Central Office Switching
Wireless Base Stations
SIMPLIFIED APPLICATION DIAGRAM
R
VDD
R1
DC/DC
Converter
or Load
3
current source, is equal to V
/R
. If
IMAX SENSE
R
PL
desired, a controlled current startup can be
programmed with a capacitor on the IMAX pin.
Power
Limiting
8
When the output current is below the fault level,
the output device is switched on. When the output
current exceeds the fault level, but is less than the
maximum sourcing level programmed by the
IMAX pin, the output remains switched on, and the
fault timer starts charging CT. Once CT charges to
2.5 V, the output device is turned off and performs
a retry some time later. When the output current
reaches the maximum sourcing current level, the
output appears as a current source, limiting the
output current to the set value defined by IMAX.
M1
1
2
Current
Control
7
6
5
Fault
Protection
and
R
S
Timer
C
VDD
UCC3913
4
R2
C
T
Other features of the UCCx913 family include
undervoltage lockout, and 8-pin small outline
(SOIC) and dual-in-line (DIP) packages.
UDG–03059
–VIN
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Copyright 1999 – 2003, Texas Instruments Incorporated
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1
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SLUS274A – JANUARY 1999 – REVISED APRIL 2003
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
ORDERING INFORMATION
(1)
T
PACKAGE
PART NUMBER
UCC2913N
UCC2913D
UCC3913N
UCC3913D
A
PDIP (N)
SOIC (D)
PDIP (N)
SOIC (D)
–40°C to 85°C
–0°C to 70°C
(1)
The N and D packaged are also available taped and reeled.
Add an R suffix to the device type (i.e., UCC2913NR).
ABSOLUTE MAXIMUM RATINGS
over operating free-air temperature range unless otherwise noted
(1)
UCC2923
UCC3913
UNIT
Input voltage
IMAX
VDD
limited to VDD
V
50
10
SHUTDOWN
PL
Input current
mA
10
Operating junction temperature range, T
–55 to 150
–65 to 150
300
J
Storage temperature, T
stg
°C
Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds
(1)
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only,
and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is
not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. All voltages are with respect to
VSS (the most negative voltage). All currents are positive into and negative out of the specified terminal.
RECOMMENDED OPERATING CONDITIONS
MIN NOM MAX UNIT
20 mA
Input current, I
VDD
2
5
N PACKAGE
(TOP VIEW)
D PACKAGE
(TOP VIEW)
SD/FLT
IMAX
VDD
CT
PL
1
2
3
4
8
7
6
5
SD/FLT
IMAX
VDD
CT
PL
1
2
3
4
8
7
6
5
OUT
SENSE
VSS
OUT
SENSE
VSS
2
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SLUS274A – JANUARY 1999 – REVISED APRIL 2003
ELECTRICAL CHARACTERISTICS
T
= –40°C to 85°C for UCC2913, T = 0°C to 70°C for UCC3913, T = T = 2 mA, CT = 4.7 pF, T = T (unless otherwise noted)
I
A
A
J
A, VDD A J
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
INPUT SUPPLY
Minimum input current, VDD
Regulator voltage
1
9.5
7
2
10.5
8
mA
V
2 mA≤ I
SOURCE
≤ 10 mA
8.5
6
Undervoltage lockout off-voltage
FAULT TIMING
T = 25 °C
47.5
46.0
50.0
50.0
50
53.0
53.5
500
–50
J
Overcurrent threshold voltage
Overcurrent input bias
mV
Over temperature
nA
V
CT
= 1.0 V,
I
= 0 A
–22
–36
µA
PL
Timing capacitance charge current
Overload condition,
–0.7
–1.2
–1.7
mA
V
V
– V
IMAX
= 300 mV
SENSE
= 1.0 V,
Timing capacitance discharge current
Timing capacitance fault threshold voltage
Timing capacitance reset threshold voltage
Output duty cycle
I
= 0 A
= 0 A
0.6
2.2
1.0
2.4
1.5
2.6
µA
V
CT
PL
PL
0.32
1.7%
0.50
2.7%
0.62
3.7%
V
Fault condition,
I
OUTPUT
I
I
I
= 0 A
8.5
6
10
8
OUT
OUT
OUT
High-level output voltage
Low-level output voltage
= –1 A
= 0 A,
V
0.01
0.6
V
– V
= 100mV
= 100mV
SENSE
IMAX
IMAX
I
V
= 2 A,
OUT
0.2
– V
SENSE
LINEAR AMPLIFIER
V
V
= 100 mV
= 400 mV
85
100
400
50
115
430
500
IMAX
Sense control voltage
mV
nA
370
IMAX
Input bias
SHUTDOWN/FAULT
Shutdown threshold voltage
Input current
1.4
15
1.7
25
2.0
45
V
V
= 5 V
µA
SD/FLT
High-level output voltage
Low-level output voltage
Delay-to-output time
POWER LIMITING
PL regulator voltage
6.0
7.5
9.0
V
0.01
300
150
ns
I
I
I
= 64 µA
4.35
0.6%
4.85
1.2%
0.1%
5.35
1.7%
V
PL
PL
PL
= 64 µA
Duty cycle control
= 1 mA
0.045%
0.17%
OVERLOAD
Delay-to-output time
Output sink current
Overload threshold voltage
300
100
200
500
260
ns
V
– V
= 300mV
40
mA
mV
SENSE
IMAX
Relataive to I
140
IMAX
3
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SLUS274A – JANUARY 1999 – REVISED APRIL 2003
TERMINAL FUNCTIONS
TERMINAL
I/O
DESCRIPTION
NAME
CT
NO.
4
I
I
A capacitor is connected to this pin in order to set the maximum fault time.
This pin programs the maximum allowable sourcing current.
Output drive to the MOSFET pass element.
IMAX
OUT
2
7
O
I
PL
8
This feature ensures that the average MOSFET power dissipation is controlled.
Input voltage from the current sense resistor.
SENSE
SD/FLT
VDD
6
I
1
O
O
O
This pin provides fault output indication and shutdown control.
Current driven with a resistor to a voltage at least 10V more positive than VSS.
Ground reference for the device and the most negative voltage available.
3
VSS
5
DETAILED PIN DESCRIPTIONS
CT
A capacitor connected to this pin allows setting of the maximum fault time. The maximum fault time must be
more than the time to charge external load capacitance. The maximum fault time is defined as:
ǒ2 CTǓ
t
+
FAULT
I
CH
(1)
(2)
where
I
+ 36 mA ) I
PL
CH
and I is the current into the power limit pin. Once the fault time is reached the output shuts down for a time
PL
given by:
6
t
+ 2 10 C
SD
T
(3)
IMAX
This pin programs the maximum allowable sourcing current. Since V
is a regulated voltage, a voltage divider
DD
can be derived from V
to generate the program level for the IMAX pin. The current level at which the output
DD
appears as a current source is equal to the voltage on the IMAX pin over the current sense resistor. If desired,
a controlled current startup can be programmed with a capacitor on the IMAX pin, and a programmed start delay
can be achieved by driving the shutdown with an open collector/drain device into an R-C network.
PL
This pin’s feature ensures that the average MOSFET power dissipation is controlled. A resistor is connected
from this pin to the drain of the N-channel MOSFET pass element. When the voltage across the N-channel
MOSFET exceeds 5 V, current flows into the PL pin which adds to the fault timer charge current, reducing the
duty cycle from the 3% level. When I is much greater 36 µA, then the average MOSFET power dissipation
PL
is given by:
*6
P
+ IMAX 1 10
R
PL
FET(avg)
(4)
SENSE
Input voltage from the current sense resistor. When there is greater than 50 mV across this pin with respect to
VSS, a fault is sensed, and C starts to charge.
T
4
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SLUS274A – JANUARY 1999 – REVISED APRIL 2003
DETAILED PIN DESCRIPTIONS (continued)
SD/FLT
This pin provides fault output indication and shutdown control. Interface into and out of this pin is usually
performed through level shift transistors. When 20 µA is sourced into this pin, shutdown drives high causing the
output to disable the N-channel MOSFET pass device. When opened, and under a non-fault condition, the
SD/FLT pin pulls to a low state. When a fault is detected by the fault timer, or undervoltage lockout, this pin drives
to a high state, indicating the output MOSFET is off.
VDD
Current driven with a resistor to a voltage at least 10-V more positive than VSS. Typically a resistor is connected
to ground. The 10-V shunt regulator clamps VDD at 10 V above the VSS pin, and is also used as an output
reference to program the maximum allowable sourcing current.
BLOCK DIAGRAM
VDD
3
IMAX
2
UVLO
1= UNDERVOLTAGE
8
7
PL
LOGIC
SUPPLY
5.0V
REF
V
DD
V
DD
–
9.5-V SHUNT
REGULATOR
0.2 V
+
5.0 V
+
–
V
DD
OUT
–
+
LINEAR
CURRENT
AMPLIFIER
50
OVERLOAD COMPARATOR
DISABLE
SD/FLT
1
6
5
SENSE
VSS
+
ON–TIME
CONTROL
50 mV
SOURCE
ONLY
–
20 µA
OVERCURRENT
COMPARATOR
4
CT
UDG–99001
5
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SLUS274A – JANUARY 1999 – REVISED APRIL 2003
APPLICATION INFORMATION
Typical Fault Mode
Figure 1 shows the detailed circuitry for the fault timing function of the UCCx913. This initial discussion of the
typical fault mode ignores the overload comparator, and current source I3. Once the voltage across the current
sense resistor, R , exceeds 50 mV, a fault has occurred. This causes the timing capacitor to charge with a
S
combination of 36 µA plus the current from the power limiting amplifier. The PL amplifier is designed to source
current into the CT pin only and to begin sourcing current once the voltage across the output FET exceeds 5 V.
The current I is related to the voltage across the FET with the following expression:
PL
V
* 5 V
FET
I
+
PL
R
PL
(5)
where V
is the voltage across the N-channel MOSFET pass device.
FET
(How this feature limits average power dissipation in the pass device is described in further detail in the following
sections). Note that under a condition where the output current is more than the fault level, but less than the
maximum level, V
≈ V (input voltage), I = 0, the C charging current is 36 µA.
OUT
SS
PL
T
LOAD
0.2 V
OVERLOAD COMPARATOR
I3
IMAX
PL
V
DD
–
R
PL
SENSE
8
+
I1
36 µA
–
1mA
+
5.0 V
TO OUTPUT
DRIVE
OUTPUT
OVERCURRENT
COMPARATOR
H=OFF
SENSE
6
5
2.5 V
H=CLOSE
+
–
50 mV
–
+
S
R
Q
Q
R
H=CLOSE
S
VSS
I2
1 µA
–
0.5 V
+
VSS
INPUT VOLTAGE
CT
FAULT TIMING CIRCUITRY
4
C
T
UDG–99004
VSS
Figure 1. Fault Timing Circuitry Including Power Limit and Overload Comparator
6
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SLUS274A – JANUARY 1999 – REVISED APRIL 2003
APPLICATION INFORMATION
During a fault, C charges at a rate determined by the internal charging current and the external timing capacitor.
T
Once C charges to 2.5 V, the fault comparator switches and sets the fault latch. Setting of the fault latch causes
T
both the output to switch off and the charging switch to open. C must now discharge with the 1-µA current
T
source, I2, until 0.5 V is reached. Once the voltage at CT reaches 0.5 V, the fault latch resets, which re-enables
the output and allows the fault circuitry to regain control of the charging switch. If a fault is still present, the fault
comparator closes the charging switch causing the cycle to begin. Under a constant fault, the duty cycle is given
by:
1 mA
) 36 mA
Duty Cycle +
I
PL
(6)
Average power dissipation in the pass element is given by:
1 mA
) 36 mA
ǒ Ǔ
P
+ V
IMAX
FET
FET(avg)
I
PL
(7)
(8)
(9)
Where VFET >> 5 V I can be approximated as :
PL
V
FET
I
^
PL
R
PL
and where I >> 36 µA, the duty cycle can be approximated as :
PL
1 mA R
PL
Duty Cycle +
V
FET
Therefore, the maximum average power dissipation in the MOSFET can be approximated by:
1 mA R
PL
ǒ Ǔ+ IMAX 1 mA R
P
+ V
IMAX
FET
FET(avg)
PL
V
FET
(10)
Notice that in the approximation, V
MOSFET pass element.
cancels. therefore, average power dissipation is limited in the N-channel
FET
Overload Comparator
The linear amplifier in the UCCx913 ensures that the output N-channel MOSFET does not pass more than I
MAX
(which is V
/R ). In the event the output current exceeds the programmed IMAX by 0.2 V/R which can only
IMAX
S S(
occur if the output MOSFET is not responding to a command from the device) the CT pin begins charging with
I3, 1 mA, and continue to charge to approximately 8 V. This allows a constant fault to show up on the SD/FLT
pin, and also since the voltage on CT charges past 2.5 V only in an overload fault mode, it can be used for
detection of output FET failure or to build in redundancy in the system.
7
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SLUS274A – JANUARY 1999 – REVISED APRIL 2003
APPLICATION INFORMATION
Determining External Component Values (See FIgure 2)
To set R
V
the following must be achieved:
VDD
IN(min)
10 V
u
) 2 mA
(
)
R
R1 ) R2
VDD
(11)
In order to estimate the minimum timing capacitor, C , several things must be taken into account. For example,
T
given the schematic below as a possible (and at this point, a standard) application, certain external component
values must be known in order to estimate C
.
T(min)
Then use the given the values of C
IMAX pin, to calculate the approximate startup time of the node V
, Load, R
, VSS, and the resistors determining the voltage on the
OUT
SENSE
. This startup time must be faster than the
OUT
time it takes for CT to charge to 2.5 V (relative to VSS), and is the basis for estimating the minimum value of
CT. In order to determine the value of the sense resistor, R , assuming the user has determined the fault
SENSE
current, R
can be calculated by:
SENSE
50 mV
R
+
SENSE
I
FAULT
(12)
is the maximum current that the device allows through the transistor, M1,
Next, calculate the variable I
. I
MAX MAX
and during startup with an output capacitor the power MOSFET, M1, can be modeled as a constant current
source of value I
where:
MAX
V
IMAX
I
+
MAX
R
SENSE
(13)
where V
= voltage on IMAX pin.
IMAX
R
VDD
3
VDD
V
OUT
R
PL
R1
PL
8
M1
C
OUT
OUT
7
6
5
2
IMAX
SENSE
LOAD
R
SENSE
R2
VSS
UCC3913
VSS
Note: LOAD = I
LOAD
For Current Source Load
For Resistive Load
LOAD = R
OUT
UDG–03045
Figure 2. External Component Connections
8
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SLUS274A – JANUARY 1999 – REVISED APRIL 2003
APPLICATION INFORMATION
TIMING DIAGRAM
I
OUT
MAX
I
I
FAULT
Output
Current
Io(nom)
t
t
t
0A
VCT
2.5V
C
T
Voltage
(w/respect to VSS)
0.5V
0V
V
OUT
0V
Output
Voltage
(w/respect to GND)
VSS
t
0
t
1
t
2
t
3
t
4
t
5
t
6
t
7
t
8
t9 t10
TIME
DESCRIPTION
Safe condition. Output current is nominal, output voltage is at the negative rail, VSS.
t0
Fault control reached. Output current reaches the programmed fault value. CT begins to charge at approximately
t1
t2
t3
t4
36-µA.
Maximum current reached. Output current reaches the programmed maximum level and becomes a constant current
with value IMAX.
Fault occurs. CT has charged to 2.5V. Fault output goes high. The FET turns off allowing no output current to flow.
VOUT floats up to ground.
Retry. CT has discharged to 0.5 V, but fault current is still exceeded, CT begins charging again, FET is on, V
down to VSS.
pulled
OUT
t5
t6
t5 = t3. Illustrates 3% duty cycle.
t6 = t4
Output short circuit. If V
OUT
is short circuited to ground, CT charges at a higher rate depending upon the values for
t7
VSS and R
.
PL
t8
t9
Fault occurs. Output is still short circuited, but the occurrence of a fault turns the FET off so no current is conducted.
t9 = t4. Output short circuit released, still in fault mode.
t10
t10 = t0. Fault released. Safe condition. Return to normal operaton of the circuit breaker.
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SLUS274A – JANUARY 1999 – REVISED APRIL 2003
APPLICATION INFORMATION
C
VDD
R1
R2
VSS
R
VDD
C
SS
VDD
IMAX
OUTPUT
T
3
2
PL
8
7
UVLO
1 = UNDERVOLTAGE
LOGIC
SUPPLY
5.0 V
REF
R
V
DD
V
DD
–
9.5 SHUNT
REGULATOR
+
OUT
+
–
V
DD
LINEAR
CURRENT
AMPLIFIER
–
+
50 Ω
DISABLE
SD/FLT
1
SENSE
VSS
6
5
+
ON–TIME
CONTROL
SOURCE
ONLY
–
FAULT=
50 mV
R
S
20 µA
C
T
4
CT
VSS
UDG–99002
Figure 3. Typical Application Diagram
To calculate the startup time using the current source load.
C
I
|VSS|
OUT
t
+
START
* I
MAX
LOAD
(14)
(15)
To calculate the startup time using the resistive load.
I
R
MAX
R
OUT
ln ǒ
Ǔ
t
+ C
R
OUT OUT
START
I
* |VSS|
MAX
OUT
10
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SLUS274A – JANUARY 1999 – REVISED APRIL 2003
APPLICATION INFORMATION
Once t
is calculated, the power limit feature of the UCCx913 must be addressed and component values
START
derived. Assuming the designer chooses to limit the maximum allowable average power that is associated with
the circuit breaker, the power limiting resistor, R , can be easily determined by the following:
PL
P
FET(avg)
R
+
PL
1 mA I
MAX
(16)
(17)
where a minimum R exists defined by
PL
|VSS|
R
+
PL(min)
10mA
Finally, after computing the aforementioned variables, the minimum timing capacitor can be derived for a current
source load with the following equation.
ǒ98 mA R ) |VSS| * 10 VǓ
t
START
PL
C
+
T(min)
4 V R
PL
(18)
(19)
The minimum timing capacitor can be derived for a resistive load with the following equation.
C
+
T(min)
ǒ49 mA R
OUTǓ ) R
OUT
t
) |VSS| * 5 V * I
R
C
|VSS|
OUT
START
PL
MAX
2 V R
PL
AVERAGE POWER DISSIPATION
vs
MOSFET VOLTAGE
25.0
I
= 4 A
MAX
R
= ∞
PL
22.5
UCC2913
UCC3913
LOCAL VDD
20.0
17.5
R3
R4
SHUTDOWN
FAULT OUT
R
= 10 MΩ
PL
15.0
12.5
10.0
R
= 500 kΩ
PL
R
= 5 MΩ
PL
LOCAL GND
R
= 200 kΩ
PL
LEVEL SHIFT
7
SD/FLT
7.5
R
= 2 MΩ
= 1 MΩ
PL
PL
5.0
2.5
VSS
R
UDG–99003
0
0
25
50
75
100 125 150 175 200
V
FET
– MOSFET Voltage– V
Figure 5
Figure 4. Possible Level Shift Circuitry Interface
11
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SLUS274A – JANUARY 1999 – REVISED APRIL 2003
SAFETY RECOMMENDATION
Although the UCC3913 is designed to provide system protection for all fault conditions, all integrated circuits
can ultimately fail short. For this reason, if the UCC3913 is intended for use in safety critical applications where
UL or some other safety rating is required, a redundant safety device such as a fuse should be placed in series
with the device. The UCC3913 will prevent the fuse from blowing for virtually all fault conditions, increasing
system reliability and reducing maintenance cost, in addition to providing the hot swap benefits of the device.
12
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PACKAGE OPTION ADDENDUM
www.ti.com
17-May-2014
PACKAGING INFORMATION
Orderable Device
UCC2913D
Status Package Type Package Pins Package
Eco Plan
Lead/Ball Finish
MSL Peak Temp
Op Temp (°C)
-40 to 85
Device Marking
Samples
Drawing
Qty
(1)
(2)
(6)
(3)
(4/5)
ACTIVE
SOIC
SOIC
SOIC
SOIC
D
8
8
8
8
75
Green (RoHS
& no Sb/Br)
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
UCC2913
UCC2913DG4
UCC2913DTR
UCC2913DTRG4
ACTIVE
ACTIVE
ACTIVE
D
D
D
75
Green (RoHS
& no Sb/Br)
-40 to 85
UCC2913
UCC2913
UCC2913
2500
2500
Green (RoHS
& no Sb/Br)
-40 to 85
Green (RoHS
& no Sb/Br)
-40 to 85
UCC2913J
UCC2913N
UCC2913NG4
UCC3913D
OBSOLETE
OBSOLETE
OBSOLETE
ACTIVE
CDIP
PDIP
PDIP
SOIC
JG
P
8
8
8
8
TBD
TBD
TBD
Call TI
Call TI
Call TI
Call TI
-40 to 85
-40 to 85
-40 to 85
0 to 70
UCC2913N
P
Call TI
Call TI
D
75
75
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
UCC3913
UCC3913
UCC3913
UCC3913
UCC3913N
UCC3913DG4
UCC3913DTR
ACTIVE
ACTIVE
ACTIVE
SOIC
SOIC
SOIC
D
D
D
8
8
8
Green (RoHS
& no Sb/Br)
CU NIPDAU
CU NIPDAU
CU NIPDAU
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
0 to 70
0 to 70
0 to 70
2500
2500
Green (RoHS
& no Sb/Br)
UCC3913DTRG4
Green (RoHS
& no Sb/Br)
UCC3913N
OBSOLETE
OBSOLETE
PDIP
PDIP
P
P
8
8
TBD
TBD
Call TI
Call TI
Call TI
Call TI
0 to 70
0 to 70
UCC3913NG4
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
17-May-2014
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
14-Jul-2012
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
UCC2913DTR
UCC3913DTR
SOIC
SOIC
D
D
8
8
2500
2500
330.0
330.0
12.4
12.4
6.4
6.4
5.2
5.2
2.1
2.1
8.0
8.0
12.0
12.0
Q1
Q1
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
14-Jul-2012
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SPQ
Length (mm) Width (mm) Height (mm)
UCC2913DTR
UCC3913DTR
SOIC
SOIC
D
D
8
8
2500
2500
367.0
367.0
367.0
367.0
35.0
35.0
Pack Materials-Page 2
MECHANICAL DATA
MCER001A – JANUARY 1995 – REVISED JANUARY 1997
JG (R-GDIP-T8)
CERAMIC DUAL-IN-LINE
0.400 (10,16)
0.355 (9,00)
8
5
0.280 (7,11)
0.245 (6,22)
1
4
0.065 (1,65)
0.045 (1,14)
0.310 (7,87)
0.290 (7,37)
0.063 (1,60)
0.015 (0,38)
0.020 (0,51) MIN
0.200 (5,08) MAX
0.130 (3,30) MIN
Seating Plane
0.023 (0,58)
0.015 (0,38)
0°–15°
0.100 (2,54)
0.014 (0,36)
0.008 (0,20)
4040107/C 08/96
NOTES: A. All linear dimensions are in inches (millimeters).
B. This drawing is subject to change without notice.
C. This package can be hermetically sealed with a ceramic lid using glass frit.
D. Index point is provided on cap for terminal identification.
E. Falls within MIL STD 1835 GDIP1-T8
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