UCC2817-EP [TI]
BiCMOS POWER-FACTOR PREREGULATOR; 的BiCMOS功率因数前置稳压器
| 型号： | UCC2817-EP |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | BiCMOS POWER-FACTOR PREREGULATOR |
| 文件： | 总23页 (文件大小：599K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
UCC2817-EP
UCC2818-EP
www.ti.com ........................................................................................................................................................................................... SLUS716–DECEMBER 2008
BiCMOS POWER-FACTOR PREREGULATOR
1
FEATURES
2
•
Controls Boost Preregulator to Near-Unity
Power Factor
SUPPORTS DEFENSE, AEROSPACE,
AND MEDICAL APPLICATIONS
•
•
•
•
Controlled Baseline
One Assembly/Test Site
One Fabrication Site
Available in Military (–55°C/125°C)
Temperature Range(1)
Extended Product Life Cycle
Extended Product-Change Notification
Product Traceability
•
•
•
•
•
•
•
•
•
•
•
Limits Line Distortion
World-Wide Line Operation
Overvoltage Protection
Accurate Power Limiting
Average Current Mode Control
Improved Noise Immunity
Improved Feed-Forward Line Regulation
Leading Edge Modulation
150-µA Typical Start-Up Current
Low-Power BiCMOS Operation
12-V to 17-V Operation
•
•
•
D, DW, N, or PW PACKAGE
(TOP VIEW)
GND
PKLMT
CAOUT
CAI
MOUT
IAC
DRVOUT
VCC
CT
1
2
3
4
5
6
7
8
16
15
14
13
12
11
SS
RT
VSENSE
VAOUT
VFF
10 OVP/EN
VREF
9
(1) Additional temperature ranges are available - contact factory
DESCRIPTION/ORDERING INFORMATION
The UCC2817 and UCC2818 provides all the functions necessary for active power-factor-corrected
preregulators. The controller achieves near-unity power factor by shaping the ac-input line current waveform to
correspond to that of the ac input line voltage. Average current mode control maintains stable, low-distortion
sinusoidal line current.
Designed with TI's BiCMOS process, the UCC2817 and UCC2818 offers new features, such as lower start-up
current, lower power dissipation, overvoltage protection, a shunt UVLO detect circuitry, a leading-edge
modulation technique to reduce ripple current in the bulk capacitor, and an improved, low-offset (±2-mV) current
amplifier to reduce distortion at light load conditions.
The UCC2817 offers an on-chip shunt regulator with low start-up current suitable for applications utilizing a
bootstrap supply. The UCC2818 is intended for applications with a fixed supply (VCC).
The devices are available in a 16-pin D package.
ORDERING INFORMATION
TA = TJ
PACKAGE(1)
ORDERABLE PART NUMBER
TURN-ON THRESHOLD
–55°C to 125°C
SOIC – D
Reel
UCC2818MDREP
10.2 V
(1) Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at
www.ti.com/sc/package.
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
2
Unitrode is a trademark of Texas Instruments.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2008, Texas Instruments Incorporated
UCC2817-EP
UCC2818-EP
SLUS716–DECEMBER 2008 ........................................................................................................................................................................................... www.ti.com
BLOCK DIAGRAM
VCC
15
OVP/EN 10
7.5-V
Reference
16 V (For UCC2817 Only)
9
VREF
SS 13
UVLO
1.9 V
ENABLE
−
+
VAOUT
7
16 V/10 V (UCC2817)
10.5 V/10 V (UCC2818)
Zero Power
0.33 V
VCC
−
+
Voltage
Error Amplifier
VSENSE 11
−
+
Current
Amplifier
8 V
OVP
Q
+
−
7.5 V
X
P
Mult
−
+
16 DRVOUT
PWM
−
+
X
S
2
VFF
8
X
PWM
Latch
OSC
CLK
R
R
Mirror
2:1
1
2
GND
CLK
Oscillator
IAC
6
5
PKLMT
−
+
MOUT
4
3
12
14
CAI
CAOUT RT
CT
UDG-98182
2
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Pin Descriptions
CAI: Current amplifier noninverting input. Place a resistor between this pin and the GND side of current sense
resistor. This input and the inverting input (MOUT) remain functional down to and below GND.
CAOUT: Current amplifier output. This is the output of a wide bandwidth operational amplifier that senses line
current and commands the PFC pulse-width modulator (PWM) to force the correct duty cycle. Compensation
components are placed between CAOUT and MOUT.
CT: Oscillator timing capacitor. A capacitor from CT to GND sets the PWM oscillator frequency according to:
0.6
RT CT
f [ ǒ
Ǔ
The lead from the oscillator timing capacitor to GND should be as short and direct as possible.
DRVOUT: Gate drive. The output drive for the boost switch is a totem-pole MOSFET gate driver on DRVOUT.
Use a series gate resistor to prevent interaction between the gate impedance and the output driver that might
cause the DRVOUT to overshoot excessively. See characteristic curve (Figure 13) to determine minimum
required gate resister value. Some overshoot of the DRVOUT output is always expected when driving a
capacitive load.
GND: Ground. All voltages measured with respect to ground. VCC and REF should be bypassed directly to GND
with a 0.1-µF or larger ceramic capacitor.
IAC: Current proportional to input voltage. This input to the analog multiplier is a current proportional to
instantaneous line voltage. The multiplier is tailored for very low distortion from this current input (IIAC) to
multiplier output. The recommended maximum IIAC is 500 µA.
MOUT: Multiplier output and current amplifier inverting input. The output of the analog multiplier and the inverting
input of the current amplifier are connected together at MOUT. As the multiplier output is a current, this is a
high-impedance input so the amplifier can be configured as a differential amplifier. This configuration improves
noise immunity and allows for the leading-edge modulation operation. The multiplier output current is limited to (2
× IIAC). The multiplier output current is given by the equation:
I
(V
* 1)
IAC
+
VAOUT
I
MOUT
2
V
K
VFF
Where:
K = 1/V is the multiplier gain constant
OVP/EN: Over-voltage/enable. A window comparator input that disables the output driver if the boost output
voltage is a programmed level above the nominal, or disables both the PFC output driver and resets SS if pulled
below 1.9 V (typ).
PKLMT: PFC peak current limit. The threshold for peak limit is 0 V. Use a resistor divider from the negative side
of the current sense resistor to VREF to level shift this signal to a voltage level defined by the value of the sense
resistor and the peak current limit. Peak current limit is reached when PKLMT voltage falls below 0 V.
RT: Oscillator charging current. A resistor from RT to GND is used to program oscillator charging current. A
resistor between 10 kΩ and 100 kΩ is recommended. Nominal voltage on this pin is 3 V.
SS: Soft-start. VSS is discharged for VVCC low conditions. When enabled, SS charges an external capacitor with a
current source. This voltage is used as the voltage error signal during start-up, enabling the PWM duty cycle to
increase slowly. In the event of a VVCC dropout, the OVP/EN is forced below 1.9 V (typ), SS quickly discharges to
disable the PWM.
Note: In an open-loop test circuit, grounding the SS pin does not ensure 0% duty cycle. Please see the
application section for details.
VAOUT: Voltage amplifier output. This is the output of the operational amplifier that regulates output voltage. The
voltage amplifier output is internally limited to approximately 5.5 V to prevent overshoot.
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VCC: Positive supply voltage. Connect to a stable source of at least 20 mA between 10 V and 17 V for normal
operation. Bypass VCC directly to GND to absorb supply current spikes required to charge external MOSFET gate
capacitances. To prevent inadequate gate drive signals, the output devices are inhibited unless VVCC exceeds
the upper under-voltage lockout voltage threshold and remains above the lower threshold.
VFF: Feed-forward voltage. The RMS voltage signal generated at this pin by mirroring 1/2 of the IIAC into a single
pole external filter. At low line, the VFF voltage should be 1.4 V.
VSENSE: Voltage amplifier inverting input. This is normally connected to a compensation network and to the
boost converter output through a divider network.
VREF: Voltage reference output. VREF is the output of an accurate 7.5-V voltage reference. This output is
capable of delivering 20 mA to peripheral circuitry and is internally short-circuit current limited. VREF is disabled
and remains at 0 V when VVCC is below the UVLO threshold. Bypass VREF to GND with a 0.1-µF or larger
ceramic capacitor for best stability. Please refer to Figure 8 and Figure 9 for VREF line and load regulation
characteristics.
ABSOLUTE MAXIMUM RATINGS(1)
over operating free-air temperature range (unless otherwise noted)
MIN
MAX UNIT
VCC
ICC
Supply voltage
18
20
0.2
1.2
8
V
mA
A
Supply current
Gate drive current, continuous
Gate drive current
A
CAI, MOUT, SS
PKLMT
Input voltage
5
V
VSENSE, OVP/EN
RT, IAC, PKLMT
VCC (no switching)
DRVOUT, PKLMT, MOUT
10
10
20
–0.5
1
Input current
mA
Maximum negative voltage
Power dissipation
V
W
θJA
TJ
Package thermal impedance
Junction temperature
Storage temperature range
Lead temperature
°C/W
°C
–55
–65
150
150
300
Tstg
Tsol
°C
Soldering, 10 s
°C
(1) Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating
conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
THERMAL RESISTANCE
PACKAGE
θJC(°C/W)
θJA(°C/W)
SOIC-16 (D)
22
40 to 70(1)
(1) Specified θJA (junction to ambient) is for devices mounted to 5-in2 FR4 PC board with 1-oz copper, where noted. When resistance range
is given, lower values are for 5-in2 aluminum PC board. Test PWB was 0.062-in thick and typically used 0,635-mm trace widths for
power packages and 1,3-mm trace widths for nonpower packages with a 100-mil × 100-mil probe land area at the end of each trace.
4
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ELECTRICAL CHARACTERISTICS
TA = –55°C to 125°C, TA = TJ, VCC = 12 V, RT = 22 kΩ, CT = 270 pF (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX UNIT
Supply Current
Supply current, off
VCC = (VCC turn-on threshold –
0.3 V)
150
4
300 µA
Supply current, on
VCC = 12 V, No load on
DRVOUT
2
6
mA
UVLO
VCC turn-on threshold
VCC turn-off threshold
UVLO hysteresis
UCC2817
UCC2817
UCC2817
UCC2817
UCC2818
UCC2818
UCC2818
15.4
9.4
16
9.7
6.3
17
16.6
V
V
V
V
V
V
V
5.8
Maximum shunt voltage
VCC turn-on threshold
VCC turn-off threshold
UVLO hysteresis
15.4
9.7
17.5
10.9
10.2
9.7
0.5
9.4
0.3
Voltage Amplifier
Input voltage
7.309
7.5
50
90
5.5
50
7.691
V
VSENSE bias current
Open-loop gain
VSENSE = VREF, VAOUT = 2.5 V
VAOUT = 2 V to 5 V
IL = –150 µA
200 nA
dB
50
5.3
0
High-level output voltage
Low-level output voltage
5.6
V
IL = 150 µA
150 mV
Overvoltage Protection and Enable
VREF +
0.48
VREF +
0.5
VREF +
0.52
Overvoltage reference
V
Hysteresis
Enable threshold
Enable hysteresis
Current Amplifier
Input offset voltage
Input bias current
Input offset current
Open-loop gain
300
1.7
0.1
500
1.9
0.2
600 mV
2.1
0.3
V
V
VCM = 0 V, VCAOUT = 3 V
VCM = 0 V, VCAOUT = 3 V
VCM = 0 V, VCAOUT = 3 V
VCM = 0 V, VCAOUT = 2 V to 5 V
–3.5
0
–50
25
2.5 mV
–100 nA
100 nA
dB
86
55
VCM = 0 V to 1.5 V,
VCAOUT = 3 V
Common-mode rejection ratio
80
dB
High-level output voltage
Low-level output voltage
Gain bandwidth product(1)
Voltage Reference
Input voltage
IL = –120 mA
IL = 1 mA
5.6
0.1
6.5
0.2
2.5
6.9
0.5
V
V
MHz
7.3
0
7.5
7.65
V
Load regulation
IREF = 1 mA to 2 mA
VCC = 10.8 V to 15 V(2)
VREF = 0 V
10 mV
10 mV
–50 mA
Line regulation
0
Short-circuit current
Oscillator
–20
–25
100
Initial accuracy
TA = 25°C
85
–1.5%
80
115 kHz
Voltage stability
VCC = 10.8 V to 15 V
Line, temperature
1.5%
120 kHz
5.5
Total variation
Ramp peak voltage
4.5
5
V
(1) Ensured by design, not production tested.
(2) Reference variation for VCC < 10.8 V is shown in Figure 8.
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ELECTRICAL CHARACTERISTICS (continued)
TA = –55°C to 125°C, TA = TJ, VCC = 12 V, RT = 22 kΩ, CT = 270 pF (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX UNIT
4.5
Ramp amplitude voltage (peak
to peak)
3.5
4
V
Peak Current Limit
PKLMT reference voltage
PKLMT propagation delay
–15
150
15 mV
500 ns
350
Multiplier
High line, low power output
current
IAC = 500 µA, VFF = 4.7 V,
VAOUT = 1.25 V
11
–53
–8
–6
–90
–19
–300
–300
1
–33
High-line, high-power output
current
IAC = 500 µA, VFF = 4.7 V,
VAOUT = 5 V
–112
Low-line, low-power output
current
IAC = 150 µA, VFF = 1.4 V,
VAOUT = 1.25 V
IMOUT
–50 µA
–350
Low-line, high-power output
current
IAC = 150 µA, VFF = 1.4 V,
VAOUT = 5 V
–268
–250
0.5
IAC = 150 µA, VFF = 1.3 V,
VAOUT = 5 V
IAC limited output current
Gain constant (K)
–400
IAC = 200 µA, VFF = 3 V,
VAOUT = 2.5 V
1.6 1/V
–2
IAC = 150 µA, VFF = 1.4 V,
VAOUT = 0.25 V
0
IAC = 500 µA, VFF = 4.7 V,
VAOUT = 0.25 V
IMOUT
Zero current
0
–2 µA
–3.5
IAC = 500 µA, VFF = 4.7 V,
VAOUT = 0.5 V
0
IAC = 150 µA, VFF = 1.4 V,
VAOUT = 5 V
Power limit (IMOUT × VFF
)
–375
–420
–490 µW
Feed Forward
VFF output current
IAC = 300 µA
–140
–6
–150
–10
–160 µA
–16 µA
Soft Start
Softstart charge current
Gate Driver
Pullup resistance
IO = –100 mA to –200 mA
IO = 100 mA
5
2
12
10
Ω
Ω
Pulldown resistance
CL = 1 nF, RL = 10 Ω,
VDRVOUT = 0.7 V to 9 V
Output rise time
25
50 ns
50 ns
CL = 1 nF, RL = 10 Ω,
VDRVOUT = 9 V to 0.7 V
Output fall time
10
Maximum duty cycle
93%
0.2
95%
99%
Minimum controlled duty cycle
Zero Power
At 100 kHz
2%
Zero-power comparator
threshold
Measured on VAOUT
0.33
0.5
V
6
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APPLICATION INFORMATION
The UCC2817 is a BiCMOS average current mode boost controller for high-power-factor, high-efficiency,
preregulator power supplies. Figure 1 shows the UCC2817 in a 250-W PFC preregulator circuit. Off-line
switching power converters normally have an input current that is not sinusoidal. The input current waveform has
a high harmonic content because current is drawn in pulses at the peaks of the input voltage waveform. An
active power-factor correction circuit programs the input current to follow the line voltage, forcing the converter to
look like a resistive load to the line. A resistive load has 0° phase displacement between the current and voltage
waveforms. Power factor (PF) can be defined in terms of the phase angle between two sinusoidal waveforms of
the same frequency:
PF = cos θ
Therefore, a purely resistive load would have a power factor of 1. In practice, power factors of 0.999 with total
harmonic distortion (THD) of less than 3% are possible with a well-designed circuit. Following guidelines are
provided to design PFC boost converters using the UCC2817.
NOTE: Schottky diodes, D5 and D6, are required to protect the PFC controller from electrical over stress during
system power up.
C10
1 µ F
C11
1 µF
R16
Ω
100
VCC
R15
24k
D7
D8
R21
R13
383k 383k
L1
IAC
1mH
R18
24k
V
D1
8A, 600V
O
F1
AC2
+
D2
6A, 600V
C14
C13
F
µ
0.47
600V
V
F
µ
1.5
400V
LINE
85−270 V
AC
V
Q1
IRFP450
OUT
D3
C12
220µF
385V−DC
AC1
R14
0.25
Ω
450V
3W
6A 600V
−
R17
Ω
20
UCC2817
R9
4.02k
R10
4.02k
R12
2k
1
2
GND
DRVOUT 16
D4
VCC
C3
PKLIMIT
µ
1
F CER
D5
VCC 15
R11
10k
3
4
5
CAOUT
CAI
C2
100
µ F AI EI
C1
560pF
V
REF
MOUT
CT 14
SS 13
C9 1.2nF
R8 12k
µ
C4 0.01 F
6
IAC
C8 270pF
R1 12k
RT 12
C7 150nF
D6
µ
R7 100k C15 2.2
F
VSENSE 11
V
R2
499k
R19
499k
O
R3 20k
7
8
VAOUT
VFF
C6 2.2µF
R4
249k
R20 274k
OVP/EN 10
R5
10k
R6 30k
µF
1
C5
VREF
9
V
UDG-98183
REF
Figure 1. Typical Application Circuit
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Power Stage
LBOOST: The boost inductor value is determined by:
ǒVIN(min) DǓ
+
L
BOOST
(
)
DI fs
Where:
D = Duty cycle
ΔI = Inductor ripple current
fS = Switching frequency
For the example circuit, a switching frequency of 100 kHz, a ripple current of 875 mA, a maximum duty cycle of
0.688, and a minimum input voltage of 85 VRMS produces a boost inductor value of about 1 mH. The values used
in this equation are at the peak of low line, where the inductor current and its ripple are at a maximum.
COUT: Two main criteria, the capacitance and the voltage rating, dictate the selection of the output capacitor. The
value of capacitance is determined by the holdup time required for supporting the load after input ac voltage is
removed. Holdup is the amount of time that the output stays in regulation after the input has been removed. For
this circuit, the desired holdup time is approximately 16 ms. Expressing the capacitor value in terms of output
power, output voltage, and holdup time gives the equation:
ǒ2 P DtǓ
OUT
C
+ ǒV
OUT(min) Ǔ
OUT
2
2
* V
OUT
In practice, the calculated minimum capacitor value may be inadequate because output ripple voltage
specifications limit the amount of allowable output capacitor ESR. Attaining a sufficiently low value of ESR often
necessitates the use of a much larger capacitor value than calculated. The amount of output capacitor ESR
allowed can be determined by dividing the maximum specified output ripple voltage by the inductor ripple current.
In this design holdup time was the dominant determining factor and a 220-µF, 450-V capacitor was chosen for
the output voltage level of 385 VDC at 250 W.
Power switch selection: As in any power-supply design, tradeoffs between performance, cost, and size have to
be made. When selecting a power switch, it can be useful to calculate the total power dissipation in the switch for
several different devices at the switching frequencies being considered for the converter. Total power dissipation
in the switch is the sum of switching loss and conduction loss. Switching losses are the combination of the gate
charge loss, COSS loss, and turnon and turnoff losses:
PGATE = QGATE × VGATE × fs
1
2
2
P
+
C
V
fs
) t
COSS
OSS
OFF
1
2
I ǒtON
Ǔ
P
) P
+
V
fs
ON
OFF
OFF
L
OFF
8
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Where:
QGATE = Total gate charge
VGATE = Gate drive voltage
fS = Clock frequency
COSS = Drain source capacitance of the MOSFET
IL = Peak inductor current
tON and tOFF = Switching times (estimated using device parameters RGATE, QGD and VTH
)
VOFF = Voltage across the switch during the off time (in this case VOFF = VOUT
)
Conduction loss is calculated as the product of the RDS(on) of the switch (at the worst-case junction temperature)
and the square of RMS current:
2
P
= R
× K × I
COND
DS(on)
RMS
Where:
K = temperature factor found in the manufacturer's RDS(on) vs junction temperature curves
Calculating these losses and plotting against frequency gives a curve that enables the designer to determine
which manufacturer's device has the best performance at the desired switching frequency, or which switching
frequency has the least total loss for a particular power switch. For this design example, an IRFP450 HEXFET™
from International Rectifier was chosen because of its low RDS(on) and its VDSS rating. The IRFP450 RDS(on) of 0.4
Ω and the maximum VDSS of 500 V made it an ideal choice. A review of this procedure can be found in the
Unitrode™ Power-Supply Design Seminar SEM1200, Topic 6, Design Review: 140 W (Multiple Output High
Density DC/DC Converter).
Soft Start
The soft-start circuitry is used to prevent overshoot of the output voltage during start up. This is accomplished by
slowly bringing up the voltage amplifier output (VVAOUT), which allows for the PWM duty cycle to slowly increase.
Use the following equation to select a capacitor for the soft-start pin.
In this example, tDELAY = 7.5 ms, which yields a CSS of 10 nF.
10 mA t
DELAY
C
+
SS
7.5 V
In an open-loop test circuit, shorting the soft-start pin to ground does not ensure 0% duty cycle. This is due to the
current amplifiers input offset voltage, which could force the current amplifier output high or low depending on the
polarity of the offset voltage. However, in the typical application, there is sufficient amount of inrush and bias
current to overcome the current amplifier offset voltage.
Multiplier
The output of the multiplier of the UCC2817 is a signal representing the desired input line current. It is an input to
the current amplifier, which programs the current loop to control the input current to give high power factor
operation. As such, the proper functioning of the multiplier is key to the success of the design. The inputs to the
multiplier are VAOUT, the voltage amplifier error signal, IIAC, a representation of the input rectified ac line voltage,
and an input voltage feed-forward signal, VVFF. The output of the multiplier, IMOUT, can be expressed as:
ǒVVAOUT * 1Ǔ
I
+ I
MOUT
IAC
2
K V
VFF
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Where:
K = Constant typically equal to 1/V
The Electrical Characteristics table covers all the required operating conditions for designing with the multiplier.
Additionally, curves in Figure 10, Figure 11, and Figure 12 provide typical multiplier characteristics over its entire
operating range.
The IIAC signal is obtained through a high-value resistor connected between the rectified ac line and the IAC pin
of the UCC2817 and UCC2818. This resistor RIAC is sized to give the maximum IIAC current at high line. For the
UCC2817 and UCC2818, the maximum IIAC current is about 500 µA. A higher current than this can drive the
multiplier out of its linear range. A smaller current level is functional, but noise can become an issue, especially
at low input line. Assuming a universal line operation of 85 VRMS to 265 VRMS gives a RIAC value of 750 kΩ,
because of voltage-rating constraints of a standard 1/4-W resistor, use a combination of lower-value resistors
connected in series to give the required resistance and distribute the high voltage amongst the resistors. For this
design example, two 383-kΩ resistors were used in series.
The current into the IAC pin is mirrored internally to the VFF pin where it is filtered to produce a voltage
feed-forward signal proportional to line voltage. The VFF voltage is used to keep the power-stage gain constant,
and to provide input power limiting.See the TI application report SLUA196 for detailed explanation on how the
VFF pin provides power limiting. The following equation can be used to size the VFF resistor RVFF to provide
power limiting where VIN(min) is the minimum RMS input voltage, and RIAC is the total resistance connected
between the IAC pin and the rectified line voltage.
1.4 V
R
+
[ 30 kW
VFF
V
0.9
IN(min)
2 R
IAC
Because the VFF voltage is generated from line voltage, it needs to be adequately filtered to reduce THD caused
by the 120-Hz rectified line voltage. Refer to Unitrode Power-Supply Design Seminar, SEM-700 Topic 7
(Optimizing the Design of a High Power Factor Preregulator). A single pole filter was adequate for this design.
Assuming that an allocation of 1.5% total harmonic distortion from this input is allowed, and that the second
harmonic ripple is 66% of the input ac line voltage, the amount of attenuation required by this filter is:
1.5 %
+ 0.022
66 %
A ripple frequency (fR) of 120 Hz and an attenuation of 0.022 requires that the pole of the filter (fP) be placed at:
f = 120 Hz × 0.022 ≈ 2.6 Hz
P
The following equation can be used to select the filter capacitor CVFF required to produce the desired low-pass
filter.
1
C
+
[ 2.2 mF
VFF
2 p R
f
VFF
P
The RMOUT resistor is sized to match the maximum current through the sense resistor to the maximum multiplier
current. The maximum multiplier current, or IMOUT(max), can be determined by the equation:
ǒVVAOUT(max) * 1 VǓ
I
@V
IAC
IN(min)
I
+
MOUT(max)
2
K V
VFF
(min)
10
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IMOUT(max) for this design is approximately 315 µA. The RMOUT resistor can then be determined by:
V
RSENSE
R
+
MOUT
I
MOUT(max)
In this example, VRSENSE was selected to give a dynamic operating range of 1.25 V, which gives an RMOUT of
roughly 3.91 kΩ.
Voltage Loop
The second major source of harmonic distortion is the ripple on the output capacitor at the second harmonic of
the line frequency. This ripple is fed back through the error amplifier and appears as a third harmonic ripple at
the input to the multiplier. The voltage loop must be compensated not just for stability but also to attenuate the
contribution of this ripple to the total harmonic distortion of the system (see Figure 2).
C
f
V
OUT
C
R
Z
f
R
IN
−
+
R
D
V
REF
Figure 2. Voltage Amplifier Configuration
The gain of the voltage amplifier, GVA, can be determined by first calculating the amount of ripple present on the
output capacitor. The peak value of the second harmonic voltage is given by the equation:
P
IN
V
+
OPK
2 p f C
V
R
OUT
OUT
In this example, VOPK = 3.91 V. Assuming an allowable contribution of 0.75% (1.5% peak to peak) from the
voltage loop to the THD budget, set the gain equal to:
ǒDVVAOUTǓ 0.015
G
+
VA
2 V
OPK
Where:
ΔVVAOUT = Effective output voltage range of the error amplifier (5 V for the UCC2817).
The network needed to realize this filter is comprised of an input resistor, RIN, and feedback components Cf, CZ,
and Rf. The value of RIN is already determined because of its function as one-half of a resistor divider from VOUT
feeding back to the voltage amplifier for output voltage regulation. In this case, the value was chosen to be
1 MΩ. This high value was chosen to reduce power dissipation in the resistor. In practice, the resistor value
would be realized by the use of two 500-kΩ resistors in series because of the voltage rating constraints of most
standard 1/4-W resistors. The value of Cf is determined by the equation:
1
C +
f
2 p f G
R
R
VA
IN
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In this example, Cf = 150 nF. Resistor Rf sets the dc gain of the error amplifier and, thus, determines the
frequency of the pole of the error amplifier. The location of the pole can be found by setting the gain of the loop
equation to one and solving for the crossover frequency. The frequency, expressed in terms of input power, can
be calculated by the equation:
P
2
IN
f
+
VI
2
(
)
2 p DV
V
R C
IN
C
VAOUT
OUT
OUT
f
fVI for this converter is 10 Hz. A derivation of this equation can be found in the Unitrode Power Supply Design
Seminar SEM1000, Topic 1 (A 250-kHz, 500-W Power Factor Correction Circuit Employing Zero Voltage
Transitions).
Solving for Rf becomes:
1
R +
f
2 p f C
VI
f
or Rf = 100 kΩ.
Due to the low output impedance of the voltage amplifier, capacitor CZ was added in series with RF to reduce
loading on the voltage divider. To ensure the voltage loop crossed over at fVI, CZ was selected to add a zero at
1/10th of fVI. For this design, a 2.2-µF capacitor was chosen for CZ. The following equation can be used to
calculate CZ:
1
C
+
Z
f
VI
2 p
R
f
10
Current Loop
The gain of the power stage is:
V
R
OUT
s L
SENSE
G
(s) +
ID
V
BOOST
P
RSENSE has been chosen to give the desired differential voltage for the current sense amplifier at the desired
current limit point. In this example, a current limit of 4 A and a reasonable differential voltage to the current
amplifier of 1 V gives a RSENSE value of 0.25 Ω. VP in this equation is the voltage swing of the oscillator ramp, 4 V
for the UCC2817. Setting the crossover frequency of the system to 1/10th of the switching frequency, or 10 kHz,
requires a power-stage gain at that frequency of 0.383. In order for the system to have a gain of 1 at the
crossover frequency, the current amplifier must have a gain of 1/GID at that frequency. GEA, the current amplifier
gain is then:
1
1
G
+
+
+ 2.611
EA
0.383
G
ID
RI is the RMOUT resistor, previously calculated to be 3.9 kΩ (see Figure 3). The gain of the current amplifier is
Rf/RI, so multiplying RI by GEA gives the value of Rf, in this case approximately 12 kΩ. Setting a zero at the
crossover frequency and a pole at one-half the switching frequency completes the current loop compensation.
1
C
+
Z
2 p R f
f
C
1
C
+
P
f
s
2 p R
f
2
12
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C
P
C
R
Z
f
R
I
−
+
CAOUT
Figure 3. Current Loop Compensation
The UCC2817 current amplifier has the input from the multiplier applied to the inverting input. This change in
architecture from previous TI PFC controllers improves noise immunity in the current amplifier. It also adds a
phase inversion into the control loop. The UCC2817 takes advantage of this phase inversion to implement
leading-edge duty cycle modulation. Synchronizing a boost PFC controller to a downstream dc-to-dc controller
reduces the ripple current seen by the bulk capacitor between stages, reducing capacitor size and cost and
reducing EMI. This is explained in greater detail in a following section. The UCC2817 current amplifier
configuration is shown in Figure 4.
L
BOOST
V
OUT
Q
−
+
BOOST
R
SENSE
Z
f
PWM
MULT
CA
COMPARATOR
−
−
+
+
Figure 4. UCC2818 Current Amplifier Configuration
Start Up
The UCC2818 version of the device is intended to have VCC connected to a 12-V supply voltage. The UCC2817
has an internal shunt regulator enabling the device to be powered from bootstrap circuitry, as shown in the
typical application circuit of Figure 1. The current drawn by the UCC2817 during undervoltage lockout, or start-up
current, is typically 150 µA. Once VCC is above the UVLO threshold, the device is enabled and draws
4 mA typically. A resistor connected between the rectified ac line voltage and the VCC pin provides current to the
shunt regulator during power up. Once the circuit is operational, the bootstrap winding of the inductor provides
the VCC voltage. Sizing of the start-up resistor is determined by the start-up time requirement of the system
design.
DV
Dt
I
+ C
C
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V
0.9
RMS
I
R +
C
Where:
IC = Charge current
C = Total capacitance at the VCC pin
ΔV = UVLO threshold
Δt = Allowed start-up time
Assuming a 1-s allowed start-up time, a 16-V UVLO threshold, and a total VCC capacitance of 100 µF, a resistor
value of 51 kΩ is required at a low line input voltage of 85 VRMS. The IC start-up current is sufficiently small as to
be ignored in sizing the start-up resistor.
Capacitor Ripple Reduction
For a power system where the PFC boost converter is followed by a dc-to-dc converter stage, there are benefits
to synchronizing the two converters. In addition to the usual advantages, such as noise reduction and stability,
proper synchronization can significantly reduce the ripple currents in the boost circuit output capacitor. Figure 5
shows the impact of proper synchronization by showing a PFC boost converter together with the simplified input
stage of a forward converter. The capacitor current during a single switching cycle depends on the status of the
switches Q1 and Q2 and is shown in Figure 6. With a synchronization scheme that maintains conventional
trailing-edge modulation on both converters, the capacitor current ripple is highest. The greatest ripple current
cancellation is attained when the overlap of Q1 offtime and Q2 ontime is maximized. One method of achieving
this is to synchronize the turnon of the boost diode (D1) with the turnon of Q2. This approach implies that the
boost converter leading edge is pulse width modulated, while the forward converter is modulated with traditional
trailing-edge PWM. The UCC2817 is designed as a leading edge modulator with easy synchronization to the
downstream converter to facilitate this advantage. Table 1 compares the ICB(rms) for D1/Q2 synchronization as
offered by UCC2817, versus the ICB(rms) for the other extreme of synchronizing the turnon of Q1 and Q2 for a
200-W power system with a VBST of 385 V.
i
D1
i
Q2
I
L
L
IN
D1
Q2
V
BST
i
CB
LOAD
Q1
C
BST
UDG-97130-1
Figure 5. Simplified Representation of a Two-Stage PFC Power Supply
14
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UDG-97131
Figure 6. Timing Waveforms for Synchronization Scheme
Table 1. Effects of Synchronization on Boost Capacitor Current
VIN = 85 V
VIN = 120 V
VIN = 240 V
D(Q2)
0.35
Q1/Q2
1.491 A
1.432 A
D1/Q2
0.835 A
0.93 A
Q1/Q2
1.341 A
1.276 A
D1/Q2
0.663 A
0.664 A
Q1/Q2
1.024 A
0.897 A
D1/Q2
0.731 A
0.614 A
0.45
Table 1 shows that the boost capacitor ripple current can be reduced by about 50% at nominal line and about
30% at high line with the synchronization scheme facilitated by the UCC2817. Figure 7 shows the suggested
technique for synchronizing the UCC2817 to the downstream converter. With this technique, maximum ripple
reduction as shown in Figure 6 is achievable. The output capacitance value can be significantly reduced if its
choice is dictated by ripple current or the capacitor life can be increased as a result. In cost-sensitive designs
where holdup time is not critical, this is a significant advantage.
An alternative method of synchronization to achieve the same ripple reduction is possible. In this method, the
turnon of Q1 is synchronized to the turnoff of Q2. While this method yields almost identical ripple reduction and
maintains trailing edge modulation on both converters, the synchronization is much more difficult to achieve and
the circuit can become susceptible to noise as the synchronizing edge itself is being modulated.
Gate Drive
From Down
Stream PWM
C1
UCC2817
D2
CT
C
T
D1
R
T
RT
Figure 7. Synchronizing the UCC2817 to a Downstream Converter
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REFERENCE VOLTAGE
vs
REFERENCE VOLTAGE
vs
SUPPLY VOLTAGE
REFERENCE CURRENT
7.60
7.55
7.50
7.45
7.40
7.510
7.505
7.500
7.495
7.490
9
10
11
12
13
14
0
5
10
15
20
25
VCC − Supply Voltage − V
I
− Reference Current − mA
VREF
Figure 8.
Figure 9.
MULTIPLIER OUTPUT CURRENT
vs
MULTIPLIER GAIN
vs
VOLTAGE ERROR AMPLIFIER OUTPUT
VOLTAGE ERROR AMPLIFIER OUTPUT
1.5
1.3
1.1
350
300
250
IAC = 150
µ A
IAC = 150
A
µ
200
150
IAC = 300
A
µ
0.9
0.7
0.5
IAC = 300
A
µ
IAC = 500 µ A
100
50
0
A
µ
IAC = 500
4.0
1.0
2.0
3.0
4.0
5.0
0.0
1.0
2.0
3.0
5.0
VAOUT − Voltage Error Amplifier Output − V
VAOUT − Voltage Error Amplifier Output − V
Figure 10.
Figure 11.
16
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RECOMMENDED MINIMUM GATE RESISTANCE
MULTIPLIER CONSTANT POWER PERFORMANCE
500
vs
SUPPLY VOLTAGE
17
16
15
14
13
12
400
VAOUT = 5 V
300
VAOUT = 4 V
200
VAOUT = 3 V
11
10
100
VAOUT = 2 V
9
8
0
0.0
1.0
2.0
3.0
4.0
5.0
10
12
14
16
18
20
VFF − Feed-Forward Voltage − V
V
CC
− Supply Voltage − V
Figure 12.
Figure 13.
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PACKAGE OPTION ADDENDUM
www.ti.com
7-Aug-2009
PACKAGING INFORMATION
Orderable Device
UCC2818MDREP
V62/09617-01XE
Status (1)
ACTIVE
ACTIVE
Package Package
Pins Package Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)
Qty
Type
Drawing
SOIC
D
16
2500 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
SOIC
D
16
2500 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and
package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS
compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
OTHER QUALIFIED VERSIONS OF UCC2818-EP :
Catalog: UCC2818
•
NOTE: Qualified Version Definitions:
Catalog - TI's standard catalog product
•
Addendum-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
15-Dec-2008
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0 (mm)
B0 (mm)
K0 (mm)
P1
W
Pin1
Diameter Width
(mm) W1 (mm)
(mm) (mm) Quadrant
UCC2818MDREP
SOIC
D
16
2500
330.0
16.4
6.5
10.3
2.1
8.0
16.0
Q1
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
15-Dec-2008
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SOIC 16
SPQ
Length (mm) Width (mm) Height (mm)
333.2 345.9 28.6
UCC2818MDREP
D
2500
Pack Materials-Page 2
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