UCC2817APWR_技术文档

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SLUS577B − SEPTEMBER, 2003 − REVISED FEBRUARY 2006

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FEATURES

DESCRIPTION

D

Controls Boost Preregulator to Near-Unity

Power Factor

The UCC3817A and the UCC3818A family

provides all the functions necessary for active

power factor corrected preregulators. The

controller achieves near unity power factor by

shaping the ac input line current waveform to

correspond to that of the ac input line voltage.

Average current mode control maintains stable,

low distortion sinusoidal line current.

D

Limits Line Distortion

World Wide Line Operation

Over-Voltage Protection

Accurate Power Limiting

Average Current Mode Control

Improved Noise Immunity

Improved Feed-Forward Line Regulation

Leading Edge Modulation

150-µA Typical Start-Up Current

Low-Power BiCMOS Operation

12-V to 17-V Operation

Designed in Texas Instrument’s BiCMOS process,

the UCC3817A/UCC3818A offers new features

such as lower start-up current, lower power

dissipation, overvoltage protection, a shunt UVLO

detect circuitry, a leading-edge modulation

technique to reduce ripple current in the bulk

capacitor and an improved, low-offset ( 2 mV)

current amplifier to reduce distortion at light load

conditions.

BLOCK DIAGRAM

VCC

15

OVP/EN 10

SS 13

16 V (FOR UCC3817A ONLY)

7.5 V

REFERENCE

9

VREF

UVLO

16 V/10 V (UCC3817A)

1.9 V

ENABLE

−

+

VAOUT

7

10.5 V/10 V (UCC3818A)

ZERO POWER

0.33 V

VCC

−

+

VOLTAGE

ERROR AMP

VSENSE 11

7.5 V

−

+

CURRENT

AMP

8.0 V

PWM

OVP

Q

+

−

X

÷

MULT

−

+

16 DRVOUT

−

+

X

S

2

VFF

8

X

PWM

LATCH

OSC

CLK

R

MIRROR

2:1

1

2

GND

CLK

OSCILLATOR

IAC

6

5

PKLMT

−

+

MOUT

4

3

12

14

CAI

CAOUT RT

CT

UDG-03122

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

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Copyright  2006, Texas Instruments Incorporated

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1

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SLUS577B − SEPTEMBER, 2003 − REVISED FEBRUARY 2006

DESCRIPTION (CONTINUED)

The UCC3817A/18A family of PFC Controllers is directly pin for pin compatible with the UCC3817/18 family of

devices. Only the output stage of UCC3817A family has been modified to allow use of a smaller external gate

drive resistor values. For some power supply designs where an adequately high enough gate drive resistor can

not be used, the UCC3817A/18A family offers a more robust output stage at the cost of increasing the internal

gate resistances. The gate drive of the UC3817A/18A family however remains strong at 1.2 A of peak current

capability.

UCC3817A offers an on-chip shunt regulator with low start-up current, suitable for applications utilizing a

bootstrap supply. UCC3818A is intended for applications with a fixed supply (VCC). Both devices are available

in the 16-pin D, N and PW packages.

PIN CONNECTION DIAGRAM

D, N, AND PW PACKAGES

(TOP VIEW)

GND

PKLMT

CAOUT

CAI

DRVOUT

VCC

CT

1

2

3

4

5

6

7

8

16

15

14

13

12

SS

MOUT

IAC

RT

11 VSENSE

10 OVP/EN

VAOUT

VFF

9

VREF

AVAILABLE OPTIONS TABLE

PACKAGE DEVICES

(1)

TSSOP (PW) PACKAGE

SOIC (D) PACKAGE

PDIP (N) PACKAGE

T

A

= T

J

Turn-on

Threshold

16 V

Turn-on

Threshold

10.2 V

Turn-on

Threshold

16 V

Turn-on

Threshold

10.2 V

Turn-on

Threshold

16 V

Turn-on

Threshold

10.2 V

−40°C to 85°C

0°C to 70°C

UCC2817AD

UCC3817AD

UCC2818AD

UCC3818AD

UCC2817AN

UCC3817AN

UCC2818AN

UCC3818AN

UCC2817APW

UCC3817APW

UCC2818APW

UCC3818APW

NOTES: (1) The D and PW packages are available taped and reeled. Add R suffix to the device type (e.g. UCC3817ADR) to order quantities

of 2,500 devices per reel (D package) and 2,000 devices per reel (for PW package). Bulk quantities are 40 units (D package) and

90 units (PW package) per tube.

THERMAL RESISTANCE TABLE

PACKAGE

SOIC−16 (D)

PDIP−16 (N)

θjc(°C/W)

θja(°C/W)

(1)

22

12

40 to 70

25 to 50

(1)

(2)

TSSOP−16 (PW)

14

123 to 147

2

NOTES: (1) Specifiedθja (junction to ambient) is for devices mounted to 5-inch FR4 PC board with one ounce copper

2

where noted. When resistance range is given, lower values are for 5 inch aluminum PC board. Test PWB

was 0.062 inch thick and typically used 0.635-mm trace widths for power packages and 1.3-mm trace

widths for non-power packages with a 100-mil x 100-mil probe land area at the end of each trace.

(2) Modeled data. If value range given for θja, lower value is for 3x3 inch. 1 oz internal copper ground plane,

higher value is for 1x1-inch. ground plane. All model data assumes only one trace for each non-fused

lead.

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SLUS577B − SEPTEMBER, 2003 − REVISED FEBRUARY 2006

ABSOLUTE MAXIMUM RATINGS

over operating free-air temperature (unless otherwise noted)

†

UCCx81xA

UNIT

V

Supply voltage VCC

18

Supply current ICC

20

mA

Gate drive current, continuous

Gate drive current

0.2

A

1.2

Input voltage, CAI, MOUT, SS

Input voltage, PKLMT

8

5

V

Input voltage, VSENSE, OVP/EN

Input current, RT, IAC, PKLMT

Input current, VCC (no switching)

Maximum negative voltage, DRVOUT, PKLMT, MOUT

Power dissipation

10

mA

20

−0.5

V

1

−55 to 150

−65 to 150

300

W

Junction temperature, T

Storage temperature, T

J

°C

stg

Lead temperature, T (soldering, 10 seconds)

sol

Power dissipation

1

W

†

Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and

functional operation of the device at these or any other conditions beyond those indicated under recommended operating conditions is not implied.

Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

ELECTRICAL CHARACTERISTICS

T = 0°C to 70°C for the UCC3817A and T = −40°C to 85°C for the UCC2817A, T = T VCC = 12 V, R = 22 kΩ,

A

J,

T

C = 270 pF, (unless otherwise noted)

T

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX UNITS

Supply Current Section

Supply current, off

VCC = (VCC turn-on threshold −0.3 V)

VCC = 12 V, No load on DRVOUT

150

4

300

6

µA

Supply current, on

2

mA

UVLO Section

VCC turn-on threshold (UCCx817)

VCC turn-off threshold (UCCx817)

UVLO hysteresis (UCCx817)

Maximum shunt voltage (UCCx817)

VCC turn-on threshold (UCCx818)

VCC turn-off threshold (UCCx818)

UVLO hysteresis (UCCx818)

Voltage Amplifier Section

15.4

9.4

16

9.7

6.3

17

16.6

5.8

I

= 10 mA

15.4

9.7

17.5

10.8

V

VCC

10.2

9.7

0.5

9.4

0.3

T

= 0°C to 70°C

7.387

7.369

7.5 7.613

7.5 7.631

A

Input voltage

V

T

A

= −40°C to 85°C

V

bias current

V

= V

,

VAOUT = 2.5 V

50

90

200

nA

dB

V

SENSE

VAOUT = 2 V to 5 V

REF

Open loop gain

50

5.3

0

High-level output voltage

Low-level output voltage

I

= −150 µA

= 150 µA

5.5

50

5.6

L

150

mV

L

3

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SLUS577B − SEPTEMBER, 2003 − REVISED FEBRUARY 2006

ELECTRICAL CHARACTERISTICS

T = 0°C to 70°C for the UCC3817A and T = −40°C to 85°C for the UCC2817A, T = T VCC = 12 V, R = 22 kΩ,

A

J,

T

C = 270 pF, (unless otherwise noted)

T

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX UNITS

Over Voltage Protection and Enable Section

VREF VREF VREF

+0.48 +0.50 +0.52

Over voltage reference

V

Hysteresis

300

1.7

0.1

500

1.9

0.2

600

2.1

0.3

mV

Enable threshold

Enable hysteresis

Current Amplifier Section

V

Input offset voltage

V

= 0 V,

V

= 3 V

−3.5

0

2.5

mV

nA

CM

CAOUT

Input bias current

= 0 V,

= 3 V

−50 −100

Input offset current

= 0 V,

= 3 V

25

100

Open loop gain

= 0 V,

= 2 V to 5 V

= 3 V

90

60

dB

Common-mode rejection ratio

High-level output voltage

Low-level output voltage

Gain bandwidth product

Voltage Reference Section

= 0 V to 1.5 V,

80

6.5

0.2

2.5

I

= −120 µA

5.6

0.1

6.8

0.5

L

V

= 1 mA

L

(1)

MHz

T

= 0°C to 70°C

7.387

7.369

0

7.5 7.613

7.5 7.631

10

A

Input voltage

V

T

A

= −40°C to 85°C

Load regulation

Line regulation

I

= 1 mA to 2 mA

REF

VCC = 10.8 V to 15 V

= 0 V

mV

mA

(2)

0

10

Short-circuit current

Oscillator Section

Initial accuracy

V

−20

−25

100

−50

REF

T

A

= 25°C

85

−1

115

1

kHz

%

Voltage stability

Total variation

VCC = 10.8 V to 15 V

Line, temp

80

120

5.5

kHz

Ramp peak voltage

4.5

5

4

V

Ramp amplitude voltage

(peak to peak)

3.5

4.5

Peak Current Limit Section

PKLMT reference voltage

PKLMT propagation delay

−15

150

15

mV

ns

350

500

NOTES: 1. Ensured by design, not production tested.

2. Reference variation for V < 10.8 V is shown in Figure 8.

CC

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SLUS577B − SEPTEMBER, 2003 − REVISED FEBRUARY 2006

ELECTRICAL CHARACTERISTICS

T = 0°C to 70°C for the UCC3817A and T = −40°C to 85°C for the UCC2817A, T = T VCC = 12 V, R = 22 kΩ,

A

J,

T

C = 270 pF, (unless otherwise noted)

T

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX UNITS

Multiplier Section

I

, high line, low power output

MOUT

I

= 500 µA,

= 150 µA,

V

= 4.7 V,

= 1.4 V,

VAOUT = 1.25 V

VAOUT = 5 V

0

−6

−20

−23

AC

FF

current, (0°C to 85°C)

I

, high line, low power output

MOUT

current, (−40°C to 85°C)

I

, high line, high power output

, low line, low power output

, low line, high power output

, IAC limited output current

MOUT

current

−70

−10

−90 −105

−19 −50

µA

I

MOUT

current

VAOUT = 1.25 V

VAOUT = 5 V

I

MOUT

current

−268 −300 −345

−250 −300 −400

I

= 150 µA,

= 300 µA,

= 150 µA,

= 500 µA,

= 150 µA,

V

FF

V

FF

V

FF

V

FF

V

FF

V

FF

V

FF

= 1.3 V,

= 3 V,

VAOUT = 5 V

MOUT

Gain constant (K)

AC

VAOUT = 2.5 V

VAOUT = 0.25 V

VAOUT = 0.5 V

VAOUT = 5 V

0.5

1

0

1.5

−2

1/V

= 1.4 V,

= 4.7 V,

= 1.4 V,

I

, zero current

MOUT

−2

µA

I

, zero current, (0°C to 85°C)

, zero current, (−40°C to 85°C)

−3

MOUT

−3.5

MOUT

Power limit (I

MOUT

x V )

FF

−375 −420 −485

−140 −150 −160

µW

µA

Feed-Forward Section

VFF output current

Soft Start Section

SS charge current

Gate Driver Section

Pullup resistance

I

= 300 µA

AC

−6

−10

−16

I

= –100 mA to −200 mA

= 100 mA

9

4

12

10

O

Ω

Pulldown resistance

Output rise time

O

C

= 1 nF,

R

= 10 Ω,

V

= 0.7 V to 9.0 V

= 9.0 V to 0.7 V

25

50

L

DRVOUT

ns

Output fall time

10

50

DRVOUT

Maximum duty cycle

93%

0.20

95%

99%

2%

Minimum controlled duty cycle

Zero Power Section

At 100 kHz

Zero power comparator threshold

Measured on VAOUT

0.33

0.50

V

5

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SLUS577B − SEPTEMBER, 2003 − REVISED FEBRUARY 2006

PIN ASSIGNMENTS

TERMINAL

I/O

DESCRIPTION

NAME

CAI

NO.

4

I

O

I

Current amplifier noninverting input

Current amplifier output

Oscillator timing capacitor

Gate drive

CAOUT

CT

3

14

16

1

DRVOUT

GND

O

−

I

Ground

IAC

6

Current proportional to input voltage

MOUT

OVP/EN

PKLMT

RT

5

I/O Multiplier output and current amplifier inverting input

10

2

I

Over-voltage/enable

PFC peak current limit

Oscillator charging current

Soft-start

12

13

7

I

SS

I

VAOUT

VCC

O

I

Voltage amplifier output

Positive supply voltage

Feed-forward voltage

Voltage amplifier inverting input

Voltage reference output

15

8

VFF

I

VSENSE

VREF

11

9

I

O

Pin Descriptions

CAI: Place a resistor between this pin and the GND side of current sense resistor. This input and the inverting

input (MOUT) remain functional down to and below GND.

CAOUT: This is the output of a wide bandwidth operational amplifier that senses line current and commands

the PFC pulse-width modulator (PWM) to force the correct duty cycle. Compensation components are placed

between CAOUT and MOUT.

CT: A capacitor from CT to GND sets the PWM oscillator frequency according to:

0.6

RT CT

_{f [}ǒ

Ǔ

The lead from the oscillator timing capacitor to GND should be as short and direct as possible.

DRVOUT: The output drive for the boost switch is a totem-pole MOSFET gate driver on DRVOUT. To avoid the

excessive overshoot of the DRVOUT while driving a capacitive load, a series gate current-limiting/damping

resistor is recommended to prevent interaction between the gate impedance and the output driver. The value

of the series gate resistor is based on the pulldown resistance (R

VCC voltage (VCC), and the required maximum gate drive current (I

which is 4 Ω typical), the maximum

pulldown

). Using the equation below, a series

MAX

gate resistance of resistance 11 Ω would be required for a maximum VCC voltage of 18 V and for 1.2 A of

maximum sink current. The source current will be limited to approximately 900 mA (based on the R

typical).

of 9-Ω

pullup

_{VCC *}ǒ_I

_pulldownǓ

R

MAX

R

+

GATE

I

MAX

GND: All voltages measured with respect to ground. VCC and REF should be bypassed directly to GND with

a 0.1-µF or larger ceramic capacitor.

6

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SLUS577B − SEPTEMBER, 2003 − REVISED FEBRUARY 2006

Pin Descriptions (cont.)

IAC: This input to the analog multiplier is a current proportional to instantaneous line voltage. The multiplier

is tailored for very low distortion from this current input (I ) to multiplier output. The recommended maximum

IAC

I

is 500 µA.

IAC

MOUT: The output of the analog multiplier and the inverting input of the current amplifier are connected together

at MOUT. As the multiplier output is a current, this is a high-impedance input so the amplifier can be configured

as a differential amplifier. This configuration improves noise immunity and allows for the leading-edge

_{modulation operation. The multiplier output current is limited to}ǒ_{2 I}Ǔ_{. The multiplier output current is given}

IAC

by the equation:

I

(V

* 1)

VAOUT

IAC

I

+

MOUT

2

V

K

VFF

1

V

where K + is the multiplier gain constant.

OVP/EN: A window comparator input that disables the output driver if the boost output voltage is a programmed

level above the nominal or disables both the PFC output driver and resets SS if pulled below 1.9 V (typ).

PKLMT: The threshold for peak limit is 0 V. Use a resistor divider from the negative side of the current sense

resistor to VREF to level shift this signal to a voltage level defined by the value of the sense resistor and the

peak current limit. Peak current limit is reached when PKLMT voltage falls below 0 V.

RT: A resistor from RT to GND is used to program oscillator charging current. A resistor between 10 kΩ and

100 kΩ is recommended. Nominal voltage on this pin is 3 V.

SS: V is discharged for V

source. This voltage is used as the voltage error signal during start-up, enabling the PWM duty cycle to increase

low conditions. When enabled, SS charges an external capacitor with a current

SS

VCC

slowly. In the event of a V

the PWM.

dropout, the OVP/EN is forced below 1.9 V (typ), SS quickly discharges to disable

VCC

Note: In an open-loop test circuit, grounding the SS pin does not ensure 0% duty cycle. Please see the

application section for details.

VAOUT: This is the output of the operational amplifier that regulates output voltage. The voltage amplifier output

is internally limited to approximately 5.5 V to prevent overshoot.

VCC: Connect to a stable source of at least 20 mA between 10 V and 17 V for normal operation. Bypass VCC

directly to GND to absorb supply current spikes required to charge external MOSFET gate capacitances. To

prevent inadequate gate drive signals, the output devices are inhibited unless V

under-voltage lockout voltage threshold and remains above the lower threshold.

exceeds the upper

VCC

VFF: The RMS voltage signal generated at this pin by mirroring 1/2 of the I

At low line, the VFF voltage should be 1.4 V.

into a single pole external filter.

IAC

VSENSE: This is normally connected to a compensation network and to the boost converter output through a

divider network.

VREF: VREF is the output of an accurate 7.5-V voltage reference. This output is capable of delivering 20 mA

to peripheral circuitry and is internally short-circuit current limited. VREF is disabled and remains at 0 V when

V

is below the UVLO threshold. Bypass VREF to GND with a 0.1-µF or larger ceramic capacitor for best

VCC

stability. Please refer to Figures 8 and 9 for VREF line and load regulation characteristics.

7

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SLUS577B − SEPTEMBER, 2003 − REVISED FEBRUARY 2006

APPLICATION INFORMATION

The UCC3817A is a BiCMOS average current mode boost controller for high power factor, high efficiency

preregulator power supplies. Figure 1 shows the UCC3817A in a 250-W PFC preregulator circuit. Off-line

switching power converters normally have an input current that is not sinusoidal. The input current waveform

has a high harmonic content because current is drawn in pulses at the peaks of the input voltage waveform.

An active power factor correction circuit programs the input current to follow the line voltage, forcing the

converter to look like a resistive load to the line. A resistive load has 0° phase displacement between the current

and voltage waveforms. Power factor can be defined in terms of the phase angle between two sinusoidal

waveforms of the same frequency:

PF + cosQ

(1)

Therefore, a purely resistive load would have a power factor of 1. In practice, power factors of 0.999 with THD

(total harmonic distortion) of less than 3% are possible with a well-designed circuit. Following guidelines are

provided to design PFC boost converters using the UCC3817A.

NOTE: Schottky diodes, D5 and D6, are required to protect the PFC controller from electrical over stress during

system power up.

C10

1 µ F

C11

1 µF

R16

Ω

100

VCC

R15

24k

D7

D8

R21

R13

383k 383k

L1

IAC

1mH

R18

24k

V

D1

8A, 600V

O

F1

AC2

+

D2

6A, 600V

C14

1.5µ

400V

C13

0.47µ

600V

V

F

LINE

85−270 V

AC

V

Q1

IRFP450

OUT

D3

C12

385V−DC

AC1

R14

0.25

µ

220

F

Ω

450V

3W

6A 600V

−

R17

20Ω

UCC3817A

R9

4.02k

R10

4.02k

R12

2k

1

2

GND

DRVOUT 16

D4

VCC

C3

PKLIMIT

1µF CER

D5

VCC 15

R11

10k

3

4

5

CAOUT

CAI

C2

100

µ F AI EI

C1

560pF

V

REF

MOUT

CT 14

SS 13

C9 1.2nF

R8 12k

C4 0.01µF

6

IAC

C8 270pF

R1 12k

RT 12

C7 150nF

D6

R7 100k C15 2.2µ F

VSENSE 11

V

R2

499k

R19

499k

O

R3 20k

7

8

VAOUT

VFF

C6 2.2µF

R4

249k

R20 274k

OVP/EN 10

R5

10k

R6 30k

µF

C5 1

VREF

9

V

REF

UDG-98183

Figure 1. Typical Application Circuit

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SLUS577B − SEPTEMBER, 2003 − REVISED FEBRUARY 2006

APPLICATION INFORMATION

Power Stage

L

: The boost inductor value is determined by:

BOOST

ǒ_V

_DǓ

IN(min)

L

+

BOOST

(

)

DI fs

(2)

where D is the duty cycle, ∆I is the inductor ripple current and f is the switching frequency. For the example

S

circuit a switching frequency of 100 kHz, a ripple current of 875 mA, a maximum duty cycle of 0.688 and a

minimum input voltage of 85 V

equation are at the peak of low line, where the inductor current and its ripple are at a maximum.

gives us a boost inductor value of about 1 mH. The values used in this

RMS

C

: Two main criteria, the capacitance and the voltage rating, dictate the selection of the output capacitor.

OUT

The value of capacitance is determined by the holdup time required for supporting the load after input ac voltage

is removed. Holdup is the amount of time that the output stays in regulation after the input has been removed.

For this circuit, the desired holdup time is approximately 16 ms. Expressing the capacitor value in terms of output

power, output voltage, and holdup time gives the equation:

ǒ_{2 P Dt}Ǔ

OUT

C

⁺ǒ_V

_OUT(min)Ǔ

OUT

2

* V

OUT

(3)

In practice, the calculated minimum capacitor value may be inadequate because output ripple voltage

specifications limit the amount of allowable output capacitor ESR. Attaining a sufficiently low value of ESR often

necessitates the use of a much larger capacitor value than calculated. The amount of output capacitor ESR

allowed can be determined by dividing the maximum specified output ripple voltage by the inductor ripple

current. In this design holdup time was the dominant determining factor and a 220-µF, 450-V capacitor was

chosen for the output voltage level of 385 VDC at 250 W.

9

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SLUS577B − SEPTEMBER, 2003 − REVISED FEBRUARY 2006

APPLICATION INFORMATION

Power switch selection: As in any power supply design, tradeoffs between performance, cost and size have

to be made. When selecting a power switch, it can be useful to calculate the total power dissipation in the switch

for several different devices at the switching frequencies being considered for the converter. Total power

dissipation in the switch is the sum of switching loss and conduction loss. Switching losses are the combination

of the gate charge loss, C

loss and turnon and turnoff losses:

OSS

GATE

2

P

+ Q

V

f

GATE

COSS

GATE

S

(4)

(5)

1

2

P

+

C

V

f

S

OSS

OFF

1

2

_Iǒ_t

Ǔ

f

P

) P

+

V

) t

ON

OFF

L

ON

OFF

S

(6)

where Q

is the total gate charge, V

is the gate drive voltage, f is the clock frequency, C is the drain

OSS

GATE

L

S

source capacitance of the MOSFET, I is the peak inductor current, t

(estimated using device parameters R

off time, in this case V

and t

are the switching times

ON

OFF

, Q

and V ) and V

is the voltage across the switch during the

GATE GD

TH

OFF

= V

.

OFF

OUT

Conduction loss is calculated as the product of the R

and the square of RMS current:

of the switch (at the worst case junction temperature)

DS(on)

2

P

+ R

K I

COND

DS(on)

RMS

(7)

where K is the temperature factor found in the manufacturer’s R

vs. junction temperature curves.

DS(on)

Calculating these losses and plotting against frequency gives a curve that enables the designer to determine

either which manufacturer’s device has the best performance at the desired switching frequency, or which

switching frequency has the least total loss for a particular power switch. For this design example an IRFP450

HEXFET from International Rectifier was chosen because of its low R

and its V

rating. The IRFP450’s

DS(on)

DSS

R

of 0.4 Ω and the maximum V

of 500 V made it an ideal choice. An excellent review of this procedure

DS(on)

DSS

can be found in the Unitrode Power Supply Design Seminar SEM1200, Topic 6, Design Review: 140 W, [Multiple

Output High Density DC/DC Converter].

Softstart

The softstart circuitry is used to prevent overshoot of the output voltage during start up. This is accomplished

by bringing up the voltage amplifier’s output (V ) slowly which allows for the PWM duty cycle to increase

VAOUT

slowly. Please use the following equation to select a capacitor for the softstart pin.

In this example t is equal to 7.5 ms, which

DELAY

would yield a C of 10 nF.

SS

10 mA t

DELAY

C

+

SS

7.5 V

(8)

In an open-loop test circuit, shorting the softstart pin to ground does not ensure 0% duty cycle. This is due to

the current amplifiers input offset voltage, which could force the current amplifier output high or low depending

on the polarity of the offset voltage. However, in the typical application there is sufficient amount of inrush and

bias current to overcome the current amplifier’s offset voltage.

10

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SLUS577B − SEPTEMBER, 2003 − REVISED FEBRUARY 2006

APPLICATION INFORMATION

Multiplier

The output of the multiplier of the UCC3817A is a signal representing the desired input line current. It is an input

to the current amplifier, which programs the current loop to control the input current to give high power factor

operation. As such, the proper functioning of the multiplier is key to the success of the design. The inputs to the

multiplier are VAOUT, the voltage amplifier error signal, I

, a representation of the input rectified ac line

IAC

voltage, and an input voltage feedforward signal, V

as:

. The output of the multiplier, I

, can be expressed

VFF

MOUT

ǒ_V

_* 1Ǔ

VAOUT

I

+ I

IAC

MOUT

2

K V

(9)

VFF

1

V

where K is a constant typically equal to

.

The electrical characteristics table covers all the required operating conditions for designing with the

multiplier. Additionally, curves in Figures 10, 11, and 12 provide typical multiplier characteristics over its entire

operating range.

The I

signal is obtained through a high-value resistor connected between the rectified ac line and the IAC

IAC

pin of the UCC3817A/18A. This resistor (R ) is sized to give the maximum I

UCC3817A/18A the maximum I

current at high line. For the

IAC

current is about 500 µA. A higher current than this can drive the multiplier

IAC

out of its linear range. A smaller current level is functional, but noise can become an issue, especially at low

input line. Assuming a universal line operation of 85 V to 265 V gives a R value of 750 kΩ. Because

RMS

IAC

of voltage rating constraints of standard 1/4-W resistor, use a combination of lower value resistors connected

in series to give the required resistance and distribute the high voltage amongst the resistors. For this design

example two 383-kΩ resistors were used in series.

The current into the IAC pin is mirrored internally to the VFF pin where it is filtered to produce a voltage feed

forward signal proportional to line voltage. The VFF voltage is used to keep the power stage gain constant; and

to provid input power limiting. Please refer to Texas Instruments application note SLUA196 for detailed

explanation on how the VFF pin provides power limiting. The following equation can be used to size the VFF

resistor (R

) to provide power limiting where V

is the minimum RMS input voltage and R

is the total

VFF

IN(min)

IAC

resistance connected between the IAC pin and the rectified line voltage.

1.4 V

R

+

[ 30 kW

VFF

V

0.9

IN(min)

2 R

IAC

(10)

11

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SLUS577B − SEPTEMBER, 2003 − REVISED FEBRUARY 2006

APPLICATION INFORMATION

Because the VFF voltage is generated from line voltage it needs to be adequately filtered to reduce total

harmonic distortion caused by the 120 Hz rectified line voltage. Refer to Unitrode Power Supply Design

Seminar, SEM−700 Topic 7, [Optimizing the Design of a High Power Factor Preregulator.] A single pole filter

was adequate for this design. Assuming that an allocation of 1.5% total harmonic distortion from this input is

allowed, and that the second harmonic ripple is 66% of the input ac line voltage, the amount of attenuation

required by this filter is:

1.5 %

66 %

+ 0.022

(11)

With a ripple frequency (f ) of 120 Hz and an attenuation of 0.022 requires that the pole of the filter (f ) be placed

R

P

at:

f + 120 Hz 0.022 [ 2.6 Hz

(12)

P

The following equation can be used to select the filter capacitor (C

filter.

) required to produce the desired low pass

VFF

1

C

+

[ 2.2 mF

VFF

2 p R

f

P

VFF

(13)

The R

resistor is sized to match the maximum current through the sense resistor to the maximum multiplier

MOUT

current. The maximum multiplier current, or I

, can be determined by the equation:

MOUT(max)

ǒ_V

_{* 1 V}Ǔ

I

@V

IN(min)

IAC

VAOUT(max)

I

+

MOUT(max)

2

K V

VFF

(min)

(14)

(15)

I

for this design is approximately 315 µA. The R

resistor can then be determined by:

MOUT(max)

MOUT

V

RSENSE

R

+

MOUT

I

MOUT(max)

In this example V

was selected to give a dynamic operating range of 1.25 V, which gives an R

of

RSENSE

MOUT

roughly 3.91 kΩ.

12

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SLUS577B − SEPTEMBER, 2003 − REVISED FEBRUARY 2006

APPLICATION INFORMATION

Voltage Loop

The second major source of harmonic distortion is the ripple on the output capacitor at the second harmonic

of the line frequency. This ripple is fed back through the error amplifier and appears as a 3rd harmonic ripple

at the input to the multiplier. The voltage loop must be compensated not just for stability but also to attenuate

the contribution of this ripple to the total harmonic distortion of the system. (refer to Figure 2).

C

f

V

OUT

C

R

Z

f

R

IN

−

+

R

D

V

REF

Figure 2. Voltage Amplifier Configuration

The gain of the voltage amplifier, G , can be determined by first calculating the amount of ripple present on

VA

the output capacitor. The peak value of the second harmonic voltage is given by the equation:

P

IN

V

⁺ǒ_{2 p f C}

_OUTǓ

OPK

V

OUT

R

(16)

In this example V

is equal to 3.91 V. Assuming an allowable contribution of 0.75% (1.5% peak to peak) from

OPK

the voltage loop to the total harmonic distortion budget we set the gain equal to:

ǒ_DV

Ǔ ₍

0.015

)

VAOUT

G

+

VA

2 V

OPK

(17)

where ∆V

is the effective output voltage range of the error amplifier (5 V for the UCC3817A). The network

VAOUT

needed to realize this filter is comprised of an input resistor, R , and feedback components C , C , and R . The

IN

f

Z

f

value of R is already determined because of its function as one half of a resistor divider from V

feeding

IN

OUT

back to the voltage amplifier for output voltage regulation. In this case the value was chosen to be 1 MΩ. This

high value was chosen to reduce power dissipation in the resistor. In practice, the resistor value would be

realized by the use of two 500-kΩ resistors in series because of the voltage rating constraints of most standard

1/4-W resistors. The value of C is determined by the equation:

f

1

C +

f

ǒ

_INǓ

2 p f G R

R

VA

(18)

13

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SLUS577B − SEPTEMBER, 2003 − REVISED FEBRUARY 2006

APPLICATION INFORMATION

In this example C equals 150 nF. Resistor R sets the dc gain of the error amplifier and thus determines the

f

frequency of the pole of the error amplifier. The location of the pole can be found by setting the gain of the loop

equation to one and solving for the crossover frequency. The frequency, expressed in terms of input power, can

be calculated by the equation:

P

2

IN

f

⁺ǒ₍

_C_fǓ

VI

2

)

2 p DV

V

R C

OUT OUT

IN

VAOUT

(19)

f

for this converter is 10 Hz. A derivation of this equation can be found in the Unitrode Power Supply Design

VI

Seminar SEM1000, Topic 1, [A 250-kHz, 500-W Power Factor Correction Circuit Employing Zero Voltage

Transitions].

Solving for R becomes:

f

1

R +

f

ǒ

_C_fǓ

2 p f

VI

(20)

or R equals 100 kΩ.

f

Due to the low output impedance of the voltage amplifier, capacitor C was added in series with R to reduce

Z

F

loading on the voltage divider. To ensure the voltage loop crossed over at f , C was selected to add a zero

VI

Z

at a 10th of f . For this design a 2.2-µF capacitor was chosen for C . The following equation can be used to

VI

Z

calculate C .

Z

1

C +

Z

f

VI

2 p

R

f

10

(21)

Current Loop

The gain of the power stage is:

ǒ_V

_SENSEǓ

R

OUT

G (s) +

ID

ǒ

_PǓ

V

s L

BOOST

(22)

R

has been chosen to give the desired differential voltage for the current sense amplifier at the desired

SENSE

current limit point. In this example, a current limit of 4 A and a reasonable differential voltage to the current amp

of 1 V gives a R value of 0.25 Ω. V in this equation is the voltage swing of the oscillator ramp, 4 V for

SENSE

P

the UCC3817A. Setting the crossover frequency of the system to 1/10th of the switching frequency, or 10 kHz,

requires a power stage gain at that frequency of 0.383. In order for the system to have a gain of 1 at the crossover

frequency, the current amplifier needs to have a gain of 1/G at that frequency. G , the current amplifier gain

ID

EA

is then:

1

G

+

+ 2.611

EA

0.383

G

ID

(23)

14

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SLUS577B − SEPTEMBER, 2003 − REVISED FEBRUARY 2006

APPLICATION INFORMATION

R is the R

resistor, previously calculated to be 3.9 kΩ. (refer to Figure 3). The gain of the current amplifier

I

MOUT

is R /R , so multiplying R by G gives the value of R , in this case approximately 12 kΩ. Setting a zero at the

f

I

EA

f

crossover frequency and a pole at half the switching frequency completes the current loop compensation.

1

C +

Z

2 p R f

f

C

s

(24)

(25)

1

C +

P

f

2 p R

f

2

C

P

C

R

Z

f

R

I

−

+

CAOUT

Figure 3. Current Loop Compensation

The UCC3817A current amplifier has the input from the multiplier applied to the inverting input. This change

in architecture from previous Texas Instruments PFC controllers improves noise immunity in the current

amplifier. It also adds a phase inversion into the control loop. The UCC3817A takes advantage of this phase

inversion to implement leading-edge duty cycle modulation. Synchronizing a boost PFC controller to a

downstream dc-to-dc controller reduces the ripple current seen by the bulk capacitor between stages, reducing

capacitor size and cost and reducing EMI. This is explained in greater detail in a following section. The

UCC3817A current amplifier configuration is shown in Figure 4.

L

BOOST

V

OUT

Q

−

+

BOOST

R

SENSE

Z

f

PWM

MULT

CA

COMPARATOR

−

+

Figure 4. UCC3817A Current Amplifier Configuration

15

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SLUS577B − SEPTEMBER, 2003 − REVISED FEBRUARY 2006

APPLICATION INFORMATION

Start Up

The UCC3818A version of the device is intended to have VCC connected to a 12-V supply voltage. The

UCC3817A has an internal shunt regulator enabling the device to be powered from bootstrap circuitry as shown

in the typical application circuit of Figure 1. The current drawn by the UCC3817A during undervoltage lockout,

or start-up current, is typically 150 µA. Once VCC is above the UVLO threshold, the device is enabled and draws

4 mA typically. A resistor connected between the rectified ac line voltage and the VCC pin provides current to

the shunt regulator during power up. Once the circuit is operational, the bootstrap winding of the inductor

provides the VCC voltage. Sizing of the start-up resistor is determined by the start-up time requirement of the

system design.

DV

Dt

I

+ C

C

(26)

( )

0.9

V

RMS

R +

I

C

(27)

Where I is the charge current, C is the total capacitance at the VCC pin, ∆V is the UVLO threshold and ∆t is

C

the allowed start-up time.

Assuming a 1 second allowed start-up time, a 16-V UVLO threshold, and a total VCC capacitance of 100 µF,

a resistor value of 51 kΩ is required at a low line input voltage of 85 V

small as to be ignored in sizing the start-up resistor.

. The IC start-up current is sufficiently

RMS

Capacitor Ripple Reduction

For a power system where the PFC boost converter is followed by a dc-to-dc converter stage, there are benefits

to synchronizing the two converters. In addition to the usual advantages such as noise reduction and stability,

proper synchronization can significantly reduce the ripple currents in the boost circuit’s output capacitor.

Figure 5 helps illustrate the impact of proper synchronization by showing a PFC boost converter together with

the simplified input stage of a forward converter. The capacitor current during a single switching cycle depends

on the status of the switches Q1 and Q2 and is shown in Figure 6. It can be seen that with a synchronization

scheme that maintains conventional trailing-edge modulation on both converters, the capacitor current ripple

is highest. The greatest ripple current cancellation is attained when the overlap of Q1 offtime and Q2 ontime

is maximized. One method of achieving this is to synchronize the turnon of the boost diode (D1) with the turnon

of Q2. This approach implies that the boost converter’s leading edge is pulse width modulated while the forward

converter is modulated with traditional trailing edge PWM. The UCC3817A is designed as a leading edge

modulator with easy synchronization to the downstream converter to facilitate this advantage. Table 1 compares

the I

for D1/Q2 synchronization as offered by UCC3817A vs. the I

for the other extreme of

of 385 V.

CB(rms)

synchronizing the turnon of Q1 and Q2 for a 200-W power system with a V

BST

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SLUS577B − SEPTEMBER, 2003 − REVISED FEBRUARY 2006

APPLICATION INFORMATION

UDG-97130-1

Figure 5. Simplified Representation of a 2-Stage PFC Power Supply

UDG-97131

Figure 6. Timing Waveforms for Synchronization Scheme

17

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SLUS577B − SEPTEMBER, 2003 − REVISED FEBRUARY 2006

APPLICATION INFORMATION

Table 1 illustrates that the boost capacitor ripple current can be reduced by about 50% at nominal line and about

30% at high line with the synchronization scheme facilitated by the UCC3817A. Figure 7 shows the suggested

technique for synchronizing the UCC3817A to the downstream converter. With this technique, maximum ripple

reduction as shown in Figure 6 is achievable. The output capacitance value can be significantly reduced if its

choice is dictated by ripple current or the capacitor life can be increased as a result. In cost sensitive designs

where holdup time is not critical, this is a significant advantage.

Table 1. Effects of Synchronization on Boost Capacitor Current

V

IN

= 85 V

V

IN

= 120 V

V

IN

= 240 V

D(Q2)

0.35

Q1/Q2

D1/Q2

Q1/Q2

D1/Q2

Q1/Q2

D1/Q2

1.491 A

1.432 A

0.835 A

0.93 A

1.341 A

1.276 A

0.663 A

0.664 A

1.024 A

0.897 A

0.731 A

0.614 A

0.45

An alternative method of synchronization to achieve the same ripple reduction is possible. In this method, the

turnon of Q1 is synchronized to the turnoff of Q2. While this method yields almost identical ripple reduction and

maintains trailing edge modulation on both converters, the synchronization is much more difficult to achieve and

the circuit can become susceptible to noise as the synchronizing edge itself is being modulated.

Gate Drive

From Down

Stream PWM

C1

UCC3817A

D2

CT

C

D1

T

R

T

RT

Figure 7. Synchronizing the UCC3817A to a Down-Stream Converter

18

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SLUS577B − SEPTEMBER, 2003 − REVISED FEBRUARY 2006

APPLICATION INFORMATION

REFERENCE VOLTAGE

vs

REFERENCE CURRENT

REFERENCE VOLTAGE

vs

SUPPLY VOLTAGE

7.60

7.55

7.50

7.45

7.40

7.510

7.505

7.500

7.495

7.490

0

5

I

10

15

20

25

9

10

11

12

13

14

− Reference Current − mA

VCC − Supply Voltage − V

VREF

Figure 8

Figure 9

MULTIPLIER OUTPUT CURRENT

vs

MULTIPLIER GAIN

vs

VOLTAGE ERROR AMPLIFIER OUTPUT

1.5

1.3

1.1

350

300

250

IAC = 150

A

µ

IAC = 150

A

µ

200

150

IAC = 300

A

µ

0.9

0.7

IAC = 300

A

µ

IAC = 500

A

µ

100

50

0

A

µ

IAC = 500

4.0

0.5

1.0

2.0

3.0

4.0

5.0

0.0

1.0

2.0

3.0

5.0

VAOUT − Voltage Error Amplifier Output − V

Figure 10

Figure 11

19

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ꢉ

SLUS577B − SEPTEMBER, 2003 − REVISED FEBRUARY 2006

APPLICATION INFORMATION

MULTIPLIER CONSTANT POWER PERFORMANCE

500

400

VAOUT = 5 V

300

VAOUT = 4 V

200

VAOUT = 3 V

100

VAOUT = 2 V

0

0.0

1.0

2.0

3.0

4.0

5.0

VFF − Feedforward Voltage − V

Figure 12

References and Resources:

Application Note, Differences Between UCC3817A/18A/19A and UCC3817/18/19, Texas Instruments

Literature Number SLUA294

Evaluation Module, UCC3817EVM, 385V, 250W PFC Boost Converter

User’s Guide, UCC3817 BiCMOS Power Factor Preregulator Evaluation Board, Texas Instruments Literature

Number SLUU077

Application Note, Synchronizing a PFC Controller from a Down Stream Controller Gate Drive, Texas

Instruments Literature Number SLUA245

Seminar topic, High Power Factor Switching Preregulator Design Optimization, L.H. Dixon, SEM−700,1990.

Seminar topic, High Power Factor Preregulator for Off−line Supplies, L.H. Dixon, SEM−600, 1988.


型号：	UCC2817APWR
厂家：	TEXAS INSTRUMENTS
描述：	BiCMOS POWER FACTOR PREREGULATOR BiCMOS功率因数前置稳压器稳压器
文件：	总33页 (文件大小：639K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

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