TVP5150AM1ZQCR [TI]
ULTRALOW POWER NTSC/PAL/SECAM VIDEO DECODER WITH REBUST SYNC DETECTOR; 超低功耗NTSC / PAL / SECAM视频, REBUST同步检测器解码器型号: | TVP5150AM1ZQCR |
厂家: | TEXAS INSTRUMENTS |
描述: | ULTRALOW POWER NTSC/PAL/SECAM VIDEO DECODER WITH REBUST SYNC DETECTOR |
文件: | 总79页 (文件大小:370K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
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ꢉꢊ ꢋꢌ ꢍꢊꢎ ꢏ ꢂꢎ ꢏꢐ ꢌ ꢑꢀ ꢒꢓ ꢇꢂꢆꢔꢇ ꢒꢕ ꢓꢆꢈ ꢁ ꢖ ꢗ ꢐ ꢎ
ꢘ ꢐ ꢙꢎ ꢗꢐ ꢌ ꢚꢖ ꢋꢛ ꢜ ꢎ ꢝꢞꢟꢋ ꢒꢠꢡꢙ ꢘ ꢐꢋꢐꢙꢋ ꢎꢌ
Data Manual
May 2004
HPA Digital Audio Video
SLES098
IMPORTANT NOTICE
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Contents
Section
1
Title
Page
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1−1
1.1
1.2
1.3
1.4
1.5
1.6
1.7
1.8
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1−1
Product Family . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1−2
Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1−3
Related Products . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1−3
Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1−3
Functional Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1−4
Terminal Assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1−5
Terminal Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1−5
2
Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2−1
2.1
2.2
2.3
2.4
2.5
2.6
2.7
2.8
2.9
Analog Front End . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2−1
Composite Processing Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 2−1
Adaptive Comb Filtering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2−1
Color Low-Pass Filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2−1
Luminance Processing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2−2
Chrominance Processing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2−2
Timing Processor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2−3
VBI Data Processor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2−3
VBI FIFO and Ancillary Data in Video Stream . . . . . . . . . . . . . . . . . . . 2−4
2.10 Raw Video Data Output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2−5
2.11 Output Formatter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2−5
2.12 Synchronization Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2−5
2.13 AVID Cropping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2−7
2.14 Embedded Syncs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2−8
2
2.15 I C Host Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2−9
2
2.15.1
2.15.2
I C Write Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2−9
2
I C Read Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2−10
2.15.2.1
2.15.2.2
2.15.2.3
Read Phase 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . 2−10
Read Phase 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . 2−11
I C Timing Requirements . . . . . . . . . . . . . . . . . 2−11
2
2.16 Clock Circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2−11
2.17 Genlock Control and RTC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2−12
2.17.1
2.17.2
TVP5150A Genlock Control Interface . . . . . . . . . . . . . . . . . . 2−12
RTC Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2−13
2.18 Reset and Power Down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2−13
2.19 Internal Control Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2−13
2.20 Register Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2−16
iii
2.20.1
2.20.2
2.20.3
2.20.4
2.20.5
2.20.6
2.20.7
2.20.8
2.20.9
Video Input Source Selection #1 Register . . . . . . . . . . . . . . 2−16
Analog Channel Controls Register . . . . . . . . . . . . . . . . . . . . 2−17
Operation Mode Controls Register . . . . . . . . . . . . . . . . . . . . 2−17
Miscellaneous Control Register . . . . . . . . . . . . . . . . . . . . . . . 2−18
Autoswitch Mask Register . . . . . . . . . . . . . . . . . . . . . . . . . . . 2−20
Color Killer Threshold Control Register . . . . . . . . . . . . . . . . 2−20
Luminance Processing Control #1 Register . . . . . . . . . . . . 2−21
Luminance Processing Control #2 Register . . . . . . . . . . . . 2−22
Brightness Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . 2−22
2.20.10 Color Saturation Control Register . . . . . . . . . . . . . . . . . . . . . 2−22
2.20.11 Hue Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2−23
2.20.12 Contrast Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2−23
2.20.13 Outputs and Data Rates Select Register . . . . . . . . . . . . . . . 2−23
2.20.14 Luminance Processing Control #3 Register . . . . . . . . . . . . 2−24
2.20.15 Configuration Shared Pins Register . . . . . . . . . . . . . . . . . . . 2−25
2.20.16 Active Video Cropping Start Pixel MSB Register . . . . . . . . 2−25
2.20.17 Active Video Cropping Start Pixel LSB Register . . . . . . . . . 2−26
2.20.18 Active Video Cropping Stop Pixel MSB Register . . . . . . . . 2−26
2.20.19 Active Video Cropping Stop Pixel LSB Register . . . . . . . . . 2−26
2.20.20 Genlock and RTC Register . . . . . . . . . . . . . . . . . . . . . . . . . . . 2−27
2.20.21 Horizontal Sync (HSYNC) Start Register . . . . . . . . . . . . . . . 2−28
2.20.22 Vertical Blanking Start Register . . . . . . . . . . . . . . . . . . . . . . . 2−29
2.20.23 Vertical Blanking Stop Register . . . . . . . . . . . . . . . . . . . . . . . 2−29
2.20.24 Chrominance Control #1 Register . . . . . . . . . . . . . . . . . . . . . 2−30
2.20.25 Chrominance Control #2 Register . . . . . . . . . . . . . . . . . . . . . 2−31
2.20.26 Interrupt Reset Register B . . . . . . . . . . . . . . . . . . . . . . . . . . . 2−32
2.20.27 Interrupt Enable Register B . . . . . . . . . . . . . . . . . . . . . . . . . . 2−33
2.20.28 Interrupt Configuration Register B . . . . . . . . . . . . . . . . . . . . . 2−34
2.20.29 Video Standard Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2−34
2.20.30 Cb Gain Factor Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2−34
2.20.31 Cr Gain Factor Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2−35
2.20.32 Macrovision On Counter Register . . . . . . . . . . . . . . . . . . . . . 2−35
2.20.33 Macrovision Off Counter Register . . . . . . . . . . . . . . . . . . . . . 2−35
2.20.34 656 Revision Select Register . . . . . . . . . . . . . . . . . . . . . . . . . 2−35
2.20.35 MSB of Device ID Register . . . . . . . . . . . . . . . . . . . . . . . . . . . 2−35
2.20.36 LSB of Device ID Register . . . . . . . . . . . . . . . . . . . . . . . . . . . 2−36
2.20.37 ROM Major Version Register . . . . . . . . . . . . . . . . . . . . . . . . . 2−36
2.20.38 ROM Minor Version Register . . . . . . . . . . . . . . . . . . . . . . . . . 2−36
2.20.39 Vertical Line Count MSB Register . . . . . . . . . . . . . . . . . . . . . 2−36
2.20.40 Vertical Line Count LSB Register . . . . . . . . . . . . . . . . . . . . . 2−36
2.20.41 Interrupt Status Register B . . . . . . . . . . . . . . . . . . . . . . . . . . . 2−37
2.20.42 Interrupt Active Register B . . . . . . . . . . . . . . . . . . . . . . . . . . . 2−37
2.20.43 Status Register #1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2−38
2.20.44 Status Register #2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2−39
iv
2.20.45 Status Register #3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2−39
2.20.46 Status Register #4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2−40
2.20.47 Status Register #5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2−40
2.20.48 Closed Caption Data Registers . . . . . . . . . . . . . . . . . . . . . . . 2−41
2.20.49 WSS Data Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2−41
2.20.50 VPS Data Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2−42
2.20.51 VITC Data Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2−42
2.20.52 VBI FIFO Read Data Register . . . . . . . . . . . . . . . . . . . . . . . . 2−42
2.20.53 Teletext Filter and Mask Registers . . . . . . . . . . . . . . . . . . . . 2−43
2.20.54 Teletext Filter Control Register . . . . . . . . . . . . . . . . . . . . . . . . 2−44
2.20.55 Interrupt Status Register A . . . . . . . . . . . . . . . . . . . . . . . . . . . 2−45
2.20.56 Interrupt Enable Register A . . . . . . . . . . . . . . . . . . . . . . . . . . 2−46
2.20.57 Interrupt Configuration Register A . . . . . . . . . . . . . . . . . . . . . 2−47
2.20.58 VDP Configuration RAM Register . . . . . . . . . . . . . . . . . . . . . 2−47
2.20.59 VDP Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2−49
2.20.60 FIFO Word Count Register . . . . . . . . . . . . . . . . . . . . . . . . . . . 2−49
2.20.61 FIFO Interrupt Threshold Register . . . . . . . . . . . . . . . . . . . . 2−50
2.20.62 FIFO Reset Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2−50
2.20.63 Line Number Interrupt Register . . . . . . . . . . . . . . . . . . . . . . . 2−50
2.20.64 Pixel Alignment Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2−50
2.20.65 FIFO Output Control Register . . . . . . . . . . . . . . . . . . . . . . . . 2−51
2.20.66 Full Field Enable Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2−51
2.20.67 Line Mode Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2−52
2.20.68 Full Field Mode Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2−53
Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3−1
3
3.1
Absolute Maximum Ratings Over Operating Free-Air Temperature
Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3−1
3.2
Recommended Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . 3−1
3.2.1
Crystal Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3−1
3.3
Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3−2
3.3.1
3.3.2
3.3.3
DC Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . 3−2
Analog Processing and A/D Converters . . . . . . . . . . . . . . . . 3−2
Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3−3
3.3.3.1
3.3.3.2
Clocks, Video Data, Sync Timing . . . . . . . . . . . 3−3
I C Host Port Timing . . . . . . . . . . . . . . . . . . . . . 3−4
2
4
Example Register Settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4−1
4.1
Example 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4−1
4.1.1
4.1.2
Assumptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4−1
Recommended Settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4−1
4.2
Example 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4−1
4.2.1
4.2.2
Assumptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4−1
Recommended Settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4−1
5
6
Application Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5−1
5.1 Application Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5−1
Mechanical Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6−1
v
List of Illustrations
Figure
1−1
2−1
2−2
2−3
2−4
2−5
2−6
2−7
2−8
2−9
3−1
3−2
5−1
Title
Page
Functional Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1−4
Composite Processing Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2−2
8-bit 4:2:2, Timing With 2x Pixel Clock (SCLK) Reference . . . . . . . . . . . . 2−6
Horizontal Synchronization Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2−7
AVID Application . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2−8
Reference Clock Configurations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2−11
GLCO Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2−12
RTC Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2−13
Configuration Shared Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2−19
Horizontal Sync . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2−28
Clocks, Video Data, and Sync Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3−3
2
I C Host Port Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3−4
Application Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5−1
List of Tables
Table
Title
Page
1−1
2−1
2−2
2−3
2−4
2−5
2−6
2−7
2−8
2−9
Terminal Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1−5
Data Types Supported by the VDP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2−3
Ancillary Data Format and Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2−4
Summary of Line Frequencies, Data Rates, and Pixel Counts . . . . . . . . 2−5
EAV and SAV Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2−8
Write Address Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2−9
2
I C Terminal Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2−9
Read Address Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2−10
Reset and Power Down Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2−13
Registers Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2−14
2−10 Analog Channel and Video Mode Selection . . . . . . . . . . . . . . . . . . . . . . . . 2−16
2−11 Digital Output Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2−18
2−12 Clock Delays (SCLKs) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2−28
2−13 VBI Configuration RAM For Signals With Pedestal . . . . . . . . . . . . . . . . . . 2−48
vi
1 Introduction
The TVP5150A device is an ultralow power NTSC/PAL/SECAM video decoder. Available in a space saving 32-pin
TQFP package, the TVP5150A decoder converts NTSC, PAL, and SECAM video signals to 8-bit ITU-R BT.656
format. Discrete syncs are also available. The optimized architecture of the TVP5150A decoder allows for
ultralow-power consumption. The decoder consumes 115 mW of power in typical operation and consumes less than
1 mW in power-down mode, considerably increasing battery life in portable applications. The decoder uses just one
2
crystal for all supported standards. The TVP5150A decoder can be programmed using an I C serial interface. The
decoder uses a 1.8-V supply for its analog and digital supplies, and a 3.3-V supply for its I/O.
The TVP5150A decoder converts baseband analog video into digital YCbCr 4:2:2 component video. Composite and
S-video inputs are supported. The TVP5150A decoder includes one 9-bit analog-to-digital converter (ADC) with 2x
sampling. Sampling is ITU-R BT.601 (27.0 MHz, generated from the 14.31818-MHz crystal or oscillator input) and
is line-locked. The output formats can be 8-bit 4:2:2 or 8-bit ITU-R BT.656 with embedded synchronization.
The TVP5150A decoder utilizes Texas Instruments patented technology for locking to weak, noisy, or unstable
signals. A Genlock/real-time control (RTC) output is generated for synchronizing downstream video encoders.
Complementary 4-line adaptive comb filtering is available for both the luma and chroma data paths to reduce both
cross-luma and cross-chroma artifacts; a chroma trap filter is also available.
Video characteristics including hue, contrast, brightness, saturation, and sharpness may be programmed using the
2
industry standard I C serial interface. The TVP5150A decoder generates synchronization, blanking, lock, and clock
signals in addition to digital video outputs. The TVP5150A decoder includes methods for advanced vertical blanking
interval (VBI) data retrieval. The VBI data processor slices, parses, and performs error checking on teletext, closed
caption, and other data in several formats.
The TVP5150A decoder detects copy-protected input signals according to the Macrovision standard and detects
Type 1, 2, 3, and colorstripe pulses.
The main blocks of the TVP5150A decoder include:
•
•
•
•
•
•
•
•
•
•
Robust sync detector
ADC with analog processor
Y/C separation using 4-line adaptive comb filter
Chrominance processor
Luminance processor
Video clock/timing processor and power-down control
Output formatter
2
I C interface
VBI data processor
Macrovision detection for composite and S-video
1.1 Features
•
•
•
•
Accepts NTSC (M, 4.43), PAL (B, D, G, H, I, M, N), and SECAM (B, D, G, K, K1, L) video data
Supports ITU-R BT.601 standard sampling
High-speed 9-bit ADC
Two composite inputs or one S-video input
Macrovision is a trademark of Macrovision Corporation.
Other trademarks are the property of their respective owners.
1−1
•
Fully differential CMOS analog preprocessing channels with clamping and automatic gain control (AGC)
for best signal-to-noise (S/N) performance
•
•
•
•
•
Ultralow power consumption: 115 mW typical
32-pin TQFP package
Power-down mode: <1 mW
2
Brightness, contrast, saturation, hue, and sharpness control through I C
Complementary 4-line (3-H delay) adaptive comb filters for both cross-luminance and cross-chrominance
noise reduction
•
•
•
•
•
Patented architecture for locking to weak, noisy, or unstable signals
Single 14.31818-MHz crystal for all standards
Internal phase-locked loop (PLL) for line-locked clock and sampling
Subcarrier Genlock output for synchronizing color subcarrier of external encoder
Standard programmable video output format:
−
−
ITU-R BT.656, 8-bit 4:2:2 with embedded syncs
8-bit 4:2:2 with discrete syncs
•
•
Macrovision copy protection detection
Advanced programmable video output formats:
−
−
2x oversampled raw VBI data during active video
Sliced VBI data during horizontal blanking or active video
•
VBI modes supported
−
−
−
−
−
Teletext (NABTS, WST)
Closed-caption decode with FIFO, and extended data services (EDS)
Wide screen signaling, video program system, CGMS, vertical interval time code
Gemstar 1x/2x electronic program guide compatible mode
Custom configuration mode that allows the user to program the slice engine for unique VBI data signals
•
Power-on reset
1.2 Product Family
This data manual covers three devices in the TVP5150A product family: the TVP5150APBS, the TVP5150AM1PBS,
and the TVP5150AM1ZQC. The hardware for these three devices is identical. The following software changes are
the differences between these two devices. For the remainder of this document, unless otherwise noted, TVP5150A
refers to all three devices.
•
•
TVP5150APBS
−
−
−
ROM version 3.21
SECAM is masked from the autoswitch process in the default mode of register 0x04
Only supports ITU-R BT656.4 timing
TVP5150AM1PBS/TVP5150AM1ZQC
−
−
−
ROM version 4.00
SECAM is unmasked from the autoswitch process in the default mode of register 0x04
Addition of register 0x30 to select ITU-R BT656.3 or ITU-R BT656.4 timing
1−2
1.3 Applications
The following is a partial list of suggested applications:
•
•
•
•
•
•
•
Digital television
PDA
Notebook PCs
Cell phones
Video recorder/players
Internet appliances/web pads
Handheld games
1.4 Related Products
•
TVP5146 NTSC/PAL/SECAM 4x10-Bit Digital Video Decoder With Macrovision Detection, YPbPr/RGB
Inputs, 5-Line Comb Filter and SCART/Digital RGB Overlay SupportDecoder With Robust Sync Detector,
Literature Number SLES084
1.5 Ordering Information
PACKAGED DEVICES
32TQFP-PBS
T
A
PACKAGE OPTION
0°C to 70°C
0°C to 70°C
0°C to 70°C
0°C to 70°C
0°C to 70°C
0°C to 70°C
TVP5150APBS
Tray
Tape and reel
Tray
TVP5150APBSR
TVP5150AM1PBS
TVP5150AM1PBSR
TVP5150AM1ZQC
TVP5150AM1ZQCR
Tape and reel
Tray
Tape and reel
1−3
1.6 Functional Block Diagram
MACROVISION
DETECTION
LUMINANCE
PROCESSING
M
U
X
AIP1A
AIP1B
A/D
YOUT[7:0]
YCbCr 8-BIT
4:2:2
AGC
CHROMINANCE
PROCESSING
VBI / DATA SLICER
SCL
SDA
2
I C
HOST PROCESSOR
INTERFACE
PDN
XTAL1
XTAL2
FID/GLCO
VSYNC/PALI
INTERQ/GPCL/VBLK
HSYNC
PCLK/SCLK
AVID
Figure 1−1. Functional Block Diagram
1−4
1.7 Terminal Assignments
TQFP PACKAGE
(TOP VIEW)
ZQC PACKAGE
(BOTTOM VIEW)
32 31 30 29 28 27 26 25
G
F
1
2
3
4
5
6
7
8
24
AIP1A
AIP1B
VSYNC/PALI
FID/GLCO
SDA
23
22
21
20
19
18
17
E
D
C
B
A
PLL_AGND
PLL_AVDD
XTAL1/OSC
XTAL2
SCL
DVDD
DGND
AGND
YOUT0
YOUT1
RESETB
9 10 11 12 13 14 15 16
7
1
2
3
4
5
6
1.8 Terminal Functions
Table 1−1. Terminal Functions
TERMINAL
NUMBER
NAME
I/O
DESCRIPTION
PBS
ZQC
Analog Section
AGND
7
1
E1
A1
I
I
Substrate. Connect to analog ground.
Analog input. Connect to the video analog input via 0.1-µF capacitor. The maximum input range
is 0−0.75 V , and may require an attenuator to reduce the input amplitude to the desired level.
AIP1A
PP
If not used, connect to AGND via 0.1-µF capacitor. Refer to Figure 5−1.
Analog input. Connect to the video analog input via 0.1-µF capacitor. The maximum input range
is 0−0.75 V , and may require an attenuator to reduce the input amplitude to the desired level.
AIP1B
2
B1
I
PP
If not used, connect to AGND via 0.1-µF capacitor. Refer to Figure 5−1.
Analog ground
CH_AGND
CH_AVDD
31
32
A3
A2
I
I
Analog supply. Connect to 1.8-V analog supply.
B2, B3, B6, C4,
C5, D3−D6,
E2−E5, F2, F5,
F6
NC
−
−
No connect
PLL_AGND
PLL_AVDD
3
4
C2
C1
I
I
PLL ground. Connect to analog ground.
PLL supply. Connect to 1.8-V analog supply.
1−5
Table 1−1. Terminal Functions (Continued)
TERMINAL
NUMBER
PBS ZQC
Analog Section (continued)
I/O
DESCRIPTION
NAME
A/D reference ground. Connect to analog ground through 1-µF capacitor. Also, it is recommended to
connect directly to REFP through 1-µF capacitor. Refer to Figure 5−1.
REFM
30
29
A4
B4
I
I
REFP
A/D reference supply. Connect to analog ground through 1-µF capacitor. Refer to Figure 5−1.
Digital Section
Active video indicator. This signal is high during the horizontal active time of the video output. AVID
toggling during vertical blanking intervals is controlled by bit 2 of the active video cropping start pixel
LSB register at address 12h (see Section 2.20.17).
AVID
26
A6
O
DGND
DVDD
19
20
E6
E7
I
I
Digital ground
Digital supply. Connect to 1.8-V digital supply
FID: Odd/even field indicator or vertical lock indicator. For the odd/even indicator, a 1 indicates the odd
field.
GLCO: This serial output carries color PLL information. A slave device can decode the information to
allow chroma frequency control from the TVP5150A decoder. Data is transmitted at the SCLK rate in
Genlock mode. In RTC mode, SCLK/4 is used.
FID/GLCO
HSYNC
23
25
27
C6
A7
B5
O
O
Horizontal synchronization signal
INTREQ: Interrupt request output.
GPCL/VBLK: General-purpose control logic. This terminal has two functions:
1. GPCL: General-purpose output. In this mode the state of GPCL is directly programmed via I C.
INTREQ/GPCL/
VBLK
2
I/O
2. VBLK: Vertical blank output. In this mode the GPCL terminal indicates the vertical blanking interval
2
of the output video. The beginning and end times of this signal are programmable via I C.
IO_DVDD
10
9
G2
G1
I
Digital supply. Connect to 3.3 V.
PCLK/SCLK
O
System clock at either 1x or 2x the frequency of the pixel clock.
Power-down terminal (active low). Puts the decoder in standby mode. Preserves the value of the
registers.
PDN
28
8
A5
F1
I
I
Active-low reset. RESETB can be used only when PDN = 1.
When RESETB is pulled low, it resets all the registers and restarts the internal microprocessor.
RESETB
2
I/O I C serial clock (open drain)
SCL
SDA
21
22
D7
C7
2
I/O I C serial data (open drain)
VSYNC: Vertical synchronization signal
PALI: PAL line indicator or horizontal lock indicator
For the PAL line indicator:
VSYNC/PALI
24
B7
O
1 = Indicates a noninverted line
0 = Indicates an inverted line
External clock reference. The user may connect XTAL1 to an oscillator or to one terminal of a crystal
oscillator. The user may connect XTAL2 to the other terminal of the crystal oscillator or not connect
XTAL2 at all. One single 14.31818-MHz crystal or oscillator is needed for ITU-R BT.601 sampling, for
all supported standards.
XTAL1/OSC
XTAL2
5
6
D2
D1
I
O
12
13
14
15
16
17
18
G3
F4
G4
G5
G6
G7
F7
YOUT[6:0]
I/O Output decoded ITU-R BT.656 output/YCbCr 4:2:2 output with discrete sync.
2
I2CSEL: Determines address for I C (sampled during reset). A pullup or pulldown register is needed
(>1 kΩ) to program the terminal to the desired address.
1 = Address is 0xBA
YOUT7/I2CSEL
11
F3
I/O
0 = Address is 0xB8
YOUT7: MSB of output decoded ITU-R BT.656 output/YCbCr 4:2:2 output.
1−6
2 Functional Description
2.1 Analog Front End
The TVP5150A decoder has an analog input channel that accepts two video inputs, which are ac-coupled. The
decoder supports a maximum input voltage range of 0.75 V; therefore, an attenuation of one-half is needed for most
input signals with a peak-to-peak variation of 1.5 V. The maximum parallel termination before the input to the device
is 75 Ω. Please refer to the applications diagram in Figure 5−1 for the recommended configuration. The two analog
input ports can be connected as follows:
•
•
Two selectable composite video inputs or
One S-video input
An internal clamping circuit restores the ac-coupled video signal to a fixed dc level.
The programmable gain amplifier (PGA) and the AGC circuit work together to make sure that the input signal is
amplified sufficiently to ensure the proper input range for the ADC.
The ADC has 9 bits of resolution and runs at a maximum speed of 27 MHz. The clock input for the ADC comes from
the PLL.
2.2 Composite Processing Block Diagram
The composite processing block processes NTSC/PAL/SECAM signals into the YCbCr color space. Figure 2−1
explains the basic architecture of this processing block.
Figure 2−1 illustrates the luminance/chrominance (Y/C) separation process in the TVP5150A decoder. The
composite video is multiplied by subcarrier signals in the quadrature modulator to generate the color difference
signals Cb and Cr. Cb and Cr are then low-pass (LP) filtered to achieve the desired bandwidth and to reduce crosstalk.
An adaptive 4-line comb filter separates CbCr from Y. Chroma is remodulated through another quadrature modulator
and subtracted from the line-delayed composite video to generate luma. Contrast, brightness, hue, saturation, and
2
sharpness (using the peaking filter) are programmable via I C.
The Y/C separation is bypassed for S-video input. For S-video, the remodulation path is disabled.
2.3 Adaptive Comb Filtering
The 4-line comb filter can be selectively bypassed in the luma or chroma path. If the comb filter is bypassed in the
luma path, then chroma notch filters are used. TI’s patented adaptive 4-line comb filter algorithm reduces artifacts
such as hanging dots at color boundaries and detects and properly handles false colors in high frequency luminance
images such as a multiburst pattern or circle pattern.
2.4 Color Low-Pass Filter
In some applications, it is desirable to limit the Cb/Cr bandwidth to avoid crosstalk. This is especially true in case of
video signals that have asymmetrical Cb/Cr sidebands. The color LP filters provided limit the bandwidth of the Cb/Cr
signals.
Color LP filters are needed when the comb filtering turns off, due to extreme color transitions in the input image.
Please refer to Section 2.20.25, Chrominance Control #2 Register, for the response of these filters. The filters have
three options that allow three different frequency responses based on the color frequency characteristics of the input
video.
2−1
Gain Factor
Peak
Detector
Bandpass
X
Peaking
Composite
Delay
+
Delay
Y
Line
Delay
−
Y
Quadrature
Modulation
Contrast
Brightness
Saturation
Adjust
Cb
Cr
SECAM Luma
Notch
Filter
Cb
Cr
Notch
Filter
SECAM Color
Demodulation
Color
LPF ↓ 2
Composite
Cb
4-Line
Adaptive
Comb
Burst
Accumulator
(Cb)
LP
Filter
Delay
Filter
LP
Filter
Color
LPF ↓ 2
Quadrature
Modulation
Delay
Composite
Cr
Burst
Accumulator
(Cr)
Figure 2−1. Composite Processing Block Diagram
2.5 Luminance Processing
The luma component is derived from the composite signal by subtracting the remodulated chroma information. A line
delay exists in this path to compensate for the line delay in the adaptive comb filter in the color processing chain. The
luma information is then fed into the peaking circuit, which enhances the high frequency components of the signal,
thus improving sharpness.
2.6 Chrominance Processing
For NTSC/PAL formats, the color processing begins with a quadrature demodulator. The Cb/Cr signals then pass
through the gain control stage for chroma saturation adjustment. An adaptive comb filter is applied to the demodulated
signals to separate chrominance and eliminate cross-chrominance artifacts. An automatic color killer circuit is also
included in this block. The color killer suppresses the chroma processing when the color burst of the video signal is
weak or not present. The SECAM standard is similar to PAL except for the modulation of color which is FM instead
of QAM.
2−2
2.7 Timing Processor
The timing processor is a combination of hardware and software running in the internal microprocessor that serves
to control horizontal lock to the input sync pulse edge, AGC and offset adjustment in the analog front end, vertical
sync detection, and Macrovisiont detection.
2.8 VBI Data Processor
The TVP5150A VBI data processor (VDP) slices various data services like teletext (WST, NABTS), closed caption
(CC), wide screen signaling (WSS), etc. These services are acquired by programming the VDP to enable standards
in the VBI. The results are stored in a FIFO and/or registers. The teletext results are stored in a FIFO only. Table 2−1
lists a summary of the types of VBI data supported according to the video standard. It supports ITU-R BT. 601
sampling for each.
Table 2−1. Data Types Supported by the VDP
LINE MODE
REGISTER (D0h−FCh)
BITS [3:0]
SAMPLING
RATE (0Dh) NAME
BIT 7
DESCRIPTION
0000b
0000b
0001b
0001b
0010b
0010b
0011b
0011b
0100b
0100b
0101b
0101b
0110b
0110b
0111b
0111b
1000b
1000b
1001b
1001b
1010b
1010b
1011b
1011b
1100b
1100b
1101b
1110b
1111b
x
1
x
1
x
1
x
1
x
1
x
1
x
1
x
1
x
1
x
1
x
1
x
1
x
1
x
x
x
x
Reserved
WST SECAM 6
Teletext, SECAM
Reserved
x
WST PAL B 6
Teletext, PAL, System B
Reserved
x
WST PAL C 6
Teletext, PAL, System C
Reserved
x
WST, NTSC B 6
Teletext, NTSC, System B
Reserved
x
NABTS, NTSC C 6
Teletext, NTSC, System C
Reserved
x
NABTS, NTSC D 6
Teletext, NTSC, System D (Japan)
Reserved
x
CC, PAL 6
Closed caption PAL
Reserved
x
CC, NTSC 6
Closed caption NTSC
Reserved
x
WSS, PAL 6
Wide-screen signal, PAL
Reserved
x
WSS, NTSC 6
Wide-screen signal, NTSC
Reserved
x
VITC, PAL 6
Vertical interval timecode, PAL
Reserved
x
VITC, NTSC 6
Vertical interval timecode, NTSC
Reserved
x
VPS, PAL 6
Video program system, PAL
Reserved
x
x
Reserved
Active Video
Active video/full field
2−3
At powerup the host interface is required to program the VDP-configuration RAM (VDP-CRAM) contents with the
lookup table (see Section 2.20.58). This is done through port address C3h. Each read from or write to this address
will auto increment an internal counter to the next RAM location. To access the VDP-CRAM, the line mode registers
(D0h−FCh) must be programmed with FFh to avoid a conflict with the internal microprocessor and the VDP in both
writing and reading. Full field mode must also be disabled.
Available VBI lines are from line 6 to line 27 of both field 1 and field 2. Each line can be any VBI mode.
Output data is available either through the VBI-FIFO (B0h) or through dedicated registers at 90h−AFh, both of which
2
are available through the I C port.
2.9 VBI FIFO and Ancillary Data in Video Stream
Sliced VBI data can be output as ancillary data in the video stream in the ITU-R BT.656 mode. VBI data is output during
the horizontal blanking period following the line from which the data was retrieved. Table 2−2 shows the header format
and sequence of the ancillary data inserted into the video stream. This format is also used to store any VBI data into
the FIFO. The size of FIFO is 512 bytes. Therefore, the FIFO can store up to 11 lines of teletext data with the NTSC
NABTS standard.
Table 2−2. Ancillary Data Format and Sequence
BYTE
NO.
D7
(MSB)
D6
D5
D4
D3
D2
D1
D0
(LSB)
DESCRIPTION
Ancillary data preamble
0
1
2
3
4
5
6
7
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
1
1
1
1
1
1
1
1
NEP
NEP
NEP
EP
EP
EP
0
1
0
DID2
F2
N2
DID1
F1
N1
DID0
F0
N0
Data ID (DID)
F5
N5
F4
N4
F3
N3
Secondary data ID (SDID)
Number of 32 bit data (NN)
Internal data ID0 (IDID0)
Video line # [7:0]
0
0
0
Data
error
Match
#1
Match
#2
Video line # [9:8] Internal data ID1 (IDID1)
st
8
9
1. Data
Data byte
Data byte
Data byte
Data byte
:
1
word
word
2. Data
3. Data
4. Data
:
10
11
:
th
N
m−1. Data
m. Data
Data byte
Data byte
Check sum
Fill byte
NEP
1
EP
0
CS[5:0]
4(N+2)−1
0
0
0
0
0
0
EP:
Even parity for D0−D5
NEP: Negated even parity
DID:
91h: Sliced data of VBI lines of first field
53h: Sliced data of line 24 to end of first field
55h: Sliced data of VBI lines of second field
97h: Sliced data of line 24 to end of second field
SDID:
NN:
This field holds the data format taken from the line mode register of the corresponding line.
Number of Dwords beginning with byte 8 through 4(N+2). This value is the number of Dwords where
each Dword is 4 bytes.
IDID0:
Transaction video line number [7:0]
2−4
IDID1:
CS:
Bit 0/1 = Transaction video line number [9:8]
Bit 2 = Match 2 flag
Bit 3 = Match 1 flag
Bit 4 = 1 if an error was detected in the EDC block. 0 if not.
Sum of D0−D7 of DID through last data byte.
Fill byte: Fill bytes make a multiple of 4 bytes from byte 0 to last fill byte. For teletext modes, byte 8 is the sync pattern
byte. Byte 9 is 1. Data (the first data byte).
2.10 Raw Video Data Output
The TVP5150A decoder can output raw A/D video data at 2x sampling rate for external VBI slicing. This is transmitted
as an ancillary data block during the active horizontal portion of the line and during vertical blanking.
2.11 Output Formatter
The YCbCr digital output can be programmed as 8-bit 4:2:2 or 8-bit ITU-R BT.656 parallel interface standard.
Table 2−3. Summary of Line Frequencies, Data Rates, and Pixel Counts
HORIZONTAL
LINE RATE (kHz)
PIXELS PER
LINE
ACTIVE PIXELS SCLK FREQUENCY
STANDARDS
NTSC (M, 4.43), ITU-R BT.601
PER LINE
(MHz)
27.00
27.00
27.00
27.00
27.00
15.73426
15.625
858
864
858
864
864
720
PAL (B, D, G, H, I), ITU-R BT.601
PAL (M), ITU-R BT.601
720
15.73426
15.625
720
PAL (N), ITU-R BT.601
720
SECAM, ITU-R BT.601
15.625
720
2.12 Synchronization Signals
External (discrete) syncs are provided via the following signals:
•
•
•
•
•
•
VSYNC (vertical sync)
FID/VLK (field indicator or vertical lock indicator)
GPCL/VBLK (general-purpose I/O or vertical blanking indicator)
PALI/HLK (PAL switch indicator or horizontal lock indicator)
HSYNC (horizontal sync)
AVID (active video indicator)
VSYNC, FID, PALI, and VBLK are software-set and programmable to the SCLK pixel count. This allows any possible
alignment to the internal pixel count and line count. The default settings for a 525-/625-line video output are given
as an example below.
2−5
525-Line
525
1
2
3
4
5
6
7
8
9
10
11
20
21
22
Composite
Video
VSYNC
FID
GPCL/VBLK
↔
↔
VBLK Start
VBLK Stop
262 263 264 265 266 267 268 269 270 271 272 273
282 283 284
Composite
Video
VSYNC
FID
GPCL/VBLK
↔
↔
VBLK Start
VBLK Stop
625-Line
310 311 312 313 314 315 316 317 318 319 320
333 334 335 336
Composite
Video
VSYNC
FID
GPCL/VBLK
↔
↔
VBLK Start
VBLK Stop
622 623 624 625
1
2
3
4
5
6
7
20
21
22
23
Composite
Video
VSYNC
FID
GPCL/VBLK
↔
↔
VBLK Start
VBLK Stop
NOTE: Line numbering conforms to ITU-R BT.470.
Figure 2−2. 8-bit 4:2:2, Timing With 2x Pixel Clock (SCLK) Reference
2−6
ITU-R BT.656 timing.
…
…
NTSC 601 1436 1437 1438 1439 1440 1441
…
…
1455 1456
1459 1460
…
…
1713 1714 1715
1725 1726 1727
0
0
1
1
2
2
3
3
1583 1584
1587 1588
1711 1712
1723 1724
PAL 601
SECAM
1436 1437 1438 1439 1440 1441
1436 1437 1438 1439 1440 1441
…
…
17 17 17 17
24 25 26 27
…
…
1479 1480
…
…
1721 1722 1723
1607 1608
1719 1720
Y
1
Cb
0
Y
0
Cr
0
ITU 656
Cb
Y
Cr
Y
FF
00
10
80
00
00
XX
10
80
10
FF
359
718
359 719
Datastream
HSYNC
AVID
↔
HSYNC Start
↔
↔
AVID Stop
AVID Start
NOTE: AVID rising edge occurs 4 SCLK cycles early when in the ITU-R BT.656 output mode.
Figure 2−3. Horizontal Synchronization Signals
2.13 AVID Cropping
AVID or active video cropping provides a means to decrease bandwidth of the video output. This is accomplished
by horizontally blanking a number of AVID pulses and by vertically blanking a number of lines per frame. The
horizontal AVID cropping is controlled using registers 11h and 12h for start pixels MSB and LSB, respectively.
Registers 13h and 14h provide access to stop pixels MSB and LSB, respectively. The vertical AVID cropping is
controlled using the vertical blanking (VBLK) start and stop registers at addresses 18h and 19h. Figure 2−4 shows
an AVID application.
2−7
Active Video Area
AVID Cropped
Area
AVID Start
AVID Stop
HSYNC
Figure 2−4. AVID Application
2.14 Embedded Syncs
Standards with embedded syncs insert SAV and EAV codes into the datastream at the beginning and end of horizontal
blanking. These codes contain the V and F bits which also define vertical timing. F and V change on EAV. Table 2−4
gives the format of the SAV and EAV codes.
H equals 1 always indicates EAV. H equals 0 always indicates SAV. The alignment of V and F to the line and field
counter varies depending on the standard. Please refer to ITU-R BT.656 for more information on embedded syncs.
The P bits are protection bits:
P3 = V xor H
P2 = F xor H
P1 = F xor V
P0 = F xor V xor H
Table 2−4. EAV and SAV Sequence
8-BIT DATA
D7 (MSB)
D6
1
D5
1
D4
1
D3
1
D2
1
D1
1
D0
1
Preamble
Preamble
Preamble
Status word
1
0
0
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
F
V
H
P3
P2
P1
P0
2−8
2
2.15 I C Host Interface
2
The I C standard consists of two signals, serial input/output data line (SDA) and input/output clock line (SCL), which
carry information between the devices connected to the bus. A third signal (I2CSEL) is used for slave address
2
selection. Although the I C system can be multimastered, the TVP5150A decoder functions as a slave device only.
Both SDA and SCL must be connected to a positive supply voltage via a pullup resistor. When the bus is free, both
lines are high. The slave address select terminal (I2CSEL) enables the use of two TVP5150A decoders tied to the
2
same I C bus. At power up, the status of the I2CSEL is polled. Depending on the write and read addresses to be used
for the TVP5150A decoder, it can either be pulled low or high through a resistor. This terminal is multiplexed with
YOUT7 and hence must not be tied directly to ground or IO_DVDD. Table 2−6 summarizes the terminal functions of
2
the I C-mode host interface.
Table 2−5. Write Address Selection
I2CSEL
WRITE ADDRESS
0
1
B8h
BAh
2
Table 2−6. I C Terminal Description
SIGNAL
TYPE
I
DESCRIPTION
I2CSEL (YOUT7)
Slave address selection
Input/output clock line
Input/output data line
SCL
SDA
I/O (open drain)
I/O (open drain)
Data transfer rate on the bus is up to 400 kbits/s. The number of interfaces connected to the bus is dependent on
the bus capacitance limit of 400 pF. The data on the SDA line must be stable during the high period of the SCL except
for start and stop conditions. The high or low state of the data line can only change with the clock signal on the SCL
2
line being low. A high-to-low transition on the SDA line while the SCL is high indicates an I C start condition. A
2
low-to-high transition on the SDA line while the SCL is high indicates an I C stop condition.
Every byte placed on the SDA must be 8 bits long. The number of bytes which can be transferred is unrestricted. Each
2
byte must be followed by an acknowledge bit. The acknowledge-related clock pulse is generated by the I C master.
2
2.15.1 I C Write Operation
Data transfers occur utilizing the following illustrated formats.
2
An I C master initiates a write operation to the TVP5150A decoder by generating a start condition (S) followed by
2
the TVP5150A I C address (as shown below), in MSB first bit order, followed by a 0 to indicate a write cycle. After
receiving an acknowledge from the TVP5150A decoder, the master presents the subaddress of the register, or the
first of a block of registers it wants to write, followed by one or more bytes of data, MSB first. The TVP5150A decoder
2
acknowledges each byte after completion of each transfer. The I C master terminates the write operation by
generating a stop condition (P).
Step 1
0
2
I C Start (master)
S
Step 2
7
6
5
4
3
2
1
0
2
I C General address (master)
1
0
1
1
1
0
X
0
Step 3
9
2
I C Acknowledge (slave)
A
Step 4
7
6
5
4
3
2
1
0
2
I C Write register address (master)
addr
addr
addr
addr
addr
addr
addr
addr
2−9
Step 5
9
2
I C Acknowledge (slave)
A
Step 6
7
6
5
4
3
2
1
0
2
I C Write data (master)
Data
Data
Data
Data
Data
Data
Data
Data
†
Step 7
9
2
I C Acknowledge (slave)
A
Step 8
0
2
I C Stop (master)
P
†
Repeat steps 6 and 7 until all data have been written.
2
2.15.2 I C Read Operation
2
The read operation consists of two phases. The first phase is the address phase. In this phase, an I C master initiates
2
a write operation to the TVP5150A decoder by generating a start condition (S) followed by the TVP5150A I C address,
in MSB first bit order, followed by a 0 to indicate a write cycle. After receiving acknowledges from the TVP5150A
decoder, the master presents the subaddress of the register or the first of a block of registers it wants to read. After
the cycle is acknowledged, the master terminates the cycle immediately by generating a stop condition (P).
Table 2−7. Read Address Selection
I2CSEL
READ ADDRESS
0
1
B9h
BBh
2
The second phase is the data phase. In this phase, an I C master initiates a read operation to the TVP5150A decoder
2
by generating a start condition followed by the TVP5150A I C address (as shown below for a read operation), in MSB
2
first bit order, followed by a 1 to indicate a read cycle. After an acknowledge from the TVP5150A decoder, the I C
2
master receives one or more bytes of data from the TVP5150A decoder. The I C master acknowledges the transfer
at the end of each byte. After the last data byte desired has been transferred from the TVP5150A decoder to the
master, the master generates a not acknowledge followed by a stop.
2.15.2.1Read Phase 1
Step 1
0
2
I C Start (master)
S
Step 2
7
6
5
4
3
2
1
0
2
I C General address (master)
1
0
1
1
1
0
X
0
Step 3
9
2
I C Acknowledge (slave)
A
Step 4
7
6
5
4
3
2
1
0
2
I C Read register address (master)
addr
addr
addr
addr
addr
addr
addr
addr
Step 5
9
2
I C Acknowledge (slave)
A
Step 6
0
2
I C Stop (master)
P
2−10
2.15.2.2Read Phase 2
Step 7
0
2
I C Start (master)
S
Step 8
7
6
5
4
3
2
1
0
2
I C General address (master)
1
0
1
1
1
0
X
1
Step 9
9
2
I C Acknowledge (slave)
A
Step 10
7
6
5
4
3
2
1
0
2
I C Read data (slave)
Data
Data
Data
Data
Data
Data
Data
Data
†
Step 11
9
2
I C Not acknowledge (master)
A
Step 12
0
2
I C Stop (master)
P
†
Repeat steps 10 and 11 for all bytes read. Master does not acknowledge the last read data received.
2
2.15.2.3I C Timing Requirements
2
The TVP5150A decoder requires delays in the I C accesses to accommodate its internal processor’s timing. In
2
2
accordance with I C specifications, the TVP5150A decoder holds the I C clock line (SCL) low to indicate the wait
2
2
2
period to the I C master. If the I C master is not designed to check for the I C clock line held-low condition, then the
maximum delays must always be inserted where required. These delays are of variable length; maximum delays are
indicated in the following diagram:
Normal register writing address 00h−8Fh (addresses 90h−FFh do not require delays)
Slave address
(B8h)
Data
(XXh)
Start
Ack
Subaddress
Ack
Ack
Wait 64 µs
Stop
The 64-µs delay is for all registers that do not require a reinitialization. Delays may be more for some registers.
2.16 Clock Circuits
An internal line-locked PLL generates the system and pixel clocks. A 14.31818-MHz clock is required to drive the PLL.
This may be input to the TVP5150A decoder on terminal 5 (XTAL1), or a crystal of 14.31818-MHz fundamental
resonant frequency may be connected across terminals 5 and 6 (XTAL2). Figure 2−5 shows the reference clock
configurations. For the example crystal circuit shown (a parallel-resonant crystal with 14.31818-MHz fundamental
frequency), the external capacitors must have the following relationship:
C
= C = 2C − C
,
L1
L2
L
STRAY
where C
configurations.
is the terminal capacitance with respect to ground. Figure 2−5 shows the reference clock
STRAY
TVP5150A
TVP5150A
14.31818-MHz
Crystal
C
C
L1
L2
14.31818-MHz
TTL Clock
5
6
5
6
XTAL1
XTAL1
XTAL2
XTAL2
Figure 2−5. Reference Clock Configurations
2−11
2.17 Genlock Control and RTC
A Genlock control (GLCO) function is provided to support a standard video encoder to synchronize its internal color
oscillator for properly reproduced color with unstable timebase sources like VCRs.
The frequency control word of the internal color subcarrier digital control oscillator (DTO) and the subcarrier phase
reset bit are transmitted via terminal 23 (GLCO). The frequency control word is a 23-bit binary number. The frequency
of the DTO can be calculated from the following equation:
Fctrl
x
=
Fdto
Fsclk
23
2
where F
SCLK.
is the frequency of the DTO, F is the 23-bit DTO frequency control, and F
is the frequency of the
dto
ctrl
sclk
2.17.1 TVP5150A Genlock Control Interface
2
A write of 1 to bit 4 of the chrominance control register at I C subaddress 1Ah causes the subcarrier DTO phase reset
bit to be sent on the next scan line on GLCO. The active low reset bit occurs 7 SCLKs after the transmission of the
last bit of DCO frequency control. Upon the transmission of the reset bit, the phase of the TVP5150A internal
subcarrier DCO is reset to zero.
A Genlock slave device can be connected to the GLCO terminal and uses the information on GLCO to synchronize
its internal color phase DCO to achieve clean line and color lock.
Figure 2−6 shows the timing diagram of the GLCO mode.
SCLK
GLCO
MSB
21
LSB
0
22
>128 SCLK
23 SCLK
7 SCLK
23-Bit Frequency Control
1 SCLK
1 SCLK
DCO Reset Bit
Start Bit
Figure 2−6. GLCO Timing
2−12
2.17.2 RTC Mode
Figure 2−7 shows the timing diagram of the RTC mode. Clock rate for the RTC mode is 4 times slower than the GLCO
clock rate. For PLL frequency control, the upper 22 bits are used. Each frequency control bit is 2 clock cycles long.
The active low reset bit occurs 6 CLKs after the transmission of the last bit of PLL frequency control.
M
S
B
L
S
B
RTC
21
0
128 CLK
16 CLK
2 CLK
44 CLK
1 CLK
22-Bit Fsc Frequency Control
PAL
Switch
2 CLK
Start
Bit
3 CLK
1 CLK
Reset
Bit
Figure 2−7. RTC Timing
2.18 Reset and Power Down
Terminals 8 (RESETB) and 28 (PDN) work together to put the TVP5150A decoder into one of the two modes.
Table 2−8 shows the configuration.
Table 2−8. Reset and Power Down Modes
PDN
RESETB
CONFIGURATION
Reserved (unknown state)
Powers down the decoder
Resets the decoder
0
0
1
1
0
1
0
1
Normal operation
2.19 Internal Control Registers
The TVP5150A decoder is initialized and controlled by a set of internal registers which set all device operating
2
parameters. Communication between the external controller and the TVP5150A decoder is through I C. Table 2−9
shows the summary of these registers. The reserved registers must not be written. Reserved bits in the defined
registers must be written with 0s, unless otherwise noted. The detailed programming information of each register is
described in the following sections.
2−13
Table 2−9. Registers Summary
REGISTER FUNCTION
ADDRESS
00h
DEFAULT
00h
R/W
R/W
R/W
R/W
R/W
Video input source selection #1
Analog channel controls
Operation mode controls
Miscellaneous controls
Autoswitch mask:
01h
15h
02h
00h
03h
01h
TVP5150A
04h
04h
FCh
DCh
00h
10h
60h
00h
80h
80h
00h
80h
47h
00h
08h
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
TVP5150AM1
Reserved
05h
Color killer threshold control
Luminance processing control #1
Luminance processing control #2
Brightness control
06h
07h
08h
09h
Color saturation control
Hue control
0Ah
0Bh
0Ch
0Dh
0Eh
0Fh
10h
Contrast control
Outputs and data rates select
Luminance processing control #3
Configuration shared pins
Reserved
Active video cropping start MSB
Active video cropping start LSB
Active video cropping stop MSB
Active video cropping stop LSB
Genlock/RTC
11h
00h
00h
00h
00h
01h
80h
R/W
R/W
R/W
R/W
R/W
R/W
12h
13h
14h
15h
Horizontal sync start
16h
Reserved
17h
Vertical blanking start
Vertical blanking stop
Chrominance processing control #1
Chrominance processing control #2
Interrupt reset register B
Interrupt enable register B
Interrupt configuration register B
Reserved
18h
00h
00h
0Ch
14h
00h
00h
00h
R/W
R/W
R/W
R/W
R/W
R/W
R/W
19h
1Ah
1Bh
1Ch
1Dh
1Eh
1Fh−27h
28h
Video standard
00h
R/W
Reserved
29h−2Bh
2Ch
2Dh
2Eh
2Fh
30h
Cb gain factor
R
Cr gain factor
R
Macrovision on counter
Macrovision off counter
656 revision select (TVP5150AM1 only)
0Fh
01h
00h
R/W
R/W
R/W
R = Read only
W = Write only
R/W = Read and write
2−14
Table 2−9. Registers Summary (Continued)
REGISTER FUNCTION
ADDRESS
31h−7Fh
80h
DEFAULT
R/W
Reserved
MSB of device ID
51h
50h
R
R
LSB of device ID
81h
ROM major version:
TVP5150A
82h
82h
03h
04h
R
R
TVP5150AM1
ROM minor version:
TVP5150A
83h
83h
21h
00h
R
R
R
R
R
R
R
R
R
R
R
TVP5150AM1
Vertical line count MSB
Vertical line count LSB
Interrupt status register B
Interrupt active register B
Status register #1
84h
85h
86h
87h
88h
Status register #2
89h
Status register #3
8Ah
Status register #4
8Bh
Status register #5
8Ch
Reserved
8Dh−8Fh
90h−93h
94h−99h
9Ah−A6h
A7h−AFh
B0h
Closed caption data registers
WSS data registers
VPS data registers
VITC data registers
VBI FIFO read data
Teletext filter 1
R
R
R
R
R
B1h−B5h
B6h−BAh
BBh
00h
00h
00h
R/W
R/W
R/W
Teletext filter 2
Teletext filter enable
Reserved
BCh−BFh
C0h
Interrupt status register A
Interrupt enable register A
Interrupt configuration
VDP configuration RAM data
Configuration RAM address low byte
Configuration RAM address high byte
VDP status register
FIFO word count
00h
00h
04h
DCh
0Fh
00h
R/W
R/W
R/W
R/W
R/W
R/W
R
C1h
C2h
C3h
C4h
C5h
C6h
C7h
R
FIFO interrupt threshold
FIFO reset
C8h
80h
00h
00h
4Eh
00h
R/W
W
C9h
Line number interrupt
Pixel alignment register low byte
Pixel alignment register high byte
CAh
R/W
R/W
R/W
CBh
CCh
R = Read only
W = Write only
R/W = Read and write
2−15
Table 2−9. Registers Summary (Continued)
REGISTER FUNCTION
ADDRESS
CDh
DEFAULT
R/W
FIFO output control
Reserved
01h
R/W
CEh
Full field enable
CFh
00h
R/W
R/W
R/W
D0h
D1h−FBh
00h
FFh
Line mode registers
Full field mode register
Reserved
FCh
7Fh
FDh−FFh
R = Read only
W = Write only
R/W = Read and write
2.20 Register Definitions
2.20.1 Video Input Source Selection #1 Register
Address
Default
00h
00h
7
6
5
4
3
2
1
0
Channel 1 source
selection
Reserved
Black output
Reserved
S-video selection
Channel 1 source selection:
0 = AIP1A selected (default)
1 = AIP1B selected
Table 2−10. Analog Channel and Video Mode Selection
ADDRESS 00
INPUT(S) SELECTED
BIT 1
BIT 0
Composite
S-Video
AIP1A (default)
AIP1B
0
1
x
0
0
1
AIP1A (luma), AIP1B (chroma)
Black output:
0 = Normal operation (default)
1 = Force black screen output (outputs synchronized)
a. Forced to 10h in normal mode
b. Forced to 01h in extended mode
2−16
2.20.2 Analog Channel Controls Register
Address
Default
01h
15h
7
6
5
4
3
2
1
0
Reserved
1
Automatic offset control
Automatic gain control
Automatic offset control:
00 = Disabled
01 = Automatic offset enabled (default)
10 = Reserved
11 = Offset level frozen to the previously set value
Automatic gain control (AGC):
00 = Disabled (fixed gain value)
01 = AGC enabled (default)
10 = Reserved
11 = AGC frozen to the previously set value
2.20.3 Operation Mode Controls Register
Address
Default
02h
00h
7
6
5
4
3
2
1
0
Color burst
reference enable
White peak
disable
Color subcarrier
PLL frozen
Luma peak
disable
Reserved
TV/VCR mode
Power down mode
Color burst reference enable
0 = Color burst reference for AGC disabled (default)
1 = Color burst reference for AGC enabled
TV/VCR mode
00 = Automatic mode determined by the internal detection circuit. (default)
01 = Reserved
10 = VCR (nonstandard video) mode
11 = TV (standard video) mode
With automatic detection enabled, unstable or nonstandard syncs on the input video forces the detector into the VCR
mode. This turns off the comb filters and turns on the chroma trap filter.
White peak disable
0 = White peak protection enabled (default)
1 = White peak protection disabled
Color subcarrier PLL frozen:
0 = Color subcarrier PLL increments by the internally generated phase increment. (default)
GLCO pin outputs the frequency increment.
1 = Color subcarrier PLL stops operating.
GLCO pin outputs the frozen frequency increment.
Luma peak disable
0 = Luma peak processing enabled (default)
1 = Luma peak processing disabled
Power down mode:
0 = Normal operation (default)
1 = Power down mode. A/Ds are turned off and internal clocks are reduced to minimum.
2−17
2.20.4 Miscellaneous Control Register
Address
Default
03h
01h
7
6
5
4
3
2
1
0
HSYNC, VSYNC/PALI,
AVID, FID/GLCO
output enable
GPCL output
enable
Lock status
(HVLK)
YCbCr output
enable (TVPOE)
Vertical blanking
on/off
Clock output
enable
VBKO
GPCL pin
VBKO (pin 27) function select:
0 = GPCL (default)
1 = VBLK
GPCL (data is output based on state of bit 5):
0 = GPCL outputs 0 (default)
1 = GPCL outputs 1
GPCL output enable:
0 = GPCL is inactive (default)
1 = GPCL is output
NOTE: GPCL must not be programmed to be 0 when register 0Fh bit 1 is 1 (GPCL/VBLK).
Lock status (HVLK) (configured along with register 0Fh, please see Figure 2−8 for the relationship between the
configuration shared pins):
0 = Terminal VSYNC/PALI outputs the PAL indicator (PALI) signal and terminal FID/GLCO outputs the field
ID (FID) signal (default) (if terminals are configured to output PALI and FID in register 0Fh)
1 = Terminal VSYNC/PALI outputs the horizontal lock indicator (HLK) and terminal FID outputs the vertical
lock indicator (VLK) (if terminals are configured to output PALI and FID in register 0Fh)
These are additional functionalities that are provided for ease of use.
YCbCr output enable:
0 = YOUT[7:0] high impedance (default)
1 = YOUT[7:0] active
HSYNC, VSYNC/PALI, active video indicator (AVID), and FID/GLCO output enables:
0 = HSYNC, VSYNC/PALI, AVID, and FID/GLCO are high-impedance (default).
1 = HSYNC, VSYNC/PALI, AVID, and FID/GLCO are active.
Vertical blanking on/off:
0 = Vertical blanking (VBLK) off (default)
1 = Vertical blanking (VBLK) on
Clock output enable:
0 = SCLK output is high impedance.
1 = SCLK output is enabled (default).
NOTE: When enabling the outputs, ensure the clock output is not accidently disabled.
Table 2−11. Digital Output Control
Register 03h, Bit 3
(TVPOE)
Register C2h, Bit 2
(VDPOE)
YCbCr Output
Notes
0
X
1
X
0
1
High impedance After both YCbCr output enable bits are programmed.
High impedance After both YCbCr output enable bits are programmed.
Active
After both YCbCr output enable bits are programmed.
NOTE: VDPOE default is 1 and TVPOE default is 0.
2−18
0F(Bit 2)
VSYNC/PALI
0F(Bit 4)
LOCK24B
VSYNC
0
M
U
X
PALI
0
1
VSYNC/PALI/HLK/HVLK
M
U
X
Pin 24
HLK
0
1
PALI/HLK/HVLK
1
M
U
X
HLK/HVLK
HVLK
HVLK
VLK
1
0
M
U
X
VLK/HVLK
FID
1
0
M
U
X
FID/VLK/HVLK
GLCO
0
1
M
U
X
FID/GLCO/VLK/HVLK
Pin 23
0F(Bit 6)
LOCK23
0F(Bit 3)
FID/GLCO
03(Bit 4)
HVLK
VBLK
GPCL
1
0
M
U
X
VBLK/GPCL
INTREQ
1
0
M
U
X
INTREQ/GPCL//VBLK
Pin 27
SCLK
PCLK
0
1
M
U
X
PCLK/SCLK
Pin 9
03(Bit 7)
VBKO
0F(Bit 1)
INTREQ/GPCL/VBLK
0F(Bit 0)
SCLK/PCLK
Figure 2−8. Configuration Shared Pins
NOTE: Also refer to the configuration shared pins register at subaddress 0Fh.
2−19
2.20.5 Autoswitch Mask Register
Address
Device
Default
04h
TVP5150A
FCh
TVP5150AM1
DCh
7
6
5
4
3
2
1
0
Reserved
SEC_OFF
N443_OFF
PALN_OFF
PALM_OFF
Reserved
N443_OFF:
0 = NTSC443 is unmasked from the autoswitch process. Autoswitch does switch to NTSC443.
1 = NTSC443 is masked from the autoswitch process. Autoswitch does not switch to NTSC443. (default)
PALN_OFF:
0 = PAL-N is unmasked from the autoswitch process. Autoswitch does switch to PAL-N.
1 = PAL-N is masked from the autoswitch process. Autoswitch does not switch to PAL-N. (default)
PALM_OFF:
0 = PAL-M is unmasked from the autoswitch process. Autoswitch does switch to PAL-M.
1 = PAL-M is masked from the autoswitch process. Autoswitch does not switch to PAL-M. (default)
SEC_OFF:
0 = SECAM is unmasked from the autoswitch process. Autoswitch does switch to SECAM. (default for
TVP5150AM1)
1 = SECAM is masked from the autoswitch process. Autoswitch does not switch to SECAM. (default for
TVP5150A)
2.20.6 Color Killer Threshold Control Register
Address
Default
06h
10h
7
6
5
4
3
2
1
0
Reserved
Automatic color killer
Color killer threshold
Automatic color killer:
00 = Automatic mode (default)
01 = Reserved
10 = Color killer enabled, the CbCr terminals are forced to a zero color state.
11 = Color killer disabled
Color killer threshold:
11111 = −30 dB (minimum)
10000 = −24 dB (default)
00000 = −18 dB (maximum)
2−20
2.20.7 Luminance Processing Control #1 Register
Address
Default
07h
60h
7
6
5
4
3
2
1
0
2x luma output
enable
Disable raw
header
Luma bypass enabled
during vertical blanking
Luminance signal delay with respect to
chrominance signal
Pedestal not present
2x luma output enable:
0 = Output depends on bit 4, luminance bypass enabled during vertical blanking (default).
1 = Outputs 2x luma samples during the entire frame. This bit takes precedence over bit 4.
Pedestal not present:
0 = 7.5 IRE pedestal is present on the analog video input signal.
1 = Pedestal is not present on the analog video input signal (default).
Disable raw header:
0 = Insert 656 ancillary headers for raw data
1 = Disable 656 ancillary headers and instead force dummy ones (0x40) (default)
Luminance bypass enabled during vertical blanking:
0 = Disabled. If bit 7, 2x luma output enable, is 0, then normal luminance processing occurs and YCbCr
samples are output during the entire frame (default).
1 = Enabled. If bit 7, 2x luma output enable, is 0, then normal luminance processing occurs and YCbCr
samples are output during VACTIVE and 2x luma samples are output during VBLK. Luminance bypass
occurs for the duration of the vertical blanking as defined by registers 18h and 19h.
Luminance bypass occurs for the duration of the vertical blanking as defined by registers 18h and 19h.
Luma signal delay with respect to chroma signal in pixel clock increments (range −8 to +7 pixel clocks):
1111 = −8 pixel clocks delay
1011 = −4 pixel clocks delay
1000 = −1 pixel clocks delay
0000 = 0 pixel clocks delay (default)
0011 = 3 pixel clocks delay
0111 = 7 pixel clocks delay
2−21
2.20.8 Luminance Processing Control #2 Register
Address
Default
08h
00h
7
6
5
4
3
2
1
0
Reserved
Luminance filter select
Reserved
Peaking gain
Mac AGC control
Luminance filter select:
0 = Luminance comb filter enabled (default)
1 = Luminance chroma trap filter enabled
Peaking gain (sharpness):
00 = 0 (default)
01 = 0.5
10 = 1
11 = 2
Information on peaking frequency: ITU-R BT.601 sampling rate: all standards—peaking center frequency is 2.6 MHz
Mac AGC control:
00 = Auto mode
01 = Auto mode
10 = Force Macrovision AGC pulse detection off
11 = Force Macrovision AGC pulse detection on
2.20.9 Brightness Control Register
Address
Default
09h
80h
7
6
5
4
3
2
1
0
Brightness control
Brightness control:
1111 1111 = 255 (bright)
1000 0000 = 128 (default)
0000 0000 = 0 (dark)
2.20.10 Color Saturation Control Register
Address
Default
0Ah
80h
7
6
5
4
3
2
1
0
Saturation control
Saturation control:
1111 1111 = 255 (maximum)
1000 0000 = 128 (default)
0000 0000 = 0 (no color)
2−22
2.20.11 Hue Control Register
(does not apply to SECAM)
Address
Default
0Bh
00h
7
6
5
4
3
2
1
0
Hue control
Hue control:
0111 1111 = +180 degrees
0000 0000 = 0 degrees (default)
1000 0000 = −180 degrees
2.20.12 Contrast Control Register
Address
Default
0Ch
80h
7
6
5
4
3
2
1
0
Contrast control
Contrast control:
1111 1111 = 255 (maximum contrast)
1000 0000 = 128 (default)
0000 0000 = 0 (minimum contrast)
2.20.13 Outputs and Data Rates Select Register
Address
Default
0Dh
47h
7
6
5
4
3
2
1
0
YCbCr output code
range
Reserved
CbCr code format
YCbCr data path bypass
YCbCr output format
YCbCr output code range:
0 = ITU-R BT.601 coding range (Y ranges from 16 to 235. U and V range from 16 to 240)
1 = Extended coding range (Y, U, and V range from 1 to 254) (default)
CbCr code format:
0 = Offset binary code (2s complement + 128) (default)
1 = Straight binary code (2s complement)
YCbCr data path bypass:
00 = Normal operation (default)
01 = Decimation filter output connects directly to the YCbCr output pins. This data is similar to the digitized
composite data, but the HBLANK area is replaced with ITU-R BT.656 digital blanking.
10 = Digitized composite (or digitized S-video luma). A/D output connects directly to the YCbCr output pins.
11 = Reserved
2−23
YCbCr output format:
000 = 8-bit 4:2:2 YCbCr with discrete sync output
001 = Reserved
010 = Reserved
011 = Reserved
100 = Reserved
101 = Reserved
110 = Reserved
111 = 8-bit ITU-R BT.656 interface with embedded sync output (default)
2.20.14 Luminance Processing Control #3 Register
Address
Default
0Eh
00h
7
6
5
4
3
2
1
0
Reserved
Luminance trap filter select
Luminance filter stop band bandwidth (MHz):
00 = No notch (default)
01 = Notch 1
10 = Notch 2
11 = Notch 3
Luminance filter select [1:0] selects one of the four chroma trap (notch) filters to produce luminance signal by
removing the chrominance signal from the composite video signal. The stopband of the chroma trap filter is centered
at the chroma subcarrier frequency with stopband bandwidth controlled by the two control bits. Please refer to the
following table for the stopband bandwidths. The WCF bit is controlled in the chrominance control #2 register, see
Section 2.20.25.
WCF
FILTER SELECT
NTSC/PAL/SECAM ITU-R BT.601
00
01
10
11
00
01
10
11
1.2214
0.8782
0.7297
0.4986
1.4170
1.0303
0.8438
0.5537
0
1
2−24
2.20.15 Configuration Shared Pins Register
Address
Default
0Fh
08h
7
6
5
4
3
2
1
0
Reserved
LOCK23
Reserved
LOCK24B
FID/GLCO
VSYNC/PALI
INTREQ/GPCL/VBLK
SCLK/PCLK
LOCK23 (pin 23) function select:
0 = FID (default, if bit 3 is selected to output FID)
1 = Lock indicator (indicates whether the device is locked vertically)
LOCK24B (pin 24) function select:
0 = PALI (default, if bit 2 is selected to output PALI)
1 = Lock indicator (indicates whether the device is locked horizontally)
FID/GLCO (pin 23) function select (also refer to register 03h for enhanced functionality):
0 = FID
1 = GLCO (default)
VSYNC/PALI (pin 24) function select (also refer to register 03h for enhanced functionality):
0 = VSYNC (default)
1 = PALI
INTREQ/GPCL/VBLK (pin 27) function select:
0 = INTREQ (default)
1 = GPCL or VBLK depending on bit 7 of register 03h
SCLK/PCLK (pin 9) function select:
0 = SCLK (default)
1 = PCLK (1x pixel clock frequency)
Please see Figure 2−8 for the relationship between the configuration shared pins.
2.20.16 Active Video Cropping Start Pixel MSB Register
Address
Default
11h
00h
7
6
5
4
3
2
1
0
AVID start pixel MSB [7:0]
Active video cropping start pixel MSB [9:2], set this register first before setting register 12h. The TVP5150A decoder
updates the AVID start values only when register 12h is written to. This start pixel value is relative to the default values
of the AVID start pixel.
2−25
2.20.17 Active Video Cropping Start Pixel LSB Register
Address
Default
12h
00h
7
6
5
4
3
2
1
0
Reserved
AVID active
AVID start pixel LSB [1:0]
AVID active:
0 = AVID out active in VBLK (default)
1 = AVID out inactive in VBLK
Active video cropping start pixel LSB [1:0]: The TVP5150A decoder updates the AVID start values only when this
register is written to.
AVID start [9:0] (combined registers 11h and 12h):
01 1111 1111 = 511
00 0000 0001 = 1
00 0000 0000 = 0 (default)
11 1111 1111 = −1
10 0000 0000 = −512
2.20.18 Active Video Cropping Stop Pixel MSB Register
Address
Default
13h
00h
7
6
5
4
3
2
1
0
AVID stop pixel MSB
Active video cropping stop pixel MSB [9:2], set this register first before setting the register 14h. The TVP5150A
decoder updates the AVID stop values only when register 14h is written to. This stop pixel value is relative to the
default values of the AVID stop pixel.
2.20.19 Active Video Cropping Stop Pixel LSB Register
Address
Default
14h
00h
7
6
5
4
3
2
1
0
Reserved
AVID stop pixel LSB
Active video cropping stop pixel LSB [1:0]: The number of pixels of active video must be an even number. The
TVP5150A decoder updates the AVID stop values only when this register is written to.
AVID stop [9:0] (combined registers 13h and 14h):
01 1111 1111 = 511
00 0000 0001 = 1
00 0000 0000 = 0 (default) (see Figure 2−3 and Figure 2−4)
11 1111 1111 = −1
10 0000 0000 = −512
2−26
2.20.20 Genlock and RTC Register
Address
Default
15h
01h
7
6
5
4
3
2
1
0
Reserved
F/V bit control
Reserved
GLCO/RTC
F/V bit control
BIT 5
BIT 4
NUMBER OF LINES
Standard
F BIT
V BIT
ITU-R BT.656 ITU-R BT.656
Nonstandard even
Nonstandard odd
Standard
Force to 1
Toggles
Switch at field boundary
Switch at field boundary
0
0
0
ITU-R BT.656 ITU-R BT.656
1
Nonstandard
Standard
Toggles
Switch at field boundary
ITU-R BT.656 ITU-R BT.656
1
1
0
1
Nonstandard
Illegal
Pulse mode
Switch at field boundary
GLCO/RTC. The following table helps in understanding the different modes.
BIT 2
BIT 1
BIT 0
GENLOCK/RTC MODE
GLCO
0
0
1
1
X
X
X
X
0
1
0
1
RTC output mode 0 (default)
GLCO
RTC output mode 1
All other values are reserved.
Figure 2−6 shows the timing of GLCO and Figure 2−7 shows the timing of RTC.
2−27
2.20.21 Horizontal Sync (HSYNC) Start Register
Address
Default
16h
80h
7
6
5
4
3
2
1
0
HSYNC start
HSYNC start:
1111 1111 = −127 x 4 pixel clocks
1111 1110 = −126 x 4 pixel clocks
1000 0001 = −1 x 4 pixel clocks
1000 0000 = 0 pixel clocks (default)
0111 1111 = 1 x 4 pixel clocks
0111 1110 = 2 x 4 pixel clocks
0000 0000 = 128 x 4 pixel clocks
BT.656 EAV Code
BT.656 SAV Code
U
Y
V
Y
F
F
0
0
0
0
X
Y
8
0
1
0
8
0
1
0
F
F
0
0
0
0
X
Y
U
Y
YOUT
[7:0]
HSYNC
AVID
128 SCLK
Start of
Digital Line
Start of Digital
Active Line
N
hbhs
N
hb
Figure 2−9. Horizontal Sync
Table 2−12. Clock Delays (SCLKs)
STANDARD
NTSC
N
N
hb
hbhs
16
272
284
280
PAL
20
40
SECAM
Detailed timing information is also available in Section 2.12, Synchronization Signals.
2−28
2.20.22 Vertical Blanking Start Register
Address
Default
18h
00h
7
6
5
4
3
2
1
0
Vertical blanking start
Vertical blanking (VBLK) start:
0111 1111 = 127 lines after start of vertical blanking interval
0000 0001 = 1 line after start of vertical blanking interval
0000 0000 = Same time as start of vertical blanking interval (default) (see Figure 2−2)
1111 1111 = 1 line before start of vertical blanking interval
1000 0000 = 128 lines before start of vertical blanking interval
Vertical blanking is adjustable with respect to the standard vertical blanking intervals. The setting in this register
determines the timing of the GPCL/VBLK signal when it is configured to output vertical blank (see register 03h). The
setting in this register also determines the duration of the luma bypass function (see register 07h).
2.20.23 Vertical Blanking Stop Register
Address
Default
19h
00h
7
6
5
4
3
2
1
0
Vertical blanking stop
Vertical blanking (VBLK) stop:
0111 1111 = 127 lines after stop of vertical blanking interval
0000 0001 = 1 line after stop of vertical blanking interval
0000 0000 = Same time as stop of vertical blanking interval (default) (see Figure 2−2)
1111 1111 = 1 line before stop of vertical blanking interval
1000 0000 = 128 lines before stop of vertical blanking interval
Vertical blanking is adjustable with respect to the standard vertical blanking intervals. The setting in this register
determines the timing of the GPCL/VBLK signal when it is configured to output vertical blank (see register 03h). The
setting in this register also determines the duration of the luma bypass function (see register 07h).
2−29
2.20.24 Chrominance Control #1 Register
Address
Default
1Ah
0Ch
7
6
5
4
3
2
1
0
Chrominance adaptive
comb filter enable (ACE)
Chrominance comb filter
enable (CE)
Reserved
Color PLL reset
Automatic color gain control
Color PLL reset:
0 = Color PLL not reset (default)
1 = Color PLL reset
Color PLL phase is reset to zero and the color PLL reset bit then immediately returns to zero. When this bit is set,
the subcarrier PLL phase reset bit is transmitted on terminal 23 (GLCO) on the next line (NTSC or PAL).
Chrominance adaptive comb filter enable (ACE):
0 = Disable
1 = Enable (default)
Chrominance comb filter enable (CE):
0 = Disable
1 = Enable (default)
Automatic color gain control (ACGC):
00 = ACGC enabled (default)
01 = Reserved
10 = ACGC disabled
11 = ACGC frozen to the previously set value
2−30
2.20.25 Chrominance Control #2 Register
Address
Default
1Bh
14h
7
6
5
4
3
2
1
0
Reserved
Reserved
WCF
Chrominance filter select
Wideband chroma filter (WCF):
0 = Disable
1 = Enable (default)
Chrominance filter select:
00 = No notch (default)
01 = Notch 1
10 = Notch 2
11 = Notch 3
Chrominance output bandwidth (MHz):
WCF
FILTER SELECT
NTSC/PAL/SECAM ITU-R BT.601
00
01
10
11
00
01
10
11
1.2214
0.8782
0.7297
0.4986
1.4170
1.0303
0.8438
0.5537
0
1
2−31
2.20.26 Interrupt Reset Register B
Address
Default
1Ch
00h
7
6
5
4
3
2
1
0
Software
initialization
reset
Macrovision
detect changed
reset
Field rate
changed reset
Line alternation
changed reset
Color lock
H/V lock
TV/VCR
Reserved
changed reset changed reset changed reset
Interrupt reset register B is used by the external processor to reset the interrupt status bits in interrupt status
register B. Bits loaded with a 1 allow the corresponding interrupt status bit to reset to 0. Bits loaded with a 0 have no
effect on the interrupt status bits.
Software initialization reset:
0 = No effect (default)
1 = Reset software initialization bit
Macrovision detect changed reset:
0 = No effect (default)
1 = Reset Macrovision detect changed bit
Field rate changed reset:
0 = No effect (default)
1 = Reset field rate changed bit
Line alternation changed reset:
0 = No effect (default)
1 = Reset line alternation changed bit
Color lock changed reset:
0 = No effect (default)
1 = Reset color lock changed bit
H/V lock changed reset:
0 = No effect (default)
1 = Reset H/V lock changed bit
TV/VCR changed reset [TV/VCR mode is determined by counting the total number of lines/frame. The mode switches
to VCR for nonstandard number of lines]:
0 = No effect (default)
1 = Reset TV/VCR changed bit
2−32
2.20.27 Interrupt Enable Register B
Address
Default
1Dh
00h
7
6
5
4
3
2
1
0
Software initialization
occurred enable
Macrovision
detect changed
Field rate
changed
Line alternation
changed
Color lock
changed
H/V lock
changed
TV/VCR
changed
Reserved
Interrupt enable register B is used by the external processor to mask unnecessary interrupt sources for interrupt B.
Bits loaded with a 1 allow the corresponding interrupt condition to generate an interrupt on the external pin.
Conversely, bits loaded with 0s mask the corresponding interrupt condition from generating an interrupt on the
external pin. This register only affects the external pin, it does not affect the bits in the interrupt status register. A given
condition can set the appropriate bit in the status register and not cause an interrupt on the external pin. To determine
if this device is driving the interrupt pin either AND interrupt status register B with interrupt enable register B or check
the state of interrupt B in the interrupt B active register.
Software initialization occurred enable:
0 = Disabled (default)
1 = Enabled
Macrovision detect changed:
0 = Disabled (default)
1 = Enabled
Field rate changed:
0 = Disabled (default)
1 = Enabled
Line alternation changed:
0 = Disabled (default)
1 = Enabled
Color lock changed:
0 = Disabled (default)
1 = Enabled
H/V lock changed:
0 = Disabled (default)
1 = Enabled
TV/VCR changed:
0 = Disabled (default)
1 = Enabled
2−33
2.20.28 Interrupt Configuration Register B
Address
Default
1Eh
00h
7
6
5
4
3
2
1
0
Reserved
Interrupt polarity B
Interrupt polarity B:
0 = Interrupt B is active low (default).
1 = Interrupt B is active high.
Interrupt polarity B must be same as interrupt polarity A bit at bit 0 of the interrupt configuration register A at address
C2h.
Interrupt configuration register B is used to configure the polarity of interrupt B on the external interrupt pin. When
the interrupt B is configured for active low, the pin is driven low when active and high-impedance when inactive
(open-drain). Conversely, when the interrupt B is configured for active high, it is driven high for active and driven low
for inactive.
2.20.29 Video Standard Register
Address
Default
28h
00h
7
6
5
4
3
2
1
0
Reserved
Video standard
Video standard:
0000 = Autoswitch mode (default)
0001 = Reserved
0010 = (M) NTSC ITU-R BT.601
0011 = Reserved
0100 = (B, G, H, I, N) PAL ITU-R BT.601
0101 = Reserved
0110 = (M) PAL ITU-R BT.601
0111 = Reserved
1000 = (Combination-N) PAL ITU-R BT.601
1001 = Reserved
1010 = NTSC 4.43 ITU-R BT.601
1011 = Reserved
1100 = SECAM ITU-R BT.601
With the autoswitch code running, the user can force the device to operate in a particular video standard mode and
sample rate by writing the appropriate value into this register.
2.20.30 Cb Gain Factor Register
Address
2Ch
7
6
5
4
3
2
1
0
Cb gain factor
This is a read-only register that provides the gain applied to the Cb in the YCbCr data stream.
2−34
2.20.31 Cr Gain Factor Register
Address
2Dh
7
6
5
4
3
2
1
0
Cr gain factor
This is a read-only register that provides the gain applied to the Cr in the YCbCr data stream.
2.20.32 Macrovision On Counter Register
Address
Default
2Eh
0Fh
7
6
5
4
3
2
1
0
Macrovision on counter
This register allows the user to determine how many consecutive frames in which the Macrovision AGC pulses have
to be detected before the decoder decides that the Macrovision AGC pulses are present.
2.20.33 Macrovision Off Counter Register
Address
Default
2Fh
01h
7
6
5
4
3
2
1
0
Macrovision off counter
This register allows the user to determine how many consecutive frames in which the Macrovision AGC pulses are
not detected before the decoder decides that the Macrovision AGC pulses are not present.
2.20.34 656 Revision Select Register
NOTE: This register exists only for the TVP5150AM1.
Address
Default
30h
00h
7
6
5
4
3
2
1
0
656 revision
select
Reserved
656 revision select:
0 = Adheres to ITU-R BT.656.4 timing (default for TVP5150AM1, this is the only option for TVP5150A).
1 = Adheres to ITU-R BT.656.3 timing.
2.20.35 MSB of Device ID Register
Address
Default
80h
51h
7
6
5
4
3
2
1
0
MSB of device ID
This register identifies the MSB of the device ID. Value = 0x51.
2−35
2.20.36 LSB of Device ID Register
Address
Default
81h
50h
7
6
5
4
3
2
1
0
LSB of device ID
This register identifies the LSB of the device ID. Value = 0x50.
2.20.37 ROM Major Version Register
Address
Device
Default
82h
TVP5150A
03h
TVP5150AM1
04h
7
6
5
4
3
†
2
1
0
ROM major version
†
This register can contain a number from 0x01 to 0xFF.
Value = 0x03 for TVP5150A
Value = 0x04 for TVP5150AM1
2.20.38 ROM Minor Version Register
Address
Device
Default
83h
TVP5150A
21h
TVP5150AM1
00h
7
6
5
4
3
2
1
0
†
ROM minor version
†
This register can contain a number from 0x01 to 0xFF.
Value = 0x21 for TVP5150A
Value = 0x00 for TVP5150AM1
2.20.39 Vertical Line Count MSB Register
Address
84h
7
6
5
4
3
2
1
0
Reserved
Vertical line count MSB
Vertical line count bits [9:8]
2.20.40 Vertical Line Count LSB Register
Address
85h
7
6
5
4
3
2
1
0
Vertical line count LSB
Vertical line count bits [7:0]
Registers 84h and 85h can be read and combined to extract the detected number of lines per frame. This can be used
with nonstandard video signals such as a VCR in fast-forward or rewind modes to synchronize the downstream video
circuitry.
2−36
2.20.41 Interrupt Status Register B
Address
86h
7
6
5
4
3
2
1
0
Software
initialization
Macrovision detect
changed
Command
ready
Field rate
changed
Line alternation
changed
Color lock
changed
H/V lock
changed
TV/VCR
changed
Software initialization:
0 = Software initialization is not ready (default).
1 = Software initialization is ready.
Macrovision detect changed:
0 = Macrovision detect status has not changed (default).
1 = Macrovision detect status has changed.
Command ready:
0 = TVP5150A is not ready to accept a new command (default).
1 = TVP5150A is ready to accept a new command.
Field rate changed:
0 = Field rate has not changed (default).
1 = Field rate has changed.
Line alternation changed:
0 = Line alteration has not changed (default).
1 = Line alternation has changed.
Color lock changed:
0 = Color lock status has not changed (default).
1 = Color lock status has changed.
H/V lock changed:
0 = H/V lock status has not changed (default).
1 = H/V lock status has changed.
TV/VCR changed:
0 = TV/VCR status has not changed (default).
1 = TV/VCR status has changed.
Interrupt status register B is polled by the external processor to determine the interrupt source for interrupt B. After
an interrupt condition is set, it can be reset by writing to the interrupt reset register B at subaddress 1Ch with a 1 in
the appropriate bit.
2.20.42 Interrupt Active Register B
Address
87h
7
6
5
4
3
2
1
0
Reserved
Interrupt B
Interrupt B:
0 = Interrupt B is not active on the external terminal (default).
1 = Interrupt B is active on the external terminal.
The interrupt active register B is polled by the external processor to determine if interrupt B is active.
2−37
2.20.43 Status Register #1
Address
88h
7
6
5
4
3
2
1
0
Peak white
detect status
Line-alternating
status
Field rate
status
Lost lock
detect
Color subcarrier
lock status
Vertical sync
lock status
Horizontal sync
lock status
TV/VCR status
Peak white detect status:
0 = Peak white is not detected.
1 = Peak white is detected.
Line-alternating status:
0 = Nonline alternating
1 = Line alternating
Field rate status:
0 = 60 Hz
1 = 50 Hz
Lost lock detect:
0 = No lost lock since status register #1 was last read.
1 = Lost lock since status register #1 was last read.
Color subcarrier lock status:
0 = Color subcarrier is not locked.
1 = Color subcarrier is locked.
Vertical sync lock status:
0 = Vertical sync is not locked.
1 = Vertical sync is locked.
Horizontal sync lock status:
0 = Horizontal sync is not locked.
1 = Horizontal sync is locked.
TV/VCR status. TV mode is determined by detecting standard line-to-line variations and specific chroma SCH phases
based on the standard input video format. VCR mode is determined by detecting variations in the chroma SCH phases
compared to the chroma SCH phases of the standard input video format.
0 = TV
1 = VCR
2−38
2.20.44 Status Register #2
Address
89h
7
6
5
4
3
2
1
0
Weak signal
detection
PAL switch
polarity
Field sequence
status
AGC and offset frozen
status
Reserved
Macrovision detection
Weak signal detection:
0 = No weak signal
1 = Weak signal mode
PAL switch polarity of first line of odd field:
0 = PAL switch is 0
1 = PAL switch is 1
Field sequence status:
0 = Even field
1 = Odd field
AGC and offset frozen status:
0 = AGC and offset are not frozen.
1 = AGC and offset are frozen.
Macrovision detection:
000 = No copy protection
001 = AGC process present (Macrovision Type 1 present)
010 = Colorstripe process Type 2 present
011 = AGC process and colorstripe process Type 2 present
100 = Reserved
101 = Reserved
110 = Colorstripe process Type 3 present
111 = AGC process and color stripe process Type 3 present
2.20.45 Status Register #3
Address
8Ah
7
6
5
4
3
2
1
0
†
Front-end AGC gain value (analog and digital)
†
Represents 8 bits (MSB) of a 10-bit value
This register provides the front-end AGC gain value of both analog and digital gains.
2−39
2.20.46 Status Register #4
Address
8Bh
7
6
5
4
3
2
1
0
Subcarrier to horizontal (SCH) phase
SCH (color PLL subcarrier phase at 50% of the falling edge of horizontal sync of line one of odd field; step size
360_/256):
0000 0000 = 0.00_
0000 0001 = 1.41_
0000 0010 = 2.81_
1111 1110 = 357.2_
1111 1111 = 358.6_
2.20.47 Status Register #5
Address
8Ch
7
6
5
4
3
2
1
0
Autoswitch mode
Reserved
Video standard
Sampling rate
This register contains information about the detected video standard and the sampling rate at which the device is
currently operating. When autoswitch code is running, this register must be tested to determine which video standard
has been detected.
Autoswitch mode:
0 = Stand-alone (forced video standard) mode
1 = Autoswitch mode
Video standard:
VIDEO STANDARD [3:1]
SR
VIDEO STANDARD
Reserved
BIT 3
BIT2
0
BIT1
BIT 0
0
0
0
0
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
(M) NTSC ITU-R BT.601
Reserved
0
0
(B, G, H, I, N) PAL ITU-R BT.601
Reserved
1
1
(M) PAL ITU-R BT.601
Reserved
1
1
PAL-N ITU-R BT.601
Reserved
0
0
NTSC 4.43 ITU-R BT.601
Reserved
0
0
SECAM ITU-R BT.601
Sampling rate (SR):
0 = Reserved
1 = ITU-R BT.601
2−40
2.20.48 Closed Caption Data Registers
Address
90h−93h
Address
7
6
5
4
3
2
1
0
90h
91h
92h
93h
Closed caption field 1 byte 1
Closed caption field 1 byte 2
Closed caption field 2 byte 1
Closed caption field 2 byte 2
These registers contain the closed caption data arranged in bytes per field.
2.20.49 WSS Data Registers
Address
94h−99h
NTSC
ADDRESS
94h
7
6
5
4
3
2
1
0
BYTE
b5
b4
b3
b2
b1
b0
WSS field 1 byte 1
WSS field 1 byte 2
WSS field 1 byte 3
WSS field 2 byte 1
WSS field 2 byte 2
WSS field 2 byte 3
95h
b13
b12
b11
b19
b5
b10
b18
b4
b9
b8
b7
b6
96h
b17
b3
b16
b2
b15
b1
b14
b0
97h
98h
b13
b12
b11
b19
b10
b18
b9
b8
b7
b6
99h
b17
b16
b15
b14
These registers contain the wide screen signaling (WSS) data for NTSC.
Bits 0−1 represent word 0, aspect ratio
Bits 2−5 represent word 1, header code for word 2
Bits 6−13 represent word 2, copy control
Bits 14−19 represent word 3, CRC
PAL/SECAM
ADDRESS
94h
7
6
5
4
3
2
1
0
BYTE
b7
b6
b5
b4
b3
b2
b1
b9
b0
b8
WSS field 1 byte 1
WSS field 1 byte 2
95h
b13
b12
b11
b10
96h
Reserved
97h
b7
b6
b5
b4
b3
b2
b1
b9
b0
b8
WSS field 2 byte 1
WSS field 2 byte 2
98h
b13
b12
b11
b10
99h
Reserved
PAL/SECAM:
Bits 0−3 represent group 1, aspect ratio
Bits 4−7 represent group 2, enhanced services
Bits 8−10 represent group 3, subtitles
Bits 11−13 represent group 4, others
2−41
2.20.50 VPS Data Registers
Address
9Ah–A6h
ADDRESS
9Ah
7
6
5
4
3
2
1
0
VPS byte 1
VPS byte 2
VPS byte 3
VPS byte 4
VPS byte 5
VPS byte 6
VPS byte 7
VPS byte 8
VPS byte 9
VPS byte 10
VPS byte 11
VPS byte 12
VPS byte 13
9Bh
9Ch
9Dh
9Eh
9Fh
A0h
A1h
A2h
A3h
A4h
A5h
A6h
These registers contain the entire VPS data line except the clock run-in code or the start code.
2.20.51 VITC Data Registers
Address
A7h–AFh
ADDRESS
A7h
7
6
5
4
3
2
1
0
VITC byte 1, frame byte 1
VITC byte 2, frame byte 2
VITC byte 3, seconds byte 1
VITC byte 4, seconds byte 2
VITC byte 5, minutes byte 1
VITC byte 6, minutes byte 2
VITC byte 7, hour byte 1
VITC byte 8, hour byte 2
VITC byte 9, CRC
A8h
A9h
AAh
ABh
ACh
ADh
AEh
AFh
These registers contain the VITC data.
2.20.52 VBI FIFO Read Data Register
Address
B0h
7
6
5
4
3
2
1
0
FIFO read data
This address is provided to access VBI data in the FIFO through the host port. All forms of teletext data come directly
from the FIFO, while all other forms of VBI data can be programmed to come from the registers or from the FIFO.
Current status of the FIFO can be found at address C6h and the number of bytes in the FIFO is located at address
C7h. If the host port is to be used to read data from the FIFO, then the output formatter must be disabled at address
CDh bit 0. The format used for the VBI FIFO is shown in Section 2.9.
2−42
2.20.53 Teletext Filter and Mask Registers
Address
Default
B1h–BAh
00h
ADDRESS
B1h
7
6
5
4
3
2
1
0
Filter 1 mask 1
Filter 1 pattern 1
Filter 1 pattern 2
Filter 1 pattern 3
Filter 1 pattern 4
Filter 1 pattern 5
Filter 2 pattern 1
Filter 2 pattern 2
Filter 2 pattern 3
Filter 2 pattern 4
Filter 2 pattern 5
B2h
Filter 1 mask 2
Filter 1 mask 3
Filter 1 mask 4
Filter 1 mask 5
Filter 2 mask 1
Filter 2 mask 2
Filter 2 mask 3
Filter 2 mask 4
Filter 2 mask 5
B3h
B4h
B5h
B6h
B7h
B8h
B9h
BAh
For an NABTS system, the packet prefix consists of five bytes. Each byte contains four data bits (D[3:0]) interlaced
with four Hamming protection bits (H[3:0]):
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
D[3]
H[3]
D[2]
H[2]
D[1]
H[1]
D[0]
H[0]
Only the data portion D[3:0] from each byte is applied to a teletext filter function with the corresponding pattern bits
P[3:0] and mask bits M[3:0]. Hamming protection bits are ignored by the filter.
For a WST system (PAL or NTSC), the packet prefix consists of two bytes so that two patterns are used. Patterns
3, 4, and 5 are ignored.
The mask bits enable filtering using the corresponding bit in the pattern register. For example, a 1 in the LSB of mask 1
means that the filter module must compare the LSB of nibble 1 in the pattern register to the first data bit on the
transaction. If these match, then a true result is returned. A 0 in a bit of mask 1 means that the filter module must ignore
that data bit of the transaction. If all 0s are programmed in the mask bits, then the filter matches all patterns returning
a true result (default 00h).
Pattern and mask for each byte and filter are referred as <1,2><P,M><1,2,3,4,5> where:
<1,2> identifies the filter 1 or 2
<P,M> identifies the pattern or mask
<1,2,3,4,5> identifies the byte number
2−43
2.20.54 Teletext Filter Control Register
Address
Default
BBh
00h
7
6
5
4
3
2
1
0
Reserved
Filter logic
Mode
TTX filter 2 enable
TTX filter 1 enable
Filter logic: allows different logic to be applied when combining the decision of filter 1 and filter 2 as follows:
00 = NOR (Default)
01 = NAND
10 = OR
11 = AND
Mode:
0 = Teletext WST PAL mode B (2 header bytes) (default)
1 = Teletext NABTS NTSC mode C (5 header bytes)
TTX filter 2 enable:
0 = Disabled (default)
1 = Enabled
TTX filter 1 enable:
0 = Disabled (default)
1 = Enabled
If the filter matches or if the filter mask is all 0s, then a true result is returned.
2−44
2.20.55 Interrupt Status Register A
Address
Default
C0h
00h
7
6
5
4
3
2
1
0
Lock state interrupt Lock interrupt
Reserved
FIFO threshold interrupt
Line interrupt
Data interrupt
The interrupt status register A can be polled by the host processor to determine the source of an interrupt. After an
interrupt condition is set it can be reset by writing to this register with a 1 in the appropriate bit(s).
Lock state interrupt:
0 = TVP5150A is not locked to the video signal (default).
1 = TVP5150A is locked to the video signal.
Lock interrupt:
0 = A transition has not occurred on the lock signal (default).
1 = A transition has occurred on the lock signal.
FIFO threshold interrupt:
0 = The amount of data in the FIFO has not yet crossed the threshold programmed at address C8h (default).
1 = The amount of data in the FIFO has crossed the threshold programmed at address C8h.
Line interrupt:
0 = The video line number has not yet been reached (default).
1 = The video line number programmed in address CAh has occurred.
Data interrupt:
0 = No data is available (default).
1 = VBI data is available either in the FIFO or in the VBI data registers.
2−45
2.20.56 Interrupt Enable Register A
Address
Default
C1h
00h
7
6
5
4
3
2
1
0
Lock interrupt
enable
Cycle complete
interrupt enable
Bus error
interrupt enable
FIFO threshold
interrupt enable
Line interrupt
enable
Data interrupt
enable
Reserved
Reserved
The interrupt enable register A is used by the host processor to mask unnecessary interrupt sources. Bits loaded with
a 1 allow the corresponding interrupt condition to generate an interrupt on the external pin. Conversely, bits loaded
with a 0 mask the corresponding interrupt condition from generating an interrupt on the external pin. This register only
affects the interrupt on the external terminal, it does not affect the bits in interrupt status register A. A given condition
can set the appropriate bit in the status register and not cause an interrupt on the external terminal. To determine if
this device is driving the interrupt terminal either perform a logical AND of interrupt status register A with interrupt
enable register A, or check the state of the interrupt A bit in the interrupt configuration register at address C2h.
Lock interrupt enable:
0 = Disabled (default)
1 = Enabled
Cycle complete interrupt enable:
0 = Disabled (default)
1 = Enabled
Bus error interrupt enable:
0 = Disabled (default)
1 = Enabled
FIFO threshold interrupt enable:
0 = Disabled (default)
1 = Enabled
Line interrupt enable:
0 = Disabled (default)
1 = Enabled
Data interrupt enable:
0 = Disabled (default)
1 = Enabled
2−46
2.20.57 Interrupt Configuration Register A
Address
Default
C2h
04h
7
6
5
4
3
2
1
0
YCbCr enable
(VDPOE)
Reserved
Interrupt A
Interrupt polarity A
YCbCr enable (VDPOE):
0 = YCbCr pins are high impedance.
1 = YCbCr pins are active if other conditions are met (default).
Interrupt A (read-only):
0 = Interrupt A is not active on the external pin (default).
1 = Interrupt A is active on the external pin.
Interrupt polarity A:
0 = Interrupt A is active low (default).
1 = Interrupt A is active high.
Interrupt configuration register A is used to configure the polarity of the external interrupt terminal. When interrupt
A is configured as active low, the terminal is driven low when active and high-impedance when inactive (open
collector). Conversely, when the terminal is configured as active high, it is driven high when active and driven low
when inactive.
2.20.58 VDP Configuration RAM Register
Address
Default
C3h
DCh
C4h
0Fh
C5h
00h
Address
7
6
5
4
3
2
1
0
C3h
C4h
Configuration data
RAM address (7:0)
RAM
address 8
C5h
Reserved
The configuration RAM data is provided to initialize the VDP with initial constants. The configuration RAM is 512 bytes
organized as 32 different configurations of 16 bytes each. The first 12 configurations are defined for the current VBI
standards. An additional 2 configurations can be used as a custom programmed mode for unique standards like
Gemstar.
Address C3h is used to read or write to the RAM. The RAM internal address counter is automatically incremented
with each transaction. Addresses C5h and C4h make up a 9-bit address to load the internal address counter with a
specific start address. This can be used to write a subset of the RAM for only those standards of interest. Registers
D0h−FBh must all be programmed with FFh, before writing or reading the configuration RAM. Full field mode (CFh)
must be disabled as well.
The suggested RAM contents are shown below. All values are hexadecimal.
2−47
Table 2−13. VBI Configuration RAM For Signals With Pedestal
Index
Reserved
Address
000
010
020
030
040
050
060
070
080
090
0A0
0B0
0C0
0D0
0E0
0F0
100
110
0
1
2
3
4
E7
27
E7
27
E7
A7
04
04
0
5
6
7
8
9
A
B
0
0
0
0
0
0
0
0
0
0
0
0
0
C
0
0
0
0
0
0
0
0
0
0
0
0
0
D
0
0
0
0
0
0
0
0
0
0
0
0
0
E
F
0
0
0
0
0
0
0
0
0
0
0
0
0
Reserved
26 e6
Reserved
2B A6
Reserved
22 A6
Reserved
23 69
Reserved
22 69
Reserved
23 69
Reserved
02 A6
Reserved
02 69
Reserved
42 A6
Reserved
43 69
Reserved
49 A6
Reserved
49 69
Reserved
0D A6
WST SECAM 6
Reserved
AA
AA
AA
AA
AA
AA
AA
AA
5B
38
0
AA
AA
AA
AA
AA
AA
2A
2A
55
00
0
FF
FF
FF
FF
FF
FF
FF
FF
C5
3F
0
FF
FF
FF
FF
FF
FF
3F
3F
FF
00
0
2E
2E
2E
2E
2E
2E
51
51
71
71
8F
8F
CE
20
20
20
20
20
20
6E
6E
6E
6E
6D
6D
2B
b4
72
98
93
93
93
7B
8C
CD
7C
85
94
DA
0e
10
0D
0D
0D
0D
09
09
0F
08
08
08
0B
10
10
10
10
15
10
27
27
3A
39
4C
4C
60
WST PAL B 6
Reserved
WST PAL C 6
Reserved
WST NTSC 6
Reserved
NABTS, NTSC 6
Reserved
NABTS, NTSC-J 6
Reserved
CC, PAL/SECAM 6
Reserved
CC, NTSC 6
Reserved
WSS, PAL/SECAM 6
Reserved
120
130
140
150
160
170
180
190
1A0
1B0
1C0
1D0
WSS, NTSC C
Reserved
0
VITC, PAL/SECAM 6
Reserved
0
VITC, NTSC 6
Reserved
0
0
0
0
0
VPS, PAL 6
Reserved
AA
AA
FF
FF
BA
Reserved
Programmable
Reserved
Custom 1
Reserved
Custom 2
Programmable
2−48
2.20.59 VDP Status Register
Address
C6h
7
6
5
4
3
2
1
0
FIFO full error FIFO empty TTX available CC field 1 available CC field 2 available WSS available VPS available VITC available
The VDP status register indicates whether data is available in either the FIFO or data registers, and status information
about the FIFO. Reading data from the corresponding register does not clear the status flags automatically. These
flags are only reset by writing a 1 to the respective bit. However, bit 6 is updated automatically.
FIFO full error:
0 = No FIFO full error
1 = FIFO was full during a write to FIFO.
The FIFO full error flag is set when the current line of VBI data can not enter the FIFO. For example, if the FIFO has
only 10 bytes left and teletext is the current VBI line, the FIFO full error flag is set, but no data is written because the
entire teletext line will not fit. However, if the next VBI line is closed caption requiring only 2 bytes of data plus the
header, this goes into the FIFO. Even if the full error flag is set.
FIFO empty:
0 = FIFO is not empty.
1 = FIFO is empty.
TTX available:
0 = Teletext data is not available.
1 = Teletext data is available.
CC field 1 available:
0 = Closed caption data from field 1 is not available.
1 = Closed caption data from field 1 is available.
CC field 2 available:
0 = Closed caption data from field 2 is not available.
1 = Closed caption data from field 2 is available.
WSS available:
0 = WSS data is not available.
1 = WSS data is available.
VPS available:
0 = VPS data is not available.
1 = VPS data is available.
VITC available:
0 = VITC data is not available.
1 = VITC data is available.
2.20.60 FIFO Word Count Register
Address
C7h
7
6
5
4
3
2
1
0
Number of words
This register provides the number of words in the FIFO. 1 word equals 2 bytes.
2−49
2.20.61 FIFO Interrupt Threshold Register
Address
Default
C8h
80h
7
6
5
4
3
2
1
0
Number of words
This register is programmed to trigger an interrupt when the number of words in the FIFO exceeds this value (default
80h). This interrupt must be enabled at address C1h. 1 word equals 2 bytes.
2.20.62 FIFO Reset Register
Address
Default
C9h
00h
7
6
5
4
3
2
1
0
Any data
Writing any data to this register resets the FIFO and clears any data present.
2.20.63 Line Number Interrupt Register
Address
Default
CAh
00h
7
6
5
4
3
2
1
0
Field 1 enable
Field 2 enable
Line number
This register is programmed to trigger an interrupt when the video line number matches this value in bits 5:0. This
interrupt must be enabled at address C1h. The value of 0 or 1 does not generate an interrupt.
Field 1 enable:
0 = Disabled (default)
1 = Enabled
Field 2 enable:
0 = Disabled (default)
1 = Enabled
Line number: (default 00h)
2.20.64 Pixel Alignment Registers
Address
Default
CBh
4Eh
CCh
00h
Address
7
6
5
4
3
2
1
0
CBh
CCh
Switch pixel [7:0]
Reserved
Switch pixel [9:8]
These registers form a 10-bit horizontal pixel position from the falling edge of sync, where the VDP controller initiates
the program from one line standard to the next line standard; for example, the previous line of teletext to the next line
of closed caption. This value must be set so that the switch occurs after the previous transaction has cleared the delay
in the VDP, but early enough to allow the new values to be programmed before the current settings are required.
2−50
2.20.65 FIFO Output Control Register
Address
Default
CDh
01h
7
6
5
4
3
2
1
0
Reserved
Host access enable
2
This register is programmed to allow I C access to the FIFO or allowing all VDP data to go out the video port.
Host access enable:
0 = Output FIFO data to the video output Y[9:2]
2
1 = Allow I C access to the FIFO data (default)
2.20.66 Full Field Enable Register
Address
Default
CFh
00h
7
6
5
4
3
2
1
0
Reserved
Full field enable
This register enables the full field mode. In this mode, all lines outside the vertical blank area and all lines in the line
mode registers programmed with FFh are sliced with the definition of register FCh. Values other than FFh in the line
mode registers allow a different slice mode for that particular line.
Full field enable:
0 = Disable full field mode (default)
1 = Enable full field mode
2−51
2.20.67 Line Mode Registers
Address
Default
D0h
00h
D1h−FBh
FFh
ADDRESS
D0h
D1h
D2h
D3h
D4h
D5h
D6h
D7h
D8h
D9h
DAh
DBh
DCh
DDh
DEh
DFh
E0h
E1h
E2h
E3h
E4h
E5h
E6h
E7h
E8h
E9h
EAh
EBh
ECh
EDh
EEh
EFh
F0h
F1h
F2h
F3h
F4h
F5h
F6h
F7h
F8h
F9h
FAh
FBh
7
6
5
4
3
2
1
0
Line 6 Field 1
Line 6 Field 2
Line 7 Field 1
Line 7 Field 2
Line 8 Field 1
Line 8 Field 2
Line 9 Field 1
Line 9 Field 2
Line 10 Field 1
Line 10 Field 2
Line 11 Field 1
Line 11 Field 2
Line 12 Field 1
Line 12 Field 2
Line 13 Field 1
Line 13 Field 2
Line 14 Field 1
Line 14 Field 2
Line 15 Field 1
Line 15 Field 2
Line 16 Field 1
Line 16 Field 2
Line 17 Field 1
Line 17 Field 2
Line 18 Field 1
Line 18 Field 2
Line 19 Field 1
Line 19 Field 2
Line 20 Field 1
Line 20 Field 2
Line 21 Field 1
Line 21 Field 2
Line 22 Field 1
Line 22 Field 2
Line 23 Field 1
Line 23 Field 2
Line 24 Field 1
Line 24 Field 2
Line 25 Field 1
Line 25 Field 2
Line 26 Field 1
Line 26 Field 2
Line 27 Field 1
Line 27 Field 2
2−52
These registers program the specific VBI standard at a specific line in the video field.
Bit 7:
0 = Disable filtering of null bytes in closed caption modes
1 = Enable filtering of null bytes in closed caption modes (default)
In teletext modes, bit 7 enables the data filter function for that particular line. If it is set to 0, then the data filter passes
all data on that line.
Bit 6:
0 = Send VBI data to registers only.
1 = Send VBI data to FIFO and the registers. Teletext data only goes to FIFO. (default)
Bit 5:
0 = Allow VBI data with errors in the FIFO
1 = Do not allow VBI data with errors in the FIFO (default)
Bit 4:
0 = Do not enable error detection and correction
1 = Enable error detection and correction (when bits [3:0] = 1 2, 3, and 4 only) (default)
Bits [3:0]:
0000 = WST SECAM
0001 = WST PAL B
0010 = WST PAL C
0011 = WST NTSC
0100 = NABTS NTSC
0101 = TTX NTSC
0110 = CC PAL
0111 = CC NTSC
1000 = WSS PAL
1001 = WSS NTSC
1010 = VITC PAL
1011 = VITC NTSC
1100 = VPS PAL
1101 = Custom 1
1110 = Custom 2
1111 = Active video (VDP off) (default)
A value of FFh in the line mode registers is required for any line to be sliced as part of the full field mode.
2.20.68 Full Field Mode Register
Address
Default
FCh
7Fh
7
6
5
4
3
2
1
0
Full field mode
This register programs the specific VBI standard for full field mode. It can be any VBI standard. Individual line settings
take priority over the full field register. This allows each VBI line to be programmed independently but have the
remaining lines in full field mode. The full field mode register has the same definitions as the line mode registers
(default 7Fh).
2−53
2−54
3 Electrical Specifications
3.1 Absolute Maximum Ratings Over Operating Free-Air Temperature Range (unless
†
otherwise noted)
Supply voltage range: IO_DVDD to DGND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 4.5 V
DVDD to DGND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 2.3 V
PLL_AVDD to PLL_AGND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 2.3 V
CH_AVDD to CH_AGND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 2.3 V
Digital input voltage range, V to DGND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 4.5 V
I
Input voltage range, XTAL1 to PLL_GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 2.3 V
Analog input voltage range A to CH_AGND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.2 V to 2.0 V
I
Digital output voltage range, V to DGND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 4.5 V
O
Operating free-air temperature, T . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0°C to 70°C
A
Storage temperature, T
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −65°C to 150°C
stg
†
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
3.2 Recommended Operating Conditions
MIN NOM
MAX
UNIT
IO_DVDD
DVDD
Digital I/O supply voltage
Digital supply voltage
3.0
3.3
1.8
1.8
1.8
3.6
2.0
V
V
1.65
PLL_AVDD
CH_AVDD
Analog PLL supply voltage
Analog core supply voltage
Analog input voltage (ac-coupling necessary)
Digital input voltage high
1.65
2.0
V
1.65
0
2.0
V
V
V
V
V
V
0.75
V
I(P-P)
0.7 IO_DVDD
V
IH
Digital input voltage low
0.3 IO_DVDD
V
IL
XTAL input voltage high
0.7 PLL_AVDD
V
IH_XTAL
IL_XTAL
XTAL input voltage low
0.3 PLL_AVDD
V
I
I
I
I
High-level output current
2
−2
4
mA
mA
mA
mA
°C
OH
Low-level output current
OL
SCLK high-level output current
SCLK low-level output current
Operating free-air temperature
OH_SCLK
OL_SCLK
−4
70
T
0
A
3.2.1 Crystal Specifications
CRYSTAL SPECIFICATIONS
MIN
NOM
14.31818
50
MAX
UNIT
MHz
ppm
Frequency
Frequency tolerance
3−1
3.3 Electrical Characteristics
DVDD = 1.8 V, PLL_AVDD = 1.8 V, CH_AVDD = 1.8 V, IO_DVDD = 3.3 V
For minimum/maximum values: T = 0°C to 70°C, and for typical values: T = 25°C unless otherwise noted
A
3.3.1 DC Electrical Characteristics
PARAMETER
A
TEST CONDITIONS
(see NOTE 1)
MIN
TYP
MAX
UNIT
I
I
I
I
3.3-V I/O digital supply current
1.8-V digital supply current
Color bar input
Color bar input
Color bar input
Color bar input
Color bar input
4.8
25.3
5.4
mA
mA
mA
mA
mW
DD(IO_D)
DD(D)
1.8-V analog PLL supply current
1.8-V analog core supply current
Total power dissipation, normal mode
DD(PLL_A)
DD(CH_A)
24.4
115
P
150
1
TOT
Total power dissipation, power-down mode
(see Note 2)
P
Color bar input
By design
mW
DOWN
C
Input capacitance
8
pF
V
i
V
V
V
V
Output voltage high
I
I
I
I
= 2 mA
= −2 mA
= 4 mA
0.8 IO_DVDD
0.8 IO_DVDD
OH
OH
OL
OH
OL
Output voltage low
0.22 IO_DVDD
V
OL
SCLK output voltage high
SCLK output voltage low
High-level input current
Low-level input current
V
OH_SCLK
OL_SCLK
= −2 mA
0.22 IO_DVDD
V
I
I
V = V
20
20
µA
µA
IH
I
IH
V = V
IL
I
IL
NOTES: 1. Measured with a load of 15 pF.
2. Assured by device characterization.
3.3.2 Analog Processing and A/D Converters
PARAMETER
TEST CONDITIONS
MIN
TYP
500
10
MAX
UNIT
kΩ
pF
Zi
Input impedance, analog video inputs
Input capacitance, analog video inputs
By design
By design
C
i
†
Vi(pp)
∆G
Input voltage range
C
= 0.1 µF
0
0
0.75
12
V
coupling
Gain control range
DC differential nonlinearity
DC integral nonlinearity
Frequency response
Signal-to-noise ratio
Noise spectrum
dB
LSB
LSB
dB
dB
dB
°
DNL
INL
Fr
A/D only
A/D only
6 MHz
0.5
1
−0.9
50
−3
SNR
NS
6 MHz, 1.0 V
P-P
50% flat field
50
DP
Differential phase
1.5
0.5%
DG
Differential gain
†
The 0.75-V maximum applies to the sync-chroma amplitude, not sync-white. The recommended termination resistors are 37.4 Ω as seen in
Chapter 5.
3−2
3.3.3 Timing
3.3.3.1 Clocks, Video Data, Sync Timing
TEST CONDITIONS
(see NOTE 2)
PARAMETER
MIN
TYP
MAX
UNIT
Duty cycle PCLK
50%
18.5
18.5
4
t
1
t
2
t
3
t
4
t
5
t
6
PCLK high time
PCLK low time
PCLK fall time
PCLK rise time
Output hold time
Output delay time
ns
ns
ns
ns
ns
ns
10% to 90%
90% to 10%
4
2
3
8
NOTE 3: Measured with a load of 15 pF.
t
t
2
1
PCLK
t
t
4
3
V
V
OH
Y, C, AVID,
VS, HS, FID
Valid Data
Valid Data
OL
t
5
t
6
Figure 3−1. Clocks, Video Data, and Sync Timing
3−3
2
3.3.3.2 I C Host Port Timing
PARAMETER
TEST CONDITIONS
MIN
1.3
0.6
0.6
0.6
100
0
TYP
MAX
UNIT
µs
t
t
t
t
t
t
t
t
Bus free time between STOP and START
Setup time for a (repeated) START condition
Hold time (repeated) START condition
Setup time for a STOP condition
Data setup time
1
2
3
4
5
6
7
8
µs
µs
ns
ns
Data hold time
0.9
µs
Rise time VC1(SDA) and VC0(SCL) signal
Fall time VC1(SDA) and VC0(SCL) signal
Capacitive load for each bus line
250
ns
250
ns
C
400
400
pF
kHz
b
2
f
I C clock frequency
I2C
Stop Start
Stop
VC1 (SDA)
VC0 (SCL)
Data
t
t3
1
t5
t3
t6
t4
t2
t
t
7
8
2
Figure 3−2. I C Host Port Timing
3−4
4 Example Register Settings
The following example register settings are provided only as a reference. These settings, given the assumed input
connector, video format, and output format, set up the TVP5150A decoder and provide video output. Example register
settings for other features and the VBI data processor are not provided here.
4.1 Example 1
4.1.1 Assumptions
Device:
TVP5150AM1
Input connector:
Video format:
Composite (AIP1A)
NTSC-M, PAL (B, G, H, I), or SECAM
NOTE: NTSC-443, PAL-N, and PAL-M are masked from the autoswitch process by default.
See the autoswitch mask register at address 04h.
Output format:
8-bit ITU-R BT.656 with embedded syncs
4.1.2 Recommended Settings
2
Recommended I C writes: For this setup, only one write is required. All other registers are set up by default.
2
I C register address 03h = Miscellaneous controls register address
2
I C data 09h = Enables YCbCr output and the clock output
NOTE: HSYNC, VSYNC/PALI, AVID, and FID/GLCO are high impedance by default. See the
miscellaneous control register at address 03h.
4.2 Example 2
4.2.1 Assumptions
Device:
TVP5150AM1
Input connector:
Video format:
Output format:
S-video (AIP1A (luma), AIP1B (chroma))
NTSC-M, 443, PAL (B, G, H, I, M, N) or SECAM (B, D,G, K, KI, L)
8-bit 4:2:2 YCbCr with discrete sync outputs
4.2.2 Recommended Settings
2
Recommended I C writes: This setup requires additional writes to output the discrete sync 4:2:2 data outputs, the
HSYNC, and the VSYNC, and to autoswitch between all video formats mentioned above.
2
I C register address 00h = Video input source selection #1 register
2
I C data 01h = Selects the S-Video input, AIP1A (luma), and AIP1B (chroma)
2
I C register address 03h = Miscellaneous controls register address
2
I C data 0Dh = Enables the YCbCr output data, HSYNC, VSYNC/PALI, AVID, and FID/GLCO
2
I C register address 04h = Autoswitch mask register
2
I C data C0h = Unmask NTSC-443, PAL-N, and PAL-M from the autoswitch process
2
I C register address 0Dh = Outputs and data rates select register
2
I C data 40h = Enables 8-bit 4:2:2 YCbCr with discrete sync output
4−1
4−2
5 Application Information
5.1 Application Example
C2
C1
1uF
1uF
C3
1uF
PDN
PDN
INTERQ/GPCL
AVID
HSYNC
INTERQ/GPCL
AVID
HSYNC
0.1uF
R1
AVDD
C4
0.1uF
IO_DVDD
CH1_IN
37.4 Ω
R2
C11
R3
1.2K
R4
37.4 Ω
1.2K
0.1uF
1
2
3
4
5
6
7
8
24
VSYNC/PALI
FID/GLCO
SDA
R5
VSYNC/PALI
FID/GLCO
AIP1A
AIP1B
VSYNC/PALI
FID/GLCO
SDA
C5
23
22
21
20
19
18
17
CH2_IN
37.4 Ω
PLL_AGND
PLL_AVDD
XTAL1/OSC
XTAL2
AVDD
SCL
DVDD
SCL
DVDD
TVP5150A
R6
37.4 Ω
C6
DGND
C7
AGND
RESETB
YOUT0
YOUT1
0.1uF
0.1uF
S1
OSC
1
2
OSC_IN
Y1
PCLK/SCLK
PCLK/SCLK
RESETB
14.31818MHz
IO_DVDD
C8
C9
YOUT[7:0]
C10
0.1uF
IO_DVDD
CL1
CL2
R7
2
Implies I C address is BAh. If B8h is to be used,
10K
connect pulldown resistor to digital ground.
NOTE: The use of INTERQ/GPCL/AVID/HSYNC and VSYNC is optional. These are outputs and can be left floating.
When OSC is connected through S1, remove the capacitors for the crystal.
PDN needs to be high, if device has to be always operational.
RESETB is operational only when PDN is high. This allows an active low reset to the device.
Figure 5−1. Application Example
5−1
5−2
6 Mechanical Data
PBS (S-PQFP-G32)
PLASTIC QUAD FLATPACK
0,23
0,17
M
0,50
24
0,08
17
25
16
32
9
0,13 NOM
1
8
3,50 TYP
Gage Plane
5,05
SQ
4,95
0,25
7,10
SQ
0,10 MIN
6,90
0°−ā7°
0,70
0,40
1,05
0,95
Seating Plane
0,08
1,20 MAX
4087735/A 11/95
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
6−1
ZQC (S−PBGA−N48)
PLASTIC BALL GRID ARRAY
4,10
3,90
SQ
3,00 TYP
0,50
G
F
0,50
E
D
C
B
A
3,00 TYP
1
234
567
A1 Corner
Bottom View
0,77
0,71
1,00 MAX
Seating Plane
0,08
0,35
0,25
0,25
0,15
0,05
4204695/A 09/02
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. MicroStar Junior BGA package configuration.
D. Falls within JEDEC MO-225
E. This package is lead free.
MicroStar Junior is a trademark of Texas Instruments.
6−2
PACKAGE OPTION ADDENDUM
www.ti.com
22-Feb-2005
PACKAGING INFORMATION
Orderable Device
TVP5150AM1PBS
TVP5150AM1PBSR
TVP5150AM1ZQC
Status (1)
ACTIVE
ACTIVE
ACTIVE
Package Package
Pins Package Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)
Qty
Type
Drawing
TQFP
PBS
32
32
48
250 Green (RoHS & CU NIPDAU Level-3-260C-168 HR
no Sb/Br)
TQFP
PBS
ZQC
1000 Green (RoHS & CU NIPDAU Level-3-260C-168 HR
no Sb/Br)
BGA MI
CROSTA
R JUNI
OR
360
Pb-Free
(RoHS)
SNAGCU
Level-3-260C-168 HR
TVP5150AM1ZQCR
ACTIVE
BGA MI
CROSTA
R JUNI
OR
ZQC
48
2500
Pb-Free
(RoHS)
SNAGCU
Level-3-260C-168 HR
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) Eco Plan - May not be currently available - please check http://www.ti.com/productcontent for the latest availability information and additional
product content details.
None: Not yet available Lead (Pb-Free).
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Green (RoHS & no Sb/Br): TI defines "Green" to mean "Pb-Free" and in addition, uses package materials that do not contain halogens,
including bromine (Br) or antimony (Sb) above 0.1% of total product weight.
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDECindustry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
Addendum-Page 1
MECHANICAL DATA
MPQF027 – NOVEMBER 1995
PBS (S-PQFP-G32)
PLASTIC QUAD FLATPACK
0,23
0,17
M
0,50
0,08
24
17
25
32
16
9
0,13 NOM
1
8
3,50 TYP
Gage Plane
5,05
SQ
4,95
0,25
7,10
SQ
0,10 MIN
6,90
0°–7°
0,70
0,40
1,05
0,95
Seating Plane
0,08
1,20 MAX
4087735/A 11/95
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
相关型号:
TVP5150AZQCR
Ultralow Power NTSC/PAL/SECAM Video Decoder w/Robust Sync Detector 48-BGA MICROSTAR JUNIOR
TI
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