TUSB3410_技术文档

ꢀ ꢁꢂ ꢃꢄ ꢅ ꢆ ꢇ

ꢁ ꢂꢃ ꢀ ꢈ ꢂ ꢉ ꢊ ꢋꢌꢍ ꢎ ꢈꢊ ꢏ ꢐ ꢈ ꢑ ꢏꢊꢈ ꢍꢍꢉ ꢊ

Data Manual

NOTE

Designing with this device may require extensive support. Before incorporating this device into

a design, customers should contact TI or an Authorized TI Distributor.

June 2002

MSP USB

SLLS519B

IMPORTANT NOTICE

Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications,

enhancements, improvements, and other changes to its products and services at any time and to discontinue

any product or service without notice. Customers should obtain the latest relevant information before placing

orders and should verify that such information is current and complete. All products are sold subject to TI’s terms

and conditions of sale supplied at the time of order acknowledgment.

TI warrants performance of its hardware products to the specifications applicable at the time of sale in

accordance with TI’s standard warranty. Testing and other quality control techniques are used to the extent TI

deems necessary to support this warranty. Except where mandated by government requirements, testing of all

parameters of each product is not necessarily performed.

TI assumes no liability for applications assistance or customer product design. Customers are responsible for

their products and applications using TI components. To minimize the risks associated with customer products

and applications, customers should provide adequate design and operating safeguards.

TI does not warrant or represent that any license, either express or implied, is granted under any TI patent right,

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Contents

Section

Title

Page

1

Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–1

1.1 Controller Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–1

Main Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–1

2

2.1

2.2

2.3

2.4

USB Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–1

General Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–1

Enhanced UART Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–1

Pinout Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–2

3

Detailed Controller Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–1

3.1

3.2

Operating Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–1

USB Interface Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–1

3.2.1

3.2.2

External Memory Case . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–1

Host Download Case . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–1

3.3

3.4

3.5

USB Data Movement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–1

Serial Port Setup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–1

Serial Port Data Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–2

3.5.1

3.5.2

3.5.3

RS-232 Data Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–2

RS-485 Data Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–2

IrDA Data Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–2

4

MCU Memory Map (Internal Operation) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–1

4.1

Miscellaneous Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–2

4.1.1

ROMS: ROM Shadow Configuration Register

(Addr:FF90) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–2

4.1.2

4.1.3

Boot Operation (MCU Firmware Loading) . . . . . . . . . . . . . . 4–2

WDCSR: Watchdog Timer, Control, and Status Register

(Addr:FF93) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–3

4.2

4.3

Buffers + I/O RAM Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–3

Endpoint Descriptor Block (EDB–1 to EDB–3) . . . . . . . . . . . . . . . . . . . 4–5

4.3.1

4.3.2

4.3.3

4.3.4

4.3.5

4.3.6

OEPCNF_n: Output Endpoint Configuration (n = 1 to 3)

(Addr:FF08, FF10, FF18) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–6

OEPBBAX_n: Output Endpoint X-Buffer Base Address

(n = 1 to 3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–6

OEPBCTX_n: Output Endpoint X Byte Count

(n = 1 to 3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–7

OEPBBAY_n: Output Endpoint Y-Buffer Base Address

(n = 1 to 3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–7

OEPBCTY_n: Output Endpoint Y-Byte Count

(n = 1 to 3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–7

OEPSIZXY_n: Output Endpoint X-/Y-Buffer Size

(n =1 to 3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–8

iii

4.3.7

4.3.8

IEPCNF_n: Input Endpoint Configuration (n = 1 to 3)

(Addr:FF48, FF50, FF58) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–8

IEPBBAX_n: Input Endpoint X-buffer Base Address

(n = 1 to 3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–8

4.3.9

IEPBCTX_n: Input Endpoint X-Byte Count (n = 1 to 3) . . . 4–9

4.3.10

IEPBBAY_n: Input Endpoint Y-Buffer Base Address

(n = 1 to 3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–9

4.3.11

4.3.12

IEPBCTY_n: Input Endpoint Y-Byte Count (n = 1 to 3) . . . 4–9

IEPSIZXY_n: Output Endpoint X-/Y-Buffer Size

(n = 1 to 3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–10

4.4

Endpoint-0 Descriptor Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–10

4.4.1

4.4.2

4.4.3

4.4.4

IEPCNFG_0: Input Endpoint-0 Configuration Register

(Addr:FF80) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–10

IEPBCNT_0: Input Endpoint-0 Byte Count Register

(Addr:FF81) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–10

OEPCNFG_0: Output Endpoint-0 Configuration Register

(Addr:FF82) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–11

OEPBCNT_0: Output Endpoint-0 Byte Count Register

(Addr:FF83) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–11

5

USB . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5–1

5.1 USB Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5–1

5.1.1

5.1.2

5.1.3

5.1.4

5.1.5

5.1.6

5.1.7

FUNADR: Function Address Register (Addr:FFFF) . . . . . . 5–1

USBSTA: USB Status Register (Addr:FFFE) . . . . . . . . . . . 5–1

USBMSK: USB Interrupt Mask Register (Addr:FFFD) . . . . 5–2

USBCTL: USB Control Register (Addr:FFFC) . . . . . . . . . . . 5–3

MODECNFG: Mode Configuration Register (Addr:FFFB) 5–4

Vendor ID/Product ID . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5–4

SERNUM7: Device Serial Number Register (Byte 7)

(Addr:FFEF) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5–4

5.1.8

SERNUM6: Device Serial Number Register (Byte 6)

(Addr:FFEE) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5–5

5.1.9

SERNUM5: Device Serial Number Register (Byte 5)

(Addr:FFED) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5–5

5.1.10

5.1.11

5.1.12

5.1.13

5.1.14

SERNUM4: Device Serial Number Register (Byte 4)

(Addr:FFEC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5–6

SERNUM3: Device Serial Number Register (Byte 3)

(Addr:FFEB) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5–6

SERNUM2: Device Serial Number Register (Byte 2)

(Addr:FFEA) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5–6

SERNUM1: Device Serial Number Register (Byte 1)

(Addr:FFE9) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5–6

SERNUM0: Device Serial Number Register (Byte 0)

(Addr:FFE8) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5–7

5.1.15

5.1.16

Function Reset And Power-Up Reset Interconnect . . . . . . 5–7

Pullup Resistor Connect/Disconnect . . . . . . . . . . . . . . . . . . 5–8

iv

6

DMA Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–1

6.1 DMA Controller Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–1

6.1.1

6.1.2

6.1.3

6.1.4

DMACDR1: DMA Channel Definition Register (UART Transmit

Channel) (Addr:FFE0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–2

DMACSR1: DMA Control And Status Register (UART Transmit

Channel) (Addr:FFE1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–3

DMACDR3: DMA Channel Definition Register (UART Receive

Channel) (Addr:FFE4) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–4

DMACSR3: DMA Control And Status Register (UART Receive

Channel) (Addr:FFE5) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–5

6.2

Bulk Data I/O Using the EDB . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–5

6.2.1

6.2.2

IN Transaction (TUSB3410 to Host) . . . . . . . . . . . . . . . . . . . 6–5

OUT Transaction (Host to TUSB3410) . . . . . . . . . . . . . . . . . 6–6

7

UART . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7–1

7.1 UART Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7–1

7.1.1

7.1.2

7.1.3

7.1.4

7.1.5

7.1.6

7.1.7

7.1.8

7.1.9

7.1.10

7.1.11

7.1.12

7.1.13

7.1.14

RDR: Receiver Data Register (Addr:FFA0) . . . . . . . . . . . . . 7–1

TDR: Transmitter Data Register (Addr:FFA1) . . . . . . . . . . . 7–1

LCR: Line Control Register (Addr:FFA2) . . . . . . . . . . . . . . . 7–2

FCRL: UART Flow Control Register (Addr:FFA3) . . . . . . . . 7–3

Transmitter Flow Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7–4

MCR: Modem-Control Register (Addr:FFA4) . . . . . . . . . . . . 7–5

LSR: Line-status Register (Addr:FFA5) . . . . . . . . . . . . . . . . 7–6

MSR: Modem-Status Register (Addr:FFA6) . . . . . . . . . . . . 7–7

DLL: Divisor Register Low Byte (Addr:FFA7) . . . . . . . . . . . 7–8

DLH: Divisor Register High Byte (Addr:FFA8) . . . . . . . . . . . 7–8

Baud-rate Calculation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7–8

XON: Xon Register (Addr:FFA9) . . . . . . . . . . . . . . . . . . . . . . 7–9

XOFF: Xoff Register (Addr:FFAA) . . . . . . . . . . . . . . . . . . . . . 7–9

MASK: UART Interrupt-Mask Register (Addr:FFAB) . . . . . 7–10

7.2

UART Data Transfer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7–10

7.2.1

7.2.2

7.2.3

7.2.4

7.2.5

7.2.6

Receiver Data Flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7–10

Hardware Flow Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7–11

Auto RTS (Receiver Control) . . . . . . . . . . . . . . . . . . . . . . . . . 7–11

Auto CTS (Transmitter Control) . . . . . . . . . . . . . . . . . . . . . . . 7–11

Xon/Xoff Receiver Flow Control . . . . . . . . . . . . . . . . . . . . . . . 7–12

Xon/Xoff Transmit Flow Control . . . . . . . . . . . . . . . . . . . . . . . 7–12

8

9

Expanded GPIO Port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8–1

8.1 Input/Output and Control Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8–1

8.1.1 PUR_3: GPIO Pullup Register For Port 3 (Addr:FF9E) . . . 8–1

Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9–1

9.1 8052 Interrupt and Status Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . 9–1

9.1.1

9.1.2

9.1.3

9.1.4

8052 Standard Interrupt Enable (SIE) Register . . . . . . . . . 9–1

Additional Interrupt Sources . . . . . . . . . . . . . . . . . . . . . . . . . . 9–1

VECINT: Vector Interrupt Register (Addr:FF92) . . . . . . . . . 9–2

Logical Interrupt Connection Diagram (Internal/External) . 9–3

v

10 I2C-Port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10–1

10.1 I2C Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10–1

10.1.1

10.1.2

10.1.3

10.1.4

I2CSTA: I2C Status and Control Register (Addr:FFF0) . . . 10–1

I2CADR: I2C Address Register (Addr:FFF3) . . . . . . . . . . . . 10–2

I2CDAI: I2C Data-Input Register (Addr:FFF2) . . . . . . . . . . 10–2

I2CDAO: I2C Data-Output Register (Addr:FFF1) . . . . . . . . 10–2

10.2 Random-Read Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10–2

10.3 Current-Address Read Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10–3

10.4 Sequential-Read Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10–3

10.5 Byte-Write Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10–4

10.6 Page-Write Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10–5

11 TUSB3410 Bootcode Flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11–1

11.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11–1

11.2 Bootcode Programming Flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11–1

11.3 Default Bootcode Settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11–2

11.3.1

11.3.2

11.3.3

11.3.4

11.3.5

Device Descriptor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11–3

Configuration Descriptor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11–3

Interface Descriptor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11–4

Endpoint Descriptor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11–4

String Descriptor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11–5

11.4 External Device Header Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11–6

11.4.1

11.4.2

Product Signature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11–6

Descriptor Block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11–7

11.4.2.1

11.4.2.2

Descriptor Prefix . . . . . . . . . . . . . . . . . . . . . . . . 11–7

Descriptor Content . . . . . . . . . . . . . . . . . . . . . . 11–7

11.5 Checksum in Descriptor Block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11–7

11.6 Header Examples . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11–7

11.6.1

11.6.2

11.6.3

TUSB3410 Bootcode Supported Descriptor Block . . . . . 11–7

USB Descriptor Header . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11–8

Autoexec Binary Firmware . . . . . . . . . . . . . . . . . . . . . . . . . 11–10

11.7 Host Driver Downloading Header Format . . . . . . . . . . . . . . . . . . . . . 11–10

11.8 Built-In Vendor Specific USB Requests . . . . . . . . . . . . . . . . . . . . . . . 11–11

11.8.1

11.8.2

11.8.3

11.8.4

11.8.5

11.8.6

11.8.7

Reboot . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11–11

Force Execute Firmware . . . . . . . . . . . . . . . . . . . . . . . . . . . 11–11

External Memory Read . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11–11

External Memory Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11–11

2

I C Memory Read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11–12

2

I C Memory Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11–12

Internal ROM Memory Read . . . . . . . . . . . . . . . . . . . . . . . 11–12

11.9 Bootcode Programming Consideration . . . . . . . . . . . . . . . . . . . . . . . 11–13

11.9.1

11.9.2

USB Requests . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11–13

Hardware Reset Introduced by Firmware . . . . . . . . . . . . 11–16

11.10 File Listings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11–16

12 Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12–1

vi

12.1 Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12–1

12.2 Commercial Operating Condition (3.3 V) . . . . . . . . . . . . . . . . . . . . . . . 12–1

12.3 Electrical Characteristics TA = 255C, VCC = 3.3 V +5%,

VSS = 0 V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12–1

13 Application Notes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13–1

13.1 Crystal Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13–1

13.2 External Circuit Required for Reliable Bus Powered Suspend

Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13–1

14 Mechanical . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14–1

vii

List of Illustrations

Figure

Title

Page

1–1 Controller Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–1

1–2 USB-to-Serial (Single Channel) Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–2

3–1 RS-232 and IR Mode Select . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–3

3–2 USB-to-Serial Implementation (RS-232) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–4

3–3 RS-485 Bus Implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–4

4–1 MCU Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–1

5–1 Reset Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5–7

5–2 Pullup Resistor Connect/Disconnect Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . 5–8

6–1 Transaction Time-Out Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–3

7–1 MSR and MCR Registers in Loop-Back Mode . . . . . . . . . . . . . . . . . . . . . . . . 7–7

7–2 Receiver/Transmitter Data Flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7–11

7–3 Auto Flow Control Interconnect . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7–11

9–1 Internal Vector Interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9–3

11–1 Control Read Transfer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11–13

11–2 Control Write Transfer Without Data Stage . . . . . . . . . . . . . . . . . . . . . . . . . 11–14

13–1 Crystal Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13–1

13–2 External Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13–1

viii

List of Tables

Table

Title

Page

2–1 Terminal Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–4

4–1 ROM/RAM Size Definition Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–2

4–2 XDATA Space . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–3

4–3 Memory Mapped Registers Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–4

4–4 EDB Memory Locations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–5

4–5 EDB Entries in RAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–6

4–6 Input/Output EDB-0 Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–10

6–1 DMA Controller Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–1

6–2 DMA OUT-Termination Condition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–3

6–3 DMA IN-Termination Condition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–5

7–1 UART Registers Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7–1

7–2 Transmitter Flow-Control Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7–4

7–3 Receiver Flow-Control Possibilities . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7–4

7–4 DLL/DLH Values and Resulted Baud Rates . . . . . . . . . . . . . . . . . . . . . . . . . . 7–9

9–1 8052 Interrupt Location Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9–1

9–2 Vector Interrupt Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9–2

11–1 Device Descriptor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11–3

11–2 Configuration Descriptor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11–3

11–3 Interface Descriptor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11–4

11–4 Output Endpoint1 Descriptor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11–4

11–5 String Descriptor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11–5

11–6 USB Descriptors Header . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11–8

11–7 Autoexec Binary Firmware . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11–10

11–8 Host Driver Downloading Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11–10

11–9 Bootcode Response to Control Read Transfer . . . . . . . . . . . . . . . . . . . . . . 11–14

11–10 Bootcode Response to Control Write Without Data Stage . . . . . . . . . . . 11–14

11–11 Vector Interrupt Values and Sources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11–15

ix

x

1 Introduction

1.1 Controller Description

The TUSB3410 provides bridging between a USB port and an enhanced UART serial port. The TUSB3410 contains

all the necessary logic to communicate with the host computer using the USB bus. It contains an 8052 microcontroller

2

unit (MCU) with 16K bytes of RAM that can be loaded from the host or from external on-board memory via an I C

bus. It also contains 10K bytes of ROM that allow the MCU to configure the USB port at boot time. The ROM code

2

alsocontainsanI Cbootloader. AllthedevicefunctionssuchastheUSBcommanddecoding, UARTsetup, anderror

reporting are managed by the internal MCU firmware under the auspices of the PC host.

The TUSB3410 can be used to build an interface between a legacy serial peripheral device and a PC with USB ports,

such as a legacy-free PC. Once configured, data flows from the host to the TUSB3410 via USB OUT commands and

then out from the TUSB3410 on the SOUT line. Conversely, data flows into the TUSB3410 on the SIN line and then

into the host via USB IN commands.

Out

SOUT

Legacy

Serial

Peripheral

Host

(PC or OTG DRD)

USB

In

TUSB3410

SIN

Figure 1–1. Data Flow

1–1

12 MHz

Clock

Oscillator

8052

Core

PLL

and

24 MHz

Dividers

8

2 × 16-Bit

Timers

10K × 8

ROM

USB

TxR

DP, DM

16K × 8

RAM

4

Port 3

P3.(4, 3,1,0)

2K × 8

SRAM

8

2

I C

2

I C Bus

Controller

DMA-1

DMA-3

8

CPU-I/F

Susp./Res.

8

RTS

CTS

DTR

DSR

USB

SIE

8

UART–1

UBM

USB Buffer

Manager

SIN

SOUT

TDM

Control

Logic

IR

M

Encoder

U

X

SOUT/IR_SO

SIN/IR_SIN

IR

M

U

X

Encoder

Figure 1–2. USB-to-Serial (Single Channel) Controller Block Diagram

1–2

2 Main Features

2.1 USB Features

•

Fully compliant with USB 2.0 full speed Specifications

Supports 12-Mbps USB data rate (full speed)

Supports USB suspend, resume, and remote wakeup operations

Supports two power source modes:

–

Bus-powered mode

Self-powered mode

•

Can support a total of 3-input and 3-output (interrupt, bulk) endpoints

2.2 General Features

•

Integrated 8052 microcontroller with

–

256 × 8 RAM for internal data

2

10K × 8 ROM (with USB and I C boot loader)

2

16K × 8 RAM for code space loadable from host or I C port

2K × 8 Shared RAM used for data buffers and endpoint descriptor blocks (EDB)

Four GPIO pins from 8052 port 3

2

Master I C controller for EEPROM device access

MCU operates at 24 MHz providing 2 MIPS operation

128-ms Watchdog Timer

•

Built-in two-channel DMA controller for USB/UART bulk I/O

Operates from a 12-MHz crystal

Supports USB suspend and resume

Supports remote wake-up

Available in 32-pin LQFP

3.3-V operation with 1.8-V core operating voltage provided by on-chip 1.8-V voltage regulator

2.3 Enhanced UART Features

•

Software/hardware flow control:

–

Programmable Xon/Xoff characters

Programmable Auto-RTS/DTR and Auto-CTS/DSR

•

Automatic RS485-bus transceiver control, with and without echo

Selectable IrDA mode for up to 115.2 kbps transfer

Software selectable baud rate from 50 to 921.6 k baud

Programmable serial-interface characteristics

–

5-, 6-, 7-, or 8-Bit characters

Even, odd, or no parity-bit generation and detection

1-, 1.5-, or 2-Stop bit generation

•

Line break generation and detection

2–1

•

Internal test and loop-back capabilities

Modem-control functions (CTS, RTS, DSR, DTR, RI, and DCD)

Internal diagnostics capability

–

Loopback control for communications link-fault isolation

Break, parity, overrun, framing-error simulation

2.4 Pinout Information

VF PACKAGE

(TOP VIEW)

24 23 22 21 20 19 18 17

25

26

27

28

29

30

31

32

VCC

X2

16 RI/CP

15

14

13

12

11

10

9

DCD

X1/CLK1

GND

DSR

CTS

P3.4

WAKEUP

SCL

P3.3

P3.1

SDA

P3.0

RESET

1

2 3 4 5 6 7 8

2–2

Table 2–1. Terminal Functions

TERMINAL

NAME

CLKOUT

I/O

DESCRIPTION

NO.

22

O

Clock output (controlled by CLKOUTEN and CLKSLCT in MODECNFG register (see Section 5.1.5

and Note 1)

CTS

DCD

DM

13

15

7

I

UART: Clear to send (see Note 4)

UART: Data carrier detect (see Note 4)

Upstream USB port differential data minus

Upstream USB port differential data plus

UART: Data set ready (see Note 4)

UART: Data terminal ready (see Note 1)

I/O

I

DP

6

DSR

DTR

GND

P3.0

P3.1

P3.3

P3.4

PUR

RESET

RI/CP

RTS

SCL

SDA

14

21

O

8, 18, 28 GND Digital ground

32

31

30

29

5

I/O

O

I

Port-3.0 (see Notes 3, 4, 5, and 8)

Port-3.1 (see Notes 3, 4, 5, and 8)

Port-3.3 (see Notes 3, 4, 5, and 8)

Port-3.4 (see Notes 3, 4, 5, and 8)

Pull-up resistor connection (see Note 2)

Controller master reset signal (see Note 4)

UART: Ring indicator (see Note 4)

UART: Request to send (see Note 1)

9

16

20

11

10

17

19

2

I

O

I/O

I

2

Master I C controller: clock signal (see Note 1)

2

Master I C controller: data signal (see Notes 1 and 5)

SIN/IR_SIN

SOUT/IR_SOUT

SUSPEND

TEST0

UART: Serial input data / IR Serial data input (see Note 6)

UART: Serial output data / IR Serial data output (see Note 7)

Suspend condition signal (see Note 3)

O

I

23

24

3, 25

4

Test input (for factory test only) (see Note 5)

TEST1

I

Test input (for factory test only) (see Note 5)

VCC

PWR 3.3 V

VDD18

PWR 1.8-V Supply. An internal voltage regulator generates this supply voltage when terminal VREGEN

is asserted. When VREGEN is deasserted, 1.8 V must be supplied externally.

VREGEN

WAKEUP

X1/CLKI

X2

1

I

This active-low terminal is used to enable the 3.3-V to 1.8-V voltage regulator in the core.

Remote wake-up request pin. When low, wakes up system (see Note 5)

12-MHz crystal input or clock input

12

27

26

I

O

12-MHz crystal output

NOTES: 1. 3-state CMOS output (±4-mA drive/sink)

2. 3-state CMOS output (±8-mA drive/sink)

3. 3-state CMOS output (±12-mA drive/sink)

4. TTL-compatible, hysteresis input

5. TTL-compatible, hysteresis input, with internal 100-µA active pullup

6. TTL-compatible input without hysteresis, with internal 100-µA active pullup

7. Normal or IR mode: 3-state CMOS output (±4-mA drive/sink)

8. The MCU treats the outputs as open drain types in that the output can be driven low continuously, but a high output is driven for two

clock cycles and then the output is tristated.

2–3

2–4

3 Detailed Controller Description

3.1 Operating Modes

The TUSB3410 controls its USB interface in response to USB commands, and this action remains the same

independent of the serial port mode selected. On the other hand, the serial port can be set up in three modes.

As with any interface device, data movement is the TUSB3410’s main function, but typically the initial configuration

and error handling consume most of the support code. The following sections describe the various modes the device

can be used in and the means of setting up the device.

3.2 USB Interface Configuration

The TUSB3410 contains onboard ROM microcode, which enables the MCU to enumerate the device as a USB

peripheral. The ROM microcode can also load application code into internal RAM from either external memory via

2

the I C bus or from the host via the USB.

3.2.1 External Memory Case

After reset, the TUSB3410 is disconnected from the USB because the pullup resistor CONT bit is cleared. The

2

TUSB3410 checks the I C port for the existence of valid code, if it finds valid code, it uploads the code from the

external memory device into the RAM program space. Once loaded, the TUSB3410 connects to the USB by setting

the CONT bit and enumeration and configuration are performed. This is the most likely use of the device.

3.2.2 Host Download Case

2

If the valid code is not found at the I C port, the TUSB3410 connects to the USB by setting the CONT bit, and then

an enumeration and default configuration are performed. The host can then download additional microcode into RAM

to tailor the application. Then, the MCU causes a disconnect and reconnect by using the pullup resistor CONT bit

in the USBCTL register, which causes the TUSB3410 to be re-enumerated with a new configuration.

3.3 USB Data Movement

From the USB perspective, the TUSB3410 looks like a USB peripheral device. It uses endpoint 0 as its control

endpoint, as do all USB peripherals. It also configures up to three input and three output endpoints, although most

applications use one bulk input endpoint for data in, one bulk output endpoint for data out, and one interrupt endpoint

for status updates. The USB configuration likely remains the same regardless of the serial port configuration.

Most data is moved from the USB side to the UART side and vice versa using on-chip DMA transfers. Some special

cases may use programmed IO under control of the MCU.

3.4 Serial Port Setup

The serial port requires a few control registers to be written to configure its operation. This configuration likely remains

the same regardless of the data mode used. These registers include the line control register that controls the serial

word format and the divisor registers that control the baud rate.

These registers are usually controlled by the host application.

3.5 Serial Port Data Modes

The serial port can be configured in three different, although similar, data modes. Similar to the USB mode, once

configured for a specific application, it is unlikely that the mode would be changed. The different modes affect the

timing of the serial input and output or the use of the control signals. However, the basic serial-to-parallel conversion

3–1

of the receiver and parallel-to-serial conversion of the transmitter remain the same in all modes. Some features are

available in all modes, but are only applicable in certain modes. For instance, software flow control via Xoff/Xon

characters can be used in all modes, but would usually only be used in RS-232 or IrDA mode because the RS-485

mode is half-duplex communication. Similarly, hardware flow control via RTS/CTS (or DTR/DSR) handshaking is

available in RS-232 or IrDA mode. However, this would probably be used only in RS-232 mode, since in IrDA mode

only the SIN and SOUT paths are optically coupled.

3.5.1 RS-232 Data Mode

The default mode is called the RS-232 mode, and is usually used for full duplex communication on SOUT and SIN.

In this mode, the modem control outputs (RTS and DTR) are used to communicate to a modem or as general outputs.

The modem control inputs (CTS, DSR, DCD, and RI) are used for modem communication or as general inputs.

Alternatively, RTS and CTS (or DTR and DSR) can be used to throttle the data flow on SOUT and SIN to prevent

receive fifo overruns. Finally, software flow control via Xoff/Xon characters can be used for the same purpose.

This mode represents the most general-purpose applications, and the other modes are subsets of this mode.

3.5.2 RS-485 Data Mode

The RS-485 mode is very similar to the RS-232 mode in that the SOUT and SIN formats remain the same. Since

RS-485 is a bus architecture, it is inherently a single duplex communication system. The TUSB3410 in RS-485 mode

controls the RTS and DTR signals such that either can be used to enable an RS-485 driver or RS-485 receiver. When

in RS-485 mode, the enable signals for transmitting are automatically asserted whenever the DMA is set up for

outbound data. The receiver can be left enabled while the driver is enabled to allow an echo if desired, but when

receive data is expected, the driver must be disabled. Note that this precludes use of hardware flow control, since

this is a half duplex operation, it would not be effective anyhow. Software flow control is supported, but may be of

limited value.

The RS-485 mode is enabled by setting the 485E bit in the FCRL register, and a receiver enable (RCVE) bit in the

MCR allows the receiver to eavesdrop while in 485 mode.

3.5.3 IrDA Data Mode

The IrDA mode encodes SOUT and decodes SIN in the manner prescribed by the IrDA standard, up to 115.2 kbps.

Connection to an external IrDA transceiver is required. Communications is usually full duplex. Generally in an IrDA

system only the SOUT and SIN paths are connected, so hardware flow control is usually not an option. Software flow

control is supported.

The IrDA mode is enabled by setting the IREN bit in the USB control register.

The IR encoder and decoder circuitry work with the UART to change the serial bit stream into a series of pulses and

back again. For every zero bit in the outbound serial stream, the encoder sends a low-to-high-to-low pulse with the

duration of 3/16 of a bit frame at the middle of the bit time. For every one bit in the serial stream, the output remains

low for the entire bit time.

The decoding process consists of receiving the signal from the IrDA receiver and converting it to a series of zeroes

and ones. As the converse to the encoder, the decoder converts a pulse to a zero bit and the lack of a pulse to a one

bit.

3–2

SOUT

IR_TX

0

M

U

X

SOUT/IR_SOUT

SOUT

IR

From

UART

1

Encoder

IREN

0

UART

BaudOut

Clock

M

U

X

SOFTSW

1

TXCNTL

0

M

U

X

CLKOUT Pin

CLKOUTEN

3.556 MHz

CLKSLCT

1

3.3 V

0

To

UART

Receiver

M

U

X

SIN

IR_RX

IR

Decoder

SIN/IR_SIN Pin

1

Figure 3–1. RS-232 and IR Mode Select

3–3

DB9

Connector

Transceivers

12 MHz

4

7

DTR

RTS

RI

DCD

DSR

CTS

1

Serial Port

6

8

3

2

SOUT

SIN

USB-0

TUSB3410

P3.0

P3.1

P3.3

P3.4

GPIO Pins for

Other Onboard

Control Function

Figure 3–2. USB-to-Serial Implementation (RS-232)

12 MHz

RTS

RS-485 Bus

SOUT

DTR

SIN

USB-0

RS-485

TUSB3410

Transceiver

2-Bits Time

1-Bit Max

SOUT

DTR

RTS

Receiver is Disabled if RCVE = 0

Figure 3–3. RS-485 Bus Implementation

3–4

4 MCU Memory Map (Internal Operation)

Figure 4–1 illustrates the MCU memory map under boot and normal operation. For more information regarding the

integrated 8052, see the TUSBxxxx Microcontroller Reference Guide (SLLU044).

NOTE:

The internal 256 bytes of RAM are not shown, since they are assumed to be in the standard

8052 location (0000 to 00FF). The shaded areas represent the internal ROM/RAM.

When SDW bit = 0 (boot mode): The 10K ROM is mapped to address (0x0000–0x27FF) and is duplicated in location

(0x8000–0xA7FF) in code space. The internal 16K RAM is mapped to address range (0x0000–0x3FFF) in data

space. Buffers, MMR, and I/O are mapped to address range (0xF800–0xFFFF) in data space.

When SDW bit = 1 (normal mode): The 10K ROM is mapped to (0x8000–0xA7FF) in code space. The internal 166K

RAM is mapped to address range (0x0000–0x3FFFF) in code space. Buffers, MMR, and I/O are mapped to address

range (0xF800–0xFFFF) in data space.

Boot Mode (SDW = 0)

Normal Mode (SDW = 1)

CODE

XDATA

CODE

XDATA

0000

10K Boot ROM

(16K)

16K

Read/Write

Code RAM

Read Only

27FF

3FFF

8000

10K Boot ROM

A7FF

F800

2K Data

MMR

2K Data

MMR

FF7F

FF80

FFFF

Figure 4–1. MCU Memory Map

4–1

4.1 Miscellaneous Registers

4.1.1 ROMS: ROM Shadow Configuration Register (Addr:FF90)

This register is used by the MCU to switch from boot mode to normal operation mode (boot mode is set on power-on

reset only). In addition, this register provides the device revision number and the ROM/RAM configuration.

7

6

5

4

3

2

1

0

ROA

R/O

S1

S0

R3

R2

R1

R0

SDW

R/W

R/O

BIT

NAME

SDW

RESET

FUNCTION

This bit enables/disables boot ROM. (Shadow the ROM).

0

SDW = 0 When clear, the MCU executes from the 10K boot-ROM space. The boot ROM appears in two

locations: 0000 and 8000h. The 16K RAM is mapped to XDATA space; therefore, read/write

operation is possible. This bit is set by the MCU after the RAM load is completed. MCU cannot

clear this bit; it is cleared on power-up reset or watchdog time-out reset.

SDW = 1 WhensetbytheMCU,the10Kboot-ROMmapstolocation8000h,andthe16KRAMismapped

to code space, starting at location 0000h. At this point, the MCU executes from RAM, and the

write operation is disabled (no write operation is possible in code space).

4–1

6–5

R[3:0]

S[1:0]

No effect

These bits reflect the device revision number.

Code space size. These bits define the ROM or RAM code-space size (ROA bit defines ROM or RAM).

These bits are permanently set and are not affected by reset (see Table 4–1).

00 = 4K bytes code space size

01 = 8K bytes code space size

10 = 16K bytes code space size

11 = 32K bytes code space size

7

ROA

No effect

ROM or RAM version. This bit indicates whether the code space is RAM or ROM based. This bit is

permanently set and is not affected by reset (see Table 4–1).

ROA = 0 Code space is ROM

ROA = 1 Code space is RAM

Table 4–1. ROM/RAM Size Definition Table

ROMS REGISTER

BOOT ROM

RAM CODE

ROM CODE

ROA

S1

0

S0

0

1

None

10K

None

4K

8K

0

1

0

None

16K (reserved)

32K (reserved)

None

1

None

0

4K

0

1

10K

8K

None

1

0

10K

16K

None

1

10K

32K (reserved)

None

4.1.2 Boot Operation (MCU Firmware Loading)

Since the code space is in RAM (with the exception of the boot ROM), the TUSB3410 firmware must be loaded from

2

an external source. Two sources are available for booting: one from an external serial E PROM connected to the I C

bus and the other from the host via the USB. On device reset, the SDW bit (in ROMS register) and CONT bit (in

USBCTL: USB control register) are cleared. This configures the memory space to boot mode (see Memory Map) and

keeps the device disconnected from the host. The first instruction is fetched from location 0000h (which is in the 10K

ROM). The 16K RAM is mapped to XDATA space (location 0000h). The MCU executes a read from an external

2

E PROM and tests whether it contains the code (by testing for boot signature). If it contains the code, the MCU reads

2

from E PROM and writes to the 16K RAM in XDATA space. If it does not contain the code, the MCU proceeds to boot

from the USB.

4–2

Once the code is loaded, the MCU sets SDW = 1. This switches the memory map to normal mode; i.e. the 16K RAM

is mapped to code space, and the MCU starts executing from location 0000h. Once the switch is done, the MCU sets

CONT = 1 (in the USBCTL register). This connects the device to the USB and results in normal USB device

enumeration.

4.1.3 WDCSR: Watchdog Timer, Control, and Status Register (Addr:FF93)

A watchdog timer (WDT) with 1-ms clock is provided. If this register is not accessed for a period of 128 ms, the WDT

counter resets the MCU. (see Figure 5–1). The watchdog timer is enabled by default and can be disabled by writing

a pattern of 101010 into the WDD[5:0] bits.

7

6

5

4

3

2

1

0

ROA

R/W

S1

S0

R3

R2

R1

R0

SDW

W/O

R/W

BIT

NAME

WDT

RESET

FUNCTION

0

5–1

6

0

MCU must write a 1 to this bit to prevent the WDT from resetting the MCU. If MCU does not write a 1

in a period of 128 ms, the WDT resets the device. Writing a 0 has no effect on the WDT. (WDT is a

7-bit counter using a 1-ms CLK). This bit is read as 0.

WDD[5:1]

WDR

00000

0

These bits are used to disable the watchdog timer. For the timer to be disabled these bits must be set

to 10101 and WDD[0] must also be set to 0. If any other pattern is present, the watchdog timer is in

operation.

Watchdog reset indication bit. This bit indicates if the reset occurred due to power-on reset or

watchdog timer reset.

WDR = 0

WDR = 1

A power-up reset occurred

A USB reset or watchdog time-out reset occurred. To clear this bit, the MCU must write a 1.

Writing a 0 has no effect.

7

WDD[0]

1

This bit is one of the disable bits for the watchdog timer. This bit must be cleared in order for the

watchdog timer to be disabled.

4.2 Buffers + I/O RAM Map

The address range from F800 to FFFF (2K bytes) is reserved for data buffers, setup packet, endpoint descriptors

block (EDB), and all I/O. There are 128 locations reserved for MMR (memory mapped registers). Table 4–2

represents the XDATA space allocation and access restriction for the DMA, UBM, and MCU.

Table 4–2. XDATA Space

DESCRIPTION

ADDRESS RANGE

UBM ACCESS

DMA ACCESS

MCU ACCESS

FFFF

↑

FF80

Internal MMRs

(Memory Mapped Registers)

No

Yes

(Only EDB-0)

(only Data reg. and EDB-0)

FF7F

↑

FF08

EDB

Only for EDB update

Yes

(Endpoint Descriptors Block)

FF07

↑

FF00

Setup Packet

Input Endpoint-0 Buffer

Output Endpoint-0 Buffer

Data Buffers

Yes

No

Yes

FEFF

↑

FEF8

FEF7

↑

FEF0

FEEF

↑

F800

4–3

Table 4–3. Memory Mapped Registers Summary (XDATA Range = FF80 → FFFF)

ADDRESS

FFFF

FFFE

FFFD

FFFC

FFFB

FFFA

FFF9

FFF8

FFF7

FFF6

FFF5

↑

REGISTER

FUNADR

DESCRIPTION

Function address register

USBSTA

USBMSK

USBCTL

MODECNFG

DEVVIDH

DEVVIDL

DEVPIDH

DEVPIDL

DEVREVH

DEVREVL

RESERVED

I2CADR

I2CDATI

I2CDATO

I2CSTA

USB status register

USB interrupt mask register

USB control register

Mode configuration register

Device custom VID high byte register

Device custom VID low byte register

Device custom PID high byte register

Device custom PID low byte register

Device custom revision number high byte register

Device custom revision number low byte register

2

I C-port address register

FFF3

FFF2

FFF1

FFF0

FFEF

FFEE

FFED

FFEC

FFEB

FFEA

FFE9

FFE8

↑

2

I C-port data input register

2

I C-port data output register

2

I C-port status register

SERNUM7

SERNUM6

SERNUM5

SERNUM4

SERNUM3

SERNUM2

SERNUM1

SERNUM0

RESERVED

DMACSR3

DMACDR3

RESERVED

DMACSR1

DMACDR1

RESERVED

MASK

Serial number byte 7 register

Serial number byte 6 register

Serial umber byte 5 register

Serial number byte 4 register

Serial number byte 3 register

Serial number byte 2 register

Serial number byte 1 register

Serial number byte 0 register

FFE5

FFE4

↑

DMA–3: Control and status register

DMA–3: Channel definition register

FFE1

FFE0

↑

DMA–1: Control and status register

DMA–1: Channel definition register

FFAB

FFAA

FFA9

FFA8

FFA7

FFA6

FFA5

FFA4

FFA3

FFA2

FFA1

FFA0

FF9E

UART: Interrupt mask register

UART: Xoff register

XOFF

XON

UART: Xon register

DLH

UART: Divisor high-byte register

UART: Divisor low-byte register

UART: Modem status register

UART: Line status register

UART: Modem control register

UART: Flow control register

UART: Line control registers

UART: Transmitter data registers

UART: Receiver data registers

GPIO: Pullup register for port 3

DLL

MSR

LSR

MCR

FCRL

LCR

TDR

RDR

PUR_3

4–4

Table 4–3. Memory Mapped Registers Summary (XDATA Range = FF80 → FFFF) (Continued)

ADDRESS

REGISTER

RESERVED

DESCRIPTION

↑

FF93

WDCSR

Watchdog timer control and status register

Vector interrupt register

FF92

↑

VECINT

RESERVED

ROMS

FF90

↑

ROM shadow configuration register

RESERVED

OEPBCNT_0

OEPCNFG_0

IEPBCNT_0

IEPCNFG_0

FF83

FF82

FF81

FF80

Output endpoint_0: Byte count register

Output endpoint_0: Configuration register

Input endpoint_0: Byte count register

Input endpoint_0: Configuration register

Table 4–4. EDB Memory Locations

ADDRESS

↑

REGISTER

RESERVED

IEPCNF_3

DESCRIPTION

FF58

FF50

FF48

FF47

↑

Input endpoint_3: Configuration

Input endpoint_2: Configuration

Input endpoint_1: Configuration

IEPCNF_2

IEPCNF_1

RESERVED

FF20

FF18

FF10

FF08

FF07

↑

OEPCNF_3

OEPCNF_2

OEPCNF_1

Output endpoint_3: Configuration

Output endpoint_2: Configuration

Output endpoint_1: Configuration

(8 bytes)

Setup packet block

FF00

FEFF

↑

Input endpoint-0 buffer

FEF8

FEF7

↑

(8 bytes)

Output endpoint-0 buffer

Top of buffer space

Buffer space

FEF0

FEEF

TOPBUFF

↑

F800

STABUFF

Start of buffer space

4.3 Endpoint Descriptor Block (EDB–1 to EDB–3)

Data transfers between the USB, the MCU, and external devices that are defined by an endpoint descriptor Block

(EDB). Three input- and three output-EDBs are provided. With the exception of EDB–0 (I/O endpoint–0), all EDBs

are located in SRAM as per Table 4–3. Each EDB contains information describing the X- and Y-buffers. In addition,

each EDB provides general status information.

Table 4–5 illustrates the EDB entries for EDB–1 to EDB–3. EDB–0 registers are described separately.

4–5

Table 4–5. EDB Entries in RAM (n = 1 to 3)

OFFSET

07

ENTRY NAME

EPSIZXY_n

EPBCTY_n

EPBBAY_n

SPARE

DESCRIPTION

I/O Endpoint_n: X/Y-buffer size

I/O Endpoint_n: Y-byte count

I/O Endpoint_n: Y-buffer base address

Not used

06

05

04

03

SPARE

Not used

02

EPBCTX_n

EPBBAX_n

EPCNF_n

I/O Endpoint_n: X-byte count

I/O Endpoint_n: X-buffer base address

I/O Endpoint_n: Configuration

01

00

4.3.1 OEPCNF_n: Output Endpoint Configuration (n = 1 to 3) (Addr:FF08, FF10, FF18)

7

6

5

4

3

2

1

0

UBME

R/W

ISO=0

R/W

TOGLE

R/W

DBUF

R/W

STALL

R/W

USBIE

R/W

RSV

R/W

RSV

R/W

BIT

NAME

RSV

RESET

FUNCTION

1–0

x

Reserved = 0

2

USBIE

USB interrupt enable on transaction completion. Set/cleared by the MCU

USBIE = 0 No interrupt

USBIE = 1 Interrupt on transaction completion

3

4

STALL

0

x

USB stall condition indication. Set/cleared by the MCU

STALL = 0 No stall

Stall = 1

USB stall condition. If set by the MCU, a STALL handshake is initiated and the bit is cleared

by the MCU.

DBUF

Double-buffer enable. Set/cleared by the MCU

DBUF = 0 Primary buffer only (X-buffer only)

DBUF = 1 Toggle bit selects buffer

5

6

TOGLE

ISO

x

USB toggle bit. This bit reflects the toggle sequence bit of DATA0, DATA1

ISO = 0 Nonisochronous transfer. This bit must be cleared by the MCU since only nonisochronous transfer

is supported

7

UBME

x

UBM enable/disable bit. Set/cleared by the MCU

UBME = 0 UBM cannot use this endpoint

UBME = 1 UBM can use this endpoint

4.3.2 OEPBBAX_n: Output Endpoint X-Buffer Base Address (n = 1 to 3)

7

6

5

4

3

2

1

0

A10

R/W

A9

A8

A7

A6

A5

A4

A3

R/W

BIT

7–0

NAME

RESET

FUNCTION

A[10:3]

x

A[10:3] of X-buffer base address (padded with 3 LSB of zeros for a total of 11 bits). This value is set by the

MCU. The UBM or DMA uses this value as the start-address of a given transaction. Note that the UBM or

DMA does not change this value at the end of a transaction.

4–6

4.3.3 OEPBCTX_n: Output Endpoint X Byte Count (n = 1 to 3)

7

6

5

4

3

2

1

0

NAK

R/W

C6

C5

C4

C3

C2

C1

C0

R/W

BIT

NAME

C[6:0]

RESET

x

FUNCTION

6–0

X-buffer byte count:

X000.0000b Count = 0

X000.0001b Count = 1 byte

:

X011.1111b Count = 63 bytes

X100.0000b Count = 64 bytes

Any value ≥ 100.0001b may result in unpredictable results.

NAK =0 No valid data in buffer. Ready for host OUT

NAK = 1 Buffer contains a valid packet from host (gives NAK response to Host OUT request)

7

NAK

x

4.3.4 OEPBBAY_n: Output Endpoint Y-Buffer Base Address (n = 1 to 3)

7

6

5

4

3

2

1

0

A10

R/W

A9

A8

A7

A6

A5

A4

A3

R/W

BIT

7–0

NAME

RESET

FUNCTION

A[10:3]

x

A[10:3] of Y-buffer base address (padded with 3 LSB of zeros for a total of 11 bits). This value is set by the

MCU. The UBM or DMA uses this value as the start-address of a given transaction. Furthermore, UBM or

DMA does not change this value at the end of a transaction.

4.3.5 OEPBCTY_n: Output Endpoint Y-Byte Count (n = 1 to 3)

7

6

5

4

3

2

1

0

NAK

R/W

C6

C5

C4

C3

C2

C1

C0

R/W

BIT

NAME

C[6:0]

RESET

x

FUNCTION

6–0

Y-byte count:

X000.0000b Count = 0

X000.0001b Count = 1 byte

:

X011.1111b Count = 63 bytes

X100.0000b Count = 64 bytes

Any value ≥ 100.0001b may result in unpredictable results.

NAK =0 No valid data in buffer. Ready for host OUT

NAK = 1 Buffer contains a valid packet from host (gives NAK response to Host OUT request)

7

NAK

x

4–7

4.3.6 OEPSIZXY_n: Output Endpoint X-/Y-Buffer Size (n =1 to 3)

7

6

5

4

3

2

1

0

RSV

R/W

S6

S5

S4

S3

S2

S1

S0

R/W

BIT

NAME

C[6:0]

RESET

x

FUNCTION

6–0

X- and Y-buffer size:

0000.0000b Size = 0

0000.0001b Size = 1 byte

:

0011.1111b Size = 63 bytes

0100.0000b Size = 64 bytes

Any value ≥ 100.0001b may result in unpredictable results.

7

RSV

x

Reserved = 0

4.3.7 IEPCNF_n: Input Endpoint Configuration (n = 1 to 3) (Addr:FF48, FF50, FF58)

7

6

5

4

3

2

1

0

UBME

R/W

ISO=0

R/W

TOGLE

R/W

DBUF

R/W

STALL

R/W

USBIE

R/W

RSV

R/W

RSV

R/W

BIT

NAME

RSV

RESET

FUNCTION

1–0

x

Reserved = 0

2

USBIE

USB interrupt enable on transaction completion

USBIE = 0 No interrupt

USBIE = 1 Interrupt on transaction completion

3

4

STALL

0

x

USB stall condition indication. Set by the UBM but can be set/cleared by the MCU

STALL = 0 No stall

STALL = 1 USB stall condition. If set by the MCU a STALL handshake is initiated and the bit is cleared

automatically.

DBUF

Double buffer enable

DBUF = 0 Primary buffer only (X-buffer only)

DBUF = 1 Toggle bit selects buffer

5

6

TOGLE

ISO

x

USB toggle bit. This bit reflects the toggle sequence bit of DATA0, DATA1

ISO = 0 Nonisochronous transfer. This bit must be cleared by the MCU since only nonisochronous

transfer is supported

7

UBME

x

UBM enable/disable bit. Set/cleared by the MCU

UBME = 0 UBM cannot use this endpoint

UBME = 1 UBM can use this endpoint

4.3.8 IEPBBAX_n: Input Endpoint X-buffer Base Address (n = 1 to 3)

7

6

5

4

3

2

1

0

A10

R/W

A9

A8

A7

A6

A5

A4

A3

R/W

BIT

7–0

NAME

RESET

FUNCTION

A[10:3]

x

A[10:3] of X-buffer base address (padded with 3 LSB of zeros for a total of 11 bits). This value is set by the

MCU. The UBM or DMA uses this value as the start-address of a given transaction, but note that the UBM

or DMA does not change this value at the end of a transaction.

4–8

4.3.9 IEPBCTX_n: Input Endpoint X-Byte Count (n = 1 to 3)

7

6

5

4

3

2

1

0

NAK

R/W

C6

C5

C4

C3

C2

C1

C0

R/W

BIT

NAME

C[6:0]

RESET

x

FUNCTION

6–0

X-Buffer byte count:

X000.0000b Count = 0

X000.0001b Count = 1 byte

:

X011.1111b Count = 63 bytes

X100.0000b Count = 64 bytes

Any value ≥ 100.0001b may result in unpredictable results.

7

NAK

x

NAK = 0 Buffer contains a valid packet for host-IN transaction

NAK = 1 Buffer is empty (gives NAK response to host-OUT request)

4.3.10 IEPBBAY_n: Input Endpoint Y-Buffer Base Address (n = 1 to 3)

7

6

5

4

3

2

1

0

A10

R/W

A9

A8

A7

A6

A5

A4

A3

R/W

BIT

7–0

NAME

RESET

FUNCTION

A[10:3]

x

A[10:3] of Y-buffer base address (padded with 3 LSB of zeros for a total of 11 bits). This value is set by the

MCU. The UBM or DMA uses this value as the start-address of a given transaction, but note that the UBM

or DMA does not change this value at the end of a transaction.

4.3.11 IEPBCTY_n: Input Endpoint Y-Byte Count (n = 1 to 3)

7

6

5

4

3

2

1

0

NAK

R/W

C6

C5

C4

C3

C2

C1

C0

R/W

BIT

NAME

C[6:0]

RESET

x

FUNCTION

6–0

Y-Byte count:

X000.0000b Count = 0

X000.0001b Count = 1 byte

:

X011.1111b Count = 63 bytes

X100.0000b Count = 64 bytes

Any value ≥ 100.0001b may result in unpredictable results.

NAK =0 Buffer contains a valid packet for host-IN transaction

NAK = 1 Buffer is empty (gives NAK response to host-IN request)

7

NAK

x

4–9

4.3.12 IEPSIZXY_n: Output Endpoint X-/Y-Buffer Size (n = 1 to 3)

7

6

5

4

3

2

1

0

RSV

R/W

S6

S5

S4

S3

S2

S1

S0

R/W

BIT

NAME

C[6:0]

RESET

x

FUNCTION

6–0

X- and Y-buffer size:

0000.0000b Size = 0

0000.0001b Size = 1 byte

:

0011.1111b Size = 63 bytes

0100.0000b Size = 64 bytes

Any value ≥ 100.0001b may result in unpredictable results.

7

RSV

x

Reserved = 0

4.4 Endpoint-0 Descriptor Registers

Unlike registers EDB–1 to EDB–3, which are defined as memory entries in SRAM, endpoint–0 is described by a set

of four registers (two for output and two for input). The registers and their respective addresses, used for EDB–0

description, are defined in Table 4–6. EDB–0 has no base-address register, since these addresses are hardwired into

FEF8 and FEF0. Note that the bit positions have been preserved to provide consistency with EDB–n (n = 1 to 3).

Table 4–6. Input/Output EDB-0 Registers

ADDRESS

REGISTER NAME

DESCRIPTION

BASE ADDRESS

FEF0

FF83

FF82

OEPBCNT_0

OEPCNFG_0

Output endpoint_0: Byte count register

Output endpoint_0: Configuration register

FF81

FF80

IEPBCNT_0

IEPCNFG_0

Output endpoint_0: Byte count register

Output endpoint_0: Configuration register

FEF8

4.4.1 IEPCNFG_0: Input Endpoint-0 Configuration Register (Addr:FF80)

7

6

5

4

3

2

1

0

UBME

R/W

RSV

R/O

TOGLE

R/O

RSV

R/O

STALL

R/W

USBIE

R/W

RSV

R/O

RSV

R/O

BIT

NAME

RSV

RESET

FUNCTION

1–0

0

Reserved = 0

2

USBIE

USB interrupt enable on transaction completion. Set/cleared by the MCU.

USBIE = 0 No interrupt

USBIE = 1 Interrupt on transaction completion

3

4

STALL

0

USB stall condition indication. Set/cleared by the MCU

STALL = 0 No stall

STALL = 1 USB stall condition. If set by the MCU a STALL handshake is initiated and the bit is cleared

automatically by the next setup transaction.

RSV

Double buffer enable

DBUF = 0 Primary buffer only (X-buffer only)

DBUF = 1 Toggle bit selects buffer

5

6

7

TOGLE

RSV

0

USB toggle bit. This bit reflects the toggle sequence bit of DATA0, DATA1.

Reserved = 0

UBME

UBM enable/disable bit. Set/cleared by the MCU

UBME = 0 UBM cannot use this endpoint

UBME = 1 UBM can use this endpoint

4.4.2 IEPBCNT_0: Input Endpoint-0 Byte Count Register (Addr:FF81)

7

6

5

4

3

2

1

0

4–10

NAK

RSV

C3

C2

C1

C0

R/W

R/O

R/W

BIT

NAME RESET

FUNCTION

3–0

C[3:0]

0h

Byte count:

0000b Count = 0

:

1111b Count = 7

1000b Count = 8

1001b to 1111b are reserved. (If used, they default to 8)

6–4

rsv

0

1

Reserved = 0

7

NAK

NAK =0

Buffer contains a valid packet for host-IN transaction

NAK = 1 Buffer is empty (gives NAK response to host-IN request)

4.4.3 OEPCNFG_0: Output Endpoint-0 Configuration Register (Addr:FF82)

7

6

5

4

3

2

1

0

UBME

R/W

RSV

R/O

TOGLE

R/O

RSV

R/O

STALL

R/W

USBIE

R/W

RSV

R/O

RSV

R/O

BIT

1–0

2

NAME RESET

FUNCTION

RSV

0

Reserved = 0

USBIE

USB interrupt enable on transaction completion. Set/cleared by the MCU.

USBIE = 0 No interrupt

USBIE = 1 Interrupt on transaction completion

3

STALL

0

USB stall condition indication. Set/cleared by the MCU

STALL = 0 No stall

STALL = 1 USB stall condition. If set by the MCU, a STALL handshake is initiated and the bit is cleared

automatically.

4

5

6

7

RSV

0

Reserved = 0

TOGLE

RSV

USB \toggle bit. This bit reflects the toggle sequence bit of DATA0, DATA1.

Reserved = 0

UBME

UBM enable/disable bit. Set/cleared by the MCU

UBME = 0 UBM cannot use this endpoint

UBME = 1 UBM can use this endpoint

4.4.4 OEPBCNT_0: Output Endpoint-0 Byte Count Register (Addr:FF83)

7

6

5

4

3

2

1

0

NAK

R/W

RSV

R/O

RSV

R/O

RSV

R/O

C3

C2

C1

C0

R/O

BIT

NAME RESET

FUNCTION

3–0

C[3:0]

0h

Byte count:

0000b Count = 0

:

1111b Count = 7

1000b Count = 8

1001b to 1111b are reserved

6–4

rsv

0

1

Reserved = 0

7

NAK

NAK =0

No valid data in buffer. Ready for host OUT

NAK = 1 Buffer contains a valid packet from host (gives NAK response to host-IN request).

4–11

4–12

5 USB

5.1 USB Registers

5.1.1 FUNADR: Function Address Register (Addr:FFFF)

This register contains the device function address.

7

6

5

4

3

2

1

0

RSV

R/O

FA6

R/W

FA5

R/W

FA4

R/W

FA3

R/W

FA2

R/W

FA1

R/W

FA0

R/W

BIT

NAME

RESET

FUNCTION

6–0

FA[6:0]

0

These bits define the current device address assigned to the function. The MCU writes a value to this

register because of the SET-ADDRESS host command.

7

RSV

0

Reserved = 0

5.1.2 USBSTA: USB Status Register (Addr:FFFE)

All bits in this register are set by the hardware and are cleared by the MCU when writing a 1 to the proper bit location

(writing a 0 has no effect). In addition, each bit can generate an interrupt if its corresponding mask bit is set (R/C

notation indicates read and clear only by the MCU).

7

6

5

4

3

2

1

0

RSTR

R/C

SUSR

R/C

RESR

R/C

RSV

R/O

URRI

R/C

SETUP

R/C

WAKEUP

R/C

STPOW

R/C

BIT

NAME

RESET

FUNCTION

0

STPOW

0

SETUP Overwrite bit. Set by hardware when setup packet is received while there is already a packet in

the setup buffer.

STPOW = 0

STPOW = 1

MCU can clear this bit by writing a 1 (writing 0 has no effect).

SETUP overwrite

1

2

WAKEUP

SETUP

0

Remote wakeup bit

WAKEUP = 0 The MCU can clear this bit by writing a 1 (writing 0 has no effect).

WAKEUP = 1 Remote wakeup request from WAKEUP pin

SETUP transaction received bit. As long as SETUP is 1, IN and OUT on endpoint–0 are NAKed,

regardless of their real NAK bits value.

SETUP = 0

SETUP = 1

MCU can clear this bit by writing a 1 (writing 0 has no effect).

SETUP transaction received

3

URRI

0

UART RI status bit – a rising edge causes this bit to be set.

URRI = 0

URRI = 1

URRI = 0 The MCU can clear this bit by writing a 1 (writing 0 has no effect).

URRI = 1 Ring detected, which is used to wake the chip up (bring it out of suspend).

4

5

RSV

0

Reserved

RESR

Function resume request bit

RESR = 0

RESR = 1

The MCU can clear this bit by writing a 1 (writing 0 has no effect).

Function resume is detected

6

7

SUSR

RSTR

0

Function suspended request bit. This bit is set in response to a global or selective suspend condition.

FSUSP = 0

FSUSP = 1

The MCU can clear this bit by writing a 1 (writing 0 has no effect).

Function suspend is detected

Function reset request bit. This bit is set in response to host initiating a port reset. This bit is not

affected by the USB function reset.

FRST = 0

FRST = 1

The MCU can clear this bit by writing a 1 (writing 0 has no effect).

Function reset is detected

5–1

5.1.3 USBMSK: USB Interrupt Mask Register (Addr:FFFD)

7

6

5

4

3

2

1

0

RSTR

R/W

SUSR

R/W

RESR

R/W

RSV

R/O

UR1RI

R/W

SETUP

R/W

WAKEUP

R/W

STPOW

R/W

BIT

NAME

RESET

FUNCTION

0

1

2

3

STPOW

0

SETUP overwrite interrupt-enable bit

STPOW = 0

STPOW = 1

STPOW interrupt disabled

STPOW interrupt enabled

WAKEUP

SETUP

UR1RI

Remote wakeup interrupt enable bit

WAKEUP = 0 WAKEUP interrupt disable

WAKEUP = 1 WAKEUP interrupt enable

SETUP interrupt enable bit

SETUP = 0

SETUP = 1

SETUP interrupt disabled

SETUP interrupt enabled

UART 1 R1 interrupt enable bit

URRI = 0

URRI = 1

UR1RI interrupt disable

UR1RI interrupt enable

4

5

RSV

0

Reserved

RESR

Function resume interrupt enable bit

RESR = 0

RESR = 1

Function resume interrupt disabled

Function resume interrupt enabled

6

7

SUSR

RSTR

0

Function suspend interrupt enable

FSUSP = 0

FSUSP = 1

Function suspend interrupt disabled

Function suspend interrupt enabled

Function reset interrupt bit. This bit is not affected by USB function reset.

FRST = 0

FRST = 1

Function reset interrupt disabled

Function reset interrupt enabled

5–2

5.1.4 USBCTL: USB Control Register (Addr:FFFC)

Unlike the rest of the registers, this register is cleared by the power-up reset signal only. The USB reset cannot reset

this register (see Figure 5–1).

7

6

5

4

3

2

1

0

R/W

R/O

R/W

R/O

R/W

BIT

NAME

DIR

RESET

0

As a response to a setup packet, the MCU decodes the request and sets/clears this bit to reflect the data transfer

direction.

DIR = 0

DIR = 1

USB data-OUT transaction (from host to TUSB3410)

USB data-IN transaction (from TUSB3410 to host)

1

SIR

0

SETUPinterrupt-statusbit. ThisbitiscontrolledbytheMCUtoindicatetothehardwarewhentheSETUPinterrupt

is being served.

SIR = 0

SIR = 1

SETUP interrupt is not served. The MCU clears this bit before exiting the SETUP interrupt routine.

SETUP interrupt is in progress. The MCU sets this bit when servicing the SETUP interrupt.

2

3

4

RSV

0

1

Reserved = 0

RSV

FRSTE

Function reset-connection bit. This bit connects/disconnects the USB function reset to/from the MCU reset.

FRSTE = 0 Function reset is not connected to MCU reset

FRSTE = 1 Function reset is connected to MCU reset

5

6

7

RWUP

IREN

0

Device remote wakeup request. This bit is set by the MCU and is cleared automatically.

RWUP = 0

RWUP = 1

Writing a 0 to this bit has no effect

When MCU writes a 1, a remote-wakeup pulse is generated.

IR mode enable. This bit is set and cleared by firmware.

IREN = 0

IREN = 1

IR encoder/decoder is disabled, UART mode is selected

IR encoder/decoder is enabled, UART mode is deselected

CONT

Connect/disconnect bit

CONT = 0

CONT = 1

Upstream port is disconnected. Pullup disabled.

Upstream port is connected. Pullup enabled.

5–3

5.1.5 MODECNFG: Mode Configuration Register (Addr:FFFB)

This register is cleared by the power-up reset signal only. The USB reset cannot reset this register.

7

6

5

4

3

2

1

0

RSV

R/O

RSV

R/O

RSV

R/O

RSV

R/O

CLKSLCT

R/W

CLKOUTEN

R/W

SOFTSW

R/W

TXCNTL

R/W

BIT

NAME

TXCNTL

RESET

FUNCTION

Transmit output control: Hardware or firmware switching select for 3-state serial output buffer.

0

1

2

3

0

TXCNTL = 0

TXCNTL = 1

Hardware automatic switching is selected

Firmware toggle switching is selected

SOFTSW

0

Soft switch: Firmware controllable 3-state output buffer enable for serial output pin.

SOFTSW = 0

SOFTSW = 1

Serial output buffer is enabled

Serial output buffer is disabled

CLKOUTEN

CLKSLCT

Clock output enable: Enable/disable the clock output at CLKOUT terminal.

CLKOUTEN = 0 Clock output is disabled. Device drives low at CLKOUT terminal.

CLKOUTEN = 1 Clock output is enabled

Clock output source select: Select between 3.556-MHz fixed clock or UART baud out clock as output

clock source.

CLKSLCT = 0

CLKSLCT = 1

UART baud out clock is selected as clock output

Fixed 3.556-MHz free running clock is selected as clock output

4–7

RSV

0

Reserved

Clock Output Control

The CLKOUTEN bit in the Mode Configuration Register (MODECNFG) is used to enable or disable the clock output

at the CLKOUT terminal of the TUSB3410. The power up default of CLKOUT is disabled to ensure the clock is not

applied to the smart card until it is powered. Firmware can write a 1 to enable the clock output if needed.

The CLKSLCT bit in the MODECNFG register is used to select the output clock source from either a fixed 3.556-MHz

free-running clock or the UART BaudOut clock.

5.1.6 Vendor ID/Product ID

USB–IF and Microsoft WHQL certification requires that end equipment makers use their own unique vendor ID and

product ID for each product (model). OEMs cannot use silicon vendor’s (for instance, TI’s default) VID/PID in their

end products. A unique VID/PID combination will avoid potential driver conflicts and enable logo certification. See

www.usb.org for more information.

5.1.7 SERNUM7: Device Serial Number Register (Byte 7) (Addr:FFEF)

Each TUSB3410 chip has a unique 64-bit serial die id number, which is generated during manufacturing. The die id

is incremented sequentially, however there is no assurance without skip in the die id number. The device serial

number register utilizes (mirrors) this unique 64-bit serial die id number.

After power-up reset, this read-only register (SERNUM7) contains the most significant byte (byte 7) of the complete

64-bit device serial number. The USB reset cannot reset this register.

7

6

5

4

3

2

1

0

D63

R/O

D62

R/O

D61

R/O

D60

R/O

D59

R/O

D58

R/O

D57

R/O

D56

R/O

BIT

7–0

NAME

D[7:0]

RESET

Device serial number byte 7 value

FUNCTION

Device serial number byte 7 value

5–4

Procedure to load device serial number value in shared RAM:

•

After power-up reset, boot code copies the predefined USB descriptors to shared RAM. As a result, the

default serial number hard-coded in the boot code (0x00 hex) is copied to the shared RAM data space.

•

Once the boot code finishes copying descriptors, it performs a read to the SERNUM7 to SERNUM0

registers and overwrites the device serial number value stored in the shared RAM with the one found in the

SERNUM7 to SERNUM0 registers.

•

Once the boot code finishes the read to SERNUM7 – SERNUM0 registers, it then checks if EEPROM is

present on the I C port. If the EEPROM is present and contains a valid device serial number as part of the

USB device descriptor information stored in EEPROM, the boot code overwrites the serial number value

stored in shared RAM with the one found in EEPROM. Otherwise, the device serial number value stored

in shared RAM stays unchanged from previous step.

2

In summary, the serial number value in external EEPROM has the highest priority to be loaded into shared

RAM data space. The serial number value stored in shared RAM is used as part of the valid device

descriptor information during normal operation.

5.1.8 SERNUM6: Device Serial Number Register (Byte 6) (Addr:FFEE)

The device serial number register utilizes (mirrors) this unique 64-bit serial die id number.

After power-up reset, this read-only register (SERNUM6) contains byte 6 of the complete 64-bit device serial number.

The USB reset cannot reset this register.

7

6

5

4

3

2

1

0

D55

R/O

D54

R/O

D53

R/O

D52

R/O

D51

R/O

D50

R/O

D49

R/O

D48

R/O

BIT

7–0

NAME

D[7:0]

RESET

Device serial number byte 6 value

FUNCTION

Device serial number byte 6 value

NOTE: See the same procedure described in SERNUM7 register for procedure to load device serial number into the shared RAM.

5.1.9 SERNUM5: Device Serial Number Register (Byte 5) (Addr:FFED)

The device serial number register utilizes (mirrors) this unique 64-bit serial die id number.

After power-up reset, this read-only register (SERNUM5) contains byte 5 of the complete 64-bit device serial number.

The USB reset cannot reset this register.

7

6

5

4

3

2

1

0

D47

R/O

D46

R/O

D45

R/O

D44

R/O

D43

R/O

D42

R/O

D41

R/O

D40

R/O

BIT

7–0

NOTE: See the same procedure described in SERNUM7 register for procedure to load device serial number into the shared RAM.

NAME

RESET

FUNCTION

D[7:0]

Device serial number byte 5 value

5–5

5.1.10 SERNUM4: Device Serial Number Register (Byte 4) (Addr:FFEC)

The device serial number register utilizes (mirrors) this unique 64-bit serial die id number.

After power-up reset, this read-only register (SERNUM4) contains byte 4 of the complete 64-bit device serial number.

The USB reset cannot reset this register.

7

6

5

4

3

2

1

0

D39

R/O

D38

R/O

D37

R/O

D36

R/O

D35

R/O

D34

R/O

D33

R/O

D32

R/O

BIT

7–0

NAME

D[7:0]

RESET

Device serial number byte 4 value

FUNCTION

Device serial number byte 4 value

NOTE: See the same procedure described in SERNUM7 register for procedure to load device serial number into the shared RAM.

5.1.11 SERNUM3: Device Serial Number Register (Byte 3) (Addr:FFEB)

The device serial number register utilizes (mirrors) this unique 64-bit serial die id number.

After power-up reset, this read-only register (SERNUM3) contains byte 3 of the complete 64-bit device serial number.

The USB reset cannot reset this register.

7

6

5

4

3

2

1

0

D31

R/O

D30

R/O

D29

R/O

D28

R/O

D27

R/O

D26

R/O

D25

R/O

D24

R/O

BIT

7–0

NAME

D[7:0]

RESET

Device serial number byte 3 value

FUNCTION

Device serial number byte 3 value

NOTE: See the same procedure described in SERNUM7 register for procedure to load device serial number into the shared RAM.

5.1.12 SERNUM2: Device Serial Number Register (Byte 2) (Addr:FFEA)

The device serial number register utilizes (mirrors) this unique 64-bit serial die id number.

After power-up reset, this read-only register (SERNUM2) contains byte 2 of the complete 64-bit device serial number.

The USB reset cannot reset this register.

7

6

5

4

3

2

1

0

D23

R/O

D22

R/O

D21

R/O

D20

R/O

D19

R/O

D18

R/O

D17

R/O

D16

R/O

BIT

7–0

NAME

D[7:0]

RESET

FUNCTION

Device serial number byte 2 value

0

NOTE: See the same procedure described in SERNUM7 register for procedure to load device serial number into the shared RAM.

5.1.13 SERNUM1: Device Serial Number Register (Byte 1) (Addr:FFE9)

The device serial number register utilizes (mirrors) this unique 64-bit serial die id number.

After power-up reset, this read-only register (SERNUM1) contains byte 1 of the complete 64-bit device serial number.

The USB reset cannot reset this register.

7

6

5

4

3

2

1

0

D15

R/O

D14

R/O

D13

R/O

D12

R/O

D11

R/O

D10

R/O

D9

D8

R/O

BIT

7–0

NOTE: See the same procedure described in SERNUM7 register for procedure to load device serial number into the shared RAM.

NAME

RESET

FUNCTION

D[7:0]

Device serial number byte 1 value

5–6

5.1.14 SERNUM0: Device Serial Number Register (Byte 0) (Addr:FFE8)

The device serial number register utilizes (mirrors) this unique 64-bit serial die id number.

After power-up reset, this read-only register (SERNUM0) contains byte 0 of the complete 64-bit device serial number.

The USB reset cannot reset this register.

7

6

5

4

3

2

1

0

D7

D6

D5

D4

D3

D2

D1

D0

R/O

BIT

7–0

NAME

D[7:0]

RESET

Device serial number byte 0 value

FUNCTION

Device serial number byte 0 value

NOTE: See the same procedure described in SERNUM7 register for procedure to load device serial number into the shared RAM.

5.1.15 Function Reset And Power-Up Reset Interconnect

Figure 5–1 represents the logical connection of the USB-function reset (USBR) and power-up reset (RESET) pins.

The internal RESET signal is generated from the RESET pin (PURS signal) or from the USB reset (USBR signal).

The USBR can be enabled or disabled by the FRSTE bit in the USBCTL register (on power up, FRSTE = 0). The

internal RESET is used to reset all registers and logic, with the exception of the USBCTL and GLOBCTL registers

which are cleared by the PURS signal only.

USBCTL Register

To Internal MMRs

GLOBCTL Register

MCU

RESET

PURS

USBR

RESET

USB Function Reset

G2

FRSTE

WDT Reset

WDD[4:0]

Figure 5–1. Reset Diagram

5–7

5.1.16 Pullup Resistor Connect/Disconnect

The TUSB3410 enumeration can be activated by the MCU (there is no need to disconnect the cable physically).

Figure 5–2 represents the implementation of the TUSB3410 connect and disconnect from a USB up-stream port.

When CONT = 1 in the USBCTL register, the CMOS driver sources VDD to the pullup resistor (PUR pin) presenting

a normal connect condition to the USB hub (high speed). When CONT = 0, the PUR pin is driven low. In this state,

the 1.5-kΩ resistor is connected to GND, resulting in the device disconnection state. The PUR driver is a CMOS driver

that can provide (VDD – 0.1 V) minimum at 8-mA source current.

CMOS

PUR

CONT-Bit

1.5 kΩ

D+

DP0

DM0

D–

15 kΩ

HUB

TUSB3410

Figure 5–2. Pullup Resistor Connect/Disconnect Circuit

5–8

6 DMA Controller

Table 6–1 outlines the DMA channels and their associated transfer directions. Two channels are provided for data

transfer between the host and the UART.

Table 6–1. DMA Controller Registers

DMA CHANNEL

DMA–1

TRANSFER DIRECTION

Host to UART

COMMENTS

DMA writes to UART TDR register

DMA reads from UART RDR register

DMA–3

UART to host

6.1 DMA Controller Registers

Each DMA channel can point to one of three EDBs (EDB[3:1]) and transfer data to/from the UART channel. The DMA

can move data from a given out-point buffer (defined by EDB) to the destination port. Similarly, the DMA can move

data from a port to a given input-endpoint buffer. Two modes of DMA transfers are supported: burst and continuous.

•

Burst (CNT = 0) Mode

The DMA stops at the end of a block-data transfer (or if an error condition occurred) and interrupts the MCU.

It is the responsibility of the MCU to update the X/Y bit and the NAK bit in the EDB.

•

Continuous (CNT = 1) Mode

At the end of a block transfer the DMA updates the byte count and NAK bit in the EDB when receiving. In

addition, it uses the X/Y bit to switch automatically, without interrupting the MCU (the X/Y bit toggle is

performed by the UBM). The DMA stops only when a time-out or error condition occurs. When the DMA is

transmitting (from the X/Y buffer) it continues alternating between X/Y buffers until it detects a byte count

smallerthanthebuffersize(buffersizeistypically64bytes). Atthatpointitcompletesthetransferandstops.

6–1

6.1.1 DMACDR1: DMA Channel Definition Register (UART Transmit Channel) (Addr:FFE0)

These registers are used to define the EDB number that the DMA uses for data transfer to the UARTS. In addition,

these registers define the data transfer direction and selects X or Y as the transaction buffer.

7

6

5

4

3

2

1

0

EN

R/W

INE

R/W

CNT

R/W

XY

T/R

R/O

E2

E1

E0

R/W

BIT NAME RESET

FUNCTION

2–0 E[2:0]

0

Endpoint descriptor pointer. This field points to a set of EDB registers that is to be used for a given transfer.

3

T/R

This bit is always zero, indicating that the DMA data transfer is from SRAM to the UART TDR register. (The MCU

cannot change this bit.)

4

XY

0

X/Y buffer select bit. Valid only when CNT = 0

XY = 0

XY = 1

Next buffer to transmit/receive is the X buffer

Next buffer to transmit/receive is the Y buffer

5

CNT

DMA continuous transfer control bit. This bit defines the mode of the DMA transfer.

CNT = 0 Burst mode: The DMA stops the transfer when the byte count is zero or when a partial packet has been

received (byte count < 64). At the end of transfer, the high-to-low transition of EN interrupts the MCU (if

enabled). In this mode, the X/Y bit is set by the MCU to define the current buffer (X or Y).

CNT = 1 Continuous mode: In this mode, the DMA and UBM alternate between the X- and Y-buffers. The DMA

sets the X/Y bit and the UBM uses it for the transfer. The DMA alternates between the X-/Y-buffers and

continues transmitting (from X-/Y-buffer) without MCU intervention. The DMA terminates, and interrupts

the MCU, under the following conditions:

1. When the UBM byte count < buffer size (in EDB), the DMA transfers the partial packet and interrupt

the MCU on completion.

2. Transaction timer expires. The DMA interrupts the MCU.

6

7

INE

EN

0

DMA Interrupt enable/disable bit. This bit is used to enable/disable the interrupt on transfer completion.

INE = 0

INE = 1

Interrupt is disabled. In addition, PPKT and TXFT do not clear the EN-bit and the DMAC is not disabled.

Enables the EN interrupt. When this bit is set, the DMA interrupts the MCU on a 1 to 0 transition of the

EN bit. (When transfer is completed, EN = 0)

DMA channel enable bit. The MCU sets this bit to start the DMA transfer. When the transfer completes, or when it

is terminated due to error, this bit is cleared. The 1 to 0 transition of this bit generates an interrupt (if interrupt is

enabled).

EN = 0

DMAishalted. TheDMAishaltedwhenthebytecountreacheszeroortransactiontime-outoccurs. When

halted, the DMA updates the byte count, sets NAK = 0 in OEDB, and interrupts the MCU (if INE = 1).

EN = 1

Setting this bit starts the DMA transfer.

6–2

6.1.2 DMACSR1: DMA Control And Status Register (UART Transmit Channel) (Addr:FFE1)

This register is used to define the transaction time-out value. In addition, it contains a completion code that reports

any errors or a time-out condition.

7

6

5

4

3

2

1

0

TEN

R/W

C4

C3

C2

C1

C0

TXFT

R/C

PPKT

R/C

R/W

BIT

NAME RESET

FUNCTION

Partial packet condition bit. This bit is set by the DMA and cleared by the MCU (see Table 6–2).

0

PPKT

TXFT

C[4:0]

0

PPKT = 0

PPKT = 1

No partial-packet condition

Partial-packet condition detected. When IEN = 0, this bit does not clear the EN bit in DMACDR;

therefore, the DMAC stays enabled, ready for the next transaction. Clears when MCU writes a 1.

Writing a 0 has no effect.

1

Transfer time-out condition (see Table 6–2)

TXFT = 0

TXFT = 1

DMA stopped transfer without time-out

DMA stopped due to transaction time-out. When IEN = 0, this bit does not clear the EN bit in

DMACDR; therefore, the DMAC stays enabled, ready for the next transaction. DMA clears when

the MCU writes a 1. Writing a 0 has no effect.

6–2

This field is used to define the transaction time-out value in 1-ms increments. This value is loaded to a down

counter every time a byte transfer occurs. The down counter is decremented every SOF pulse (1 ms). If the

counter decrements to zero it sets TXFT = 1 (in DMACSR register) and halts the DMA transfer. The counter starts

counting only when TEN = 1 and EN = 1 (in DMACDR) and the first byte has been transmitted (see Figure 6–1).

00000 = 0-ms time-out

:

11111 = 31-ms time-out

7

TEN

0

Transaction time-out counter enable/disable bit.

TEN = 0

TEN = 1

Counter is disabled (does not time-out)

Counter is enabled

Table 6–2. DMA OUT-Termination Condition

OUT TERMINATION

UART partial packet

UART time-out

TXFT

PPKT

COMMENTS

0

1

0

This condition occurs when the host sends a partial packet.

This condition occurs when X- and Y-output buffers are full and the UART transmitter cannot

transmit (due to flow-control restriction) or if host has no data to transmit.

C[4:0]

SOF

TEN

EN

Counter

Load

TXFT

Figure 6–1. Transaction Time-Out Diagram

6–3

6.1.3 DMACDR3: DMA Channel Definition Register (UART Receive Channel) (Addr:FFE4)

These registers are used to define the EDB number that the DMA uses for data transfer from the UARTS. In addition,

these registers define the data transfer direction and selects X or Y as the transaction buffer.

7

6

5

4

3

2

1

0

EN

R/W

INE

R/W

CNT

R/W

XY

T/R

R/O

E2

E1

E0

R/W

BIT

NAME

E[2:0]

RESET

FUNCTION

2–0

0

1

Endpoint descriptor pointer. This field points to a set of EDB registers that are used for a given transfer.

3

T/R

This bit is always 1. This indicates that the DMA data transfer is from UART RDR register to SRAM.

(The MCU cannot change this bit.)

4

5

XY

0

XY Buffer select bit. Valid only when CNT = 0.

XY = 0

XY = 1

Next buffer to transmit/receive is X

Next buffer to transmit/receive is Y

CNT

DMA continuous transfer control bit. This bit defines the mode of the DMA transfer.

CNT = 0 Burst mode: DMA stops the transfer when the byte count = 0 or when a receiver error occurs.

At the end of transfer, the high-to-low transition of EN interrupts the MCU (if enabled). In this

mode, the XY bit is set by the MCU to define the current buffer (X or Y).

CNT = 1 Continuous mode: In this mode, the DMA and UBM alternate between the X- and Y-buffers.

The UBM sets the XY bit and the DMA uses it for the transfer. The DMA alternates between

the X-/Y-buffers and continues receiving (to X-/Y-buffer) without MCU intervention. The DMA

terminates the transfer and interrupts the MCU, under the following conditions:

1. Transaction time-out expired: DMA updates EDB and interrupts the MCU. UBM transfers

the partial packet to the host.

2. UART receiver error condition: DMA updates EDB and does not interrupt the MCU. UBM

transfers the partial packet to the host.

6

7

INE

EN

0

DMA interrupt enable/disable bit. This bit is used to enable/disable the interrupt on transfer completion.

INE = 0

Interrupt is disabled. In addition, OVRUN and TXFT do not clear the EN bit and the DMAX is

not disabled.

INE = 1

Enables the EN interrupt. When this bit is set, the DMA interrupts the MCU on a 1 to 0 transition

of the EN bit. (When transfer is completed, EN = 0).

DMA channel enable bit. The MCU sets this bit to start the DMA transfer. When transfer completes, or

when terminated due to error, this bit is cleared. The 1 to 0 transition of this bit generates an interrupt (if

interrupt is enabled).

EN = 0

DMA is halted. The DMA is halted when transaction time-out occurs, or under a UART

receiver-error condition. When halted, the DMA updates the byte count and sets NAK = 0 in

IEDB. If the termination is due to transaction time-out, the DMA generates an interrupt.

However, if the termination is due to a UART error condition, the DMA does not generate an

interrupt. (The UART generates the interrupt.)

EN = 1

Setting this bit starts the DMA transfer.

6–4

6.1.4 DMACSR3: DMA Control And Status Register (UART Receive Channel) (Addr:FFE5)

This register is used to define the transaction time-out value. In addition, it contains a completion code that reports

any errors or a time-out condition.

7

6

5

4

3

2

1

0

TEN

R/W

C4

C3

C2

C1

C0

TXFT

R/C

OVRUN

R/C

R/W

BIT

NAME

RESET

FUNCTION

0

OVRUN

0

Overrun condition bit. This bit is set by DMA and cleared by the MCU (see Table 6–3)

OVRUN = 0 No overrun condition

OVRUN = 1 Overrun condition detected. When IEN = 0, this bit does not clear the EN bit in DMACDR;

therefore, the DMAC stays enabled, ready for the next transaction. Clears when the MCU writes

a 1. Writing a 0 has no effect.

1

TXFT

C[4:0]

0

Transfer time-out condition bit (see Table 6–3)

TXFT = 0

TXFT =1

DMA stopped transfer without time-out

DMA stopped due to transaction time-out. When IEN = 0, this bit does not clear the EN bit in

DMACDR; therefore, the DMAC stays enabled, ready for the next transaction. Clears when the

MCU writes a 1. Writing a 0 has no effect.

6–2

00000b This field is used to define the transaction time-out value in 1-ms increments. This value is loaded to a down

counter every time a byte transfer occurs. The down counter is decremented every SOF pulse (1 ms). If the

counterdecrementstozeroitsetsTXFT=1(inDMACSRregister)andhaltstheDMAtransfer.Thecounterstarts

counting only when TEN = 1 and EN = 1 (in DMACDR) and the first byte has been received (see Figure 6–1).

00000 = 0-ms time-out

:

11111 = 31-ms time-out

7

TEN

0

Transaction time-out counter enable/disable bit

TEN = 0

TEN = 1

Counter is disabled (does not time-out)

Counter is enabled

Table 6–3. DMA IN-Termination Condition

IN TERMINATION

UART error

TXFT

OVRUN

COMMENTS

0

1

0

UART error condition detected

UART partial packet

0

This condition occurs when UART receiver has no more data for the host (data

starvation).

UART overrun

1

This condition occurs when X- and Y-input buffers are full and the UART FIFO is full (host

is busy).

6.2 Bulk Data I/O Using the EDB

The UBM (USB buffer manager) and the DMAC (DMA controller) access the EDB to fetch buffer parameters for IN

and OUT transactions (IN and OUT are with respect to host). In this discussion, it is assumed that (a) the MCU

initialized the EDBs, (b) DMA-continuous mode is being used, (c) double buffering is being used, and (d) the X/Y

toggle is controlled by the UBM.

NOTE: The IN and OUT transfers apply to UART.

6.2.1 IN Transaction (TUSB3410 to Host)

1. The MCU initializes the IEDB (64-byte packet, and double buffering is used) and the following DMA

registers:

•

DMACSR: Defines the transaction time-out value.

DMACDR: Defines the IEDB being used and the DMA mode of operation (continuous mode). Once this

register is set with EN = 1, the transfer starts.

6–5

2. The DMA transfers data from the UART to the X buffer. When a block of 64 bytes is transferred, the DMA

updates the byte count and sets NAK = 0 in IEDB (indicating to the UBM that the X buffer is ready to be

transferred to host). The UBM starts X-buffer transfer to host using the byte-count value in IEDB and toggles

the X/Y bit. The DMA continues transferring data from a device to Y-buffer. At the end of the block transfer,

the DMA updates the byte count and sets NAK = 0 in IEDB (indicating to the UBM that the Y-buffer is ready

to be transferred to host). The DMA continues the transfer from the device to host, alternating between

X-and Y-buffers without MCU intervention.

3. Transfer termination: As mentioned, the DMA/UBM continues the data transfer, alternating between the X-

and Y-buffers. Termination of the transfer can happen under the following conditions:

•

Stop Transfer: The host notifies the MCU (via control-end-point) to stop the transfer. Under this

condition, the MCU sets EN = 0 in the DMACDR register.

•

Partial Packet: The device receiver has no data to be transferred to host. Under this condition, the

byte-count value is less than 64 when the transaction timer time-out occurs. When the DMA detects this

condition, it sets TXFT = 1 and OVRUN = 0, updates the byte count and NAK bit (partial packet) in the

IEDB, and interrupts the MCU. UBM transfers the partial packet to host.

•

Buffer Overrun: The host is busy, X- and Y-buffers are full (X NAK = 0 and Y–NAK = 0) and the DMA

cannot write to these buffers. The transaction time-out stops the DMA transfer, the DMA sets TXFT = 1

and OVRUN = 1, and interrupts the MCU.

UART Error Condition: When receiving from a UART, a receiver-error condition stops the DMA and

sets TXFT = 1 and OVRUN = 0, but the EN bit remains set at 1. Therefore, the DMA does not interrupt

the MCU. However, the UART generates a status interrupt, notifying the MCU that an error condition

has occurred.

6.2.2 OUT Transaction (Host to TUSB3410)

1. The MCU initializes the OEDB (64-byte packet, and double buffering is used) and the following DMA

registers:

•

DMACSR: Defines the transaction time-out value.

DMACDR: Defines the OEDB being used, and the DMA mode of operation (continuous mode). Once

the EN bit is set to 1 in this register, the transfer starts.

2. The UBM transfers data from host to X-buffer. When a block of 64 bytes is transferred, the UBM updates

the byte count and sets NAK = 1 in OEDB (indicating to DMA that the X-buffer is ready to be transferred

to the UART). The DMA starts X-buffer transfer using the byte-count value in OEDB. The UBM continues

transferring data from host to Y-buffer. At the end of the block transfer, the UBM updates the byte count and

sets NAK = 1 in OEDB (indicating to DMA that the Y-buffer is ready to be transferred to device). The DMA

continuesthetransferfromtheX-/Y-bufferstothedevice, alternatingbetweenX-andY-bufferswithoutMCU

intervention.

3. Transfer termination: The DMA/UBM continues the data transfer alternating between X- and Y-buffers. The

termination of the transfer can happen under the following conditions:

•

Stop Transfer: The host notifies the MCU (via control-end point) to stop the transfer. Under this

condition, the MCU sets EN = 0 in the DMACDR register.

•

Partial-Packet: UBM receives a partial packet from host. Under this condition, the byte-count value is

less than 64 and the transaction timer does not time-out. When the DMA detects this condition, it

transfers the partial packet to the device, sets TXFT = 0 and PPKT = 1, updates NAK = 0 in OEDB, and

interrupts the MCU.

•

Time-out: The device is busy, X- and Y-buffers are full (X-NAK = 1 and Y-NAK = 1) and the UBM cannot

write to these buffers. Under this condition the transaction timer time-out stops the DMA transfer, sets

TXFT = 1 and OVRUN = 0, and interrupts the MCU.

6–6

7 UART

7.1 UART Registers

Table 7–1 summarizes the UART registers. These registers are used for data I/O, control, and status information.

UART setup is done by the MCU. Data transfer is typically performed by the DMAC. However, the MCU can perform

data transfer without DMA; this is useful when debugging the firmware.

Table 7–1. UART Registers Summary

REGISTER NAME

RDR

ACCESS

R/O

FUNCTION

UART receiver data register

UART transmitter data register

UART line control register

UART flow control register

UART modem control register

UART line status register

UART modem status register

UART divisor register (low byte)

UART divisor register (high byte)

UART Xon register

COMMENTS

Can be accessed by MCU or DMA

TDR

W/O

R/W

R/O

LCR

FCRL

MCR

LSR

Can generate an interrupt

MSR

R/O

DLL

R/W

DLH

XON

XOFF

MASK

UART Xoff register

UART interrupt mask register

Can control three interrupt sources

7.1.1 RDR: Receiver Data Register (Addr:FFA0)

The receiver data register consists of a 32-byte FIFO. Data received from the SIN pin are converted from

serial-to-parallel format and stored in this FIFO. Data transfer from this register to the RAM buffer is the responsibility

of the DMA controller.

7

6

5

4

3

2

1

0

D7

D6

D5

D4

D3

D2

D1

D0

R/O

BIT

7–0

NAME

D[7:0]

RESET

FUNCTION

0

Receiver byte

7.1.2 TDR: Transmitter Data Register (Addr:FFA1)

The transmitter data register is double buffered. Data written to this register is loaded into the shift register, and shifted

out on SOUT. Data transfer from the RAM buffer to this register is the responsibility of the DMA controller.

7

6

5

4

3

2

1

0

D7

D6

D5

D4

D3

D2

D1

D0

W/O

BIT

7–0

NAME

D[7:0]

RESET

FUNCTION

0

Transmit byte

7–1

7.1.3 LCR: Line Control Register (Addr:FFA2)

This register controls the data communication format. The word length, number of stop bits, and parity type are

selected by writing the appropriate bits to the LCR.

7

6

5

4

3

2

1

0

FEN

R/W

BRK

R/W

FPTY

R/W

EPRTY

R/W

PRTY

R/W

STP

R/W

WL1

R/W

WL0

R/W

BIT

NAME

RESET

FUNCTION

1:0

WL{1–0]

0

Specifies the word length for transmit and receive

00b = 5 bits

01b = 6 bits

10b = 7 bits

11b = 8 bits

2

STP

0

Specifies the number of stop bits for transmit and receive

STP = 0

STP = 1

1 stop bit (word length = 5, 6, 7, 8)

1.5 stop bits (word length = 5)

2 stop bits (word length = 6, 7, 8)

3

4

5

6

7

PRTY

EPRTY

FPTY

BRK

0

Specifies whether parity is used

PRTY = 0

PRTY = 1

No parity

Parity is generated

Specifies whether even or odd parity is generated

EPRTY = 0 Odd parity is generated (if PRTY = 1)

EPRTY = 1 Even parity is generated (if PRTY = 1)

Selects the forced parity bit

FPTY = 0

FPTY = 1

Parity is not forced

Parity bit is forced. If [EPRTY = 0], the parity bit is forced to 1

This bit is the break-control bit

BRK = 0

BRK = 1

Normal operation

Forces SOUT into break condition (logic 0)

FEN

FIFO enable. This bit is used to disable/enable the FIFO. To reset the FIFO, the MCU clears and then sets

this bit.

FEN = 0

FEN = 1

The FIFO is cleared and disabled. When disabled the selected receiver flow control is activated.

The FIFO is enabled and it can receive data.

7–2

7.1.4 FCRL: UART Flow Control Register (Addr:FFA3)

This register provides the flow-control modes of operation (see Table 7–3 for more details).

7

6

5

4

3

2

1

0

485E

R/W

DTR

R/W

RTS

R/W

RXOF

R/W

DSR

R/W

CTS

R/W

TXOA

R/W

TXOF

R/W

BIT

NAME RESET

FUNCTION

This bit controls the transmitter Xon/Xoff flow control.

0

1

2

TXOF

TXOA

CTS

0

TXOF = 0

TXOF = 1

Disable transmitter Xon/Xoff flow control

Enable transmitter Xon/Xoff flow control

This bit controls the transmitter Xon-on-any/Xoff flow control

TXOA = 0

TXOA = 1

Disable the transmitter Xon-on-any/Xoff flow control

Enable the transmitter Xon-on-any/Xoff flow control

Transmitter CTS flow-control enable bit

CTS = 0

CTS = 1

Disables transmitter CTS flow control

CTS flow control is enabled, i.e., when CTS input pin is high, transmission is halted; when the CTS

pin is low, transmission resumes.

3

DSR

0

Transmitter DSR flow-control enable bit

DSR = 0

DSR = 1

Disables transmitter DSR flow control

DSR flow control is enabled, i.e., when DSR input pin is high, transmission is halted; when the DSR

pin is low, transmission resumes.

4

5

RXOF

RTS

0

This bit controls the receiver Xon/Xoff flow control.

RXOF = 0

RXOF = 1

Receiver does not attempt to match Xon/Xoff characters

Receiver searches for Xon/Xoff characters

Receiver RTS flow control enable bit

RTS = 0

RTS = 1

Disables receiver RTS flow control

Receiver RTS flow control is enabled. RTS output pin goes high when the receiver FIFO HALT

trigger level is reached; it goes low, when the receiver FIFO RESUME receiving trigger level is

reached.

6

7

DTR

0

Receiver DTR flow-control enable bit

DTR = 0

DTR = 1

Disables receiver DTR flow control

Receiver DTR flow control is enabled. DTR output pin goes high when the receiver FIFO HALT

trigger level is reached; it goes low, when the receiver FIFO RESUME receiving trigger level is

reached.

485E

RS485 enable bit. This bit is used to configure the UART to control external RS485 transceivers. When

configured in half-duplex mode (485E=1), RTS or DTR can be used to enable the RS485 driver or receiver.

See Figure 5.

485E = 0

485E = 1

UART is in normal operation mode (full duplex)

The UART is in half duplex RS485 mode. In this mode RTS and DTR are active with opposite

polarity (when RTS = 0, DTR = 1). When the DMA is ready to transmit, it drives RTS = 1 (and

DTR = 0) 2–bit–time before transmission starts. When DMA terminates the transmission, it drives

RTS = 0 (and DTR = 1) after transmission stops. When 485E is set to 1, the DTR and RTS bits in

the MCR register have no effect. Also, see the RCVE bit in MCR: modem-control register.

7–3

7.1.5 Transmitter Flow Control

On reset (power up, USB or soft reset) the transmitter defaults to the Xon state and the flow control is set to mode–0

(flow control is disabled).

Table 7–2. Transmitter Flow-Control Modes

3

DSR

0

2

CTS

0

1

0

MODE

TXOA

TXOF

0

1

All flow control is disabled

Xon/Xoff flow control is enabled

Xon on any/ Xoff flow control

Not permissible (see Note 1)

CTS flow control

0

1

0

1

0

1

0

1

0

1

0

2

0

3

X

4

0

1

5

Combination flow control (see Note 2)

Combination flow control

DSR flow control

0

1

6

0

1

7

1

0

9-E

Combination flow control

NOTES: 1. This is a nonpermissible combination. If used, TXOA and TXOF are cleared.

2. Combination example: Transmitter stops when either CTS or Xoff is detected. Transmitter resumes when both CTS is negated and

Xon is detected.

Table 7–3. Receiver Flow-Control Possibilities

6

DTR

0

5

RTS

0

4

MODE

RXOF

0

1

2

3

4

5

6

7

All flow control is disabled

Xon/Xoff flow control is enabled

RTS flow control

0

1

0

1

0

1

0

1

0

1

Combination flow control (see Note 3)

DTR flow control

0

1

0

Combination flow control

Combination flow control (see Note 4)

Combination flow control

1

0

1

NOTES: 3. Combination example: Both RTS is asserted and Xoff transmitted when FIFO is full. Both RTS is deasserted and Xon is transmitted

when FIFO is empty.

4. Combination example: Both DTR and RTS are asserted when FIFO is full. Both DTR and RTS are deasserted when FIFO is empty.

7–4

7.1.6 MCR: Modem-Control Register (Addr:FFA4)

This register provides control for modem interface I/O and definition of the flow control mode.

7

6

5

4

3

2

1

0

LCD

R/W

LRI

R/W

RTS

R/W

DTR

R/W

SEN

R/W

LOOP

R/W

RCVE

R/W

URST

R/W

BIT

NAME

URST

RESET

FUNCTION

0

Uart soft reset. This bit can be used by the MCU to reset the UART.

URST = 0 Normal operation. Writing a 0 by MCU has no effect.

URST = 1 When the MCU writes a 1 to this bit, a UART reset is generated (ORed with hard reset). When

the UART exits the reset state, URST is cleared. The MCU can monitor this bit to determine if the

UART completed the reset cycle.

1

RCVE

0

Receiver enable bit. This bit is valid only when 485E in FCRL is 1 (RS485 mode). When 485E = 0, this bit has

no effect on the receiver.

RCVE = 0 When485E=1, theUARTreceiverisdisabledwhenRTS=1, i.e., whendataisbeingtransmitted,

the UART receiver is disabled.

RCVE = 1 When 485E = 1, the UART receiver is enabled regardless of the RTS state, i.e., UART receiver

is enabled all the time. This mode can be used to detect collisions on the RS-485 bus when

received data does not match transmitted data.

2

LOOP

0

This bit controls the normal-/loop-back mode of operation (see Figure 7–1).

LOOP = 0 Normal operation

LOOP = 1 Enable loop-back mode of operation. In this mode the following occur:

S

SOUT is set high

S

SIN is disconnected from the receiver input.

S

The transmitter serial output is looped back into the receiver serial input.

S

The four modem-control inputs: CTS, DSR, DCD, and RI are disconnected.

S

DTR, RTS, LRI and LCD are internally connected to the four modem-control inputs, and read

in the MSR register as follows:

S DTR is reflected in MSR[4] bit

S RTS is reflected in MSR[5] bit

S LRI is reflected in MSR[6] bit

S LCD is reflected in MSR[7] bit

3

4

RSV

DTR

0

Reserved

This bit controls the state of the DTR output pin (see Figure 7–1). This bit has no effect when auto-flow control

is used or when 485E = 1 (in FCRL register).

DTR = 0

DTR = 1

Forces the DTR output pin to inactive (high)

Forces the DTR output pin to active (low)

5

RTS

0

This bit controls the state of the RTS output pin (see Figure 7–1). This bit has no effect when auto-flow control

is used or when 485E = 1 (in FCRL register).

RTS = 0

RTS = 1

Forces the RTS output pin to inactive (high)

Forces the RTS output pin to active (low)

7–5

6

7

LRI

0

This bit is used for loop-back mode only. When in loop-back mode, this bit is reflected in MSR[6]-bit (see

Figure 7–1).

LRI = 0

LRI = 1

Clears MSR[6] = 0

Sets MSR[6] = 1

LCD

This bit is used for loop-back mode only. When in loop-back mode, this bit is reflected in MSR[7]-bit (see

Figure 7–1).

LCD = 0

LCD = 1

Clears MSR[7] = 0

Sets MSR[7] = 1

7.1.7 LSR: Line-status Register (Addr:FFA5)

This register provides the status of the data transfer. DMA transfer is halted when any of OVR, PTE, FRE, BRK, or

EXIT is 1.

7

6

5

4

3

2

1

0

RSV

R/O

TEMT

R/O

TxE

R/O

RxF

R/O

BRK

R/C

FRE

R/C

PTE

R/C

OVR

R/C

BIT

NAME

OVR

RESET

FUNCTION

0

1

2

3

0

This bit indicates the overrun condition of the receiver. If set, it halts the DMA transfer and generates a

status interrupt (if enabled).

OVR = 0

OVR = 1

No overrun error

Overrun error has occurred. Clears when the MCU writes a 1. Writing a 0 has no effect.

PTE

FRE

BRK

This bit indicates the parity condition of the received byte. If set, it halts the DMA transfer and generates a

status interrupt (if enabled).

PTE = 0

PTE = 1

No parity error in data received

Parity error in data received. Clears when the MCU writes a 1. Writing a 0 has no effect.

This bit indicates the framing condition of the received byte. If set, it halts the DMA transfer and generates

a status interrupt (if enabled).

FRE = 0

FRE = 1

No framing error in data received

Framing error in data received. Clears when MCU writes a 1. Writing a 0 has no effect.

This bit indicates the break condition of the received byte. If set, it halts the DMA transfer and generates a

status interrupt (if enabled).

BRK = 0

BRK = 1

No break condition

A break condition in data received was detected. Clears when the MCU writes a 1. Writing a 0

has no effect.

4

5

RxF

TxE

0

1

This bit indicates the condition of the receiver data register. Typically, the MCU does not monitor this bit

since data transfer is done by the DMA controller.

RxF = 0

RxF = 1

No data in the RDR

RDR contains data. Generates Rx interrupt (if enabled).

This bit indicates the condition of the transmitter data register. Typically, the MCU does not monitor this bit

since data transfer is done by the DMA controller.

TxE = 0

TxE = 1

TDR is not empty

TDR is empty. Generates Tx interrupt (if enabled).

6

7

TEMT

RSV

1

0

This bit indicates the condition of both transmitter data register and shift register is empty.

TEMT = 0 Either TDR or TSR is not empty

TEMT = 1 Both TDR and TSR are empty

Reserved = 0

7–6

CTS

DSR

RI

(4) LCTS

(5) LDSR

(6) LRI

DCD

MSR

(7) LCD

DTR

RTS

(4) DTR

(5) RTS

(6) LRI

MCR

(7) LCD

(2) LOOP

Figure 7–1. MSR and MCR Registers in Loop-Back Mode

7.1.8 MSR: Modem-Status Register (Addr:FFA6)

This register provides information about the current state of the control lines from the modem.

7

6

5

4

3

2

1

0

LCD

R/O

LRI

R/O

LDSR

R/O

LCTS

R/O

∆CD

R/C

TRI

R/C

∆DSR

R/C

∆CTS

R/C

BIT

NAME

∆CTS

RESET

FUNCTION

0

This bit indicates that the CTS input has changed state. Cleared when the MCU writes a 1 to this bit.

Writing a 0 has no effect.

∆CTS = 0 Indicates no change in the CTS input

∆CTS = 1 Indicates that the CTS input has changed state since the last time it was read. Clears when the

MCU writes a 1. Writing a 0 has no effect.

1

∆DSR

0

This bit indicates that the DSR input has changed state. Cleared when the MCU writes a 1 to this bit.

Writing a 0 has no effect.

∆DSR = 0 Indicates no change in the DSR input

∆DSR = 1 Indicates that the DSR input has changed state since the last time it was read. Clears when the

MCU writes a 1. Writing a 0 has no effect.

2

3

TRI

0

Trailing edge of the ring indicator. This bit indicates that the RI input has changed from low to high. This bit

is cleared when the MCU writes a 1 to this bit. Writing a 0 has no effect.

TRI = 0

TRI = 1

Indicates no applicable transition on the RI input

Indicates that an applicable transition has occurred on the RI input.

∆CD

This bit indicates that the CD input has changed state. Cleared when the MCU writes a 1 to this bit. Writing

a 0 has no effect.

∆CD = 0

∆CD = 1

Indicates no change in the CD input

Indicates that the CD input has changed state since the last time it was read.

4

5

6

LCTS

LDSR

LRI

0

During loopback, this bit reflects the status of MCR[1] (see Figure 7–1)

LCTS = 0 CTS input is high

LCTS = 1 CTS input is low

During loop back, this bit reflects the status of MCR[0] (see Figure 7–1).

LDSR = 0 DSR input is high

LDSR= 1

DSR input is low

During loop back, this bit reflects the status of MCR[2] (see Figure 7–1).

LRI = 0

LRI = 1

RI input is high

RI input is low

7–7

BIT

NAME

LCD

RESET

FUNCTION

7

0

During loopback, this bit reflects the status of MCR[3] (see Figure 7–1).

LCD = 0

CD input is high

CD input is low

7.1.9 DLL: Divisor Register Low Byte (Addr:FFA7)

This register contains the low byte of the baud-rate divisor.

7

6

5

4

3

2

1

0

D7

D6

D5

D4

D3

D2

D1

D0

R/W

BIT

7–0

NAME

D[7:0]

RESET

FUNCTION

Low-byte value of the 16-bit divisor for generation of the baud clock in the baud-rate generator.

08h

7.1.10 DLH: Divisor Register High Byte (Addr:FFA8)

This register contains the high byte of the baud-rate divisor.

7

6

5

4

3

2

1

0

D15

R/W

D14

R/W

D13

R/W

D12

R/W

D11

R/W

D10

R/W

D9

D8

R/W

BIT

7–0

NAME

RESET

FUNCTION

High-byte value of the 16-bit divisor for generation of the baud clock in the baud-rate generator.

D[15:8]

00h

7.1.11 Baud-rate Calculation

The following formulas are used to calculate the baud-rate clock and the divisors. The baud-rate clock is derived from

the 96-MHz master clock (dividing by 6.5). The table below presents the divisors used to achieve the desired baud

rates, together with the associate rounding errors.

96 MHz

Baud CLK +

+ 14.76923077 MHz

6.5

6

14.76923077 10

Baud Rate 16

Divisor +

7–8

Table 7–4. DLL/DLH Values and Resulted Baud Rates

DLL/DLH VALUE

DESIRED BAUD

ACTUAL BAUD

ERROR %

DEC.

769

385

192

128

96

64

48

24

16

8

HEX.

0301

0181

00C0

0080

0060

0040

0030

0018

0010

0008

0004

0002

0001

1 200

2 400

1 200.36

2 397.60

0.03

0.01

0.16

4 800

4 807.69

7 200

7 211.54

9 600

9 615.38

14 400

19 200

38 400

57 600

115 200

230 400

460 800

921 600

14 423.08

19 230.77

38 461.54

57 692.31

115 384.62

230 769.23

461 538.46

923 076.92

4

2

1

NOTE: The TUSB3410 does support baud rates lower than 1200 bps, which are not

listed due to less interest.

7.1.12 XON: Xon Register (Addr:FFA9)

This register contains a value that is compared to the received data stream. Detection of a match interrupts the MCU

(only if the interrupt enable bit is set). This value is also used for Xon transmission.

7

6

5

4

3

2

1

0

D7

D6

D5

D4

D3

D2

D1

D0

R/W

BIT

7–0

NAME

D[7:0]

RESET

FUNCTION

Xon value to be compared to the incoming data stream

0000

7.1.13 XOFF: Xoff Register (Addr:FFAA)

This register contains a value that is compared to the received data stream. Detection of a match halts the DMA

transfer, and interrupts the MCU (only if the interrupt enable bit is set). This value is also used for Xoff transmission.

7

6

5

4

3

2

1

0

D7

D6

D5

D4

D3

D2

D1

D0

R/W

BIT

7–0

NAME

D[7:0]

RESET

FUNCTION

Xoff value to be compared to the incoming data stream

0000

7–9

7.1.14 MASK: UART Interrupt-Mask Register (Addr:FFAB)

This register controls the UARTs interrupt sources.

7

6

5

4

3

2

1

0

RSV

R/O

RSV

R/O

RSV

R/O

RSV

R/O

RSV

R/O

RRIE

R/W

SIE

R/W

MIE

R/W

BIT

NAME

MIE

RESET

FUNCTION

0

This bit controls the UART-modem interrupt.

MIE = 0

MIE = 1

Modem interrupt is disabled

Modem interrupt is enabled

1

SIE

TRI

RSV

0

This bit controls the UART-status interrupt.

SIE = 0

MIE = 1

Status interrupt is disabled

Status interrupt is enabled

2

This bit controls the UART-TxE/RxF interrupts

TRIE = 0 TxE/RxF interrupts are disabled

TRIE = 1 TxE/RxF interrupts are enable

7–3

Reserved = 0

7.2 UART Data Transfer

Figure 7–2 illustrates the data transfer between the UART and the host using the DMA controller and the USB buffer

manager (UBM). A buffer of 512 bytes is reserved for buffering the UART channel (transmit and receive buffers). The

UART channel has 64 bytes of double-buffer space (X- and Y-buffer). When the DMA writes to the X-buffer, the UBM

reads from the Y-buffer. Similarly, when the DMA reads from the X-buffer, the UBM writes to the Y-buffer. The DMA

channel is configured to operate in the continuous mode (by setting DMACDR[CNT] = 1). Once the MCU enables

the DMA, data transfer toggles between the UMB and the DMA without MCU intervention. See IN transaction

(TUSB3410 to host) for DMA transfer-termination condition.

7.2.1 Receiver Data Flow

The UART receiver has a 32-byte FIFO. The receiver FIFO has two trigger levels. One is the high-level mark (HALT),

which is set to 28 bytes, and the other is the low-level mark (RESUME), which is set to 4 bytes. When the HALT mark

is reached, either the RTS pin goes high or Xoff is transmitted (depending on the auto setting). When the FIFO

reaches the RESUME mark, then either the RTS pin goes low or Xon is transmitted.

7–10

Receiver

Halt on Error or Time-Out

64-Byte

Y-Buffer

RDR: 32-Byte FIFO

DMA

DMACDR

SIN

4

8

64-Byte

X-Buffer

RTS/DTR = 1

X/Y

or Xoff Transmitted

RTS/DTR = 0

or Xon Transmitted

Host

UBM

Xoff/Xon

CTS/DTR = 1/0

Pause/Run

64-Byte

Y-Buffer

DMA

DMACDR

SOUT

64-Byte

X-Buffer

TDR

Figure 7–2. Receiver/Transmitter Data Flow

7.2.2 Hardware Flow Control

Figure 7–3 illustrates the connection necessary to achieve hardware flow control. The CTS and RTS signals are

provided for this purpose. Auto CTS and auto RTS (and Xon/Xoff) can be enabled/disabled independently by

programming the FCRL register.

TUSB3410

SIN

External Device

SOUT

RTS

SOUT

CTS

SIN

RTS

Figure 7–3. Auto Flow Control Interconnect

7.2.3 Auto RTS (Receiver Control)

In this mode, the RTS output pin signals the receiver-FIFO status to an external device. The RTS output signal is

controlled by the high- and low-level marks of the FIFO. When the high-level mark is reached, RTS goes high,

signaling to an external sending device to halt its transfer. Conversely, when the low-level mark is reached, RTS goes

low, signaling to an external sending device to resume its transfer.

Data transfer from the FIFO to the X-/Y-buffer is performed by the DMA controller. See OUT transaction (TUSB3410

to host) for DMA transfer-termination condition.

7.2.4 Auto CTS (Transmitter Control)

In this mode, the CTS input pin controls the transfer from internal buffer (X or Y) to the TDR. When the DMA controller

transfers data from the Y-buffer to the TDR and the CTS input pin goes high, the DMA controller is suspended until

CTS goes low. Meanwhile, the UBM is transferring data from the host to the X-buffer. When CTS goes low, the DMA

resumes the transfer. Data transfer continues alternating between the X- and Y-buffers, without MCU intervention.

See OUT transaction (TUSB3410 to host) for DMA transfer-termination condition.

7–11

7.2.5 Xon/Xoff Receiver Flow Control

To enable Xon/Xoff flow control, certain MCR bits must be set as follows: MCR[5] = 1 and MCR[7:6] = 0. In this mode,

the Xon/Xoff bytes are transmitted to an external sending device to control the device’s transmission. When the

high-level mark (of the FIFO) is reached, the Xoff byte is transmitted, signaling to an external sending device to halt

its transfer. Conversely, when the low-level mark is reached, the Xon byte is transmitted, signaling to an external

sending device to resume its transfer. The data transfer from the FIFO to X-/Y-buffer is performed by the DMA

controller.

7.2.6 Xon/Xoff Transmit Flow Control

To enable Xon/Xoff flow control, certain MCR bits must be set as follows: MCR[5] = 1 and MCR[7:6] = 0. In this mode,

the incoming data are compared to the XON and XOFF registers. If a match to XOFF is detected, the DMA is paused.

If a match to XON is detected, the DMA resumes. Meanwhile, the UBM is transferring data from the host to the

X-buffer. The MCU does not switch the buffers unless the Y-buffer is empty and the X-buffer is full. When Xon is

detected, the DMA resumes the transfer.

7–12

8 Expanded GPIO Port

8.1 Input/Output and Control Registers

The TUSB3410 has four general-purpose I/O pins (P3.0, P3.1, P3.3, P3.4) that are controlled by firmware running

on the MCU. Each pin can be controlled individually and each is implemented with a 12-mA push/pull Cmos output

with tristate control plus input. The MCU treats the outputs as open drain types in that the output can be driven low

continuously, but a high output is driven for two clock cycles and then the output is tristated.

An input pin can be read using the MOV instruction. For example, MOV C,P3.3 reads the input on P3.3. As a

precaution, be certain the associated output is tristated before reading the input.

An output can be set high (and then tristated) using the SETB instruction. For example, SETB P3.1 sets P3.1 high.

An output can be set low using the CLR instruction, as in CLR P3.4, which sets P3.4 low (driven continuously until

changed).

Each GPIO pin has an associated internal pullup resistor. It is strongly recommended that the pullup resistor remain

connected to the pin to prevent oscillations in the input buffer. The only exception is if an external source always drives

the input.

8.1.1 PUR_3: GPIO Pullup Register For Port 3 (Addr:FF9E)

7

6

5

4

3

2

1

0

RSV

R/O

RSV

R/O

RSV

R/O

RSV

R/W

Pin3

R/W

RSV

R/O

Pin1

R/W

Pin0

R/W

BIT

0–7

NAME

RESET

FUNCTION

Pin N

(N = 0 to 7)

0

The MCU may write to this register. If the MCU sets this bit to 1, the pullup resistor is disconnected from

the pin. If the MCU clears this bit to 0, the pullup resistor is connected to the pin. The pullup resistor is

connected to the V

power supply.

CC

8–1

8–2

9 Interrupts

9.1 8052 Interrupt and Status Registers

All 8052 standard, five interrupt sources are preserved. SIE is the standard interrupt-enable register that controls the

five interrupt sources. All the additional interrupt sources are ORed together to generate EX0. The XINTO signal is

provided to interrupt an external MCU (see Figure 9–1).

Table 9–1. 8052 Interrupt Location Map

INTERRUPT SOURCE

DESCRIPTION

UART interrupt

START ADDRESS

0023H

COMMENTS

ES

ET1

EX1

ET0

EX0

Reset

Timer-1 interrupt

External interrupt-1

Timer-0 interrupt

External interrupt-0

001BH

0013H

000BH

0003H

Used for all internal peripherals

0000H

9.1.1 8052 Standard Interrupt Enable (SIE) Register

7

6

X

5

X

4

3

2

1

0

EA

R/W

ES

ET1

R/W

EX1

R/W

ET0

R/W

EX0

R/W

BIT

NAME

EX0

RESET

FUNCTION

0

1

2

3

4

0

Enable or disable external interrupt-0

EX0 = 1 External interrupt-0 is disabled

EX0 = 1 External interrupt-0 is enabled

ET0

EX1

ET1

ES

0

Enable or disable timer-0 interrupt

ET0 = 0

ET0 = 1

Timer-0 interrupt is disabled

Timer-0 interrupt is enabled

Enable or disable external interrupt-1

EX1 = 0 External interrupt-1 is disabled

EX1 = 1 External interrupt-1 is enabled

Enable or disable timer-1 interrupt

ET1 = 0

Timer-1 interrupt is disabled

EX1 = 1 Timer-1 interrupt is enabled

Enable or disable serial port interrupts

ES = 0

ES = 1

Serial-port interrupt is disabled

Serial-port interrupt is enabled

5, 6

7

RSV

EA

0

Reserved

Enable or disable all interrupts (global disable)

EA = 0

EA = 1

Disable all interrupts

Each interrupt source is individually controlled

9.1.2 Additional Interrupt Sources

2

All nonstandard 8052 interrupts (DMA, I C, etc.) are ORed to generate an internal INT0. Note, the external INT0 is

not used. Furthermore, the INT0 must be programmed as an active low-level interrupt (not edge triggered). A vector

interrupt register is provided to identify all interrupt sources (see VECINT: vector-interrupt register). Up to 64 interrupt

vectors are provided. It is the responsibility of the MCU to read the vector and dispatch to the proper interrupt routine.

9–1

9.1.3 VECINT: Vector Interrupt Register (Addr:FF92)

This register contains a vector value, which identifies the internal interrupt source that trapped to location 0003H.

Writing (any value) to this register removes the vector and updates the next vector value (if another interrupt is

pending). Note:thevectorvalueisoffset;therefore, itsvalueisinincrementsoftwo(bit0issetto0). Whennointerrupt

is pending, the vector is set to 00h (see Table 9–2). As shown, the interrupt vector is divided to two fields: I[2:0] and

G[3:0]. The I field defines the interrupt source within a group (on a first-come-first-served basis). In the G field, which

defines the group number, group G0 is the lowest, and G15 is the highest priority.

7

6

5

4

3

I2

2

I1

1

I0

0

G3

R/O

G2

R/O

G1

R/O

G0

R/O

BIT

NAME

RESET

FUNCTION

3–1

I[2:0]

0H

This field defines the interrupt source in a given group. See Table 9–2. Bit 0 = 0 always; therefore, vector values

are offset by two.

7–4

G[3:0]

0H

This field defines the interrupt group. I[2:0] and G[3:0] combine to produce the actual interrupt vector.

Table 9–2. Vector Interrupt Values

G[3:0]

I[2:0]

(Hex)

0

VECTOR

(Hex)

00

INTERRUPT SOURCE

(Hex)

0

1

No interrupt

0

10

Not used

1

2

3

12

14

16

Output endpoint-1

Output endpoint-2

Output endpoint-3

2

0

20

Not used

2

3

1

2

3

0

1

2

3

4

5

6

7

22

24

26

30

32

34

36

38

3A

3C

3E

Input endpoint-1

Input endpoint-2

Input endpoint-3

STPOW packet received

SETUP packet received

RESERVED

RESR interrupt

SUSR interrupt

RSTR interrupt

Reserved

2

4

0

1

2

3

40

42

44

46

I C TXE interrupt

2

I C RXF interrupt

Input endpoint-0

Output endpoint-0

4

4–7

48 → 4E

Not used

5

0

1

4–7

50

52

58 → 5E

UART status interrupt

UART modem interrupt

Not used

6

7

0

1

4–7

5–7

60

62

68 → 6E

70 → 7E

UART RXF interrupt

UART TXE interrupt

Not used

8

0

2

5–7

80

84

88–8E

DMA1 interrupt

DMA3 interrupt

Not used

9–15

X

90 → FE

Not used

9–2

9.1.4 Logical Interrupt Connection Diagram (Internal/External)

Figure 9–1 shows the logical connection of the interrupt sources and its relation with XINTO. The priority encoder

generates an 8-bit vector, corresponding to 64 interrupt sources (not all are used). The interrupt priorities are hard

wired. Vector 0x88 is the highest and 0x12 is the lowest.

Interrupts

Priority

Encoder

IEO

XINTO

Vector

IEO (INT0)

Figure 9–1. Internal Vector Interrupt

9–3

9–4

2

10 I C-Port

2

10.1 I C Registers

2

10.1.1 I2CSTA: I C Status and Control Register (Addr:FFF0)

This register is used to control the stop condition for read and write operations. In addition, it provides transmitter and

receiver handshake signals with their respective interrupt enable bits.

7

6

5

4

3

2

1

0

RXF

R/O

RIE

R/W

ERR

R/C

1/4

R/W

TXE

R/O

TIE

R/W

SRD

R/W

SWR

R/W

BIT

NAME

RESET

FUNCTION

2

0

SWR

0

Stop write condition. This bit determines if the I C controller generates a stop condition when data

from the I2CDAO register is transmitted to an external device.

SWR = 0

Stop condition is not generated when data from the I2CDAO register is shifted out to an

external device.

SWR = 1

Stop condition is generated when data from the I2CDAO register is shifted out to an

external device.

2

1

SRD

0

Stop read condition. This bit determines if the I C controller generates a stop condition when data is

received and loaded into the I2CDAI register.

SRD = 0

Stop condition is not generated when data from the SDA line is shifted into the I2CDAI

register.

SRD = 1

Stop condition is generated when data from the SDA line are shifted into the I2CDAI

register.

2

I C transmitter empty interrupt enable

2

3

TIE

0

1

TIE = 0

TIE = 1

Interrupt disable

Interrupt enable

2

TXE

I C transmitter empty. This bit indicates that data can be written to the transmitter. It can be used for

polling or it can generate an interrupt.

TXE = 0

Transmitter is full. This bit is cleared when the MCU writes a byte to the II2CDAO

register.

2

TXE = 1

Transmitter is empty. The I C controller sets this bit when the contents of the I2CDAO

register are copied to the SDA shift register.

4

5

1/4

0

Bus speed selection

1/4 = 0

1/4 = 1

100-kHz bus speed

400-kHz bus speed

ERR

Bus error condition. This bit is set by the hardware when the device does not respond. It is cleared by

the MCU.

ERR = 0

ERR = 1

No bus error

Bus error condition has been detected. Clears when the MCU writes a 1. Writing a 0 has

no effect.

2

I C receiver ready interrupt enable

6

7

RIE

0

RIE = 0

RIE = 1

Interrupt disable

Interrupt enable

2

RXF

I C receiver full. This bit indicates that the receiver contains new data. It can be used for polling or it

can generate an interrupt.

RXF = 0

RXF = 1

Receiver is empty. This bit is cleared when the MCU reads the I2CDAI register.

2

Receiver contains new data. This bit is set by the I C controller when the received serial

data has been loaded into the I2CDAI register.

10–1

2

10.1.2 I2CADR: I C Address Register (Addr:FFF3)

This register holds the device address and the read/write command bit.

7

6

5

4

3

2

1

0

A6

A5

A4

A3

A2

A1

A0

R/W

BIT

NAME

R/W

RESET

FUNCTION

0

Read/write command bit

R/W = 0 Write operation

R/W = 1 Read operation

7–1

A[6:0]

0h

Seven address bits for device addressing

2

10.1.3 I2CDAI: I C Data-Input Register (Addr:FFF2)

This register holds the received data from an external device.

7

6

5

4

3

2

1

0

D7

D6

D5

D4

D3

D2

D1

D0

R/O

BIT

7–0

NAME

D[7:0]

RESET

FUNCTION

8-bit input data from an I C device

2

0

2

10.1.4 I2CDAO: I C Data-Output Register (Addr:FFF1)

This register holds the data to be transmitted to an external device. Writing to this register starts the transfer on the

SDA line.

7

6

5

4

3

2

1

0

D7

D6

D5

D4

D3

D2

D1

D0

W/O

BIT

7–0

NAME

D[7:0]

RESET

FUNCTION

8-bit output data to an I C device

2

0

10.2 Random-Read Operation

A random read requires a dummy byte-write sequence to load in the data word address. Once the device-address

word and the data-word address are clocked out and acknowledged by the device, the MCU starts a current-address

sequence. The following describes the sequence of events to accomplish this transaction.

Device Address + EPROM [High Byte]

2

•

The MCU sets I2CSTA[SRD] = 0. This forces the I C controller not to generate a stop condition after the

contents of the I2CDAI register are received.

2

•

The MCU sets I2CSTA[SWR] = 0. This forces the I C controller not to generate a stop condition after the

contents of the I2CDAO register are transmitted.

•

The MCU writes the device address (R/W bit = 0) to the I2CADR register (write operation)

The MCU writes the high byte of the E2PROM address into the I2CDAO register (this starts the transfer on

the SDA line).

•

The TXE bit in the I2CSTA register is cleared (indicates busy).

The content of the I2CADR register is transmitted to E2PROM (preceded by start condition on SDA).

10–2

•

The contents of the I2CDAO register are transmitted to E2PROM. (EPROM address).

The TXE bit in the I2CSTA register is set and interrupts the MCU, indicating that the I2CDAO register has

been transmitted.

•

A stop condition is not generated.

EPROM [Low Byte]

•

The MCU writes the low byte of the E2PROM address into the I2CDAO register.

The TXE bit in the I2CSTA register is cleared (indicates busy).

The contents of the I2CDAO register are transmitted to the device (E2PROM address).

The TXE bit in the I2CSTA register is set and interrupts the MCU, indicating that the I2CDAO register has

been transmitted.

•

This completes the dummy write operation. At this point, the E2ROM address is set and the MCU can do

either a single- or a sequential-read operation.

10.3 Current-Address Read Operation

2

Once the E PROM address is set, the MCU can read a single byte by executing the following steps:

2

•

The MCU sets I2CSTA[SRD] = 1. This forces the I C controller to generate a stop condition after the

I2CDAI-register contents are received.

•

The MCU writes the device address (R/W bit = 1) to the I2CADR register (read operation).

The MCU writes a dummy byte to the I2CDAO register (this starts the transfer on SDA line).

The RXF bit in the I2CSTA register is cleared.

The contents of the I2CADR register are transmitted to the device (preceded by start condition on SDA).

The data from E2PROM are latched into the I2CDAI register (stop condition is transmitted).

The RXF bit in the I2CSTA register is set and interrupts the MCU, indicating that the data are available.

The MCU reads the I2CDAI register. This clears the RXF bit (I2CSTA[RXF] = 0).

End

10.4 Sequential-Read Operation

2

Once the E PROM address is set, the MCU can execute a sequential read operation by executing the following (this

example illustrates a 32-byte sequential read):

Device Address

2

•

The MCU sets I2CSTA[SRD] = 0. This forces the I C controller not to generate a stop condition after the

I2CDAI register contents are received.

•

The MCU writes the device address (R/W bit = 1) to the I2CADR register (read operation).

The MCU writes a dummy byte to the I2CDAO register (this starts the transfer on the SDA line).

The RXF bit in the I2CSTA register is cleared.

ThecontentsoftheI2CADRregisteraretransmittedtothedevice(precededbystartconditiononSDA).

N-Byte Read (31 Bytes)

•

The data from the device are latched into the I2CDAI register (stop condition is not transmitted).

The RXF bit in the I2CSTA register is set and interrupts the MCU, indicating that data are available.

The MCU reads the I2CDAI register. This clears the RXF bit (I2CSTA[RXF] = 0).

This operation repeats 31 times.

Last-Byte Read (Byte 32)

2

•

MCU sets I2CSTA[SRD] = 1. This forces the I C controller to generate a stop condition after the I2CDAI

register contents are received.

10–3

•

The data from the device is latched into the I2CDAI register (stop condition is transmitted).

The RXF bit in the I2CSTA register is set and interrupts the MCU, indicating that data are available.

The MCU reads the I2CDAI register. This clears the RXF bit (I2CSTA[RXF] = 0)

End

10.5 Byte-Write Operation

The byte-write operation involves three phases: device address + EPROM [high byte] phase, EPROM [low byte]

phase, and EPROM [DATA] phase. The following describes the sequence of events to accomplish the byte-write

transaction.

Device Address + EPROM [High Byte]

2

•

TheMCUsetsI2CSTA[SWR]=0. ThisforcestheI Ccontrollertonotgenerateastopconditionafterthe

contents of the I2CDAO register are transmitted.

•

The MCU writes the device address (R/W bit = 0) to the I2CADR register (write operation).

The MCU writes the high byte of the E2PROM address into the I2CDAO register (this starts the transfer

on the SDA line).

•

The TXE bit in the I2CSTA register is cleared (indicates busy).

ThecontentsoftheI2CADRregisteraretransmittedtothedevice(precededbystartconditiononSDA).

The contents of the I2CDAO register are transmitted to the device (E2PROM high address).

The TXE bit in the I2CSTA register is set and interrupts the MCU, indicating that the I2CDAO register

contents have been transmitted.

EPROM [Low Byte]

•

The MCU writes the low byte of the E2PROM address into the I2CDAO register.

The TXE bit in the I2CSTA register is cleared (indicating busy).

The contents of the I2CDAO register are transmitted to the device (E2PROM address).

The TXE bit in the I2CSTA register is set and interrupts the MCU, indicating that the I2CDAO register

contents have been transmitted.

EPROM [DATA]

2

•

The MCU sets I2CSTA[SWR] = 1. This forces the I C controller to generate a stop condition after the

contents of I2CDAO register are transmitted.

•

The The data to be written to E2PROM is written by the MCU into the I2CDAO register.

The TXE bit in the I2CSTA register is cleared (indicates busy).

The contents of the I2CDAO register are transmitted to the device (E2PROM data).

The TXE bit in the I2CSTA register is set and interrupts the MCU, indicating that the I2CDAO register

contents have been transmitted.

2

•

The I C controller generates a stop condition after the contents of the I2CDAO register are transmitted.

End

10–4

10.6 Page-Write Operation

The page-write operation is initiated in the same way as byte write, with the exception that a stop condition is not

generated after the first EPROM [DATA] is transmitted. The following describes the sequence of writing 32 bytes in

page mode.

Device Address + EPROM [High Byte]

2

•

TheMCUsetsI2CSTA[SWR]=0. ThisforcestheI Ccontrollernottogenerateastopconditionafterthe

contents of the I2CDAO register are transmitted.

•

The MCU writes the device address (R/W bit = 0) to the I2CADR register (write operation).

The MCU writes the high byte of the E2PROM address into the I2CDAO register

The TXE bit in the I2CSTA register is cleared (indicating busy).

ThecontentsoftheI2CADRregisteraretransmittedtothedevice(precededbystartconditiononSDA).

The contents of the I2CDAO register are transmitted to the device (E2PROM address).

The TXE bit in the I2CSTA register is set and interrupts the MCU, indicating that the I2CDAO register

contents have been transmitted.

EPROM [Low Byte]

•

The MCU writes the low byte of the E2PROM address into the I2CDAO register.

The TXE bit in the I2CSTA register is cleared (indicates busy).

The contents of the I2CDAO register are transmitted to the device (E2PROM address).

The TXE bit in the I2CSTA register is set and interrupts the MCU, indicating that the I2CDAO register

contents have been transmitted.

EPROM [DATA]—31 Bytes

•

The data to be written to the E2PROM are written by the MCU into the I2CDAO register.

The TXE bit in the I2CSTA register is cleared (indicates busy).

The contents of the I2CDAO register are transmitted to the device (E2PROM data).

The TXE bit in the I2CSTA register is set and interrupts the MCU, indicating that the I2CDAO register

contents have been transmitted.

•

This operation repeats 31 times.

EPROM [DATA]—Last Byte

2

•

The MCU sets I2CSTA[SWR] = 1. This forces the I C controller to generate a stop condition after the

contents of the I2CDAO register are transmitted.

•

The MCU writes the last date byte to be written to the E2PROM, into the I2CDAO register.

The TXE bit in the I2CSTA register is cleared (indicates busy).

The contents of the I2CDAO register are transmitted to E2PROM (E2PROM data).

The TXE bit in the I2CSTA register is set and interrupts the MCU, indicating that the I2CDAO register

contents have been transmitted.

2

•

The I C controller generates a stop condition after the contents of the I2CDAO register are transmitted.

End of 32-byte page-write operation.

10–5

10–6

11 TUSB3410 Bootcode Flow

11.1 Introduction

TUSB3410 bootcode is a program embedded within TUSB3410 device. This program is designed to load application

firmware from either external memory device or USB host bootloader device driver. After finished downloading,

bootcode releases its control to the application firmware.

This document describes how the bootcode initializes the TUSB3410 device in detail. In addition, the default USB

2

descriptor, I C device header format, USB host driver firmware downloading format, and supported built-in USB

vendor specific requests are listed for reference. Users should carefully follow the appropriate format to interface with

the bootcode. All unsupported formats might cause unexpected results.

The bootcode source code is also provided for programming reference.

11.2 Bootcode Programming Flow

2

After power-on reset, the bootcode initializes the I C and USB registers along with internal variables. The bootcode

2

then checks to see if the I C device contains a valid signature. If the I C device has a valid signature, the bootcode

continues searching for descriptor blocks and then processes them if the checksum is correct. If application firmware

was found, the bootcode downloads it and releases the control to the application firmware. Otherwise, the bootcode

connects to the USB and waits for host driver to download application firmware. Once firmware downloading is

finished, the bootcode releases the control to the firmware.

The following is the bootcode step-by-step operation.

•

Check if bootcode is in the application mode. If the bootcode is in the application mode, the bootcode

releases the control to the application firmware. Otherwise, the bootcode continues.

•

Initialize all the default settings.

–

Call CopyDefaultSettings() routine.

2

Set I C to 400-kHz speed.

Call UsbDataInitialization() routine.

Set bFUNADR = 0

Disconnect from USB (bUSBCTL = 0x00)

Bootcode handles USB reset

Copy predefined device, configuration, and string descriptors to RAM

Disable all endpoints and enable USB interrupt(SETUP, RSTR, SUSPR, and RESU)

•

Search for product signature

Check if valid signature is in I C. If not, skip I C process.

2

–

Read 2 bytes from address 0x0000 with type III and device address 0. Stop searching if valid

signature is found.

Read 2 bytes from address 0x0000 with type II and device address 4. Stop searching if valid

signature is found.

2

Load customized device, configuration and string descriptors from I C EEPROM.

2

–

Process each descriptor block from I C until end of header is found

If descriptor block is device, configuration or string descriptors, the bootcode overwrites the default

descriptors.

If descriptor block is binary firmware, the bootcode makes a note and loads the firmware later on.

11–1

If descriptor block is auto-execution firmware, the bootcode loads it and releases the control to the

firmware.

If descriptor block is end of header, the bootcode stops searching.

2

•

Set header pointer to the beginning of the binary firmware in I C EEPROM.

Enable global and USB interrupts and set connection bit to 1.

–

Set global interrupt bit. EA = 1.

Set internal interrupt bit. EX0 = 1.

Set connection bit. CONT = 1.

•

Wait for any interrupt events until Get DEVICE DESCIPTOR setup packet arrives.

–

Suspend interrupt

Set IDLE = 1 to enter suspend mode. USB reset wakes up the microcontroller.

Resume interrupt

Bootcode wakes up and waits for new USB requests.

Reset interrupt

Call UsbReset() routine.

Setup interrupt

Bootcode process the request.

Reboot

If Reboot=1, disconnect from USB and restart at address 0x0000.

2

•

Download firmware from I C EEPROM

–

Disable global interrupt. Reset EA = 0.

Load firmware to xdata space if available.

Download firmware from USB.

2

–

If no firmware in I C EEPROM, host downloads firmware via output endpoint 1.

In the first data packet to output endpoint 1, host driver add 3 bytes before the application firmware in

binary format. These three bytes are LSB and MSB of firmware size and then arithmetic checksum of

binary firmware.

•

Release control to firmware.

–

Update USB configuration and interface number.

Release control to application firmware.

Application firmware

Either disconnect from bus or continue responding to USB requests.

–

11.3 Default Bootcode Settings

The bootcode has its own predefined device, configuration, and string descriptors. These default descriptors should

be used in evaluation only. They should not be used in end-user product.

11–2

11.3.1 Device Descriptor

Device descriptor describes the USB version that the device supports, device class, protocol, vendor, product

identifications, strings, and number of configuration. The OS (operation system like Windows, MAC, or Linux) reads

this descriptor to decide which device driver should be used to communicate to this device.

The bootcode uses 0x0451(Texas Instruments) as vendor ID and 0x3410(TUSB3410) as product ID. It also supports

three different strings and one configuration. Table 11–1 lists the device descriptor.

Table 11–1. Device Descriptor

OFFSET

FIELD

bLength

SIZE

1

VALUE

DESCRIPTION

0

1

0x12

Size of this descriptor in bytes

Device Descriptor type

USB spec 1.1

bDescriptorType

bcdUSB

1

2

0x0110

4

bDeviceClass

bDeviceSubClass

bDeviceProtocol

bMaxPacketSize0

idVendor

1

0xFF

Device class is vendor–specific

We have no subclasses.

We use no protocols.

5

1

0

6

1

0

7

1

8

Max. packet size for endpoint zero

8

2

0x0451

USB–assigned vendor ID = TI

10

12

14

15

16

17

idProduct

2

0x3410

TI part number = TUSB3410

bcdDevice

2

0x100

Device release number = 1.0

iManufacturer

iProducct

1

2

3

1

Index of string descriptor describing manufacturer

Index of string descriptor describing product

Index of string descriptor describing device’s serial number

Number of possible configurations:

1

iSerialNumber

bNumConfigurations

1

11.3.2 Configuration Descriptor

The configuration descriptor describes the number of interfaces supported by this configuration, power configuration,

and current consumption.

The bootcode declares only one interface running in bus-powered mode. It consumes up to 100 mA at boot time.

Table 11–2 lists the configuration descriptor.

Table 11–2. Configuration Descriptor

OFFSET

FIELD

bLength

SIZE

VALUE

DESCRIPTION

0

1

2

1

2

9

2

Size of this descriptor in bytes.

Configuration descriptor type

bDescriptor Type

wTotalLength

25 = 9 + 9 + 7 Total length of data returned for this configuration. Includes the combined length

of all descriptors (configuration, interface, endpoint, and class- or

vendor-specific) returned for this configuration.

4

5

bNumInterfaces

1

Number of interfaces supported by this configuration

bConfigurationValue

Value to use as an argument to the SetConfiguration() request to select this

configuration.

6

7

iConfiguration

bmAttributes

1

0

Index of string descriptor describing this configuration.

Configuration characteristics

0x80

D7:

D6:

Reserved (set to one)

Self-powered

D5:

D4–0:

Remote wakeup is supported

Reserved (reset to zero)

8

bMaxPower

1

0x32

This device consumes 100 mA.

11–3

11.3.3 Interface Descriptor

The interface descriptor describes the number of endpoints supported by this interface as well as interface class,

subclass, and protocol.

The bootcode supports only one endpoint and use its own class. Table 11–3 lists the interface descriptor.

Table 11–3. Interface Descriptor

OFFSET

FIELD

SIZE

VALUE

DESCRIPTION

0

1

2

bLength

1

9

4

0

Size of this descriptor in bytes

Interface descriptor type

bDescriptorType

bInterfaceNumber

Numberofinterface. Zero-basedvalueidentifyingtheindexinthearrayofconcurrent

interfaces supported by this configuration.

3

4

bAlternateSetting

bNumEndpoints

1

0

1

Value used to select alternate setting for the interface identified in the prior field

Number of endpoints used by this interface (excluding endpoint zero). If this value is

zero, this interface only uses the default control pipe.

5

6

7

8

bInterfaceClass

bInterfaceSubClass

bInterfaceProtocol

iInterface

1

0xFF

The interface class is vendor specific.

0

Index of string descriptor describing this interface

11.3.4 Endpoint Descriptor

The endpoint descriptor describes the type and size of communication pipe supported by this endpoint.

The bootcode supports only one output endpoint with the size of 64 bytes in addition to control endpoint 0 (required

by all USB devices). Table 11–4 lists the endpoint descriptor.

Table 11–4. Output Endpoint1 Descriptor

OFFSET

FIELD

SIZE

VALUE

DESCRIPTION

0

1

2

bLength

1

7

5

Size of this descriptor in bytes

Endpoint descriptor type

bDescriptorType

bEndpointAddress

0x01

Bit 3…0: The endpoint number

Bit 7:

Direction

0 = OUT endpoint

1 = IN endpoint

3

bmAttributes

1

2

Bit 1…0: Transfer type

10 = Bulk

11 = Interrupt

4

6

wMaxPacketSize

bInterval

2

1

64

0

Maximum packet size this endpoint is capable of sending or receiving when this

configuration is selected.

Interval for polling endpoint for data transfers. Expressed in milliseconds.

11–4

11.3.5 String Descriptor

The string descriptor contains string in the unicode format. It is used to show the manufacturers name, product model,

and serial number in human readable format.

The bootcode supports three strings. The first string is the manufacturers name, the second string is the product

name, and the last string is the serial number. Table 11–5 lists the string descriptor.

Table 11–5. String Descriptor

OFFSET

0

FIELD

bLength

SIZE

1

2

1

2

1

2

VALUE

4

DESCRIPTION

Size of string 0 descriptor in bytes

String descriptor type

English

1

bDescriptorType

wLANGID[0]

bLength

0x03

2

0x0409

36

4

Size of string 1 descriptor in bytes

String descriptor type

Unicode, T is the first byte

Texas Instruments

5

bDescriptorType

bString

0x03

6

‘T’,0x00

‘e’,0x00

‘x’,0x00

‘a’,0x00

‘s’,0x00

‘ ’,0x00

‘I’,0x00

‘n’,0x00

‘s’,0x00

‘t’,0x00

‘r’,0x00

‘u’,0x00

‘m’,0x00

‘e’,0x00

‘n’,0x00

‘t’,0x00

‘s’,0x00

42

8

10

12

14

16

18

20

22

24

26

28

30

32

34

36

38

40

41

42

44

46

48

50

52

54

56

58

60

62

64

66

68

70

bLength

bDescriptorType

bString

Size of string 2 descriptor in bytes

STRING descriptor type

0x03

‘T’,0x00

‘U’,0x00

‘S’,0x00

‘B’,0x00

‘3’,0x00

‘4’,0x00

‘1’,0x00

‘0’,0x00

‘ ‘,0x00

‘B‘,0x00

‘o’,0x00

‘t’,0x00

‘ ’,0x00

‘D’,0x00

UNICODE, T is first byte

TUSB3410 boot device

11–5

Table 11–5. String Descriptor (Continued)

OFFSET

72

FIELD

SIZE

2

VALUE

‘e‘,0x00

‘v’,0x00

‘I,0x00

‘c’,0x00

‘e’,0x00

34

DESCRIPTION

74

2

76

2

78

2

80

2

82

bLength

bDescriptorType

bString

1

Size of string 3 descriptor in bytes

STRING descriptor type

84

1

0x03

86

2

r0,0x00

r1,0x00

r2,0x00

r3,0x00

r4,0x00

r5,0x00

r6,0x00

r7,0x00

r8,0x00

r9,0x00

rA,0x00

rB,0x00

rC,0x00

rD,0x00

rE,0x00

rF,0x00

UNICODE

88

2

R0 to rF are BCD of SERNUM0 to

SERNUM7 registers. 16 digit hex

16 digit hex numbers are created from

SERNUM0 to SERNUM7 registers

90

2

92

2

94

2

96

2

98

2

100

102

104

106

108

110

112

114

116

2

11.4 External Device Header Format

2

The header can be restored in various storage devices such as ROM, parallel/serial EEPROM, I C, or flash ROM.

A valid header should contain a product signature and one or more descriptor blocks. The descriptor block contains

the descriptor prefix and content. In the descriptor prefix, the data type, size, and checksum are specified to describe

the content. The descriptor content contains the necessary information for the bootcode to process.

The header processing routine always counts from the first descriptor block until the desired block number is reached.

The header reads in descriptor prefix with the size of 4 bytes. This prefix contains the type of block, size, and

checksum. For example, if the bootcode would like to find the position on third descriptor block, it reads in the first

descriptor prefix, calculates the position on the second descriptor prefix based on the size specified in the prefix.

bootcode, then repeats the same calculation to find out the position of the third descriptor block.

2

Note that the header-processing routine of the TUSB3410 only supports the I C device. No other storage device

should be used to store header information.

11.4.1 Product Signature

The product signature should be stored at the first 2 bytes of storage device. These 2 bytes should match the product

number. The order of these 2 bytes should be the LSB first and then the MSB. For example, UMP (TUSB5152) is

0x5152. Therefore, the first byte should be 0x52 and the second byte should be 0x51.

2

The TUSB3410 bootcode searches the first 2 bytes of the I C device. If the first 2 bytes are not 0x10 and 0x34, the

bootcode skips the header processing.

11–6

11.4.2 Descriptor Block

Each descriptor block contains prefix and content. The size of the prefix is always 4 bytes. It contains the data type,

size, and checksum for data integrity. The descriptor content contains the corresponding information specified in the

prefix. It could be as small as 1 byte or as large as 65535 bytes. The next descriptor immediately follows the previous

descriptor. If there are no more descriptors, an extra byte with a value of zero should be added to indicate the end

of header.

11.4.2.1 Descriptor Prefix

The first byte of the descriptor prefix is the data type. This tells the bootcode how to process the data in the descriptor

content. The second and third bytes are the size of descriptor content. The second byte is the low byte of the size

and the third byte is the high byte. The last byte is the 8-bit arithmetic checksum of descriptor content.

11.4.2.2 Descriptor Content

Information stored in the descriptor content can be the USB information, firmware, or other type of data. The size of

the content should be from 1 byte to 65535 bytes.

11.5 Checksum in Descriptor Block

Each descriptor prefix contains one checksum of the descriptor content. If the checksum is wrong, the bootcode

simply ignores the descriptor block.

11.6 Header Examples

The header can be specified in different ways. The following descriptors show examples of the header format and

the supported descriptor block.

11.6.1 TUSB3410 Bootcode Supported Descriptor Block

The TUSB3410 bootcode supports the following descriptor blocks.

•

USB Device Descriptor

USB Configuration Descriptor

USB String Descriptor

1

Binary Firmware

2

Autoexec Binary Firmware

1

2

Binary firmware is loaded when the bootcode receives the first get device descriptor request from host. Downloading the firmware should

either continue that request in the data stage or disconnect from the USB and then reconnect to the USB as a new device.

The bootcode loads this autoexec binary firmware before it connects to the USB. The firmware should connect to the USB once it is

loaded.

11–7

11.6.2 USB Descriptor Header

Table 11–6 contains the USB device, configuration, and string descriptors for the bootcode. The last byte is zero to

indicate the end of header.

Table 11–6. USB Descriptors Header

OFFSET

TYPE

SIZE

VALUE

DESCRIPTION

0

Signature0

0x10

FUNCTION_PID_L

1

2

1

2

1

2

1

Signature1

Data Type

0x34

0x03

FUNCTION_PID_H

2

USB device descriptor

3

Data Size (low byte)

Data Size (high byte)

Check Sum

0x12

The device descriptor is 18 bytes.

4

0x00

5

0xCC

0x12

Checksum of data below

6

bLength

Size of device descriptor in bytes

Device descriptor type

7

bDescriptorType

bcdUSB

0x01

8

0x0110

0xFF

0x00

USB spec 1.1

10

11

12

13

14

16

18

20

21

22

23

24

25

26

27

28

29

30

bDeviceClass

bDeviceSubClass

bDeviceProtocol

bMaxPacketSize0

idVendor

Device class is vendor-specific

We have no subclasses.

0x00

We use no protocols

0x08

Maximum packet size for endpoint zero

USB–assigned vendor ID = TI

TI part number = TUSB3410

Device release number = 1.0

Index of string descriptor describing manufacturer

Index of string descriptor describing product

Index of string descriptor describing device’s serial number

Number of possible configurations:

USB configuration descriptor

25 bytes

0x0451

0x3410

0x0100

0x01

idProduct

bcdDevice

iManufacturer

iProducct

0x02

iSerialNumber

bNumConfigurations

Data Type

0x03

0x01

0x04

Data Size (low byte)

Data Size (high byte)

Check Sum

0x19

0x00

0xC6

0x09

Checksum of data below

bLength

Size of this descriptor in bytes

CONFIGURATION Descriptor type

bDescriptorType

wTotalLength

0x02

25(0x19) = Total length of data returned for this configuration. Includes the combined length of

9 + 9 + 7

all descriptors (configuration, interface, endpoint, and class- or vendor-specific)

returned for this configuration.

32

33

bNumInterfaces

1

0x01

Number of interfaces supported by this configuration

bConfigurationValue

Value to use as an argument to the SetConfiguration() request to select this

configuration

34

35

iConfiguration

bmAttributes

1

0x00

0xE0

Index of string descriptor describing this configuration.

Configuration characteristics

D7:

D6:

Reserved (set to one)

Self–powered

D5:

D4–0:

Remote Wakeup is supported

Reserved (reset to zero)

36

37

38

39

bMaxPower

bLength

1

0x64

0x09

0x04

0x00

This device consumes 100 mA.

Size of this descriptor in bytes

INTERFACE descriptor type

bDescriptorType

bInterfaceNumber

Number of interface. Zero-based value identifying the index in the array of

concurrent interfaces supported by this configuration.

11–8

Table 11–6. USB Descriptors Header (Continued)

OFFSET

40

TYPE

SIZE

VALUE

0x00

DESCRIPTION

bAlternateSetting

bNumEndpoints

1

Value used to select alternate setting for the interface identified in the prior field

41

0x01

Number of endpoints used by this interface (excluding endpoint zero). If this value

is zero, this interface only uses the default control pipe.

42

43

44

45

46

47

48

bInterfaceClass

bInterfaceSubClass

bInterfaceProtocol

iInterface

1

0xFF

0x00

0x07

0x05

0x01

The interface class is vendor specific.

Index of string descriptor describing this interface

Size of this descriptor in bytes

bLength

bDescriptorType

bEndpointAddress

ENDPOINT descriptor type

Bit 3…0: The endpoint number

Bit 7:

Direction

0 = OUT endpoint

1 = IN endpoint

49

50

bmAttributes

1

2

0x02

Bit 1…0: Transfer Type

10 = Bulk

11 = Interrupt

wMaxPacketSize

0x0040

Maximum packet size this endpoint is capable of sending or receiving when this

configuration is selected.

52

53

54

55

56

57

58

59

61

62

63

65

67

68

69

71

73

74

75

77

79

81

83

bInterval

Data Type

1

2

1

2

1

2

1

2

1

0x00

0x05

Interval for polling endpoint for data transfers. Expressed in milliseconds.

USB String descriptor

Data Size (low byte)

Data Size (high byte)

Check Sum

0x1A

26(0x1A) = 4 + 6 + 6 + 10

0x00

0x50

Checksum of data below

Size of string 0 descriptor in bytes

STRING descriptor type

English

bLength

0x04

bDescriptorType

wLANGID[0]

bLength

0x03

0x0409

0x06

Size of string 1 descriptor in bytes

STRING descriptor type

UNICODE, ‘T’ is the first byte.

TI = 0x54, 0x49

bDescriptorType

bString

0x03

‘T’,0x00

‘I’,0x00

0x06

bLength

bDescriptorType

bString

Size of string 2 descriptor in bytes

STRING descriptor type

UNICODE, ‘u’ is the first byte.

‘uC’ = 0x75, 0x43

0x03

‘u’,0x00

‘C’,0x00

0x0A

bLength

bDescriptorType

bString

Size of string 3 descriptor in bytes

STRING descriptor type

UNICODE, ‘T’ is the first byte.

‘3410’ = 0x33, 0x34, 0x31, 0x30

0x03

‘3’,0x00

‘4’,0x00

‘1’,0x00

‘0’,0x00

0x00

Data Type

End of header

11–9

11.6.3 Autoexec Binary Firmware

If the application requires firmware loaded prior to USB connection, the following header can be used. The bootcode

loads the firmware and release the control to the firmware directly without connecting to the USB. However, per the

USB specification requirement, any USB device should connect to the bus and respond to the host within the first

100 ms. Therefore, if downloading time is more than 100 ms, the USB and header speed descriptor blocks should

be added before the autoexec binary firmware. Table 11–7 shows an example of autoexec binary firmware header.

Table 11–7. Autoexec Binary Firmware

OFFSET

TYPE

SIZE

VALUE

DESCRIPTION

FUNCTION_PID_L

0x0000

Signature0

0x10

1

0x0001

0x0002

0x0003

0x0004

0x0005

0x0006

0x456d

Signature1

Data Type

1

0x34

0x07

0x67

0x45

0xNN

FUNCTION_PID_H

1

Autoexec binary firmware

0x4567 bytes of application code

Data Size (low byte)

Data Size (high byte)

Check Sum

1

0x4567

1

Checksum of the following firmware

Binary application code

End of header

Program

Data Type

0x00

11.7 Host Driver Downloading Header Format

If firmware downloading from the host driver is desired, the host driver should follow the format in Table 11–8. The

Texas Instruments bootloader driver generates the proper format. Therefore, users only need to provide the binary

image of the application firmware for the Bootloader. If the checksum is wrong, the bootcode disconnects from the

USB and waits before it reconnects to the USB.

Table 11–8. Host Driver Downloading Format

OFFSET

TYPE

SIZE

VALUE

DESCRIPTION

Application firmware size

0x0000 Firmware size (low byte)

0xXX

1

0x0001 Firmware size (low byte)

0x0002 Checksum

1

0xYY

0xZZ

Checksum of binary application code

Binary application code

0x0003 Program

0xYYXX

11–10

11.8 Built-In Vendor Specific USB Requests

The bootcode supports several vendor specific USB requests. These requests are primarily for internal testing only.

These functions should not be used in normal operation.

11.8.1 Reboot

The reboot command forces the bootcode to reboot. The bootcode starts over.

bmRequestType

USB_REQ_TYPE_DEVICE |

USB_REQ_TYPE_VENDOR |

USB_REQ_TYPE_OUT

01000000b

bRequest

wValue

wIndex

wLength

Data

BTC_REBOOT

None

0x85

0x0000

None

11.8.2 Force Execute Firmware

The force execute firmware command requests the bootcode to execute the downloaded firmware unconditionally.

bmRequestType

USB_REQ_TYPE_DEVICE |

USB_REQ_TYPE_VENDOR |

USB_REQ_TYPE_OUT

01000000b

bRequest

wValue

wIndex

wLength

Data

BTC_FORCE_EXECUTE_FIRMWARE

0x8F

None

0x0000

11.8.3 External Memory Read

The bootcode returns the content of the specified address.

bmRequestType

USB_REQ_TYPE_DEVICE |

USB_REQ_TYPE_VENDOR |

USB_REQ_TYPE_IN

11000000b

bRequest

wValue

wIndex

wLength

Data

BTC_EXETERNAL_MEMORY_READ

0x90

None

0x0000

Data address

0xNNNN (From 0x0000 to 0xFFFF)

1 byte

0x0001

0xNN

Byte in the specified address

11.8.4 External Memory Write

The external memory write command tells the bootcode to write data to the specified address.

bmRequestType

USB_REQ_TYPE_DEVICE |

USB_REQ_TYPE_VENDOR |

USB_REQ_TYPE_OUT

01000000b

bRequest

wValue

BTC_EXETERNAL_MEMORY_WRITE

0x91

HI: 0x00

LO: Data

0x00NN

wIndex

wLength

Data

Data address

None

0xNNNN (From 0x0000 to 0xFFFF)

0x0000

None

11–11

2

11.8.5 I C Memory Read

2

The bootcode returns the content of the specified address in I C EEPROM.

2

In the wValue field, the I C device number is from 0x00 to 0x07 in high filed. The memory type is from 0x01 to 0x03

for CAT I to CAT III devices. If bit 7 of bValueL is set, then 400 kHz is used. Otherwise, 100 kHz is used. This request

2

is also used to set the device number and speed before the I C write request.

bmRequestType

USB_REQ_TYPE_DEVICE |

USB_REQ_TYPE_VENDOR |

USB_REQ_TYPE_IN

11000000b

bRequest

wValue

BTC_I2C_MEMORY_READ

0x92

2

HI:

I C device number

0xXXYY

LO:

Memory type bit[1:0]

Speed bit[7]

wIndex

wLength

Data

Data address

0xNNNN (From 0x0000 to 0xFFFF)

1 byte

0x0001

0xNN

Byte in the specified address

2

11.8.6 I C Memory Write

2

The I C memory write command tells the bootcode to write data to the specified address. The SPI mode setting is

done in the SPI read command.

bmRequestType

USB_REQ_TYPE_DEVICE |

USB_REQ_TYPE_VENDOR |

USB_REQ_TYPE_OUT

01000000b

bRequest

wValue

BTC_I2C_MEMORY_WRITE

0x93

HI: should be zero

LO: Data

0x00NN

wIndex

wLength

Data

Data address

None

0xNNNN (From 0x0000 to 0xFFFF)

0x0000

None

11.8.7 Internal ROM Memory Read

The bootcode returns the byte of the specified address in ROM. That is, the binary code of the bootcode.

bmRequestType

USB_REQ_TYPE_DEVICE |

USB_REQ_TYPE_VENDOR |

USB_REQ_TYPE_OUT

01000000b

bRequest

wValue

wIndex

wLength

Data

BTC_INTERNAL_ROM_MEMORY_READ

0x94

None

0x0000

Data address

0xNNNN (From 0x0000 to 0xFFFF)

1 byte

0x0001

0xNN

Byte in the specified address

11–12

11.9 Bootcode Programming Consideration

11.9.1 USB Requests

For each USB request, the bootcode follows the steps below to ensure proper operation of the hardware.

1. Determine the direction of the request by checking the MSB of the bmRequestType field and set the

USBCTL_DIR bit accordingly.

2. Decode the command

3. If another setup is pending, then return. Otherwise, serve the request.

4. Check again, if another setup is pending then go to step 2.

5. Clear the interrupt source and then the VECINT register.

6. Exit the interrupt routine.

11.9.1.1 USB Requests

The USB request consist of three types of transfers. They are control-read-with-data-stage, control-write-

without-data-stage, and control-write-with-data-stage transfer. In each transfer, arrows indicate interrupts generated

after receiving the setup packet, in or out token.

Figure 11–1 and Figure 11–2 show the USB data flow and how the hardware and firmware respond to the USB

requests. Table 11–9 and Table 11–10 lists the bootcode reposes to the standard USB requests.

Setup Stage

Setup (0)

Data Stage

StatusStage

OUT(1)

More

IN(1)

IN(0)

IN(0/1)

INT

Packets

INT

1.Hardware generates interrupt

to MCU.

1.Hardware generates interrupt to

MCU.

1.Hardware does NOT generate

interrupt to MCU.

2.Hardware sets NAK on both

endpoints.

2.Copy data to IN buffer.

3.Clear the NAK bit.

3.Set DIR bit in USBCTL to

indicate the data directory.

3.Decode the setup packet

4.If another setup packet

arrives, abandon this one.

5.Executes appropriate routines.

a) Clear NAK bit in OUT

endpoint.

4.If all data has been sent out,

stall input endpoint.

b) Copy data to IN endpoint

buffer and set byte count.

Figure 11–1. Control Read Transfer

11–13

Table 11–9. Bootcode Response to Control Read Transfer

CONTROL READ

ACTION IN BOOTCODE

Return power and remote wakeup settings

Return 2 bytes of zeros

Return endpoint status

Return device descriptor

Return configuration descriptor

Return string descriptor

Stall

Get status of device

Get status of interface

Get status of endpoint

Get descriptor of device

Get descriptor of configuration

Get descriptor of string

Get descriptor of interface

Get descriptor of endpoint

Get configuration

Stall

Return bConfiguredNumber value

Return bInterfaceNumber value

Get interface

Setup Stage

Setup (0)

Status Stage

IN(1)

INT

1.Hardware generates interrupt

to MCU.

2.Hardware sets NAK on both

endpoints.

1.Hardware does NOT generates

interrupt to MCU.

3.Set DIR bit in USBCTL to

indicate the data directory.

3.Decode the setup packet

4.If another setup packet

arrives, abandon this one.

5.Executes appropriate routines.

a) Clear NAK bit in IN

endpoint.

b) Keep a note so IN interrupt

routine can take proper

action to the request.

Figure 11–2. Control Write Transfer Without Data Stage

Table 11–10. Bootcode Response to Control Write Without Data Stage

CONTROL WRITE WITHOUT DATA STAGE

Clear feature of device

Clear feature of interface

Clear feature of endpoint

Set feature of device

Set feature of interface

Set feature of endpoint

Set address

ACTION IN BOOTCODE

Stall

Clear endpoint stall

Stall

Stall endpoint

Set device address

Stall

Set descriptor

Set configuration

Set bConfiguredNumber

SetbInterfaceNumber

Stall

Set interface

Sync. frame

11–14

11.9.1.2 Interrupt Handling Routine

The higher-vector number has a higher priority than the lower-vector number. Table 11–11 lists all the interrupts and

source of interrupts.

Table 11–11. Vector Interrupt Values and Sources

G[3:0]

(Hex)

I[2:0]

(Hex)

VECTOR

(Hex)

INTERRUPT SOURCE SHOULD BE

CLEARED

INTERRUPT SOURCE

0

1

0

1

00

10

No Interrupt

No Source

Output–endpoint–1

Output–endpoint–2

Output–endpoint–3

Output–endpoint–4

NOT USED

VECINT register

1

2

12

1

3

14

1

4

16

2

4–7

1

18→1E

20

2

Input–endpoint–1

Input–endpoint–2

Input–endpoint–3

Input–endpoint–4

NOT USED

VECINT register

2

22

2

3

24

2

4

26

2

4–7

0

28→2E

30

3

STPOW packet received

SETUP packet received

PSOF interrupt

USBSTA/ VECINT registers

3

1

32

3

2

34

3

36

RESR interrupt

FSPR interrupt

3

4

38

3

5

3A

RTSR interrupt

3

6

3C

HSTL interrupt

3

7

3E

NOT USED

4

0

40

I2C TXE interrupt

Input–endpoint–0

Output–endpoint–0

NOT USED

VECINT register

4

1

42

4

2

44

4

3

46

4

4–7

0

48→4E

50

5

UART1 status interrupt

UART1 modern interrupt

NOT USED

LSR/VECNT register

LSR/VECINT register

5

1

52

5

3–7

0

54→5E

60

6

UART1 RXF interrupt

UART1 TXE interrupt

NOT USED

LSR/VECNT register

LSR/VECINT register

6

1

62

6

2–7

0–7

0

64→6E

70→7E

80

7

NOT USED

8

DMA1 interrupt

NOT USED

DMACSR/VECNT register

8

1

82

8

2

84

DMA3 interrupt

NOT USED

8

3–7

0–7

86→7E

90→FE

9–15

NOT USED

11–15

11.9.2 Hardware Reset Introduced by the Firmware

This feature can be used in firmware upgrade. Once the upgrade is done, the application firmware disconnects from

the USB for at least 200 ms to ensure OS has unloaded the device driver. The firmware then enables the watchdog

timer (enabled by default after power-on reset) and enters an endless loop without resetting the watchdog timer. Once

the watchdog timer times out, it resets the chip as if the chip gets the power-on reset. The bootcode takes over control

and starts the power-on sequence again.

11.10 File Listings

ThebootloadcodecanbeobtainedfromtheTIwebsiteunderSLLS519.code.zip. Thelistshownbelowarethenames

of the files that can be downloaded.

•

Types.h

USB.h

TUSB3410.h

Bootcode.h

Watchdog.h

Bootcode.c

Bootlsr.c

BootUSB.c

Header.h

Header.c

I2c.h

I2c.c

11–16

12 Electrical Specifications

†

12.1 Absolute Maximum Ratings

Supply voltage, V

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 3.6 V

CC

Input voltage, V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to V

+ 0.5 V

I

CC

Output voltage, V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to V

O

Input clamp current, I

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±20 mA

IK

Output clamp current, I

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±20 mA

OK

†

Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and

functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not

implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

12.2 Commercial Operating Condition (3.3 V)

PARAMETER

MIN

TYP

MAX

UNIT

V

Supply voltage

Input voltage

3

3.3

3.6

CC

0

V

I

CC

TTL

2

V

High-level input voltage

V

IH

IL

CMOS

TTL

0.7 × V

CC

0

0.8

0.2 × V

70

V

Low-level input voltage

Operating temperature

V

CMOS

CC

T

A

°C

12.3 Electrical Characteristics T = 25°C, V

= 3.3 V ±5%, V = 0 V

SS

A

CC

PARAMETER

TEST CONDITIONS

MIN TYP

MAX

UNIT

TTL

V

– 0.5

CC

V

High-level output voltage

Low-level output voltage

Positive threshold voltage

Negative threshold voltage

I

= –4 mA

V

OH

OL

IT+

IT–

hys

OH

CMOS

TTL

– 0.5

CC

0.5

1.8

= 4 mA

V

OL

CMOS

TTL

V = V

I

IH

CMOS

TTL

0.7 × V

CC

1.8

0.8

V = V

I

V

CMOS

TTL

0.2 × V

CC

0.3

0.7

CC

Hysteresis (V_IT+– V

)

V = V

I

V

IT–

CMOS

TTL

0.17 × V

0.3 × V

CC

±20

±1

I

High-level input current

Low-level input current

V = V

µA

IH

I

CMOS

TTL

±20

±1

V = V

IL

I

IL

CMOS

I

Output leakage current (Hi-Z)

Output low drive current

Output high drive current

V = V

I

or V

SS

±20

µA

mA

OZ

OL

OH

CC

0.1

‡

Clock duty cycle

50%

‡

Jitter specification

±100

18

ppm

pF

C

Input capacitance

I

Output capacitance

10

pF

O

‡

Applies to all clock outputs

12–1

12–2

13 Application Notes

13.1 Crystal Selection

The TUSB3410 requires a 12-MHz clock source to work properly. This clock source can be a crystal placed across

the X1 and X2 terminals. A parallel resonant crystal is recommended. Most parallel resonant crystals are specified

at a frequency with a load capacitance of 18 pF. This load can be realized by placing 33-pF capacitors from each end

of the crystal to ground. Together with the input capacitance of the TUSB3410 and stray board capacitance, this

provides close to two 36-pF capacitors in series to emulate the 18-pF load requirement. Note, that when using a

crystal, it takes about 2 ms after power up for a stable clock to be produced.

TUSB3410

33 pF

X2

12 MHz

33 pF

X1

Figure 13–1. Crystal Selection

13.2 External Circuit Required for Reliable Bus Powered Suspend Operation

TI has found a potential problem with the action of the SUSPEND output pin immediately after power on. In some

cases the SUSPEND pin can power up asserted high. When used in a bus powered application this can cause a

problem because the VREGEN# input is usually connected to the SUSPEND output. This in turn causes the internal

1.8-V voltage regulator to shut down, which means an external crystal may not have time to begin oscillating, thus

the device will not initialize itself correctly.

TI has determined an on-chip fix for this problem, but has not determined a schedule on when the fix will be

implemented. In the meantime, the components R2 and D1 (rated to 25 mA) in the circuit shown below can be used

as a workaround. Note that R1 and C1 are required components for proper reset operation, unless the reset signal

is provided by another means. R2 and D1 can be left in place or removed once the silicon is modified.

Note that use of an external oscillator (1.8-V output) versus a crystal would avoid this situation, but it is not expected

that many applications would use an oscillator. Also note that self-powered applications would probably not see this

problem because the VREGEN# input would likely be tied low, enabling the internal 1.8-V regulator at all times.

13–1

3.3 V

TUSB3410

R1

15 kΩ

RESET

R2

32 kΩ

VREGEN

C1

1 µF

D1

SUSPEND

Figure 13–2. External Circuit

13.3 Wakeup Timing From WAKEUP or RI Pin

TheTUSB3410canbebroughtoutofthesuspendedstate, orwokenup, byacommandfromthehost. TheTUSB3410

also supports remote wakeup and can be awakened by either of two input signals. A low pulse on the WAKEUP pin

or a low-to-high transition on the RI pin wakes the device up. Note that for reliable operation, either condition must

persist for approximately 3 ms minimum. This allows time for the crystal to power up since in the suspend mode the

crystal interface is powered down. The state of the WAKEUP or RI pin is then sampled by the clock to verify there

was a valid wakeup event.

13–2

14 Mechanical

VF (S-PQFP-G32)

PLASTIC QUAD FLATPACK

0,45

0,30

M

0,22

0,80

24

17

25

16

32

9

0,13 NOM

1

8

5,60 TYP

7,20

SQ

6,80

Gage Plane

9,20

SQ

8,80

0,25

0,05 MIN

0°–ā7°

1,45

1,35

0,75

0,45

Seating Plane

0,10

1,60 MAX

4040172/C 10/96

NOTES: A. All linear dimensions are in millimeters.

B. This drawing is subject to change without notice.

C. Falls within JEDEC MS-026

14–1

14–2


型号：	TUSB3410
厂家：	TEXAS INSTRUMENTS
描述：	USB TO SERIAL PORT CONTROLLER USB转串口控制器控制器
文件：	总92页 (文件大小：314K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

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