TUSB3210_技术文档

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ꢁ

ꢂ

ꢃ

ꢄ

ꢅ

ꢆ

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ꢁ ꢈ ꢉꢊ ꢋ ꢌꢍꢎꢏ ꢂꢋ ꢌ ꢉꢎ ꢏ ꢃ ꢐꢍ ꢑꢋ ꢈ ꢋ ꢌ ꢎꢏꢒ ꢓꢐ ꢌ ꢔ ꢕꢍꢋ ꢖ ꢋꢊ ꢉꢗꢋ

ꢘ ꢕꢈ ꢙ ꢌꢕ ꢏ ꢏꢋ ꢌ

Data Manual

NOTE

Designing with this device may require extensive support. Before incorporating this device into

a design, customers should contact TI or an Authorized TI Distributor.

February 2001

MSDS Bus Solutions

SLLS466

IMPORTANT NOTICE

Texas Instruments and its subsidiaries (TI) reserve the right to make changes to their products or to discontinue

any product or service without notice, and advise customers to obtain the latest version of relevant information

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pertaining to warranty, patent infringement, and limitation of liability.

TI warrants performance of its products to the specifications applicable at the time of sale in accordance with

TI’sstandardwarranty. TestingandotherqualitycontroltechniquesareutilizedtotheextentTIdeemsnecessary

to support this warranty. Specific testing of all parameters of each device is not necessarily performed, except

those mandated by government requirements.

Customers are responsible for their applications using TI components.

In order to minimize risks associated with the customer’s applications, adequate design and operating

safeguards must be provided by the customer to minimize inherent or procedural hazards.

TI assumes no liability for applications assistance or customer product design. TI does not warrant or represent

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Contents

Section

Title

Page

1

Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–1

1.1

1.2

1.3

1.4

1.5

Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–1

Functional Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–2

Terminal Assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–3

Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–3

Terminal Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–4

2

Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–1

2.1

2.2

MCU Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–1

Miscellaneous Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–2

2.2.1

2.2.2

2.2.3

2.2.4

2.2.5

2.2.6

TUSB3210 Boot Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–2

MCNFG: MCU Configuration Register . . . . . . . . . . . . . . . . . 2–3

PUR_n: GPIO Pullup Register for Port n (n = 0 to 3) . . . . . 2–3

INTCFG: Interrupt Configuration . . . . . . . . . . . . . . . . . . . . . . 2–3

WDCSR: Watchdog Timer, Control, and Status Register . 2–4

PCON: Power Control Register (at SFR 87h) . . . . . . . . . . . 2–4

2.3

2.4

Buffers + I/O RAM Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–4

Endpoint Descriptor Block (EDB-1 to EDB-3) . . . . . . . . . . . . . . . . . . . . 2–7

2.4.1

2.4.2

2.4.3

2.4.4

2.4.5

2.4.6

2.4.7

2.4.8

2.4.9

2.4.10

2.4.11

2.4.12

OEPCNF_n: Output Endpoint Configuration . . . . . . . . . . . 2–7

OEPBBAX_n: Output Endpoint X-Buffer Base-Address . . 2–8

OEPBCTX_n: Output Endpoint X Byte Count . . . . . . . . . . 2–8

OEPBBAY_n: Output Endpoint Y-Buffer Base-Address . . 2–8

OEPBCTY_n: Output Endpoint Y Byte Count . . . . . . . . . . . 2–8

OEPSIZXY_n: Output Endpoint X/Y Byte Count . . . . . . . . 2–9

IEPCNF_n: Input Endpoint Configuration . . . . . . . . . . . . . . 2–9

IEPBBAX_n: Input Endpoint X-Buffer Base-Address . . . . . 2–9

IEPBCTX_n: Input Endpoint X-Byte Base-Address . . . . . . 2–10

IEPBBAY_n: Input Endpoint Y-Buffer Base-Address . . . . . 2–10

IEPBCTY_n: Input Endpoint Y Byte Count . . . . . . . . . . . . . 2–10

IEPSIZXY_n: Input Endpoint X/Y-Buffer Size . . . . . . . . . . . 2–11

2.5

2.6

Endpoint-0 Descriptor Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–11

2.5.1

2.5.2

2.5.3

IEPCNFG_0: Input Endpoint-0 Configuration Register . . . 2–11

IEPBCNT_0: Input Endpoint-0 Byte Count Register . . . . . 2–12

OEPCNFG_0: Output Endpoint-0 Configuration

Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–12

2.5.4

OEPBCNT_0: Output Endpoint-0 Byte Count Register . . . 2–13

USB Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–13

2.6.1 FUNADR: Function Address Register . . . . . . . . . . . . . . . . . 2–13

iii

2.6.2

2.6.3

2.6.4

2.6.5

USBSTA: USB Status Register . . . . . . . . . . . . . . . . . . . . . . . 2–14

USBMSK: USB Interrupt Mask Register . . . . . . . . . . . . . . . 2–15

USBCTL: USB Control Register . . . . . . . . . . . . . . . . . . . . . . 2–16

VIDSTA: VID/PID Status Register . . . . . . . . . . . . . . . . . . . . . 2–16

2.7

2.8

2.9

Function Reset and Power-Up Reset Interconnect . . . . . . . . . . . . . . . 2–17

Pullup Resistor Connect/Disconnect . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–18

8052 Interrupt and Status Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–18

2.9.1

2.9.2

2.9.3

2.9.4

2.9.5

8052 Standard Interrupt Enable Register . . . . . . . . . . . . . . . 2–19

Additional Interrupt Sources . . . . . . . . . . . . . . . . . . . . . . . . . . 2–19

VECINT: Vector Interrupt Register . . . . . . . . . . . . . . . . . . . . . 2–20

Logical Interrupt Connection Diagram (INT0) . . . . . . . . . . . 2–21

P2[7:0] Interrupt (INT1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–21

2.10 I2C Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–22

2.10.1

2.10.2

2.10.3

2.10.4

I2CSTA: I2C Status and Control Register . . . . . . . . . . . . . . 2–22

I2CADR: I2C Address Register . . . . . . . . . . . . . . . . . . . . . . . 2–23

I2CDAI: I2C Data-Input Register . . . . . . . . . . . . . . . . . . . . . . 2–23

I2CDAO: I2C Data-Output Register . . . . . . . . . . . . . . . . . . . 2–23

2.11 Read/Write Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–23

2.11.1

2.11.2

2.11.3

2.11.4

2.11.5

Read Operation (Serial EEPROM) . . . . . . . . . . . . . . . . . . . . 2–23

Current Address Read Operation . . . . . . . . . . . . . . . . . . . . . 2–24

Sequential Read Operation . . . . . . . . . . . . . . . . . . . . . . . . . . 2–24

Write Operation (Serial EEPROM) . . . . . . . . . . . . . . . . . . . . 2–25

Page Write Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–26

3

Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–1

3.1

3.2

3.3

Absolute Maximum Ratings Over Operating Free-air Temperature . 3–1

Commercial Operating Condition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–1

Electrical Characteristics, T = 25°C, V

= 3.3 V ± 0.3 V,

CC

A

GND = 0 V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–1

Application . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–1

4

5

4.1

4.2

Examples . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–1

Reset Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–2

Mechanical Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5–1

iv

List of Illustrations

Figure

Title

Page

1–1 TUSB3210 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–2

2–1 MCU Memory Map (TUSB3210) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–1

2–2 MCU Memory Map (ROM Version) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–2

2–3 Reset Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–17

2–4 Pullup Resistor Connect/Disconnect Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . 2–18

2–5 Internal Vector Interrupt (EX0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–21

2–6 P2[7:0] Input Port Interrupt Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–21

4–1 Example LED Connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–1

4–2 Partial Connection Bus Power Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–1

4–3 Upstream Connection (a) Non-switching Power Mode (b) Switching

Power Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–2

4–4 Downstream Connection–(Only One Port Shown) . . . . . . . . . . . . . . . . . . . . . 4–2

4–5 Reset Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–2

List of Tables

Table

Title

Page

2–1 XDATA Space . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–5

2–2 Memory Mapped Registers Summary (XDATA Range = FF80 → FFFF) . . 2–5

2–3 EDB and Buffer Allocations in XDATA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–6

2–4 EDB Entries in RAM (n = 1 to 3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–7

2–5 Input/Output EDB-0 Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–11

2–6 External Pins Mapping to S[3:0] in VIDSTA Register . . . . . . . . . . . . . . . . . . . 2–17

2–7 8052 Interrupt Location Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–18

2–8 Vector Interrupt Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–20

v

vi

1 Introduction

The TUSB3210 has 8k × 8 RAM space for application development. A ROM based version of the TUSB3210 has 8k

× 8 ROM space for predeveloped customer specific production applications. In addition, the programmability of the

TUSB3210 makes it flexible enough to use for various other general USB I/O applications. Unique vendor

identification and product identification (VID/PID) may be selected without the use of an external EEPROM. Using

a 12 MHz crystal, the onboard oscillator generates the internal system clocks. The device may be programmed via

2

an inter-IC (I C) serial interface at power on from an EEPROM, or optionally, the application firmware may be

downloaded from a host PC via USB. The popular 8052-based microprocessor allows several third party standard

tools to be used for application development. In addition, the vast amounts of application code available in the general

market may also be utilized (this may or may not require some code modification due to hardware variations).

1.1 Features

•

Multiproduct support with one code and one chip (up to 16 products with one chip)

Fully compliant with the USB release 1.1 specification

Supports USB suspend/resume and remote wake-up operation

Integrated 8052 Microcontroller with:

–

256 × 8 RAM for internal data

2

8k × 8 RAM code space available for downloadable firmware from host or I C port. [1]

512 × 8 shared RAM used for data buffers and endpoint descriptor blocks (EDB) [2]

Four 8052 GPIO ports, Port 0,1, 2 and 3

2

Master I C controller for external slave device access

Watchdog timer

•

Operates from a 12 MHz crystal

On-chip PLL generates 48/12 MHz

Supports a total of 4 input and 4 output endpoints

Power-down mode

Single 3.3 V operation [3]

64-pin TQFP package

Applications include keyboard, bar code reader, flash memory reader, general-purpose controller

[1] The TUSB3210 has 8K x 8 RAM for development.

[2] This is the buffer space for USB packet transactions.

[3] 1.8 V required only to support suspend mode.

1–1

1.2 Functional Block Diagram

12 MHz

Clock

Oscillator

PLL

and

Dividers

Reset,

Interrupt

and WDT

8052

Core

RSTI

6K x 8

ROM

2 x 16-Bit

Timers

8

USB

USB-0

TxR

Port-0

8

P0.[7:0]

P1.[7:0]

P2.[7:0]

P3.[7:0]

8K x 8

[1]

RAM

Port-1

Port-2

Port-3

512 x 8

SRAM

Logic

CPU – I/F

Suspend/

Resume

2

I C

2

8

I C Bus

Controller

USB

SIE

UBM

USB Buffer

Manager

8

TDM

Control

Logic

[1] The TUSB3210 has 8K x 8 RAM for development. 8k x 8 ROM version available. Contact TI Marketing

Figure 1–1. TUSB3210 Block Diagram

1–2

1.3 Terminal Assignments

PM PACKAGE

(TOP VIEW)

48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33

49

P0.6

P0.7

P1.1

P1.0

P2.7

P2.6

P2.5

P2.4

P2.3

P2.2

GND

P2.1

32

31

30

29

28

27

26

25

24

23

50

51

52

53

54

55

56

57

58

P3.7

P3.6

P3.5

P3.4

P3.3

P3.2

P3.1/S1

P3.0/S0

GND 59

X2 60

X1 61

22 P2.0

21 SELF/BUS

20

19

18

17

TEST2

DM

62

63

64

VCC

NC

DP

NC

PUR

1 2

3

4

5

6 7 8 9 10 11 12 13 14 15 16

1.4 Ordering Information

PACKAGE

T

PLASTIC QUAD FLATPACK

(PM)

A

0°C to 70°C

TUSB3210PM

1–3

1.5 Terminal Functions

TERMINAL

I/O

DESCRIPTION

NAME

DM

NO.

19

I/O

I

Differential data minus USB

Differential data plus USB

Power supply ground

DP

18

GND

5,24,42,5

9

NC

2, 3, 6,

No connection

7, 63, 64

P0.0

P0.1

P0.2

P0.3

P0.4

P0.5

P0.6

P0.7

P1.0

P1.1

P1.2

P1.3

P1.4

P1.5

P1.6

P1.7

P2.0

P2.1

P2.2

P2.3

P2.4

P2.5

P2.6

P2.7

P3.0/S0

P3.1/S1

P3.2

P3.3

43

44

45

46

47

48

49

50

31

32

33

34

35

36

40

41

22

23

25

26

27

28

29

30

58

57

56

55

I/O

General-purpose I/O port 0 bit 0, Schmitt-trigger input 100 µA active pullup, open drain output

General-purpose I/O port 0 bit 1, Schmitt-trigger input 100 µA active pullup, open drain output

General-purpose I/O port 0 bit 2, Schmitt-trigger input 100 µA active pullup, open drain output

General-purpose I/O port 0 bit 3, Schmitt-trigger input 100 µA active pullup, open drain output

General-purpose I/O port 0 bit 4, Schmitt-trigger input 100 µA active pullup, open drain output

General-purpose I/O port 0 bit 5, Schmitt-trigger input 100 µA active pullup, open drain output

General-purpose I/O port 0 bit 6, Schmitt-trigger input 100 µA active pullup, open drain output

General-purpose I/O port 0 bit 7, Schmitt-trigger input 100 µA active pullup, open drain output

General-purpose I/O port 1 bit 0, Schmitt-trigger input 100 µA active pullup, open drain output

General-purpose I/O port 1 bit 1, Schmitt-trigger input 100 µA active pullup, open drain output

General-purpose I/O port 1 bit 2, Schmitt-trigger input 100 µA active pullup, open drain output

General-purpose I/O port 1 bit 3, Schmitt-trigger input 100 µA active pullup, open drain output

General-purpose I/O port 1 bit 4, Schmitt-trigger input 100 µA active pullup, open drain output

General-purpose I/O port 1 bit 5, Schmitt-trigger input 100 µA active pullup, open drain output

General-purpose I/O port 1 bit 6, Schmitt-trigger input 100 µA active pullup, open drain output

General-purpose I/O port 1 bit 7, Schmitt-trigger input 100 µA active pullup, open drain output

General-purpose I/O port 2 bit 0, Schmitt-trigger input 100 µA active pullup, open drain output

General-purpose I/O port 2 bit 1, Schmitt-trigger input 100 µA active pullup, open drain output

General-purpose I/O port 2 bit 2, Schmitt-trigger input 100 µA active pullup, open drain output

General-purpose I/O port 2 bit 3, Schmitt-trigger input 100 µA active pullup, open drain output

General-purpose I/O port 2 bit 4, Schmitt-trigger input 100 µA active pullup, open drain output

General-purpose I/O port 2 bit 5, Schmitt-trigger input 100 µA active pullup, open drain output

General-purpose I/O port 2 bit 6, Schmitt-trigger input 100 µA active pullup, open drain output

General-purpose I/O port 2 bit 7, Schmitt-trigger input 100 µA active pullup, open drain output

General-purpose I/O port 3 bit 0, Schmitt-trigger input 100 µA active pullup, open drain output

General-purpose I/O port 3 bit 1, Schmitt-trigger input 100 µA active pullup, open drain output

General-purpose I/O port 3 bit 2

General-purpose I/O port 3 bit 3, Schmitt-trigger input 100 µA active pullup, open drain output;

will not support INT1 input

P3.4

P3.5

P3.6

P3.7

PUR

RST

RSV

S2

54

53

52

51

17

13

1, 4

8

I/O

O

General-purpose I/O port 3 bit 4, Schmitt-trigger input 100 µA active pullup, open drain output

General-purpose I/O port 3 bit 5, Schmitt-trigger input 100 µA active pullup, open drain output

General-purpose I/O port 3 bit 6, Schmitt-trigger input 100 µA active pullup, open drain output

General-purpose I/O port 3 bit 7, Schmitt-trigger input 100 µA active pullup, open drain output

Pullup resistor connection pin (3-state) push-pull CMOS output (±8 mA)

Controller master reset signal, Schmitt-trigger input 100 µA active pullup

Reserved (Do not connect these pins)

I

VID/PID selection pin

S3

9

VID/PID selection pin

1–4

1.5 Terminal Functions (Continued)

TERMINAL

I/O

DESCRIPTION

NAME

SCL

NO.

12

2

Serial clock I C; open drain output

O

I/O

I

2

Serial data I C; open drain output

SDA

11

SELF/BUS

SUSP

TEST0

TEST1

TEST2

VCC

21

USB power MODE select: self-powered (HIGH), bus-powered (LOW)

Suspend status signal: suspended (HIGH); unsuspended (LOW)

Test input0, Schmitt-trigger input 100 µA active pullup

Test input1, Schmitt-trigger input 100 µA active pullup

Test input2, Schmitt-trigger input 100 µA active pullup

Power supply input 3.3 V typical

16

O

I

14

15

I

20

I

10,39,62

37

I

VDDOUT

VREN

X1

O

I

Power supply regulator output 1.8 V (May be used as an input when VREN is low)

Voltage regulator enable: enable active LOW; disable active HIGH

12-MHz crystal input

38

61

I

X2

60

O

12-MHz crystal output

1–5

1–6

2 Functional Description

2.1 MCU Memory Map

Figure 2–1 illustrates the MCU memory map under boot and normal operation. It must be noted that the internal 256

bytes of IDATA are not shown since it is assumed to be in the standard 8052 location (0000 to 00FF). The shaded

areas represent the internal ROM/RAM.

When SDW bit = 0 (Boot mode): The 6k-ROM is mapped to address (0000–17FF) and is duplicated in location

(8000–97FF) in code space. The internal 8k-RAM is mapped to address range (0000–1FFF) in data space. Buffers,

MMR and I/O are mapped to address range (FD80–FFFF) in data space.

When SDW bit = 1 (Normal mode): The 6k-ROM is mapped to (8000–97FF) in code space. The internal 8k-RAM

is mapped to address range (0000–1FFF) code space. Buffers, MMR and I/O are mapped to address range

(FD80–FFFF) in data space.

Boot Mode (SDW = 0)

Normal Mode (SDW = 1)

CODE

XDATA

CODE

XDATA

0000

17FF

1FFF

6k Boot ROM

8k

RAM

Read/Write

8k

Code RAM

Read Only

8000

97FF

6k Boot ROM

FD80

512 Bytes

RAM

512 Bytes

RAM

FF80

FFFF

MMR

Figure 2–1. MCU Memory Map (TUSB3210)

2–1

CODE

XDATA

0000

8k ROM

1FFF

FD80

512 Bytes

RAM

FF80

FFFF

MMR

Figure 2–2. MCU Memory Map (ROM Version)

2.2 Miscellaneous Registers

2.2.1 TUSB3210 Boot Operation

Since the code-space is in RAM (with the exception of the boot ROM), the TUSB3210 firmware must be loaded from

2

an external source. Two options for booting are available: an external serial EEPROM source connected to the I C

bus, or the host may be used via the USB. On device reset, the SDW bit (in ROM register) and CONT bit in USB

Control Register (USBCTL) will be cleared. This will configure the memory space to boot mode (see memory map)

and will keep the device disconnected from the host.

Thefirstinstructionwillbefetchedfromlocation0000(whichisinthe6k-ROM). The8k-RAMwillbemappedtoXDATA

space (location 0000h). MCU will execute a read from an external EEPROM and test to see if it contains the code

(test for boot signature). If it contains the code, MCU will read from EEPROM and write to the 8k-RAM in XDATA

space. If not, MCU will proceed to boot from USB.

Oncethecodeisloaded, theMCUwillsetSDWto1. Thiswillswitchthememorymaptonormalmode, i.e. the8k-RAM

will be mapped to code space, and the MCU will start executing from location 0000h. Once the switch is done, the

MCU will set CONT to 1 (in USBCTL register) This will connect the device to the USB bus, resulting in the normal

USB device enumeration.

2–2

2.2.2 MCNFG: MCU Configuration Register

This register is used to control the MCU clock rate.

7

6

5

4

3

2

1

0

12/48

R/W

XINT

R/W

RSV

R/O

R3

R2

R1

R0

SDW

R/W

R/O

BIT

NAME

RESET

FUNCTION

0

SDW

0

This bit enables/disables boot ROM. In the ROM version of the controller, this bit has no effect.

SDW = 0

When clear, MCU executes from the 6k boot ROM space. The boot ROM appears in two

locations: 0000 and 8000h. The 8k RAM is mapped to XDATA space; therefore, Read/Write

operation is possible. This bit is set by MCU after the RAM load is completed. MCU cannot

clear this bit. It is cleared on power-up-reset or function reset.

SDW = 1

When set by MCU, the 6k boot ROM maps to location 8000h, and the 8k RAM is mapped to

code-space, starting at location 0000h. At this point, MCU executes from RAM, and write

operation is disabled (No write operation is possible in code space).

4–1

R[3:0]

RSV

No affect These bits reflect the device revision number

5

0

Reserved

6

7

XINT

12/48

0

INT1 source control bit.

XINT = 0 INT1 is connected to P3.3-pin and operates as a standard INT1 interrupt

XINT = 1 INT1 is connected to the OR of Port–2 inputs.

0

This bit selects 12 or 48MHz clock for MCU

12/48 = 0 12 MHz

12/48 = 1 48 MHz

2.2.3 PUR_n: GPIO Pullup Register for Port n (n = 0 to 3)

7

6

5

4

3

2

1

0

Pin7

R/W

Pin6

R/W

Pin5

R/W

Pin4

R/W

Pin3

R/W

Pin2

R/W

Pin1

R/W

Pin0

R/W

BIT

NAME

RESET

FUNCTION

0–7

PinN

(N = 0 to 7)

0

The MCU may write to this register. If the MCU sets this bit to 1, the pullup resistor is disconnected from

the pin. If the MCU clears this bit to 0, the pullup resistor is connected to the pin. The pullup resistor is

connected to V

power supply.

CC

2.2.4 INTCFG: Interrupt Configuration

7

6

5

4

3

I3

2

I2

1

I1

0

I0

RSV

R/O

RSV

R/O

RSV

R/O

RSV

R/O

R/W

BIT

NAME

RESET

FUNCTION

0–3

I[3:0]

0010

The MCU may write to this register to set the interrupt delay time for Port 2 on the MCU. The value of the

lower nibble represents the delay in ms. Default after reset is 2 ms.

4–7

RSV

0

Reserved

2–3

2.2.5 WDCSR: Watchdog Timer, Control, and Status Register

A watchdog timer (WDT) with 1ms clock is provided. If this register is not accessed for a period of 32ms, the WDT

counter will reset the MCU. (See Figure 2–3, Reset Diagram). When the IDL bit in PCON is set, the WDT will be

suspended until an interrupt is detected. At this point, the IDL bit will be cleared and the WDT will resume operation.

7

6

5

4

3

2

1

0

WDE

R/W

WDR

R/W

RSV

R/O

RSV

R/O

RSV

R/O

RSV

R/O

RSV

R/O

WDT

W/O

BIT

NAME

RESET

FUNCTION

0

WDT

0

MCU must write a 1 to this bit to prevent the WDT from resetting the MCU. If MCU does not write a 1 in a

periodof 31ms, the WDT will reset the device. Writing a 0 has no effect on the WDT. (WDT is a 5-bit counter

using 1ms CLK). This bit is read as 0.

5–1

RSV

0

Reserved = 0

6

WDR

Watchdog reset indication bit. This bit indicates if the reset occurred due to power-on reset or watchdog

timer reset.

WDR = 0

WDR = 1

A power-up or USB reset occurred.

Awatchdogtimeoutresetoccurred.Toclearthisbit, theMCUmustwritea1. Writinga0hasno

effect.

7

WDE

0

Watchdog Timer Enable.

WDE = 0

WDE = 1

This bit is cleared only on power-up, USB-reset (if enabled) or WDT reset.

WhenMCUwritesa1tothisbittheWDTwillstartrunning. MCUcannotdisabletheWDT. Only

poweruporUSBreset(ifenabled)canclearit. WhenMCUisinidlestate(IDL=1), theWDTis

suspended.

2.2.6 PCON: Power Control Register (at SFR 87h)

7

6

5

4

3

2

1

0

SMOD

R/W

RSV

R/O

RSV

R/O

RSV

R/O

GF1

R/W

GF0

R/W

RSV

R/O

IDL

R/W

BIT

NAME

RESET

FUNCTION

0

IDL

0

MCU idle mode bit. This bit can be set by MCU and is cleared only by INT1 interrupt.

IDL = 0

MCU is NOT in idle mode. This bit is cleared by INT1 interrupt logic when INT1 is asserted for

at least 400µs.

IDL = 1

MCU is in idle mode and RAM is in low-power mode. The oscillator/APLL is off and the WDT

will be suspended. When in suspend mode, only INT1 can be used to exit from idle mode and

generate an interrupt. INT1 must be asserted for at least 400µs for the interrupt to be

recognized.

1

RSV

GF[1:0]

RSV

0

00

0

Reserved

3–2

6–4

7

General-purpose bits. MCU can write and read them.

Reserved

SMOD

0

Double baud rate control bit. For more information see UART serial interface in M8052 core specification.

2.3 Buffers + I/O RAM Map

The address range from FD80 to FFFF is reserved for data buffers, setup packet, endpoint descriptor blocks (EDB),

and all I/O. RAM space of 512 bytes [FD80–FF7F] is used for EDB and buffers. The FF80–FFFF range is used for

memory mapped registers (MMR). Table 2–1 represents the internal XDATA space allocation.

2–4

Table 2–1. XDATA Space

DESCRIPTION

ADDRESS RANGE

FFFF

Internal MMR

(Memory mapped registers)

↑

FF80

FF7F

EDB

↑

(Endpoint descriptor blocks)

FF08

FF07

↑

Setup packet buffer

Input endpoint-0 buffer

Output endpoint-0 buffer

FF00

FEFF

↑

512 byte

RAM

FEF8

FEF7

↑

FEF0

FEEF

Data buffers

(367 bytes)

↑

FD80

Table 2–2. Memory Mapped Registers Summary (XDATA Range = FF80 → FFFF)

ADDRESS

FFFF

FFFE

FFFD

FFFC

↑

REGISTER

FUNADR

USBSTA

USBMSK

USBCTL

RESERVED

VIDSTA

RESERVED

I2CADR

I2CDAI

DESCRIPTION

FUNADR: Function address register

USBSTA: USB status register

USBMSK: USB interrupt mask register

USBCTL: USB control register

FFF6

↑

VIDSTA: VID/PID status register

FFF3

FFF2

FFF1

FFF0

↑

I2CADR: I2C address register

I2CDAI: I2C data-input register

I2CDAO: I2C data-output register

I2CSTA: I2C status and control register

I2CDAO

I2CSTA

RESERVED

PUR3

FF97

FF96

FF95

FF94

FF93

FF92

Port 3 pullup resistor register

Port 2 pullup resistor register

Port 1 pullup resistor register

Port 0 pullup resistor register

PUR2

PUR1

PUR0

WDCSR

VECINT

WDCSR: Watchdog timer, control & status register

VECINT: Vector interrupt register

2–5

Table 2–2. Memory Mapped Registers Summary (XDATA Range = FF80 → FFF) (Continued)

ADDRESS

FF91

FF90

↑

REGISTER

RESERVED

MCNFG

DESCRIPTION

MCNFG: MCU configuration register

RESERVED

INTCFG

FF84

FF83

FF82

FF81

FF80

INTCFG: Interrupt delay configuration register

OEPBCNT_0

OEPCNFG_0

IEPBCNT_0

IEPCNFG_0

OEPBCNT_0: Output endpoint-0 byte count register

OEPCNFG_0: Output endpoint-0 configuration register

IEPBCNT_0: Input endpoint-0 byte count register

IEPCNFG_0: Input endpoint-0 configuration register

Table 2–3. EDB and Buffer Allocations in XDATA

ADDRESS

FF7F

DESCRIPTION

↑

(32–bytes)

RESERVED

FF60

FF5F

↑

(8–bytes)

Input endpoint_3: configuration

Input endpoint_2: configuration

Input endpoint_1: configuration

FF58

FF57

↑

FF50

FF4F

↑

FF48

FF47

↑

(40–bytes)

RESERVED

FF20

FF1F

↑

(8–bytes)

Output endpoint_3: configuration

Output endpoint_2: configuration

Output endpoint_1: configuration

Setup packet block

FF18

FF17

↑

FF10

FF0F

↑

FF08

FF07

↑

FF00

FEFF

↑

Input endpoint_0 buffer

FEF8

2–6

Table 2–3. EDB and Buffer Allocations in XDATA (Continued)

ADDRESS

DESCRIPTION

FEF7

↑

(8–bytes)

Output endpoint_0 buffer

Top of buffer space

FEF0

FEEF

↑

TOPBUFF

Buffers space

FD80

STABUFF

Start of buffer space

2.4 Endpoint Descriptor Block (EDB-1 to EDB-3)

Data transfers between USB, MCU and external devices are defined by an endpoint descriptor block (EDB). Four

input and four output EDBs are provided. With the exception of EDB–0 (I/O Endpoint–0), all EDBs are located in

SRAM as shown in Table 2–3. Each EDB contains information describing the X and Y buffers. In addition, it provides

general status information.

Table 2–4 illustrates the EDB entries for EDB–1 to EDB–3. EDB–0 registers will be described separately.

Table 2–4. EDB Entries in RAM (n = 1 to 3)

Offset

07

ENTRY NAME

EPSIZXY_n

EPBCTY_n

EPBBAY_n

SPARE

DESCRIPTION

I/O endpoint_n: X/Y buffer size

06

I/O endpoint_n: Y byte count

I/O endpoint_n: Y buffer base address

Not used

05

04

03

SPARE

Not used

02

EPBCTX_n

EPBBAX_n

EPCNF_n

I/O endpoint_n: X byte count

I/O endpoint_n: X buffer base address

I/O endpoint_n: configuration

01

00

2.4.1 OEPCNF_n: Output Endpoint Configuration (n=1 to 3)

7

6

5

4

3

2

1

0

UBME

R/W

ISO

R/W

TOGLE

R/W

DBUF

R/W

STALL

R/W

USBIE

R/W

RSV

R/O

RSV

R/O

BIT

1–0

2

NAME

RSV

RESET

FUNCTION

0

x

Reserved

USBIE

USB interrupt enable on transaction completion. Set/clear by MCU.

USBIE = 0 no interrupt

USBIE = 1 interrupt on transaction completion

3

4

STALL

DBUF

0

x

USB stall condition indication. Set/clear by MCU.

STALL = 0 No stall

STALL = 1 USBstallcondition. If set by MCU, a STALLhandshakeisinitiatedandthebitisclearedbyMCU.

Double buffer enable. Set/clear by MCU.

DBUF = 0 Primary buffer only (X–buffer only)

DBUF = 1 Toggle bit selects buffer

5

6

TOGLE

ISO

x

USB Toggle bit. This bit reflects the toggle sequence bit of DATA0, DATA1

ISO = 0

Non-isochronoustransfer. ThisbitmustbeclearedbyMCUsinceonlyNon-isochronoustransfer

is supported.

7

UBME

x

UBM enable/disable bit. Set/clear by MCU.

UBME = 0 UBM cannot use this endpoint.

UBME = 1 UBM can use this endpoint.

2–7

2.4.2 OEPBBAX_n: Output Endpoint X-Buffer Base-Address (n=1 to 3)

7

6

5

4

3

2

1

0

A

10

A

9

A

8

A

7

A

6

A

5

A

4

A

3

R/W

BIT

NAME

RESET

FUNCTION

7–0

A[10:3]

x

A[10:3] of X–buffer base address (padded with 3-LSB of zeros for a total of 11-bits). This value is set by the

MCU. UBM or DMA uses this value as the start-address of a given transaction. Furthermore, UBM or DMA

does not change this value at the end of a transaction.

2.4.3 OEPBCTX_n: Output Endpoint X Byte Count (n=1 to 3)

7

6

5

4

3

2

1

0

NAK

R/W

C

0

6

5

4

3

2

1

R/W

BIT

NAME

RESET

FUNCTION

6–0

C[6:0]

x

X-Buffer Byte count:

X000.0000b > Count = 0

X000.0001b > Count = 1 byte

:

X011.1111b > Count = 63 bytes

X100.0000b > Count = 64 bytes

Any value ≥ 100.0001b produces unpredictable results.

7

NAK

x

NAK= 0 No valid data in buffer. Ready for host out

NAK= 1 Buffer contains a valid packet from Host (host-out request is NAK)

2.4.4 OEPBBAY_n: Output Endpoint Y-Buffer Base-Address (n=1 to 3)

7

6

5

4

3

2

1

0

A

10

A

9

A

8

A

7

A

6

A

5

A

4

A

3

R/W

BIT

NAME

RESET

FUNCTION

7–0

A[10:3]

x

A[10:3] of Y–buffer base address (padded with 3-LSB of zeros for a total of 11 bits). This value is set by the

MCU. UBM or DMA uses this value as the start-address of a given transaction. Furthermore, UBM or DMA

does not change this value at the end of a transaction.

2.4.5 OEPBCTY_n: Output Endpoint Y Byte Count (n=1 to 3)

7

6

5

4

3

2

1

0

NAK

R/W

C

0

6

5

4

3

2

1

R/W

BIT

NAME

RESET

FUNCTION

6–0

C[6:0]

x

Y-Byte count:

X000.0000b > Count = 0

X000.0001b > Count = 1 byte

:

X011.1111b > Count = 63 bytes

X100.0000b > Count = 64 bytes

Any value ≥ 100.0001b will result in unpredictable results.

7

NAK

x

NAK= 0 No valid data in buffer. Ready for host out

NAK= 1 Buffer contains a valid packet from host (host-out request is NAK)

2–8

2.4.6 OEPSIZXY_n: Output Endpoint X/Y Byte Count (n=1 to 3)

7

6

5

4

3

2

1

0

RSV

R/O

S

0

6

5

4

3

2

1

R/W

BIT

NAME

RESET

FUNCTION

6–0

S[6:0]

x

X AND Y-Buffer size:

0000.0000b > Count = 0

0000.0001b > Count = 1 byte

:

0011.1111b > Count = 63 bytes

0100.0000b > Count = 64 bytes

Any value ≥ 100.0001b produces unpredictable results.

7

RSV

0

Reserved

2.4.7 IEPCNF_n: Input Endpoint Configuration (n=1 to 3)

7

6

5

4

3

2

1

0

UBME

R/W

ISO

R/W

TOGLE

R/W

DBUF

R/W

STALL

R/W

USBIE

R/W

RSV

R/O

RSV

R/O

BIT

1–0

2

NAME

RSV

RESET

FUNCTION

x

Reserved = 0

USBIE

USB interrupt enable on transaction completion.

USBIE = 0 No interrupt

USBIE = 1 Interrupt on transaction completion

3

4

STALL

DBUF

0

x

USB stall condition indication. Set by UBM, but can be set/cleared by MCU.

STALL = 0 No stall

STALL = 1 USB stall condition. If set by MCU, a STALL handshake will be initiated and the bit is cleared

automaticallly.

Double buffer enable

DBUF = 0 Primary buffer only (X–buffer only)

DBUF = 1 Toggle bit selects buffer

5

6

TOGLE

ISO

x

USB Toggle bit. This bit reflects the toggle sequence bit of DATA0, DATA1

ISO = 0

Non-isochronous transfer. This bit must be cleared by MCU since only Non-isochronous

transfer is supported.

7

UBME

x

UBM enable/disable bit. Set/clear by MCU.

UBME = 0 UBM cannot use this endpoint.

UBME = 1 UBM can use this endpoint.

2.4.8 IEPBBAX_n: Input Endpoint X-Buffer Base-Address (n=1 to 3)

7

6

5

4

3

2

1

0

A

10

A

9

A

8

A

7

A

6

A

5

A

4

A

3

R/W

BIT

NAME

RESET

FUNCTION

7–0

A[10:3]

x

A[10:3] of X-buffer base address (padded with 3-LSB of zeros for a total of 11 bits). This value is set by the

MCU. UBM or DMA uses this value as the start-address of a given transaction. Furthermore, UBM or DMA

does not change this value at the end of a transaction.

2–9

2.4.9 IEPBCTX_n: Input Endpoint X-Byte Base-Address (n=1 to 3)

7

6

5

4

3

2

1

0

NAK

R/W

C

0

6

5

4

3

2

1

R/W

BIT

NAME

RESET

FUNCTION

6–0

C[6:0]

x

X-Buffer Byte count:

X000.0000b > Count = 0

X000.0001b > Count = 1 byte

:

X011.1111b > Count = 63 bytes

X100.0000b > Count = 64 bytes

Any value ≥ 100.0001b produces unpredictable results.

7

NAK

x

NAK = 0 Buffer contains a valid packet for host-in transaction

NAK = 1 Buffer is empty (host-in request is NAK)

2.4.10 IEPBBAY_n: Input Endpoint Y-Buffer Base-Address (n=1 to 3)

7

6

5

4

3

2

1

0

A

10

A

9

A

8

A

7

A

6

A

5

A

4

A

3

R/W

BIT

NAME

RESET

FUNCTION

7–0

A[10:3]

x

A[10:3] of Y-buffer base address (padded with 3-LSB of zeros for a total of 11 bits). This value is set by the

MCU. UBM or DMA uses this value as the start-address of a given transaction. Furthermore, UBM or DMA

does not change this value at the end of a transaction.

2.4.11 IEPBCTY_n: Input Endpoint Y Byte Count (n=1 to 3)

7

6

5

4

3

2

1

0

NAK

R/W

C

0

6

5

4

3

2

1

R/W

BIT

NAME

RESET

FUNCTION

6–0

C[6:0]

x

X-Byte count:

X000.0000b > Count = 0

X000.0001b > Count = 1 byte

:

X011.1111b > Count = 63 bytes

X100.0000b > Count = 64 bytes

Any value ≥ 100.0001b produces unpredictable results.

7

NAK

x

NAK = 0 Buffer contains a valid packet for host-in transaction

NAK = 1 Buffer is empty (host-in request is NAK)

2–10

2.4.12 IEPSIZXY_n: Input Endpoint X/Y-Buffer Size (n=1 to 3)

7

6

5

4

3

2

1

0

RSV

R/O

S

0

6

5

4

3

2

1

R/W

BIT

NAME

RESET

FUNCTION

6–0

S[6:0]

x

X AND Y-Buffer size:

0000.0000b > Count = 0

0000.0001b > Count = 1 byte

:

0011.1111b > Count = 63 bytes

0100.0000b > Count = 64 bytes

Any value ≥ 100.0001b produces unpredictable results.

7

RSV

x

Reserved

2.5 Endpoint-0 Descriptor Registers

UnlikeEDB-1 to EDB-3, which are defined as memory entries in SRAM, Endpoint-0 is described by a set of 4 registers

(two for output and two for input). Table 2–5 defines the registers and their respective addresses used for EDB-0

description. EDB-0 has no Base-Address-Register, since these addresses are hardwired to FEF8 and FEF0. Note

that the bit positions have been preserved to provide consistency with EDB-n (n = 1 to 3).

Table 2–5. Input/Output EDB-0 Registers

ADDRESS

FF83

REGISTER NAME

OEPBCNT_0

OEPCNFG_0

IEPBCNT_0

DESCRIPTION

BASE ADDRESS

FEF0

Output endpoint_0: byte count register

Output endpoint_0: configuration register

Input endpoint_0: byte count register

Input endpoint_0: configuration register

FF82

FF81

FF80

IEPCNFG_0

FEF8

2.5.1 IEPCNFG_0: Input Endpoint-0 Configuration Register

7

6

5

4

3

2

1

0

UBME

R/W

RSV

R/O

TOGLE

R/O

RSV

R/O

STALL

R/W

USBIE

R/W

RSV

R/O

RSV

R/O

BIT

1–0

2

NAME

RSV

RESET

FUNCTION

0

Reserved

USBIE

USB interrupt enable on transaction completion. Set/clear by MCU

USBIE = 0 No interrupt

USBIE = 1 Interrupt on transaction completion

3

STALL

0

USB stall condition indication. Set/clear by MCU.

STALL = 0 No stall

STALL = 1 USB stall condition. If set by MCU, a STALL handshake is initiated and the bit is cleared

automaticallly by next setup transaction.

4

5

6

7

RSV

TOGLE

RSV

0

Reserved

USB toggle bit. This bit reflects the toggle sequence bit of DATA0, DATA1

Reserved

UBME

UBM enable/disable bit. Set/clear by MCU.

UBME = 0 UBM cannot use this endpoint.

UBME = 1 UBM can use this endpoint.

2–11

2.5.2 IEPBCNT_0: Input Endpoint-0 Byte Count Register

7

6

5

4

3

2

1

0

NAK

R/W

RSV

R/O

RSV

R/O

RSV

R/O

C

0

3

2

1

R/W

BIT

NAME

RESET

FUNCTION

3–0

C[3:0]

0000

Byte count:

0000b > Count = 0

:

0111b > Count =7

1000b > Count = 8

1001b to 1111b are reserved. (If used, defaults to 8)

6–4

RSV

NAK

0

1

Reserved

7

NAK= 0 Buffer contains a valid packet for host-in transaction

NAK= 1 Buffer is empty (host-in request is NAK)

2.5.3 OEPCNFG_0: Output Endpoint-0 Configuration Register

7

6

5

4

3

2

1

0

UBME

R/W

RSV

R/O

TOGLE

R/O

RSV

R/O

STALL

R/W

USBIE

R/W

RSV

R/O

RSV

R/O

BIT

1–0

2

NAME

RSV

RESET

FUNCTION

0

Reserved

USBIE

USB interrupt enable on transaction completion. Set/clear by MCU

USBIE = 0 no interrupt

USBIE = 1 interrupt on transaction completion

3

STALL

0

USB stall condition indication. Set/clear by MCU.

STALL = 0 No stall

STALL = 1 USB stall condition. If set by MCU, a STALL handshake is initiated and the bit is cleared

automaticallly.

4

5

6

7

RSV

TOGLE

RSV

0

Reserved

USB toggle bit. This bit reflects the toggle sequence bit of DATA0, DATA1

Reserved

UBME

UBM enable/disable bit. Set/clear by MCU.

UBME = 0 UBM cannot use this endpoint.

UBME = 1 UBM can use this endpoint.

2–12

2.5.4 OEPBCNT_0: Output Endpoint-0 Byte Count Register

7

6

5

4

3

2

1

0

NAK

R/W

RSV

R/O

RSV

R/O

RSV

R/O

C

0

3

2

1

R/W

BIT

NAME

RESET

FUNCTION

3–0

C[3:0]

0000

Byte count:

0000b > Count = 0

:

0111b > Count =7

1000b > Count = 8

1001b to 1111b are reserved. (If used, defaults to 8)

6–4

RSV

NAK

0

1

Reserved = 0

7

NAK= 0 No valid data in buffer. Ready for host out

NAK= 1 Buffer contains a valid packet from host. (NAK the host)

2.6 USB Registers

2.6.1 FUNADR: Function Address Register

This register contains the device function address.

7

6

5

4

3

2

1

0

RSV

R/O

FA6

R/W

FA5

R/W

FA4

R/W

FA3

R/W

FA2

R/W

FA1

R/W

FA0

R/W

BIT

NAME

RESET

FUNCTION

6–0

FA[6:0]

0000000 Thesebitsdefinethecurrentdeviceaddressassignedtothefunction. MCUwritesavaluetothisregisteras

a result of SET-ADDRESS host command.

7

RSV

0

Reserved

2–13

2.6.2 USBSTA: USB Status Register

All bits in this register are set by the hardware and will be cleared by MCU when writing a 1 to the proper bit location

(writing a 0 has no effect). In addition, each bit can generate an interrupt if its corresponding mask bit is set (R/C

notation indicates read and clear only by MCU).

7

6

5

4

3

2

1

0

RSTR

R/C

SUSR

R/C

RESR

R/C

PWOFF

R/C

PWON

R/C

SETUP

R/C

RSV

R/O

STPOW

R/C

BIT

NAME

RESET

FUNCTION

0

STPOW

0

SETUP overwrite bit. Set by hardware when setup packet is received while there is already a packet in the

setup buffer.

STPOW = 0 MCU can clear this bit by writing a 1. (Writing 0 has no effect)

STPOW = 1 SETUP overwrite

Reserved

1

2

RSV

0

SETUP

SETUP transaction received bit.

As long as SETUP is 1, IN and OUT on endpoint-0 is NAK regardless of the value of their real NAK bits.

SETUP = 0

SETUP = 1

MCU can clear this bit by writing a 1. (Writing 0 has no effect)

SETUP transaction received.

3

4

5

PWON

PWOFF

RESR

0

Power on request for Port-3.

This bit indicates if power-onto Port-3has been received. Thisbit generatesaPWONinterrupt (If enabled).

PWON = 0

PWON = 1

MCU can clear this bit by writing a 1. (Writing 0 has no effect)

Power on to Port-3 has been received.

Power off request for Port-3. This bit indicates whether power-off to Port-3 has been received. This bit

generates a PWOFF interrupt (If enabled).

PWOFF = 0 MCU can clear this bit by writing a 1. (Writing 0 has no effect)

PWOFF = 1 Power off to Port-3 has been received

Function resume request bit

RESR = 0

RESR = 1

MCU can clear this bit by writing a 1. (Writing 0 has no effect)

Function resume is detected

6

7

SUSR

RSTR

0

Function suspended request bit. This bit is set in response to a global or selective suspend condition.

SUSR =0 MCU can clear this bit by writing a 1. (Writing 0 has no effect)

SUSR =1 Function suspend is detected.

Function reset request bit. This bit is set in response to host initiating a port reset. This bit is not affected by

USB function reset.

RSTR = 0 MCU can clear this bit by writing a 1. (Writing 0 has no effect)

RSTR = 1 Function reset is detected.

2–14

2.6.3 USBMSK: USB Interrupt Mask Register

7

6

5

4

3

2

1

0

RSTR

R/W

SUSR

R/W

RESR

R/W

PWOFF

R/W

PWON

R/W

SETUP

R/W

RSV

R/O

STPOW

R/W

BIT

NAME

RESET

FUNCTION

0

STPOW

0

SETUP overwrite interrupt enable bit

STPOW = 0 STPOW interrupt disabled

STPOW = 1 STPOW interrupt enabled

1

2

RSV

0

Reserved = 0

SETUP

SETUP interrupt enable bit

SETUP = 0 SETUP interrupt disabled

SETUP = 1 SETUP interrupt enabled

3

4

5

6

7

PWON

PWOFF

RESR

SUSR

RSTR

0

Power-on interrupt enable bit

PWON = 0 PWON interrupt disabled

PWON = 1 PWON interrupt enabled

Power-off interrupt enable bit

PWOFF = 0 PWOFF interrupt disabled

PWON = 1 PWOFF interrupt enabled

Function resume interrupt enable

RESR = 0 function resume interrupt disabled

RESR = 1 function resume interrupt enabled

Function suspend interrupt enable

SUSR = 0 function suspend interrupt disabled

SUSR = 1 function suspend interrupt enabled

Function reset interrupt enable

RSTR = 0 function reset interrupt disabled

RSTR = 1 function reset interrupt enabled

2–15

2.6.4 USBCTL: USB Control Register

Unlike the other registers, this register is cleared by the power-up-reset signal only. The USB-reset cannot reset this

register. (See Figure 2–3: Reset Diagram)

7

6

5

4

3

2

1

0

CONT

R/W

RSV

R/O

RWUP

R/W

FRSTE

R/W

RWE

R/W

B/S

R/W

SIR

R/W

DIR

R/W

BIT

NAME

RESET

FUNCTION

0

DIR

0

As a response to a setup packet, the MCU will decode the request and set or clear this bit to reflect the data

transfer direction.

DIR = 0 > USB data OUT transaction. (From host to TUSB3210)

DIR = 1 > USB data IN transaction. (From TUSB3210 to host)

1

SIR

0

SETUP interrupt status bit. This bit is controlled by the MCU to indicate to the hardware when SETUP

interrupt is being served.

SIR = 0

SETUP interrupt is not served. MCU will clear this bit before exiting the SETUP interrupt

routine.

SIR = 1

SETUP interrupt is in progress. MCU will set this bit when servicing the SETUP interrupt.

2

3

B/S

0

Bus/Self power control bit

B/S = 0 > The device is bus-powered

B/S = 1 > The device is self-powered

RWE

Remote wake-up enable bit.

RWE = 0

RWE = 1

MCU clears it when host sends command to clear the feature.

MCU writes 1 to it when host sends set device feature command to enable remote wake-up

feature

4

5

FRSTE

RWUP

1

0

Function reset connection bit. This bit connects/disconnects the USB function reset from the MCU reset.

FRSTE = 0 function reset is not connected to MCU reset

FRSTE = 1 function reset is connected to MCU reset

Device remote wake-up request. This bit is set by MCU and is cleared automatically.

RWUP = 0 Writing a 0 to this bit has no effect.

RWUP = 1 When MCU writes a 1, a Remote wake-up pulse is generated.

Reserved

6

7

RSV

0

CONT

Connect/Disconnect Bit

CONT = 0 Upstream port is disconnected. Pullup disabled

CONT = 1 Upstream port is connected. Pullup enabled

2.6.5 VIDSTA: VID/PID Status Register

Thisregisterisusedtoreadthevalueonfourexternalpins. Thefirmwarecanusethisvaluetoselectoneofthevendor

identification/product identifications (VID/PID) stored in memory. The TUSB3210/D supports up to 16 unique

VID/PIDs with application code to support different products. This provides a unique opportunity for original

equipment manufacturers (OEM) to have one device ROM programmed to support up to 16 different product lines

by using S0–S3 to select VID/PID and behavioral application code for the selected product.

7

6

5

4

3

2

1

0

RSV

R/O

RSV

R/O

RSV

R/O

RSV

R/O

S3

S2

S1

S0

R/O

BIT

NAME

RESET

FUNCTION

3–0

S[3:0]

x

VID/PID selection bits. These bits reflect the status of the external pins as defined by Table 2–7. Note that a

pin tied Low will be reflected as 0 and a pin tied high will be reflected as a 1.

7–4

RSV

0

Reserved = 0

2–16

Table 2–6. External Pins Mapping to S[3:0] in VIDSTA Register

NAME

VIDSTA REGISTER

COMMENTS

NO.

58

57

8

S[3:0]

S0

P3.0

P3.1

S2

Dual function P3.0 I/O or S0 input

Dual function P3.1 I/O or S1 input

S2-pin is input

S1

S2

9

S3

S3-pin is input

2.7 Function Reset and Power-Up Reset Interconnect

Figure 2–3 represents the logical connection of USB-function-reset (USBR) and power-up-reset (RST-pin). The

internal RESET signal is generated from the RST pin (PURS signal) or from the USB-reset (USBR signal). The USBR

can be enabled or disabled by the FRSTE bit in the USBCTL register (on power up FRSTE is = 0). The internal RESET

is used to reset all registers and logic, with the exception of the USBCTL and MISCTL registers. The USBCTL and

MCU configuration register (MCNFG) are cleared by PURS signal only.

USBCTL Register

MCNFG Register

All Internal MMR

RST

PURS

RESET

MCU

USBR

WDT Reset

USB Function Reset

WDE

FRSTE

Figure 2–3. Reset Diagram

2–17

2.8 Pullup Resistor Connect/Disconnect

After reading firmware into RAM the TUSB3210 can re-enumerate using the new firmware (no need to physically

disconnect and re-connect the cable). Figure 2–4 shows an equivalent circuit implementation for Connect and

Disconnect from a USB up-stream port (also see Firgure 4–4b). When CONT bit in USBCTL register is 1, the CMOS

driver sources VDD to the pullup resistor (PUR pin) presenting a normal connect condition to the USB hub (high

speed). When CONT bit is 0, PUR pin is driven low. In this state, the 1.5 kΩ resistor is connected to GND, resulting

in device disconnection state. The PUR driver is a CMOS driver that can provide (VDD–0.1) volt minimum at 8 mA

source current.

CMOS

PUR

CONT-Bit

1.5 kΩ

TUSB2036A

D+

D–

DP0

DM0

15 kΩ

HUB

TUSB3210

Figure 2–4. Pullup Resistor Connect/Disconnect Circuit

2.9 8052 Interrupt and Status Registers

All 8052 standard 5 interrupt sources are preserved. SIE is the standard interrupt enable register, which controls the

five interrupt sources. All the additional interrupt sources are connected together as an OR to generate EX0. XINTO#

signal is provided to interrupt an external MCU (see Interrupt connection diagram, Figure 2–5).

Table 2–7. 8052 Interrupt Location Map

INTERRUPT

SOURCE

DESCRIPTION

START

ADDRESS

COMMENTS

ES

ET1

EX1

ET0

EX0

Reset

UART interrupt

Timer–1 interrupt

Internal INT1

0023H

001BH

0013H

000BH

0003H

0000H

Used for P2[7:0] interrupt

Timer–0 interrupt

Internal INT0

Used for all internal peripherals

2–18

2.9.1 8052 Standard Interrupt Enable Register

7

6

5

4

3

2

1

0

EA

RSV

R/O

RSV

R/O

ES

ET1

R/W

EX1

R/W

ET0

R/W

EX0

R/W

BIT

NAME

RESET

FUNCTION

0

EX0

0

Enable or disable external interrupt-0

EX0 = 0 external interrupt-0 is disabled

EX0 = 1 external interrupt-0 is enabled

1

2

3

4

ET0

EX1

ET1

ES

0

Enable or disable timer-0 interrupt

ET0 = 0 timer-0 interrupt is disabled

ET0 = 1 timer-0 interrupt is enabled

Enable or disable external interrupt-1

EX1 = 0 external interrupt-1 is disabled

EX1 = 1 external interrupt-1 is enabled

Enable or disable timer-1 interrupt

ET1 = 0 timer-1 interrupt is disabled

ET1 = 1 timer-1 interrupt is enabled

Enable or disable serial port interrupts

ES = 0 serial port interrupt is disabled

ES = 1 serial port interrupt is enabled

5,6

7

RSV

EA

0

Reserved

Enable or disable all interrupts (global disable)

EA = 0 disable all interrupts

EA = 1 each interrupt source is individually controlled.

2.9.2 Additional Interrupt Sources

2

All nonstandard 8052 interrupts (USB, I C, etc.) are connected as an OR to generate an internal INT0. It must be

noted that the external INT0 and INT1 are not used. Furthermore, INT0 must be programmed as an active low level

interrupt (not edge triggered). A vector interrupt register is provided to identify all interrupt sources (see vector

interrupt register definition). Up to 64 interrupt vectors are provided. It is the responsibility of the MCU to read the

vector and dispatch the proper interrupt routine.

2–19

2.9.3 VECINT: Vector Interrupt Register

This register contains a vector value identifying the internal interrupt source that trapped to location 0003H. Writing

any value to this register removes the vector and update the next vector value (if another interrupt is pending). Note

that the vector value is offset. Therefore, its value is in increments of two (bit-0 is set to 0). When no interrupt is

pending, the vector is set to 00h. (see Table 2–8: Vector Interrupt Values). As shown, the interrupt vector is divided

into two fields; I[2:0] and G[3:0]. The I-field defines the interrupt source within a group (on first come first served basis)

and the G-field, which defines the group number. Group G0 is the lowest and G15 is the highest priority.

7

6

5

4

3

I2

2

I1

1

I0

0

G3

G2

G1

G0

R/W

R/O

BIT

NAME

RESET

FUNCTION

3–1

I[2:0]

000

This field defines the interrupt source in a given group. See Table 2–8: Vector Interrupt Values.

Bit-0 is always = 0, therefore, vector values will be offset by two.

7–4

G[3:0]

0000

This field defines the interrupt group. I[2:0] and G[3:0] combine to produce the actual interrupt vector.

Table 2–8. Vector Interrupt Values

G[3:0]

(Hex)

I[2:0]

(Hex)

VECTOR

(Hex)

INTERRUPT SOURCE

0

1

0

00

10

No interrupt

NOT USED

1

12

Output endpoint-1

Output endpoint-2

Output endpoint-3

NOT USED

1

2

14

1

3

16

1

4–7

0

18–1E

20

2

NOT USED

2

1

22

Input endpoint-1

Input endpoint-2

Input endpoint-3

NOT USED

2

24

2

3

26

2

4–7

0

28–2E

30

3

STPOW packet received

SETUP packet received

PWON interrupt

PWOFF interrupt

RESR interrupt

SUSR interrupt

RSTR interrupt

RESERVED

3

1

32

3

2

34

3

36

3

4

38

3

5

3A

3

6

3C

3

7

3E

4

0

40

I2C TXE interrupt

I2C RXF interrupt

Input endpoint–0

Output endpoint–0

NOT USED

4

1

42

4

2

44

4

3

46

4

4–7

X

48 → 4E

90 → FE

5–15

NOT USED

2–20

2.9.4 Logical Interrupt Connection Diagram (INT0)

Figure 2–5 represents the logical connection of the interrupt sources and its relation with XINTO#. The priority

encoder generates an 8-bit vector, corresponding to 64 interrupt sources (not all are used). The interrupt priorities

are hard wired. Vector 4E is the highest and 00 is the lowest.

Interrupts

Priority

Encoder

EX0

Vector

Figure 2–5. Internal Vector Interrupt (EX0)

2.9.5 P2[7:0] Interrupt (INT1)

Figure2–6illustratestheconceptualPort-2interrupt. AllPort-2inputsignalsareconnectedinalogicalORtogenerate

INT1 interrupt. Note that the inputs are active low and INT1 is programed as an edge-triggered interrupt. In addition,

INT1 is connected to the suspend/resume logic for remote wake-up support. As illustrated, XINT-bit in MCU

configuration register (MCNFG) is used to select the EXI interrupt source. When XINT = 0, P3.3 is the source, and

when XINT = 1, P2[7:0] is the source.

P2[7:0]

EX1

(INT1)

Suspend/

Resume

Logic

1

P3.3

XINT-Bit

Figure 2–6. P2[7:0] Input Port Interrupt Generation

2–21

2.10 I2C Registers

2.10.1 I2CSTA: I2C Status and Control Register

This register is used to control the stop condition for read and write operation. In addition, it provides transmitter and

receiver handshake signals with their respective interrupt enable bits.

7

6

5

4

3

2

1

0

RXF

R/C

RIE

R/W

ERR

R/C

1/4

R/W

TXE

R/C

TIE

R/W

SRD

R/W

SWR

R/W

BIT

NAME

RESET

FUNCTION

0

SWR

0

Stopwrite condition. This bit defines if the I2C controller generates a stop condition when data from I2CDAO

register is transmitted to an external device.

SWR = 0 Stop condition is not generated when data from I2CDAO register is shifted out to an external

device.

SWR = 1 Stopcondition is generated when data from I2CDAO register is shifted out to an external device.

1

SRD

0

Stop read condition. This bit defines if the I2C controller will generate a stop condition when data is received

and loaded into I2CDAI register.

SRD = 0 Stop condition is not generated when data from SDA line is shifted into I2CDAI register.

SRD = 1 Stop condition is generated when data from SDA line is shifted into I2CDAI register.

2

3

TIE

0

1

I C transmitter empty interrupt enable.

TIE = 0 Interrupt disable

TIE = 1 Interrupt enable

2

TXE

I Ctransmitterempty. Thisbitindicatesthatdatacanbewrittentothetransmitter. Itcanbeusedforpollingor

it can generate an interrupt.

TXE = 0 Transmitter is full. This bit is cleared when MCU writes a byte to I2CDAO register.

TXE = 1 Transmitter is empty. The I2C controller sets this bit when the content of I2CDAO register is

copied to the SDA shift–register.

4

5

1/4

0

Bus speed selection.

¼ = 0 > 100 kHz bus speed

¼ = 1 > 400 kHz bus speed

ERR

Bus error condition. This bit is set by the hardware when the device does not respond. It is cleared by the

MCU.

ERR = 0 No bus error

ERR = 1 Bus error condition has been detected. Clears when MCU writes a 1. Writing a 0 has no effect.

2

6

7

RIE

0

I C receiver ready interrupt enable.

RIE = 0 Interrupt disable

RIE = 1 Interrupt enable

2

RXF

I C receiver full. This bit indicates that the receiver contains new data. It can be used for polling or it can

generate an interrupt.

RXF = 0 Receiver is empty. This bit is cleared when MCU reads the I2CDAI register.

RXF = 1 Receivercontainsnewdata. ThisbitissetbytheI2Ccontrollerwhenthereceivedserialdatahas

been loaded into I2CDAI register

2–22

2.10.2 I2CADR: I2C Address Register

This register holds the device address and the read/write command bit.

7

6

5

4

3

2

1

0

A

0

R/W

6

5

4

3

2

1

R/W

BIT

NAME

RESET

FUNCTION

0

R/W

0

Read/write command bit.

R/W = 0 Write operation

R/W = 1 Read operation

7–1

A[6:0]

0000000 Seven address bits for device addressing.

2.10.3 I2CDAI: I2C Data-Input Register

This register holds the received data from an external device.

7

6

5

4

3

2

1

0

D

0

7

6

5

4

3

2

1

R/O

BIT

NAME

RESET

FUNCTION

7–0

D[7:0]

0

8-bit input data from an I2C device

2.10.4 I2CDAO: I2C Data-Output Register

This register holds the data to be transmitted to an external device. Writing to this register starts the transfer on the

SDA line.

7

6

5

4

3

2

1

0

D7

D6

D5

D4

D3

D2

D1

D0

R/W

BIT

NAME

RESET

FUNCTION

7–0

D[7:0]

0

8-bit output data to an I2C device

2.11 Read/Write Operations

2.11.1 Read Operation (Serial EEPROM)

A serial read requires a dummy byte write sequence to load in the 16-bit data word address. Once the device address

word and data word address is clocked out and acknowledged by the device, the MCU starts a current address

sequence. The following describes the sequence of events to accomplish this transaction:

Device Address + EEPROM [High-byte]

•

MCU sets I2CSTA[SRD] = 0. This forces the I2C controller not to generate a stop condition after the content

of I2CDAI register is received.

•

MCU sets I2CSTA[SWR] = 0. This forces the I2C controller to NOT generate a stop condition after the

content of I2CDAO register is transmitted.

•

MCU writes the device address (R/W bit = 0) to I2CADR register (write operation)

MCU writes the High-Byte of the EEPROM address into I2CDAO register, starting the transfer on SDA line

TXE bit in I2CSTA is cleared, indicating busy

2–23

•

The content of I2CADR register is transmitted to the EEPROM (preceded by start condition on SDA)

The content of I2CDAO register is transmitted to the EEPROM (EEPROM address)

TXE bit in I2CSTA is set, and interrupts the MCU, indicating that I2CDAO register has been transmitted

No stop condition is generated

EEPROM [Low-byte]

•

MCU writes the Low-byte of the EEPROM address into I2CDAO register

TXE bit in I2CSTA is cleared, indicating busy

The content of I2CDAO register is transmitted to the device (EEPROM address)

TXE bit in I2CSTA is set, and interrupts the MCU, indicating that I2CDAO register has been transmitted

This completes the dummy write operation. At this point, the EEPROM address is set and the MCU can do

a single or a sequential read operation.

2.11.2 Current Address Read Operation

Once the EEPROM address is set the MCU can read a single byte by executing the following steps:

1. MCU sets I2CSTA[SRD] = 1, forcing the I2C controller to generate a stop condition after I2CDAI register

is received.

2. MCU writes the device address (R/W bit = 1) to I2CADR register (read operation).

3. MCU writes a dummy byte to I2CDAO register, starting the transfer on SDA line

4. RXF bit in I2CSTA is cleared

5. The content of I2CADR register is transmitted to the device, preceded by start condition on SDA

6. Data from the EEPROM is latched in I2CDAI register (stop condition is transmitted)

7. RXF bit in I2CSTA is set, and interrupt the MCU, indicating that the data is available.

8. MCU reads I2CDAI register. This clears RXF bit (I2CSTA[RXF] = 0)

9. END

2.11.3 Sequential Read Operation

Once the EEPROM address is set, the MCU can execute a sequential read operation by executing the following steps

(Note: this example illustrates 32-byte sequential read):

1. Device Address

•

MCU sets I2CSTA[SRD] = 0. This forces the I2C controller to not generate a stop condition after I2CDAI

register is received

•

MCU writes the device address (R/W bit = 1) to I2CADR register (read operation)

MCU writes a dummy byte to I2CDAO register, starting the transfer on SDA line

RXF bit in I2CSTA is cleared

The content of I2CADR register is transmitted to the device (preceded by start condition on SDA)

2. N-Byte Read (31-bytes)

•

Data from the device is latched in I2CDAI register (stop condition is not transmitted)

RXF bit in I2CSTA is set, and interrupt the MCU, indicating that data is available

2–24

•

MCU reads I2CDAI register, clearing RXF bit (I2CSTA[RXF] = 0)

This operation repeats 31 times

3. Last-Byte read (byte No. 32)

•

MCU sets I2CSTA[SRD] = 1. This forces the I2C controller to generate a stop condition after I2CDAI

register is received

•

Data from the device is latched in I2CDAI register (Stop condition is transmitted)

RXF bit in I2CSTA is set, and interrupt the MCU, indicating that data is available

MCU reads I2CDAI register, clearing RXF bit (I2CSTA[RXF] = 0)

END

2.11.4 Write Operation (Serial EEPROM)

Byte write operation involves three phases: 1) device address + EEPROM [High–byte] phase, 2) EEPROM

[Low–byte] phase, and 3) EEPROM [DATA]. The following describes the sequence of events to accomplish the byte

write transaction:

Device Address + EEPROM [High-byte]

•

MCU sets I2CSTA[SWR] = 0. This forces the I2C controller to not generate a stop condition after the content

of I2CDAO register is transmitted.

•

MCU writes the device address (R/W bit = 0) to I2CADR register (write operation)

MCU writes the high-byte of the EEPROM address into I2CDAO register, starting the transfer on SDA line

TXE bit in I2CSTA is cleared, indicating busy

The content of I2CADR register is transmitted to the device (preceded by start condition on SDA)

The content of I2CDAO register is transmitted to the device (EEPROM high-address)

TXE bit in I2CSTA is set, and interrupts the MCU, indicating that I2CDAO register has been transmitted

EEPROM [Low-byte]

•

MCU writes the low–byte of the EEPROM address into I2CDAO register

TXE bit in I2CSTA is cleared, indicating busy

The content of I2CDAO register is transmitted to the device (EEPROM address)

TXE bit in I2CSTA is set, and interrupts the MCU, indicating that I2CDAO register has been transmitted

EEPROM [DATA]

•

MCU sets I2CSTA[SWR] = 1. This forces the I2C controller to generate a stop condition after the content

of I2CDAO register is transmitted.

•

MCU writes the DATA to be written to the EEPROM into I2CDAO register

TXE bit in I2CSTA is cleared, indicating busy

The content of I2CDAO register is transmitted to the device (EEPROM data)

TXE bit in I2CSTA is set, and interrupts the MCU, indicating that I2CDAO register has been transmitted

I2C controller generates a stop condition after the content of I2CDAO register is transmitted

END

2–25

2.11.5 Page Write Operation

Page write operation is initiated the same way as byte write, with the exception that stop condition is not generated

after the first EEPROM [DATA] is transmitted. The following describes the sequence of writing 32-bytes in page mode:

Device Address + EEPROM [High-byte]

•

MCU sets I2CSTA[SWR] = 0. This forces the I2C controller to not generate a stop condition after the content

of I2CDAO register is transmitted.

•

MCU writes the device address (R/W bit = 0) to I2CADR register (write operation)

MCU writes the high-byte of the EEPROM address into I2CDAO register.

TXE bit in I2CSTA is cleared, indicating busy

The content of I2CADR register is transmitted to the device (preceded by start condition on SDA)

The content of I2CDAO register is transmitted to the device (EEPROM address)

TXE bit in I2CSTA is set, and interrupt the MCU, indicating that I2CDAO register has been sent.

EEPROM [Low-byte]

•

MCU writes the low-byte of the EEPROM address into I2CDAO register

TXE bit in I2CSTA is cleared, indicating busy

The content of I2CDAO register is transmitted to the device. (EEPROM address)

TXE bit in I2CSTA is set, and interrupts the MCU, indicating that I2CDAO register has been sent.

31 Bytes EEPROM [DATA]

•

MCU writes the DATA to be written to the EEPROM into I2CDAO register

TXE bit in I2CSTA is cleared, indicating busy

The content of I2CDAO register is transmitted to the device (EEPROM data)

TXE bit in I2CSTA is set, and interrupts the MCU, indicating that I2CDAO register has been sent.

This operation repeats 31 times.

Last Byte EEPROM [DATA]

•

MCU sets I2CSTA[SWR] = 1. This forces the I2C controller to generate a stop condition after the content

of I2CDAO register is transmitted.

•

MCU writes the last DATA byte to be written to the EEPROM into I2CDAO register

TXE bit in I2CSTA is cleared, indicating busy

The content of I2CDAO register is transmitted to the EEPROM (EEPROM data)

TXE bit in I2CSTA is set, and interrupts the MCU, indicating that I2CDAO register has been sent

I2C controller generates a stop condition after the content of I2CDAO register is transmitted

END of 32-byte page write operation

2–26

3 Electrical Specifications

3.1 Absolute Maximum Ratings Over Operating Free-Air Temperature

†

(unless otherwise noted)

Supply voltage, V

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 4 V

CC

Input voltage, V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to V

+ 0.5 V

I

CC

Output voltage, V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to V

O

Input clamp current, I . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±20 mA

IK

OK

Output clamp current, I

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±20 mA

Storage temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150°C

†

Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and

functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not

implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

3.2 Commercial Operating Condition

PARAMETER

MIN NOM

MAX

UNIT

V

Supply voltage

3

0

2

0

3.3

3.6

CC

Input voltage

V

I

CC

High level input voltage

Low level input voltage

Operating temperature

V

IH

IL

CC

0.8

V

T

A

70

°C

3.3 Electrical Characteristics, T = 25°C, V

= 3.3 V ± 0.3V, GND = 0 V

A

CC

PARAMETER

TEST CONDITIONS

MIN NOM

MAX

UNIT

V

OH

V

OL

V

IT+

V

IT–

V

hys

High-level output voltage

I

= –4 mA

V –0.5

CC

OH

Low-level output voltage

= 4 mA

0.5

2

V

OL

Positive input threshold voltage

Negative input threshold voltage

V = V

V

I

IH

IL

V = V

I

0.8

V

Hysteresis (V

IT+

– V

)

V = V

I

1

V

IT–

I

High-level input current

Low-level input current

V = V

I

±1

10

µA

pF

mA

µA

IH

V = V

I

IL

Output Leakage Current (Hi-Z)

Input capacitance

Output capacitance

Quiescent

V = V

I

or V

CC SS

OZ

C

5

7

I

O

I

25

45

CC

Suspend

CCx

3–1

3–2

4 Application

4.1 Examples

Figure 4–1 illustrates the Port-3 pins that are assigned to drive the four example LEDs. For the connection example

shown, P3[7:4] can sink up to 12 mA (open-drain output). Figure 4–2 illustrates the partial connection bus power

mode. Figure 4–3 shows the USB upstream connection, and Figure 4–4 illustrates the downstream connection (only

one port shown).

V

CC

TUSB3210

P3.2

P3.3

P3.4

P3.5

Figure 4–1. Example LED Connection

C5

C4

V

CC

R4

TPS76333

VR

X1

X2

5 V

C1

V

SCL

SDA

CC

EPROM

C2

CC

C3

R5

TUSB3210

R1

R2

V

CC

V

DDOUT

VREN

SUSP

R3

Figure 4–2. Partial Connection Bus Power Mode

4–1

PUR

Bus PWR

(5 V)

3.3 V

1.5 kΩ

DP0

DM0

DP0

DM0

D+

D–

(a)

(b)

Figure 4–3. Upstream Connection (a) Non-Switching Power Mode (b) Switching Power Mode

5 V

To Power Switch

DP1

DM1

R1

R2

D+

D–

15 kΩ

GND

NOTE: Ferrite beads can be used on power lines to help ESD.

Figure 4–4. Downstream Connection – (Only One Port Shown)

4.2 Reset Timing

There are two requirements for the reset signal timing. First, the reset window should be between 100 msec and 10

msec. At power up, this time is measured from the time the power ramps up to 90% of the nominal Vcc until the reset

signal goes high (above 1.2 V). The second requirement is that the clock has to be valid during the last 60 msec of

the reset window. These two requirements are depicted in Figure 4–5. Notice that when using a 12 MHz crystal or

the 48 MHz oscillator, the clock signal may take several milliseconds to ramp up and become valid after power up.

Therefore, the reset window may need to be elongated up to 10 msec. to ensure that there is a 60 msec overlap with

a valid clock.

V

CC

3.3 V

CLK

90%

RESET

1.2 V

0 V

t

>60 µs

100 µs < RESET TIME < 10 ms

Figure 4–5. Reset Timing

4–2

5 Mechanical Data

PM (S-PQFP-G64)

PLASTIC QUAD FLATPACK

0,27

0,17

0,50

48

M

0,08

33

49

32

64

17

0,13 NOM

1

16

7,50 TYP

Gage Plane

10,20

SQ

9,80

0,25

12,20

SQ

0,05 MIN

0°–ā7°

11,80

1,45

1,35

0,75

0,45

Seating Plane

1,60 MAX

0,08

4040152/C 11/96

NOTES: A. All linear dimensions are in millimeters.

B. This drawing is subject to change without notice.

C. Falls within JEDEC MS-026

D. May also be thermally enhanced plastic with leads connected to the die pads.

5–1

5–2


型号：	TUSB3210
厂家：	TEXAS INSTRUMENTS
描述：	UNIVERSAL SERIAL BUS GENERAL-PURPOSE DEVICE CONTROLLER 通用串行总线通用设备控制器控制器
文件：	总44页 (文件大小：172K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

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