TPS65982BBZBHR [TI]
带集成 5V 负载开关且适用于 USB-PD 设备的双 USB 告示板 | ZBH | 96 | -10 to 85;型号: | TPS65982BBZBHR |
厂家: | TEXAS INSTRUMENTS |
描述: | 带集成 5V 负载开关且适用于 USB-PD 设备的双 USB 告示板 | ZBH | 96 | -10 to 85 开关 光电二极管 |
文件: | 总44页 (文件大小:1225K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
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TPS65982BB
SLVSER3A –NOVEMBER 2018–REVISED APRIL 2020
TPS65982BB Dual USB Billboard for USB-PD Devices with Integrated 5-V Load Switch
1 Features
2 Applications
1
•
Port-power switch
•
•
•
•
•
Docking systems
Charger adapters
–
–
–
5-V, 3-A integrated switch to VBUS
Over-current limiter, over-voltage protector
Slew-rate control
USB PD devices
USB PD–enabled bus-powered devices
DisplayPort, Thunderbolt
•
USB low-speed endpoint
–
–
I2C-update capable billboard strings
3 Description
Integrated USB mux supports two Type-C
ports
The TPS65982BB device provides a USB billboard
endpoint for USB-PD devices implementing alternate
modes. The integrated internal USB multiplexor
allows the TPS65982BB to support up to two USB
Type-C ports. The TPS65982BB communicates with
USB-PD port controllers using an I2C interface to
enable the billboard as well as update stored
billboard strings. An integrated 5-V load switch
provides VBUS protection for an optional USB Type-
A port.
–
I2C control
•
•
Power management
Power supply from 3.3-V
NFBGA package
–
–
–
0.5-mm pitch
Through-hole via compatible for all pins
Device Information(1)
PART
NUMBER
PACKAGE
BODY SIZE (NOM)
TPS65982BB NFBGA (96)
6.00 mm × 6.00 mm
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
Simplified Diagram
D+/-
2
USB
Type-C
Connector
5 V
VBUS
3 A
TPS65982BB
3.3 V
USB
Type-C
Connector
USB PA
USB PB
PD
Controller
I2C
Interface
Billboard
D+/-
2
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
TPS65982BB
SLVSER3A –NOVEMBER 2018–REVISED APRIL 2020
www.ti.com
Table of Contents
1
2
3
4
5
6
Features.................................................................. 1
Applications ........................................................... 1
Description ............................................................. 1
Revision History..................................................... 2
Pin Configuration and Functions......................... 3
Specifications......................................................... 6
6.1 Absolute Maximum Ratings ...................................... 6
6.2 ESD Ratings.............................................................. 6
6.3 Recommended Operating Conditions....................... 7
6.4 Thermal Information.................................................. 7
6.5 Power Supply Characteristics ................................... 8
6.6 Power Supervisor Characteristics............................. 9
6.7 Power Consumption Characteristics......................... 9
6.8 Port-Power Switch Characteristics............................ 9
6.9 Port-Data Multiplexer Characteristics ..................... 10
6.10 Port-Data Multiplexer Clamp Characteristics........ 10
7
8
Parameter Measurement Information ................ 14
Detailed Description ............................................ 16
8.1 Overview ................................................................. 16
8.2 Functional Block Diagram ....................................... 17
8.3 Feature Description................................................. 17
8.4 Device Functional Modes........................................ 24
Application and Implementation ........................ 29
9.1 Application Information............................................ 29
9.2 Typical Application .................................................. 29
9
10 Power Supply Recommendations ..................... 31
10.1 3.3-V Power .......................................................... 31
10.2 1.8-V Core Power ................................................. 31
10.3 VDDIO................................................................... 32
11 Layout................................................................... 33
11.1 Layout Guidelines ................................................. 33
11.2 Layout Example .................................................... 33
12 Device and Documentation Support ................. 37
12.1 Documentation Support ........................................ 37
12.2 Receiving Notification of Documentation Updates 37
12.3 Support Resources ............................................... 37
12.4 Trademarks........................................................... 37
12.5 Electrostatic Discharge Caution............................ 37
12.6 Glossary................................................................ 37
6.11 Port-Data Multiplexer Signal Monitoring Pullup and
Pulldown Characteristics.......................................... 10
6.12 USB Endpoint Characteristics............................... 11
6.13 Input/Output (I/O) Characteristics ......................... 11
6.14 I2C Slave Characteristics ...................................... 12
6.15 Thermal Shutdown Characteristics ....................... 13
6.16 Oscillator Characteristics ...................................... 13
6.17 SPI Master Switching Characteristics................... 13
6.18 Typical Characteristics.......................................... 14
13 Mechanical, Packaging, and Orderable
Information ........................................................... 37
4 Revision History
Changes from Original (November 2018) to Revision A
Page
•
First public release as a catalog device ................................................................................................................................ 1
2
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SLVSER3A –NOVEMBER 2018–REVISED APRIL 2020
5 Pin Configuration and Functions
ZBH Package
96-Pin NFBGA
Transparent Top View
1
2
3
4
5
6
7
8
9
10
11
A
B
C
D
E
F
G
H
J
GND
LDO_1V8D
SPI_CLK
SPI_MISO
I2C2_SDA
GND
GND
GND
NC
SENSE
PP_5V0
VDDIO
I2C1_IRQz
I2C1_SDA
LDO_BMC
I2C_ADDR
LDO_3V3
VIN_3V3
GND
NC
NC
SPI_SSz
SPI_MOSI
I2C2_SCL
I2C2_IRQz
GND
GND
NC
SENSE
PP_5V0
PP_5V0
PP_5V0
NC
NC
I2C1_SCL
GND
GND
GND
GND
GND
HRESET
NC
GND
GND
GND
SS
GND
GND
GND
GND
GND
NC
NC
GND
GND
NC
NC
NC
GND
VIN_3V3
BB_EN
GND
VBUS
NC
NC
R_OSC
VOUT_3V3
GND
NC
GND
PP_5V0_EN
GND
CONFIG
VBUS
VBUS
K
L
LDO_1V8A BB_PLUG_PB BB_BOOT_OK
GND
GND
USB_RP_N
USB_RP_P
PA_USB_P
PA_USB_N
PB_USB_P
PB_USB_N
GND
GND
NC
NC
VBUS
GND
BB_PLUG_PA
BB_SRST
NC
NC
Not to scale
Pin Functions
PIN
POR
STATE
TYPE
DESCRIPTION
NAME
NO.
A11, B11,
C11, D11
5-V supply for VBUS. Bypass with capacitance CPP_5V0 to GND. Tie pin to GND when
unused.
PP_5V0
VBUS
Power
Power
—
—
H11, J10,
J11, K11
5-V output from PP_5V0. Bypass with capacitance CVBUS to GND.
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Pin Functions (continued)
PIN
POR
STATE
TYPE
DESCRIPTION
NAME
NO.
H1, F10
B1
VIN_3V3
VDDIO
Power
Power
—
—
Supply for core circuitry and I/O. Bypass with capacitance CVIN_3V3 to GND.
VDD for I/O.
Output of supply switched from VIN_3V3. Bypass with capacitance COUT_3V3 to GND.
Float pin when unused.
VOUT_3V3
LDO_3V3
H2
G1
Power
Power
—
—
Output of the VBUS to 3.3 V LDO or connected to VIN_3V3 by a switch. Main internal
supply rail. Used to power optional external flash memory. Bypass with capacitance
CLDO_3V3 to GND.
Output of the 3.3-V or 1.8-V LDO for core analog circuits. Bypass with capacitance
CLDO_1V8A to GND.
LDO_1V8A
LDO_1V8D
K1
A2
Power
Power
—
—
Output of the 3.3-V or 1.8-V LDO for core digital circuits. Bypass with capacitance
CLDO_1V8D to GND.
LDO_BMC
PA_USB_P
PA_USB_N
PB_USB_P
PB_USB_N
E1
K6
L6
K7
L7
Power
—
Output of the 1.1V output level LDO. Bypass with capacitance CLDO_BMC to GND.
Port A USB D+ connection.
Analog I/O
Analog I/O
Analog I/O
Analog I/O
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Port A USB D- connection.
Port B USB D+ connection.
Port B USB D- connection.
System-side USB2.0 high-speed connection to port multiplexer. Ground pin with between 1-
kΩ and 5-MΩ resistance when unused.
USB_RP_P
USB_RP_N
L5
K5
Analog I/O
Analog I/O
Hi-Z
Hi-Z
System-side USB2.0 high-speed connection to port multiplexer. Ground pin with between 1-
kΩ and 5-MΩ resistance when unused.
SENSE
SENSE
B10
A10
Analog input
Analog input
Analog input
Analog input
Short pin to VBUS.
Short pin to VBUS.
Analog
output
SS
H7
G2
Driven low
Hi-Z
Soft Start. Tie pin to capacitance CSS to ground.
External resistance setting for oscillator accuracy. Connect R_OSC to GND through
resistance RR_OSC.
R_OSC
Analog I/O
PP_5V0_EN
CONFIG
G11
H6
Digital I/O
Hi-Z
Hi-Z
Input enable signal for PP_5V0 power path.
Boot Configuration pin. Tie directly to ground.
Analog input
Output. Driven high once the TPS65982BB has completed its boot and configuration
routines.
BB_BOOT_OK
K3
Digital I/O
Hi-Z
BB_EN
G10
L3
Digital I/O
Digital I/O
Digital I/O
Digital I/O
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Input. When driven high enables billboard output on PA_USB_P and PA_USB_N.
Input. When asserted high, initiates a soft reset of the TPS65982BB.
BB_SRST
BB_PLUG_PB
BB_PLUG_PA
K2
L2
Input. Signals the TPS65982BB to enable the USB billboard on the PA_USB pins.
Input. Signals the TPS65982BB to enable the USB billboard on the PB_USB pins.
Active high hardware reset input. Assertion causes a reboot sequence. Ground pin when
HRESET functionality will not be used.
HRESET
D6
D1
D2
C1
A5
B5
Digital Input
Digital I/O
Digital I/O
Hi-Z
I2C port 1 serial data. Open-drain output. Tie pin to LDO_3V3 or VDDIO (depending on
configuration) through a 10-kΩ resistance when used or unused.
I2C_SDA1
I2C_SCL1
I2C_IRQ1Z
I2C_SDA2
I2C_SCL2
Digital input
Digital input
Hi-Z
I2C port 1 serial clock. Open-drain output. Tie pin to LDO_3V3 or VDDIO (depending on
configuration) through a 10-kΩ resistance when used or unused.
I2C port 1 interrupt. Active low. Implement externally as an open drain with a pullup
resistance. Float pin when unused.
Digital
output
I2C port 2 serial data. Open-drain output. Tie pin to LDO_3V3 or VDDIO (depending on
configuration) through a 10-kΩ resistance when used or unused.
Digital I/O
Digital I/O
Digital input
Digital input
I2C port 2 serial clock. Open-drain output. Tie pin to LDO_3V3 or VDDIO (depending on
configuration) through a 10-kΩ resistance when used or unused.
I2C port 2 interrupt. Active low. Implement externally as an open drain with a pullup
resistance. Float pin when unused.
Digital
output
I2C_IRQ2Z
I2C_ADDR
SPI_CLK
B6
F1
A3
Hi-Z
Sets the I2C address for both I2C ports.
Analog I/O
Analog input
Digital input
Digital
output
SPI serial clock. Ground pin when unused
Digital
output
SPI_MOSI
SPI_MISO
B4
A4
Digital input
Digital input
SPI serial master output to slave. Ground pin when unused.
SPI serial master input from slave. This pin is used during boot sequence to determine if
the optional flash memory is valid. Refer to the Device Functional Modes section for more
details. Ground pin when unused.
Digital input
4
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SLVSER3A –NOVEMBER 2018–REVISED APRIL 2020
Pin Functions (continued)
PIN
POR
STATE
TYPE
DESCRIPTION
NAME
NO.
Digital
output
SPI_SSZ
B3
Digital input
SPI slave select. Ground pin when unused.
A1, A6, A7,
A8, B7, B8,
D5, D8, E4,
E5, E6, E7,
E8, F5, F6,
F7, F8, G5,
G6, G7, G8,
H4, H5, H8,
H10, J1, J2,
K4, K8, L1,
L4, L8
GND
Ground
NA
Ground. Connect all balls to ground plane.
A9, B2, B9,
C2, C10,
D7, D10,
E2, E10,
E11, F2, F4,
F11, G4,
NC
Blank
NA
Populated Ball that must remain unconnected.
K9, K10, L9,
L10, L11
C3, C4, C5,
C6, C7, C8,
C9, D3, D4,
D9, E3, E9,
F3, F9, G3,
G9, H3, H9,
J3, J4, J5,
J6, J7, J8,
J9
No Ball
Blank
NA
Unpopulated Ball for A1 marker and unpopulated inner ring.
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6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)(1)
MIN
–0.3
–0.3
–0.3
–0.3
–0.3
–0.3
–0.3
–0.3
MAX
UNIT
PP_5V0
VIN_3V3
6
3.6
VI
Input voltage(2)
V
SENSE
6
VDDIO
LDO_3V3 + 0.3
LDO_1V8A, LDO_1V8D, LDO_BMC
2
VIO Output voltage(2)
LDO_3V3
3.45
V
V
VOUT_3V3, I2C _IRQ1Z, I2C_IRQ2Z, SPI_MOSI, SPI_CLK, SPI_SSZ, I2C_ADDR
VBUS
LDO_3V3 + 0.3
6
I2C_SDA1, I2C_SCL1, SPI_MISO, I2C_SDA2, I2C_SCL2, USB_RP_P, USB_RP_N,
CONFIG, PP_5V0_EN, BB_BOOT_OK, BB_SRST, BB_PLUG_PB, BB_PLUG_PA
–0.3
LDO_3V3 + 0.3
2
VIO I/O voltage(2)
R_OSC
–0.3
-0.3
–2
HRESET
LDO_1V8D + 0.3
PA_USB_P, PA_USB_N, PB_USB_P, PB_USB_N (Switches Open)
PA_USB_P, PA_USB_N, PB_USB_P, PB_USB_N (Switches Closed)
6
–0.3
–10
–55
6
TJ
Operating junction temperature
125
150
°C
°C
Tstg Storage temperature
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) All voltage values are with respect to network GND. All GND pins must be connected directly to the GND plane of the board.
6.2 ESD Ratings
VALUE
UNIT
Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1)
±1500
V(ESD)
Electrostatic discharge
V
Charged-device model (CDM), per JEDEC specification JESD22-
C101(2)
±500
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process. Manufacturing with
less than 500-V HBM is possible with the necessary precautions.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process. Manufacturing with
less than 250-V CDM is possible with the necessary precautions.
6
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6.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
MIN
2.85
4.75
1.7
MAX
3.45
5.5
UNIT
VIN_3V3
Input voltage(1) PP_5V0
VI
V
VDDIO
3.45
5.5
VBUS
4
VIO
I/O voltage(1)
V
PA_USB_P, PA_USB_N, PB_USB_P, PB_USB_N
–2
5.5
TA
TB
TJ
Ambient operating temperature
Operating board temperature
Operating junction temperature
–10
–10
–10
85
°C
°C
°C
100
125
(1) All voltage values are with respect to network GND. All GND pins must be connected directly to the GND plane of the board.
6.4 Thermal Information
TPS65982BB
THERMAL METRIC(1)
ZBH (NFBGA)
UNIT
96 PINS
42.4
12.4
13
RθJA
RθJC(top)
RθJB
ψJT
Junction-to-ambient thermal resistance
Junction-to-case (top) thermal resistance
Junction-to-board thermal resistance
°C/W
°C/W
°C/W
°C/W
°C/W
Junction-to-top characterization parameter
Junction-to-board characterization parameter
0.3
ψJB
13
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
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6.5 Power Supply Characteristics
Recommended operating conditions; TA = –10 to +85°C unless otherwise noted
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
EXTERNAL
VIN_3V3
VBUS
Input 3.3-V supply
2.85
4
3.3
5
3.45
5.5
V
V
Output DC bus voltage.
5-V supply input to power VBUS. This supply
does not power the TPS65982BB
PP_5V0
4.75
1.7
5
5.5
V
V
VDDIO(1)
Optional supply for I/O cells
3.45
INTERNAL
DC 3.3 V generated internally by either a switch
from VIN_3V3, an LDO from PP_CABLE, or an
LDO from VBUS
VLDO_3V3
2.7
3.3
3.45
V
VLDO_1V8D
VLDO_1V8A
DC 1.8 V generated for internal digital circuitry
DC 1.8 V generated for internal analog circuitry
1.7
1.7
1.8
1.8
1.9
1.9
V
V
DC voltage generated on LDO_BMC. Setting for
USB-PD.
VLDO_BMC
IOUT_3V3
1.05 1.125
1.2
V
External DC current supplied by VOUT_3V3
100
mA
DC current supplied by LDO_1V8D. This is
intended for internal loads only but small external
loads may be added
ILDO_1V8D
50
5
mA
mA
mA
ILDO_1V8DEX External DC current supplied by LDO_1V8D
DC current supplied by LDO_1V8A. This is
intended for internal loads only but small external
loads may be added
ILDO_1V8A
20
ILDO_1V8AEX External DC current supplied by LDO_1V8A
5
5
mA
mA
mA
mV
DC current supplied by LDO_BMC. This is
ILDO_BMC
intended for internal loads only
ILDO_BMCEX
VFWD_DROP
External DC current supplied by LDO_BMC
0
Forward voltage drop across VIN_3V3 to
LDO_3V3 switch
ILOAD = 50 mA
25
60
1.1
90
Input switch resistance from VIN_3V3 to
LDO_3V3
RIN_3V3
VVIN_3V3 – VLDO_3V3 > 50 mV
0.5
1.75
0.7
Ω
Ω
Output switch resistance from VIN_3V3 to
VOUT_3V3
ROUT_3V3
TR_OUT3V3
0.35
10-90% rise time on VOUT_3V3 from switch
enable
CVOUT_3V3 = 1 μF
35
120
µs
(1) I/O buffers are not fail-safe to LDO_3V3. Therefore, VDDIO may power-up before LDO_3V3. When VDDIO powers up before LDO_3V3,
the I/Os shall not be driven high. When VDDIO is low and LDO_3V3 is high, the I/Os may be driven high.
8
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6.6 Power Supervisor Characteristics
Recommended operating conditions; TA = –10 to +85°C unless otherwise noted
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
Undervoltage threshold for LDO_3V3. Locks out 1.8-V
LDOs
UV_LDO3V3
LDO_3V3 rising
2.2
2.325
2.45
V
UVH_LDO3V3
UV_5V0
Undervoltage hysteresis for LDO_3V3
Undervoltage threshold for PP_5V0
Undervoltage hysteresis for PP_P5V0
Overvoltage threshold for VBUS.
LDO_3V3 falling
PP_5V0 rising
PP_5V0 falling
VBUS rising
20
3.5
20
5
80
3.725
80
150
3.95
150
24
mV
V
UVH_5V0
OV_VBUS
mV
V
Overvoltage threshold step for VBUS. This value is the
LSB of the programmable threshold
OVLSB_VBUS
VBUS rising
328
mV
OVH_VBUS
UV_VBUS
Overvoltage hysteresis for VBUS
Undervoltage threshold for VBUS.
VBUS falling, % of OV_VBUS
VBUS falling
0.9%
2.5
1.3%
1.7%
18.21
V
Undervoltage threshold step for VBUS. This value is the
LSB of the programmable threshold
UVLSB_VBUS
UVH_VBUS
VBUS falling
249
mV
Undervoltage hysteresis for VBUS
VBUS rising, % of UV_VBUS
0.9%
1.3%
1.7%
6.7 Power Consumption Characteristics
Recommended operating conditions; TA = 25°C (Room temperature) unless otherwise noted(1)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
VIN_3V3 = VDDIO = 3.45 V, VBUS = 0, 100-kHz
oscillator running
IVIN_3V3 in sleep
71
µA
VIN_3V3 = VDDIO = 3.45 V, VBUS=0, 100-kHz
oscillator running,
IVIN_3V3 idle
2.2
mA
48-MHz oscillator running
VIN_3V3 = VDDIO = 3.45 V, VBUS = 0, 100-kHz
Oscillator running,
IVIN_3V3 active
5.3
mA
48-MHz oscillator running
(1) Application code can result in other power consumption measurements by adjusting enabled circuitry and clock rates. Application code
also provisions the wake-up mechanisms (for example, I2C activity and GPIO activity).
6.8 Port-Power Switch Characteristics
Recommended operating conditions; TA = –10 to +85°C unless otherwise noted
PARAMETER
TEST CONDITIONS(1)
MIN
TYP
MAX
60
UNIT
mΩ
mA
μA
RPP5V
PP_5V0 to VBUS power switch resistance
Active quiescent current from PP_5V0
Shutdown quiescent current from PP_5V0
PP_5V0 current limit
50
IPP5VACT
IPP5VSD
ILIMPP5V
1
100
3.69
3.019
1.95
3.355
3
I = 100 mA, reverse current
blocking disabled
4.05
A/V
IPP5V_ACC(2)
PP_5V0 current sense accuracy
I = 200 mA
I = 500 mA
I ≥ 1 A
2.4
2.64
2.7
3
3
3
3.6
3.36
3.3
A/V
A/V
A/V
Configured as a source or as a
sink with soft start disabled.
PP_5V0 = 5 V, CVBUS = 10 μF,
ILOAD = 100 mA
PP_5V0 path turn on time from enable to
VBUS = 95% of PP_5V0 voltage
TON_5V
2.5
ms
Reverse-current blocking voltage threshold for
PP_5V0 switches
VREV5V0
VSAFE0V
2
0
6
10
mV
V
Voltage that is a safe 0 V per USB-PD
Specifications
0.8
(1) Maximum capacitance on VBUS when configured as a source must not exceed 12 µF.
(2) The current sense in the ADC does not accurately read below the current VREV5V0/RPP5V or VREVHV/RPPHV because of the
reverse blocking behavior. When reverse blocking is disabled, the values given for accuracy are valid.
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6.9 Port-Data Multiplexer Characteristics
Recommended operating conditions; TA = –10 to +85°C unless otherwise noted
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
USB_RP MULTIPLEXER PATH(1)(2)
Vi = 3 V, IO = 20 mA
4.5
3
10
7
USB_RON
On resistance of USB_RP to Px_USB_P/N
Ω
Ω
Vi = 400 mV, IO = 20 mA
On-resistance difference between P and N paths of
USB_RP to Px_USB_P/N
USB_ROND
Vi = 0.4 V to 3 V, IO = 20 mA
–0.15
0.15
150
15
Time from enable bit with charge
pump off
USB_TON
Switch-on time from enable of USB USB_RP path
µs
Time from enable bit at charge-
pump steady state
Time from disable bit at charge-
pump steady state
USB_TOFF
USB_BW
Switch-off time from disable of USB_RP path
3-dB bandwidth of USB_RP path
500
ns
MHz
dB
CL = 10 pF
850
RL = 50 Ω, VI = 800 mV, f = 240
MHz
USB_ISO
USB_XTLK
Off isolation of USB_RP path
–19
–26
Channel-to-channel crosstalk of USB_RP path
RL = 50 Ω, f = 240 MHz
dB
(1) All RON specified maximums are the maximum of either of the switches in a pair. All ROND specified maximums are the maximum
difference between the two switches in a pair. ROND does not add to RON.
(2) See the USB Endpoint Characteristics table for the USB_EP specifications.
6.10 Port-Data Multiplexer Clamp Characteristics
Recommended operating conditions; TA = –10 to +85°C unless otherwise noted
PARAMETER
TEST CONDITIONS
MIN
3.8
10
TYP
MAX UNIT
VCLMP_IND
ICLMP_IND
Clamp voltage triggering indicator to the digital core
Clamp current at VCLMP_IND
3.95
4.1
V
250
μA
Time from clamp-current crossing ICLMP_IND to
interrupt signal assertion
TCLMP_PRT(1)
I ≥ ICLMP_IND rising
0
4
μs
V = LDO_3V3
250
15
nA
ICLMP
USB_EP and USB_RP port-clamp current
V = VCLMP_IND + 500 mV
3.5
mA
(1) The TCLMP_PRT time includes the time through the digital synchronizers. When the clock speed is reduced, the signal assertion time
can be longer.
6.11 Port-Data Multiplexer Signal Monitoring Pullup and Pulldown Characteristics
Recommended operating conditions; TA = –10 to +85°C unless otherwise noted
PARAMETER
TEST CONDITIONS
LDO_3V3 = 3.3 V
MIN
350
3.5
70
TYP
500
5
MAX UNIT
RPU05
RTPU5
RPU100
500-Ω pullup and pulldown resistance
5-kΩ pullup and pulldown resistance
100-kΩ pullup and pulldown resistance
650
6.5
Ω
LDO_3V3 = 3.3 V
LDO_3V3 = 3.3 V
kΩ
kΩ
100
130
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6.12 USB Endpoint Characteristics
Recommended operating conditions; TA = –10 to +85°C unless otherwise noted
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
TRANSMITTER(1)
T_RISE_EP
Rising transition time
Low-speed (1.5 Mbps) data rate only
Low-speed (1.5 Mbps) data rate only
Low-speed (1.5 Mbps) data rate only
75
75
300
300
25%
2
ns
ns
T_FALL_EP
Falling transition time
T_RRM_EP
Rise and fall time matching
Output crossover voltage
–20%
1.3
V_XOVER_EP
V
Source resistance of driver including 2nd-stage port-
data multiplexer
RS_EP
34
Ω
DIFFERENTIAL RECEIVER(1)
VOS_DIFF_EP
VIN_CM_EP
RPU_EP
Input offset
–100
0.8
100
2.5
mV
V
Common-mode range
D– bias resistance
Receiving
1.425
1.575
kΩ
SINGLE ENDED RECEIVER(1)
VTH_SE_EP
Single ended threshold
Single ended threshold hysteresis
Signal rising or falling
Signal falling
0.8
2
V
VHYS_SE_EP
200
mV
(1) The USB endpoint PHY is functional across the entire VIN_3V3 operating range, but parameter values are only verified by design for
VIN_3V3 ≥ 3.135 V
6.13 Input/Output (I/O) Characteristics
Recommended operating conditions; TA = –10 to +85°C unless otherwise noted
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
SPI
SPI_VIH
SPI_VIL
SPI_HYS
SPI_ILKG
High-level input voltage
Low-level input voltage
Input hysteresis voltage
Leakage current
LDO_3V3 = 3.3 V
2
V
V
LDO_3V3 = 3.3 V
0.8
1
LDO_3V3 = 3.3 V
0.2
–1
V
Output is Hi-Z, VIN = 0 to LDO_3V3
IO = –8 mA, LDO_3V3=3.3 V
IO = –15 mA, LDO_3V3=3.3 V
IO = 10 mA
μA
2.9
2.5
SPI_VOH
SPI output high voltage
SPI output low voltage
V
V
0.4
0.8
SPI_VOL
IO = 20 mA
GPIO, MRESET
GPIO_VIH
LDO_3V3 = 3.3 V
VDDDIO = 1.8 V
LDO_3V3 = 3.3 V
VDDIO = 1.8 V
2
High-level input voltage
Low-level input voltage
Input hysteresis voltage
V
V
V
1.25
0.8
GPIO_VIL
0.63
LDO_3V3 = 3.3 V
VDDIO = 1.8 V
0.2
0.09
–1
GPIO_HYS
GPIO_ILKG
GPIO_RPU
GPIO_RPD
GPIO_DG
I/O leakage current
Pullup resistance
INPUT = 0 V to VDD
Pullup enabled
1
150
150
μA
kΩ
kΩ
ns
50
100
100
20
Pulldown resistance
Digital input path deglitch
Pulldown enabled
50
IO = –2 mA, LDO_3V3 = 3.3 V
IO = –2 mA, VDDIO = 1.8 V
IO = 2 mA, LDO_3V3 = 3.3 V
IO = 2 mA, VDDIO = 1.8 V
2.9
GPIO_VOH
GPIO_VOL
GPIO output high voltage
GPIO output low voltage
V
V
1.35
0.4
0.45
HRESET
HRESET_VIH
HRESET_VIL
HRESET_HYS
HRESET_ILKG
High-level input voltage
Low-level input voltage
Input hysteresis Voltage
I/O leakage current
1.25
V
V
0.63
1
0.09
–1
V
INPUT = 0 V to LDO_1V8D
μA
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Input/Output (I/O) Characteristics (continued)
Recommended operating conditions; TA = –10 to +85°C unless otherwise noted
PARAMETER
TEST CONDITIONS
MIN
0.6
TYP
MAX
UNIT
HRESET_THIGH
HRESET_TLOW
HRESET minimum high time to assert a reset condition.
HRESET minimum low time to deassert a reset condition.
ms
0.6
I2C_IRQ1Z, I2C_IRQ2Z
OD_VOL
OD_LKG
Low-level output voltage
Leakage current
IOL = 2 mA
0.4
1
V
Output is Hi-Z, VIN = 0 to LDO_3V3
–1
μA
6.14 I2C Slave Characteristics
Recommended operating conditions; TA = –10 to +85°C unless otherwise noted
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
SDA and SCL COMMON CHARACTERISTICS
ILEAK
Input leakage current
Voltage on pin = LDO_3V3
IOL = 3 mA, LDO_3V3 = 3.3 V
IOL = 3 mA, VDDIO = 1.8 V
VOL = 0.4 V
-3
3
0.4
μA
VOL
SDA output low voltage
V
0.36
3
6
IOL
SDA maximum output-low current
Input low signal
mA
V
VOL = 0.6 V
LDO_3V3 = 3.3 V
VDDIO = 1.8 V
0.99
0.54
VIL
LDO_3V3 = 3.3 V
VDDIO = 1.8 V
2.31
1.26
0.17
0.09
VIH
Input high signal
V
LDO_3V3 = 3.3 V
VDDIO = 1.8 V
VHYS
Input hysteresis
V
I2C pulse width suppressed
Pin Capacitance
TSP
CI
50
10
ns
pF
SDA and SCL STANDARD MODE CHARACTERISTICS
I2C clock frequency
FSCL
0
4
100
kHz
μs
I2C clock high time
THIGH
I2C clock low time
TLOW
4.7
250
0
μs
I2C serial data-setup time
TSUDAT
ns
ns
μs
I2C serial data-hold time
THDDAT
I2C valid data time
TVDDAT
SCL low to SDA output valid
3.4
3.4
ACK signal from SCL low to SDA
(out) low
I2C valid data time of ACK condition
TVDACK
μs
I2C output fall time
TOCF
10 pF to 400 pF bus
250
ns
μs
μs
μs
μs
I2C bus free time between stop and start
TBUF
4.7
4.7
4
I2C start or repeated start condition setup time
TSTS
I2C start or repeated start condition hold time
TSTH
I2C stop-condition setup time
TSPS
4
SDA and SCL FAST MODE CHARACTERISTICS
I2C clock frequency
FSCL
0
0.6
1.3
100
0
400
kHz
μs
I2C clock high time
THIGH
I2C clock low time
TLOW
μs
I2C serial data-setup time
TSUDAT
ns
ns
μs
I2C serial data-hold time
THDDAT
I2C valid data time
TVDDAT
SCL low to SDA output valid
0.9
0.9
ACK signal from SCL low to SDA
(out) low
I2C valid data time of ACK condition
TVDACK
μs
10 pF to 400 pF bus, VDD = 3.3 V
10 pF to 400 pF bus, VDD = 1.8 V
12
6.5
1.3
250
250
I2C output fall time
TOCF
ns
I2C bus free time between stop and start
TBUF
μs
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I2C Slave Characteristics (continued)
Recommended operating conditions; TA = –10 to +85°C unless otherwise noted
PARAMETER
TEST CONDITIONS
MIN
0.6
0.6
0.6
TYP
MAX
UNIT
μs
I2C start or repeated start condition setup time
I2C start or repeated start condition hold time
I2C stop-condition setup time
TSTS
TSTH
TSPS
μs
μs
6.15 Thermal Shutdown Characteristics
Recommended operating conditions; TA = –10 to +85°C unless otherwise noted
PARAMETER
TEST CONDITIONS
MIN
TYP
160
20
MAX UNIT
TSD_MAIN
TSDH_MAIN
TSD_PWR
TSDH_PWR
TSD_DG
Thermal shutdown temperature of the main thermal shutdown Temperature rising
145
175
165
0.1
°C
°C
°C
°C
ms
Thermal shutdown hysteresis of the main thermal shutdown
Thermal shutdown temperature of the power-path block
Thermal shutdown hysteresis of the power-path block
Programmable thermal shutdown detection deglitch time
Temperature falling
Temperature rising
Temperature falling
135
150
37
6.16 Oscillator Characteristics
Recommended operating conditions; TA = –10 to +85°C unless otherwise noted
PARAMETER
48-MHz oscillator
FOSC_100K 100-kHz oscillator
TEST CONDITIONS
MIN
47.28
95
TYP
MAX UNIT
FOSC_48M
48 48.72
MHz
kHz
100
105
14.98
5
15.01
5
RR_OSC
External oscillator set resistance (0.2%)
15
kΩ
6.17 SPI Master Switching Characteristics
Recommended operating conditions; TA = –10 to +85°C unless otherwise noted
PARAMETER
Frequency of SPI_CLK
TEST CONDITIONS
MIN
TYP
MAX UNIT
FSPI
11.82
12 12.18
MHz
ns
TPER
Period of SPI_CLK (1/F_SPI)
82.1 83.33
84.6
TWHI
SPI_CLK high width
30
30
30
160
–5
21
0
ns
TWLO
SPI_CLK low width
ns
TDACT
TDINACT
TDMOSI
TSUMISO
THDMSIO
SPI_SZZ falling to SPI_CLK rising delay time
SPI_CLK falling to SPI_SSZ rising delay time
SPI_CLK falling to SPI_MOSI Valid delay time
SPI_MISO valid to SPI_CLK falling setup time
SPI_CLK falling to SPI_MISO invalid hold time
50
180
5
ns
ns
ns
ns
ns
10% to 90%, CL = 5 pF to 50 pF,
LDO_3V3 = 3.3 V
TRSPI
TFSPI
SPI_SSZ/CLK/MOSI rise time
SPI_SSZ/CLK/MOSI fall time
0.1
0.1
8
8
ns
ns
90% to 10%, CL = 5 pF to 50 pF,
LDO_3V3 = 3.3 V
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6.18 Typical Characteristics
41
40
39
38
37
36
35
34
33
32
-10
0
10 20 30 40 50 60 70 80 90 100
Temperature (èC)
D001
Figure 1. PP_5V0 Switch On-Resistance vs Temperature
7 Parameter Measurement Information
t
f
t
r
t
SU;DAT
70 %
30 %
70 %
30 %
SDA
cont.
cont.
t
t
HD;DAT
VD;DAT
t
f
t
HIGH
t
r
70 %
30 %
70 %
30 %
70 %
30 %
70 %
30 %
SCL
t
HD;STA
t
LOW
th
9
clock
1 / f
S
SCL
st
1
clock cycle
t
BUF
SDA
SCL
t
VD;ACK
t
t
t
t
SU;STO
SU;STA
HD;STA
SP
70 %
30 %
Sr
P
S
th
9
clock
002aac938
Figure 2. I2C Slave Interface Timing
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Parameter Measurement Information (continued)
t
t
t
wlow
per
whigh
SPI_SSZ
SPI_CLK
t
t
dact
dinact
t
t
dmosi
dmosi
SPI_MOSI
SPI_MISO
Valid Data
t
sumiso
Valid Data
t
hdmiso
Figure 3. SPI Master Timing
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8 Detailed Description
8.1 Overview
The TPS65982BB is a USB billboard controller for USB Type-C systems. The integrated USB2 data multiplexer
allows the billboard controller to be switched between two USB Type-C ports or allows a USB2 device controller
to be passed through to the ports.
The TPS65982BB includes an integrated 5V load switch that may be used to supply VBUS power to an
additional USB Type-A receptacle. See the Port-Power Switches section for a high-level block diagram of the
port power switch, a description of the features, and more detailed circuitry.
The port-data multiplexer connects various input pairs to the system port through the PA_USB_P, PA_USB_N,
PB_USB_P, PB_USB_N pins. For a high-level block diagram of the port-data multiplexer, a description of the
features, and more detailed circuitry, refer to the USB Port-Data Multiplexer section.
The power-management circuitry receives and provides power to the TPS65982BB internal circuitry and to the
VOUT_3V3 and LDO_3V3 outputs. See the Power Management section for a high-level block diagram of the
power management circuitry, a description of the features, and more detailed circuitry.
The digital core provides the engine for handling control of all other TPS65982BB functionality. A portion of the
digital core contains ROM memory which contains all the firmware required to execute USB billboard behavior. In
addition, a section of the ROM, called boot code, is capable of initializing the TPS65982BB device, loading of
device configuration information, and loading any code patches into volatile memory in the digital core. See the
Digital Core section for a description of the features, and more detailed circuitry.
The TPS65982BB is an I2C slave to be controlled by a host processor (see the I2C Slave Interface section), and
an SPI master to write to and read from an optional external flash memory (see the SPI Master Interface
section).
The TPS65982BB device also integrates a thermal shutdown mechanism (see the Thermal Shutdown section)
and runs off of accurate clocks provided by the integrated oscillators (see the Oscillators section).
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8.2 Functional Block Diagram
PP_5V0
VBUS
3A
VDDIO
VIN_3V3
VOUT_3V3
HRESET
SS
LDO_3V3
LDO_1V8A
LDO_1V8D
LDO_BMC
Power & Supervisor
R_OSC
I2C_ADDR
CONFIG
BB_BOOT_OK
BB_SRST
BB_PLUG_PA
BB_PLUG_PB
PP_5V0_EN
3
3
4
I2C_SDA/SCL/IRQ1Z
I2C_SDA/SCL/IRQ2Z
SPI_MOSI/MISO/SSZ/CLK
Digital Core
2
2
PA_USB_P/N
PB_USB_P/N
2
USB_RP_P/N
Port Mux & Endpoint
GND
8.3 Feature Description
8.3.1 Port-Power Switches
Fast
current
limit
3A
PP_5V
VBUS
Gate Control and Sense
Figure 4. Port-Power Paths
8.3.1.1 5-V Power Delivery
The TPS65982BB device provides a power switch to VBUS from PP_5V0. The switch path provides 5 V at up to
3 A to from PP_5V0 to VBUS. Figure 4 shows a simplified circuit for the switch from PP_5V0 to VBUS.
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Feature Description (continued)
8.3.1.2 5-V Power Switch
The PP_5V0 path is unidirectional, only sourcing power from PP_5V0 to VBUS. When the switch is on, the
protection circuitry limits reverse current from VBUS to PP_5V0. Figure 5 shows the I-V characteristics of the
reverse-current protection feature. Figure 5 and the reverse-current limit can be approximated using Equation 1.
IREV5V0 = VREV5V0/RPP5V
(1)
I
1/RPP5V
VREV5V0
V
IREV5V0
Figure 5. 5V Switch I-V Curve
8.3.1.3 PP_5V0 Current Limit
The current through PP_5V0 to VBUS is limited to ILIMPP5V and is controlled automatically by the digital core.
When the current exceeds ILIMPP5V, the current-limit circuit activates. Depending on the severity of the
overcurrent condition, the transient response reacts in one of two ways: and Figure 7 show the approximate
response time and clamping characteristics of the circuit for a hard short while Figure 8 shows the shows the
approximate response time and clamping characteristics for a soft short with a load of 2 Ω.
12
10
8
6
5
4
3
2
1
0
I VBUS
VBUS
6
4
2
0
-2
-1
Time (5 ms/div)
D004
Figure 6. PP_5V0 Current Limit With a Hard Short
12
10
8
6
5
4
3
2
1
0
I VBUS
VBUS
6
4
2
0
-2
-1
Time (200 ms/div)
D005
Figure 7. PP_5V0 Current Limit With a Hard Short (Extended Time Base)
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Feature Description (continued)
6
5
4
3
2
1
0
6
I VBUS
VBUS
5
4
3
2
1
0
Time (200 ms/div)
D006
Figure 8. PP_5V0 Current Limit With a Soft Short (2 Ω)
8.3.1.4 VBUS Transition to VSAFE0V
When VBUS transitions to almost 0 V (VSAFE0V), the pulldown circuit in Figure 9 turns on until VBUS reaches
VSAFE0V. This transition occurs within the time, TSAFE0V.
PP_5V0 Gate Control
and Current Limit
PP_5V0
VBUS
Fast
current
limit
VHVDISPD
Slew Rate
Controlled
Pulldown
Figure 9. PP_5V0 Slew-Rate Control
8.3.2 USB Port-Data Multiplexer
The includes a USB2 data multiplexor capable of connecting the integrated USB billboard or USB_RP
passthrough to the USB2 D+ and D- pins of up to two USB Type-C connectors. The multiplexor connection state
is determined by the state of the BB_PLUG_PB and BB_PLUG_PA GPIO inputs. PA_USB_P, PA_USB_N
connect to the D+ and D- pins of the "Port A" type-c connector and PB_USB_P, PB_USB_N connect to the D+
and D- pins of the "Port B" type-c connector.
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Feature Description (continued)
PA_USB_P
PA_USB_N
USB_RP_P/N
PB_USB_P
PA_USB_N
USB_EP_P/N
Figure 10. Port-Data Multiplexers
8.3.2.1 Port Multiplexer Clamp
Each input to the multiplexer is clamped to prevent voltages on the port from exceeding the safe operating
voltage of circuits attached to the system side of the port data multiplexer. Figure 11 shows the simplified
clamping circuit. When a path through the multiplexer is closed, the clamp is connected to the one of the port
pins (PA_USB_P/N, PB_USB_P/N). When a path through the multiplexer is not closed, then the port pin is not
clamped. As the pin voltage rises above the VCLMP_IND voltage, the clamping circuit activates, and sinks
current to ground, preventing the voltage from rising further.
2nd Stage Mux Input
VREF
Figure 11. Port Mux Clamp
8.3.2.2 USB2.0 Low-Speed Endpoint
The USB low-speed endpoint is a USB 2.0 low-speed (1.5 Mbps) interface used to support HID class-based
accesses. The TPS65982BB device supports control of endpoint EP0. This endpoint enumerates to a USB 2.0
bus to provide USB-Billboard information to a host system as defined in the USB Type-C standard. EP0 is used
for advertising the Billboard Class. When a host is connected to a device that provides Alternate Modes that
cannot be supported by the host, the Billboard class allows a means for the host to report back to the user
without any silent failures.
Figure 12 shows the physical layer of the USB endpoint. The physical layer consists of the analog transceiver,
the serial interface engine, and the endpoint FIFOs. The physical layer supports low-speed operation.
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Feature Description (continued)
USB_EP
LDO_3V3
PA_USB_P
USB_RP
RPU_EP
PA_USB_N
RS_EP
RS_EP
EP_TX_DP
EP_TX_DN
EP0/EP1
TX/RX
FIFO
32
To M0+
USB_EP
EP_RX_RCV
Serial
Interface
Engine
PB_USB_P
USB_RP
RX/TX
Status
Control
Digital Core
Interrupts
& Control
PB_USB_N
EP_RX_DP
EP_RX_DN
Transceiver
Figure 12. USB Endpoint PHY
The transceiver is made up of a fully-differential output driver, a differential to single-ended receive buffer and
two single-ended receive buffers on the D+/D– independently. The output driver drives the D+/D– of the selected
output of the port multiplexer. The signals pass through the port-data multiplexer to the port pins. When driving,
the signal is driven through a source resistance RS_EP. RS_EP is shown as a single resistor in the USB
endpoint PHY but this resistance also includes the resistance of the port-data multiplexer defined in the Port-
Data Multiplexer Characteristics table. RPU_EP is disconnected during transmit mode of the transceiver.
When the endpoint is in receive mode, the resistance RPU_EP is connected to the D– pin of the A or B port
(PA_USB_N or PB_USB_N) depending on the detected orientation of the cable. The RPU_EP resistance
advertises low-speed mode only.
8.3.3 Power Management
The TPS65982BB power management block receives power and generates voltages to provide power to the
TPS65982BB internal circuitry. These generated power rails are LDO_3V3, LDO_1V8A, and LDO_1V8D. The
LDO_3V3 power rail is also a low power output to load an optional external flash memory. The VOUT_3V3
power rail is a low-power output that does not power internal circuitry that is controlled by the application code
and can be used to power other ICs in some applications. Figure 13 shows the power-supply path.
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Feature Description (continued)
VIN_3V3
VOUT_3V3
VREF
To Digital Core
LDO_3V3
VREF
EN
LDO_1V8D
LDO
LDO_1V8A_EN
VREF
EN
LDO_1V8A
LDO
LDO_1V8D_EN
Figure 13. Power Supply Path
The TPS65982BB device is powered from VIN_3V3. Current flows from VIN_3V3 to LDO_3V3 to power the core
3.3-V circuitry and the 3.3-V I/Os. A second LDO steps the voltage down from LDO_3V3 to LDO_1V8D and
LDO_1V8A to power the 1.8-V core digital circuitry and 1.8-V analog circuits.
8.3.3.1 Power-On and Supervisory Functions
A power-on-reset (POR) circuit monitors each supply. This POR allows the active circuitry to turn on only when a
good supply is present. In addition to the POR and supervisory circuits for the internal supplies, a separate
programmable voltage supervisor monitors the VOUT_3V3 voltage.
8.3.4 Digital Core
8.3.5 Power Reset-Control Module (PRCM)
The PRCM implements all clock management, reset control, and sleep-mode control.
8.3.6 Interrupt Monitor
The interrupt control module handles all interrupt from the external GPIO as well as interrupts from internal
analog circuits.
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Feature Description (continued)
8.3.7 I2C Slave
Two I2C interfaces provide interface to the digital core from the system. These interfaces operate as a slave and
support low-speed and full-speed signaling. See the I2C Slave Interface section for more information.
8.3.8 SPI Master
The SPI master provides a serial interface to an optional, external flash memory. The optional flash memory can
be used to store code patches and or device configurations. The recommended memory is the W25X05CL (64
KB) serial-flash memory. A memory of at least (24 KB) is required for the TPS65982BB device (shared or
unshared) if device configuration and patch memory features are used. See the SPI Master Interface section for
more information.
8.3.9 Thermal Shutdown
The TPS65982BB device has both a central thermal shutdown to the chip and a local thermal shutdown for the
power-path block. The central thermal shutdown monitors the temperature of the center of the die and disables
all functions except for supervisory circuitry. This shutdown also halts digital core when die temperature goes
above a rising temperature of TSD_MAIN. The temperature shutdown has a hysteresis of TSDH_MAIN and
when the temperature falls back below this value, the device resumes normal operation. The power-path block
has a local thermal-shutdown circuit to detect an overtemperature condition because of overcurrent, and quickly
turns off the power switches. The power-path thermal shutdown values are TSD_PWR and TSDH_PWR. The
output of the thermal shutdown circuit is deglitched by TSD_DG before triggering. The thermal shutdown circuits
generate interrupt events to the digital core.
8.3.10 Oscillators
The TPS65982BB device has two independent oscillators for generating internal clock domains. A 48-MHz
oscillator generates clocks for the core during normal operation and clocks for the USB 2.0 endpoint physical
layer. An external resistance is placed on the R_OSC pin to set the oscillator accuracy. A 100-kHz oscillator
generates clocks for various timers and clocking the core during low-power states.
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8.4 Device Functional Modes
8.4.1 SPI Master Interface
The TPS65982BB device loads any ROM patch, configuration or both from flash memory during the sequence.
The SPI master electrical characteristics are defined in SPI Master Switching Characteristics and timing
characteristics are defined in Figure 3. The TPS65982BB device is designed to power the flash from LDO_3V3,
and therefore pullup resistors used for the flash memory must be tied to LDO_3V3. The flash memory IC must
support a 12-MHz SPI clock frequency. The size of the flash must be at least 24 KB to hold the maximum ROM
patch and configuration code outlined in the section. The SPI master of the TPS65982BB device supports SPI
Mode 0. For Mode 0, data delay is defined such that data is output on the same cycle as the chip select
(SPI_SSZ pin) becomes active. The chip select polarity is active-low. The clock phase is defined such that data
(on the SPI_MISO and SPI_MOSI pins) is shifted out on the falling edge of the clock (SPI_CLK pin) and data is
sampled on the rising edge of the clock. The clock polarity for chip select is defined such that when data is not
being transferred the SPI_CLK pin is held (or idling) low. The minimum erasable sector size of the flash must be
4 KB. The W25X05CL device or similar is recommended.
8.4.2 I2C Slave Interface
The TPS65982BB device has two I2C interface ports. I2C port 1 is comprised of the I2C_SDA1, I2C_SCL1, and
I2C_IRQ1Z pins. I2C port 2 is comprised of the I2C_SDA2, I2C_SCL2, and I2C_IRQ2Z pins. These interfaces
provide general-status information about the TPS65982BB device and about the ability to control the
TPS65982BB behavior.
8.4.2.1 I2C Interface Description
The TPS65982BB device supports standard and fast mode I2C interface. The bidirectional I2C bus consists of the
serial clock (SCL) and serial data (SDA) lines. Both lines must be connected to a supply through a pullup
resistor. The data transfer can only be initiated when the bus is not busy.
A master sending a start condition (a high-to-low transition on the SDA I/O) while the SCL input is high initiates
I2C communication. After the Start Condition, the device address byte is sent, most significant bit (MSB) first,
including the data direction bit (R/W).
After receiving the valid address byte, this device responds with an acknowledge (ACK), a low on the SDA I/O
during the high of the ACK-related clock pulse. On the I2C bus, only one data bit is transferred during each clock
pulse. The data on the SDA line must remain stable during the high pulse of the clock period as changes in the
data line at this time are interpreted as control conditions (START or STOP). The master sends a Stop Condition,
a low-to-high transition on the SDA I/O while the SCL input is high.
Any number of data bytes can be transferred from the transmitter to receiver between the start and the stop
conditions. Each byte of eight bits is followed by one ACK bit. The transmitter must release the SDA line before
the receiver can send an ACK bit. The device that acknowledges, must pull down the SDA line during the ACK
clock pulse, so that the SDA line remains low during the high pulse of the ACK-related clock period. When a
slave receiver is addressed, it must generate an ACK after each byte is received. Similarly, the master must
generate an ACK after each byte that it receives from the slave transmitter. Setup and hold times must be met to
ensure proper operation
A master receiver signals an end of data to the slave transmitter by not generating an acknowledge (NACK) after
the last byte has been clocked out of the slave. The master receiver holding the SDA line high does this. In this
event, the transmitter must release the data line to enable the master to generate a stop condition.
Figure 14 shows the start and stop conditions of the transfer. Figure 15 shows the SDA and SCL signals for
transferring a bit. Figure 16 shows a data transfer sequence with the ACK or NACK at the last clock pulse.
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Device Functional Modes (continued)
SDA
SCL
S
P
Start Condition
Stop Condition
Figure 14. I2C Definition of Start and Stop Conditions
SDA
SCL
Data Line
Change
Figure 15. I2C Bit Transfer
Data Output
by Transmitter
Nack
Data Output
by Receiver
SCL From
Master
Ack
1
2
8
9
S
Clock Pulse for
Acknowledgement
Start
Condition
Figure 16. I2C Acknowledgment
8.4.2.2 I2C Clock Stretching
The TPS65982BB device features clock stretching for the I2C protocol. The TPS65982BB slave I2C port can hold
the clock line (SCL) low after receiving (or sending) a byte, indicating that the slave is not yet ready to process
more data. The master communicating with the slave must not finish the transmission of the current bit and must
wait until the clock line actually goes high. When the slave is clock stretching, the clock line remains low.
The master must wait until it observes the clock line transitioning high plus an additional minimum time (4 μs for
standard 100 kbps I2C) before pulling the clock low again.
Any clock pulse can be stretched but typically it is the interval before or after the acknowledgment bit.
8.4.2.3 I2C Address Setting
The boot code sets the hardware configurable unique I2C address of the TPS65982BB device before the port is
enabled to respond to I2C transactions. For the I2C1 interface, the unique I2C address is determined by the
analog level set by the analog I2C_ADDR strap pin (three bits) as listed in Table 1.
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Device Functional Modes (continued)
Table 1. I2C Default Unique Address I2C1(1)
Bit 7
0
Bit 6
1
Bit 5
1
Bit 4
1
Bit 3
Bit 2
Bit 1
Bit 0
R/W
I2C_ADDR_DECODE[2:0]
(1) Any bit is maskable for each port independently providing firmware override of the I2C address.
For the I2C2 interface, the unique I2C address is determined by the analog level set by the analog I2C_ADDR
strap pin (three bits) as listed in Table 2.
Table 2. I2C Default Unique Address I2C2(1)
Bit 7
0
Bit 6
1
Bit 5
0
Bit 4
0
Bit 3
Bit 2
Bit 1
Bit 0
R/W
I2C_ADDR_DECODE[2:0]
(1) ny bit is maskable for each port independently, providing firmware override of the I2C address.
8.4.2.4 Unique-Address Interface
The unique-address interface allows for complex interaction between an I2C master and a single TPS65982BB
device. The I2C slave sub-address is used to receive or respond to the protocol commands of the host interface.
Figure 17 and Figure 18 show the write and read protocol for the I2C slave interface. Figure 19 provides a key to
explain the terminology used. The key to the protocol diagrams is in the SMBus specification and is repeated
here in part.
1
7
1
1
8
1
8
1
8
1
Unique Address
Register Number
Byte Count = N
Data Byte 1
S
Wr
A
A
A
A
8
1
8
1
Data Byte 2
Data Byte N
A
A
P
Figure 17. I2C Unique Address-Write Register Protocol
1
7
1
1
8
1
1
7
1
1
8
1
S
Unique Address
Wr
A
Register Number
A
Sr
Unique Address
Rd
A
Byte Count = N
A
8
1
8
1
8
1
A
1
Data Byte 1
A
Data Byte 2
A
Data Byte N
P
Figure 18. I2C Unique Address-Read Register Protocol
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1
7
1
1
A
x
8
1
A
x
1
S
Slave Address
Wr
Data Byte
P
S
Start Condition
SR
Rd
Wr
x
Repeated Start Condition
Read (bit value of 1)
Write (bit value of 0)
Field is required to have the value x
Acknowledge (this bit position may be 0 for an ACK or
1 for a NACK)
A
P
Stop Condition
Master-to-Slave
Slave-to-Master
Continuation of protocol
Figure 19. I2C Read/Write Protocol Key
8.4.2.5 I2C Pin Address Setting
To enable the setting of multiple I2C addresses using a single TPS65982BB pin, a resistance is placed externally
on the I2C_ADDR pin. The internal ADC then decodes the address from this resistance value. Figure 20 shows
the decoding.
5µA
I2C_ADDR
ADC
R_I2C
Figure 20. I2C Address Decode
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Table 3 lists the external resistance required to set bits [3:1] of the I2C unique address.
Table 3. I2C Address Resistance
TPS65982BB
DEVICE
EXTERNAL
RESISTANCE (1%)
I2C UNIQUE
ADDRESS [3:1]
Device 0
Device 7
Device 6
Device 5
Device 4
Device 3
Device 2
Device 1
0
0x00
0x01
0x02
0x03
0x04
0x05
0x06
0x07
38.3k
84.5k
140k
205k
280k
374k
Open
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9 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
9.1 Application Information
The TPS65982BB is controlled through I2C and GPIO to perform the billboard function for two USB Type-C ports.
The external flash is connected through SPI to the TPS65982BB and contains the firmware to execute the
billboard function. Alternatively, an embedded controller (EC) or PD controller is capable of loading the firmware
to the TPS65982BB through I2C. Generally the PD controller is used to control the TPS65982BB through GPIO
and I2C as the PD controller is managing the USB Type-C ports.
9.2 Typical Application
U2
VBUS
G11
J10
J11
H11
K11
PP_5V0_EN
VBUS
VBUS
VBUS
VBUS
PP_5V0_EN
LDO_3V3
C10
1uF
C9 22uF
SYS_5V0
D11
C11
B11
A11
PP_5V0
PP_5V0
PP_5V0
PP_5V0
C11
0.1uF
R5
3.3k
R6
3.3k
R7
3.3k
R8
3.3k
U3
VCC
8
1
6
5
2
3
7
GND
A10
B10
DI/IO0
SENSE
SENSE
GND
DO/IO1
WP/IO2
HOLD/IO3
CS
CLK
L2
L5
K5
BB_PLUG_PA
USB_RP_P
USB_RP_N
BB_PLUG_PA
USB_RP_P
USB_RP_N
GND
4
K6
L6
GND
PA_USB_P
PA_USB_N
PA_USB_P
PA_USB_N
K3
L3
BB_BOOT_OK
BB_SRST
BB_BOOT_OK
BB_SRST
W25Q80DVSNIG
D6
R9
15.0k
HRESET
HRESET
GND
K7
L7
PB_USB_P
PB_USB_N
PB_USB_P
PB_USB_N
H7
G2
H6
B1
F10
H1
H2
G1
K1
C12
0.22 µF
15.0k
0
SS
R_OSC
R10
15.0k
K2
R11
R12
BB_PLUG_PB
BB_PLUG_PB
A3
B4
A4
B3
SPI_CLK
CONFIG
SPI_CLK
SPI_SSZ
SPI_MOSI
SPI_MISO
SPI_SSZ
SPI_MOSI
SPI_MISO
SYS_3V3
GND
VDDIO
VIN_3V3
VIN_3V3
VOUT_3V3
LDO_3V3
LDO_1V8A
LDO_1V8D
LDO_BMC
B5
A5
B6
I2C2_SCL
I2C2_SDA
I2C2_IRQZ
EC_I2C_SCL2
EC_I2C_SDA2
EC_I2C_IRQ2
C13
4.7uF
LDO_3V3
D2
D1
C1
LDO_3V3
I2C1_SCL
I2C1_SDA
I2C1_IRQZ
PD_CONTROLLER_I2C_SCL1
PD_CONTROLLER_I2C_SDA1
PD_CONTROLLER_I2C_IRQ1
C14
C15
C16
C17
10uF
4.7uF
4.7uF
4.7uF
R13
3.3k
R14
F1
I2C_ADDR
3.3k
R15
3.3k
A2
E1
EC_I2C_SCL2
EC_I2C_SDA2
EC_I2C_IRQ2
R16
0
L10
A9
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
B2
B9
LDO_3V3
A1
A6
A7
A8
B7
B8
D5
D8
E4
E5
E6
E7
E8
F5
F6
F7
F8
G5
G6
G7
G8
H4
H5
H8
H10
J1
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
C2
C10
D7
D10
E2
GND
R17
3.3k
R18
GND
3.3k
R19
3.3k
PD_CONTROLLER_I2C_SCL1
PD_CONTROLLER_I2C_SDA1
PD_CONTROLLER_I2C_IRQ1
E10
E11
F2
F4
F11
G4
G10
K9
K10
L9
L11
J2
K4
K8
L1
L4
L8
TPS65982BBZBHR
GND
Figure 21. Example Schematic
9.2.1 VBUS Load Switch
The load switch is capable of providing up to 3A for multiple USB Type-A receptacles. The 22uF capacitance on
PP_5V0 is for the local PP_5V0 pins. There should be additional capacitance on the SYS_5V0 that should be
able to support load transients for the number of ports used in the system. The VBUS side capacitance should
be less than PP_5V0 to optimize the over current protection.
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Typical Application (continued)
9.2.2 HRESET
HRESET is the hardware reset on the TPS65982BB and it is a 1.8V (Max) pin. Most PD Controllers and ECs will
drive to 3.3V and will require a resistor divider to drive the HRESET pin.
9.2.3 Dual Port Billboard Support
The TPS65982BB will route the USB2 paths from two USB Type-C ports and provide VBUS with over current
protection to a USB Type-A receptacle or a USB Hub. The TPS65982BB implements a “first come – first serve”
with the two USB2 paths, where the USB2 connection to the USB Type-A or USB Hub is connected to the USB
Type-C port that was connected first. The device will maintain that connection until all connections are removed.
When the PD controller fails to enter an alternate mode, the PD controller will communicate to the TPS65982BB
through I2C to enable the billboard function. Upon receiving the I2C command, the TPS65982BB will connect its
USB endpoint to the connected Type-C port and will be able to send the proper billboard message. The block
diagram below shows the system application for billboard support for two Type-C ports.
Figure 22. Application Block Diagram
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10 Power Supply Recommendations
10.1 3.3-V Power
10.1.1 1VIN_3V3 Input Switch
The VIN_3V3 input is the main supply to the TPS65982BB device. The VIN_3V3 switch (S1 in Figure 13) is a
unidirectional switch from VIN_3V3 to LDO_3V3, not allowing current to flow backwards from LDO_3V3 to
VIN_3V3. This switch is on when 3.3 V is available. See Table 4 for the recommended external capacitance on
the VIN_3V3 pin.
10.1.2 VOUT_3V3 Output Switch
The VOUT_3V3 output switch (S2 in Figure 13) enables a low-current auxiliary supply to an external element.
This switch is controlled by and is off by default. See Table 4 for the recommended external capacitance on the
VOUT_3V3 pin.
10.2 1.8-V Core Power
The internal circuitry is powered from 1.8 V. Two LDOs step the voltage down from LDO_3V3 to 1.8 V. One LDO
powers the internal digital circuits. The other LDO powers the internal low-voltage analog circuits.
10.2.1 1.8-V Digital LDO
The 1.8-V digital LDO provides power to all internal low-voltage digital circuits which includes the digital core,
memory, and other digital circuits. See Table 4 for the recommended external capacitance on the LDO_1V8D
pin.
10.2.2 1.8-V Analog LDO
The 1.8-V analog LDO provides power to all internal low-voltage analog circuits. See Table 4 for the
recommended external capacitance on the LDO_1V8A pin.
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10.3 VDDIO
The VDDIO pin provides a secondary input allowing some I/Os to be powered by a source other than LDO_3V3.
The default state is power from LDO_3V3. The memory stored in the flash configures the I/Os to use LDO_3V3
or VDDIO as a source. The application code automatically scales the input and output voltage thresholds of the
I/O buffer accordingly. See the section for more information on the I/O buffer circuitry. See Table 4 for the
recommended external capacitance on the VDDIO pin.
10.3.1 Recommended Supply Load Capacitance
Table 4 lists the recommended board capacitances for the various supplies. The typical capacitance is the
nominally rated capacitance that must be placed on the board as close to the pin as possible. The maximum
capacitance must not be exceeded on pins for which it is specified. The minimum capacitance is minimum
capacitance allowing for tolerances and voltage derating ensuring proper operation.
Table 4. Recommended Supply Load Capacitance
CAPACITANCE
VOLTAGE
RATING
MIN
(ABS
MIN)
TYP
(TYP
PLACED)
PARAMETER
DESCRIPTION
MAX
(ABS MAX)
CVIN_3V3
Capacitance on VIN_3V3
Capacitance on LDO_3V3
6.3 V
6.3 V
6.3 V
4 V
5 µF
5 µF
10 μF
10 µF
1 μF
CLDO_3V3
CVOUT_3V3
CLDO_1V8D
CLDO_1V8A
CLDO_BMC
25 µF
2.5 μF
12 µF
12 µF
4 µF
Capacitance on VOUT_3V3
Capacitance on LDO_1V8D
Capacitance on LDO_1V8A
Capacitance on LDO_BMC
0.1 μF
500 nF
500 nF
1 µF
2.2 µF
2.2 µF
2.2 µF
4 V
4 V
Capacitance on VDDIO. When shorted to LDO_3V3, the
CLDO_3V3 capacitance may be shared.
CVDDIO
6.3 V
0.1 µF
1 µF
CVBUS
CPP_5V0
CSS
Capacitance on VBUS
25 V
10 V
6.3 V
0.5 µF
2.5 µF
1 µF
12 µF
Capacitance on PP_5V0
Capacitance on soft start pin
4.7 µF
220 nF
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11 Layout
11.1 Layout Guidelines
Proper placement and routing will maintain signal integrity for the high speed signals and power integrity for the
VBUS power switch. The following guidelines show the recommended methodology to properly route all required
signals. Board manufacturing capabilities must be taken into account with any layout to guarantee
manufacturability.
11.2 Layout Example
The layout example is based on the schematic below. Other system components are not shown as they have
their own layout recommendations.
U1
VBUS
G11
J10
J11
H11
K11
PP_5V0_EN
VBUS
VBUS
VBUS
VBUS
PP_5V0_EN
C2
1uF
C1 22uF
SYS_5V0
D11
C11
B11
A11
PP_5V0
PP_5V0
PP_5V0
PP_5V0
GND
A10
B10
SENSE
SENSE
GND
L2
L5
K5
BB_PLUG_PA
USB_RP_P
USB_RP_N
BB_PLUG_PA
USB_RP_P
USB_RP_N
K6
L6
PA_USB_P
PA_USB_N
PA_USB_P
PA_USB_N
K3
L3
BB_BOOT_OK
BB_SRST
HRESET
BB_BOOT_OK
BB_SRST
HRESET
D6
K7
L7
PB_USB_P
PB_USB_N
PB_USB_P
PB_USB_N
H7
G2
H6
B1
F10
H1
H2
G1
K1
C3
0.22 µF
SS
R_OSC
K2
R1
15.0k
BB_PLUG_PB
BB_PLUG_PB
LDO_3V3
DNP
A3
B4
A4
B3
CONFIG
CONFIG
R2
SPI_CLK
CONFIG
SPI_CLK
SPI_MOSI
SPI_MISO
SPI_SSZ
SYS_3V3
SPI_MOSI
SPI_MISO
SPI_SSZ
R3
0
VDDIO
VIN_3V3
VIN_3V3
VOUT_3V3
LDO_3V3
LDO_1V8A
LDO_1V8D
LDO_BMC
B5
A5
B6
I2C2_SCL
I2C2_SDA
I2C2_IRQZ
I2C2_SCL
I2C2_SDA
I2C2_IRQ
C4
4.7uF
GND
D2
D1
C1
LDO_3V3
I2C1_SCL
I2C1_SDA
I2C1_IRQZ
I2C1_SCL
I2C1_SDA
I2C1_IRQ
C5
C6
C7
C8
10uF
4.7uF
4.7uF
4.7uF
F1
I2C_ADDR
A2
E1
R4
0
L10
A9
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
B2
B9
A1
A6
A7
A8
B7
B8
D5
D8
E4
E5
E6
E7
E8
F5
F6
F7
F8
G5
G6
G7
G8
H4
H5
H8
H10
J1
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
C2
GND
C10
D7
D10
E2
GND
E10
E11
F2
F4
F11
G4
G10
K9
K10
L9
L11
J2
K4
K8
L1
L4
L8
TPS65982BBZBHR
GND
Figure 23. Layout Example Schematic
11.2.1 Component Placement
The recommended placement is to have the TPS65982BB on the Top Layer and have all of the passive
components on the opposite layer of the PCB. This will significantly reduce solution size and allows for more
clearance for the high speed and interface signals. The figures below show the top and bottom placement.
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Layout Example (continued)
Figure 24. Top Placement
Figure 25. Bottom Placement
11.2.2 Recommended Via Size and Trace Widths
For all LDO voltages, GPIO, Interface (I2C/SPI) and VIN_3V3 a single via connection to the pads on the
TPS65982BB is sufficient. For PP_5V0 and VBUS it is recommended to use 4 vias to reduce inductance through
the VBUS switch and to have low resistive connection to the bulk cap on the opposite layer. The recommended
via is a 16mil diameter / 8mil hole that is filled (epoxy fill or Cu fill) and tented on both sides of the PCB. The
tenting will help reduce solder from wicking and lifting the BGA package. The figure below shows the
recommended via size.
Figure 26. Recommended Via Size
The table below shows the minimum trace widths. It is recommended to take into account any losses that may
be present such as resistance from system supplies to input supply pins (VIN_3V3).
Table 5. Minimum Trace Widths
Signal
VIN_3V3 (H1, B1)
Minimum Width (mil)
6
6
4
8
LDO_3V3, LDO_1V8A, LDO_1V8D, LDO_BMC
GPIO, VIN_3V3 (F10)
Component GND
34
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Product Folder Links: TPS65982BB
TPS65982BB
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SLVSER3A –NOVEMBER 2018–REVISED APRIL 2020
11.2.3 USB2 Routing
It is important to reduce the number of vias use when routing USB2 signals from the two Type-C receptacles and
to the USB Type-A receptacle or USB hub. Routing on the top and bottom layers only will reduce the amount of
antenna created when using a through hole via to connect an outer layer to an inner layer. When fanning out the
BGA it is recommended to use 4mil traces to get enough clearance to route the width and gap requirements for
impedance matching. Follow the USB2 specification and USB Hub requirements for complete routing rules.
11.2.4 Oval Pad for BGA Fanout
The footprint below uses an oval footprint for the outer pads of the BGA. This allows for routing the inner pads
through the outer pads. The figure below shows the pad size for the out oval pads.
Figure 27. Example Footprint
Figure 28. Oval Pad Sizing
11.2.5 Top and Bottom Layer Complete Routing
The figures below incorporate the guidelines to route all of the required TPS65982BB signals on the top and
bottom layer only. For GND and the VBUS switch (PP_5V0 & VBUS) they are connected all with planes/pours.
Follow the amount of vias used and placement to ensure proper grounding and heat dissipation. All vias must be
connected to a GND plane.
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Figure 29. Top Layer Routing
Figure 30. Bottom Layer Routing
36
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TPS65982BB
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SLVSER3A –NOVEMBER 2018–REVISED APRIL 2020
12 Device and Documentation Support
12.1 Documentation Support
12.1.1 Related Documentation
For related documentation see the following:
•
NSR20F30NXT5G data sheet, Schottky Barrier Diode,
http://www.onsemi.com/PowerSolutions/product.do?id=NSR20F30NX
•
•
•
•
•
USB Power Delivery Specification Revision 3.0, V2.0 (August 2019)
USB Type-C Specification Release 2.0 (August 2019)
Billboard Device Class Spec Revision 1.21 (September 2016)
USB Battery Charging Specification Revision 1.2 (December 7th, 2010)
W25X05CL data sheet, 2.5 / 3 / 3.3 V 512K-Bit Serial Flash Memory With 4KB Sectors and Dual I/O SPI,
www.winbond.com/hq/product/code-storage-flash-memory/serial-nor-flash/?__locale=en&partNo=W25X05CL
12.2 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper
right corner, click on Alert me to register and receive a weekly digest of any product information that has
changed. For change details, review the revision history included in any revised document.
12.3 Support Resources
TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help — straight
from the experts. Search existing answers or ask your own question to get the quick design help you need.
Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do
not necessarily reflect TI's views; see TI's Terms of Use.
12.4 Trademarks
E2E is a trademark of Texas Instruments.
12.5 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
12.6 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
13 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
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Product Folder Links: TPS65982BB
PACKAGE OPTION ADDENDUM
www.ti.com
7-Oct-2021
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
TPS65982BBZBHR
ACTIVE
NFBGA
ZBH
96
2500 RoHS & Green
Call TI
Level-3-260C-168 HR
-10 to 85
TPS65982BB
BH
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
10-Aug-2022
TAPE AND REEL INFORMATION
REEL DIMENSIONS
TAPE DIMENSIONS
K0
P1
W
B0
Reel
Diameter
Cavity
A0
A0 Dimension designed to accommodate the component width
B0 Dimension designed to accommodate the component length
K0 Dimension designed to accommodate the component thickness
Overall width of the carrier tape
W
P1 Pitch between successive cavity centers
Reel Width (W1)
QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE
Sprocket Holes
Q1 Q2
Q3 Q4
Q1 Q2
Q3 Q4
User Direction of Feed
Pocket Quadrants
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
TPS65982BBZBHR
NFBGA
ZBH
96
2500
330.0
16.4
6.3
6.3
2.1
8.0
16.0
Q1
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
10-Aug-2022
TAPE AND REEL BOX DIMENSIONS
Width (mm)
H
W
L
*All dimensions are nominal
Device
Package Type Package Drawing Pins
NFBGA ZBH 96
SPQ
Length (mm) Width (mm) Height (mm)
336.6 336.6 31.8
TPS65982BBZBHR
2500
Pack Materials-Page 2
PACKAGE OUTLINE
ZBH0096A
NFBGA - 1 mm max height
SCALE 2.000
PLASTIC BALL GRID ARRAY
6.1
5.9
B
A
BALL A1 CORNER
INDEX AREA
6.1
5.9
(0.65)
C
1 MAX
SEATING PLANE
0.08 C
BALL TYP
5
0.25
TYP
0.19
TYP
SYMM
(0.5) TYP
L
K
J
(0.5) TYP
H
G
F
SYMM
96X
5
TYP
E
D
C
0.35
0.25
0.15
0.05
C A
C
B
B
A
0.5 TYP
1
2
3
4
5
6
7
8
9 10 11
0.5 TYP
4221754/B 09/2018
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
www.ti.com
EXAMPLE BOARD LAYOUT
ZBH0096A
NFBGA - 1 mm max height
PLASTIC BALL GRID ARRAY
96X ( 0.25)
(0.5) TYP
1
2
3
4
5
6
7
8
9
10
11
A
B
(0.5) TYP
C
D
E
F
G
H
J
SYMM
K
L
SYMM
LAND PATTERN EXAMPLE
SCALE:15X
0.05 MAX
0.05 MIN
METAL UNDER
SOLDER MASK
(
0.25)
METAL
(
0.25)
SOLDER MASK
OPENING
SOLDER MASK
OPENING
NON-SOLDER MASK
DEFINED
SOLDER MASK
DEFINED
(PREFERRED)
SOLDER MASK DETAILS
NOT TO SCALE
4221754/B 09/2018
NOTES: (continued)
4. Final dimensions may vary due to manufacturing tolerance considerations and also routing constraints.
For information, see Texas Instruments literature number SPRAA99 (www.ti.com/lit/spraa99).
www.ti.com
EXAMPLE STENCIL DESIGN
ZBH0096A
NFBGA - 1 mm max height
PLASTIC BALL GRID ARRAY
96X ( 0.25)
(0.5) TYP
(R0.05) TYP
7
1
2
3
5
8
9
4
6
10
11
A
B
(0.5) TYP
C
D
E
F
G
H
J
METAL
TYP
SYMM
K
L
SYMM
SOLDER PASTE EXAMPLE
BASED ON 0.1 mm THICK STENCIL
SCALE:20X
4221754/B 09/2018
NOTES: (continued)
5. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release.
www.ti.com
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