TPS65988DK [TI]
适用于 USB4 器件且具有集成电源开关的双端口 USB Type-C® 和 USB PD 控制器;
| 型号： | TPS65988DK |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 适用于 USB4 器件且具有集成电源开关的双端口 USB Type-C® 和 USB PD 控制器 开关 控制器 电源开关 光电二极管 |
| 文件： | 总68页 (文件大小：4508K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
TPS65988DK
ZHCSLZ8A –SEPTEMBER 2020 –REVISED AUGUST 2021
TPS65988DK 适用于USB4 和Thunderbolt 4 器件、双端口、具有集成电源开关
的USB Type-C® 和USB PD 控制器
1 特性
2 应用
• 该器件由USB-IF 进行了PD3.0 认证
• 扩展坞系统
• 监控器
• USB4 集线器
– 认证新的USB PD 设计时需使用PD3.0 器件
• TID#：5431
– 有关PD2.0 与PD3.0 的文章
• TPS65988DK 是USB4 和Thunderbolt 4 (TBT4)
器件PD3.0 控制器
3 说明
TPS65988DK 是一款高度集成的独立式双端口 USB
Type-C 和电力传输 (PD) 控制器，并针对 USB4 和
TBT4 器件进行了优化。TPS65988DK 集成了全面管
理的电源路径与强大的保护功能，可提供完整的 USB-
C PD 解决方案。进行线缆检测时，TPS65988DK 会
使用 USB PD 协议在 CC 线路上进行通信。在线缆检
测和 USB PD 协商完成后，TPS65988DK 会启用合适
的电源路径并为外部多路复用器配置交替模式设置。
Intel 的 USB4 和 TBT4 器件终端设备参考设计使用了
此器件，确保PD 控制器在这类设计中提供适当的系统
级交互，从而显著降低系统设计的复杂性，并缩短上市
时间。
– 此PD 控制器仅适用于USB4 器件设计
– 请参考Intel 参考设计，文档编号631605
– 如果设计的不是USB4 器件，请访问
www.ti.com/usb-c 参阅选型指南和入门信息，以
及E2E 指南
• 全面管理的集成电源路径：
– 集成两个5V 至20V、5A、25mΩ双向开关
– UL2367 认证编号：20190107-E169910
– IEC62368-1 认证编号：US-34617-UL
• 集成强大的电源路径保护
– 20V/5A 电源路径配置为接收端口时，集成了反
向电流保护、欠压保护、过压保护和压摆率控制
– 20V/5A 电源路径配置为源端口时，集成了欠压
保护、过压保护和提供浪涌电流保护的电流限制
• USB Type-C® 电力传输(PD) 控制器
器件信息
封装(1)
封装尺寸（标称值）
器件型号
TPS65988DK
QFN (56)
7.00mm x 7.00mm
(1) 如需了解所有可用封装，请参阅数据表末尾的可订购产品附
录。
– 13 个可配置GPIO
– 获得USB PD 3.0 认证
– 获得USB Type-C 规范认证
– 线缆连接和方向检测
– 集成式VCONN 开关
– 物理层和策略引擎
– 3.3V LDO 输出，在电池电量耗尽时提供支持
– 通过3.3V 或VBUS 源供电
– 1 个I2C 主要或次级端口
• 只有1 个I2C 主要端口
• 只有1 个I2C 次级端口
简化版原理图
本文档旨在为方便起见，提供有关TI 产品中文版本的信息，以确认产品的概要。有关适用的官方英文版本的最新信息，请访问
www.ti.com，其内容始终优先。TI 不保证翻译的准确性和有效性。在实际设计之前，请务必参考最新版本的英文版本。
English Data Sheet: SLVSFN9
TPS65988DK
ZHCSLZ8A –SEPTEMBER 2020 –REVISED AUGUST 2021
www.ti.com.cn
Table of Contents
9.1 Application Information............................................. 43
9.2 Typical Applications.................................................. 43
10 Power Supply Recommendations..............................48
10.1 3.3-V Power............................................................ 48
10.2 1.8-V Power............................................................ 48
10.3 Recommended Supply Load Capacitance..............48
11 Layout...........................................................................49
11.1 Layout Guidelines................................................... 49
11.2 Layout Example...................................................... 49
11.3 Stack-up and Design Rules.....................................50
11.4 Main Component Placement...................................51
11.5 Super Speed Type-C Connectors........................... 51
11.6 Capacitor Placement...............................................52
11.7 CC1/2 Capacitors & ADCIN1/2 Resistors............... 53
11.8 CC and SBU Protection Placement........................ 54
11.9 CC Routing..............................................................55
11.10 DRAIN1 and DRAIN2 Pad Pours..........................56
11.11 VBUS Routing....................................................... 58
11.12 Completed Layout.................................................59
11.13 Power Dissipation................................................. 60
12 Device and Documentation Support..........................61
12.1 Device Support....................................................... 61
12.2 Documentation Support.......................................... 61
12.3 支持资源..................................................................61
12.4 Trademarks.............................................................61
12.5 Electrostatic Discharge Caution..............................61
12.6 术语表..................................................................... 61
13 Mechanical, Packaging, and Orderable
1 特性................................................................................... 1
2 应用................................................................................... 1
3 说明................................................................................... 1
4 Revision History.............................................................. 2
5 Pin Configuration and Functions...................................3
6 Specifications.................................................................. 7
6.1 Absolute Maximum Ratings........................................ 7
6.2 ESD Ratings............................................................... 7
6.3 Recommended Operating Conditions.........................7
6.4 Thermal Information....................................................8
6.5 Power Supply Requirements and Characteristics.......8
6.6 Power Consumption Characteristics...........................9
6.7 Power Switch Characteristics..................................... 9
6.8 Cable Detection Characteristics................................11
6.9 USB-PD Baseband Signal Requirements and
Characteristics.............................................................12
6.10 Thermal Shutdown Characteristics.........................13
6.11 Oscillator Characteristics........................................ 13
6.12 I/O Characteristics.................................................. 13
6.13 I2C Requirements and Characteristics....................14
6.14 SPI Controller Timing Requirements.......................15
6.15 HPD Timing Requirements..................................... 16
6.16 Typical Characteristics............................................16
7 Parameter Measurement Information..........................17
8 Detailed Description......................................................18
8.1 Overview...................................................................18
8.2 Functional Block Diagram.........................................19
8.3 Feature Description...................................................19
8.4 Device Functional Modes..........................................40
9 Application and Implementation..................................43
Information.................................................................... 61
4 Revision History
Changes from Revision * (September 2020) to Revision A (August 2021)
Page
• 更改了特性列表..................................................................................................................................................1
• 更新了说明部分..................................................................................................................................................1
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5 Pin Configuration and Functions
PP_HV2 -1
PP_HV2 -2
VBUS2 -3
42- GPIO14 (PWM)
41- GPIO13
40- GPIO12
57
DRAIN2
39- SPI_CS (GPIO11)
VBUS2 -4
38- SPI_CLK (GPIO10)
37- SPI_PICO (GPIO9)
36- SPI_POCI (GPIO8)
VIN_3V3 -5
ADCIN1 -6
DRAIN2 -7
DRAIN1 -8
LDO_3V3 -9
59
GND
35- LDO_1V8
34- I2C2_IRQ
ADCIN2 -10
58
33- I2C2_SDA
32- I2C2_SCL
31- HPD2 (GPIO4)
30- HPD1 (GPIO3)
PP_HV1 -11
DRAIN1
PP_HV1 -12
VBUS1 -13
VBUS1 -14
29- I2C1_IRQ
图5-1. RSH Package 56-Pin QFN Top View
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表5-1. Pin Functions
PIN
TYPE(2)
RESET STATE(1)
DESCRIPTION
NAME
NO.
Boot configuration Input. Connect to resistor
divider between LDO_3V3 and GND.
ADCIN1
6
I
Input
Input
I2C address configuration Input. Connect to
resistor divider between LDO_3V3 and GND.
ADCIN2
C1_CC1
C1_CC2
10
24
26
I
Output to Type-C CC or VCONN pin for port 1.
Filter noise with capacitor to GND.
I/O
I/O
High-Z
High-Z
Output to Type-C CC or VCONN pin for port 1.
Filter noise with capacitor to GND.
C1_USB_N (GPIO19)
C1_USB_P (GPIO18)
53
50
I/O
I/O
Input (High-Z)
Input (High-Z)
Port 1 USB D–connection for BC1.2 support.
Port 1 USB D+ connection for BC1.2 support.
Output to Type-C CC or VCONN pin for port 2.
Filter noise with capacitor to GND.
C2_CC1
C2_CC2
45
47
I/O
I/O
High-Z
High-Z
Output to Type-C CC or VCONN pin for port 2.
Filter noise with capacitor to GND.
C2_USB_N (GPIO21)
C2_USB_P (GPIO20)
55
54
I/O
I/O
Input (High-Z)
Input (High-Z)
Port 2 USB D–connection for BC1.2 support.
Port 2 USB D+ connection for BC1.2 support.
Drain of internal power path 1. Connect thermal
pad 58 to as big of pad as possible on PCB for
best thermal performance. Short the other pins to
this thermal pad.
DRAIN1
8, 15, 19, 58
—
—
Drain of internal power path 2. Connect thermal
pad 57 to as big of pad as possible on PCB for
best thermal performance. Short the other pins to
this thermal pad.
DRAIN2
GND
7, 52, 56, 57
20, 51
—
—
—
—
Unused pin. Tie to GND.
General Purpose Digital I/O 0. Float pin when
unused. GPIO0 is asserted low during the
TPS65988DK boot process. Once device
configuration and patches are loaded GPIO0 is
released.
GPIO0
16
I/O
Input (High-Z)
General Purpose Digital I/O 1. Ground pin with a
1-MΩresistor when unused in the application.
GPIO1
GPIO2
17
18
I/O
I/O
Input (High-Z)
Input (High-Z)
General Purpose Digital I/O 2. Float pin when
unused.
General Purpose Digital I/O 3. Configured as Hot
Plug Detect (HPD) TX and RX for port 1 when
DisplayPort alternate mode is enabled. Float pin
when unused.
GPIO3 (HPD1)
GPIO4 (HPD2)
30
31
I/O
I/O
Input (High-Z)
Input (High-Z)
General Purpose Digital I/O 4. Configured as Hot
Plug Detect (HPD) TX and RX for port 2 when
DisplayPort alternate mode is enabled. Float pin
when unused.
I2C port 3 serial clock. Open-drain output. Tie pin
to I/O voltage through a 10-kΩresistance when
used. Float pin when unused.
I2C3_SCL (GPIO5)
I2C3_SDA (GPIO6)
21
22
I/O
I/O
Input (High-Z)
Input (High-Z)
I2C port 3 serial data. Open-drain output. Tie pin to
I/O voltage through a 10-kΩresistance when
used. Float pin when unused.
I2C port 3 interrupt detection (port 3 operates as
an I2C Master Only). Active low detection.
Connect to the I2C slave's interrupt line to detect
when the slave issues an interrupt. Float pin when
unused.
I2C3_IRQ (GPIO7)
23
I/O
Input (High-Z)
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表5-1. Pin Functions (continued)
PIN
TYPE(2)
RESET STATE(1)
DESCRIPTION
NAME
NO.
General Purpose Digital I/O 12. Float pin when
unused.
GPIO12
40
I/O
I/O
I/O
I/O
Input (High-Z)
Input (High-Z)
Input (High-Z)
Input (High-Z)
General Purpose Digital I/O 13. Float pin when
unused.
GPIO13
41
42
43
General Purpose Digital I/O 14. May also function
as a PWM output. Float pin when unused.
GPIO14 (PWM)
GPIO15 (PWM)
General Purpose Digital I/O 15. May also function
as a PWM output. Float pin when unused.
General Purpose Digital I/O 16. May also function
as single wire enable signal for external power
path 1. Pull-down with external resistor when used
for external path control. Float pin when unused.
GPIO16 (PP_EXT1)
GPIO17 (PP_EXT2)
48
49
I/O
I/O
Input (High-Z)
Input (High-Z)
General Purpose Digital I/O 17. May also function
as single wire enable signal for external power
path 2. Pull-down with external resistor when used
for external path control. Float pin when unused.
Active high hardware reset input. Will reinitialize all
device settings. Ground pin when HRESET
functionality will not be used.
HRESET
44
29
27
28
34
32
I/O
O
Input
I2C port 1 interrupt. Active low. Implement
externally as an open drain with a pull-up
resistance. Float pin when unused.
I2C1_IRQ
I2C1_SCL
I2C1_SDA
I2C2_IRQ
I2C2_SCL
High-Z
High-Z
High-Z
High-Z
High-Z
I2C port 1 serial clock. Open-drain output. Tie pin
to I/O voltage through a 10-kΩresistance when
used or unused.
I/O
I/O
O
I2C port 1 serial data. Open-drain output. Tie pin to
I/O voltage through a 10-kΩresistance when used
or unused.
I2C port 2 interrupt. Active low. Implement
externally as an open drain with a pull-up
resistance. Float pin when unused.
I2C port 2 serial clock. Open-drain output. Tie pin
to I/O voltage through a 10-kΩresistance when
used or unused.
I/O
I2C port 2 serial data. Open-drain output. Tie pin to
I/O voltage through a 10-kΩresistance when used
or unused.
I2C2_SDA
LDO_1V8
33
35
I/O
High-Z
Output of the 1.8-V LDO for internal circuitry.
Bypass with capacitor to GND
PWR
—
Output of the VBUS to 3.3-V LDO or connected to
VIN_3V3 by a switch. Main internal supply rail.
Used to power external flash memory. Bypass with
capacitor to GND.
LDO_3V3
9
PWR
—
5-V supply input for port 1 C_CC pins. Bypass with
capacitor to GND.
PP1_CABLE
PP2_CABLE
25
46
PWR
PWR
—
—
5-V supply input for port 2 C_CC pins. Bypass with
capacitor to GND.
System side of first VBUS power switch. Bypass
with capacitor to ground. Tie to ground when
unused.
PP_HV1
11, 12
PWR
—
System side of second VBUS power switch.
Bypass with capacitor to ground. Tie to ground
when unused.
PP_HV2
SPI_CLK
1, 2
38
PWR
I/O
—
Input
SPI serial clock. Ground pin when unused.
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表5-1. Pin Functions (continued)
PIN
TYPE(2)
RESET STATE(1)
DESCRIPTION
NAME
NO.
SPI serial controller input from peripheral. Ground
pin when unused.
SPI_POCI
36
I/O
Input
SPI serial controller output to peripheral. Ground
pin when unused.
SPI_PICO
SPI_CS
VBUS1
37
39
I/O
I/O
Input
Input
—
SPI chip select. Ground pin when unused.
Port side of first VBUS power switch. Bypass with
capacitor to ground.
13, 14
PWR
Port side of second VBUS power switch. Bypass
with capacitor to ground.
VBUS2
3, 4
5
PWR
PWR
—
—
Supply for core circuitry and I/O. Bypass with
capacitor to GND.
VIN_3V3
Ground reference for the device as well as thermal
pad used to conduct heat. from the device. This
connection serves two purposes. The first purpose
is to provide an electrical ground connection for
the device. The second purpose is to provide a low
thermal-impedance path from the device die to the
PCB. This pad must be connected to a ground
plane.
Thermal Pad (PPAD)
59
GND
—
(1) Reset State indicates the state of a given pin immediately following power application, prior to any configuration from firmware.
(2) I = input, O = output, I/O = bidirectional, GND = ground, PWR = power, NC = no connect.
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6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)(1)
MIN
–0.3
–0.3
–0.3
–0.3
–0.3
–0.3
–0.3
–0.5
–0.5
–10
MAX
UNIT
PPx_CABLE
Input voltage(2)
6
V
VIN_3V3
3.6
LDO_1V8
2
Output voltage(2) LDO_3V3
3.6
V
V
I2Cx _IRQ, SPI_PICO, SPI_CLK, SPI_CS, SWD_CLK
PP_HVx, VBUSx(4)
LDO_3V3 + 0.3 (3)
24
I2Cx_SDA, I2Cx_SCL, SPI_POCI, GPIOn, HRESET, ADCINx
LDO_3V3 + 0.3 (3)
I/O voltage (2)
Cx_USB_P, Cx_USB_N
6
6
Cx_CC1, Cx_CC2
Operating junction temperature, TJ
Operating junction temperature PPHV switch, TJ
Storage temperature, Tstg
125
150
150
°C
°C
°C
–10
–55
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under
Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device
reliability.
(2) All voltage values are with respect to underside power pad. The underside power pad should be directly connected to the ground plane
of the board.
(3) Not to exceed 3.6 V.
(4) For VBUSx a TVS with a break down voltage falling between the Recommended max and the Abs max value is recommended such as
TVS2200.
6.2 ESD Ratings
VALUE
UNIT
Human body model (HBM), per ANSI/
ESDA/JEDEC JS-001, all pins(1)
±1500
V(ESD)
Electrostatic discharge
V
Charged device model (CDM), per
JEDEC specification JESD22-C101, all
pins(2)
±500
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
6.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)(1)
MIN
3.135
2.95
4.5
4
NOM
MAX
UNIT
VIN_3V3
3.45
5.5
(1)
Input voltage, VI
PP_CABLE
V
PP_HV
22
VBUS
22
Cx_USB_P, Cx_USB_N
0
LDO_3V3
5.5
(1)
I/O voltage, VIO
V
Cx_CC1, Cx_CC2
0
GPIOn, I2Cx_SDA, I2Cx_SCL, SPI, ADCIN1, ADCIN2
0
LDO_3V3
75
Operating ambient temperature, TA
Operating junction temperature, TJ
–10
–10
°C
125
(1) All voltage values are with respect to underside power pad. Underside power pad must be directly connected to ground plane of the
board.
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6.4 Thermal Information
TPS65988DK
RSH (QFN)
56 PINS
36.4
THERMAL METRIC(1)
UNIT
(2)
RθJA
Junction-to-ambient thermal resistance
Junction-to-case (top) thermal resistance
Junction-to-board thermal resistance
°C/W
°C/W
°C/W
°C/W
°C/W
RθJC(top)
28.3
(2)
RθJB
13.7
(2)
Junction-to-top characterization parameter
Junction-to-board characterization parameter
11.3
ψJT
(2)
13.6
ψJB
Rθ
Junction-to-case (bottom GND pad) thermal resistance
Junction-to-case (bottom DRAIN1/2 pad) thermal resistance
0.7
5.6
°C/W
°C/W
JC(bot_Controller)
RθJC(bot_FET)
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
(2) Thermal metrics are not JDEC standard values and are based on the TPS65988 evaluation board.
6.5 Power Supply Requirements and Characteristics
over operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX UNIT
EXTERNAL
VIN_3V3
Input 3.3-V supply
3.135
2.95
3.3
5
3.45
5.5
V
V
Input to power Vconn output on C_CC
pins
PP_CABLE
PP_HV
VBUS
Source power from PP_HV to VBUS
Sink power from VBUS to PP_HV
4.5
4
5
5
22
22
V
V
Recommended capacitance on the
VIN_3V3 pin
CVIN_3V3
5
10
µF
µF
Recommended capacitance on
PPx_CABLE pins
CPP_CABLE
2.5
4.7
Recommended capacitance on
PP_HVx pin when configured as a
source
CPP_HV_SRC
2.5
4.7
µF
Recommended capacitance on
PP_HVx pin when configured as a
sink
CPP_HV_SNK
1
47
1
120
12
μF
μF
Recommended capacitance on
VBUSx pins
CVBUS
0.5
INTERNAL
VLDO_3V3
Output voltage of LDO from VBUS to VIN_3V3 = 0 V, VBUS1 ≥4 V, 0 ≤
3.15
250
3.3
3.45
850
V
LDO_3V3
I
LOAD ≤50 mA
Drop out voltage of LDO_3V3 from
VBUS
VDO_LDO_3V3
ILOAD = 50 mA
500
mV
Allowed External Load current on
LDO_3V3 pin
ILDO_3V3_EX
VLDO_1V8
25
1.85
200
mA
V
Output voltage of LDO_1V8
1.75
1.8
0 ≤ILOAD ≤20 mA
Forward voltage drop across VIN_3V3
to LDO_3V3 switch
VFWD_DROP
ILOAD = 50 mA
mV
Recommended capacitance on
LDO_3V3 pin
CLDO_3V3
5
10
25
6
μF
μF
Recommended capacitance on
LDO_1V8 pin
CLDO_1V8
2.2
4.7
SUPERVISORY
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6.5 Power Supply Requirements and Characteristics (continued)
over operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
2.2
20
TYP
2.325
80
MAX UNIT
Undervoltage threshold for LDO_3V3.
Locks out 1.8-V LDOs.
UV_LDO3V3
UVH_LDO3V3
UV_PCBL
LDO_3V3 rising
2.45
150
V
mV
V
Undervoltage hysteresis for LDO_3V3 LDO_3V3 falling
Undervoltage threshold for
PP_CABLE rising
PP_CABLE
2.5
2.625
2.75
Undervoltage hysteresis for
PP_CABLE falling
PP_PCABLE
UVH_PCBL
OV_VBUS
20
5
50
80
24
mV
V
Overvoltage threshold for VBUS. This
value is a 6-bit programmable
threshold
VBUS rising
Overvoltage threshold step for VBUS.
This value is the LSB of the
programmable threshold
OVLSB_VBUS
OVH_VBUS
UV_VBUS
VBUS rising
328
mV
%
Overvoltage hysteresis for VBUS
VBUS falling, % of OV_VBUS
VBUS falling
1.4
2.5
1.65
1.9
Undervoltage threshold for VBUS.
This value is a 6-bit programmable
threshold.
18.21
V
Undervoltage threshold step for
VBUS. This value is the LSB of the
programmable threshold.
UVLSB_VBUS
UVH_VBUS
VBUS falling
249
1.3
mV
%
Undervoltage hysteresis for VBUS
VBUS rising, % of UV_VBUS
0.9
1.7
6.6 Power Consumption Characteristics
over operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
VIN_3V3 = 3.3 V, VBUS = 0 V, No
cables connected, Tj = 25°C,
configured as sink, BC1.2 disabled
Sleep (Sink)
45
55
µA
µA
(1)
IVIN_3V3
VIN_3V3 = 3.3 V, VBUS = 0 V, No
cables connected, Tj = 25°C,
configured as source or DRP, BC1.2
disabled
Sleep (Source/DRP)
VIN_3V3 = 3.3 V, Cables connected,
No active PD communication, Tj =
25°C
(1)
(1)
IVIN_3V3
IVIN_3V3
Idle (Attached)
Active
5
8
mA
mA
VIN_3V3 = 3.3 V, Tj = 25°C
(1) Does not include current draw due to GPIO loading
6.7 Power Switch Characteristics
over operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
222
269
MAX
325
UNIT
mΩ
mΩ
4.7 ≤PP_CABLE ≤5.5
2.95 ≤PP_CABLE < 4.7
PP_CABLE to C_CCn power switch
resistance
RPPCC
414
PP_HVx to VBUSx power switch
resistance
RPPHV
IPPHV
Tj = 25°C
25
33
5
mΩ
Continuous current capabillity of
power path from PP_HVx to VBUSx
TA < 60°C (1)
A
Continuous current capabillity of
power path from PP_CABLEx to
Cx_CCn
TJ = 125°C
TJ = 85°C
320
600
mA
mA
IPPCC
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6.7 Power Switch Characteristics (continued)
over operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
Active quiescent current from PP_HV Source Configuration, Comparator
IHVACT
IHVSD
1
mA
pin, EN_HV = 1
RCP function enabled, ILOAD = 100 mA
Shutdown quiescent current from
PP_HV pin, EN_HV = 0
VPPHV = 20 V
100
µA
1.140
1.380
1.620
1.860
2.100
2.34
1.267
1.533
1.800
2.067
2.333
2.600
2.867
3.133
3.400
3.667
3.933
4.200
4.467
4.733
5.00
1.393
1.687
1.980
2.273
2.567
2.860
3.153
3.447
3.74
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
2.580
2.820
3.060
3.300
3.540
3.780
4.020
4.260
4.500
4.740
4.980
5.220
5.460
5.697
4.033
4.327
4.620
4.913
5.207
5.500
5.793
6.087
6.380
6.673
6.963
Over Current Clamp Firmware
Selectable Settings
IOCC
5.267
5.533
5.800
6.067
6.330
PP_HV Quick Response Current
Limit
IOCP
10
0.75
6
A
A
ILIMPPCC
IHV_ACC 1
PP_CABLE current limit
0.6
3.9
0.9
8.1
I = 100 mA, Reverse current blocking
disabled
PP_HV current sense accuracy
A/V
IHV_ACC 1
IHV_ACC 1
IHV_ACC 1
PP_HV current sense accuracy
PP_HV current sense accuracy
PP_HV current sense accuracy
I = 200 mA
I = 500 mA
I ≥1 A
4.8
5.28
5.4
6
6
6
7.2
6.72
6.6
A/V
A/V
A/V
PP_HV path turn on time from
enable to VBUS = 95% of PP_HV
voltage
Configured as a source or as a sink
with soft start disabled. PP_HV = 20 V,
CVBUS = 10 µF, ILOAD = 100 mA
tON_HV
tON_FRS
tON_CC
8
150
2
ms
μs
ms
PP_HV path turn on time from
enable to VBUS = 95% of PP_HV
voltage during an FRS enable
Configured as a source. PP_HV = 5 V,
CVBUS = 10 µF, ILOAD = 100 mA
PP_CABLE path turn on time from
enable to C_CCn = 95% of the
PP_CABLE voltage
PP_CABLE = 5 V, C_CCn = 500 nF,
ILOAD = 100 mA
ILOAD = 100 mA, setting 0
ILOAD = 100 mA, setting 1
ILOAD = 100 mA, setting 2
ILOAD = 100 mA, setting 3
Diode Mode
0.270
0.6
0.409
0.787
1.567
3.388
6
0.45
1
V/ms
V/ms
V/ms
V/ms
mV
Configurable soft start slew rate for
sink configuration
SS
1.2
1.7
3.6
10
6
2.3
Reverse current blocking voltage
threshold for PP_HV switch
VREVPHV
Comparator Mode
3
mV
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6.7 Power Switch Characteristics (continued)
over operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
0.8
UNIT
V
Voltage that is a safe 0 V per USB-
PD specification
VSAFE0V
tSAFE0V
SRPOS
0
Voltage transition time to VSAFE0V
650
0.03
ms
Maximum slew rate for positive
voltage transitions
V/µs
Maximum slew rate for negative
voltage transitions
SRNEG
tSTABLE
V/µs
ms
–0.03
EN to stable time for both positive
and negative voltage transitions
275
Supply output tolerance beyond
VSRCNEW during time tSTABLE
VSRCVALID
VSRCNEW
tVCONNDIS
0.5
5
V
%
–0.5
–5
Supply output tolerance
Time from cable detach to
VVCONNDIS
250
ms
Voltage at which VCONN is
considered discharged
VVCONNDIS
150
mV
(1) Allowable ambient temperature is dependant on device board layout. Junction temperature of PPHV switch may not exceed 150C.
6.8 Cable Detection Characteristics
over operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
Source Current through each C_CC pin when
in a disconnected state and Configured as a
Source advertising Default USB current to a
peripheral device
IH_CC_USB
73.6
80
86.4
µA
Source Current through each C_CC pin when
in a disconnected state when Configured as a
Source advertising 1.5-A to a UFP
IH_CC_1P5
165.6
303.6
180
330
194.4
356.4
µA
µA
Source Current through each C_CC pin when
in a disconnected state and Configured as a
Source advertising 3.0-A to a UFP.
VIN_3V3 ≥3.135 V, VCC
2.6 V
<
IH_CC_3P0
Voltage Threshold for detecting a Source
attach when configured as a Sink and the
Source is advertising Default USB current
source capability
VD_CCH_USB
0.15
0.2
0.25
V
Voltage Threshold for detecting a Source
advertising 1.5-A source capability when
configured as a Sink
VD_CCH_1P5
0.61
1.16
1.5
0.66
1.23
1.55
1.55
2.55
0.2
0.7
1.31
1.65
1.65
2.615
0.25
V
V
V
V
V
V
Voltage Threshold for detecting a Source
advertising 3-A source capability when
configured as a Sink
VD_CCH_3P0
Voltage Threshold for detecting a Sink attach
VH_CCD_USB when configured as a Source and advertising
Default USB current source capability.
IH_CC = IH_CC_USB
IH_CC = IH_CC_1P5
Voltage Threshold for detecting a Sink attach
when configured as a Source and advertising
1.5-A source capability
VH_CCD_1P5
1.5
Voltage Threshold for detecting a Sink attach
when configured as a Source and advertising
3.0-A source capability.
IH_CC = IH_CC_3P0
VIN_3V3 ≥3.135 V
VH_CCD_3P0
2.45
0.15
Voltage Threshold for detecting an active cable
VH_CCA_USB attach when configured as a Source and
advertising Default USB current capability.
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6.8 Cable Detection Characteristics (continued)
over operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
Voltage Threshold for detecting active cables
attach when configured as a Source and
advertising 1.5-A capability.
VH_CCA_1P5
0.35
0.4
0.45
V
Voltage Threshold for detecting active cables
attach when configured as a Source and
advertising 3-A capability.
VH_CCA_3P0
0.75
4.59
0.8
5.1
0.85
5.61
V
Pulldown resistance through each C_CC pin
when in a disconnect state and configured as a V = 1 V, 1.5 V
Sink. LDO_3V3 powered.
RD_CC
kΩ
Pulldown resistance through each C_CC pin
when in a disabled state. LDO_3V3 powered.
RD_CC_OPEN
V = 0 V to LDO_3V3
V = 1.5 V, 2.0 V
500
kΩ
kΩ
Pulldown resistance through each C_CC pin
when LDO_3V3 unpowered
RD_DB
4.08
5.1
6.12
5
RFRSWAP
VTH_FRS
Fast Role Swap signal pull down
Ω
Fast role swap request detection voltage
threshold
490
520
550
mV
6.9 USB-PD Baseband Signal Requirements and Characteristics
over operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
COMMON
PD_BITRATE
UI (2)
PD data bit rate
270
300
330
3.7
Kbps
µs
Unit interval (1/PD_BITRATE)
Capacitance for a cable plug (each
3.03
3.33
CCBLPLUG (1) plug on a cable may have up to this
value)
25
65
pF
ZCABLE
Cable characteristic impedance
32
Ω
Receiver capacitance. Capacitance
CRECEIVER (3) looking into Cx_CCn pin when in
receiver mode.
100
pF
TRANSMITTER
TX output impedance. Source
output impedance at the Nyquist
ZDRIVER
frequency of USB2.0 low speed
(750kHz) while the source is driving
the C_CCn line.
33
75
Ω
Rise time. 10 % to 90 % amplitude
points, minimum is under an
unloaded condition. Maximum set
by TX mask.
tRISE
300
ns
Fall time. 90 % to 10 % amplitude
points, minimum is under an
unloaded condition. Maximum set
by TX mask.
tFALL
300
ns
V
VTX
Transmit high voltage
1.05
1.125
1.2
RECEIVER
VRXTR
VRXTR
VRXTF
Rx receive rising input threshold
Rx receive rising input threshold
Rx receive falling input threshold
Rx receive falling input threshold
Port configured as Source
Port configured as Sink
Port configured as Sink
Port configured as Source
840
504
240
576
875
525
250
600
910
546
260
624
mV
mV
mV
mV
VRXTF
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6.9 USB-PD Baseband Signal Requirements and Characteristics (continued)
over operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
Number of transitions for signal
detection (number to count to
detect non-idle bus).
NCOUNT
TTRANWIN
ZBMCRX
3
Time window for detecting non-idle
bus.
12
5
20
µs
Does not include pull-up or pulldown
resistance from cable detect.
Transmitter is Hi-Z.
Receiver input impedance
MΩ
Rx bandwidth limiting filter. Time
TRXFILTER (4) constant of a single pole filter to
limit broadband noise ingression
100
ns
(1) The capacitance of the bulk cable is not included in the CCBLPLUG definition. It is modeled as a transmission line.
(2) UI denotes the time to transmit an unencoded data bit not the shortest high or low times on the wire after encoding with BMC. A single
data bit cell has duration of 1 UI, but a data bit cell with value 1 will contain a centrally place 01 or 10 transition in addition to the
transition at the start of the cell.
(3) CRECEIVER includes only the internal capacitance on a C_CCn pin when the pin is configured to be receiving BMC data. External
capacitance is needed to meet the required minimum capacitance per the USB-PD Specifications. TI recommends adding capacitance
to bring the total pin capacitance to 300 pF for improved TX behavior.
(4) Broadband noise ingression is because of coupling in the cable interconnect.
6.10 Thermal Shutdown Characteristics
over operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
Thermal Shutdown Temperature of the
main thermal shutdown
TSD_MAIN
TSDH_MAIN
TSD_PWR
TSDH_PWR
Temperature rising
145
160
175
°C
Thermal Shutdown hysteresis of the
main thermal shutdown
Temperature falling
Temperature rising
Temperature falling
20
160
20
°C
°C
°C
Thermal Shutdown Temperature of the
power path block
145
175
Thermal Shutdown hysteresis of the
power path block
6.11 Oscillator Characteristics
over operating free-air temperature range (unless otherwise noted)
PARAMETER
24-MHz oscillator
100-kHz oscillator
TEST CONDITIONS
MIN
22.8
95
TYP
24
MAX
25.2
105
UNIT
MHz
kHz
ƒOSC_24M
ƒOSC_100K
100
6.12 I/O Characteristics
over operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
SPI
SPI_VIH
SPI_VIL
SPI_HYS
SPI_ILKG
SPI_VOH
SPI_VOL
SWDIO
High-level input voltage
Low input voltage
LDO_1V8 = 1.8 V
1.3
V
V
LDO_1V8 = 1.8 V
0.63
1
Input hysteresis voltage
Leakage current
LDO_1V8 = 1.8 V
0.09
-1
V
Output is Hi-Z, VIN = 0 to LDO_3V3
IO = –2 mA, LDO_3V3 = 3.3 V
IO = 2 mA
µA
V
SPI output high voltage
SPI output low voltage
2.88
0.4
V
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UNIT
6.12 I/O Characteristics (continued)
over operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
SWDCLK
GPIO
GPIO_VIH
GPIO_VIL
GPIO_HYS
GPIO_ILKG
GPIO_RPU
GPIO_RPD
GPIO_DG
GPIO_VOH
GPIO_VOL
I2C_IRQx
OD_VOL
High-level input voltage
Low input voltage
LDO_1V8 = 1.8 V
LDO_1V8 = 1.8 V
LDO_1V8 = 1.8 V
INPUT = 0 V to VDD
Pullup enabled
1.3
V
V
0.63
Input hysteresis voltage
I/O leakage current
0.09
–1
50
V
1
150
150
µA
Pullup resistance
100
100
20
kΩ
kΩ
ns
V
Pulldown resistance
Digital input path deglitch
GPIO output high voltage
GPIO output low voltage
Pulldown enabled
50
2.88
IO = –2 mA, LDO_3V3 = 3.3 V
IO = 2 mA, LDO_3V3 = 3.3 V
0.4
V
Low-level output voltage
Leakage current
IOL = 2 mA
0.4
1
V
OD_LKG
Output is Hi-Z, VIN = 0 to LDO_3V3
µA
–1
6.13 I2C Requirements and Characteristics
over operating free-air temperature range (unless otherwise noted).
PARAMETER
SDA AND SCL COMMON
CHARACTERISTICS
ILEAK Input leakage current
VOL
TEST CONDITIONS
MIN
TYP
MAX
UNIT
Voltage on Pin = LDO_3V3
IOL = 3 mA, LDO_3V3 = 3.3 V
VOL = 0.4 V
3
µA
V
–3
SDA output low voltage
0.4
3
6
mA
mA
V
IOL
SDA max output low current
VOL = 0.6 V
LDO_3V3 = 3.3 V
LDO_1V8 = 1.8 V
LDO_3V3 = 3.3 V
LDO_1V8 = 1.8 V
LDO_3V3 = 3.3 V
LDO_1V8 = 1.8 V
0.99
0.54
VIL
Input low signal
Input high signal
Input hysteresis
V
2.31
1.3
V
VIH
V
0.17
0.09
V
VHYS
V
tSP
CI
I2C pulse width suppressed
Pin capacitance
50
10
ns
pF
SDA AND SCL STANDARD
MODE CHARACTERISTICS
I2C clock frequency
0
4
100
kHz
µs
µs
ns
ƒSCL
tHIGH
I2C clock high time
tLOW
I2C clock low time
4.7
250
0
tSU;DAT
tHD;DAT
tVD;DAT
I2C serial data setup time
I2C serial data hold time
I2C valid data time
ns
SCL low to SDA output valid
3.45
3.45
250
µs
ACK signal from SCL low to SDA (out)
low
tVD;ACK
tOCF
I2C valid data time of ACK condition
I2C output fall time
µs
ns
µs
10-pF to 400-pF bus
I2C bus free time between stop and
start
tBUF
4.7
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6.13 I2C Requirements and Characteristics (continued)
over operating free-air temperature range (unless otherwise noted).
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
I2C start or repeated Start condition
setup time
tSU;STA
4.7
µs
I2C Start or repeated Start condition
hold time
tHD;STA
tSU;STO
4
4
µs
µs
I2C Stop condition setup time
SDA AND SCL FAST MODE
CHARACTERISTICS
I2C clock frequency
Configured as Slave
Configured as Master
0
0
400
400
kHz
kHz
µs
ƒSCL
I2C clock frequency
I2C clock high time
320
ƒSCL_MASTER
tHIGH
0.6
1.3
100
0
tLOW
I2C clock low time
µs
tSU;DAT
tHD;DAT
tVD;DAT
I2C serial data setup time
I2C serial data hold time
I2C Valid data time
ns
ns
SCL low to SDA output valid
0.9
0.9
µs
ACK signal from SCL low to SDA (out)
low
tVD;ACK
I2C Valid data time of ACK condition
I2C output fall time
µs
10-pF to 40-pF bus, VDD = 3.3 V
10-pF to 400-pF bus, VDD = 1.8 V
12
250
250
ns
ns
tOCF
6.5
I2C bus free time between stop and
start
tBUF
1.3
0.6
µs
µs
I2C start or repeated Start condition
setup time
tSU;STA
I2C Start or repeated Start condition
hold time
tHD;STA
tSU;STO
0.6
0.6
µs
µs
I2C Stop condition setup time
6.14 SPI Controller Timing Requirements
MIN
11.4
79.36
30
NOM
12
MAX
12.6
UNIT
MHz
ns
Frequency of SPI_CLK
ƒSPI
tPER
Period of SPI_CLK (1/F_SPI)
83.33
87.72
tWHI
SPI_CLK high width
ns
tWLO
SPI_CLK low width
30
ns
tDACT
tDINACT
tDPICO
tSUPOCI
tHDMSIO
tRIN
SPI_SZZ falling to SPI_CLK rising delay time
SPI_CLK falling to SPI_CSZ rising delay time
SPI_CLK falling to SPI_PICO Valid delay time
SPI_POCI valid to SPI_CLK falling setup time
SPI_CLK falling to SPI_POCI invalid hold time
SPI_POCI input rise time
30
50
180
10
ns
158
–10
33
ns
ns
ns
0
ns
5
ns
10% to 90%, CL = 5 to 50 pF, LDO_3V3 =
3.3 V
tRSPI
tFSPI
SPI_CSZ/CLK/PICO rise time
SPI_CSZ/CLK/PICO fall time
1
1
25
ns
ns
90% to 10%, CL = 5 to 50 pF, LDO_3V3 =
3.3 V
25
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UNIT
6.15 HPD Timing Requirements
MIN
NOM
MAX
DP SOURCE SIDE (HPD
TX)
tIRQ_MIN
HPD IRQ minimum assert time
HPD assert 2-ms min time
675
3
750
825
µs
t2 MS_MIN
3.33
3.67
ms
DP SINK SIDE (HPD
RX)
HPD_HDB_SEL = 0
HPD_HDB_SEL = 1
300
100
300
1.35
375
111
375
1.5
450
122
450
1.65
µs
ms
µs
tHPD_HDB
HPD high debounce time
tHPD_LDB
tHPD_IRQ
HPD low debounce time
HPD IRQ limit time
ms
6.16 Typical Characteristics
32
100
70
50
30
20
30
28
26
24
22
10
7
5
3
2
1
0.7
0.5
100ms
10ms
1ms
100us
10us
0.3
0.2
0.1
0.5 0.7
1
2
3
4 5 6 7 8 10
Vds (V)
20 30 40 50
-20
0
20
40
60
80
Temperature (°C)
100
120
140
D005
D004
图6-2. PPHVx SOA Curve
图6-1. PPHVx Rdson vs Junction Temperature
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7 Parameter Measurement Information
t
f
t
r
t
SU;DAT
70 %
30 %
70 %
30 %
SDA
cont.
t
t
HD;DAT
VD;DAT
t
f
t
HIGH
t
r
70 %
30 %
70 %
30 %
70 %
30 %
70 %
30 %
SCL
cont.
t
HD;STA
t
LOW
th
9
clock
1 / f
S
SCL
st
1
clock cycle
t
BUF
SDA
SCL
t
VD;ACK
t
t
t
t
SU;STO
SU;STA
HD;STA
SP
70 %
30 %
Sr
P
S
th
9
clock
002aac938
图7-1. I2C Slave Interface Timing
t
t
t
wlow
per
whigh
SPI_CSZ
SPI_CLK
t
t
dinact
dact
t
t
dpico
dpico
SPI_PICO
SPI_POCI
Valid Data
t
supoci
Valid Data
t
hdpoci
图7-2. SPI Controller Timing
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8 Detailed Description
8.1 Overview
The TPS65988DK is a fully-integrated USB Power Delivery (USB-PD) management device providing cable plug
and orientation detection for two USB Type-C and PD plug or receptacles. The TPS65988DK communicates with
the cable and another USB Type-C and PD device at the opposite end of the cable, enables integrated port
power switch, controls an external high current port power switch and negotiates alternate modes for each port.
The TPS65988DK may also control an attached super-speed multiplexer via GPIO or I2C to simultaneously
support USB3.0/3.1 data rates and DisplayPort video.
Each Type-C port controlled by the TPS65988DK is functionally identical and supports the full range of the USB
Type-C and PD standards.
The TPS65988DK is divided into five main sections:
• USB-PD controller
• cable plug and orientation detection circuitry
• port power switches
• power management circuitry
• digital core
The USB-PD controller provides the physical layer (PHY) functionality of the USB-PD protocol. The USB-PD
data is output through either the C_CC1 pin or the C_CC2 pin, depending on the orientation of the reversible
USB Type-C cable. For a high-level block diagram of the USB-PD physical layer, a description of its features and
more detailed circuitry, see the USB-PD Physical Layer section.
The cable plug and orientation detection analog circuitry automatically detects a USB Type-C cable plug
insertion and also automatically detects the cable orientation. For a high-level block diagram of cable plug and
orientation detection, a description of its features and more detailed circuitry, see Port Power Switches.
The port power switches provide power to the system port through the VBUS pin and also through the C_CC1 or
C_CC2 pins based on the detected plug orientation. For a high-level block diagram of the port power switches, a
description of its features and more detailed circuitry, see the Port Power Switches section.
The power management circuitry receives and provides power to the TPS65988DK internal circuitry and to the
LDO_3V3 output. For a high-level block diagram of the power management circuitry, a description of its features
and more detailed circuitry, see the Power Management section.
The digital core provides the engine for receiving, processing and sending all USB-PD packets as well as
handling control of all other TPS65988DK functionality. A portion of the digital core contains ROM memory which
contains all the necessary firmware required to execute Type-C and PD applications. In addition, a section of the
ROM called boot code, is capable of initializing the TPS65988DK, loading of device configuration information
and loading any code patches into volatile memory in the digital core. For a high-level block diagram of the
digital core, a description of its features and more detailed circuitry, see the Digital Core section.
The TPS65988DK is an I2C slave to be controlled by a host processor (see the I2C Interfaces section), and an
SPI controller to write to and read from an optional external flash memory (see the SPI Controller Interface
section).
The TPS65988DK also integrates a thermal shutdown mechanism (see theThermal Shutdown section) and runs
off of accurate clocks provided by the integrated oscillators (see the Oscillators section).
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8.2 Functional Block Diagram
PP_HV1
VBUS1
VBUS2
5 A
PP_HV2
5 A
600 mA
PP1_CABLE
600 mA
LDO_3V3
LDO_1V8
PP2_CABLE
VIN_3V3
HRESET
Power & Supervisor
ADCIN1
Cable Detect &
C1_CC1
ADCIN2
5
USB-PD Phy
C1_CC2
GPIO0-4
3
Cable Power
I2C1_SDA/SCL/IRQ
3
I2C2_SDA/SCL/IRQ
3
I2C3_SDA/SCL/IRQ
4
SPI_PICO/POCI/CS/CLK
Cable Detect &
C2_CC1
USB-PD Phy
6
Core
&
Other Digital
GPIO12-17
C2_CC2
Cable Power
Charger
Detection &
Advertisement
2
2
C1_USB_P/N
C2_USB_P/N
PPAD
8.3 Feature Description
8.3.1 USB-PD Physical Layer
图 8-1 shows the USB PD physical layer block surrounded by a simplified version of the analog plug and
orientation detection block. This block is duplicated for the second TPS65988DK port.
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Fast
current
limit
600 mA
PP1_CABLE
Cx_CC1 Gate Control
and Current Limit
LDO_3V3
C1_CC1
C1_CC2
Digital
Core
USB-PD
Decode
LDO_3V3
Cx_CC1 Gate Control
and Current Limit
Fast
current
limit
图8-1. USB-PD Physical Layer, Simplified Plug and Orientation Detection Circuitry
USB-PD messages are transmitted in a USB Type-C system using a BMC signaling. The BMC signal is output
on the same pin (Cx_CC1 or Cx_CC2) that is DC biased due to the DFP (or UFP) cable attach mechanism
shown in Port Power Switches.
8.3.1.1 USB-PD Encoding and Signaling
图 8-2 illustrates the high-level block diagram of the baseband USB-PD transmitter. 图 8-3 illustrates the high-
level block diagram of the baseband USB-PD receiver.
4b5b
Encoder
BMC
Encoder
Data
to PD_TX
CRC
图8-2. USB-PD Baseband Transmitter Block Diagram
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Data
BMC
Decoder
SOP
Detect
4b5b
Decoder
from PD_RX
CRC
图8-3. USB-PD Baseband Receiver Block Diagram
The USB-PD baseband signal is driven on the Cx_CCn pins with a tri-state driver. The tri-state driver is slew rate
limited to reduce the high frequency components imparted on the cable and to avoid interference with
frequencies used for communication.
8.3.1.2 USB-PD Bi-Phase Marked Coding
The USBP-PD physical layer implemented in the TPS65988DK is compliant to the USB-PD Specifications. The
encoding scheme used for the baseband PD signal is a version of Manchester coding called Biphase Mark
Coding (BMC). In this code, there is a transition at the start of every bit time and there is a second transition in
the middle of the bit cell when a 1 is transmitted. This coding scheme is nearly DC balanced with limited disparity
(limited to 1/2 bit over an arbitrary packet, so a very low DC level). 图8-4 illustrates Biphase Mark Coding.
0
1
0
1
0
1
0
1
0
0
0
1
1
0
0
0
1
1
Data in
BMC
图8-4. Biphase Mark Coding Example
The USB PD baseband signal is driven onto the Cx_CC1 or Cx_CC2 pins with a tri-state driver. The tri-state
driver is slew rate to limit coupling to D+/D– and to other signal lines in the Type-C fully featured cables. When
sending the USB-PD preamble, the transmitter starts by transmitting a low level. The receiver at the other end
tolerates the loss of the first edge. The transmitter terminates the final bit by an edge to ensure the receiver
clocks the final bit of EOP.
8.3.1.3 USB-PD Transmit (TX) and Receive (Rx) Masks
The USB-PD driver meets the defined USB-PD BMC TX masks. Since a BMC coded “1” contains a signal
edge at the beginning and middle of the UI, and the BMC coded “0” contains only an edge at the beginning,
the masks are different for each. The USB-PD receiver meets the defined USB-PD BMC Rx masks. The
boundaries of the Rx outer mask are specified to accommodate a change in signal amplitude due to the ground
offset through the cable. The Rx masks are therefore larger than the boundaries of the TX outer mask. Similarly,
the boundaries of the Rx inner mask are smaller than the boundaries of the TX inner mask. Triangular time
masks are superimposed on the TX outer masks and defined at the signal transitions to require a minimum edge
rate that has minimal impact on adjacent higher speed lanes. The TX inner mask enforces the maximum limits
on the rise and fall times. Refer to the USB-PD Specifications for more details.
8.3.1.4 USB-PD BMC Transmitter
The TPS65988DK transmits and receives USB-PD data over one of the Cx_CCn pins for a given CC pin pair
(one pair per USB Type-C port). The Cx_CCn pins are also used to determine the cable orientation (see Port
Power Switches) and maintain the cable/device attach detection. Thus, a DC bias exists on the Cx_CCn pins.
The transmitter driver overdrives the Cx_CCn DC bias while transmitting, but returns to a Hi-Z state allowing the
DC voltage to return to the Cx_CCn pin when not transmitting. 图8-5 shows the USB-PD BMC TX and RX driver
block diagram.
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LDO_3V3
Driver
Level
Shifter
PD_TX
C_CC1
C_CC2
Level
Shifter
PD_RX
Digitally
Adjustable
VREF
USB-PD Modem
图8-5. USB-PD BMC TX/Rx Block Diagram
图 8-6 shows the transmission of the BMC data on top of the DC bias. Note, The DC bias can be anywhere
between the minimum threshold for detecting a UFP attach (VD_CCH_USB) and the maximum threshold for
detecting a UFP attach to a DFP (VD_CCH_3P0). This means that the DC bias can be below VOH of the
transmitter driver or above VOH.
VOH
DC Bias
DC Bias
VOL
VOH
DC Bias
DC Bias
VOL
图8-6. TX Driver Transmission with DC Bias
The transmitter drives a digital signal onto the Cx_CCn lines. The signal peak, VTXP, is set to meet the TX
masks defined in the USB-PD Specifications.
When driving the line, the transmitter driver has an output impedance of ZDRIVER. ZDRIVER is determined by
the driver resistance and the shunt capacitance of the source and is frequency dependent. ZDRIVER impacts
the noise ingression in the cable.
图 8-7 shows the simplified circuit determining ZDRIVER. It is specified such that noise at the receiver is
bounded.
RDRIVER
ZDRIVER
Driver
CDRIVER
图8-7. ZDRIVER Circuit
8.3.1.5 USB-PD BMC Receiver
The receiver block of the TPS65988DK receives a signal that falls within the allowed Rx masks defined in the
USB PD specification. The receive thresholds and hysteresis come from this mask.
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图 8-8 shows an example of a multi-drop USB-PD connection. This connection has the typical UFP (device) to
DFP (host) connection, but also includes cable USB-PD TX/Rx blocks. Only one system can be transmitting at a
time. All other systems are Hi-Z (ZBMCRX). The USB-PD Specification also specifies the capacitance that can
exist on the wire as well as a typical DC bias setting circuit for attach detection.
UFP
DFP
System
System
Pullup
Cable
for Attach
Detection
Connector
Connector
Tx
Rx
Tx
Rx
RD
for Attach
Detection
CRECEIVER
CRECEIVER
CCBLPLUG
CCBLPLUG
图8-8. Example USB-PD Multi-Drop Configuration
8.3.2 Power Management
The TPS65988DK power management block receives power and generates voltages to provide power to the
TPS65988DK internal circuitry. These generated power rails are LDO_3V3 and LDO_1V8. LDO_3V3 may also
be used as a low power output for external flash memory. The power supply path is shown in 图8-9.
VBUS1
VIN_3V3
VBUS2
VREF
LDO
LDO_3V3
LDO_1V8
VREF
LDO
图8-9. Power Supplies
The TPS65988DK is powered from either VIN_3V3, VBUS1, or VBUS2. The normal power supply input is
VIN3V3. In this mode, current flows from VIN_3V3 to LDO3V3 to power the core 3.3-V circuitry and I/Os. A
second LDO steps the voltage down from LDO_3V3 to LDO_1V8 to power the 1.8-V core digital circuitry. When
VIn_3V3 power is unavailable and power is available on VBUS1 or VBUS2 , the TPS65988DK is powered from
VBUS. In this mode, the voltage on VBUS1 or VBUS 2 is stepped down through an LDO to LDO_3V3.
8.3.2.1 Power-On and Supervisory Functions
A power-on reset (POR) circuit monitors each supply. This POR allows active circuitry to turn on only when a
good supply is present.
8.3.2.2 VBUS LDO
The TPS65988DK contains an internal high-voltage LDO which is capable of converting up to 22 V from VBUS
to 3.3 V for powering internal device circuitry. The VBUS LDO is only used during dead battery operation while
the VIN_3V3 supply is not present. The VBUS LDO may be powered from either VBUS1 or VBUS2. The path
connecting each VBUS to the internal LDO blocks reverse current, preventing power on one VBUS from leaking
to the other. When power is present on both VBUS inputs, the internal LDO draws current from both VBUS pins.
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8.3.2.3 Supply Switch Over
VIN_3V3 takes precedence over VBUS, meaning that when both supply voltages are present the TPS65988DK
powers from VIN_3V3. See 图 8-9 for a diagram showing the power supply path block. There are two cases in
which a power supply switch-over occurs. The first is when VBUS is present first and then VIN_3V3 becomes
available. In this case, the supply automatically switches over to VIN_3V3 and brown-out prevention is verified
by design. The other way a supply switch-over occurs is when both supplies are present and VIN_3V3 is
removed and falls below 2.85 V. In this case, a hard reset of the TPS65988DK is initiated by device firmware,
prompting a re-boot.
8.3.3 Port Power Switches
The figure below shows the TPS65988DK internal power paths. The TPS65988DK features two internal high-
voltage power paths. Each path contains two back to back common drain N-Fets, current monitor, overvoltage
monitor, undervoltage monitor, and temperature sensing circuitry. Each path may conduct up to 5 A safely.
Additional external paths may be controlled through the TPS65988DK GPIOs.
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Fast
current
limit
5A
PP_HV2
VBUS2
VBUS1
Fast
current
limit
5A
PP_HV1
PP_EXT1 (GPIO16)
PP_EXT2(GPIO17)
Dead
Battery
Supply
HV Gate Control and
Sense
HV Gate Control and
Sense
C1_CC1 Gate
Control
Fast
current
limit
PP1_CABLE
C1_CC1
600mA
C1_CC2 Gate
Control
C1_CC2
C2_CC1 Gate
Control
Fast
current
limit
PP2_CABLE
C2_CC1
600mA
C2_CC2 Gate
Control
C2_CC2
图8-10. Port Power Switches
8.3.3.1 PP_HV Power Switch
The TPS65988DK has two integrated bi-directional high-voltage switches that are rated for up to 5 A of current.
Each switch may be used as either a sink or source path for supporting USB-PD power up to 20 V at 5 A of
current.
Note
The power paths can sustain up to 5 A of continuous current as long as the internal junction
temperature of each path remains below 150°C. Care should be taken to follow the layout
recommendations described in DRAIN1 and DRAIN2 Pad Pours.
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8.3.3.1.1 PP_HV Overcurrent Clamp
The internal source PP_HV path has an integrated overcurrent clamp circuit. The current through the internal
PP_HV paths are current limited to IOCC. The IOCC value is selected by application firmware and only enabled
while acting as a source. When the current through the switch exceeds IOCC, the current clamping circuit
activates and the path behaves as a constant current source. If the duration of the overcurrent event exceeds
the deglitch time, the switch is latched off.
8.3.3.1.2 PP_HV Overcurrent Protection
The TPS65988DK continuously monitors the forward voltage drop across the internal power switches. When a
forward drop corresponding to a forward current of IOCP is detected the internal power switch is latched off to
protect the internal switches as well as upstream power supplies.
8.3.3.1.3 PP_HV OVP and UVP
Both the overvoltage and undervoltage protection levels are configured by application firmware. When the
voltage on a port's VBUS pin exceeds the set overvoltage threshold or falls below the set undervoltage threshold
the associated PP_HV path is automatically disabled.
8.3.3.1.4 PP_HV Reverse Current Protection
The TPS65988DK reverse current protection has two modes of operation: Comparator Mode and Ideal Diode
Mode. Both modes disable the power switch in cases of reverse current. The comparator protection mode is
enabled when the switch is operating as a source, while the ideal diode protection is enabled while operating as
a sink.
In the Comparator mode of reverse current protection, the power switch is allowed to behave resistively until the
current reaches the amount calculated in 方程式 1 and then blocks reverse current from VBUS to PP_HV. 图
8-11 shows the diode behavior of the switch with comparator mode enabled.
IREVHV = VREVHV/RPPHV
(1)
I
1/RPPHV
VREVHV
V
IREVHV
图8-11. Comparator Mode (Source) Internal HV Switch I-V Curve
In the Ideal Diode mode of reverse current protection, the switch behaves as an ideal diode and blocks reverse
current from PP_HV to VBUS. 图8-12 shows the diode behavior of the switch with ideal diode mode enabled.
I
1/RPPHV
VREVHV/RPPHV
VBUS-PP_HV
VREVHV
图8-12. Ideal Diode Mode (Sink) Internal HV Switch I-V Curve
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8.3.3.2 Schottky for Current Surge Protection
To prevent the possibility of large ground currents into the TPS65988DK during sudden disconnects due to
inductive effects in a cable, it is recommended that a Schottky diode be placed from VBUS to ground as shown
in 图8-13.
PP_HV2
PP_HV1
VBUS2
VBUS1
PPAD
图8-13. Schottky for Current Surge Protection
8.3.3.3 PP_EXT Power Path Control
GPIO16 and GPIO17 of the TPS65988DK are intended for control of additional external power paths. These
GPIO are active high when configured for external path control and disables in response to an OVP or UVP
event. Overcurrent protection and thermal shutdown are not available for external power paths controlled by
GPIO16 and GPIO17.
Note
GPIO16 and GPIO17 must be pulled to ground through an external pull-down resistor when used as
external path control signals.
8.3.3.4 PP_CABLE Power Switch
The TPS65988DK has two integrated 5-V unidirectional power muxes that are rated for up to 600 mA of current.
Each mux may supply power to either of the port CC pins for use as VCONN power.
8.3.3.4.1 PP_CABLE Overcurrent Protection
When enabled and providing VCONN power the TPS65988DK PP_CABLE power switches have a 600-mA
current limit. When the current through the PP_CABLE switch exceeds 600 mA, the current limiting circuit
activates and the switch behaves as a constant current source. The switches do not have reverse current
blocking when the switch is enabled and current is flowing to either Cx_CC1 or Cx_CC2.
8.3.3.4.2 PP_CABLE Input Good Monitor
The TPS65988DK monitors the voltage at the PP_CABLE pins prior to enabling the power switch. If the voltage
at PP_CABLE exceeds the input good threshold the switch is allowed to close, otherwise the switch remains
open. Once the switch has been enabled, PP_CABLE is allowed to fall below the input good threshold.
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8.3.3.5 VBUS Transition to VSAFE5V
The TPS65988DK has an integrated active pull-down on VBUS for transitioning from high voltage to VSAFE5V.
When the high voltage switch is disabled and VBUS > VSAFE5V, an amplifier turns on a current source and
pulls down on VBUS. The amplifier implements active slew rate control by adjusting the pull-down current to
prevent the slew rate from exceeding specification. When VBUS falls to VSAFE5V, the pull-down is turned off.
8.3.3.6 VBUS Transition to VSAFE0V
When VBUS transitions to near 0 V (VSAFE0V), the pull-down circuit in VBUS Transition to VSAFE5V is turned
on until VBUS reaches VSAFE0V. This transition occurs within time TSAFE0V.
8.3.4 Cable Plug and Orientation Detection
图 8-14 shows the plug and orientation detection block at each Cx_CCn pin (C1_CC1, C1_CC2, C2_CC1,
C2_CC2). Each pin has identical detection circuitry.
LDO_3V3
IH_CC_STD
IH_CC_1P5
IH_CC_3P0
VREF1
VREF2
VREF3
Cx_CCn
RD_CC
图8-14. Plug and Orientation Detection Block
8.3.4.1 Configured as a DFP
When one of the TPS65988DK ports is configured as a DFP, the device detects when a cable or a UFP is
attached using the Cx_CC1 and Cx_CC2 pins. When in a disconnected state, the TPS65988DK monitors the
voltages on these pins to determine what, if anything, is connected. See USB Type-C Specification for more
information.
表8-1 shows the Cable Detect States for a DFP.
表8-1. Cable Detect States for a DFP
C_CC1 C_CC2
CONNECTION STATE
Open Nothing attached
Open UFP attached
RESULTING ACTION
Continue monitoring both C_CC pins for attach. Power is not applied to VBUS or
VCONN until a UFP connect is detected.
Open
Rd
Monitor C_CC1 for detach. Power is applied to VBUS but not to VCONN (C_CC2).
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表8-1. Cable Detect States for a DFP (continued)
C_CC1 C_CC2
CONNECTION STATE
RESULTING ACTION
Open
Ra
Rd
UFP attached
Monitor C_CC2 for detach. Power is applied to VBUS but not to VCONN (C_CC1).
Powered Cable-No UFP
attached
Monitor C_CC2 for a UFP attach and C_CC1 for cable detach. Power is not applied to
VBUS or VCONN (C_CC1) until a UFP attach is detected.
Open
Powered Cable-No UFP
attached
Monitor C_CC1 for a UFP attach and C_CC2 for cable detach. Power is not applied to
VBUS or VCONN (C_CC1) until a UFP attach is detected.
Open
Ra
Ra
Rd
Ra
Rd
Ra
Provide power on VBUS and VCONN (C_CC1) then monitor C_CC2 for a UFP
detach. C_CC1 is not monitored for a detach.
Powered Cable-UFP Attached
Powered Cable-UFP attached
Provide power on VBUS and VCONN (C_CC2) then monitor C_CC1 for a UFP
detach. C_CC2 is not monitored for a detach.
Rd
Debug Accessory Mode
attached
Rd
Sense either C_CC pin for detach.
Sense either C_CC pin for detach.
Audio Adapter Accessory
Mode attached
Ra
When a TPS65988DK port is configured as a DFP, a current IH_CC is driven out each C_CCn pin and each pin
is monitored for different states. When a UFP is attached to the pin a pull-down resistance of Rd to GND exists.
The current IH_CC is then forced across the resistance Rd generating a voltage at the C_CCn pin.
When configured as a DFP advertising Default USB current sourcing capability, the TPS65988DK applies
IH_CC_USB to each C_CCn pin. When a UFP with a pull-down resistance Rd is attached, the voltage on the
C_CCn pin pulls below VH_CCD_USB. The TPS65988DK can be configured to advertise default (500 mA or
900 mA), 1.5-A and 3-A sourcing capabilities when acting as a DFP.
When the C_CCn pin is connected to an active cable VCONN input, the pull-down resistance is different (Ra). In
this case the voltage on the C_CCn pin will pull below VH_CCA_USB/1P5/3P0 and the system recognizes the
active cable.
The VH_CCD_USB/1P5/3P0 thresholds are monitored to detect a disconnection from each of these cases
respectively. When a connection has been recognized and the voltage on the C_CCn pin rises above the
VH_CCD_USB/1P5/3P0 threshold, the system registers a disconnection.
8.3.4.2 Configured as a UFP
When a TPS65988DK port is configured as a UFP, the TPS65988DK presents a pull-down resistance RD_CC
on each C_CCn pin and waits for a DFP to attach and pull-up the voltage on the pin. The DFP pulls-up the
C_CCn pin by applying either a resistance or a current. The UFP detects an attachment by the presence of
VBUS. The UFP determines the advertised current from the DFP by the pull-up applied to the C_CCn pin.
8.3.4.3 Configured as a DRP
When a TPS65988DK port is configured as a DRP, the TPS65988DK alternates the port's C_CCn pins between
the pull-down resistance, Rd, and pull-up current source, Rp.
8.3.4.4 Fast Role Swap Signaling
The TPS65988DK cable plug block contains additional circuitry that may be used to support the Fast Role Swap
(FRS) behavior defined in the USB Power Delivery Specification. The circuitry provided for this functionality is
detailed in 图8-15.
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Cx_CC1
Cx_CC2
To Cable
Detect and
Orientation
R_FRSWAP
R_FRSWAP
To Digital Core
VREF
图8-15. Fast Role Swap Detection and Signaling
When a TPS65988DK port is operating as a sink with FRS enabled, the TPS65988DK monitors the CC pin
voltage. If the CC voltage falls below VTH_FRS a fast role swap situation is detected and signaled to the digital
core. When this signal is detected the TPS65988DK ceases operating as a sink and begin operating as a
source.
When a TPS65988DK port is operating as a source with FRS enabled, the TPS65988DK digital core can signal
to the connected port partner that a fast role swap is required by enabling the R_FRSWAP pull down on the
connected CC pin. When this signal is sent the TPS65988DK ceases operating as the source and begin
operating as a sink.
8.3.5 Dead Battery Operation
8.3.5.1 Dead Battery Advertisement
The TPS65988DK supports booting from no-battery or dead-battery conditions by receiving power from VBUS.
Type-C USB ports require a sink to present Rd on the CC pin before a USB Type-C source provides a voltage on
VBUS. The TPS65988DK hardware is configured to present this Rd during a dead-battery or no-battery
condition. Additional circuitry provides a mechanism to turn off this Rd once the device no longer requires power
from VBUS. 图 8-16 shows the configuration of the C_CCn pins, and elaborates on the basic cable plug and
orientation detection block shown in 图 8-14. A resistance R_RPD is connected to the gate of the pull-down FET
on each C_CCn pin. During normal operation when configured as a sink, RD is RD_CC; however, while dead-
battery or no-battery conditions exist, the resistance is un-trimmed and is RD_DB. When RD_DB is presented
during dead-battery or no-battery, application code switches to RD_CC.
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C_CCn
R_RPD
RD_DB
RD_DB_EN
RD_CC
RD_CC_EN
图8-16. Dead Battery Pull-Down Resistor
In this case, the gate driver for the pull-down FET is Hi-Z at its output. When an external connection pulls up on
C_CCn (the case when connected to a DFP advertising with a pull-up resistance Rp or pull-up current), the
connection through R_RPD pulls up on the FET gate turning on the pull-down through RD_DB. In this condition,
the C_CCn pin acts as a clamp VTH_DB in series with the resistance RD_DB.
8.3.5.2 BUSPOWER (ADCIN1)
The BUSPOWER input to the internal ADC controls the behavior of the TPS65988DK in response to VBUS
being supplied during a dead battery condition. The pin must be externally tied to the LDO_3V3 output via a
resistive divider. At power-up the ADC converts the BUSPOWER voltage and the digital core uses this value to
determine start-up behavior. It is recommended to tie ADCin1 to LDO_3V3 through a resistor divider as shown in
图 8-17. For more information about how to use the ADCIN1 pin to configure the TPS65988DK, see the Boot
section.
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LDO_3V3
ADCIN1
R1
R2
ADC
图8-17. ADCIN1 Resistor Divider
Note
Devices implementing the BP_WaitFor3V3_External configuration must use GPIO16 for port 1
external path control and GPIO17 for port 2 external path control.
8.3.6 ADC
The TPS65988DK integrated ADC is accessible to internal firmware only. The ADC reads are not available for
external use.
8.3.7 DisplayPort HPD
To enable HPD signaling through PD messaging, a single pin is used as the HPD input and output for each port.
When events occur on these pins during a DisplayPort connection though the Type-C connector (configured by
firmware), hardware timers trigger and interrupt the digital core to indicate needed PD messaging. When one of
the TPS65988DK's ports is operating as a DP source, its corresponding HPD pin operates as an output (HPD
TX), and when a port is operating as a DP sink, its corresponding HPD pin operates as an input (HPD RX).
When DisplayPort is not enabled via firmware both HPD1 and HPD2 operate as generic GPIOs (GPIO3 and
GPIO4).
8.3.8 Digital Interfaces
8.3.8.1 General GPIO
图8-18 shows the GPIO I/O buffer for all GPIOn pins. GPIOn pins can be mapped to USB Type-C, USB PD, and
application-specific events to control other ICs, interrupt a host processor, or receive input from another IC. This
buffer is configurable to be a push-pull output, a weak push-pull, or open drain output. When configured as an
input, the signal can be a de-glitched digital input . The push-pull output is a simple CMOS output with
independent pull-down control allowing open-drain connections. The weak push-pull is also a CMOS output, but
with GPIO_RPU resistance in series with the drain. The supply voltage to the output buffer is LDO_3V3 and
LDO_1V8 to the input buffer. When interfacing with non 3.3-V I/O devices the output buffer may be configured as
an open drain output and an external pull-up resistor attached to the GPIO pin. The pull-up and pull-down output
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drivers are independently controlled from the input and are enabled or disabled via application code in the digital
core.
LDO_3V3
GPIO_OD_EN
GPIO_OE
GPIO_DO
GPIO_PU_EN
GPIO_RPU
GPIO_RPD
GPIO_PD_EN
20ns
Deglitch
GPIO
GPIO_DI
GPIO_AI_EN
图8-18. General GPIO Buffer
8.3.8.2 I2C
The TPS65988DK features three I2C interfaces. The I2C1 interface is configurable to operate as a master or
slave. The I2C2 interface may only operate as a slave. The I2C3 interface may only operate as a master. The I2C
I/O driver is shown in 图 8-19. This I/O consists of an open-drain output and in input comparator with de-
glitching. The I2C input thresholds are set by LDO_1V8 and by default.
50ns
I2C_DI
Deglitch
I2C_SDA/SCL
I2C_DO
图8-19. I2C Buffer
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8.3.8.3 SPI
The TPS65988DK has a single SPI controller interface for use with external memory devices. 图 8-20 shows the
I/O buffers for the SPI interface.
SPI_x
SPIin
CMOS
Output
SPIout
SPI_OE
图8-20. SPI buffer
8.3.9 Digital Core
The figure below shows a simplified block diagram of the digital core.
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HRESET
GPIO 0-4
GPIO 12-17
GPIO 20-21
I2C1_SDA
I2C1_SCL
I2C1_IRQZ
I2C2_SDA
I2C2_SCL
I2C2_IRQZ
I2C3_SDA
I2C3_SCL
I2C3_IRQZ
SPI_CLK
I2C
Port 1
I2C to
System Control
I2C
Port 2
I2C to
Thunderbolt Controller
Digital Core
CBL_DET
Bias CTL
USB PD Phy
and USB-PD
I2C
Port 3
I2C to
I2C Peripherals
SPI_PICO
SPI_POCI
SPI_CSZ
SPI to
Flash
(firmware)
SPI
OSC
Temp
Sense
Thermal
Shutdown
图8-21. Digital Core Block Diagram
8.3.10 I2C Interfaces
8.3.10.1 I2C Interface Description
The TPS65988DK support Standard and Fast mode I2C interface. The bidirectional I2C bus consists of the serial
clock (SCL) and serial data (SDA) lines. Both lines must be connected to a supply through a pull-up resistor.
Data transfer may be initiated only when the bus is not busy.
A master sending a Start condition, a high-to-low transition on the SDA input/output, while the SCL input is high
initiates I2C communication. After the Start condition, the device address byte is sent, most significant bit (MSB)
first, including the data direction bit (R/W).
After receiving the valid address byte, this device responds with an acknowledge (ACK), a low on the SDA input
and output during the high of the ACK-related clock pulse. On the I2C bus, only one data bit is transferred during
each clock pulse. The data on the SDA line must remain stable during the high pulse of the clock period as
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changes in the data line at this time are interpreted as control commands (Start or Stop). The master sends a
Stop condition, a low-to-high transition on the SDA input and output while the SCL input is high.
Any number of data bytes can be transferred from the transmitter to receiver between the Start and the Stop
conditions. Each byte of eight bits is followed by one ACK bit. The transmitter must release the SDA line before
the receiver can send an ACK bit. The device that acknowledges must pull down the SDA line during the ACK
clock pulse, so that the SDA line is stable low during the high pulse of the ACK-related clock period. When a
slave receiver is addressed, it must generate an ACK after each byte is received. Similarly, the master must
generate an ACK after each byte that it receives from the slave transmitter. Setup and hold times must be met to
ensure proper operation.
A master receiver signals an end of data to the slave transmitter by not generating an acknowledge (NACK) after
the last byte has been clocked out of the slave. The master receiver holding the SDA line high does this. In this
event, the transmitter must release the data line to enable the master to generate a Stop condition.
图 8-22 shows the start and stop conditions of the transfer. 图 8-23 shows the SDA and SCL signals for
transferring a bit. 图8-24 shows a data transfer sequence with the ACK or NACK at the last clock pulse.
SDA
SCL
S
P
Start Condition
Stop Condition
图8-22. I2C Definition of Start and Stop Conditions
SDA
SCL
Data Line
Change
图8-23. I2C Bit Transfer
Data Output
by Transmitter
Nack
Data Output
by Receiver
SCL From
Master
Ack
1
2
8
9
S
Clock Pulse for
Acknowledgement
Start
Condition
图8-24. I2C Acknowledgment
8.3.10.2 I2C Clock Stretching
The TPS65988DK features clock stretching for the I2C protocol. The TPS65988DK slave I2C port may hold the
clock line (SCL) low after receiving (or sending) a byte, indicating that it is not yet ready to process more data.
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The master communicating with the slave must not finish the transmission of the current bit and must wait until
the clock line actually goes high. When the slave is clock stretching, the clock line remains low.
The master must wait until it observes the clock line transitioning high plus an additional minimum time (4 μs for
standard 100-kbps I2C) before pulling the clock low again.
Any clock pulse may be stretched but typically it is the interval before or after the acknowledgment bit.
8.3.10.3 I2C Address Setting
Each of the TPS65988DK's two I2C slave interfaces responds to two unique I2C addresses. The first address
allows communication with Port 1 of the TPS65988DK and the second address allows communication with Port
2 of the TPS65988DK.
The boot flow sets the hardware configurable unique I2C addresses of the TPS65988DK before the port s are
enabled to respond to I2C transactions. For the I2C1 interface, the unique I2C address es are determined by the
analog level set by the analog ADCIN2 pin as shown in 表8-2 and 表8-3.
表8-2. I2C Default Unique Address I2C1 - Port 1
DEFAULT I2C UNIQUE ADDRESS
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
R/W
Set by ADCIN2 divider, see I2C Pin Address Setting (ADCIN2)
Note 1: Any bit is maskable for each port independently providing firmware override of the I2C address.
表8-3. I2C Default Unique Address I2C1 - Port 2
DEFAULT I2C UNIQUE ADDRESS
Bit 7
Bit 6
Bit 5
Set by ADCIN2 divider, see I2C Pin Address Setting (ADCIN2)
Note 1: Any bit is maskable for each port independently providing firmware override of the I2C address.
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
R/W
For the I2C2 interface, the unique I2C address is a fixed value as shown in 表8-4 and 表8-5.
表8-4. I2C Default Unique Address I2C2 - Port 1
DEFAULT I2C UNIQUE ADDRESS
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
R/W
Set by ADCIN2 divider, see I2C Pin Address Setting (ADCIN2)
Note 1: Any bit is maskable for each port independently, providing firmware override of the I2C address.
表8-5. I2C Default Unique Address I2C2 - Port 2
DEFAULT I2C UNIQUE ADDRESS
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
R/W
Set by ADCIN2 divider, see I2C Pin Address Setting (ADCIN2)
Note 1: Any bit is maskable for each port independently, providing firmware override of the I2C address.
Note
The TPS65988DK I2C address values are set and controlled by device firmware. Certain firmware
configurations may override the presented address settings.
8.3.10.4 Unique Address Interface
The Unique Address Interface allows for complex interaction between an I2C master and a single TPS65988DK.
The I2C Slave sub-address is used to receive or respond to Host Interface protocol commands. 图 8-25 and 图
8-26 show the write and read protocol for the I2C slave interface, and a key is included in 图 8-27 to explain the
terminology used. The TPS65988DK Host interface uses a different unique address to identify each of the two
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USB Type-C ports controlled by the TPS65988DK. The key to the protocol diagrams is in the SMBus
Specification and is repeated here in part.
1
7
1
1
8
1
8
1
8
1
S
Unique Address
Wr
A
Register Number
A
Byte Count = N
A
Data Byte 1
A
8
1
8
1
Data Byte 2
A
Data Byte N
A
P
图8-25. I2C Unique Address Write Register Protocol
1
S
7
1
1
8
1
1
7
1
1
8
1
Unique Address
Wr
A
Register Number
A
Sr
Unique Address
Rd
A
Byte Count = N
A
8
1
8
1
8
1
Data Byte 1
A
Data Byte 2
A
Data Byte N
A
1
P
图8-26. I2C Unique Address Read Register Protocol
1
7
1
1
A
x
8
1
A
x
1
S
Slave Address
Wr
Data Byte
P
S
Start Condition
SR
Rd
Wr
x
Repeated Start Condition
Read (bit value of 1)
Write (bit value of 0)
Field is required to have the value x
Acknowledge (this bit position may be 0 for an ACK or
1 for a NACK)
A
P
Stop Condition
Master-to-Slave
Slave-to-Master
Continuation of protocol
图8-27. I2C Read/Write Protocol Key
8.3.10.5 I2C Pin Address Setting (ADCIN2)
To enable the setting of multiple I2C addresses using a single TPS65988DK pin, a resistor divider is placed
externally on the ADCIN2 pin. The internal ADC then decodes the address from this divider value. 图8-28 shows
the decoding.
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LDO_3V3
R1
R2
ADC
ADCIN2
图8-28. I2C Address Divider
表8-6 lists the external divider needed to set bits [3:1] of the I2C Unique Address.
表8-6. I2C Address Selection
DIV = R2/(R1+R2)(1)
I2C1 UNIQUE ADDRESS (7bit)
I2C2 UNIQUE ADDRESS (7bit)
I2C2 PORT 1 I2C2 PORT 2
0x38 0x3F
DIV_min
DIV_max
I2C1 PORT 1
I2C1 PORT 2
0x24
Short to GND
0.18
0.38
0x20
0x21
0x22
0x23
0.20
0.40
0.6
0x25
0x3F
0x4F
0x48
0x38
0x48
0x4F
0.58
0x26
Short to LDO_3V3
0x27
(1) External resistor tolerance of 1% is required. Resistor values must be chosen to yield a DIV value centered nominally between listed
MIN and MAX values.
8.3.11 SPI Controller Interface
The TPS65988DK loads any ROM patch and-or configuration from flash memory during the boot sequence. The
TPS65988DK is designed to power the flash from LDO_3V3 in order to support dead-battery or no-battery
conditions, and therefore pull-up resistors used for the flash memory must be tied to LDO_3V3. The flash
memory IC must support 12 MHz SPI clock frequency. The size of the flash must be at least 64 kB. The SPI
controller of the TPS65988DK supports SPI Mode 0. For Mode 0, data delay is defined s0 that data is output on
the same cycle as chip select (SPI_CS pin) becomes active. The chip select polarity is active-low. The clock
phase is defined such that data (on the SPI_POCI and SPI_PICO pins) is shifted out on the falling edge of the
clock (SPI_CLK pin) and data is sampled on the rising edge of the clock. The clock polarity for chip select is
defined such that when data is not being transferred the SPI_CLK pin is held (or idling) low. The minimum
erasable sector size of the flash must be 4 KB. The W25X05CL or similar is recommended.
8.3.12 Thermal Shutdown
The TPS65988DK features a central thermal shutdown as well as independent thermal sensors for each internal
power path. The central thermal shutdown monitors the overall temperature of the die and disables all functions
except for supervisory circuitry when die temperature goes above a rising temperature of TSD_MAIN. The
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temperature shutdown has a hysteresis of TSDH_MAIN and when the temperature falls back below this value,
the device resumes normal operation.
The power path thermal shutdown monitors the temperature of each internal power path and disables the power
path in response to an overtemperature event. Once the temperature falls below TSDH_PWR the path can be
configured to resume operation or remain disabled until re-enabled by firmware.
8.3.13 Oscillators
The TPS65988DK has two independent oscillators for generating internal clock domains. A 24-MHz oscillator
generates clocks for the core during normal operation. A 100-kHz oscillator generates clocks for various timers
and clocking the core during low power states.
8.4 Device Functional Modes
8.4.1 Boot
At initial power on the device goes through a boot routine. This routine is responsible for initializing device
register values and loading device patch and configuration bundles. The device's functional behavior after boot
can be configured through the use of pin straps on the SPI_POCI and ADCIN1 pins as shown in 表8-7.
表8-7. Boot Mode Pin Strapping
ADCIN1
SPI_POCI
DIV = R2/(R1+R2)(1)
DEAD BATTERY MODE
DEVICE CONFIGURATION
DIV MIN
0.00
0.20
0.30
0.40
0.50
0.60
0.10
0.20
0.30
0.40
0.50
0.60
0.70
0.80
0.90
DIV MAX
0.18
0.28
0.38
0.48
0.58
1.00
0.18
0.28
0.38
0.48
0.58
0.68
0.78
0.88
1.00
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
BP_NoResponse
BP_WaitFor3V3_Internal
BP_ECWait_Internal
BP_WaitFor3V3_External
BP_ECWait_External
BP_NoWait
Safe Configuration
Safe Configuration
Infinite Wait
Safe Configuration
Infinite Wait
Safe Configuration
Infinite Wait
BP_NoResponse
BP_NoResponse
BP_ECWait_Internal
BP_NoWait
Infinite Wait
Infinite Wait
Configuration 3
Infinite Wait
BP_ECWait_External
BP_NoResponse
BP_NoWait
Infinite Wait
Reserved
BP_NoResponse
BP_NoWait
Infinite Wait
Configuration 5
(1) External resistor tolerance of 1% is required. Resistor values must be chosen to yield a DIV value centered nominally between listed
MIN and MAX values.
The pin strapping configures two different parameters, Dead battery mode and device configuration. The dead
battery mode selects device behavior when powered from VBUS. The dead battery mode behaviors are detailed
in 表8-8.
表8-8. Dead Battery Configurations
CONFIGURATION
DESCRIPTION
No power switch is enabled and the device does not start-up until VIN_3V3 is
present.
BP_NoResponse
The internal power switch from VBUSx to PP_HVx is enabled for the port receiving
power. The device does not continue to start-up or attempt to load device
configurations until VIN_3V3 is present.
BP_WaitFor3V3_Internal
BP_WaitFor3V3_External
The external power switch from VBUSx to PP_HVx is enabled for the port receiving
power. The device does not continue to start-up or attempt to load device
configurations until VIN_3V3 is present.
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表8-8. Dead Battery Configurations (continued)
CONFIGURATION
DESCRIPTION
The internal power switch from VBUSx to PP_HVx is enabled for the port receiving
power. The device infinitely tries to load configuration.
BP_ECWait_Internal
The external power switch from VBUSx to PP_HVx is enabled for the port receiving
power. The device infinitely tries to load configuration.
BP_ECWait_External
BP_NoWait
The device continues to start-up and attempts to load configurations while
receiving power from VBUS. Once configuration is loaded the appropriate power
switch is closed based on the loaded configuration.
Note
Devices implementing the BP_WaitFor3V3_External configuration must use GPIO16 for port 1
external path control and GPIO17 for port 2 external path control.
When powering up from VIN_3V3 or VBUS the device will attempt to load configuration information from the SPI
or I2C digital interfaces. The device configuration settings select the device behavior should configuration
information not be available during the device boot process. 表 8-9 shows the device behavior for each device
configuration setting.
表8-9. Device Default Configurations
CONFIGURATION
Safe
DESCRIPTION
Ports disabled, if powered from VBUS operates a legacy sink
Device infinitely waits in boot state for configuration information
Reserved
Infinite Wait
Configuration 1
Configuration 2
Reserved
UFP only (Internal Switch)
5-20 V at 0.9 - 3.0-A Sink capability
TBT Alternate Modes not enabled
DisplayPort Alternate Modes not enabled
Configuration 3
Configuration 4
Reserved
UFP only (External Switch))
5-20 V at 0.9-3.0-A Sink capability
5 V at 3.0-A Source capability
Configuration 5
TBT Alternate Modes not enabled
DisplayPort Alternate Modes not enabled
8.4.2 Power States
The TPS65988DK may operate in one of three different power states: Active, Idle, or Sleep. The functionality
available in each state is summarized in 表8-10.
表8-10. Power States
ACTIVE
IDLE
SLEEP
Type-C State
Type-C Port 1 State
LDO_3V3(1)
Connected or Unconnected
Connected or Unconnected
Unconnected
Valid
Valid
Valid
Valid
Valid
LDO_1V8
Valid
Oscillator Status
Digital Core Clock Frequency
100-kHz Oscillator Status
24-MHz Oscillator Status
12 MHz
Enabled
Enabled
4 MHz - 6 MHz
Enabled
100 kHz
Enabled
Disabled
Enabled
Available Features
Type-C Detection
Yes
Yes
Yes
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表8-10. Power States (continued)
ACTIVE
IDLE
SLEEP
PD Communication
I2C Communication
SPI Communication
Yes
No
No
No
No
Yes
Yes
No
Yes
Wake Events
Wake on Attach/Detach
Wake on PD Communication
Wake on I2C Communication
N/A
N/A
N/A
Yes
Yes(2)
Yes
Yes
No
Yes
(1) LDO_3V3 may be generated from either VIN_3V3 or VBUS. If LDO_3V3 is generated from VBUS, TPS65988DK ports only operate as
sinks.
(2) Wake up from Idle to Active upon a PD message is supported however the first PD message received is lost.
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9 Application and Implementation
Note
以下应用部分中的信息不属于TI 器件规格的范围，TI 不担保其准确性和完整性。TI 的客 户应负责确定
器件是否适用于其应用。客户应验证并测试其设计，以确保系统功能。
9.1 Application Information
The TPS65988DK firmware implements a host interface over I2C to allow for the configuration and control of all
device options. Initial device configuration is configured through a configuration bundle loaded onto the device
during boot. The bundle may be loaded through I2C or SPI. The TPS65988DK configuration bundle and host
interface allow the device to be customized for each specific application. The configuration bundle can be
generated through the Application Customization Tool.
9.2 Typical Applications
9.2.1 USB4 Device Application with Host Charging
The figure below shows a USB4 Device application, where there are a total of four Type-C PD Ports. One port is
the main connection to a USB4 Host that is a UFP in terms of data and a source of power. The other three ports
are DFPs in terms of data and source power. Generally the main UFP source Type-C PD port provides the
highest power (up to 100 W) to charge a USB4 Host. The key four devices in the system are the PD Controller
(2), Dock Management Controller, USB4 Hub Controller, and UFP Variable Power Supply.
Type-C Power
Barrel
Jack
I2C Communication
SPI Communication
Data Protocol
SPI
Flash
TPS65982DMC
TPS55288
System 5 V
USB2 UFP
USB2 DFP
I2C Host
USB4 Hub Controller
I2C Host
PPHV1
PPHV2
PPHV1
PPHV2
TPS65988
I2C2
I2C2
TPS65988
I2C1
I2C1
VBUS1
VBUS2
VBUS1
VBUS2
Port B DFP Type-C
(5V @ 3A)
Port C DFP Type-C
(5V @ 3A)
Port D DFP Type-C
(5V @ 3A)
图9-1. USB4 Device Block Diagram
In this application, two dual port TPS65988DK PD controllers are used to determine the connection and provide
power on the Type-C ports. The primary TPS65988DK manages Port A (UFP Source) and Port B (DFP Source).
The secondary TPS65988DK manages the other two, Port C (DFP Source) and Port D (DFP Source). For
systems that do not need all four ports a combination of TPS65988DK and TPS65988DK may be used to scale
for specific design requirements. The PD controllers have two I2C clients that are controlled by the Dock
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Management Controller and the USB4 Hub Controller. The PD controllers have an optional I2C Host that may be
used to control a variable power supply.
The Dock Management Controller (DMC), TPS65982DMC, main functions are the Connection Manager, Power
Manager, Input Power Control, Secure Firmware Update & booting of the PD controllers. The Connection
Manager determines the capabilities of the UFP connection and sets the DFP capabilities accordingly. The
Power Manager keeps the power allocated to each of the Type-C ports within a specific power budget and also
monitors the entire system power to keep from over loading the Barrel Jack adapter supply. The DMC also
controls the input power to the system and soft starts the power path to prevent large inrush currents when the
Barrel Jack supply is connected. The Secure Firmware Update is accomplished over USB2, the DMC is
connected to one of the USB2 DFP ports on the USB4 Hub Controller or USB2 Hub in the system. The DMC
provides the Secure Firmware Update for itself and the PD controllers. The DMC will boot the PD controllers
over the I2C connection. The I2C connection between the DMC and PD controllers also serves as
communication channel for the Connection and Power Manager.
The USB4 Hub Controller manages the data paths for all of the Type-C ports and determines the required data
protocol by reading the PD controller status over I2C connection. The UFP port is the main connection to the
USB4 Hub Controller from a USB4 host. The other DFP ports act as expansion ports to connect other USB
Type-C & PD devices.
The UFP Variable Power Supply provides 5 V/9 V/15 V/20 V up to 100 W to charge the connected USB4 host.
The TPS55288 is used in this application since it is capable of tightly regulating the output voltage and current.
The TPS55288 is best connected to the I2C Host on the Primary PD controller, to set the output voltage and
current regulation. The other DFP ports generally support 5 V @ 3 A to connect to Type-C & PD devices.
9.2.1.1 Design Requirements
9.2.1.1.1 Power Supply Design Requirements
表9-1 shows the Power Design parameters for the USB4 Device application.
表9-1. Power Supply Design Requirements
POWER DESGIN PARAMETERS
VALUE
CURRENT PATH
UFP Source Port A
5 V/9 V/15 V/20 V @ 5 A
5 V @ 9 A (3 A per port)
5 V @ 2 A (500 mA per port)
20 V @ 10 A (Imax sensed)
3.3 V @ 150 mA (50 mA per device)
Host Charging VBUS
DFP VBUS
DFP Source Port B/C/D
PP_CABLE Port A/B/C/D
DMC External Input Path
VIN_3V3 PD Controller & DMC
VCONN Source
USB4 Device Input Power
PD Controller & DMC Power
9.2.1.2 Detailed Design Procedure
9.2.1.2.1 USB Power Delivery Source Capabilities
表9-2 summarizes the source PDOs for all of the ports for the USB4 Device.
表9-2. Source Capabilities
PORT
Port A
Port B
Port C
Port D
PDO TYPES
VOLTAGE
CURRENT
Fixed
5 V/9 V/15 V/20 V
3 A/3 A/3 A/5 A
Fixed
5 V
5 V
5 V
3 A
3 A
3 A
Fixed
Fixed
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9.2.1.2.2 USB Power Delivery Sink Capabilities
The UFP Source port is the only DRP port that may connect as a DFP or UFP which means that it should have
at least one sink capability when connected as a UFP. The DFP ports can only connect as a DFP, where they do
not have any sink capabilities.
表9-3. Sink Capabilities
PORT
PDO TYPES
VOLTAGE
CURRENT
Port A
Fixed
5 V
0 A
9.2.1.2.3 Supported Data Modes
USB4 Hub Controllers may vary on the data supported on the UFP and DFP ports. In this specific example the
USB4 Hub Controllers support USB3, DisplayPort, Thunderbolt, and USB4 on the UFP Port. The DFP Ports will
also support these modes when connected to other Type-C & PD devices.
表9-4. Data Modes
MODE OF OPERATION
USB Data
DATA
DATA ROLE
USB3.1 Gen2
DP Video
UFP: Device, DFP: Host
UFP: UFP_D, DFP: DFP_D
UFP: Host/Device, DFP: Host
UFP: Device, DFP Host
DisplayPort
Thunderbolt
USB4
PCIe/DP Video
Tunneled USB3/PCIe/DP
9.2.1.2.4 USB4 Hub Controller & PD Controller I2C Communication
The I2C connection from the PD controllers and the USB4 Hub Controller communicates the connection present
at the Type-C Ports. Each port on the USB4 controller may have its I2C interrupt pin to notify the USB4 Hub
Controller which port has a new connection. The PD controllers have an option to use the shared interrupt for
both ports or to have a separate interrupt for each port that is mapped to a GPIO in its configuration. In the
shared interrupt case, the USB4 Hub Controller will query both port addresses and will determine which port has
a data connection. For the dedicated interrupt the USB4 hub controller will only query the specific port address
and determine the connection present.
图9-2 shows the dedicated GPIO interrupt connection.
PA IRQ
PD IRQ
PC IRQ
USB4 Hub Controller
PB IRQ
I2C Host
PA GPIO IRQ
PB GPIO IRQ
I2C2
Client
PC GPIO IRQ
I2C2
Client
PD GPIO IRQ
TPS65988
TPS65988
I2C Communication
I2C Interrupt
图9-2. Dedicated Interrupts for USB4 Hub
图9-3 shows the shared interrupt connection on I2C2_IRQ.
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PA IRQ
PD IRQ
PC IRQ
USB4 Hub Controller
PB IRQ
I2C Host
PB GPIO IRQ
I2C2_IRQ
I2C2
Client
I2C2
Client
TPS65988
TPS65988
I2C Communication
I2C Interrupt
图9-3. Shared Interrupts for USB4 Hub
表9-5 shows an example of the port I2C addresses for each of the PD controller ports.
表9-5. Recommended I2C Addresses - Hub Controller
PORT
Port A
Port B
Port C
Port D
I2C ADDRESS
0x38
0x3F
0x48
0x4F
9.2.1.2.5 Dock Management Controller & PD Controller I2C Communication
The I2C connection from the PD controllers and the Dock Management Controller communicates to boot up the
PD controllers and enable the Connection & Power Manager functions. The DMC has two GPIO dedicated for
Port A/B and Port C/D interrupts. The shared interrupt connection to the Dock Management Controller will query
both port addresses and will determine which port has been updated.
PA/PB GPIO IRQ
PC/PD GPIO IRQ
TPS65982DMC
I2C Host
I2C1_IRQ
I2C1 Client
I2C1 Client
I2C1_IRQ
I2C Communication
I2C Interrupt
TPS65988
TPS65988
图9-4. Interupt Configuration for DMC
表9-6 shows and example of the port I2C address for each of the PD controller ports.
表9-6. Recommended I2C Addresses - DMC
PORT
Port A
Port B
I2C ADDRESS
0x20
0x24
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表9-6. Recommended I2C Addresses - DMC (continued)
PORT
Port C
Port D
I2C ADDRESS
0x21
0x25
9.2.1.2.6 SPI Flash Options
The TPS65982DMC is connected to the SPI Flash which contains the firmware for the DMC and the PD
controllers connected. 表9-7 shows the supported SPI flash options.
表9-7. SPI Flash Options
MANUFACTURER
Winbond
Spansion
AMIC
PART NUMBER
W25Q80JVNIQ
S25FL208K
SIZE
8 Mb
8 Mb
8 Mb
8 Mb
8 Mb
8 Mb
A25L080
Macronix
Micron
MX25L8006EM1I
M25PE80-VMN6TP
M25PX80-VMN6TP
Micron
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10 Power Supply Recommendations
10.1 3.3-V Power
10.1.1 VIN_3V3 Input Switch
The VIN_3V3 input is the main supply to the TPS65988DK device. The VIN_3V3 switch (see 图 8-9) is a
unidirectional switch from VIN_3V3 to LDO_3V3, not allowing current to flow backwards from LDO_3V3 to
VIN_3V3. This switch is on when 3.3 V is available. See 表 10-1 for the recommended external capacitance on
the VIN_3V3 pin.
10.1.2 VBUS 3.3-V LDO
The 3.3-V LDO from VBUS steps down voltage from VBUS to LDO_3V3 which allows the TPS65988DK device
to be powered from VBUS when VIN_3V3 is unavailable. This LDO steps down any recommended voltage on
the VBUS pin. When VBUS is 20 V, as is allowable by USB PD, the internal circuitry of the TPS65988DK device
operates without triggering thermal shutdown; however, a significant external load on the LDO_3V3 pin can
increase the temperature enough to trigger a thermal shutdown. The VBUS 3.3-V LDO blocks reverse current
from LDO_3V3 back to VBUS allowing VBUS to be unpowered when LDO_3V3 is driven from another source.
See 表10-1 for the recommended external capacitance on the VBUS and LDO_3V3 pins.
10.2 1.8-V Power
The internal circuitry is powered from 1.8 V. The 1.8-V LDO steps the voltage down from LDO_3V3 to 1.8 V. The
1.8-V LDO provides power to all internal low-voltage digital circuits which includes the digital core, memory and
other digital circuits. The 1.8-V LDO also provides power to all internal low-voltage analog circuits. See 表 10-1
for the recommended external capacitance on the LDO_1V8 pin.
10.3 Recommended Supply Load Capacitance
表 10-1 lists the recommended board capacitances for the various supplies. The typical capacitance is the
nominally rated capacitance that must be placed on the board as close to the pin as possible. The maximum
capacitance must not be exceeded on pins for which it is specified. The minimum capacitance is minimum
capacitance allowing for tolerances and voltage derating ensuring proper operation.
表10-1. Recommended Supply Load Capacitance
CAPACITANCE
VOLTAGE
RATING
PARAMETER
DESCRIPTION
MIN
TYP
MAX
(ABSOLUTE) (PLACED) (ABSOLUTE)
CVIN_3V3
CLDO_3V3
CLDO_1V8
CVBUS1
Capacitance on VIN_3V3
Capacitance on LDO_3V3
Capacitance on LDO_1V8
Capacitance on VBUS1
Capacitance on VBUS2
6.3 V
6.3 V
4 V
5 µF
5 µF
10 μF
10 µF
4.7 µF
1 µF
25 µF
12 µF
12 µF
12 µF
2.2 µF
0.5 µF
0.5 µF
2.5 µF
1 µF
25 V
25 V
10 V
25 V
CVBUS2
1 µF
CPP_HV_SRC
CPP_HV_SNK
Capacitance on PP_HV when configured as a 5-V source
Capacitance on PP_HV when configured as a 20-V sink
4.7 µF
47 µF
120 µF
Capacitance on PP_CABLE. When shorted to PP_HV congifured as a 5-V
source, the CPP_HV_SRC capacitance may be shared.
CPP_CABLE
10 V
2.5 µF
4.7 µF
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11 Layout
11.1 Layout Guidelines
A dual port full featured USB Type-C and PD system can be easily implemented in a 20 mm × 40 mm (800 mm2)
area with the TPS65988DK. This area includes two Type-C receptacles, two low Rdson external power paths,
Type-C protection for CC and SBU pins, and the TPS65988DK. The layout techniques in this guide can be
applied to other USB Type-C systems.
11.2 Layout Example
The schematic below shows the design used for this layout example. All TPS65988 I/O are routed in this
example, not all designs will use all of the I/O on the device. For differential routing for USB3.1, USB2.0,
DisplayPort, and Thunderbolt follow their requirements defined by their respective specifications.
U1A
C1
220pF
GND
16
17
18
30
31
21
22
23
36
37
38
39
40
41
42
43
48
49
50
53
54
55
24
26
GPIO0
GPIO1
C1_CC1
C1_CC2
C1_CC1
C1_CC2
GPIO_0
GPIO_1
GPIO_2
GPIO_3
GPIO_4
GPIO_5
GPIO_6
GPIO_7
SPI_POCI
SPI_PICO
SPI_CLK
SPI_CS
GPIO_12
GPIO_13
GPIO_14
GPIO_15
PA_PPEXT_EN
PB_PPEXT_EN
C1_USB_P
C1_USB_N
C2_USB_P
C2_USB_N
GPIO2
HPD1 (GPIO3)
HPD2 (GPIO4)
I2C3_SCL (GPIO5)
I2C3_SDA (GPIO6)
I2C3_IRQ (GPIO7)
SPI_POCI (GPIO8)
SPI_PICO (GPIO9)
SPI_CLK (GPIO10)
SPI_CS (GPIO11)
GPIO12
C2
220pF
27
28
29
I2C1_SCL
I2C1_SDA
I2C1_IRQ
I2C1_SCL
I2C1_SDA
I2C1_IRQZ
C3
220pF
GND
45
47
GND
C2_CC1
C2_CC2
C2_CC1
C2_CC2
C4
220pF
32
33
34
I2C2_SCL
I2C2_SDA
I2C2_IRQ
I2C2_SCL
I2C2_SDA
I2C2_IRQZ
GPIO13
GPIO14 (PWM)
GPIO15 (PWM)
GPIO16 (PP_EXT1)
GPIO17 (PP_EXT2)
C1_USB_P (GPIO18)
C1_USB_N (GPIO19)
C2_USB_P (GPIO20)
C2_USB_N (GPIO21)
GND
LDO_3V3
44
6
HRESET
ADCIN1
ADCIN2
HRESET
R1
10.0k
10
TPS65988DHRSHR
R2
100k
R3
10.0k
GND
C5
1µF
C6
1µF
U1B
GND
VBUS1
C7
10µF
GND
35
9
13
14
LDO_1V8
LDO_3V3
LDO_1V8
VBUS1
VBUS1
LDO_3V3
R4
100k
3
4
VBUS2
VBUS2
VBUS2
C8
10µF
25
46
SYS_5V0
PP1_CABLE
PP2_CABLE
C9
22µF
C10
22µF
11
12
PP_HV1
PP_HV1
SYS_5V0
GND
DRAIN1
DRAIN2
8
15
19
58
GND
DRAIN1
DRAIN1
DRAIN1
DRAIN1
1
2
PP_HV2
PP_HV2
GND
C11
22µF
C12
22µF
5
VIN_3V3
VIN_3V3
7
52
56
57
DRAIN2
DRAIN2
DRAIN2
DRAIN2
C13
10µF
GND
GND
20
51
59
GND
GND
GND
GND
TPS65988DHRSHR
GND
Common Source Configuration
Common Source Configuration
Q1A
7,8
Q1B
5,6
1
3
3
1
SYS_PWR
VBUS1
SYS_PWR
VBUS2
5,6
7,8
C15
0.1µF
C16
1µF
R5
10.0k
C17
0.1µF
C19
0.1µF
C20
1µF
R6
10.0k
C21
0.1µF
C14
10µF
C18
10µF
Q2B
Q2A
GND
GND
R7
10.0k
R8
10.0k
1
1
PA_PPEXT_EN
PB_PPEXT_EN
Q3
Q4
R9
100k
R10
100k
GND
GND
图11-1. Layout Example Device Schematic
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图11-2. Example Connector Schematic
11.3 Stack-up and Design Rules
An 8-layer stack-up is used and this particular stack is common with most processor chipset guides. In some
systems a 10-layer stack-up is used, the same principles can be carried over from the 8-layer to a 10-layer
stack-up. 图11-3 shows the details of each of the layers. The two outer layers have a thickness of 1.0-oz copper
and the inner layers are 0.5-oz copper.
图11-3. 8 Layer Board Stack Up
表 11-1 shows the recommended routing for each of these layers. For power routing the Power 1/2 planes can
be stacked to allow for high currents.
表11-1. Recommend Routing for Layers
Layer
Routing
SSTXRX1
High Speed
Power 1
Differential: 85 Z, 90 Z, 100 Z, Single Ended: 50 Z, Power, and GPIO
Differential: 85 Z, 90 Z, 100 Z, Single Ended: 50 Z, and GPIO
Power and GPIO
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表11-1. Recommend Routing for Layers (continued)
Layer
Power 2
SSTXRX2
Routing
Power and GPIO
Differential: 85 Z, 90 Z, 100 Z, Single Ended: 50 Z, Power, and GPIO
The vias used in this layout example are 8mil/16mil. There are no blind and buried vias used in this layout
example and for any via on pad used it is recommended to use epoxy filled vias. The figure below shows the via
sizing.
图11-4. Recommended Minimum Via Sizing
11.4 Main Component Placement
This layout example will place the two Type-C connectors close to each other as they would be a notebook. The
Type-C connectors are placed 1000 mils from center to center. This will allow for enough space for the end-user
to plug in two USB Type-C devices with ease. The external power paths can be placed in between the ports to
make the connection to the system supply easier. The TPS65988DK is placed above the external power path.
This will make for a better connection to VBUS for the TPS65988DK and the external power path. The High
Level Placement figure below shows the solution size and placement of these main components. It is
recommended to follow the layout guide in a step by step process.
图11-5. High Level Placement
11.5 Super Speed Type-C Connectors
In this layout example a dual row SMT mid mount Type-C connector is used. Start by placing vias for all the
signals on the Type-C connector that need to be routed on another layer. Once the vias have been placed, route
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out the super speed lines and place their ESD protection close to the Type-C connector. The figures below show
the via placement, top routing, and bottom routing for the super speed signals on the Type-C connector. The
same should be implemented for both Type-C connectors.
图11-6. Type-C Connector Via Placement
图11-7. Type-C Connector SSTXRX Top Layer
图11-8. Type-C Connector SSTXRX Bottom Layer
11.6 Capacitor Placement
All of the capacitors for the TPS65988DK must be placed close to their respective pin. For the PP_HV1/2,
VBUS1/2, VIN_3V3 and LDO_3V3 it is recommended to place their capacitors on the opposite side of the
TPS65988DK with the GND terminal facing away from the TPS65988DK. This method will have all of the GND
terminals together in order to have a solid plane that can be stitched to GND. The DRAIN1/2 pad will also have
more room for their bottom side pour. PP_CABLE1/2 and LDO_1V8 are placed on the opposite side but their
GND terminals are facing toward the TPS65988DK to share the common GND pour from the TPS65988DK GND
pad. VBUS1/2 and PP_HV1/2 should have at least four vias to connect the TPS65988DK pin, capacitors and
pours. For VIN_3V3, LDO_3V3, LDO_1V8 and PP_CABLE1/2 they can be connected with a single via to their
capacitors and pours.
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图11-9. System Capacitors Placement Top/Bottom 图11-10. System Capacitors Placement Top Layer
Layer
图11-11. System Capacitors Placement Bottom Layer
11.7 CC1/2 Capacitors & ADCIN1/2 Resistors
The CC1/2 capacitors should be placed on the same layer as the TPS65988DK and should be placed relatively
close to the pins. The ADCIN1/2 resistors have more flexibility where they are placed. In this layout example
they are placed close to the LDO_3V3. The figure below shows the placement.
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图11-12. CC and ADCIN1/2 Component Placements
11.8 CC and SBU Protection Placement
The protection device should be placed close to the Type-C connector. In this layout example they are placed in
between the Type-C connectors and the TPS65988DK.
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图11-13. Protection Placement
11.9 CC Routing
Routing the CC lines with an 8 mil trace will guarantee the needed current for supporting powered Type C cables
through VCONN. For more information on VCONN refer to the Type C specification. For capacitor GND pin use
a 16-mil trace when possible. GPIO signals can be fanned out on the top layer with a 4-mil trace. 表 11-2
summarizes the minimum trace widths for these signals.
表11-2. Recommended Minimum Widths
Route
CC1, CC2, PP_CABLE1, PP_CABLE2
VIN_3V3, LDO_3V3, LDO_1V8
Component GND
Minimum Width (mils)
8
6
10
4
GPIO
图11-14 shows the CC routing from the connector to the protection device and to the TPS65988DK.
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图11-14. Complete CC Routing
11.10 DRAIN1 and DRAIN2 Pad Pours
The drain pads are used for dissipating heat from the two power paths. DRAIN1 and DRAIN2 should NEVER be
connected to each other or to GND. They should be left floating with their own nets assigned. The top layer
should have all of the DRAIN1 pins tied to the DRAIN1 pan and the DRAIN2 pins tied to the DRAIN2 pad. When
high currents are expected in the system it is recommended to place “fins”on the DRAIN1 and DRAIN2 pads.
The effective heat dissipation distance is roughly 3 mm from the pad so it does not have to extend to a large
area. 图11-15 shows the top layer routing for DRAIN1 and DRAIN2.
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图11-15. DRAIN1 and DRAIN2 Top Layer
On the bottom layer DRAIN1 and DRAIN2 pour are also required and it is recommended to have a larger pour
than the DRAIN1 and DRAIN2 pads. The bottom layer will provide most of the heat dissipation and space should
be reserved for the pours. 图11-16 shows the bottom layer routing for the DRAIN1 and DRAIN2 pads.
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图11-16. Figure 13. DRAIN1 and DRAIN2 Bottom Layer
11.11 VBUS Routing
When higher current are required in the system and there are space constraints it is recommended to stack
power planes to help carry the higher currents. These are mostly used at the Type-C connector where most of
the room will be reserved for SSTX/RX, USB2, SBU and CC signals. 表 11-3 summarizes the recommended
widths for various VBUS currents.
表11-3. Recommended Trace Width for VBUS Currents
VBUS Current
Trace Width (0.5 oz Copper)
Trace Width (1 oz Copper)
1.5 A
3 A
50 mil
100 mil
240 mil
30 mil
60 mil
5 A
120 mil
The figures below show the SSTXRX1, Power1, Power2 and SSTXRX2 layers and the VBUS routing for the two
ports.
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图11-18. VBUS Routing Power 1
图11-17. VBUS Routing Top Layer
图11-19. VBUS Routing Power 2
图11-20. VBUS Routing Bottom Layer
11.12 Completed Layout
A dual port Type-C and PD system can easily be placed and routed in an area smaller than 1 × 2 inches allowing
for Super Speed signals to be routed easily to the system. The figures below show the complete layout for all of
the layers and 3D views of the PCB area.
图11-21. SSTXRX1 Layer
图11-22. High Speed Layer
图11-23. Power 1 Layer
图11-24. Power 2 Layer
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图11-26. Top 3D View
图11-25. SSTXRX2 Layer
图11-27. Bottom 3D View
11.13 Power Dissipation
The total power dissipation inside the TPS65988DK should not cause the temperature of the power paths to
exceed the maximum junction temperature of 150°C or the controller to exceed the maximum junction
temperature to exceed 125°C.
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12 Device and Documentation Support
12.1 Device Support
12.1.1 Firmware Warranty Disclaimer
IN ORDER FOR THE TPS6598X DEVICE TO FUNCTION IN ACCORDANCE WITH THIS SPECIFICATIONS,
YOU WILL NEED TO DOWNLOAD THE LATEST VERSION OF THE FIRMWARE FOR THE DEVICE. IF YOU
DO NOT DOWNLOAD AND INCORPORATE THE LATEST VERSION OF THE FIRMWARE INTO THE DEVICE,
THEN THE DEVICE IS PROVIDED “AS IS” AND TI MAKES NO WARRANTY OR REPRESENTATION
WHATSOEVER IN RESPECT OF SUCH DEVICE, AND DISCLAIMS ANY AND ALL WARRANTIES AND
REPRESENTATIONS WITH RESPECT TO SUCH DEVICE. FURTHER, IF YOU DO NOT DOWNLOAD AND
INCORPORATE THE LATEST VERSION OF THE FIRMWARE INTO THE DEVICE, TI WILL NOT BE LIABLE
FOR AND SPECIFICALLY DISCLAIMS ANY DAMAGES, INCLUDING DIRECT DAMAGES, HOWEVER
CAUSED, WHETHER ARISING UNDER CONTRACT, TORT, NEGLIGENCE, OR OTHER THEORY OF
LIABILITY RELATING TO THE DEVICE, EVEN IF TI IS ADVISED OF THE POSSIBILITY OF SUCH
DAMAGES.
12.2 Documentation Support
12.2.1 Related Documentation
• TUSB1064 USB TYPE-C™ DP Alt Mode 10 Gbps Sink-Side Linear Redriver Crosspoint Switch data sheet
12.3 支持资源
TI E2E™ 支持论坛是工程师的重要参考资料，可直接从专家获得快速、经过验证的解答和设计帮助。搜索现有解
答或提出自己的问题可获得所需的快速设计帮助。
链接的内容由各个贡献者“按原样”提供。这些内容并不构成 TI 技术规范，并且不一定反映 TI 的观点；请参阅
TI 的《使用条款》。
12.4 Trademarks
TI E2E™ is a trademark of Texas Instruments.
USB Type-C® is a registered trademark of USB Implementers Forum.
所有商标均为其各自所有者的财产。
12.5 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled
with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may
be more susceptible to damage because very small parametric changes could cause the device not to meet its published
specifications.
12.6 术语表
TI 术语表
本术语表列出并解释了术语、首字母缩略词和定义。
13 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
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重要声明和免责声明
TI 提供技术和可靠性数据（包括数据表）、设计资源（包括参考设计）、应用或其他设计建议、网络工具、安全信息和其他资源，不保证没
有瑕疵且不做出任何明示或暗示的担保，包括但不限于对适销性、某特定用途方面的适用性或不侵犯任何第三方知识产权的暗示担保。
这些资源可供使用TI 产品进行设计的熟练开发人员使用。您将自行承担以下全部责任：(1) 针对您的应用选择合适的TI 产品，(2) 设计、验
证并测试您的应用，(3) 确保您的应用满足相应标准以及任何其他安全、安保或其他要求。这些资源如有变更，恕不另行通知。TI 授权您仅可
将这些资源用于研发本资源所述的TI 产品的应用。严禁对这些资源进行其他复制或展示。您无权使用任何其他TI 知识产权或任何第三方知
识产权。您应全额赔偿因在这些资源的使用中对TI 及其代表造成的任何索赔、损害、成本、损失和债务，TI 对此概不负责。
TI 提供的产品受TI 的销售条款(https:www.ti.com/legal/termsofsale.html) 或ti.com 上其他适用条款/TI 产品随附的其他适用条款的约束。TI
提供这些资源并不会扩展或以其他方式更改TI 针对TI 产品发布的适用的担保或担保免责声明。重要声明
邮寄地址：Texas Instruments, Post Office Box 655303, Dallas, Texas 75265
Copyright © 2021，德州仪器(TI) 公司
PACKAGE OPTION ADDENDUM
www.ti.com
26-Mar-2021
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
TPS65988DKRSHR
ACTIVE
VQFN
RSH
56
2500 RoHS & Green
NIPDAUAG
Level-3-260C-168 HR
-10 to 75
T65988
DK
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
PACKAGE OUTLINE
RSH0056E
VQFN - 1 mm max height
S
C
A
L
E
2
.
0
0
0
PLASTIC QUAD FLATPACK - NO LEAD
A
7.15
6.85
B
PIN 1 INDEX AREA
7.15
6.85
C
1 MAX
SEATING PLANE
0.08 C
0.05
0.00
3.4 0.1
1.75 0.1
PKG
(0.2)
15
28
52X 0.4
14
29
2.55 0.1
5.5 0.1
58
57
4X
5.2
SYMM
59
2.6 0.1
1
42
0.25
0.15
0.1
56X
PIN 1 ID
43
56
C A B
C
0.6
0.4
56X
(0.2) TYP
0.05
(0.35)
TYP
4223928/B 09/2018
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. The package thermal pad must be soldered to the printed circuit board for thermal and mechanical performance.
www.ti.com
EXAMPLE BOARD LAYOUT
RSH0056E
VQFN - 1 mm max height
PLASTIC QUAD FLATPACK - NO LEAD
3X 0.05 MAX
ALL AROUND
(3.4)
(0.65)
2X
48X (0.2)
(1.75)
PKG
48X (0.7)
SEE SOLDER MASK
OPTIONS
4X (0.7)
56
43
(0.2) TYP
1
42
8X (0.2)
1.18
(2.6)
(1.45)
1.32 TYP
SYMM
52X (0.4)
57
58
59
(6.7)
(5.5)
(1.475)
(0.875) TYP
4X SOLDER MASK
DEFINED PAD
(2.55)
29
14
PADS 57,58 & 59
NON SOLDER MASK
DEFINED
(
0.2) TYP
28
15
3X
(0.15)
VIA
3X
(1.2)
(0.475) TYP
SOLDER MASK
OPENING
(1.875)
5X (1.05)
(6.7)
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE: 10X
0.05 MAX
ALL AROUND
0.05 MIN
ALL AROUND
METAL
METAL UNDER
SOLDER MASK
EXPOSED
METAL
EXPOSED
METAL
SOLDER MASK
OPENING
SOLDER MASK
OPENING
NON SOLDER MASK
DEFINED
SOLDER MASK
DEFINED
SOLDER MASK OPTIONS
NOT TO SCALE
4223928/A 09/2018
NOTES: (continued)
4. This package is designed to be soldered to a thermal pad on the board. For more information, refer to QFN/SON PCB application note
in literature No. SLUA271 (www.ti.com/lit/slua271).
5. Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to their locations shown
on this view. It is recommended that vias under paste be filled, plugged or tented.
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EXAMPLE STENCIL DESIGN
RSH0056E
VQFN - 1 mm max height
PLASTIC QUAD FLATPACK - NO LEAD
PKG
4X (0.7)
4X
(1.67)
TYP
(1.47)
48X (0.2)
(0.2) TYP
(0.215)
TYP
48X (0.7)
56
43
8X (0.2)
4X (1.15)
1
42
52X (0.4)
(1.32)
TYP
(1.35)
(0.775)
57
58
(0.66) TYP
59
SYMM
(6.7)
(0.8)
(1.35)
8X (1.12)
29
14
METAL UNDER
SOLDER MASK
TYP
28
15
METAL
TYP
SOLDER MASK
OPENING
TYP
(1.875)
8X (1.47)
(6.7)
SOLDER PASTE EXAMPLE
BASED ON 0.1 MM THICK STENCIL
EXPOSED PAD PRINTED SOLDER COVERAGE BY AREA
PAD 57 & 58: 75%
PAD 59: 70%
SCALE: 12X
4223928/B 09/2018
NOTES: (continued)
6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
www.ti.com
重要声明和免责声明
TI“按原样”提供技术和可靠性数据（包括数据表）、设计资源（包括参考设计）、应用或其他设计建议、网络工具、安全信息和其他资源，
不保证没有瑕疵且不做出任何明示或暗示的担保，包括但不限于对适销性、某特定用途方面的适用性或不侵犯任何第三方知识产权的暗示担
保。
这些资源可供使用 TI 产品进行设计的熟练开发人员使用。您将自行承担以下全部责任：(1) 针对您的应用选择合适的 TI 产品，(2) 设计、验
证并测试您的应用，(3) 确保您的应用满足相应标准以及任何其他功能安全、信息安全、监管或其他要求。
这些资源如有变更，恕不另行通知。TI 授权您仅可将这些资源用于研发本资源所述的 TI 产品的应用。严禁对这些资源进行其他复制或展示。
您无权使用任何其他 TI 知识产权或任何第三方知识产权。您应全额赔偿因在这些资源的使用中对 TI 及其代表造成的任何索赔、损害、成
本、损失和债务，TI 对此概不负责。
TI 提供的产品受 TI 的销售条款或 ti.com 上其他适用条款/TI 产品随附的其他适用条款的约束。TI 提供这些资源并不会扩展或以其他方式更改
TI 针对 TI 产品发布的适用的担保或担保免责声明。
TI 反对并拒绝您可能提出的任何其他或不同的条款。IMPORTANT NOTICE
邮寄地址：Texas Instruments, Post Office Box 655303, Dallas, Texas 75265
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