TPS65980 [TI]
Thunderbolt™ 总线电源管理 IC (PMIC);型号: | TPS65980 |
厂家: | TEXAS INSTRUMENTS |
描述: | Thunderbolt™ 总线电源管理 IC (PMIC) 集成电源管理电路 |
文件: | 总30页 (文件大小:1056K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
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TPS65980
ZHCSCE0A –APRIL 2014–REVISED APRIL 2014
TPS65980 Thunderbolt™ 总线电源降压/升压
1 特性
3 说明
1
•
•
•
•
•
由 Thunderbolt™ 总线供电
TPS65980 是一款直流/直流开关稳压器,此稳压器由
电压范围介于 2.5V 至 15.75V 之间的 Thunderbolt™
或 Thunderbolt™ 2 电源总线供电,并且生成 3 个独立
3.3V 电源输出。
2.5V 至 15.75V 输入
3.3V 输出
电缆电源输出电流限制
热关断
TBT_OUT 电源为本地外设 Thunderbolt™ 控制器和支
持电路供电。 CBL_OUT 电源将电能输送回
Thunderbolt™ 电缆,并且具有可调电流限值。
DEV_OUT 电源为器件中的所有其他电路供电来执行
其设计的功能。
2 应用范围
•
•
•
Thunderbolt™/Thunderbolt™ 2 系统
总线供电系统
电源管理系统
TPS65980 采用 24 引脚
5mm x 4mm x 0.9mm 超薄四方平面无引线 (VQFN)
封装。
器件信息(1)
器件名称
TPS65980
封装
封装尺寸
5mm x 4mm
VQFN (24)
(1) 要了解所有可用封装,请见数据表末尾的可订购产品附录。
4 简化电路原理图
DEV_OUT
CDEV_OUT
L
CP
TBT_OUT
TBT_OUT
SW
CBOOT
BOOT
TBT_IN
TBT_IN
COMP
TBT_OUT
CTBT_OUT
GND
TBT_IN
Thunderbolt
DEV_EN
CTBT_IN
Controller
TBT
Connector
CBL_ILIMIT
RC
CC
CSS
CCBL_OUT
CBL_OUT
1
PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not necessarily include testing of all parameters.
English Data Sheet: SLVSCK1
TPS65980
ZHCSCE0A –APRIL 2014–REVISED APRIL 2014
www.ti.com.cn
目录
8.1 Overview ................................................................. 12
8.2 Functional Block Diagram ....................................... 13
8.3 Feature Description................................................. 14
8.4 Device Functional Modes........................................ 14
Application and Implementation ........................ 15
9.1 Application Information............................................ 15
9.2 Typical Application ................................................. 15
1
2
3
4
5
6
7
特性.......................................................................... 1
应用范围................................................................... 1
说明.......................................................................... 1
简化电路原理图........................................................ 1
修订历史记录 ........................................................... 2
Pin Configuration and Functions......................... 3
Specifications......................................................... 4
7.1 Absolute Maximum Ratings ...................................... 4
7.2 Handling Ratings....................................................... 4
7.3 Recommended Operating Conditions....................... 5
7.4 Thermal Information.................................................. 5
7.5 Electrical Characteristics........................................... 6
7.6 Timing Requirements................................................ 7
7.7 Timing Diagrams....................................................... 8
7.8 Typical Characteristics............................................ 10
Detailed Description ............................................ 12
9
10 Power Supply Recommendations ..................... 20
11 Layout................................................................... 20
11.1 Layout Guidelines ................................................. 20
11.2 Layout Example .................................................... 20
12 器件和文档支持 ..................................................... 22
12.1 Trademarks........................................................... 22
12.2 Electrostatic Discharge Caution............................ 22
12.3 Glossary................................................................ 22
13 机械封装和可订购信息 .......................................... 22
8
5 修订历史记录
Changes from Original (April 2014) to Revision A
Page
•
已将文档修改为完整版。 ....................................................................................................................................................... 1
2
Copyright © 2014, Texas Instruments Incorporated
TPS65980
www.ti.com.cn
ZHCSCE0A –APRIL 2014–REVISED APRIL 2014
6 Pin Configuration and Functions
VQFN (RHF) 24-Pin
TOP VIEW
VQFN (RHF) 24-Pin
BOTTOM
19
18
17
16
15
14
13
1
2
3
4
5
6
7
TBT_OUT
TBT_OUT
SW
BOOT
CBL_ILIMIT
COMP
TBT_IN
TBT_IN
DEV_EN
GND
Exposed Pad
(Connect to GND)
TBT_IN
TBT_IN
Exposed Pad
(Connect to GND)
GND
DEV_EN
CBL_ILIMIT
TBT_OUT
TBT_OUT
BOOT
SW
COMP
1
2
3
4
5
6
7
19
18
17
16
15
14
13
Pin Functions
PIN
I/O
DESCRIPTION
NO.
NAME
1
SS
ANALOG
Soft Start Capacitance. This pin sets the soft start ramp rate when the TBT_IN voltage ramps from
0V to high voltage.
2, 3, 4
5
GND
GND
Device Ground
HV_OK
OUTPUT
High Voltage Present Indicator. This pin indicates that a high voltage is present on TBT_IN. The
output asserts high when the TBT_IN pin is above the VHVT voltage and the RESET output is
asserting high.
6
7
RESET
OUTPUT
Reset output indicator. This pin asserts low when TBT_OUT is in under-voltage.
CBL_OUT
PWROUT Current Limited Power Output to Thunderbolt™ Cable. This pin supplies power to the Thunderbolt™
cable. The current limit of this pin is set by the CBL_ILIMIT pin.
8
9
CBL_ILIMIT INPUT
Current Limit Set. Logic input that sets the current limit state on the CBL_OUT pin. Tie pin to
TBT_OUT for a logic high input.
DEV_EN
INPUT
Device Enable Input. When input pin is high, DEV_OUT is high impedance. When input pin low,
DEV_OUT is connected to TBT_OUT.
10
GND
ANALOG
Device Ground
11, 12
13, 14
TBT_OUT
DEV_OUT
PWROUT Power Output to Thunderbolt™ circuitry. This pin supplies power to the Thunderbolt™ controller.
PWROUT Power Output to peripheral device. This pin supplies power to circuitry not associated with the
Thunderbolt™ controller or the Thunderbolt™ cable. It is intended to supply power to the peripheral
device main function.
15
16
CPP
ANALOG
ANALOG
GND
Charge Pump Capacitance Positive Output
CPN
Charge Pump Capacitance Negative Output
17, 18
19, 20
21
PGND
SW
Buck Controller Power Ground
ANALOG
ANALOG
PWRIN
Buck Controller Switch Output
BOOT
TBT_IN
COMP
Buck Controller Bootstrap
22, 23
24
Power Input from Thunderbolt™ Cable. This pin is the power supply to the device.
Buck Converter Compensation. This pin provides compensation to the buck converter feedback loop.
ANALOG
Copyright © 2014, Texas Instruments Incorporated
3
TPS65980
ZHCSCE0A –APRIL 2014–REVISED APRIL 2014
www.ti.com.cn
7 Specifications
7.1 Absolute Maximum Ratings
over operating free-air temperature (unless otherwise noted)(1)
MIN
–0.3
–0.3
–0.3
–0.3
–0.3
–0.6
–2
MAX
UNIT
TBT_IN
18
3.6
25
DEV_EN
BOOT
BOOT (10 ns transient)
BOOT (vs SW)
27
7
SW
Input voltage range(2)
18
V
SW (10 ns transient)
20
COMP
SS
–0.3
–0.3
–0.3
–0.3
–0.3
–0.3
–0.3
–0.2
–0.2
–40
3.6
3.6
3.6
7.2
3.6
3.6
3.6
0.2
0.2
85
CBL_ILIMIT
CPP
CPN
TBT_OUT, CBL_OUT, DEV_OUT
Output voltage range(2)
V
RESET, HV_OK
Vdiff
Voltage from GND to Thermal Pad
Voltage from PGND to GND
V
V
TA
TJ
Operating ambient temperature
Operating junction temperature
°C
°C
–40
125
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) All voltage values are with respect to network ground pin.
7.2 Handling Ratings
MIN
–55
MAX
150
UNIT
Tstg
Storage temperature range
°C
Human body model (HBM), per ANSI/ESDA/JEDEC JS-001, all
pins(1)
0
0
2
kV
V
V(ESD)
Electrostatic discharge
Charged device model (CDM), per JEDEC specification
JESD22-C101, all pins(2)
500
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
4
Copyright © 2014, Texas Instruments Incorporated
TPS65980
www.ti.com.cn
ZHCSCE0A –APRIL 2014–REVISED APRIL 2014
7.3 Recommended Operating Conditions
over operating free-air temperature (unless otherwise noted)
MIN
2.5
MAX UNIT
TBT_IN
Supply input voltage range
15.75
3.6
DEV_EN
BOOT
SW
–0.1
–0.1
–0.6
–0.1
–0.1
–0.1
–0.1
–0.1
–0.1
–0.1
–40
25
16.5
COMP
3.6
3.6
3.6
7.2
3.6
3.6
3.6
85
V
Input voltage
range
VI
SS
CBL_ILIMIT
CPP
CPN
TBT_OUT, CBL_OUT, DEV_OUT
RESET, HV_OK
Output voltage
range
VO
V
TA
TJ
Operating free-air temperature
Operating junction temperature
°C
°C
–40
125
7.4 Thermal Information
TPS65980
THERMAL METRIC(1)
RHF
24 PIN
30.1
26.9
8.2
UNIT
RθJA
Junction-to-ambient thermal resistance
RθJC(top)
RθJB
Junction-to-case (top) thermal resistance
Junction-to-board thermal resistance
°C/W
ψJT
Junction-to-top characterization parameter
Junction-to-board characterization parameter
Junction-to-case (bottom) thermal resistance
0.3
ψJB
8.2
RθJC(bot)
1.5
(1) For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.
Copyright © 2014, Texas Instruments Incorporated
5
TPS65980
ZHCSCE0A –APRIL 2014–REVISED APRIL 2014
www.ti.com.cn
7.5 Electrical Characteristics
Unless otherwise noted all specifications applies over the VTBT_IN range and operating ambient temperature of
–40°C ≤ TA ≤ 85°C, CTBT_IN = 22 µF, CTBT_OUT = 10 µF, CCBL_OUT = 1 µF, CSS = 10 nF, and 33 V/µs logic input transitions.
Typical values are for VTBT_IN = 12 V and TA = 25°C.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
POWER SUPPLIES AND CURRENTS
VTBT_IN
TBT_IN Input voltage range
2.5
3
12
3.1
2.6
4.5
100
15.75
3.2
V
V
TBT_OUT to RESET clear high
TBT_OUT to RESET assert low
TBT_IN to HV_OK assert
TBT_IN to HV_OK clear
TBT_IN Input slew rate
TBT_OUT rising
VREF_RSTN
TBT_OUT falling
2.5
4.36
2.7
VHVTR
VHVTHYST
SR02L
TBT_IN rising
4.64
V
TBT_IN Falling hysteresis
TBT_IN transition from 0 V to 3.3 V
TBT_IN transition from 3.3 V to 15 V
mV
0.1
0.1
30
30
5
kV/s
kV/s
kA/s
SRL2H
IRAMP
TBT_IN Input slew rate
Combined output di/dt(1)
Buck converter efficiency
Charge pump efficiency
ILOADTOTAL = 3 A, VTBT_IN = 12 V
87%
47%
Efficiency
VTBT_IN = 3.3 V, ILOADTOTAL = 25 mA
POWER OUTPUT PINS (LOW VOLTAGE INPUT)(2)
VTBT_IN
TBT_IN Input voltage range
TBT_OUT Output voltage range(3)
2.5
3.135
5
3.3
3.4
3.4
50
V
V
VTBT_OUT
3.25
RESET high
RESET low
mA
µA
ITBT_OUT
TBT_OUT Load current(4)(5)
100
POWER OUTPUT PINS (HIGH VOLTAGE INPUT)(6)
VTBT_IN
TBT_IN Input voltage range
10
3.221
3.221
235
12
3.27
3.27
15.75
3.319
3.42
V
V
I_LOADTOTAL = 1 A to 3.5 A
VTBT_OUT
ITBT_OUT
VCBL_OUT
VDEV_OUT
TBT_OUT Output voltage range(3)
TBT_OUT Load current(4)
I_LOADTOTAL = 0.235 A to 3.5 A
1000
3.319
3.319
3.319
mA
V
ILIMIT = 0, ICBL_OUT = 0 to 720 mA
ILIMIT = 1, ICBL_OUT = 0 to 1.44 A
IDEV_OUT = 0 to 2500 mA
3.171
3.12
3
3.27
3.27
3.27
CBL_OUT Output voltage range(3)
DEV_OUT Output Voltage Range
V
POWER OUTPUT PINS (HIGH VOLTAGE INPUT DURING SYSTEM SLEEP)
VTBT_IN
TBT_IN Input voltage range
5.2
3.221
3.221
5
12
3.27
3.27
15.75
3.319
3.42
V
V
I_LOADTOTAL = 1 A to 3.5 A
VTBT_OUT
TBT_OUT DC Output voltage range
I_LOADTOTAL = 0.235 A to 3.5 A
ITBT_OUT
VCBL_OUT
VDEV_OUT
TBT_OUT Load current
CBL_OUT Output voltage range(3)
31
mA
V
ICBL_OUT = 0 to 235 mA
IDEV_OUT = 0 to 700 mA
3.171
3
3.27
3.3
3.319
3.319
DEV_OUT Output voltage range
V
CABLE OUTPUT (HIGH VOLTAGE INPUT & HIGH VOLTAGE INPUT DURING SLEEP)
VCBL_OUT_MON
CBL_OUT Ramp-up monotonicity(7)
CBL_OUT ramp from off to on
0
2
mV
After settling
All output combined Load > 1 mA
%
P-P
VCBL_OUT_RIP
CBL_OUT Voltage ripple
All output combined Load < 1 mA
ILIMIT = 0
40 mVP=P
0.8
1.6
1.1
2.2
1.4
A
2.8
ILIM_CBLOUT
CBL_OUT Current limit
ILIMIT = 1
RCBL_OUT = 0.5 Ω to GND, ILIMIT = 0
RCBL_OUT = 0.01 Ω to GND, ILIMIT = 0
500
µs
8
tLIM_CBLOUT
Short circuit response time
(1) The three voltage outputs (TBT_OUT, CBL_OUT, DEV_OUT) all pull current from a single node. Therefore, the total combined current
cannot exceed the maximum di/dt.
(2) CBL_OUT and DEV_OUT are open (high impedance) for this input voltage range.
(3) During light load conditions, the average output voltage may reach 3.5 V with peaks not exceeding 3.42 V.
(4) TBT_OUT load current flows from the TBT_OUT pin when the device is in charge pump mode and pulls the buck converter inductor
when the device is in buck mode.
(5) TBT_OUT load current will not go higher than 50mA until after the device asserts HV_OK.
(6) The maximum current supplied by the TPS65980 to all outputs is limited to 3.5 A. Max power depends on the Thunderbolt™ system and
how much power is supplied to the input.
(7) A monotonicity of 0 mV means that the output does not have a negative going ramp at anytime during its power up ramp. A ripple of up
to 62 mV from the DC/DC will occur.
6
Copyright © 2014, Texas Instruments Incorporated
TPS65980
www.ti.com.cn
ZHCSCE0A –APRIL 2014–REVISED APRIL 2014
Electrical Characteristics (continued)
Unless otherwise noted all specifications applies over the VTBT_IN range and operating ambient temperature of
–40°C ≤ TA ≤ 85°C, CTBT_IN = 22 µF, CTBT_OUT = 10 µF, CCBL_OUT = 1 µF, CSS = 10 nF, and 33 V/µs logic input transitions.
Typical values are for VTBT_IN = 12 V and TA = 25°C.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
DEV_EN AND ILIMIT INPUT LOGIC
VIH
VIL
IIN
High-level input voltage
Low-level input voltage
Input leakage to GND
2.6
V
V
0.6
1
VDEV_EN = 3.3V
mA
RESET AND HV_OK OUTPUT LOGIC
VOH
High-level output voltage
Low-level output voltage
IL = –1.5 mA, Referenced to VTBT_OUT
IL = 1.5 mA
–250
0
0
mV
mV
VOL
250
SOFT START(8)
IINRUSH
Inrush current di/dt
250
150
kA/s
THERMAL SHUTDOWN
TSD
Shutdown temperature
Shutdown hysteresis
120
135
10
°C
°C
TSDHYST
(8) The charge pump will limit the normal ramp of current. Soft start will control the inrush current when the input ramps from 0 V to high
voltage (not a normal operating condition). See recommended components section for required soft-start cap.
7.6 Timing Requirements
MIN
TYP
MAX UNIT
V
V
TBT_IN ≥ 0.9 × VTBT_IN(min) to
TBT_OUT ≥ 0.99 × VTBT_OUT(min)
tIN2OR
TBT_IN to TBT_OUT On Time
TBT_IN to TBT_OUT Off Time
20
4
ms
ms
RTBT_OUT = 100 Ω
VTBT_IN ≤ 0.9 × VTBT_IN(min) to
TBT_OUT ≤ 0.1 × VTBT_OUT(min)
tIN2OF
V
2.4
RTBT_OUT = 100 Ω
TBT_OUT ≥ VREF_RSTN(max) rising to
VRESET = 0.9 × VOH, CRESETN = 100 pF
TBT_IN ≤ 0.9 × VTBT_IN(min) to
VRESET = 0.1 × VOH, CRESETN = 100 pF
TBT_IN ≥ VHVTR to VHV_OK = 0.9 × VOH
CHV_OK = 100 pF
TBT_IN ≤ VHVTR-VHVTHYST to
VHV_OK = 0.1 × VOH, CHV_OK = 100 pF
HV_OK ≥ 1.65 V to VCBL_OUT = 2.95 V
RCB_OUT = 100 Ω, CHV_OK = 100 pF
HV_OK ≤ 1.65 V to VCBL_OUT = 2.95 V
V
tOUT2RR
tIN2RF
tHV2OKR
tHV2OKF
TBT_OUT to RESETZ High time
TBT_IN to RESETZ Low time
TBT_IN Rise to HV_OK
20
20
10
10
10
40
10
10
50
µs
ms
µs
V
V
V
TBT_IN Fall to HV_OK
µs
V
(1)(2)
tHV2CR
tHV2CF
HV_OK to CBL_OUT On time
HV_OK to CBL_OUT Off time
CABLE_OUT Ramp time
0.1
ms
µs
V
RCB_OUT = 100 Ω, CHV_OK = 100 pF
VCBL_OUT ramp 10% to 90%
CCBL_OUT = 0 to 52 µF
tRCBL
0.1
0.1
ms
ms
ms
ms
VDEV_EN ≤ 1.65 V to VDEV_OUT = 2.7 V
RDEV_OUT = 100 Ω
tDEVEN
tDEVDIS
tHV2DEVEN
DEV_EN to DEV_OUT On time
DEV_EN to DEV_OUT Off time
VDEV_EN ≥ 1.65V to VDEV_OUT = 2.7 V
RDEV_OUT = 100 Ω
VHV_OK ≥ 1.65 V to VDEV_EN ≤ 1.65 V
Wait time from HV_OK High before
DEV_EN can be asserted low(2)
2
CHV_OK = 100 pF
(1) TBT_IN must transition from 3.3 V to high voltage, not from 0 V to high voltage
(2) During the transition from low voltage input to high voltage input, the total load of all outputs combined can not exceed 85 mA until 2 ms
after HV_OK asserts high.
Copyright © 2014, Texas Instruments Incorporated
7
TPS65980
ZHCSCE0A –APRIL 2014–REVISED APRIL 2014
www.ti.com.cn
7.7 Timing Diagrams
15.75V
10V
SRL2H
3.4V
2.5V
TBT_IN
0V
SR02L
Figure 1. TBT_IN Slew Rates
The TPS65980 has two normal operating regions. The first region is when 2.5 V ≤ VTBT_IN ≤ 3.4 V. This is the
normal power-up state and is termed the low-voltage state. When the input transitions to this range, the input
slew rate must meet the SR02L limits. In this voltage range, the TPS65980 operates with a charge pump to
generate the nominally 3.3 V output. When the input voltage moves to the higher end of this range, the buck
converter takes over to produce the 3.3 V. In normal operation, the TPS65980 input voltage will transition from
the low-voltage range to a high-voltage range where 10 V ≤ VTBT_IN ≤ 15.75 V. This is the high-voltage state and
is the state where the TPS65980 will operate most of the time. In this state, the device operates as a buck
converter providing a nominally 3.3 V output. Figure 1 shows the input voltage transitions and states.
VHVTR - VHVTHYST
VHVTR
0.9·VTBT_IN(min)
TBT_IN
TBT_OUT
RESET
0.9·VTBT_IN(min)
0V
0V
0V
0V
tIN2OR
0.99·VTBT_OUT(Min)
0.1·VTBT_OUT(Min)
VREF_RSTN
tIN2OF
tOUT2RR
0.9·VOH
0.1·VOH
tIN2RF
tHV2OKF
tHV2OKR
HV_OK
0.9·VOH
0.1·VOH
Figure 2. Timing Diagram
Figure 2 shows normal operating timing diagram for the TBT_OUT output voltage and the RESET and HV_OK
output indicator signals. When TBT_IN transitions to the low-voltage range, TBT_OUT will power up a short time
later. Once TBT_OUT reaches the normal output range, RESET will transition high. However, timing for RESET
is measured from the input TBT_IN transitioning high. When TBT_IN transitions from the low-voltage input range
to the high-voltage input range, HV_OK will transition high. RESET is an active-high output indicating that the
TBT_OUT voltage is valid and. HV_OK is an active-high output indicating that the TBT_IN voltage is in the high-
voltage range. When in the high-voltage state, the TPS65980 can provide much higher output current than when
in the low-voltage state.
8
Copyright © 2014, Texas Instruments Incorporated
TPS65980
www.ti.com.cn
ZHCSCE0A –APRIL 2014–REVISED APRIL 2014
Timing Diagrams (continued)
When the TBT_IN input transitions from high-voltage to low-voltage, HV_OK will de-assert to a logic low. When
the TBT_IN input voltage falls below the minimum operating voltage, the RESET output will de-assert low.
HV_OK
1.65V
1.65V
1.65V
0V
DEV_EN
0V
0V
0V
tHV2CR
tHV2CF
tHV2CR
0.95·VCBL_OUT(Min)
0.95·VCBL_OUT(Min)
0.95·VCBL_OUT(Min)
CBL_OUT
DEV_OUT
tDEVEN
tDEVDIS
0.95·VDEV_OUT(Min)
0.95·VDEV_OUT(Min)
0.95·VDEV_OUT(Min)
0.95·VDEV_OUT(Min)
Figure 3. Timing Diagram
Figure 3 shows the CBL_OUT and DEV_OUT outputs and timing based on the HV_OK signal and the DEV_ENZ
input. The CBL_OUT output will be connected to TBT_OUT and supplying 3.3V when HV_OK is asserting high.
The DEV_OUT output will be connected to TBT_OUT and supplying 3.3 V when HV_OK is asserting high and
the DEV_ENZ input is low.
Copyright © 2014, Texas Instruments Incorporated
9
TPS65980
ZHCSCE0A –APRIL 2014–REVISED APRIL 2014
www.ti.com.cn
7.8 Typical Characteristics
100
90
80
70
60
50
40
30
20
10
0
100
90
80
70
60
50
40
30
20
10
0
Vin = 5.2V
Vin = 8.2V
Vin = 11.2V
Vin = 14.2V
Vin = 15.75V
Vin = 2.5V
Vin = 2.8V
Vin = 3.1V
Vin = 3.3V
0
0
0
0.0075 0.015 0.0225
0.03
0.0375 0.045
0
0.2
0.4
0.6
0.8
1
1.2
1.4
1.6
1.8
IO - Output Current - A
ITBT_OUT - A
D001
D002
Figure 4. Low Voltage Efficiency
Figure 5. High Voltage Efficiency (System Sleep)
100
90
80
70
60
50
40
30
20
10
0
3.27
3.268
3.266
3.264
3.262
3.26
3.258
3.256
3.254
3.252
3.25
Vin = 10V
Vin = 12V
Vin = 14V
Vin = 15.75V
0.4 0.8 1.2 1.6
2
2.4 2.8 3.2 3.6
4
0
5
10
15
20
25
30
35
40
45
50
ITBT_OUT - A
ITBT_OUT - mA
D003
D004
VIN = 3.3V
Figure 6. High Voltage Efficiency (Active)
Figure 7. TBT_OUT Load Regulation
3.36
3.34
3.32
3.3
3.4
3.35
3.3
3.28
3.26
3.24
3.22
3.2
3.25
3.2
3.15
3.1
0.4
0.8
1.2
1.6
2
2.4
2.8
3.2
3.6
0
0.3
0.6
0.9
1.2
1.5
1.8
2.1
2.4
2.7
ITBT_OUT - A
IDEV_OUT - A
D005
D006
VIN = 12V
VIN = 12V
Figure 8. TBT_OUT Load Regulation
Figure 9. DEV_OUT Load Regulation
10
Copyright © 2014, Texas Instruments Incorporated
TPS65980
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ZHCSCE0A –APRIL 2014–REVISED APRIL 2014
Typical Characteristics (continued)
4
4
3.5
3
3.5
3
2.5
2
2.5
2
1.5
1
0.5
0
1.5
1
-0.5
-1
0.5
0
-1.5
-2
-0.2
0.2
0.6
1
1.4
1.8
2.2
2.6
0
0.2
0.4
0.6
0.8
1
1.2
1.4
ICBL_OUT - A
ICBL_OUT - A
D007
D008
VIN = 12V
CBL_ILIMIT = 1
VIN = 12V
CBL_ILIMIT = 0
Figure 10. CBL_OUT Load Regulation
Figure 11. CBL_OUT Load Regulation
3.36
500mA
1A
2A
3A
3.5A
3.34
3.32
3.3
3.28
3.26
3.24
3.22
3.2
5
6
7
8
9
10 11 12 13 14 15 16
VTBT_IN - V
D009
Figure 12. TBT_OUT Line Regulation
Copyright © 2014, Texas Instruments Incorporated
11
TPS65980
ZHCSCE0A –APRIL 2014–REVISED APRIL 2014
www.ti.com.cn
8 Detailed Description
8.1 Overview
The TPS65980 is a switching regulator designed for Thunderbolt™ and Thunderbolt™ 2 bus-powered systems.
The TPS65980 receives power from a Thunderbolt™ host in the range of 2.5 V to 15.75 V and produces three
separate 3.3 V outputs. TBT_OUT is the main output from the regulator. This output is generated from a
switched-cap charge pump when the input is in the low-voltage range. The output is generated from a switching
buck converter when the input voltage is in the high-voltage range. The TBT_OUT output powers the local
Thunderbolt™ controller and any additional Thunderbolt™ circuitry. Once in the input has settled in the high-
voltage range, the other two outputs can be powered from the TBT_OUT output. When the TBT_OUT is
supplying 3.3 V, the RESET output asserts high. When the TBT_OUT voltage is below the valid output range,
RESET asserts low. When TBT_IN is in the high-voltage input range and RESET is asserting high (valid output),
HV_OK will assert high indicating that high-voltage has been received.
The CBL_OUT output supplies power back to the Thunderbolt™ cable for powering the active cable circuitry.
This output is connected to the TBT_OUT output with a FET switch and is current limited.
The CBL_ILIMIT logic input pin sets the current limit level. The DEV_OUT output provides power to all other
circuitry in the system. This output is not current limited and is enabled/disabled by the DEV_EN logic input.
12
Copyright © 2014, Texas Instruments Incorporated
TPS65980
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ZHCSCE0A –APRIL 2014–REVISED APRIL 2014
8.2 Functional Block Diagram
BOOT
TBT_IN
SS
MN1A
I-Sense
Switch-Mode
Control
MN1B
AERROR
SW
RFB1
COMP
RFB2
VREF
MN2
PGND
RESET
CPN
VREF
Charge
Pump
CPP
HV_OK
TBT_IN
4.5V
TBT_OUT
Gate
Driver
HV_OK
HV_OK
MN3
MN3
CBL_OUT
DEV_OUT
I-Limit
CBL_ILIMIT
DEV_EN
GND
Copyright © 2014, Texas Instruments Incorporated
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TPS65980
ZHCSCE0A –APRIL 2014–REVISED APRIL 2014
www.ti.com.cn
8.3 Feature Description
8.3.1 2.5-V to 15.75-V Input
The TPS65980 is powered from a Thunderbolt™ Bus. This is typically an input to a port from Thunderbolt™
cable. This input will start at 3.3 V (2.5 V ≤ VTBT_IN ≤ 3.4 V) until a link is established between a host and the
peripheral device containing the TPS65980. Once the link is established, the voltage at the input can transition to
a higher operating voltage (10 V ≤ VTBT_IN ≤ 15.75 V).
8.3.2 3.3-V Outputs
The TPS65980 has three separate 3.3 V outputs. One output, TBT_OUT, is the output from the buck/boost and
the other outputs, CBL_OUT and DEV_OUT, are outputs that through load switches from TBT_OUT.
The TBT_OUT supply provides power to the local peripheral Thunderbolt™ controller and support circuitry. The
CBL_OUT supply provides power back to the Thunderbolt™ cable and has adjustable current limit. The
DEV_OUT supply provides power to all other circuitry in the device to perform its designed function.
8.3.3 Thermal Shutdown
The TPS65980 as a thermal shutdown feature preventing the device from over heating during current limiting
situations. The thermal shutdown occurs at a 135°C junction temperature typically. A 10°C hysteresis occurs
before the thermal shutdown is cleared.
8.3.4 Cable Power Out Current Limit
The CBL_OUT output is current limited internally. The current limit has two values which are set by the
CBL_ILIMIT logic input. When CBL_ILIMIT = 0, the current limit will bet set to 1.1 A typically. When CBL_ILIMIT
= 1, the current limit will be set to 2.2 A typically.
8.4 Device Functional Modes
8.4.1 Operation with 2.5 V ≤ VTBT_IN ≤ 3.4 V
The TPS65980 has two normal operating regions. The first region is when 2.5 V ≤ VTBT_IN ≤ 3.4 V. This is the
normal power-up state and is termed the low-voltage state. When the input transitions to this range, the input
slew rate must meet the SR02L limits. In this voltage range, the TPS65980 operates with a charge pump to
generate the nominally 3.3 V output. When the input voltage moves to the higher end of this range, the buck
converter takes over to produce the 3.3 V.
8.4.2 Operation with 10 V ≤ VTBT_IN ≤ 15.75 V
In normal operation, the TPS65980 input voltage will transition from the low-voltage range to a high-voltage
range where 10 V ≤ VTBT_IN ≤ 15.75 V. This is the high-voltage state and is the state where the TPS65980 will
operate most of the time. In this state, the device operates as a buck converter providing a nominally 3.3 V
output.
14
Copyright © 2014, Texas Instruments Incorporated
TPS65980
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ZHCSCE0A –APRIL 2014–REVISED APRIL 2014
9 Application and Implementation
9.1 Application Information
The TPS65980 DC/DC switching regulator that receives power from a Thunderbolt™ or Thunderbolt™ 2 power
bus ranging from 2.5 V to 15.75 V and generates three separate 3.3-V supply outputs.
9.2 Typical Application
9.2.1 Single-Port Bus-Powered Thunderbolt™ Device
DEV_OUT
CDEV_OUT
L
CP
TBT_OUT
SW
TBT_OUT
TBT_OUT
GND
CBOOT
BOOT
TBT_IN
TBT_IN
COMP
CTBT_OUT
TBT_IN
Thunderbolt
Controller
DEV_EN
CBL_ILIMIT
CTBT_IN
TBT
Connector
RC
CC
CSS
CCBL_OUT
CBL_OUT
Figure 13. Typical Application (Single-Port Bus-Powered Thunderbolt™ Device)
9.2.1.1 Design Requirements
Table 1. Recommended Component Values
COMPONENT DESCRIPTION
MIN
TYP
22
10
1
MAX
52
UNIT
µF
nF
CIN
TBT_IN Input Capacitance
17.6
8
CBOOT
CCP
CSS
CTBT
CCBL
CDEV
CC
Converter Bootstrap Capacitance
12
Charge Pump Capacitance (ceramic with ESR ≤ 10 mΩ)
Soft Start Capacitance
0.8
8
1.2
12
µF
nF
10
20
1
TBT_OUT Output Capacitance (ceramic with ESR ≤ 10 mΩ)
CBL_OUT Output Capacitance (ceramic with ESR ≤ 10 mΩ)
DEV_OUT Output Capacitance (ceramic with ESR ≤ 10 mΩ)
Compensation Capacitance
16
0.8
0.8
8
24
µF
µF
µF
nF
1.2
1.2
12
1
10
10
10
RC
Compensation Resistance
8
12
kΩ
µH
L
Inductor SRR1280 (ESR ≤ 20 mΩ)
8
12
9.2.1.2 Detailed Design Procedure
The TPS65980 should use the recommended component values in Table 1. The device is designed to fit the
needs of a Thunderbolt™ bus powered peripheral and the recommended component values are chosen to
satisfy those conditions. The input capacitance CIN can be as high as 52 µF, but this maximum capacitance must
include all capacitances seen at the input to the Thunderbolt™ port.
Copyright © 2014, Texas Instruments Incorporated
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TPS65980
ZHCSCE0A –APRIL 2014–REVISED APRIL 2014
www.ti.com.cn
9.2.1.3 Application Performance Plots
CTBT_OUT = 10 µF
VTBT_IN = 12 V
CTBT_OUT = 10 µF
VTBT_IN = 12 V
Figure 14. TBT_OUT Load Transient Response
(0.5A to 3.5A Step)
Figure 15. TBT_OUT Load Transient Response
(3.5A to 0.5A Step)
Figure 16. 0V to 3.3V Power Up With 50mA Load
Figure 17. 3.3V to 0V Power Down With 50mA Load
Figure 18. 3.3V to 15.75V Vin Step With 50mA Load
Figure 19. 15.75 to 3.3V Vin Step With 50mA Load
16
Copyright © 2014, Texas Instruments Incorporated
TPS65980
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ZHCSCE0A –APRIL 2014–REVISED APRIL 2014
CBL_ILIMIT = 0
CBL_ILIMIT = 1
Figure 20. Short Circuit Current Limit Response
Figure 21. Short Circuit Current Limit Response
Copyright © 2014, Texas Instruments Incorporated
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TPS65980
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www.ti.com.cn
9.2.2 Dual-Port Bus-Powered Thunderbolt™ Device
DEV_OUT
CDEV
L
CP
TBT_OUT
SW
TBT_OUT
CBOOT
BOOT
I-Limit
TBT_OUT
GND
CTBT
TBT Port 1
Connector
TBT_IN
TBT_IN
Thunderbolt
Controller
I-Limit
TBT Port2
Connector
TBT_IN
COMP
DEV_EN
CBL_ILIMIT
RC
CC
CSS
CCBL
CBL_OUT
Figure 22. Typical Application (Dual-Port Bus-Powered Thunderbolt™ Device)
9.2.2.1 Design Requirements
In a dual-port application, the TBT_IN input voltage will be selected from either port. A simple diode-or function
will produce TBT_IN from the higher of the two inputs. The diode-or selection will allow the high-voltage supply to
be at TBT_IN.
In a dual port system, the TPS65980 must provide cable power to both ports. In this case, a second current
limiting device (TPS22920) connected between TBT_OUT and the port is recommended. The CBL_OUT pin can
also supply current to both ports. In this case, tying CBL_ILIMIT to TBT_OUT will double the amount of current
that can be supplied before current limiting. When using this method, the voltage drop to the CBL_OUT pin will
increase and care must be taken that other systems resistance do not cause the cable voltage to drop below the
allowed pin voltage specified in the Thunderbolt™ specification. To avoid issues with voltage drop in the system,
it is recommended that the second port be powered from TBT_OUT as shown in Figure 22. This relieves the
voltage drop due to extra current through the CBL_OUT load switch.
18
Copyright © 2014, Texas Instruments Incorporated
TPS65980
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ZHCSCE0A –APRIL 2014–REVISED APRIL 2014
Table 2. Recommended Component Values
COMPONENT DESCRIPTION
MIN
TYP
22
10
1
MAX
52
UNIT
µF
nF
CIN
TBT_IN Input Capacitance
17.6
8
CBOOT
CCP
CSS
CTBT
CCBL
CDEV
CC
Converter Bootstrap Capacitance
12
Charge Pump Capacitance (ceramic with ESR ≤ 10 mΩ)
Soft Start Capacitance
0.8
8
1.2
12
µF
nF
10
20
1
TBT_OUT Output Capacitance (ceramic with ESR ≤ 10 mΩ)
CBL_OUT Output Capacitance (ceramic with ESR ≤ 10 mΩ)
DEV_OUT Output Capacitance (ceramic with ESR ≤ 10 mΩ)
Compensation Capacitance
16
0.8
0.8
8
24
µF
µF
µF
nF
1.2
1.2
12
1
10
10
10
RC
Compensation Resistance
8
12
kΩ
µH
L
Inductor SRR1280 (ESR ≤ 20 mΩ)
8
12
9.2.2.2 Detailed Design Procedure
Refer to Detailed Design Procedure in the Single-Port Bus-Powered Thunderbolt™ Device section.
9.2.2.3 Application Performance Plots
Refer to Application Performance Plots in the Single-Port Bus-Powered Thunderbolt™ Device section.
Copyright © 2014, Texas Instruments Incorporated
19
TPS65980
ZHCSCE0A –APRIL 2014–REVISED APRIL 2014
www.ti.com.cn
10 Power Supply Recommendations
The TPS65980 is designed to operate from a Thunderbolt™ bus. The input will range from 2.5 V to 15.75 V. The
input should be placed as near to the port connector as possible.
11 Layout
11.1 Layout Guidelines
Proper placement and routing will maximize the performance of the TPS65980. Follow Figure 23 for optimized
layout and routing (hashed planes indicate bottom layer).
11.2 Layout Example
TBT_OUT Plan
DEV_OUT
Planes
SW
Plane
TBT_IN Plane
CBL_OUT Plane
GND Plane
Figure 23. Top View Board Layout
20
Copyright © 2014, Texas Instruments Incorporated
TPS65980
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ZHCSCE0A –APRIL 2014–REVISED APRIL 2014
Layout Example (continued)
For TBT_IN, the input capacitors must be placed close to the device with an inductance less than 1nH from input
capacitors to the TBT_IN pins. Layout tools and calculators are available to approximate the inductance. The
input capacitors must have their GND side area via stitched to the GND plane. The GND side of the input cap
should also share the same polygon as the PGND/PowerPad on the top layer. PowerPad should be connected to
the GND plane through multiple vias.
Inductor placement should be above the TPS65980, slightly to the left of the device. The SW pins to the inductor
must be connected though a plane as shown in Figure 23. The TBT_OUT pins also have to be connected to the
other side of the inductor with a plane. This plane should be wide to overlap the output capacitors. The GND side
of the output capacitors should be stitched to the GND plane.
The CBL_OUT output capacitor should be placed close to the device on the top layer with an inductance less
than 1 nH from the capacitor to the CBL_OUT pin. The DEV_OUT capacitor is best placed on the bottom side of
the board with two planes (top and bottom) connect through a set of vias. The number of vias placed should be
able to carry at least 3 A (DEV_OUT = 2.5 A max) for margin and inductance path less than 1nH from DEV_OUT
pins to capacitor. When routing DEV_OUT to an internal power plane, follow Figure 24 for via paths.
DEV_OUT Pins
TPS65980
Top
Power
Vias
GND
Bottom
(Indicates Current Flow)
DEV_OUT Cap
Figure 24. DEV_OUT Recommended Routing
The charge pump capacitor must be placed on the top layer close to the CPP and CPN pins. The inductance
paths from capacitor to the pins must be less than 1 nH. SS and Compensation components should be placed on
the top layer close to the device.
Copyright © 2014, Texas Instruments Incorporated
21
TPS65980
ZHCSCE0A –APRIL 2014–REVISED APRIL 2014
www.ti.com.cn
12 器件和文档支持
12.1 Trademarks
Thunderbolt is a trademark of Intel Corporation.
12.2 Electrostatic Discharge Caution
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
12.3 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms and definitions.
13 机械封装和可订购信息
以下页中包括机械封装和可订购信息。 这些信息是针对指定器件可提供的最新数据。 这些数据会在无通知且不对
本文档进行修订的情况下发生改变。 欲获得该数据表的浏览器版本,请查阅左侧的导航栏。
22
Copyright © 2014, Texas Instruments Incorporated
PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
TPS65980RHFR
TPS65980RHFT
ACTIVE
VQFN
VQFN
RHF
24
24
3000 RoHS & Green
250 RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
-40 to 85
-40 to 85
TPS
65980
ACTIVE
RHF
NIPDAU
TPS
65980
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
20-Apr-2023
TAPE AND REEL INFORMATION
REEL DIMENSIONS
TAPE DIMENSIONS
K0
P1
W
B0
Reel
Diameter
Cavity
A0
A0 Dimension designed to accommodate the component width
B0 Dimension designed to accommodate the component length
K0 Dimension designed to accommodate the component thickness
Overall width of the carrier tape
W
P1 Pitch between successive cavity centers
Reel Width (W1)
QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE
Sprocket Holes
Q1 Q2
Q3 Q4
Q1 Q2
Q3 Q4
User Direction of Feed
Pocket Quadrants
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
TPS65980RHFR
TPS65980RHFT
VQFN
VQFN
RHF
RHF
24
24
3000
250
330.0
180.0
12.4
12.4
4.3
4.3
5.3
5.3
1.3
1.3
8.0
8.0
12.0
12.0
Q1
Q1
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
20-Apr-2023
TAPE AND REEL BOX DIMENSIONS
Width (mm)
H
W
L
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SPQ
Length (mm) Width (mm) Height (mm)
TPS65980RHFR
TPS65980RHFT
VQFN
VQFN
RHF
RHF
24
24
3000
250
346.0
210.0
346.0
185.0
33.0
35.0
Pack Materials-Page 2
PACKAGE OUTLINE
RHF0024A
VQFN - 1 mm max height
S
C
A
L
E
3
.
0
0
0
PLASTIC QUAD FLATPACK - NO LEAD
4.1
3.9
A
B
PIN 1 INDEX AREA
0.5
0.3
5.1
4.9
0.30
0.18
DETAIL
OPTIONAL TERMINAL
TYPICAL
C
1 MAX
SEATING PLANE
0.08 C
0.05
0.00
2.65 0.1
2X 2
(0.1) TYP
12
EXPOSED
8
THERMAL PAD
20X 0.5
7
13
3.65 0.1
2X
3
25
SYMM
SEE TERMINAL
DETAIL
19
1
0.30
0.18
24X
0.1
C B A
PIN 1 ID
(OPTIONAL)
24
20
SYMM
0.05
0.5
0.3
24X
4219064 /A 04/2017
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. The package thermal pad must be soldered to the printed circuit board for thermal and mechanical performance.
www.ti.com
EXAMPLE BOARD LAYOUT
RHF0024A
VQFN - 1 mm max height
PLASTIC QUAD FLATPACK - NO LEAD
(2.65)
SYMM
20
24
24X (0.6)
1
19
24X (0.24)
(3.65)
(1.575)
20X (0.5)
25
SYMM
(4.8)
(0.62)
TYP
(R0.05)
TYP
13
7
(
0.2) TYP
VIA
8
12
(1.025)
TYP
(3.8)
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE:18X
0.07 MIN
ALL AROUND
0.07 MAX
ALL AROUND
SOLDER MASK
OPENING
METAL
EXPOSED
METAL
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
EXPOSED
METAL
NON SOLDER MASK
DEFINED
SOLDER MASK
DEFINED
(PREFERRED)
SOLDER MASK DETAILS
4219064 /A 04/2017
NOTES: (continued)
4. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature
number SLUA271 (www.ti.com/lit/slua271).
5. Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to their locations shown
on this view. It is recommended that vias under paste be filled, plugged or tented.
www.ti.com
EXAMPLE STENCIL DESIGN
RHF0024A
VQFN - 1 mm max height
PLASTIC QUAD FLATPACK - NO LEAD
6X (1.17)
(0.685) TYP
20
24
24X (0.6)
1
19
24X (0.24)
(1.24)
TYP
20X (0.5)
SYMM
(4.8)
25
6X (1.04)
13
(R0.05) TYP
7
METAL
TYP
12
8
SYMM
(3.8)
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
EXPOSED PAD 25
75% PRINTED SOLDER COVERAGE BY AREA UNDER PACKAGE
SCALE:20X
4219064 /A 04/2017
NOTES: (continued)
6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
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