TPS65296 [TI]
4.5V 至 18V 输入电压、完整 LPDDR4 和 LPDDR4X 存储器电源解决方案;
| 型号： | TPS65296 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 4.5V 至 18V 输入电压、完整 LPDDR4 和 LPDDR4X 存储器电源解决方案 双倍数据速率 光电二极管 存储 |
| 文件： | 总34页 (文件大小：1830K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
TPS65296
ZHCSK81A – SEPTEMBER 2019 – REVISED OCTOBER 2020
TPS65296 - 完整 LPDDR4/LPDDR4X 存储器电源解决方案
1 特性
3 说明
•
同步降压转换器 (VDD2)
TPS65296 器件能够以最低的总成本和最小的空间为
LPDDR4/LPDDR4X 存储器系统提供完整的电源解决
方案。它符合 JEDEC 标准中的 LPDDR4/LPDDR4X
加电和断电顺序要求。TPS65296 采用两个同步降压转
换器（VDD1 和 VDD2）和一个 1.5A LDO (VDDQ)。
– 输入电压范围：4.5V 至 18V
– 输出电压固定为 1.1V
– D-CAP3™ 模式控制，可实现快速瞬态响应
– 持续输出电流：8A
– 高级 Eco-mode™ 脉冲跳跃
– 集成式 22mΩ/8.6mΩ RDS(on) 内部电源开关
– 600kHz 开关频率
TPS65296 采 用 D-CAP3™ 模 式 ， 开 关 频 率 为
600kHz，可实现快速瞬态响应、良好的负载/线路调
节，并支持陶瓷输出电容器，而无需外部补偿电路。
– 内部软启动：1.6ms
– 逐周期过流保护
TPS65296 利用内部的低 Rdson 电源 MOSFET 提供
了丰富的功能和很高的效率。它支持灵活的电源状态控
制，在 S3 状态下将 VDDQ 置于高阻抗状态，在
S4/S5 状态下对 VDD1、VDD2 和 VDDQ 进行放电。
全面的保护特性包括 OVP、UVP、OCP、UVLO 和热
关断保护。该器件采用热增强型 18 引脚 HotRod™
VQFN 封装，并且设计用于在 –40°C 至 125°C 的结
温范围内工作。
– 锁存输出 OV/UV 保护
•
同步降压转换器 (VDD1)
– 输入电压范围：3V 至 5.5V
– 输出电压固定为 1.8V
– D-CAP3™ 模式控制，可实现快速瞬态响应
– 持续输出电流：1A
– 高级 Eco-mode™ 脉冲跳跃
– 集成式 150mΩ/120mΩ RDS(on) 内部电源开关
– 580kHz 开关频率
器件信息 (1)
封装尺寸（标称值）
器件型号
TPS65296
封装
VQFN (18)
3.00mm × 3.00mm
(1) 如需了解所有可用封装，请参阅数据表末尾的可订购产品附
录。
– 内部软启动：1ms
– 逐周期过流保护
L_VDD1
VDD1
– 锁存输出 OV/UV 保护
PVIN
PVIN
SW_VDD1
VDD1SNS
Cout_VDD1
Cout_VDD2
PVIN_VDD1
• 1.5A LDO (VDDQ)
C-bst
L_VDD2
BST
SW
– 1.5A 持续输出电流
VCC_5V
5V
VDD2
TPS65296
– 仅需 10μF 的陶瓷输出电容
– 在 S3 状态下支持高阻态输出
– ±30mV VDDQ 输出精度（直流 + 交流）
低静态电流：150µA
电源正常指示器
VDD2SNS
VDD2
VLDOIN
VDDQ
Cout_VDDQ
VDDQ
PGOOD
VDDQSNS
VDD_EN
VDDQREF
VDDQ_REF
Cout_VDDQREF
•
•
•
•
•
VDDQ_EN
AGND
PGND_VDD1
PGND
输出放电功能
加电和断电排序控制
非锁存 OT 和 UVLO 保护
典型应用
• 18 引脚 3.0mm × 3.0mm HotRod™ VQFN 封装
2 应用
•
•
•
•
笔记本电脑、台式机和服务器
超极本、平板电脑
单板计算机、工业计算机
分布式电源系统
本文档旨在为方便起见，提供有关 TI 产品中文版本的信息，以确认产品的概要。有关适用的官方英文版本的最新信息，请访问
www.ti.com，其内容始终优先。TI 不保证翻译的准确性和有效性。在实际设计之前，请务必参考最新版本的英文版本。
English Data Sheet: SLUSDU2
TPS65296
www.ti.com.cn
ZHCSK81A – SEPTEMBER 2019 – REVISED OCTOBER 2020
Table of Contents
8 Application and Implementation..................................18
8.1 Application Information............................................. 18
8.2 Typical Application.................................................... 18
9 Power Supply Recommendations................................26
10 Layout...........................................................................27
10.1 Layout Guidelines................................................... 27
10.2 Layout Example...................................................... 27
11 Device and Documentation Support..........................28
11.1 Device Support........................................................28
11.2 Support Resources................................................. 28
11.3 Receiving Notification of Documentation Updates..28
11.4 Trademarks............................................................. 28
11.5 Electrostatic Discharge Caution..............................28
11.6 Glossary..................................................................28
12 Mechanical, Packaging, and Orderable
1 特性................................................................................... 1
2 应用................................................................................... 1
3 说明................................................................................... 1
4 Revision History.............................................................. 2
5 Pin Configuration and Functions...................................3
6 Specifications.................................................................. 4
6.1 Absolute Maximum Ratings........................................ 4
6.2 ESD Ratings............................................................... 4
6.3 Recommended Operating Conditions.........................4
6.4 Thermal Information....................................................5
6.5 Electrical Characteristics.............................................5
6.6 Typical Characteristics................................................7
7 Detailed Description......................................................12
7.1 Overview...................................................................12
7.2 Functional Block Diagram.........................................13
7.3 Feature Description...................................................14
7.4 Device Functional Modes..........................................16
Information.................................................................... 29
4 Revision History
注：以前版本的页码可能与当前版本的页码不同
Changes from Revision * (September 2019) to Revision A (October 2020)
Page
•
更新了整个文档的表、图和交叉参考的编号格式。.............................................................................................1
• Updated Package Information - package outline for pin 16 and pin 18............................................................29
• Updated Package Information - example board layout for pin 16 and pin 18...................................................29
• Updated Package Information - example stencil design for pin 16 and pin 18.................................................29
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ZHCSK81A – SEPTEMBER 2019 – REVISED OCTOBER 2020
5 Pin Configuration and Functions
BST
18
SW PGND_VDD1
1
16
15
SW_VDD1
VLDOIN
2
14
13
12
11
VDDQ
PVIN_VDD1
VCC_5V
17
3
AGND
VDDQSNS
VDD2SNS
VDD1SNS
4
5
7
9
VDD_EN
8
6
10
VDDQREF
VDDQ_EN
PVIN PGOOD PGND
图 5-1. 18-Pin VQFN RJE Package (Top View)
表 5-1. Pin Functions
PIN
I/O
DESCRIPTION
NAME
VLDOIN
VDDQ
AGND
NO.
1
P
O
G
I
Power supply input for VDDQ LDO. Connect VDD2 in typical application.
VDDQ 1.5-A LDO output. It is recommended to connect to 10-μF or larger capacitance for stability.
Signal ground
2
3
VDDQSNS
VDD2SNS
VDDQREF
PVIN
4
VDDQ output voltage feedback
5
I
VDD2 output voltage feedback
6
O
P
Internal reference for VDDQ. Recommend to connect to 0.22-μF or larger capacitance for stability.
Input power supply for VDD2 buck
7
Power good signal open-drain output. PGOOD goes high when VDD1 and VDD2 output voltage are within
the target range.
PGOOD
8
O
PGND
9
G
I
Power ground for VDD2 buck
VDDQ_EN
10
VDDQ_EN signal input for VDDQ LDO enable control. For detail control setup, refer to 表 7-1.
VDD_EN signal input for VDD1 buck and VDD2 buck enable control. For detail control setup, refer to 表
7-1.
VDD_EN
11
I
VDD1SNS
VCC_5V
12
13
14
15
16
17
I
VDD1 output voltage feedback
P
P
O
G
O
Power supply for VDD1 and VDD2 buck converter control logic circuit
Input power supply for VDD1 buck
PVIN_VDD1
SW_VDD1
PGND_VDD1
SW
VDD1 switching node connection to the inductor and bootstrap capacitor
Power ground for VDD1 buck
VDD2 switching node connection to the inductor and bootstrap capacitor
High-side MOSFET gate driver bootstrap voltage input for VDD2 buck. Connect a capacitor between the
BST pin and the SW pin.
BST
18
I
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6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted) (1)
MIN
–0.3
–0.3
–0.3
MAX
20
UNIT
PVIN
V
V
V
VBST
25
VBST-SW
6
Input voltage
VDD_EN, VDDQ_EN, VCC_5V, PVIN_VDD1,
6
V
–0.3
VLDOIN, VDD1SNS, VDD2SNS, VDDQSNS
PGND, AGND, PGND_VDD1
SW
0.3
20
22
7
V
V
–0.3
–0.3
–3
SW (10-ns transient)
V
Output voltage
SW_VDD1
V
–0.3
–3
SW_VDD1 (10-ns transient)
PGOOD, VDDQ, VDDQREF
8
V
6
V
–0.3
–40
–55
TJ
Operating junction temperature
Storage temperature
150
150
°C
°C
Tstg
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under
Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device
reliability.
6.2 ESD Ratings
VALUE
±2000
±500
UNIT
V
Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1)
Electrostatic
discharge
V(ESD)
Charged-device model (CDM), per JEDEC specification JESD22- V C101(2)
V
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
6.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
MIN
4.5
MAX
UNIT
PVIN
18
23
V
V
V
VBST
–0.3
–0.3
VBST-SW
5.5
Input voltage
VDD_EN, VDDQ_EN, VCC_5V, PVIN_VDD1,
VLDOIN, VDD1SNS, VDD2SNS, VDDQSNS
5.5
V
–0.3
PGND, AGND, PGND_VDD1
SW
0.3
18
20
6
V
V
–0.3
–0.3
–3
SW (10-ns transient)
SW_VDD1
V
Output voltage
V
–0.3
–2
SW_VDD1 (10-ns transient)
PGOOD, VDDQ, VDDQREF
7
V
5.5
8
V
–0.3
IVDD2OUT
TJ
VDD2 Output current
A
Operating junction temperature
125
°C
–40
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6.4 Thermal Information
TPS65296
THERMAL METRIC(1)
RJE (VQFN)
18 PINS
58.1
UNIT
RθJA
Junction-to-ambient thermal resistance
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
RθJC(top)
RθJB
Junction-to-case (top) thermal resistance
Junction-to-board thermal resistance
26.1
17.7
Junction-to-top characterization parameter
Junction-to-board characterization parameter
Junction-to-case (bottom) thermal resistance
0.5
ψJT
17.7
ψJB
RθJC(bot)
N/A
(1) For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report.
6.5 Electrical Characteristics
TJ=-40oC to 125oC, VPVIN=12V, VPVIN_VDD1=5V (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
INPUT SUPPLY VOLTAGE
VVDD_EN = VVDDQ_EN = 0 V
5
µA
µA
µA
V
IVCC_5V
VCC_5V supply current
PVIN input voltage range
VVDD_EN = 5 V, VVDDQ_EN = 0 V, no load
VVDD_EN = VVDDQ_EN = 5 V, no load
110
150
VIN
4.5
3.3
1.1
18
UVLO
Wake up VCC_5V voltage
Shut down VCC_5V voltage
Hysteresis VCC_5V voltage
4.1
3.6
500
4.5
V
V
UVLO
VCC_5V under-voltage lockout
mV
VDD2
VVDD2SNS
IVDD2SNS
IVDD2DIS
tVDD2SS
tVDD2DLY
RDSONH
RDSONL
IVDD2OCL
fsw
VDD2 sense voltage
1.115
40
1.13
V
VDD2SNS input current
VDD2 discharge current
VDD2 soft-start time
VVDD2SNS =1.1 V
µA
VVDD_EN = VVDDQ_EN = 0 V, VVDD2SNS = 0.5 V
12
mA
ms
ms
mΩ
mΩ
A
1.6
2
2.65
3.5
VDD2 ramp up delay time
High-side switch resistance
Low-side switch resistance
Low-side valley current limited
VDD2 switching freqency
Minimum off time
1.3
8.2
TJ = 25°C, VVCC_5V = 5V
TJ = 25°C, VVCC_5V = 5V
VOUT = 1.1 V, L = 0.68 µH
22
8.6
9.8
600
198
11.5
kHz
ns
tOFF(MIN)
PGOOD (VDD2, VDD1)
VDD2SNS / VDD1SNS falling (Fault)
VDD2SNS / VDD1SNS rising (Good)
VDD2SNS / VDD1SNS rising (Fault)
VDD2SNS / VDD1SNS falling (Good)
87
93
%
%
%
%
VTHPG
PGOOD threshold
115
110
VPGOOD =0.5V, VVDD_EN =VVDDQ_EN = 5 V, no
load
IPGMAX
PG sink current
46
1
mA
ms
tPGDLY
PG start-up delay
PG from low to high
VDD1
VVDD1SNS
IVDD1SNS
IVDD1DIS
VDD1 sense voltage
1.75
1.8
20
12
1.85
V
VDD1SNS input current
VDD1 discharge current
VVDD1SNS =1.8 V
µA
mA
VVDD_EN = VVDDQ_EN = 0 V, VVDD1SNS = 0.5 V
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TJ=-40oC to 125oC, VPVIN=12V, VPVIN_VDD1=5V (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
1.0
MAX
UNIT
ms
tVDD1SS
RDSONH
RDSONL
IVDD1OCL
fsw
VDD1 soft-start time
2
High-side switch resistance
Low-side switch resistance
Low-side valley current limited
VDD1 switching frequency
Minimum off time
TJ = 25°C, VPVIN_VDD1 = 5V, VVCC_5V = 5V
TJ = 25°C, VPVIN_VDD1=5V, VVCC_5V = 5V
VVDD1SNS = 1.8 V, L = 4.7 µH
150
120
1.6
mΩ
mΩ
A
1.05
2.1
580
195
31
kHz
ns
tOFF(MIN)
tOOA
OOA mode operation period
VVDD1SNS =1.8 V
µs
OVP AND UVP (VDD2, VDD1)
VOVP
OVP threshold voltage
UVP threshold voltage
OVP delay
OVP detect voltage
UVP detect voltage
120
125
62.5
20
130
%
%
VUVP1
tOVPDLY
tUVPDLY
57.5
67.5
µs
µs
UVP delay
250
VDDQ OUTPUT
VVDDQ
Output voltage
0.57
1.7
0.6
2.2
0.63
V
A
TJ = 25°C, IVDDQ ≤1.5A
IVDDQOCLSRC Source current limit
VVDD2SNS = 1.1 V, VVDDQ= VVDDQSNS= 0.5 V
TJ = 25°C, VVDD_EN = 5 V, VVDDQ_EN = 5 V
IVDDQLK
Leakage current
5
0.5
1
IVDDQSNSBIA
VDDQSNS input bias current
VVDD_EN = 5 V, VVDDQ_EN = 5 V
VVDD_EN = 5 V, VVDDQ_EN = 0 V
0
0
–0.5
–1
µA
S
IVDDQSNSLK VDDQSNS leakage current
VDDQ output delay relative to
VDDQ_EN
IVDDQDLY
35
us
TJ = 25°C, VVDD_EN = VVDDQ_EN = 0 V,
VVDD2SNS = 1.1 V, VVDDQ =0.5V
IVDDQDIS
VDDQ discharge current
5.7
mA
VDD_EN, VDDQ_EN LOGIC THRESHOLD
VDD_EN/VDDQ_EN high-level
voltage
VIH
1.35
V
V
VDD_EN/VDDQ_EN low-level
voltage
VIL
0.5
VDD_EN/VDDQ_EN resistance to
RTOGND
GND
500
kΩ
THERMAL PROTECTION
TOTP
OTP trip threshold
OTP hysteresis
150
20
°C
°C
TOTPHSY
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6.6 Typical Characteristics
190
180
170
160
150
140
130
5.5
5.3
5.1
4.9
4.7
4.5
-50
-20
10
40
70
100
130
-50
-20
10
40
70
100
130
Junction Temperature (èC)
Junction Temperature (èC)
D001
D002
VVDD_EN = 5 V
VVDDQ_EN = 5 V
VVDD_EN = 0 V
VVDDQ_EN = 0 V
图 6-1. VCC_5V Supply Current vs Junction
图 6-2. VCC_5V Shutdown Current vs Temperature
Temperature
1.11
1.106
1.102
1.098
1.094
1.09
1.85
1.83
1.81
1.79
1.77
1.75
-50
-20
10
40
70
100
130
-50
-20
10
40
70
100
130
Junction Temperature (èC)
Junction Temperature (èC)
D003
D004
图 6-3. VDD2 Output Voltage vs Junction
图 6-4. VDD1 Output Voltage vs Junction
Temperature
Temperature
1.16
1.05
1
0.95
0.9
1.14
1.12
1.1
0.85
0.8
1.08
1.06
1.04
0.75
0.7
-50
-20
10
40
70
100
130
-50
-20
10
40
70
100
130
Junction Temperature (èC)
Junction Temperature (èC)
D005
D007
图 6-5. Enable On Voltage (VDD_EN) vs Junction
图 6-6. Enable Off Voltage (VDD_EN) vs Junction
Temperature
Temperature
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1.16
1.14
1.12
1.1
1
0.95
0.9
0.85
0.8
1.08
1.06
1.04
0.75
-50
-20
10
40
70
100
130
-50
-20
10
40
70
100
130
Junction Temperature (èC)
Junction Temperature (èC)
D006
D008
图 6-7. Enable On Voltage (VDDQ_EN) vs Junction 图 6-8. Enable Off Voltage (VDDQ_EN) vs Junction
Temperature Temperature
35
30
25
20
15
10
12
11
10
9
8
7
6
-50
-20
10
40
70
100
130
-50
-20
10
40
70
100
130
Junction Temperature (èC)
Junction Temperature (èC)
D009
D010
图 6-9. VDD2 High-Side RDS(on) vs Junction
图 6-10. VDD2 Low-Side RDS(on) vs Junction
Temperature
Temperature
200
180
160
140
120
100
150
140
130
120
110
100
90
-50
-20
10
40
70
100
130
-50
-20
10
40
70
100
130
Junction Temperature (èC)
Junction Temperature (èC)
D011
D012
图 6-11. VDD1 High-Side RDS(on) vs Junction
图 6-12. VDD1 Low-Side RDS(on) vs Junction
Temperature
Temperature
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130
62
61
60
59
58
57
56
128
126
124
122
120
-50
-20
10
40
70
100
130
-50
-20
10
40
70
100
130
Junction Temperature (èC)
Junction Temperature (èC)
D013
D014
图 6-13. VDD2 OVP Threshold vs Junction
图 6-14. VDD2 UVP Threshold vs Junction
Temperature
Temperature
127
126
125
124
123
122
121
62
61
60
59
58
57
56
-50
-20
10
40
70
100
130
-50
-20
10
40
70
100
130
Junction Temperature (èC)
Junction Temperature (èC)
D015
D016
图 6-15. VDD1 OVP Threshold vs Junction
图 6-16. VDD1 UVP Threshold vs Junction
Temperature
Temperature
15
14
13
12
11
10
15
14
13
12
11
10
9
-50
-20
10
40
70
100
130
-50
-20
10
40
70
100
130
Junction Temperature (èC)
Junction Temperature (èC)
D017
D018
图 6-17. VDD2SNS Discharge Current vs Junction
图 6-18. VDD1SNS Discharge Current vs Junction
Temperature
Temperature
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8
7
6
5
4
3
11
10.6
10.2
9.8
9.4
9
-50
-20
10
40
70
100
130
-50
-20
10
40
70
100
130
Junction Temperature (èC)
Junction Temperature (èC)
D019
D021
图 6-19. VDDQSNS Discharge Current vs Junction
图 6-20. VDD2 Valley Current Limit vs Junction
Temperature
Temperature
1.65
1.6
1.7
1.65
1.6
1.55
1.5
1.55
1.5
1.45
1.4
1.45
-50
-20
10
40
70
100
130
-50
-20
10
40
70
100
130
Junction Temperature (èC)
Junction Temperature (èC)
D022
D023
图 6-21. VDD1 Valley Current Limit vs Junction
图 6-22. VDD2 Soft-Start Time vs Junction
Temperature
Temperature
1.2
1.16
1.12
1.08
1.04
1
800
700
600
500
400
300
200
-50
-20
10
40
70
100
130
4
6
8
10
12
14
PVIN (V)
16
18
20
22
24
Junction Temperature (èC)
D024
D027
IOUT = 8 A
图 6-23. VDD1 Soft-Start Time vs Junction
Temperature
图 6-24. VDD2 Switching Frequency vs Input
Voltage
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800
800
700
600
500
400
300
200
100
0
700
600
500
400
300
200
VPVIN=7.4V
VPVIN=12V
VPVIN=19V
3
3.25 3.5 3.75
4 4.25 4.5 4.75
PVIN_VDD1 (V)
5
5.25 5.5
0
1
2
3
4
I-Load (A)
5
6
7
8
D026
D028
IOUT = 1 A
图 6-26. VDD2 Switching Frequency vs Load
Current
图 6-25. VDD1 Switching Frequency vs Input
Voltage
800
700
600
500
400
300
200
100
VPVIN_VDD1=3.3V
VPVIN_VDD1=5V
0
0
0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9
PVIN_VDD1 (V)
1
D029
图 6-27. VDD1 Switching Frequency vs Load Current
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7 Detailed Description
7.1 Overview
The TPS65296 integrates two synchronous step-down buck converters and a LDO to support complete
LPDDR4/LPDDR4X power solution. The VDD2 buck converter has fixed 1.1-V output and supports continuous
8-A output current, and it can operate from 4.5-V to 18-V PVIN input voltage. The VDD1 buck converter has the
fixed 1.8-V output and supports continuous 1-A output current, and can operate from 3-V to 5.5-V PVIN_VDD1
input voltage. The VDDQ LDO has continuous 1.5-A output current capability.
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7.2 Functional Block Diagram
PG high threshold
VDD1
+
+
VDD1SNS
PG low threshold
VDD1
PGOOD
Logic
PG high threshold
VDD2
PGOOD
+
UV threshold
VDD2
+
UV
OV
+
PG low threshold
VDD2
+
OV threshold
VDD2
+
VCC_5V
0.8V
VCC5VOK
4.1 V /
3.6 V
+
+
PWM
VDD2SNS
+
+
Control Logic
BST
Discharge
control
PVIN
ñ
ñ
ñ
ñ
ñ
ñ
ñ
ñ
ñ
ñ
On/Off time
Minimum On/Off
Light load PSM
OVP/UVP/OCP
TSD
VDD2
Internal Ramp
VDD2
Ripple injection
VDD2
Softstart
SW
Soft-Start
Discharge
XCON
SW
PGOOD
Disable/Enable
Sequence Control
PGND
VDD2 One Shot
+
OCL
VDD_EN Threshold
+
ZC
+
VDD_EN
THOK
+
150°C /20°C
VCC_5V
PVIN_VDD1
UV threshold
VDD1
UV
OV
AGND
+
+
OV threshold
VDD1
SW_VDD1
XCON
0.8V
+
PGND_VDD1
+
PWM
VDD1SNS
+
+
+
OCL
Discharge
control
VDD1
Internal Ramp
+
ZC
VDD1
Ripple injection
VDD1
Softstart
SW_VDD1
+
VDDQ_EN
VDD1 One Shot
VDDQ_EN
threshold
VDDQREF
VLDOIN
Discharge
control
0.6V
+
+
+
VDDQ
+
Discharge
control
VDDQSNS
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7.3 Feature Description
7.3.1 PWM Operation and D-CAP3 Control
The main control loop of the two bucks is adaptive on-time pulse width modulation (PWM) controller that
supports a proprietary DCAP3 mode control. The DCAP3 mode control combines adaptive on-time control with
an internal compensation circuit for pseudo-fixed frequency and low external component count configuration with
both low-ESR and ceramic output capacitors. It is stable even with virtually no ripple at the output. The
TPS65296 also includes an error amplifier that makes the output voltage very accurate.
At the beginning of each cycle, the high-side MOSFET is turned on. This MOSFET is turned off after internal
one-shot timer expires. This one-shot duration is set proportional to the converter input voltage, VIN, and is
inversely proportional to the output voltage, VO, to maintain a pseudo-fixed frequency over the input voltage
range, hence it is called adaptive on-time control. The one-shot timer is reset and the high-side MOSFET is
turned on again when the feedback voltage falls below the reference voltage. An internal ripple generation circuit
is added to reference voltage for emulating the output ripple, this enables the use of very low-ESR output
capacitors such as multi-layered ceramic caps (MLCC). No external current sense network or loop compensation
is required for DCAP3 control topology.
Both VDD1 buck and VDD2 buck include an error amplifier that makes the output voltage very accurate. For any
control topology that is compensated internally, there is a range of the output filter it can support. The output filter
used with the TPS65296 is a low-pass L-C circuit. This L-C filter has a double-pole frequency described in 方程
式 1.
1
¦
=
P
2´ p´ LOUT ´ COUT
(1)
At low frequencies, the overall loop gain is set by the internal output set-point resistor divider network and the
internal gain of the TPS65296. The low-frequency L-C double pole has a 180 degree in-phase. At the output
filter frequency, the gain rolls off at a –40 dB per decade rate and the phase drops rapidly. The internal ripple
generation network introduces a high-frequency zero that reduces the gain roll off from –40 dB to –20 dB per
decade and increases the phase to 90 degree one decade above the zero frequency. The internal ripple injection
high-frequency zero is related to the switching frequency. The inductor and capacitor selected for the output filter
must be such that the double pole is placed close enough to the high-frequency zero, so that the phase boost
provided by this high-frequency zero provides adequate phase margin for the stability requirement. The
crossover frequency of the overall system should usually be targeted to be less than one-fifth of the switching
frequency (FSW).
7.3.2 Advanced Eco-mode Control
The VDD1 buck and VDD2 buck are designed with advanced Eco-mode control schemes to maintain high light
load efficiency. As the output current decreases from heavy load conditions, the inductor current is also reduced
and eventually comes to a point where the rippled valley touches zero level, which is the boundary between
continuous conduction and discontinuous conduction modes. The rectifying MOSFET is turned off when the zero
inductor current is detected. As the load current further decreases, the converter runs into discontinuous
conduction mode. The on-time is kept almost the same as it was in the continuous conduction mode, so that it
takes longer time to discharge the output capacitor with smaller load current to the level of the reference voltage.
This makes the switching frequency lower, proportional to the load current, and keeps the light load efficiency
high. The light load current where the transition to Eco-mode operation happens (IOUT(LL)) can be calculated from
方程式 2.
(V -VOUT ) × VOUT
1
IN
IOUT(LL)
=
×
2 × LOUT × FSW
V
IN
(2)
After identifying the application requirements, design the output inductance (LOUT) so that the inductor peak-to-
peak ripple current is approximately between 20% and 30% of the IOUT(max) (peak current in the application). It is
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also important to size the inductor properly so that the valley current does not hit the negative low-side current
limit.
7.3.3 Soft Start and Prebiased Soft Start
The VDD2 buck has an internal 1.6-ms soft start and VDD1 buck has an internal 1-ms soft start. Provide the
voltage supply to PVIN, PVIN_VDD1, and VCC_5V before asserting VDD_EN to be high. When the VDD_EN pin
becomes high, the internal soft-start function begins ramping up the reference voltage to the PWM comparator.
If the output capacitor is prebiased at start-up, the devices initiate switching and start ramping up only after the
internal reference voltage becomes greater than the feedback voltage. This scheme ensures that the converters
ramp up smoothly into regulation point.
7.3.4 Power Good
The Power Good (PGOOD) pin is an open-drain output. Once the VDD1SNS and VDD2SNS pins voltage are
between 90% and 110% of the target output voltage, the PGOOD is deasserted and floats after a 1-ms de-glitch
time. A pullup resistor of 100 kΩ is recommended to pull the voltage up to VCC_5V. The PGOOD pin is pulled
low when:
• the VDD1SNS pin voltage or VDD2SNS pin voltage is lower than 85% or greater than 115% of the target
output voltage,
• in an OVP, UVP, or thermal shutdown event,
• or during the soft-start period.
7.3.5 Overcurrent Protection and Undervoltage Protection
Both VDD1 and VDD2 bucks have the overcurrent protection and undervoltage protection, and the
implementation is same. The output overcurrent limit (OCL) is implemented using a cycle-by-cycle valley detect
control circuit. The switch current is monitored during the OFF state by measuring the low-side FET drain-to-
source voltage. This voltage is proportional to the switch current. To improve accuracy, the voltage sensing is
temperature compensated.
During the on-time of the high-side FET switch, the switch current increases at a linear rate determined by Vin,
Vout, the on-time, and the output inductor value. During the on-time of the low-side FET switch, this current
decreases linearly. The average value of the switch current is the load current IOUT. If the monitored current is
above the OCL level, the converter maintains low-side FET on and delays the creation of a new set pulse, even
the voltage feedback loop requires one, until the current level becomes OCL level or lower. In subsequent
switching cycles, the on-time is set to a fixed value and the current is monitored in the same manner.
There are some important considerations for this type of overcurrent protection. When the load current is higher
than the overcurrent threshold by one half of the peak-to-peak inductor ripple current, the OCL is triggered and
the current is being limited, the output voltage tends to drop because the load demand is higher than what the
converter can support. When the output voltage falls below 60% of the target voltage, the UVP comparator
detects it, the output will be discharged and latched after a wait time of 256 µs. When the overcurrent condition
is removed, the output voltage is latched till the VDD_EN is toggled or repower the VCC_5V power input.
7.3.6 Overvoltage Protection
Both VDD1 and VDD2 bucks have the overvoltage protection feature and have the same implementation. When
the output voltage becomes higher than 125% of the target voltage, the OVP comparator output goes high, and
then the output will be discharged and latched after a wait time of 20 µs. When the over current condition is
removed, the output voltage is latched till the VDD_EN is toggled or repower the VCC_5V power input.
7.3.7 UVLO Protection
Undervoltage Lockout protection (UVLO) monitors the VCC_5V power input. When the voltage is lower than
UVLO threshold voltage, the device is shut off and outputs are discharged. This is a non-latch protection.
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7.3.8 Output Voltage Discharge
The VDD1 buck, VDD2 buck, and VDDQ LDO block all have the discharge function by using internal MOSFETs,
which are connected to the corresponding output terminals VDD1SNS, VDD2SNS, and VDDQ. The discharge is
slow due to the lower current capability of these MOSFETs.
7.3.9 Thermal Shutdown
The TPS65296 monitors the internal die temperature. If the temperature exceeds the threshold value (typically
150°C), the device is shut off and the output will be discharged. This is a non-latch protection. The device
restarts switching when the temperature goes below the thermal shutdown recover threshold.
7.4 Device Functional Modes
7.4.1 Light Load Operation for VDD1 Buck and VDD2 Buck
When the load is light on the VDD1 or VDD2 output, the buck enters pulse skip mode after the inductor current
crosses zero. This is the Eco-mode which improves the efficiency at light load with a lower switching frequency.
Each switching cycle is followed by a period of energy saving sleep time. The sleep time ends when the
VDD1SNS or VDD2SNS voltage falls below the Eco-mode threshold voltage. As the output current decreases,
the period time between switching pulses increases.
7.4.2 Output State Control
The TPS65296 has two enable input pins (VDD_EN and VDDQ_EN) to provide simple control scheme of output
state. All of VDD1, VDD2, and VDDQ are turned on at S0 state (VDD_EN=VDDQ_EN=high). In S3 state
(VDDQ_EN=low, VDD_EN=high), VDD1 and VDD2 voltages are kept on while VDDQ is turned off and left at
high impedance state (high-Z). The VDDQ output floats and does not source current in this state. In S4/S5 states
(VDD_EN=VDDQ_EN =low), all of the three outputs are turned off and discharged to GND. Each state code
represents as follows: S0 = full ON, S3 = suspend to RAM (STR), S4 = suspend to disk (STD), S5 = soft OFF
(see 表 7-1).
表 7-1. VDDQ_EN and VDD_EN Control for Output State
STATE
S0
VDDQ_EN
VDD_EN
VDD1
VDD2
VDDQ
ON
HI
LO
LO
HI
HI
ON
ON
S3
ON
ON
OFF (High-Z)
OFF (discharge)
S5/S4
LO
OFF (discharge)
OFF (discharge)
7.4.3 Output Sequence Control
There are specific sequencing requirements for the LPDDR4/LPDDR4X VDD1 and VDD2 rails. The TPS65296
follows the power rail sequence requirements as shown in 图 7-1 and 图 7-2. VDD1 is greater than VDD2 at all
times during ramp up, operating, and ramp down. The VDDQ output ramp and stable within 35 µs after
VDDQ_EN asserted.
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VDD_EN
VDD_EN
T4
VDDQ_EN
VDDQ
T1
VDD1
T2
T
VDD2
T3
High-Z
High-Z
T1: 0.5ms to 2ms T3: 0.5ms to 2ms
T<35us
图 7-2. Power Sequence, VDDQ versus VDDQ_EN
图 7-1. Power Sequence, VDD1 and VDD2 versus
VDD_EN
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8 Application and Implementation
Note
Information in the following applications sections is not part of the TI component specification, and TI
does not warrant its accuracy or completeness. TI’s customers are responsible for determining
suitability of components for their purposes. Customers should validate and test their design
implementation to confirm system functionality.
8.1 Application Information
The TPS65296 device provides a complete power solution for LPDDR4/LPDDR4X memory system. 表 8-1
shows the power requirements for LPDDR4 and LPDDR4X.
表 8-1. LPDDR4/LPDDR4X Application
VDD1
VDD2
VDDQ
NO(Leave this pin floating)
YES
LPDDR4
YES
YES
LPDDR4X
YES
YES
The schematic of 图 8-1 shows a typical application for LPDDR4X. For VDD2 buck, the PVIN supports 4.5-V to
18-V input range with 1.1-V VDD2 output, the continuous current capability is 8 A. Usually the PVIN_VDD1 and
VCC_5V can share one 5-V power input and supports 1.8-V VDD1 output with 1-A continuous current capability,
and the PVIN_VDD1 can be lowered down to a 3.3-V power supply. The VLDOIN power input usually is
connected to VDD2 output, while also it can be connected to external 1.1-V power supply input. The schematic
of 图 8-2 shows a typical application for LPDDR4. The TPS65296 can be used for LPDDR4 when connecting
VDDQ_EN pin to GND to disable the LDO and leave VDDQ/VDDQSNS pin floating. It doesn't need input cap for
VLDOIN and output cap for VDDQ compare with the application in LPDDR4X. While it also need to connect
VLDOIN to VDD2 or external 1.1-V power supply for internal power supply.
8.2 Typical Application
图 8-1. LPDDR4X Application Schematic
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图 8-2. LPDDR4 Application Schematic
8.2.1 Design Requirements
表 8-2 lists the design parameters for this example.
表 8-2. Design Parameters
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNIT
VDD2 OUTPUT
VOUT
Output voltage
1.115
8
V
A
IOUT
Output current
Transient response
Input voltage
8-A load step
±55
12
mV
V
ΔVOUT
VIN
4.5
18
VOUT(ripple)
FSW
Output voltage ripple
Switching frequency
30
mV(P-P)
kHz
600
VDD1 OUTPUT
VOUT
Output voltage
1.8
1
V
A
IOUT
Output current
Transient response
Input voltage
1-A load step
±90
5
mV
V
ΔVOUT
VIN
3
5.5
VOUT(ripple)
FSW
Output voltage ripple
Switching frequency
30
580
mV(P-P)
kHz
OTHERS
Internal
UVLO
Start VCC_5V input voltage
VCC_5V Input voltage rising
VCC_5V Input voltage falling
V
V
VVCC_5V
Internal
UVLO
Stop VCC_5V input voltage
Light load operating mode
ECO
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8.2.2 Detailed Design Procedure
8.2.2.1 External Component Selection
8.2.2.1.1 Inductor Selection
The inductor ripple current is filtered by the output capacitor. A higher inductor ripple current means the output
capacitor should have a ripple current rating higher than the inductor ripple current. See 表 8-3 for recommended
inductor values.
The RMS and peak currents through the inductor can be calculated using 方程式 3 and 方程式 4. It is important
that the inductor is rated to handle these currents.
æ
2 ö
÷
÷
÷
ø
æ
ç
ö
÷
VOUT × V
- VOUT
(
× LOUT × FSW
IN(max)
)
1
IN(max)
ç 2
I
IL(rms)=
+
×
OUT
ç
ç
è
÷
ø
12
V
ç
è
(3)
(4)
IOUT(ripple)
I
= IOUT
+
L(peak)
2
During transient and short-circuit conditions, the inductor current can increase up to the current limit of the
device so it is safe to choose an inductor with a saturation current higher than the peak current under current
limit condition.
8.2.2.1.2 Output Capacitor Selection
After selecting the inductor the output capacitor needs to be optimized. In DCAP3, the regulator reacts within
one cycle to the change in the duty cycle so the good transient performance can be achieved without needing
large amounts of output capacitance. The recommended output capacitance range is given in 表 8-3.
Ceramic capacitors have very low ESR, otherwise the maximum ESR of the capacitor should be less than
VOUT(ripple)/IOUT(ripple)
.
表 8-3. Recommended Component Values
VOUT (V)
Fsw (kHz)
LOUT (µH)
0.68
0.56
0.47
6.8
COUT(min) (µF)
COUT(max) (µF)
600
600
600
580
580
580
88
88
88
20
20
20
142
142
142
66
1.1
1.8
4.7
66
3.3
66
For VDDQ output, high quality X5R or X7R 10-µF capacitor is recommended and a 0.47 µF is recommended for
VDDQREF output.
8.2.2.1.3 Input Capacitor Selection
The TPS65296 requires input decoupling capacitors on both power supply input PVIN and PVIN_VDD1, and the
bulk capacitors are needed depending on the application. The minimum input capacitance required is given in 方
程式 5.
IOUT×VOUT
CIN(min)
=
V
INripple×V ×FSW
IN
(5)
TI recommends using a high-quality X5R or X7R input decoupling capacitors of 30 µF on the VDD2 buck input
voltage pin PVIN, and 10 µF on the VDD1 buck input voltage pin PVIN_VDD1. The voltage rating on the input
capacitor must be greater than the maximum input voltage. The capacitor must also have a ripple current rating
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greater than the maximum input current ripple of the application. The input ripple current is calculated by 方程式
6:
VIN(min)-VOUT
(
)
VOUT
ICIN(rms) = IOUT ×
×
VIN(min)
VIN(min)
(6)
An additional 0.1-µF capacitor from PVIN to ground and from PVIN_VDD1 to ground is optional to provide
additional high frequency filtering. One ceramic capacitor of 10 µF is recommended for the decoupling capacitor
on VLDOIN pin for providing stable power on VDDQ LDO block. A 1-µF ceramic capacitor is needed for the
decoupling capacitor on VCC_5V input.
8.2.2.1.4 Bootstrap Capacitor and Resistor Selection
A 0.1-µF ceramic capacitor serialized with a 5.1-Ω resistor is recommended between the BST and SW pin for
proper operation. TI recommends using a ceramic capacitor.
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8.2.3 Application Curves
图 8-3 through 图 8-30 apply to the circuit of 图 8-1. VIN = 12 V. TA = 25°C unless otherwise specified.
95
90
85
80
75
70
65
60
55
100
95
90
85
80
75
70
65
60
VPVIN=7.4V, VOUT=1.1V
VPVIN=12V, VOUT=1.1V
VPVIN=19V, VOUT=1.1V
VPVIN_VDD1=3.3V, VOUT=1.8V
VPVIN_VDD1=5V, VOUT=1.8V
0.001
0.01
0.1
I-Load (A)
1
10
0.001
0.01
0.1
1
I-Load (A)
D029
D030
图 8-3. VDD2 Efficiency Curve, VOUT = 1.1 V
图 8-4. VDD1 Efficiency Curve, VOUT = 1.8 V
1.16
1.15
1.14
1.13
1.12
1.11
1.1
1.85
1.84
1.83
1.82
1.81
1.8
1.79
1.78
1.77
1.09
1.08
VPVIN=7.4V
VPVIN=12V
VPVIN=19V
VPVIN_VDD1=3.3V
VPVIN_VDD1=5V
1.07
1.06
1.76
1.75
0
1
2
3
4
I-Load (A)
5
6
7
8
0
0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9
I-Load (A)
1
D031
D032
图 8-5. VDD2 Load Regulation, VOUT = 1.1 V
图 8-6. VDD1 Load Regulation, VOUT = 1.8 V
0.65
0.64
0.63
0.62
0.61
0.6
1.2
1.18
1.16
1.14
1.12
1.1
0.59
0.58
0.57
0.56
0.55
1.08
1.06
1.04
IOUT=0A
IOUT=8A
1.02
1
0
0.2
0.4
0.6
0.8
I-Load (A)
1
1.2
1.4
1.6
4
6
8
10
12
14
PVIN (V)
16
18
20
22
24
D033
D034
图 8-7. VDDQ Load Regulation, VOUT = 0.6 V
图 8-8. VDD2 Line Regulation,VOUT = 1.1 V
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1.85
1.84
1.83
1.82
1.81
1.8
VDD2=50mV/div
1.79
1.78
1.77
1.76
Io=500mA/div
IOUT=0A
IOUT=1A
40ms/div
1.75
3
3.25 3.5 3.75
4 4.25 4.5 4.75
PVIN_VDD1 (V)
5
5.25 5.5
图 8-10. VDD2 Output Voltage Ripple, IOUT = 0 A
D035
图 8-9. VDD1 Line Regulation, VOUT = 1.8 V
VDD2=10mV/div
VDD1=50mV/div
Io=5A/div
Io=500mA/div
10ms/div
1us/div
图 8-11. VDD1 Output Voltage Ripple, IOUT = 0 A
图 8-12. VDD2 Output Voltage Ripple, IOUT = 8 A
VDD_EN=2V/div
VDD1=10mV/div
Io=500mA/div
VDD1=2V/div
VDD2=1V/div
PGOOD=5V/div
1us/div
2ms/div
图 8-13. VDD1 Output Voltage Ripple, IOUT = 1 A
图 8-14. Start-Up Through VDD_EN, IVDD1OUT = 0 A,
IVDD2OUT = 0 A
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VDD_EN=2V/div
VDD1=2V/div
VDD_EN=2V/div
VDD1=2V/div
VDD2=1V/div
PGOOD=5V/div
VDD2=1V/div
PGOOD=5V/div
2ms/div
20ms/div
图 8-15. Start-Up Through VDD_EN, IVDD1OUT = 1 A, 图 8-16. Shutdown Through VDD_EN, IVDD1OUT = 0
IVDD2OUT = 8 A
A, IVDD2OUT = 0 A
VDD_EN=2V/div
VDD1=2V/div
VDD_EN=2V/div
VDDQ_EN==2V/div
VDD2=1V/div
VDD2=1V/div
VDDQ=1V/div
PGOOD=5V/div
20ms/div
2ms/div
图 8-17. Shutdown Through VDD_EN, IVDD1OUT = 1
IVDD2OUT = 0 A
IVDDQ = 0 A
A, IVDD2OUT = 8 A
图 8-18. VDDQ Start-Up Through VDDQ_EN
VDD_EN=2V/div
VDDQ_EN=2V/div
VDD_EN=2V/div
VDDQ_EN=2V/div
VDD2=1V/div
VDD2=1V/div
VDDQ=1V/div
VDDQ=500mV/div
10ms/div
2ms/div
IVDD2OUT = 0 A
IVDDQ = 0 A
IVDD2OUT = 8 A
IVDDQ = 1.5 A
图 8-20. VDDQ Shutdown Through VDDQ_EN
图 8-19. VDDQ Start-Up Through VDDQ_EN
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VDD_EN=2V/div
VDD_EN=2V/div
VDDQ_EN=2V/div
VDD2=1V/div
VDD2=1V/div
VDDQ=500mV/div
VDDQ=500mV/div
4ms/div
4ms/div
IVDD2OUT = 0 A
IVDDQ = 0 A
IVDD2OUT = 8 A
IVDDQ = 1.5 A
图 8-22. VDDQ Start-Up Through VDD_EN
图 8-21. VDDQ Shutdown Through VDDQ_EN
VDD_EN=2V/div
VDD_EN=2V/div
VDD2=1V/div
VDD2=1V/div
VDDQ=500mV/div
VDDQ=500mV/div
4ms/div
10ms/div
IVDD2OUT = 8 A
IVDDQ = 1.5 A
IVDD2OUT = 0 A
IVDDQ = 0 A
图 8-23. VDDQ Start-Up Through VDD_EN
图 8-24. VDDQ Shutdown Through VDD_EN
VDD_EN=2V/div
VDD1=100mV/div
VDD2=1V/div
Io=1A/div
VDDQ=500mV/div
400us/div
4ms/div
Slew Rate=2.5A/us
IVDD2OUT = 8 A
IVDDQ = 1.5 A
图 8-26. VDD1 Transient Response, 0 A to 1 A
图 8-25. VDDQ Shutdown Through VDD_EN
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VDD2=50mV/div
VDD2=50mV/div
Io=5A/div
Io=5A/div
400us/div
400us/div
Slew Rate=2.5A/us
Slew Rate=2.5A/us
图 8-27. VDD2 Transient Response, 1.6 A to 8 A
图 8-28. VDD2 Transient Response, 0.1 A to 6.4 A
SW=10V/div
SW=5V/div
VDD1=1V/div
IL=1A/div
VDD2=500mV/div
IL=5A/div
100us/div
100us/div
图 8-29. VDD1 Normal Operation to Output Hard
图 8-30. VDD2 Normal Operation to Output Hard
Short
Short
9 Power Supply Recommendations
The TPS65296 is designed for LPDDR4/LPDDR4X complete power solution. PVIN is the power input for VDD2
buck, PVIN_VDD1 is the power input for VDD1 buck, VLDOIN input is for VDDQ LDO power supply, VCC_5V is
power supply for internal control logic. Below lists the power on sequence scenarios.
• VDD_EN is high before PVIN or PVIN_VDD1 has the power input, VCC_5V power supply must be provided
after or same time with PVIN or PVIN_VDD1, otherwise the output will be latched. This latch can be
recovered by toggling the VDD_EN pin or re-power the VCC_5V.
• VDD_EN is low before PVIN and PVIN_VDD1 has the power input, then there is no power supply input
sequence requirement for VCC_5V, PVIN and PVIN_VDD1.
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10 Layout
10.1 Layout Guidelines
• A four-layer PCB is recommended for good thermal performance and with maximum ground plane. 3-inch ×
3-inch, four-layer PCB with 2-oz. copper is used as example.
• Place the decoupling capacitors right across PVIN, PVIN_VDD1, and VLDOIN as close as possible.
• Place output inductors and capacitors with IC at the same layer, SW routing should be as short as possible to
minimize EMI, and should be a width plane to carry big current, enough vias should be added to the PGND
connection of output capacitor and also as close to the output pin as possible. Reserve some space between
VDD1 choke and VDD2 choke, just minimize radiation crosstalk.
• Place BST resistor and capacitor with IC at the same layer, close to BST and SW plane, >15 mil width trace
is recommended to reduce line parasitic inductance.
• VDD1SNS/VDD2SNS/VDDQSNS can be 10 mil and must be routed away from the switching node, BST
node or other high efficiency signal.
• PVIN and PVIN_VDD1 trace must be wide to reduce the trace impedance and provide enough current
capability.
• Output capacitors for VDDQ and VDDQREF should be put as close as output pin.
10.2 Layout Example
图 10-1 shows the recommended top-side layout. Component reference designators are the same as the circuit
shown in 图 8-1.
N
OI
LD
V
V
V
PVIN
D
D
D
D
Q
Q
R
E
F
VDD2
SW
S
W
_
V
D
D
1
PGND_VDD1
PGND
VDD1
图 10-1. Top-Side Layout
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11 Device and Documentation Support
11.1 Device Support
11.1.1 Third-Party Products Disclaimer
TI'S PUBLICATION OF INFORMATION REGARDING THIRD-PARTY PRODUCTS OR SERVICES DOES NOT
CONSTITUTE AN ENDORSEMENT REGARDING THE SUITABILITY OF SUCH PRODUCTS OR SERVICES
OR A WARRANTY, REPRESENTATION OR ENDORSEMENT OF SUCH PRODUCTS OR SERVICES, EITHER
ALONE OR IN COMBINATION WITH ANY TI PRODUCT OR SERVICE.
11.2 Support Resources
TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help — straight
from the experts. Search existing answers or ask your own question to get the quick design help you need.
Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do
not necessarily reflect TI's views; see TI's Terms of Use.
11.3 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. Click on
Subscribe to updates to register and receive a weekly digest of any product information that has changed. For
change details, review the revision history included in any revised document.
11.4 Trademarks
D-CAP3™, Eco-mode™, HotRod™, TI E2E™ are trademarks of Texas Instruments.
所有商标均为其各自所有者的财产。
11.5 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled
with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may
be more susceptible to damage because very small parametric changes could cause the device not to meet its published
specifications.
11.6 Glossary
TI Glossary
This glossary lists and explains terms, acronyms, and definitions.
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12 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
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PACKAGE OPTION ADDENDUM
www.ti.com
15-Apr-2022
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
TPS65296RJER
ACTIVE
VQFN-HR
RJE
18
3000 RoHS & Green
NIPDAU | SN
Level-2-260C-1 YEAR
-40 to 125
65296
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
PACKAGE OUTLINE
VQFN-HR - 1 mm max height
PLASTIC QUAD FLATPACK- NO LEAD
RJE0018B
3.1
2.9
A
B
3.1
2.9
PIN 1 INDEX AREA
1 MAX
C
SEATING PLANE
0.08 C
0.05
0.00
2X 0.45
0.25
0.5
0.3
4X
4X
0.6
0.4
(0.1) TYP
0.48
0.28
0.15
4X
9
7
6
10
6X 0.5
2.14
1.94
3X
PKG
2X
1.5
2X
2.5
0.3
0.2
8X
15
0.1
C A B
C
1
0.3
0.2
16
4X
18
0.5
0.3
0.05
10X
4X
0.25
0.15
2X
2X 0.65
0.33
0.23
PKG
0.1
C A B
C
2X 2.48
0.05
4223865 / C 03/2020
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
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EXAMPLE BOARD LAYOUT
VQFN-HR - 1 mm max height
PLASTIC QUAD FLATPACK- NO LEAD
RJE0018B
4X (1.24)
18
2X (0.65)
6X (0.2)
8X (0.6)
4X (0.58)
16
15
1
8X (0.25)
4X
(1.25)
(2.243)
6X (0.5)
PKG
(2.83)
(0.58)
2X
(R0.05) TYP
4X (0.25)
(2.238)
10
6
(0.7)
9
7
PKG
(2.8)
4X (0.28)
4X (0.6)
2X (0.45)
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE: 20X
SOLDER MASK
OPENING
0.05 MAX
ALL AROUND
0.05 MIN
ALL AROUND
METAL
METAL UNDER
SOLDER MASK
SOLDER MASK
OPENING
EXPOSED METAL
EXPOSED METAL
NON- SOLDER MASK
SOLDER MASK
DEFINED
DEFINED
(PREFERRED)
SOLDER MASK DETAILS
4223865 / C 03/2020
NOTES: (continued)
3. For more information, see Texas Instruments literature number SLUA271 (www.ti.com/lit/slua271).
4. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
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EXAMPLE STENCIL DESIGN
VQFN-HR - 1 mm max height
PLASTIC QUAD FLATPACK- NO LEAD
RJE0018B
4X (1.23)
18
2X (0.65)
9X (0.2)
8X (0.6)
4X (0.58)
16
4X (0.225)
15
1
8X (0.25)
4X
(1.24)
3X (1.19)
6X (0.5)
PKG
2X
(1.022)
(2.83)
2X (0.028)
(0.034)
(R0.05) TYP
(1.35)
3X
EXPOSED METAL
4X
(1.019)
6
10
(0.7)
9
7
PKG
(2.8)
4X (0.25)
4X (0.6)
2X (0.45)
SOLDER PASTE EXAMPLE
BASED ON 0.1 mm THICK STENCIL
PRINTED SOLDER COVERAGE BY AREA UNDER PACKAGE
PADS 1, 6, 10 &15: 93% & PADS 7-9,17:89%
SCALE: 20X
4223865 / C 03/2020
NOTES: (continued)
5. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations..
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