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TPS65251-1, TPS65251-2, TPS65251-3

SLVSC70A –JANUARY 2015–REVISED JANUARY 2015

TPS65251-x 4.5-V to 18-V Input, High Current, Synchronous Step Down Three Buck

Switchers With Integrated FET

The converters can operate in 5-, 9-, 12- or 15-V

systems and have integrated power transistors. The

output voltage can be set externally using a resistor

divider to any value between 0.8 V and close to the

input supply. Each converter features an enable pin

1 Features

1

•

Wide Input Supply Voltage Range (4.5 to 18 V)

Output Range 0.8 V to V_IN– 1 V

Continuous Loading: 3 A (Buck 1),

2 A (Buck 2 and 3)

that allows

a delayed start-up for sequencing

purposes, soft-start pin that allows adjustable soft-

start time by choosing the soft-start capacitor, and a

current limit (RLIMx) pin that enables the designer to

adjust current limit by selecting an external resistor

and optimize the choice of inductor. The current

mode control allows a simple RC compensation.

•

Maximum Current: 3.5 A (Buck 1),

2.5 A (Buck 2 and 3)

Adjustable Switching Frequency

300 kHz to 2.2 MHz Set by External Resistor

•

Dedicated Enable for Each Buck

External Synchronization Pin for Oscillator

Adjustable Current Limit Set by External Resistor

Soft-Start Pins

The switching frequency of the converters can either

be set with an external resistor connected to ROSC

pin or can be synchronized to an external clock

connected to the SYNC pin if needed. The switching

regulators are designed to operate from 300 kHz to

2.2 MHz. 180° out-of-phase operation between Buck

1 and Buck 2, 3 (Buck 2 and 3 run in phase)

minimizes the input filter requirements.

Current-Mode Control With Simple Compensation

Circuit

•

Power Good

Automatic PFM/PWM Operation

VQFN Package, 40-Pin 6-mm × 6-mm RHA

TPS65251-x features

a

supervisor circuit that

monitors each converter output. The PGOOD pin is

asserted when sequencing is done, all PG signals are

reported and a selectable end of reset time lapses.

The polarity of the PGOOD signal is active high.

2 Applications

•

Set Top Boxes

Blu-ray™ DVD

DVR

All converters feature an automatic low-power pulse

PFM skipping mode, which improves efficiency during

light loads and standby operation, while ensuring a

very-low output ripple, allowing for a value of less

than 2% at low output voltages.

DTV

Car Audio/Video

Security Camera

Device Information⁽¹⁾

3 Description

PART NUMBER

TPS65251-1

PACKAGE

BODY SIZE (NOM)

The TPS65251-x features three synchronous wide-

input range, high-efficiency buck converters. The

converters are designed to simplify its application

while giving the designer the option to optimize their

usage according to the target application.

TPS65251-2

VQFN (40)

6.00 mm × 6.00 mm

TPS65251-3

(1) For all available packages, see the orderable addendum at

the end of the data sheet.

FB2

GND

EN2

VIN

BST2

VIN2

VIN

V2

VIN

LX2

GND

TPS65251-X

V1

V3

LX3

LX1

LX3

LX1

VIN1

VIN3

BST3

EN3

BST1

EN1

FB1

FB3

1

An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,

intellectual property matters and other important disclaimers. PRODUCTION DATA.

TPS65251-1, TPS65251-2, TPS65251-3

SLVSC70A –JANUARY 2015–REVISED JANUARY 2015

www.ti.com

Table of Contents

7.2 Functional Block Diagram ....................................... 11

7.3 Feature Description................................................. 12

7.4 Device Functional Modes........................................ 15

Application and Implementation ........................ 16

8.1 Application Information............................................ 16

8.2 Typical Application .................................................. 16

Power Supply Recommendations...................... 29

1

2

3

4

5

6

Features.................................................................. 1

Applications ........................................................... 1

Description ............................................................. 1

Revision History..................................................... 2

Pin Configuration and Functions......................... 3

Specifications......................................................... 5

6.1 Absolute Maximum Ratings ..................................... 5

6.2 ESD Ratings.............................................................. 5

6.3 Recommended Operating Conditions....................... 5

6.4 Thermal Information.................................................. 5

6.5 Electrical Characteristics........................................... 6

6.6 Typical Characteristics for Buck 1............................. 8

6.7 Typical Characteristics for Buck 2............................. 9

6.8 Typical Characteristics for Buck 3........................... 10

Detailed Description ............................................ 11

7.1 Overview ................................................................. 11

8

9

10 Layout................................................................... 29

10.1 Layout Guidelines ................................................. 29

10.2 Layout Example .................................................... 30

11 Device and Documentation Support ................. 31

11.1 Related Links ........................................................ 31

11.2 Trademarks........................................................... 31

11.3 Electrostatic Discharge Caution............................ 31

11.4 Glossary................................................................ 31

7

12 Mechanical, Packaging, and Orderable

Information ........................................................... 31

4 Revision History

Changes from Original (January 2015) to Revision A

Page

•

Updated device status to production data ............................................................................................................................. 1

2

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SLVSC70A –JANUARY 2015–REVISED JANUARY 2015

5 Pin Configuration and Functions

30 29 28 27 26 25 24 23 22 21

31

32

20

GND

VIN

EN2

19

BST2

VIN2

18

33

34

35

VIN

LX2

17

VIN

GND

LX3

16

LX2

LX1

QFN RHA40

(power pad connected to ground)

36

37

38

15

14

13

LX3

LX1

VIN1

VIN3

BST3

EN3

BST1

EN1

39

40

12

11

1

2

3

4

5

6

7

8

9

10

Pin Functions

NAME

I/O

DESCRIPTION

NO.

1

Current limit setting for Buck 3. Fit a resistor from this pin to ground to set the peak current limit on the output

inductor.

RLIM3

SS3

I

2

Soft-start pin for Buck 3. Fit a small ceramic capacitor to this pin to set the converter soft-start time.

Compensation for Buck 3. Fit a series RC circuit to this pin to complete the compensation circuit of this

converter.

COMP3

FB3

3

O

I

4

Feedback input for Buck 3. Connect a divider set to 0.8 V from the output of the converter to ground.

Synchronous clock input. If there is a sync clock in the system, connect to the pin. When not used, connect to

GND.

SYNC

5

I

Oscillator set. This resistor sets the frequency of the internal autonomous clock. If external synchronization is

used, the resistor should be fitted and set to about 70% of external clock frequency.

ROSC

FB1

6

7

I

Feedback pin for Buck 1. Connect a divider set to 0.8 V from the output of the converter to ground.

Compensation pin for Buck 1. Fit a series RC circuit to this pin to complete the compensation circuit of this

converter.

COMP1

SS1

8

O

I

9

Soft-start pin for Buck 1. Fit a small ceramic capacitor to this pin to set the converter soft-start time.

Current limit setting pin for Buck 1. Fit a resistor from this pin to ground to set the peak current limit on the output

inductor.

RLIM1

10

I

Enable pin for Buck 1. A low-level signal on this pin disables it. If pin is left open, a weak internal pull-up to V3V

allows for automatic enable. For a delayed start-up, add a small ceramic capacitor from this pin to ground.

EN1

11

I

BST1

VIN1

12

13

14

15

16

17

18

19

I

Bootstrap capacitor for Buck 1. Fit a 47-nF ceramic capacitor from this pin to the switching node.

Input supply for Buck 1. Fit a 10-µF ceramic capacitor close to this pin.

LX1

LX2

O

Switching node for Buck 1

Switching node for Buck 2

VIN2

I

Input supply for Buck 2. Fit a 10-µF ceramic capacitor close to this pin.

BST2

Bootstrap capacitor for Buck 2. Fit a 47-nF ceramic capacitor from this pin to the switching node.

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SLVSC70A –JANUARY 2015–REVISED JANUARY 2015

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Pin Functions (continued)

I/O

DESCRIPTION

NAME

NO.

Enable pin for Buck 2. A low-level signal on this pin disables it. If pin is left open, a weak internal pull-up to V3V

allows for automatic enable. For a delayed start-up, add a small ceramic capacitor from this pin to ground.

EN2

20

I

Current limit setting for Buck 2. Fit a resistor from this pin to ground to set the peak current limit on the output

inductor.

RLIM2

SS2

21

22

23

I

Soft-start pin for Buck 2. Fit a small ceramic capacitor to this pin to set the converter soft-start time.

Compensation pin for Buck 2. Fit a series RC circuit to this pin to complete the compensation circuit of this

converter

COMP2

O

FB2

24

25

26

I

Feedback input for Buck 2. Connect a divider set to 0.8 V from the output of the converter to ground.

Low-power operation mode (active-high) input for TPS65251

Ground pin

LOW_P

GND

Power good. Open-drain output asserted after all converters are sequenced and within regulation. Polarity is

factory selectable (active-high default).

PGOOD

27

O

V7V

28

29

30

31

32

33

34

35

36

37

38

39

O

Internal supply. Connect a 10-μF ceramic capacitor from this pin to ground.

Internal supply. Connect a 3.3- to 10-μF ceramic capacitor from this pin to ground.

Analog ground. Connect all GND pins and the power pad together.

Ground pin

V3V

AGND

GND

VIN

I

Input supply

GND

LX3

Ground pin

O

Switching node for Buck 3

VIN3

Input supply for Buck 3. Fit a 10-µF ceramic capacitor close to this pin.

BST3

I

Bootstrap capacitor for Buck 3. Fit a 47-nF ceramic capacitor from this pin to the switching node.

Enable pin for Buck 3. A low-level signal on this pin disables it. If pin is left open, a weak internal pull-up to V3V

allows for automatic enable. For a delayed start-up, add a small ceramic capacitor from this pin to ground.

EN3

PAD

40

—

Power pad. Connect to ground.

4

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SLVSC70A –JANUARY 2015–REVISED JANUARY 2015

6 Specifications

6.1 Absolute Maximum Ratings

(1)

over operating free-air temperature range (unless otherwise noted)

MIN

–0.3

–1

MAX

18

7

UNIT

VIN1,VIN2, VIN3, LX1, LX2, LX3

V

LX1, LX2, LX3 (maximum withstand voltage transient <10 ns)

BST1, BST2, BST3, referenced to Lx pin

–0.3

Voltage

V7V

7

V3V, RLIM1, RLIM2, RLIM3, EN1, EN2, EN3, SS1, SS2,SS3, FB1, FB2, FB3, PGOOD, SYNC,

ROSC, RST_IN, LOW_P, COMP1, COMP2, COMP3

–0.3

3.6

V

AGND, GND

–0.3

–40

–55

0.3

125

150

V

T_J

Operating virtual junction temperature

Storage temperature

°C

T_stg

(1) Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings

only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating

conditions" is not implied. Exposure to absolute–maximum–rated conditions for extended periods may affect device reliability.

6.2 ESD Ratings

VALUE

±2000

±500

UNIT

Human body model (HBM), per ANSI/ESDA/JEDEC JS-001, all pins⁽¹⁾

Charged device model (CDM), per JEDEC specification JESD22-C101, all pins⁽²⁾

Electrostatic

discharge

V_(ESD)

V

(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.

(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

6.3 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted)

MIN

4.5

NOM

MAX

18

UNIT

V_IN

T_J

Input operating voltage

Junction temperature

V

–40

125

°C

6.4 Thermal Information

TPS65251-x

RHA

40 PINS

32.7

THERMAL METRIC⁽¹⁾

UNIT

R_θJA

Junction-to-ambient thermal resistance

R_θJC(top)

R_θJB

Junction-to-case (top) thermal resistance

Junction-to-board thermal resistance

21.4

8.3

°C/W

ψ_JT

Junction-to-top characterization parameter

Junction-to-board characterization parameter

Junction-to-case (bottom) thermal resistance

0.2

ψ_JB

N/A

R_θJC(bot)

2

(1) For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.

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SLVSC70A –JANUARY 2015–REVISED JANUARY 2015

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MAX UNIT

6.5 Electrical Characteristics

T_J= –40°C to 125°C, V_IN= 12 V, ƒ_SW= 500 Hz (unless otherwise noted)

PARAMETER

TEST CONDITIONS

MIN

TYP

INPUT SUPPLY UVLO AND INTERNAL SUPPLY VOLTAGE

V_IN

Input voltage range

Shutdown

4.5

18

V

IDD_SDN

EN pin = Low for all converters

175

20

µA

Converters enabled, no load

Buck 1 = 3.3 V, Buck 2 = 2.5 V, Buck 3

= 7.5 V,

IDD_Q

Quiescent, low power disabled (Lo)

mA

L = 4.7 µH , ƒ_SW= 800 kHz

Converters enabled, no load

Buck 1 = 3.3 V, Buck 2 = 2.5 V, Buck 3

= 7.5 V,

IDD_{Q_LOW_P}

Quiescent, low power enabled (Hi)

V_INundervoltage lockout

1

mA

V

L = 4.7 µH , ƒ_SW= 800 kHz

Rising V_IN

Falling V_IN

Both edges

4.22

4.1

UVLO_VIN

UVLO_DEGLITCH

110

3.3

µs

V

V_3p3

V_7V

Internal biasing supply

6.25

3.8

V

Rising V7V

Falling V7V

Falling edge

V7V_UVLO

UVLO for internal V7V rail

V

3.6

V7V_{UVLO_DEGLITCH}

110

µs

BUCK CONVERTERS (ENABLE CIRCUIT, CURRENT LIMIT, SOFT START, SWITCHING FREQUENCY AND SYNC CIRCUIT, LOW POWER MODE)

External GPIO mode, V3p3 = 3.2 to 3.4

V

Enable threshold high

Enable high level

0.66 x V_3p3

1.55

V_IH

V

V3p3 = 3.2 to 3.4 V, V_ENXrising

1.67

1.82

External GPIO mode, V3p3 = 3.2 to 3.4

V

Enable threshold low

0.33 x V_3p3

V_IL

Enable low level

V3p3 = 3.2 to 3.4 V, V_ENXfalling

0.98

1.10

2.1

1.1

10

1.24

25%

R_{EN_DIS}

ICH_EN

Enable discharge resistor

Pullup current enable pin

–25%

kΩ

µA

t_D

Discharge time enable pins

Soft-start pin current source

Converter switching frequency range

Frequency setting resistor

Internal oscillator accuracy

External clock threshold high

External clock threshold low

Synchronization range

Power-up

ms

µA

I_SS

5

F_{SW_BK}

Set externally with resistor

Depending on set frequency

ƒ_SW= 800 kHz

0.3

50

2.2

600

MHz

kΩ

R_FSW

ƒ_{SW_TOL}

V_SYNCH

V_SYNCL

–10%

10%

1.24

V3p3 = 3.3 V

V

V3p3 = 3.3 V

1.55

0.2

SYNC_RANGE

SYNC_{CLK_MIN}

SYNC_{CLK_MAX}

VIH_{LOW_P}

VIL_{LOW_P}

2.2

60%

1.24

MHz

Sync signal minimum duty cycle

Sync signal maximum duty cycle

Low power mode threshold high

Low power mode threshold Low

40%

V3p3 = 3.3 V, V_ENXrising

V3p3 = 3.3 V, V_ENXfalling

1.55

V

6

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SLVSC70A –JANUARY 2015–REVISED JANUARY 2015

Electrical Characteristics (continued)

T_J= –40°C to 125°C, V_IN= 12 V, ƒ_SW= 500 Hz (unless otherwise noted)

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX UNIT

FEEDBACK, REGULATION, OUTPUT STAGE

V_IN= 12 V, T_J= 25°C

V_IN= 4.5 to 18 V

–1%

–2%

0.8

1%

V

V_FB

I_FB

Feedback voltage

2%

Feedback leakage current

50

nA

ns

Minimum on-time

(current sense blanking) to specify output

regulation

t_{ON_MIN}

70

100

RLIM₁

Limit resistance range

Buck1 current limit range

Buck2 current limit range

Buck3 current limit range

V_IN= 12 V, ƒ_SW= 500 kHz

75

1.1

100

1.2

300

5.1

300

4.1

kΩ

A

RLIM_2,3

ILIM₁

kΩ

A

ILIM₂

ILIM₃

A

MOSFET (BUCK 1)

H.S. Switch

L.S. Switch

MOSFET (BUCK 2)

H.S. Switch

L.S. Switch

MOSFET (BUCK 3)

H.S. Switch

L.S. Switch

ERROR AMPLIFIER

g_M

Turn-on resistance high-side FET on CH1

Turn-on resistance low-side FET on CH1

BOOT = 6.5 V, T_J= 25°C

V_IN= 12 V, T_J= 25°C

95

50

mΩ

Turn-on resistance high-side FET on CH2

Turn-on resistance low-side FET on CH2

BOOT = 6.5 V, T_J= 25°C

V_IN= 12 V, T_J= 25°C

120

80

mΩ

Turn-on resistance high-side FET on CH3

Turn-on resistance low-side FET on CH3

BOOT = 6.5 V, T_J= 25°C

V_IN= 12 V, T_J= 25°C

120

80

mΩ

Error amplifier transconductance

COMP to ILX g_M

–2 µA < I_COMP< 2 µA

ILX = 0.5 A

130

10

µmhos

A/V

gm_PS

POWER GOOD RESET GENERATOR

Output falling

85%

90%

11

VUV_BUCKX

Threshold voltage for buck under voltage

Output rising (PG is asserted)

Each buck

t_{UV_deglitch}

t_{ON_HICCUP}

Deglitch time (both edges)

Hiccup mode ON time

ms

VUV_BUCKXasserted

13

All converters disabled. After t_{OFF_HICCUP}

elapses, all converters go through

sequencing again.

t_{OFF_HICCUP}

Hiccup mode OFF time

11

ms

Output rising (high-side FET is forced

off)

106%

104%

VOV_BUCKX

Threshold voltage for buck over voltage

Output falling (high-side FET is allowed

to switch)

TPS65251-1

TPS65251-2

TPS65251-3

1000

32

t_RP

Minimum reset period

ms

256

THERMAL SHUTDOWN

T_TRIP

Thermal shutdown trip point

Rising temperature

Device restarts

160

20

°C

µs

T_HYST

Thermal shutdown hysteresis

Thermal shutdown deglitch

t_{TRIP_DEGLITCH}

100

120

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6.6 Typical Characteristics for Buck 1

T_A= 25°C, V_IN= 12 V, V_O= 1.2 V, L = 4.7 µH, C_O= 68 µF, ƒ_SW= 500 Hz (unless otherwise noted)

90%

80%

70%

60%

50%

40%

30%

20%

10%

0%

95%

85%

75%

65%

55%

45%

35%

25%

15%

5%

Vin = 5 V

Vin = 12 V

Vin = 18 V

Vin = 5 V

Vin = 12 V

Vin = 18 V

0.0

0.5

1.0

1.5

2.0

2.5

3.0

0.0

0.5

1.0

1.5

2.0

2.5

3.0

(A)

L = 4.7 µH, 20 mΩ

Figure 1. Efficiency, Forced PWM

Figure 2. Efficiency, LOW_P Mode

95%

85%

75%

65%

55%

45%

35%

25%

15%

5%

1.220

1.210

1.200

1.190

1.180

Vin = 5 V

Vin = 12 V

Vin = 18 V

0

0.5

1

1.5

2

2.5

3

0.0

0.1

0.2

0.3

0.4

0.5

Iout (A)

(A)

L = 4.7 µH, 20 mΩ

Figure 3. Efficiency, LOW_P Mode, 0 to 500 mA

Figure 4. Load Regulation, 25°C, 1% 100-PPM Resistor

5.5

1.215

1.210

1.205

1.200

1.195

MIN

MAX

TYP

5

4.5

4

3.5

3

2.5

5

6

7

8

9 10 11 12 13 14 15 16 17 18

2

Vin (V)

1.5

1

75

100

125

150

175

200

225

250

275

300

Rlim (kΩ)

Figure 5. Line Regulation, Load = 1 A

Figure 6. Current Limit V_IN= 12 V, ƒ_SW= 500 KHz

8

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SLVSC70A –JANUARY 2015–REVISED JANUARY 2015

6.7 Typical Characteristics for Buck 2

T_A= 25°C, V_IN= 12 V, V_O= 1.8 V, L = 4.7 µH, C_O= 68 µF, ƒ_SW= 500 Hz (unless otherwise noted)

95%

85%

75%

65%

55%

45%

35%

25%

15%

5%

95%

85%

75%

65%

55%

45%

35%

25%

15%

5%

Vin = 5 V

Vin = 12 V

Vin = 18 V

Vin = 5 V

Vin = 12 V

Vin = 18 V

-5%

0.0

0.5

1.0

1.5

2.0

0.0

0.5

1.0

1.5

2.0

(A)

L = 4.7 µH, 27 mΩ

Figure 8. Efficiency, LOW_P Mode

Figure 7. Efficiency, Forced PWM

95%

85%

75%

65%

55%

45%

35%

25%

15%

5%

1.812

1.810

1.808

1.806

1.804

1.802

1.800

1.798

Vin = 5 V

Vin = 12 V

Vin = 18 V

0

0.5

1

1.5

2

0.0

0.1

0.2

0.3

0.4

0.5

Iout (A)

(A)

L = 4.7 µH, 27 mΩ

Figure 10. Load Regulation, 25°C, 1% 100-PPM Resistor

Figure 9. Efficiency, LOW_P Mode, 0 to 500 mA

4.5

1.802

1.801

1.800

1.799

1.798

1.797

1.796

1.795

MIN

MAX

TYP

4

3.5

3

2.5

5

6

7

8

9

10 11 12 13 14 15 16 17 18

Vin (V)

2

1.5

1

100

120

140

160

180

200

220

240

260

280

300

RLIM (kΩ)

Figure 12. Current Limit V_IN= 12 V, ƒ_SW= 500 kHz

Figure 11. Line Regulation, Load = 1 A

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6.8 Typical Characteristics for Buck 3

T_A= 25°C, V_IN= 12 V, V_O= 3.3 V, L = 4.7 µH, C_O= 68 µF, ƒ_SW= 500 Hz (unless otherwise noted)

100%

90%

80%

70%

60%

50%

40%

30%

20%

10%

0%

100%

90%

80%

70%

60%

50%

40%

30%

20%

10%

0%

Vin = 5 V

Vin = 12 V

Vin = 18 V

Vin = 5 V

Vin = 12 V

Vin = 18 V

0.0

0.5

1.0

1.5

2.0

0.0

0.5

1.0

1.5

2.0

(A)

L = 4.7 µH, 27 mΩ

Figure 14. Efficiency, LOW_P Mode

Figure 13. Efficiency, Forced PWM

100%

90%

80%

70%

60%

50%

40%

30%

20%

10%

0%

3.335

3.334

3.333

3.332

3.331

3.330

3.329

Vin = 5 V

Vin = 12 V

Vin = 18 V

0

0.5

1

1.5

2

0.0

0.1

0.2

0.3

0.4

0.5

Iout (A)

(A)

L = 4.7 µH, 27 mΩ

Figure 15. Efficiency, LOW_P Mode, 0 to 500 mA

Figure 16. Load Regulation, 25°C, 1% 100-PPM Resistor

4.5

3.332

3.331

3.330

3.329

3.328

3.327

3.326

3.325

MIN

MAX

TYP

4

3.5

3

2.5

2

5

6

7

8

9 10 11 12 13 14 15 16 17 18

1.5

Vin (V)

1

100

120

140

160

180

200

220

240

260

280

300

RLIM (kΩ)

Figure 18. Current Limit V_IN= 12 V, ƒ_SW= 500 KHz

Figure 17. Line Regulation, Load = 1 A

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7 Detailed Description

7.1 Overview

TPS65251-x is a power management IC with three step-down buck converters. Both high-side and low-side

MOSFETs are integrated to provide fully synchronous conversion with higher efficiency. TPS65251-x can support

4.5- to 18-V input supply, high load current, 300-kHz to 2.2-MHz clocking. The buck converters have an optional

PSM mode, which can improve power dissipation during light loads. Alternatively, the device implements a

constant frequency mode by connecting the LOW_P pin to ground. The wide switching frequency of 300 kHz to

2.2 MHz allows for efficiency and size optimization. The switching frequency is adjustable by selecting a resistor

to ground on the ROSC pin. The SYNC pin also provides a means to synchronize the power converter to an

external signal. Input ripple is reduced by 180° out-of-phase operation between Buck 1 and Buck 2. Buck 3

operates in phase with Buck 2.

All three buck converters have peak current mode control which simplifies external frequency compensation. A

traditional type II compensation network can stabilize the system and achieve fast transient response. Moreover,

an optional capacitor in parallel with the upper resistor of the feedback divider provides one more zero and

makes the crossover frequency over 100 kHz.

Each buck converter has an individual current limit, which can be set up by a resistor to ground from the RLIM

pin. The adjustable current limiting enables high-efficiency design with smaller and less expensive inductors.

The device has two built-in LDO regulators. During a standby mode, the 3.3-V LDO and the 6.5-V LDO can be

used to drive MCU and other active loads. By this, the system is able to turn off the three buck converters and

improve the standby efficiency.

The device has a power-good comparator monitoring the output voltage. Each converter has its own soft-start

and enable pins, which provide independent control and programmable soft-start.

7.2 Functional Block Diagram

AGND

ROSC

V3V

OSC

INTERNAL

VOLTAGE RAILS

SYNC

V7V

12V DC Supply

BST1

LX1

Vout BUCK1

Vout BUCK2

Vout BUCK3

VIN1

LX1

SS1

EN1

BUCK1

BUCK2

BUCK3

FB1

from enable logic

COMP1

Rlim1

BST2

LX2

VIN2

SS2

LX2

FB2

from enable logic

EN2

COMP2

Rlim2

BST3

LX3

VIN3

SS3

EN3

LX3

from enable logic

FB3

Rlim3

COMP3

VIN

LOW_P

PFM mode

PG

Generator

PGOOD

GND

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7.3 Feature Description

7.3.1 Adjustable Switching Frequency

To select the internal switching frequency, connect a resistor from ROSC to ground. Figure 19 shows the

required resistance for a given switching frequency.

700

650

600

550

500

450

400

350

300

250

200

150

100

50

0.3

0.8

1.3

1.8

F (MHz)

Figure 19. ROSC vs Switching Frequency

5_OSCꢃN:ꢄ ꢀꢅꢆ u ¦ꢃ0+]ꢄ^{±ꢀꢁꢀꢂꢂ}

(1)

For operation at 800 kHz, a 230-kΩ resistor is required.

7.3.2 Synchronization

The status of the SYNC pin is ignored during start-up and the TPS65251’s control only synchronizes to an

external signal after the PGOOD signal is asserted. The status of the SYNC pin is ignored during start-up and

the TPS65251 only synchronizes to an external clock if the PGOOD signal is asserted. When synchronization is

applied, the PWM oscillator frequency must be lower than the sync pulse frequency to allow the external signal

trumping the oscillator pulse reliably. When synchronization is not applied, the SYNC pin should be connected to

ground.

7.3.3 Out-of-Phase Operation

Buck 1 has a low conduction resistance compared to Buck 2 and 3. Normally Buck 1 is used to drive higher

system loads. Buck 2 and 3 are used to drive some peripheral loads like I/O and line drivers. The combination of

Buck 2's and Buck 3’s loads may be on par with Buck 1’s load. To reduce input ripple current, Buck 2 operates in

phase with Buck 3; Buck 1 and Buck 2 operate 180° out-of-phase. This enables the system, having less input

ripple, to lower component cost, save board space, and reduce EMI.

7.3.4 Delayed Start-Up

If a delayed start-up is required on any of the buck converters, fit a ceramic capacitor to the ENx pins. The delay

added is approximately 1.67 ms per nF connected to the pin. Note that the EN pins have a weak 1-µA pull-up to

the 3V3 rail.

7.3.5 Soft-Start Time

The device has an internal pullup current source of 5 µA that charges an external slow-start capacitor to

implement a slow-start time. Equation 2 shows how to select a slow-start capacitor based on an expected slow-

start time. The voltage reference (V_REF) is 0.8 V and the slow-start charge current (I_ss) is 5 µA. The soft-start

circuit requires 1 nF per 200 µs to be connected at the SS pin. A 1-ms soft-start time is implemented for all

converters fitting 4.7 nF to the relevant pins.

§

¨

·

¸

¹

C_SS(nF)

t_SS(ms) V_REF(V) u

I

(µA)

(2)

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Feature Description (continued)

UVLO

V7V

V3V

200µS

Internal EN

EN treshold

Enx rise time

dictated by C_EN

EN1

EN2

EN3

En discharge

10.24 ms-10%

11.26 ms +10%

PG asserted

Pre-bias timing

896µs +/-10% or

960µs +/-10%

BUCK1

BUCK2

BUCK3

Pre-biased output

Soft star rise time

dictated by C_SS

Soft start timer

10.24 ms-10%

12.28 ms +10%

PGOOD

PG timer

983ms -10%

1024ms +10%

Figure 20. TPS65251-x Timing Diagram

7.3.6 Adjusting the Output Voltage

The output voltage is set with a resistor divider from the output node to the FB pin. TI recommends to use 1%

tolerance or better divider resistors. To improve efficiency at light load, start with 40.2 kΩ for the R1 resistor and

use Equation 3 to calculate R2.

§

¨

©

·

¸

¹

0.8 V

R2 R1u

9_O± ꢀꢁꢂ 9

(3)

Vo

FB

TPS65251-X

R1

R2

-

+

0.8V

Figure 21. Voltage Divider Circuit

7.3.7 Input Capacitor

Use 10-µF X7R/X5R ceramic capacitors at the input of the converter inputs. Connect these capacitors as close

as physically possible to the input pins of the converters.

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Feature Description (continued)

7.3.8 Bootstrap Capacitor

The device has three integrated boot regulators and requires a small ceramic capacitor between the BST and LX

pin to provide the gate drive voltage for the high-side MOSFET. The value of the ceramic capacitor should be

0.047 µF. TI recommends a ceramic capacitor with an X7R or X5R grade dielectric because of the stable

characteristics over temperature and voltage.

7.3.9 Error Amplifier

The device has a transconductance error amplifier. The frequency compensation network is connected between

the COMP pin and ground.

7.3.10 Slope Compensation

The device has a built-in slope compensation ramp. The slope compensation can prevent subharmonic

oscillations in peak current mode control.

7.3.11 Power Good

The PGOOD pin is an open-drain output. The PGOOD pin is pulled low when any buck converter is pulled below

85% of the nominal output voltage. TI recommends to use a pullup resistor from the PGOOD to the output of

Buck 1. The PGOOD is pulled up when all three buck converters’ outputs are more than 90% of its nominal

output voltage.

The reset time of the PGOOD pin varies according to the part:

•

TPS65251-1 is 1 s.

TPS65251-2 is 32 ms.

TPS65251-3 is 256 ms.

The polarity of the PGOOD pin is active high.

7.3.12 3.3-V and 6.5-V LDO Regulators

The following ceramic capacitor (X7R/X5R) should be connected as close as possible to the described pins:

•

10 µF for V7V pin 28

3.3 µF for V3V pin 29

7.3.13 Current Limit Protection

All converters operate in hiccup mode: After an overcurrent event lasting more than 10 ms is sensed in any of

the converters, all the converters shut down for 10 ms, then the start-up sequencing is retried. If the overload has

been removed, the converter ramps up and operates normally. If this is not the case, the converter senses

another overcurrent event and shuts down again, repeating the cycle (hiccup) until the failure is cleared.

If an overload condition lasts for <10 ms, only the relevant affected converter goes into and out of under voltage

and no global hiccup mode occurs. The converter is protected by the cycle-by-cycle current limit during that time.

7.3.14 Overvoltage Transient Protection (OVP)

The device incorporates an OVP circuit to minimize voltage overshoot. The OVP feature minimizes the output

overshoot by implementing a circuit to compare the FB pin voltage to OVP threshold, which is 109% of the

internal voltage reference. If the FB pin voltage is greater than the OVP threshold, the high-side MOSFET is

disabled preventing current from flowing to the output and minimizing output overshoot. When the FB voltage

drops below the lower OVP threshold, which is 107%, the high-side MOSFET is allowed to turn on the next clock

cycle.

7.3.15 Thermal Shutdown

The device implements an internal thermal shutdown to protect itself if the junction temperature exceeds 160°C.

The thermal shutdown forces the device to stop switching when the junction temperature exceeds thermal trip

threshold. After the die temperature decreases below 140°C, the device reinitiates the power-up sequence. The

thermal shutdown hysteresis is 20°C.

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7.4 Device Functional Modes

7.4.1 Low-Power/Pulse Skipping Operation

When a synchronous buck converter operates at light load or standby conditions, the switching losses are the

dominant source of power losses. Under these load conditions, TPS65251-x uses a pulse skipping modulation

technique to reduce the switching losses by keeping the power transistors in the off-state for several switching

cycles, while maintaining a regulated output voltage. Figure 22 shows the output voltage and load plus the

inductor current.

V_OUT

I_L

Burst

Skipping

I_OUT

Figure 22. Low Power/Pulse Skipping

During the burst mode, the converter continuously charges up the output capacitor until the output voltage

reaches a certain limit threshold. The operation of the converter in this interval is equivalent to the peak inductor

current mode control. In each switch period, the main switch is turned on until the inductor current reaches the

peak current limit threshold. As the load increases, the number of pulses increases to make sure that the output

voltage stays within regulation limits. When the load is very light, the low-power controller has a zero crossing

detector to allow the low-side MOSFET to operate even in light load conditions. The transistor is not disabled at

light loads. A zero crossing detection circuit disables it when inductor current reverses. During the whole process,

the body diode does not conduct, but is used as blocking diode only.

During the skipping interval, the upper and lower transistors are turned off and the converter stays in idle mode.

The output capacitors are discharged by the load current until the moment when the output voltage drops to a

low threshold.

The choice of output filter influences the performance of the low-power circuit. The maximum ripple during low-

power mode can be calculated as:

K_RIPT_S

=

V_{OUT _RIPPLE}

C_OUT

where

•

K_RIPis 1.4 for Buck 1.

K_RIPis 0.7 for Buck 2 and Buck 3.

(4)

(5)

T_Scan be calculated as:

0.35

T_S=

é

ê

ë

ù

V

_IN- V_OUT

V

æ

ö

^OUTú

ç

÷

L

V

è

ø

IN

û

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8 Application and Implementation

NOTE

Information in the following applications sections is not part of the TI component

specification, and TI does not warrant its accuracy or completeness. TI’s customers are

responsible for determining suitability of components for their purposes. Customers should

validate and test their design implementation to confirm system functionality.

8.1 Application Information

The device is triple synchronous step down dc/dc converter. It is typically used to convert a higher dc voltage to

lower dc voltages with continuous available output current of 3 A/2 A/2 A. The following design procedure can be

used to select component values for the TPS65251-x.

8.2 Typical Application

1.8 V 2 A V2

C24

R22

20 kΩ

C1

10 µF

4700 pF

C21

22 µF

PG

C2

3.3 µF

LP FB2

C25

100 pF

C26

4.7 nF

R23

137 kΩ

R20

40.2 kΩ

C23

4.7 nF

FB2

C27

4.7 nF

GND

EN2

R21

C20

47 nF

VIN

BST2

VIN

VIN2

32 kΩ

L2

4.7 µH

VIN2

LX2

LX1

L3

4.7 µH

L1

4.7 µH

GND

LX3

TPS65251-x

3.3 V 2 A

1.2 V 3 A V1

V3

LX1

VIN1

BST1

VIN3

C11

22 µF

VIN1

C31

22 µF

C30

47 nF

C10

47 nF

VIN3

BST3

EN3

EN1

C17

4.7 nF

C37

4.7 nF

R13

86.6 kΩ

R10

40.2 kΩ

R30

40.2 kΩ

C13

4.7 nF

C33

4.7 nF

R33

137 kΩ

R1

383 kΩ

C16

4.7 nF

C14

4700 pF

R12

20 kΩ

C36

4.7 nF

R11

R31

12.7 kΩ

C34

4700 pF

R32

20 kΩ

80.6 kΩ

C15

100 pF

C35

100 pF

A. VIN pins require local decoupling capacitors.

Figure 23. Typical Application Circuit

8.2.1 Design Requirements

DESIGN PARAMETERS

VALUE

Output voltage

1.2 V

Transient response 0.5-A to 2-A load step

120 mV

Maximum output current

Input voltage

3 A

12 V nom, 9.6 to 14.4 V

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DESIGN PARAMETERS

Output voltage ripple

Switching frequency

VALUE

<30 mV p-p

500 kHz

8.2.2 Detailed Design Procedure

8.2.2.1 Loop Compensation Circuit

A typical compensation circuit could be type II (R_cand C_c) to have a phase margin between 60° and 90°, or type

III (R_c, C_cand C_ff) to improve the converter transient response. C_Rolladds a high frequency pole to attenuate

high-frequency noise when needed. It may also prevent noise coupling from other rails if there is possibility of

cross coupling in between rails when layout is very compact.

V_o

i_L

C_o

R_L

Gm=10A/V

R_ESR

C_ff

R₁

Current Sense

I/V Gain

FBx

g _M= 130

u

V_ref= 0.8V

R₂

COMPx

R_c

C

Roll

C_c

Figure 24. Loop Compensation

To calculate the external compensation components use Table 1:

Table 1. Design Guideline for the Loop Compensation

TYPE II CIRCUIT

TYPE III CIRCUIT

Select switching frequency that is appropriate for

application depending on L, C sizes, output ripple, EMI

concerns and etc. Switching frequencies between 500 kHz

and 1 MHz give best trade off between performance and

cost. When using smaller L and Cs, switching frequency

can be increased. To optimize efficiency, switching

frequency can be lowered.

Type III circuit recommended for

switching frequencies higher than

500 kHz.

Select cross over frequency (fc) to be less than 1/5 to 1/10

of switching frequency.

Suggested

fc = fs/10

Suggested

fc = fs/10

2p´ ƒ_c´ C_O

=

2p´ ƒ_c´ V_O´ C_O

g_M´ Vref ´ gm_ps

R_C

=

R_C

Set and calculate R_c.

g_M´ gm_ps

(6)

(9)

(7)

Calculate C_cby placing a compensation zero at or before

the converter dominant pole

R_L´ Co

C_c=

1

R_c

¦S

(10)

C_Ou R_Lu 2S

(8)

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Table 1. Design Guideline for the Loop Compensation (continued)

TYPE II CIRCUIT

TYPE III CIRCUIT

Add C_Rollif needed to remove large signal coupling to high

impedance COMP node. Make sure that

Re_sru C_O

1

C_Roll

¦S_Roll

R_C

2 u S u R_Cu C_Roll

(12)

(13)

(11)

is at least twice the cross over frequency.

Calculate C_ffcompensation zero at low frequency to boost

the phase margin at the crossover frequency. Make sure

that the zero frequency (fz_ffis smaller than soft-start

equivalent frequency (1/T_ss).

1

C_¦¦

NA

ꢁ u S u ¦]_¦¦u 5_ꢀ

(14)

8.2.2.2 Selecting the Switching Frequency

The first step is to decide on a switching frequency for the regulator. Typically, you will want to choose the

highest switching frequency possible since this will produce the smallest solution size. The high switching

frequency allows for lower valued inductors and smaller output capacitors compared to a power supply that

switches at a lower frequency. However, the highest switching frequency causes extra switching losses, which

hurt the converter’s performance. The converter is capable of running from 300 kHz to 2.2 MHz. Unless a small

solution size is an ultimate goal, a moderate switching frequency of 500 kHz is selected to achieve both a small

solution size and a high efficiency operation. Using Figure 19, R1 is determined to be 383 kΩ

8.2.2.3 Output Inductor Selection

To calculate the value of the output inductor, use Equation 15. KIND is a coefficient that represents the amount

of inductor ripple current relative to the maximum output current. In general, KIND is normally from 0.1 to 0.3 for

the majority of applications.

For this design example, use KIND = 0.2 and the inductor value is calculated to be 3.6 µH. For this design, a

nearest standard value was chosen: 4.7 µH. For the output filter inductor, it is important that the RMS current

and saturation current ratings not be exceeded. The RMS and peak inductor current can be found from

Equation 16 and Equation 17.

Vin - Vout

Io ´ K_ind

Vout

Lo =

´

Vin ´ ƒsw

(15)

(16)

Vin - Vout

Vout

Iripple =

´

Lo

Vin ´ fsw

æ

ç

è

ö²

÷

1

Vo ´ (Vinmax- Vo)

Vinmax ´ Lo ´ ƒsw

ILrms = Io²+

ILpeak = Iout +

´

12

ø

(17)

(18)

Iripple

2

8.2.2.4 Output Capacitor

There are two primary considerations for selecting the value of the output capacitor. The output capacitors are

selected to meet load transient and output ripple’s requirements.

Equation 19 gives the minimum output capacitance to meet the transient specification. For this example,

L_O= 4.7 µH, ΔI_OUT= 1.5 A – 0.75 A = 0.75 A and ΔV_OUT= 120 mV. Using these numbers gives a minimum

capacitance of 18 µF. A standard 22-µF ceramic capacitor is chose in the design.

2

DI_OUT´ L_o

Co >

V_out´ DVout

(19)

18

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Equation 20 calculates the minimum output capacitance needed to meet the output voltage ripple specification.

Where fsw is the switching frequency, V_RIPPLEis the maximum allowable output voltage ripple, and I_RIPPLEis the

inductor ripple current. In this case, the maximum output voltage ripple is 30 mV. From Equation 16, the output

current ripple is 0.46 A. From Equation 20, the minimum output capacitance meeting the output voltage ripple

requirement is 1.74 µF.

1

Co >

´

Vripple

Iripple

8 ´ ƒsw

(20)

Additional capacitance de-rating for aging, temperature and DC bias should influence this minimum value. For

this example, one 22-µF, 6.3-V X7R ceramic capacitor with 3 mΩ of ESR will be used.

8.2.2.5 Input Capacitor

A minimum 10-µF X7R/X5R ceramic input capacitor is recommended to be added between VIN and GND. These

capacitors should be connected as close as physically possible to the input pins of the converters as they handle

the RMS ripple current shown in Equation 21. For this example, I_OUT= 3 A, V_OUT= 1.2 V, V_INmin= 9.6 V, from

Equation 21, the input capacitors must support a ripple current of 0.99 A RMS.

Vinmin - Vout

(

)

Vout

Icirms = Iout ´

´

Vinmin

(21)

The input capacitance value determines the input ripple voltage of the regulator. The input voltage ripple can be

calculated using Equation 22. Using the design example values, I_OUTmax= 3 A, C_IN= 10 µF, f_SW= 500 kHz, yields

an input voltage ripple of 150 mV.

Ioutmax ´ 0.25

DVin =

Cin ´ ƒsw

(22)

8.2.2.6 Soft-Start Capacitor

The soft-start capacitor determines the minimum amount of time it will take for the output voltage to reach its

nominal programmed value during power-up. This is useful if the output capacitance is very large and would

require large amounts of current to quickly charge the capacitor to the output voltage level.

The soft-start capacitor value can be calculated using Equation 23. In this example, the converter’s soft-start time

is 0.8 ms. In TPS65251-x, Iss is 5 µA and Vref is 0.8 V. From Equation 23, the soft-start capacitance is 5 nF. A

standard 4.7-nF ceramic capacitor is chosen in this design. In this example, C16 is 4.7 nF

Tss(ms) ´ Iss(µA)

Css(nF) =

Vref(V)

(23)

8.2.2.7 Bootstrap Capacitor Selection

A 0.047-µF ceramic capacitor must be connected between the BST to LX pin for proper operation. It is

recommended to use a ceramic capacitor with X5R or better grade dielectric. The capacitor should have 10-V or

higher voltage rating.

8.2.2.8 Adjustable Current Limiting Resistor Selection

The converter uses the voltage drop on the high-side MOSFET to measure the inductor current. The overcurrent

protection threshold can be optimized by changing the trip resistor. Figure 6 governs the threshold of overcurrent

protection for Buck 1. When selecting a resistor, do not exceed the graph limits. In this example, the over current

threshold is 3.2 A. In order to prevent a premature limit trip, the minimum line is used and the resistor is 86.6 kΩ.

When setting high-side current limit to large current values, ensure that the additional load immediately prior to

an overcurrent condition will not cause the switching node voltage to exceed 20 V. Additionally, ensure during

worst case operation, with all bucks loaded immediately prior to current limit, the maximum virtual junction

temperature of the device does not exceed 125°C.

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8.2.2.9 Output Voltage and Feedback Resistors Selection

For the example design, 40.2 kΩ was selected for R10. Vout is 1.2 V, Vref = 0.8 V. Using Equation 24, R11 is

calculated as 80.4 kΩ. A standard 80.6-kΩ resistor is chose in this design.

Vout - Vref

R11 =

´ R10

Vref

(24)

8.2.2.10 Compensation

A type-II compensation circuit is adequate for the converter to have a phase margin between 60 and 90 degrees.

The following equations show the procedure of designing a peak current mode control dc/dc converter.

The compensation design takes the following steps:

1. Set up the anticipated cross-over frequency. In this example, the anticipated cross-over frequency (fc) is 65

kHz. The power stage gain (gm_PS) is 10 A/V and the GM amplifier gain (g_M) is 130 µA/V.

2p ´ ƒc ´ Vo ´ Co

R12 =

g_M´ Vref ´ gm_ps

(25)

2. Place compensation zero at low frequency to boost the phase margin at the crossover frequency. From the

procedures above, the compensation network includes a 20-kΩ resistor (R12) and a 4700-pF capacitor (C1).

3. An additional pole can be added to attenuate high frequency noise.

From the procedures above, the compensation network includes a 20-kΩ resistor (R12) and a 4700-pF capacitor

(C14).

8.2.2.11 3.3-V and 6.5-V LDO Regulators

The following ceramic capacitor (X7R/X5R) should be connected as close as possible to the described pins:

•

10 µF for V7V pin 28

3.3 µF to 10 µF for V3V pin 29

8.2.3 Application Curves

Figure 25. Buck 1 Start-Up (Ch3 = V_IN

)

Figure 26. Buck 1 Soft-Start

20

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Figure 28. Buck 1 Soft-Start 2-A Load

Figure 27. Buck 1 Start-Up 1.5-A Resistive

Figure 29. Buck 1 Switching Node, No Load

Figure 30. Buck 1 Switching Node, 1-A Load

Figure 31. Buck 1 Switching Node, 2-A Load

Figure 32. Buck 1 Switching Node, 3-A Load

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Figure 34. Buck 1 Dynamic Response, 2-A to 3-A Step

Figure 33. Buck 1 Dynamic Response, 0- to 1-A Step

Figure 35. Buck 1 Dynamic Response, 1-A to 3-A Step

Figure 36. Buck 1 Ripple, 1-A Load

Figure 38. Buck 1 Ripple, 3-A Load

Figure 37. Buck 1 Ripple, 2-A Load

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Ch1 = V_OUT

Ch4 = Inductor

Ch2 = COMP1

Ch3 = I_OUT

Ch1 = V_OUT

Ch2 = COMP1

Ch3 = I_OUT

Ch4 = Inductor

Figure 39. Buck 1 Current Limit Operation With Slow

Rising Output Current, Trip at 4 A

Figure 40. Buck 1 Current Limit Operation, Hiccup

Figure 41. Buck 1 Low-Power Output, No Load

Figure 42. Buck 1 Low-Power Operation

Ch1 = V_OUT

Ch3 = I_OUT

Ch4 = Inductor

Ch1 = V_OUT

Ch3 = I_OUT

Ch4 = Inductor

Figure 44. Buck 1 PWM to PFM Transition

Figure 43. Buck 1 PFM to PWM Transition

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Ch3 = V_IN

Figure 45. Buck 2 Start-Up, No Load

Figure 46. Buck 2 Start-Up, 2-A Load

Figure 47. Buck 2 Switching Node, No Load

Figure 48. Buck 2 Switching Node, 1-A Load

Figure 49. Buck 2 Switching Node, 2-A Load

Figure 50. Buck 2 Dynamic Response, 0-A to 1-A Step

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Figure 51. Buck 2 Dynamic Response, 1-A to 2-A Step

Figure 52. Buck 2 Ripple, No Load

Figure 53. Buck 2 Ripple, 1-A Load

Figure 54. Buck 2 Ripple, 3-A Load

Ch1 = V_OUT

Ch3 = I_OUT

Ch4 = Inductor

Figure 55. Buck 2 Low-Power Output, No Load

Figure 56. Buck 2 PFM to PWM Transition

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Ch1 = V_OUT

Ch3 = I_OUT

Ch4 = Inductor

Ch1 = V_OUT

Ch2 = COMP1

Ch3 = I_OUT

Ch4 = Inductor

Figure 57. Buck 2 PWM to PFM Transition

Figure 58. Buck 2 Current Limit Operation

Ch3 = V_IN

Figure 59. Buck 3 Start-Up

Figure 60. Buck 3 Soft-Start

Figure 61. Buck 3 Switching Node, No Load

Figure 62. Buck 3 Switching Node, 1-A Load

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Figure 63. Buck 3 Switching Node, 1.5-A Load

Figure 64. Buck 3 Dynamic Response, 0-A to 1-A Step

Figure 65. Buck 3 Dynamic Response, 1-A to 1.5-A Step

Figure 66. Buck 3 Ripple, No Load

Figure 67. Buck 3 Ripple, 1-A Load

Figure 68. Buck 3 Ripple, 3-A Load

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Ch1 = V_OUT

Ch3 = I_OUT

Ch4 = Inductor

Figure 69. Buck 3 Low-Power Output, No Load

Figure 70. Buck 3 PFM to PWM Transition

Ch1 = V_OUT

Ch3 = I_OUT

Ch4 = Inductor

Ch1 = V_OUT

Ch4 = Inductor

Ch2 = COMP1

Ch3 = I_OUT

Figure 71. Buck 3 PWM to PFM Transition

Figure 72. Buck 3 Current Limit Operation

Figure 73. Temperature Profile, V_O= 1.2 V, I_O= 3 A, V_O= 1.8 V, I_O= 2 A, V_O= 3.3 V, I_O= 2 A, T_A= 28°C

28

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9 Power Supply Recommendations

The device is designed to operate from an input voltage supply range between 4.5 V and 18 V. This input power

supply should be well regulated. If the input supply is located more than a few inches from the TPS65251-x

converter, additional bulk capacitance may be required in addition to the ceramic bypass capacitors. An

electrolytic capacitor with a value of 47 μF is a typical choice.

10 Layout

10.1 Layout Guidelines

Layout is a critical portion of PMIC designs.

•

Place VOUT, and LX on the top layer and an inner power plane for VIN.

Fit also on the top layer connections for the remaining pins of the PMIC and a large top side area filled with

ground.

•

The top layer ground area sould be connected to the internal ground layer(s) using vias at the input bypass

capacitor, the output filter cpacitor and directly under the TPS65251-x device to provide a thermal path from

the Powerpad land to ground.

•

The AGND pin should be tied directly to the power pad under the IC and the power pad.

For operation at full rated load, the top side ground area together with the internal ground plane, must provide

adequate heat dissipating area.

•

There are several signals paths that conduct fast changing currents or voltages that can interact with stray

inductance or parasitic capacitance to generate noise or degrade the power supplies performance. To help

eliminate these problems, the VIN pin should be bypassed to ground with a low ESR ceramic bypass

capacitor with X5R or X7R dielectric. Care should be taken to minimize the loop area formed by the bypass

capacitor connections, the VIN pins, and the ground connections. Since the LX connection is the switching

node, the output inductor should be located close to the LX pins, and the area of the PCB conductor

minimized to prevent excessive capacitive coupling.

•

The output filter capacitor ground should use the same power ground trace as the VIN input bypass capacitor.

Try to minimize this conductor length while maintaining adequate width.

The compensation should be as close as possible to the COMP pins. The COMP and OSC pins are sensitive

to noise so the components associated to these pins should be located as close as possible to the IC and

routed with minimal lengths of trace.

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10.2 Layout Example

Figure 74. Layout Schematic

30

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11 Device and Documentation Support

11.1 Related Links

The table below lists quick access links. Categories include technical documents, support and community

resources, tools and software, and quick access to sample or buy.

Table 2. Related Links

TECHNICAL

DOCUMENTS

TOOLS &

SOFTWARE

SUPPORT &

COMMUNITY

PARTS

PRODUCT FOLDER

SAMPLE & BUY

TPS65251-1

TPS65251-2

TPS65251-3

Click here

11.2 Trademarks

Blu-ray is a trademark of Blu-ray Disc Association.

All other trademarks are the property of their respective owners.

11.3 Electrostatic Discharge Caution

This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with

appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.

ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more

susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.

11.4 Glossary

SLYZ022 — TI Glossary.

This glossary lists and explains terms, acronyms, and definitions.

12 Mechanical, Packaging, and Orderable Information

The following pages include mechanical, packaging, and orderable information. This information is the most

current data available for the designated devices. This data is subject to change without notice and revision of

this document. For browser-based versions of this data sheet, refer to the left-hand navigation.

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PACKAGE MATERIALS INFORMATION

www.ti.com

4-Feb-2015

TAPE AND REEL INFORMATION

*All dimensions are nominal

Device

Package Package Pins

Type Drawing

SPQ

Reel

A0

B0

K0

P1

W

Pin1

Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant

(mm) W1 (mm)

TPS65251-1RHAR

TPS65251-1RHAT

TPS65251-2RHAR

TPS65251-2RHAT

TPS65251-3RHAR

TPS65251-3RHAT

VQFN

RHA

40

2500

250

330.0

180.0

330.0

180.0

330.0

180.0

16.4

6.3

1.1

12.0

16.0

Q2

2500

250

2500

250

Pack Materials-Page 1

PACKAGE MATERIALS INFORMATION

www.ti.com

4-Feb-2015

*All dimensions are nominal

Device

Package Type Package Drawing Pins

SPQ

Length (mm) Width (mm) Height (mm)

TPS65251-1RHAR

TPS65251-1RHAT

TPS65251-2RHAR

TPS65251-2RHAT

TPS65251-3RHAR

TPS65251-3RHAT

VQFN

RHA

40

2500

250

367.0

210.0

367.0

210.0

367.0

210.0

367.0

185.0

367.0

185.0

367.0

185.0

38.0

35.0

38.0

35.0

38.0

35.0

2500

250

2500

250

Pack Materials-Page 2

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TI warrants performance of its components to the specifications applicable at the time of sale, in accordance with the warranty in TI’s terms

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型号：	TPS65251-3RHAT
厂家：	TEXAS INSTRUMENTS
描述：	TPS65251-x 4.5-V to 18-V Input, High Current, Synchronous Step Down Three Buck Switchers With Integrated FET
文件：	总39页 (文件大小：3799K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

TPS65251-3RHAT [TI]

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