TPS65181BRGZT_技术文档

TPS65180, TPS65181, TPS65180B, TPS65181B

www.ti.com

SLVSA76F –MARCH 2010–REVISED FEBRUARY 2011

PMIC FOR E Ink^®Vizplex™ ENABLED ELECTRONIC PAPER DISPLAY

Check for Samples: TPS65180, TPS65181, TPS65180B, TPS65181B

1

FEATURES

•

Thermistor Monitoring

2345

•

Single Chip Power Management Solution for

–

–10°C to 85°C Temperature Range

E Ink^®Vizplex™ Electronic Paper Displays

–

±1°C Accuracy from 0°C to 50°C

I²C Serial Interface

Slave Address 0x48h (1001000)

•

Generates Positive and Negative Gate and

Source Driver Voltages and Back-Plane Bias

from a Single, Low-Voltage Input Supply

–

•

Flexible Power-Up Sequencing

•

3-V to 6-V Input Voltage Range

Interrupt and Sleep Mode Support

Boost Converter for Positive Rail Base

Thermally Enhanced Package for Efficient

Heat Management

(48-Pin 7 mm x 7 mm x 0.9 mm QFN)

Inverting Buck-Boost Converter for Negative

Rail Base

•

Two Adjustable LDOs for Source Driver

Supply

APPLICATIONS

•

Power Supply for Active Matrix E Ink^®

Vizplex™ Panels

–

LDO1: 15 V, 120 mA (VPOS)

LDO2: –15 V, 120 mA (VNEG)

•

EPD Power Supply

•

Accurate Output Voltage Tracking

VPOS - VNEG = ±50 mV

Two Charge Pumps for Gate Driver Supply

E-Book Readers

–

EPSON^®S1D13522 (ISIS) Timing Controller

EPSON^®S1D13521 (Broadsheet) Timing

Controller

–

CP1: 22 V, 10 mA (VDDH)

CP2: –20 V, 12 mA, (VEE)

•

Application Processors With Integrated or

Software Timing Controller ( OMAP™)

•

Adjustable VCOM Driver for Accurate

Panel-Backplane Biasing

–

–0.3 V to –2.5 V

±1.5% Accuracy (±18 mV)

8-Bit Control (11-mV Nominal Step Size)

15-mA Max Integrated Switch

•

Integrated 3.3-V Power Switch for Disabling

System Power Rail

DESCRIPTION

The TPS65180/TPS65181 and TPS65180B/TPS65181B family of devices are single-chip power supplies

designed to for E Ink^®Vizplex™ displays used in portable e-reader applications and support panel sizes up to

9.7 inches. Two high efficiency DC/DC boost converters generate ±17-V rails which are boosted to 22 V and –20

V by two change pumps to provide the gate driver supply for the Vizplex™ panel. Two tracking LDOs create the

±15-V source driver supplies which support up to 120-mA of output current. All rails are adjustable through the

I²C interface to accommodate specific panel requirements.

Accurate back-plane biasing is provided by a linear amplifier and can be adjusted either by an external resistor or

the I²C interface. The VCOM driver can source or sink current depending on panel condition. For automatic

VCOM adjustment in production line, VCOM can be set from –0.3 V to –2.5 V with 8-bit control through the serial

interface. The power switch is integrated to isolate VCOM driver from E Ink^®panel.

1

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas

Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

2

3

4

5

OMAP is a trademark of Texas Instruments.

Vizplex is a trademark of E Ink Corporation.

E Ink is a registered trademark of E Ink Corporation.

EPSON is a registered trademark of Seiko Epson Corporation.

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of the Texas

Instruments standard warranty. Production processing does not

necessarily include testing of all parameters.

TPS65180, TPS65181, TPS65180B, TPS65181B

SLVSA76F –MARCH 2010–REVISED FEBRUARY 2011

www.ti.com

The TPS65180/TPS65181 and TPS65180B/TPS65181B devices provide precise temperature measurement

function to monitor the panel temperature during operation. The TPS65180/TPS65180B requires the host

processor to trigger the temperature acquisition through an I²C write whereas the TPS65181/TPS65181B

automatically updates the temperature every 60 s.

This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with

appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.

ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more

susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.

FUNCTIONAL BLOCK DIAGRAM

10uF

2.2uH

VIN_P

From Input Supply

(3.0V-6.0V)

VB_SW

From Input Supply

(3.0V-6.0V)

4.7uH

VN_SW

4.7uF

DCDC1

DCDC2

PGND3

VB

VN

10uF

PBKG

4.7uF

VDDH_IN

VDDH_D

VEE_IN

VEE_D

Gate driver Supply

(22V, 10mA)

Gate driver Supply

(-20V, 12mA)

POSITIVE

CHARGE

PUMP

NEGATIVE

CHARGE

PUMP

VDDH_DRV

VDDH_FB

VEE_DRV

VEE_FB

1M

4.7uF

10nF

4.7uF

47.5k

53.6k

PGND2

VPOS_IN

VPOS

4.7uF

VNEG_IN

4.7uF

VNEG

4.7uF

Source Driver Supply

(15V, 120mA)

Source Driver Supply

(-15V, 120mA)

4.7uF

LDO1

LDO2

INT_LDO1

INT_LDO2

VREF

10k NTC

43k

TS

INT_LDO1

INT_LDO2

VREF

TEMP

SENSOR

4.7uF

ADC

4.7uF

10uF

VIN

From Input Supply

(3.0V-6.0V)

VCOM

DAC

4.7uF

MUX

AGND1

AGND2

DGND

VCOM_XADJ

VCOM_PWR

VNEG

4.7uF

VIN3P3

GATE DRIVER

From system

To system

VCOM_PANEL

VCOM_CTRL

To panel back -plane

(-0.3 to -2.5V, 15mA)

GATE DRIVER

V3P3

From uC or DSP

10k

VIO

PWR[3]

PWR[2]

PWR[1]

PWR[0]

WAKEUP

PWR_GOOD

nINT

From uC or DSP

10k

VIO

To uC or DSP

DIGITAL

CORE

To uC or DSP

SDA

SCL

From uC or DSP

From/to uC or DSP

I2C

2

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Product Folder Link(s): TPS65180 TPS65181 TPS65180B TPS65181B

TPS65180, TPS65181, TPS65180B, TPS65181B

www.ti.com

SLVSA76F –MARCH 2010–REVISED FEBRUARY 2011

ORDERING INFORMATION⁽¹⁾

T_A

PACKAGE⁽²⁾

ORDERABLE PART NUMBER

TOP-SIDE MARKING

TPS65180

TPS65180RGZR

TPS65181RGZR

TPS65181

-10°C to 85°C

RGZ

TPS65180BRGZR

TPS65180B

TPS65180BRGZR

TPS65181B

(1) For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI

web site at www.ti.com.

(2) Package drawings, thermal data, and symbolization are available at www.ti.com/packaging.

SELECTION GUIDE

DEVICE

TPS65180

TPS65181

TPS65180B

TPS65181B

PART NUMBER

TPS65180RGZR

TPS65181RGZR

TPS65180BRGZR

STATUS

Not recommended for new designs

Active

FUCNTION

TPS65180/TPS65180B

TPS65181/TPS65181B

EPSON ISIS (S1D113522)

EPSON Broadsheet (S1D13521)

OMAP

EPSON ISIS (S1D113522)

Compatilbility

OMAP

ST

Temperature sensor

I²C interface

Triggered by host

Standard

Automatically triggers every 60 s

Supports standard and Broadsheet protocol

INT register must be read before rails can be re-enabled Interrupts are automatically reset when faults

Fault recovery

after a fault

clear. No need to read INT register.

VCOM adjust default

I²C control

External potentiometer

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TPS65180, TPS65181, TPS65180B, TPS65181B

SLVSA76F –MARCH 2010–REVISED FEBRUARY 2011

www.ti.com

DEVICE INFORMATION

RGZ PACKAGE

(TOP VIEW)

24 - PWR_GOOD

23 - PBKG

VDDH_IN - 37

N/C - 38

22 - PWR0

N/C - 39

21 - PWR1

VB_SW - 40

PGND3 - 41

VB - 42

20 - PWR2

19 - PWR3

18 - SDA

VPOS_IN - 43

VPOS - 44

VIN3P3 - 45

V3P3 - 46

TS - 47

17 - SCL

16 - VCOM_PWR

15 - VCOM

14 - VCOM_PANEL

13 - N/C

AGND2 - 48

TERMINAL FUNCTIONS⁽¹⁾

TERMINAL

I/O

DESCRIPTION

NAME

VREF

NO.

1

O

I

Filter pin for 2.25-V internal reference to ADC

Open drain interrupt pin (active low)

nINT

2

VNEG

3

Negative supply output pin for panel source drivers

Input pin for LDO2 (VNEG)

VNEG_IN

WAKEUP

DGND

4

5

I

Wake up pin (active high). Pull this pin high to wake up from sleep mode.

Digital ground

6

INT_LDO2

AGND1

INT_LDO1

VIN

7

O

Internal supply (digital circuitry) filter pin

Analog ground for general analog circuitry

Internal supply (analog circuitry) filter pin

Input power supply to general circuitry

8

9

O

I

10

Analog input for conventional VCOM setup method. Tie this pin to ground if VCOM is set

through I²C interface.

VCOM_XADJ

11

I

VCOM_CTRL

N/C

12

13

VCOM_PANEL gate driver enable (active high)

Not connected

(1) There will be 0-ns, 93.75-µs, 62.52-µs of deglitch for PWRx, WAKEUP, and VCOM_CTRL, respectively.

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4

TPS65180, TPS65181, TPS65180B, TPS65181B

SLVSA76F –MARCH 2010–REVISED FEBRUARY 2011

DESCRIPTION

www.ti.com

TERMINAL

NAME

I/O

NO.

14

15

16

17

18

19

20

21

22

24

25

26

27

28

29

30

31

32

33

34

35

36

37

38

39

40

41

42

43

44

45

46

VCOM_PANEL

VCOM

O

I

Panel common-voltage output pin

Filter pin for panel common-voltage driver

Internal supply input pin to VCOM buffer. Connect to the output of DCDC2.

Serial interface (I²C) clock input

VCOM_PWR

SCL

I

SDA

I/O

I

Serial interface (I²C) data input/output

PWR3

Enable pin for CP1 (VDDH) (active high)

Enable pin for LDO1 (VPOS) (active high)

Enable pin for CP2 (VEE) (active high)

Enable pin for LDO2 (VNEG) and VCOM (active high)

Open drain power good output pin (active low)

Inverting buck-boost converter switch out (DCDC2)

Not connected

PWR2

I

PWR1

I

PWR0

I

PWR_GOOD

VN_SW

N/C

O

VIN_P

I

Input power supply to inverting buck-boost converter (DCDC2)

Feedback pin for inverting buck-boost converter (DCDC2)

Input supply pin for CP1 (VEE)

VN

VEE_IN

VEE_DRV

VEE_D

VEE_FB

PGND2

VDDH_FB

VDDH_D

VDDH_DRV

VDDH_IN

N/C

I

O

I

Driver output pin for negative charge pump (CP2)

Base voltage output pin for negative charge pump (CP2)

Feedback pin for negative charge pump (CP2)

Power ground for CP1 (VDDH) and CP2 (VEE) charge pumps

Feedback pin for positive charge pump (CP1)

Base voltage output pin for positive charge pump (CP1)

Driver output pin for positive charge pump (CP1)

Input supply pin for positive charge pump (CP1)

Not connected

I

O

I

N/C

Not connected

VB_SW

PGND3

VB

O

Boost converter switch out (DCDC1)

Power ground for DCDC1

I

Feedback pin for boost converter (DCDC1)

Input pin for LDO1 (VPOS)

VPOS_IN

VPOS

O

I

Positive supply output pin for panel source drivers

Input pin to 3.3-V power switch

VIN3P3

V3P3

O

Output pin of 3.3-V power switch

Thermistor input pin. Connect a 10k NTC thermistor and a 43k linearization resistor

between this pin and AGND2.

TS

47

48

23

I

AGND2

Reference point to external thermistor and linearization resistor

Die substrate/thermal pad. Connect to VN with short, wide trace. Wide copper trace will

improve heat dissipation. PowerPad must not be connected to ground.

PowerPad (PBKG)

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Product Folder Link(s): TPS65180 TPS65181 TPS65180B TPS65181B

TPS65180, TPS65181, TPS65180B, TPS65181B

SLVSA76F –MARCH 2010–REVISED FEBRUARY 2011

www.ti.com

ABSOLUTE MAXIMUM RATINGS

over operating free-air temperature range (unless otherwise noted)

(1)(2)

VALUE

–0.3 to 7

–0.3 to 0.3

UNIT

V

Input voltage range at VIN, VINP, VIN3P3

Ground pins to system ground

V

Voltage range at SDA, SCL, WAKEUP, PWR3, PWR2, PWR1, PWR0, VCOM_CTRL,

VDDH_FB, VEE_FB, PWR_GOOD, nINT

–0.3 to 3.6

V

VCOM_XADJ

–3.6 to 0.3

–0.3 to 20

–20 to 0.3

–0.3 to 30

Internally limited

2

V

Voltage on VB, VB_SW, VPOS_IN, VDDH_IN

Voltage on VN, VNEG_IN, VEE_IN, VCOM_PWR

Voltage from VINP to VN_SW

Peak output current

V

mA

W

Continuous total power dissipation

Junction-to-ambient thermal resistance⁽³⁾

Operating junction temperature

Operating ambient temperature⁽⁴⁾

Storage temperature

θ_JA

T_J

23

°C/W

°C

-10 to 125

-10 to 85

-65 to 150

±2000

T_A

T_stg

(HBM) Human body model

ESD rating

V

(CDM) Charged device model

±500

(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings

only, and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating

Conditions is not implied. Exposure to absolute maximum rated conditions for extended periods may affect device reliability.

(2) All voltage values are with respect to network ground terminal.

(3) Estimated when mounted on high K JEDEC board per JESD 51-7 with thickness of 1.6 mm, 4 layers, size of 76.2 mm X 114.3 mm, and

2 oz. copper for top and bottom plane. Actual thermal impedance will depend on PCB used in the application.

(4) It is recommended that copper plane in proper size on board be in contact with die thermal pad to dissipate heat efficiently. Thermal pad

is electrically connected to PBKG, which is supposed to be tied to the output of buck-boost converter. Thus wide copper trace in the

buck-boost output will help heat dissipated efficiently.

RECOMMENDED OPERATING CONDITIONS

over operating free-air temperature range (unless otherwise noted)

MIN

NOM

MAX

UNIT

Input voltage range at VIN, VINP, VIN3P3

3

3.7

6

V

Voltage range at SDA, SCL, WAKEUP, PWR3, PWR2, PWR1, PWR0,

VCOM_CTRL, VDDH_FB, VEE_FB, VCOM_XADJ, PWR_GOOD, nINT

0

3.6

V

T_A

T_J

Operating ambient temperature range

Operating junction temperature range

–10

85

°C

125

RECOMMENDED EXTERNAL COMPONENTS

PART NUMBER

INDUCTORS

VALUE

SIZE

MANUFACTURER

LQH44PN4R7MP0

VLS252012T-2R2M1R3

CAPACITORS

4.7 µH

2.2 µH

4 mm x 4 mm x 1.65 mm

2 mm x 2.5 mm x 1.2 mm

Murata

TDK

GRM21BC81E475KA12L

GRM32ER71H475KA88L

All other caps

4.7 µF, 25 V, X6S

4.7 µF, 50 V, X7R

X5R or better

805

Murata

1210

DIODES

BAS3010

SOD-323

SOD-123

Infineon

MBR130T1

ON-Semi

THERMISTOR

NCP18XH103F03RB

10 kW

603

Murata

6

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Product Folder Link(s): TPS65180 TPS65181 TPS65180B TPS65181B

TPS65180, TPS65181, TPS65180B, TPS65181B

www.ti.com

SLVSA76F –MARCH 2010–REVISED FEBRUARY 2011

ELECTRICAL CHARACTERISTICS

V_IN= 3.7 V, T_A= –10°C to 85ºC, Typical values are at T_A= 25ºC (unless otherwise noted)

PARAMETER

INPUT VOLTAGE

TEST CONDITIONS

MIN

TYP

MAX UNIT

V_IN

Input voltage range

3

3.7

2.9

6

V

V_UVLO

V_HYS

INPUT CURRENT

Undervoltage lockout threshold

V_INfalling

V_INrising

Undervoltage lockout hysteresis

400

mV

Operating quiescent current into

VIN

I_Q

Device switching, no load

5.5

mA

Operating quiescent current into

VIN

I_STD

Device in standby mode

Device in sleep mode

130

2.8

µA

I_SLEEP

Shutdown current

10

INTERNAL SUPPLIES

VI_{NT_LDO1}

V_{INT_LDO2}

V_REF

Internal supply

2.7

V

Internal supply

2.25

DCDC1 (POSITIVE BOOST REGULATOR)

V_IN

Input voltage range

Output voltage range

DC set tolerance

Output current

3

3.7

17

6

5

V

V_OUT

-5

%

I_OUT

160 mA

R_DS(ON)

MOSFET on resistance

Switch current limit

Switch current accuracy

Switching frequency

Inductor

V_IN= 3.7 V

350

1.5

mΩ

A

I_LIMIT

-30

30

%

MHz

µH

f_SW

L

1

2.2

C

Capacitor

2x4.7

20

µF

ESR

Capacitor ESR

mΩ

DCDC2 (INVERTING BUCK-BOOST REGULATOR)

V_IN

Input voltage range

Output voltage range

DC set tolerance

Output current

3

3.7

-17

6

5

V

V_OUT

-5

%

I_OUT

160 mA

R_DS(ON)

MOSFET on resistance

Switch current limit

Switch current accuracy

Inductor

V_IN= 3.7 V

350

1.5

mΩ

A

I_LIMIT

-30

30

%

µH

µF

L

4.7

2x4.7

20

C

Capacitor

ESR

Capacitor ESR

mΩ

LDO1 (VPOS)

V_{POS_IN}

Input voltage range

16.15

14.25

17

15

17.85

15.75

V

V_IN= 17 V,

V_{POS_SET[2:0]}= 0x0h to 0x7h

V_SET

Output voltage set value

V_INTERVAL

V_{POS_OUT}

V_OUTTOL

V_DROPOUT

V_LOADREG

I_LOAD

Output voltage set resolution

Output voltage range

Output tolerance

V_IN= 17 V

250

15

mV

V

V_SET= 15 V, I_LOAD= 20 mA

I_LOAD= 120 mA

14.85

-1

15.15

1

%

Dropout voltage

250 mV

Load regulation – DC

Load current range

I_LOAD= 10% to 90%

1

%

120

mA

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TPS65180, TPS65181, TPS65180B, TPS65181B

SLVSA76F –MARCH 2010–REVISED FEBRUARY 2011

www.ti.com

ELECTRICAL CHARACTERISTICS (continued)

V_IN= 3.7 V, T_A= –10°C to 85ºC, Typical values are at T_A= 25ºC (unless otherwise noted)

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX UNIT

I_LIMIT

Output current limit

Soft start time

200

mA

ms

µF

T_SS

1

C

Recommended output capacitor

4.7

LDO2 (VNEG)

V_{NEG_IN}

Input voltage range

-17.85

-15.75

-17

-15

-16.15

-14.25

V

V_IN= –17 V,

V_{NEG_SET[2:0]}= 0x0h to 0x7h

V_SET

Output voltage set value

V_INTERVAL

V_{NEG_OUT}

V_OUTTOL

V_DROPOUT

V_LOADREG

I_LOAD

Output voltage set resolution

Output voltage range

Output tolerance

V_IN= –17 V

250

-15

mV

V

V_SET= –15 V, I_LOAD= –20 mA

I_LOAD= 120 mA

-15.15

-1

-14.85

1

%

Dropout voltage

250 mV

Load regulation – DC

Load current range

Output current limit

Soft start time

I_LOAD= 10% to 90%

1

%

120

mA

ms

µF

I_LIMIT

200

T_SS

1

C

Recommended output capacitor

4.7

LD01 (POS) AND LDO2 (VNEG) TRACKING

Difference between VPOS and

VNEG

V_SET= ±15 V,

I_LOAD= ±20 mA, 0°C to 60°C

V_DIFF

-50

50 mV

VCOM DRIVER

V_{COM_SET[7:0]}= 0x74h (–1.25 V)

V_IN= 3.4 V to 4.2 V, no load

-0.8

0.8

%

Accuracy

V_{COM_SET[7:0]}= 0x74h (–1.25 V)

V_IN= 3.0 V to 6.0 V, no load

-1.5

-2.5

1.5

V_COM

Output voltage range

Resolution

-0.3

V

V_{COM_ADJ}= 1 V, 1 LSB

V_{COM_ADJ}= 0 V

11

1

17 mV

V/V

G

V_COMgain (V_{COM_XADJ}/V_COM

)

VCOM SWITCH

V_COM= –1.25 V, V_{COM_PANEL}= 0 V

C_VCOM= 4.7 µF, C_{VCOM_PANEL}= 4.7 µF

T_ON

Switch ON time

1

ms

R_DS(ON)

I_LIMIT

MOSFET ON resistance

MOSFET current limit

V_COM= –1.245 V, I_COM= 30 mA

20

35

Ω

Not tested in production

200

mA

V_COM= 0 V,

V_{COM_PANEL}= –2.5 V

I_SWLEAK

Switch leakage current

8.3

nA

VIN3P3 TO V3P3 SWITCH

R_DS(ON)

MOSFET ON resistance

V_IN3P3= 3.3 V, I_D= 2 mA

50

Ω

CP1 (VDDH) CHARGE PUMP

V_{DDH_IN}

Input voltage range

Feedback voltage

Accuracy

16.15

17

1

17.85

V

V_FB

-3

3

%

V

V_{DDH_OUT}

I_LOAD

f_SW

Output voltage range

Load current range

Switching frequency

V_SET= 22 V, I_LOAD= 2 mA

21

22

23

10 mA

KHz

560

10

C_D

Recommended driver capacitor

Recommended output capacitor

nF

C_O

4.7

µF

CP2 (VEE) NEGATIVE CHARGE PUMP

V_{EE_IN}

Input voltage range

-17.75

-17

-16.15

V

8

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Product Folder Link(s): TPS65180 TPS65181 TPS65180B TPS65181B

TPS65180, TPS65181, TPS65180B, TPS65181B

www.ti.com

SLVSA76F –MARCH 2010–REVISED FEBRUARY 2011

ELECTRICAL CHARACTERISTICS (continued)

V_IN= 3.7 V, T_A= –10°C to 85ºC, Typical values are at T_A= 25ºC (unless otherwise noted)

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX UNIT

Feedback voltage

-1

V

V_FB

Accuracy

-3

3

%

V

V_{EE_OUT}

I_LOAD

f_SW

Output voltage range

Load current range

Switching frequency

Recommended driver capacitor

Recommended output capacitor

V_SET= –20 V, I_LOAD= 3 mA

-21

-20

-19

12 mA

KHz

560

10

C_D

nF

C_O

4.7

µF

THERMISTOR MONITOR⁽¹⁾

A_TMS

Temperature to voltage ratio

Not tested in production

Temperature = 0°C

-0.0158

1.575

V/°C

V

Offset_TMS

V_{TMS_HOT}

Offset

Temp hot trip voltage (T = 50°C)

TEMP_HOT_SET = 0x8C

0.768

V

Temp hot escape voltage (T =

45°C)

V_{TMS_COOL}

TEMP_COOL_SET = 0x82

0.845

V

V_{TMS_MAX}

R_{NTC_PU}

R_LINEAR

Maximum input level

Internal pull up resistor

External linearization resistor

ADC resolution

2.25

7.307

43

V

KΩ

mV

µs

ADC_RES

ADC_DEL

TMST_TOL

Not tested in production, 1 bit

Not tested in production

8.75

19

ADC conversion time

Accuracy

-2

2

LSB

LOGIC LEVELS AND TIMING CHARTERISTICS (SCL, SDA, nINT, PWR_GOOD, PWRx, WAKEUP)

I_O= 3 mA, sink current

(SDA, nINT, PWR_GOOD)

V_OL

Output low threshold level

0.4

V

V_IL

Input low threshold level

Input high threshold level

Input bias current

V

V_IH

1.2

I_(bias)

V_IO= 1.8 V

1

µA

ms

t_low,WAKEUP

f_SCL

WAKEUP low time

minimum low time for WAKEUP pin

150

SCL clock frequency

400 KHz

OSCILLATOR

f_OSC

Oscillator frequency

Frequency accuracy

9

MHz

T_A= –40°C to 85°C

-10

10

%

THERMAL SHUTDOWN

T_SHTDWNThermal trip point

Thermal hysteresis

150

20

°C

(1) 10-kΩ Murata NCP18XH103F03RB thermistor (1%) in parallel with a linearization resistor (43kΩ, 1%) are used at TS pin for panel

temperature measurement.

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MODES OF OPERATION

The TPS65180/TPS65181 and TPS65180B/TPS65181B have three modes of operation, SLEEP, STANDBY, and

ACTIVE. SLEEP mode is the lowest-power mode in which all internal circuitry is turned off. In STANDBY, all

power rails are shut down but the device is ready to accept commands through PWR[3:0] pins and/or I²C

interface. In ACTIVE mode one or more power rails are enabled.

SLEEP

This is the lowest power mode of operation. All internal circuitry is turned off, registers are

reset to default values and the device does not respond to I²C communications.

TPS65180/TPS65181 and TPS65180B/TPS65181B enter SLEEP mode whenever WAKEUP

pin is pulled low.

STANDBY

In STANDBY all internal support circuitry is powered up and the device is ready to accept

commands either through GPIO or I²C control but none of the power rails are enabled. To

enter STANDBY mode the WAKEUP pin must be pulled high and all PWRx pins must be

pulled low or the STANDBY bit of the ENABLE register must be set high. The device also

enters STANDBY mode if input under voltage lock out (UVLO), positive boost under voltage

(VB_UV), or inverting buck-boost under voltage (VN_UV) is detected, or thermal shutdown

occurs.

ACTIVE

The device is in ACTIVE mode when any of the output rails are enabled and no fault

condition is present. This is the normal mode of operation while the device is powered up. In

ACTIVE mode, a falling edge on any PWRx pin shuts down and a rising edge powers up the

corresponding rail.

MODE TRANSISITONS

SLEEP → ACTIVE

WAKEUP pin is pulled high (rising edge) with any PWRx pin high. Rails come up in the order

defined by the PWR_SEQx registers.

SLEEP → STANDBY

WAKEUP pin is pulled high (rising edge) with all PWRx pins low. Rails will remain down until

one or more PWRx pin is pulled high.

ACTIVE → SLEEP

WAKEUP pin is pulled low (falling edge). Rails are shut down in the reverse power-up order

defined by PWR_SEQ registers.

ACTIVE → STANDBY

WAKEUP pin is high. All PWRx pins are pulled low (falling edge). Rails shut down in the

order in which PWRx pins are pulled low. In the event of thermal shut down (TSD), under

voltage lock out (UVLO), positive boost or inverting buck-boost under voltage (UV), or when

STANDBY bit is set to 1, the device shuts down all rails in the reverse power-up order

defined by the PWR_SEQx registers.

STANDBY → ACTIVE

WAKEUP pin is high and any PWRx pin is pulled high (rising edge). Rails come up in the

same order as PWRx pins are pulled high. Alternatively, if ACTIVE bit is set to 1, output rails

will power up in the order defined by the PWR_SEQx registers.

STANDBY → SLEEP

WAKEUP pin is pulled low (falling edge) while none of the output rails are enabled.

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SLVSA76F –MARCH 2010–REVISED FEBRUARY 2011

POWER DOWN

Battery removed

All rails = OFF

I2C = NO

Registersà default

SLEEP

STANDBY

ACTIVE

?

WAKEUP( ) &

All PWRx pins= low

WAKEUP(?)

All rails = OFF

= YES

I2C

WAKEUP= high &

(*)

(STANDBY bit= 1 ||

WAKEUP= high &

(ACTIVE bit= 1^(*)||

all PWRx pins= (?) ^(**)||

?

any PWRx pin( )^(**)

)

FAULT ^(**)

)

Rails

I2C

= ON

= YES

NOTES:

||, &

= logic OR, logic AND.

(?), ( ) = rising edge, falling edge.

?

FAULT = UVLO || TSD (thermal shutdown)|| BOOST UV.

(*)

= Power sequencing is register controlled.

= Power sequencing is GPIO controlled.

(**)

Figure 1. Global State Diagram

WAKE-UP AND POWER UP SEQUENCING

The TPS65180/TPS65181 and TPS65180B/TPS65181B support flexible power-up sequencing through GPIO

control using the PWR3, 2, 1, 0 pins or I²C control using the PWR_SEQ0, 1, 2 registers. Using GPIO control, the

output rails are enabled/disabled in the order in which the PWRx pins are asserted/de-asserted, respectively, and

the power-up timing is controlled by the host only.

In I²C control mode the power-up/down order and timing are defined by user register settings. The default

settings support the E Ink^®Vizplex™ panel and typically do not need to be charged by the user.

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GPIO CONTROL

Under GPIO control the system host in E Ink^®Vizplex™ panel module enables the TPS65180/TPS65181 and

TPS65180B/TPS65181B output rails by asserting the PWR0, PWR1, PWR2, PWR3 signals and the host has full

control over the order and timing in which the output rails are powered up and down. Rails are in regulation 2 ms

after their respective PWRx pin has been asserted with the exception of the first rail, which takes 6 ms to power

up. The additional time is needed to power up the positive and inverting buck-boost regulator which need to be

turned on before any other rail can be enabled. Once all rails are enabled and in regulation the PWR_GOOD pin

is

released

(pin status = HiZ and power good line is pulled high by external pull-up resistor). The PWRx pins are assigned to

the rails as follows:

•

PWR0: LDO2 (VNEG) and VCOM

PWR1: CP2 (VEE)

PWR2: LDO2 (VPOS)

PWR3: CP1 (VDDH)

Rails are powered down whenever the host de-asserts the respective PWRx pin, and once all rails are disabled

the device enters STANDBY mode. The next step is then to de-assert the WAKEUP pin to enter SLEEP mode

which is the lowest-power mode of operation.

It is possible for the host to force the TPS65180/TPS65181 and TPS65180B/TPS65181B directly into SLEEP

mode from ACTIVE mode by de-asserting the WAKEUP pin in which case the device follows the power-down

sequence defined by the PWR_SEQx registers before entering SLEEP mode.

I²C CONTROL

Under I²C control the power-up sequence is defined by the PWR_SEQx registers rather than through GPIO

control. In SLEEP mode the TPS65180/TPS65181 and TPS65180B/TPS65181B are completely turned off, the

I²C registers are reset, and the device does not accept any I²C transaction. Pull the WAKEUP pin high while all

PWRx pins are held low and the device will enter STANDBY mode which enables the I²C interface. Write to the

PWR_SEQ0 register to define the order in which the output rails will be enabled at power-up and to the

PWR_SEQ1 and PWR_SEQ2 registers to define the power-up delays between rails. Finally, set the ACTIVE bit

in the ENABLE register to 1 to execute the power-up sequence and bring up all power rails.

It is possible for the host to force the TPS65180/TPS65181 and TPS65180B/TPS65181B directly into ACTIVE

mode from SLEEP mode by pulling the WAKEUP pin high while at least one of the PWRx pins is pulled high. In

this case the default power-up sequence defined by the PWR_SEQx registers applies and the device will start

powering up the rails 5.5 ms after the WAKEUP signal has been pulled high.

To power-down the device, set the STANDBY bit of the ENABLE register to 1 then the TPS65180/TPS65181 and

TPS65180B/TPS65181B will follow the reverse power-up sequence to bring down all power rails. While the

sequencer is busy powering up the power rails, any activity on the PWRx pins is ignored. Once all rails are up,

any of the output rails can be disabled by applying a negative edge on the PWRx input pins, i.e. if the host

toggles the PWRx pin high-low or low-high-low, the respective rail will be disabled regardless of how it has been

enabled.

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SLVSA76F –MARCH 2010–REVISED FEBRUARY 2011

WAKEUP

DLY0 + 5.5ms

DLY1

DLY2

DLY3

STROBE 1

SEQ = 00

STROBE 2

SEQ = 01

STROBE 3

SEQ = 10

STROBE 4

SEQ = 11

DLY0

DLY3

DLY2

DLY1

STROBE 4

SEQ = 11

STROBE 3

SEQ = 10

STROBE 2

SEQ = 01

STROBE 1

SEQ = 00

TOP: Power-up sequence is defined by assigning strobes to individual rails. STROBE1 is the first

strobe to occur after WAKEUP has been pulled high and STROBE4 is the last event in the sequence.

STROBES are assigned to rails in PWR_SEQ0 register and delays between states are defined in

PWR_SEQ1 and PWR_SEQ2 registers.

BOTTOM: Power-down sequence follows reverse power-up sequence.

Figure 2. I²C Control

DEPENDENCIES BETWEEN RAILS

Charge pumps, LDOs, and VCOM driver are dependent on the positive and inverting buck-boost converters and

several dependencies exist that affect the power-up sequencing. These dependencies are listed below.

1. Inverting buck-boost (DCDC2) must be in regulation before positive boost (DCDC1) can be enabled.

Internally, DCDC1 enable is gated by DCDC2 power good.

2. Positive boost (DCDC1) must be in regulation before LDO2 (VNEG) can be enabled. Internally LDO2 enable

is gated DCDC1 power-good.

3. Positive boost (DCDC1) must be in regulation before VCOM can be enabled; Internally VCOM enable is

gated by DCDC1 power good.

4. Positive boost (DCDC1) must be in regulation before negative charge pump (CP2) can be enabled. Internally

CP2 enable is gated by DCDC1 power good.

5. Positive boost (DCDC1) must be in regulation before positive charge pump (CP1) can be enabled. Internally

CP1 enable is gated by DCDC1 power good.

6. LDO2 must be in regulation before LDO1 can be enabled. Internally LDO1 enable is gated by LDO2 power

good.

7. The minimum delay time between any two PWRx pins must be > 62.5 µs in order to follow the power up

sequence defined by GPIO control. If any two PWRx pins are pulled up together (< 62.5 µs apart) or the

sequencer tries to bring up the rails at the same time by assigning the same STROBE to rails in PWR_SEQ0

register, rails will be staggered in a manner that a subsequent rail’s enable is gated by PG of a preceding

rail. In this case, the default order of power-up is LDO2 (VNEG), CP2 (VEE), LDO1 (VPOS), and

CP1(VDDH). If any two PWRx pins are pulled low together or the sequencer tries to bring down the rails at

the same time by assigning the same STROBE to rails in PWR_SEQ0 register, then all rails will go down at

the same time.

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VIN

D0

PWR0

1.8ms⁽¹⁾

D1

PWR1

D2

PWR2

D3

PWR3

SLEEP

WAKEUP

STANDBY

ACTIVE

VN

VB

VNEG

DLY1

VCOM

6ms^(2,5)

DLY0 + 4ms⁽²⁾

DLY2

VEE

1ms⁽⁵⁾

DLY1

DLY3

VPOS

2ms⁽⁵⁾

DLY2

DLY0

VDDH

1ms⁽⁵⁾

DLY3

PWR_GOOD

300us (max)

11.8ms (min)

(1) Minimum delay time between WAKEUP rising edge and IC rady to accept I 2C transaction .

(2) It takes 2ms minimum for each internal boost regulator to start up before VNEG can be enabled

.

(5) It takes up to 2ms for LDOs (VPOS,VNEG) and 1ms for charge pumps (VDDH,VEE), to reach their steady state after being enabled.

DLY0-DLY3 are power up/down delays defined in register PWR _SEQ1 and PWR_SEQ2.

In this example the first power-up sequence is determined by GPIO control (WAKEUP is pulled high while PWRx pins are low).

Power-down and 2nd power-up sequence is controlled by register settings (WAKEUP pin is toggled with at least one PWR pin

held high).

Figure 3. Power-Up and Power-Down Timing Diagram

SOFTSTART

Softstart for DCDC1, DCDC2, LDO1, and LDO2 is accomplished by lowering the current limits during start-up. If

DCDC1 or DCDC2 are unable to reach power-good status within 10 ms, the corresponding UV flag is set in the

interrupt registers, the interrupt pin is pulled low, and the device enters STANDBY mode. LDO1, LDO2, positive

and negative charge pumps have a 5ms power-good time-out limit. If either rail is unable to power up within 5 ms

after it has been enabled, the corresponding UV flag is set and the interrupt pin is pulled low. However, the

device will remain in ACTIVE mode in this case.

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SLVSA76F –MARCH 2010–REVISED FEBRUARY 2011

VCOM ADJUSTMENT

Through the I²C interface the user can select between two methods of VCOM voltage adjustment:

1. Using the internal 8-bit DAC and register control.

2. Using an external voltage source (resistor divider) connected to the VCOM_XADJ pin.

VCOM ADJUSTMENT THROUGH REGISTER CONTROL

By default the TPS65180/TPS65180B is setup for internal VCOM control through the I²C interface. The default

setting for the 8-bit DAC is 0x74h which results in 1.25 V ±0.8% for VCOM. VCOM can be adjusted up or down

in

steps

of

11 mV (typ) by writing to the VCOM_ADJUST register. The output range for VCOM is limited to –0.3 V to –2.5 V.

10uF

4.7uF

VREF (2.25V)

VIN

VREF

From Input Supply

(3.0V-6.0V)

VCOM_SET[7:0]

VCOM_ADJ

4.7uF

VCOM

-0.3...-2.5V

DAC

-0.3...-2.5V

MUX

-17V

VCOM_XADJ

VCOM_PWR

VNEG

From DCDC2 (-17V)

From uC or DSP

4.7uF

VCOM_CTRL

4.7uF

GATE DRIVER

VCOM_PANEL

®

To Eiink VIXPLEX^TMPanel

Figure 4. Block Diagram of VCOM Circuit

VCOM ADJUSTMENT THROUGH EXTERNAL POTENTIOMETER

VCOM can be adjusted by an external potentiometer by setting the VCOM_ADJ bit of the VN_ADJUST register

to 0 and connecting a potentiometer to the VCOM_XADJ pin. The potentiometer must be connected between

ground and a negative supply as shown in Figure 4. The gain from VCOM_XADJ to VCOM is 1 and therefore the

voltage applied to VCOM_XADJ pin should range from –0.3 V to –2.5 V.

VPOS / VNEG SUPPLY TRACKING

LDO1 (VPOS) and LDO2 (VNEG) track each other in a way that they are of opposite sign but same magnitude.

The sum of VLDO1 and VLOD2 is guaranteed to be < 50 mV. To ensure proper tracking of the supplies the

VPOS_SET[2:0] bits of the VP_ADUST register must remain at the default setting of 010b. To adjust the

VPOS/VNEG output voltage, write to the VN_ADJUST register only and keep the VPOS_SET[2:0] bits of the

VP_ADUST register unchanged.

FAULT HANDLING AND RECOVERY

The TPS65180/TPS65181 and TPS65180B/TPS65181B monitor input and output voltages and die temperature

and will take action if operating conditions are outside normal limits. Whenever the TPS65180/TPS65181 and

TPS65180B/TPS65181B encounter:

•

Thermal Shutdown (TSD)

Positive Boost Under Voltage (VB_UV)

Inverting Buck-Boost Under Voltage (VN_UV)

Input Under Voltage Lock Out (UVLO)

it will shut down all power rails and enter STANDBY mode. Shut down follows the reverse power-up sequence

defined by the PWR_SEQx registers. Once a fault is detected, the PWR_GOOD and nINT pin are pulled low and

the corresponding interrupt bit is set in the interrupt register.

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Whenver the TPS65180/TPS65181 and TPS65180B/TPS65181B encounter under voltage on VNEG

(VNEG_UV), VPOS (VPOS_UV), VEE (VEE_UV) or VDDH (VDDH_UV) it will shut down the corresponding rail

(plus any dependent rail) only and remain in ACTIVE mode, allowing the DCDC converters to remain up. Again,

the PWR_GOOD and nINT pins will be pulled low and the corresponding interrupt bit will be set.

TPS65180/TPS65180B FAULT HANDLING

Once a fault is detected the TPS65180/TPS65180B sets the appropriate interrupt flags in the INT_STATUS1 and

INT_STATUS2 registers and pulls INT pin low to signal an interrupt to the host processor. None of the power

rails can be re-enabled before the host has read the INT_STATUSx bits and the fault has been removed. As the

PWRx inputs are edge sensitive, the host must also toggle the PWRx pins to re-enable the rails through GPIO

control, i.e. it must bring the PWRx pins low before asserting them again.

TPS65181/TPS65181B FAULT HANDLING

The TPS65181/TPS65181does not require the host processor to access the INT_STATUS registers before

re-enabling the output rails. Rails can be re-enabled as soon as the fault condition has been removed. Again, as

the PWRx inputs are edge sensitive, the host must also toggle the PWRx pins to re-enable the rails through

GPIO control, i.e. it must bring the PWRx pins low before asserting them again.

POWER GOOD PIN

The power good pin (PWR_GOOD) is an open drain output that is pulled high when all four power rails (CP1,

CP2, LDO1, LDO2) are in regulation and is pulled low if any of the rails encounters a fault. PWR_GOOD remains

low if one of the rails is not enabled by the host and only after all rails are in regulation PWR_GOOD is released

to HiZ state (pulled up by external resistor).

INTERRUPT PIN

The interrupt pin (nINT) is an open drain output that is pulled low whenever one or more of the INT_STATUS1 or

INT_STATUS2 bits are set. The nINT pin is released (returns to HiZ state) and fault bits are cleared once the

register with the set bit has been read by the host. If the fault persists, the INT_pin will be pulled low again after a

maximum of 32 µs.

Interrupt events can be masked by re-setting the corresponding enable bit in the INT_ENABLE1 and

INT_ENABLE2 register, i.e. the user can determine which events cause the nINT pin to be pulled low. The status

of the enable bits affects the nINT pin only and has no effect on any of the protection and monitoring circuits or

the INT_STATUSx bits themselves.

Note that persisting fault conditions such as thermal shutdown can cause the nINT pin to be pulled low for an

extended period of time which can keep the host in a loop trying to resolve the interrupt. If this behavior is not

desired, set the corresponding mask bit after receiving the interrupt and keep polling the INT_STATUSx register

to see when the fault condition has disappeared. After the fault is resolved, unmask the interrupt bit again.

PANEL TEMPERATURE MONITORING

The TPS65180/TPS65181 and TPS65180B/TPS65181B provide circuitry to bias and measure an external

negative temperature coefficient resistor (NTC) to monitor device temperature in a range from –10°C to 85°C

with and accuracy of ±1°C from 0°C to 50°C. The TPS65180/TPS65180B requires the host to trigger the

temperature acquisition through an I²C command whereas the TPS65181/TPS65181B triggers the temperature

acquisition automatically once every 60 s.

NTC BIAS CIRCUIT

Figure 5 below shows the block diagram of the NTC bias and measurement circuit. The NTC is biased from an

internally generated 2.25-V reference voltage through an integrated 7.307-kΩ bias resistor. A 43-kΩ resistor is

connected parallel to the NTC to linearize the temperature response curve. The circuit is designed to work with a

nominal 10-kΩ NTC and achieves accuracy of ±1°C from 0°C to 50°C. The voltage drop across the NTC is

digitized by a 10-bit SAR ADC and translated into an 8-bit two’s complement by digital per Table 1.

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SLVSA76F –MARCH 2010–REVISED FEBRUARY 2011

Table 1. ADC Output Value vs Termperature

TEMPERATURE

TMST_VALUE[7:0]

1111 0110

1111 0111

...

< -10°C

-10°C

-9°C

...

-2°C

-1°C

0°C

1111 1110

1111 1111

0000 0000

0000 0001

0000 0010

...

1°C

2°C

...

25°C

...

0001 1001

85°C

> 85°C

0101 0101

2.25V

7.307kW

10

Digital

10 bit ADC

43kW

10 kW NTC

TPS6518x

Figure 5. NTC Bias and Measurement Circuit

TPS65180/TPS65180B TEMPERATURE ACQUISITION

The TPS65180/TPS65180B requires the host to trigger the temperature acquisition before reading the

temperature value from register TMST_VALUE. A standard temperature measurement involves the following

steps:

1. The host sets the READ_THERM bit of the TMST_CONFIG register to 1. This enabled the NTC bias circuit

and internal ADC.

2. The analog to digital conversion is automatically started after a fixed 250-µs delay. While the conversion is in

progress the CONV_END bit of the TMST_CONFIG register is held low and returns to 1 after the conversion

result is available.

3. After the conversion is complete the READ_THERM bit is automatically reset, the EOC bit of the

INT_STATUS2 register is set, and the interrupt pin (nINT) is pulled low.

4. The host services the interrupt by reading the INT_STATUS2 register. This clears the interrupt pin (nINT pin

returns high). The host sees the EOC bit set and knows that the temperature data is available in the

TMST_VALUE register.

5. The host reads the temperature data from the TMST_VALUE register.

TPS65181/TPS65181B TEMPERATURE ACQUISITION

The TPS65181/TPS65181B triggers temperature acquisition once every 60s to reduce the number of required

I²C writes. The host or display timing controller can read the temperature at any time by accessing the

TMST_VALUE register without having to set the READ_THERM bit first. However, the host can always trigger an

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additional temperature reading the same way as for the TPS65180/TPS65180B. Please note that at the end of

each temperature acquisition the EOC interrupt will be set and an interrupt will be issued. Although the interrupt

is automatically cleared, the nINT pin will be pulled low for a short amount of time (6 µs). To avoid seeing the

EOS interrupt every 60s it is recommended to mask the EOC interrupt by setting the EOC_EN bit of the

INT_ENABLE2 register to 0.

OVER TEMPERATURE REPORTING

The user has the option of setting HOT and COOL (not HOT) temperature thresholds as well as controlling

interrupt behavior as the NTC exceeds HOT and cools down below COOL (not-HOT) threshold.

By default, TPS65180/TPS65181 and TPS65180B/TPS65181B compare the temperature conversion result to the

HOT threshold after each conversion. If the NTC temperature is above the HOT threshold, the TMST_HOT bit in

the INT_STATUS1 register is set to 1 and the interrupt pin (nINT) is pulled low. HOT temperature threshold is set

by the host by writing to the TMST_OS register and the HOT interrupt can be disabled by setting the HOT_EN bit

of the INT_ENABLE1 register to 0.

Once the device has detected that the NTC is above the HOT threshold it will compare subsequent temperature

acquisitions against the COOL threshold and pull the interrupt pin low when the NTC temperature drops below

the COOL threshold. However, the interrupt will be issued only if the host has unmasked the COOL interrupt by

setting TMST_COOL_EN bit of INT_ENABLE1 register to 1. The COOL threshold is set by the host by writing to

the TMST_HYST register.

To use the full functionality of the HOT/COOL interrupts the following actions are required:

1. The host sets the HOT and COOL (not HOT) thresholds by writing the TMST_OS and TMST_HYST

registers.

2. (2) For TPS65180/TPS65180B only: The host sets the READ_THERM bit of the TMST_CONFIG register to

‘1’. This initiates the temperature acquisition.

3. TPS65180/TPS65181 and TPS65180B/TPS65181B compare the result against the TMST_OS threshold and

will pull the nINT pin low if the NTC temperature exceeds the HOT threshold.

4. If the TPS65180/TPS65181 and TPS65180B/TPS65181B report a HOT condition, the host unmasks the

TMST_COOL_EN bit by setting it to 1 (INT_ENABLE1 register).

5. The host initiates a new temperature conversion by setting the READ_THERM bit of the TMST_CONFIG

register to 1. If the new temperature is still above the HOT threshold, a new HOT interrupt will be issued. If

the temperature is below HOT but above COOL threshold, no interrupt is issued (except for EOC which is

issued at the end of each conversion). If the temperature is below COOL threshold, a COOL interrupt is

issued.

6. After the temperature drops below the COOL threshold the host should set the TMST_COOL_EN bit in the

INT_ENABLE1 register to 0 to mask additional COOL interrupts after subsequent temperature acquisitions.

OVER-TEMPERATURE FAULT QUEUING

The user can specify the number of consecutive HOT temperature reads required to issue a HOT interrupt. The

user can set the FAULT_QUE[1:0] bits of the TMST_CONFIG register to specify 1, 2, 4, or 6 consecutive reads

that all must be above the HOT threshold before a HOT interrupt is issued. The fault queue is reset each time

the acquired temperature drops below the HOT threshold and can also be reset by the host by setting the

FAULT_QUE_CLR bit 1. Only if the specified number of readings have been detected which all need to be above

the HOT threshold, a HOT interrupt is issued. This function is useful to reduce noise in the temperature

measurements.

TPS65181/TPS65181B TEMPERATURE SENSOR

The TPS65181/TPS65181B automates the temperature monitoring process and is specifically designed to

operate in multi-host systems where one of the I²C hosts, e.g. the display controller, has limited I²C capability.

Standard I²C protocol requires the following steps to read data from a register:

1. Send device and register address, R/nW bit set low (write command).

2. Send device address, R/nW set high (read command).

3. The slave will respond with data from the specified register address.

Some display controllers support I²C read commands only and need to access the temperature data from the

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TPS65181/TPS65181B TMST_VALUE register. To support these systems the TPS65181/TPS65181B

automatically triggers temperature acquisition every 60s (for other acquisition intervals contact the factory) and

stores the result in TMST_VALUE register. With the FIX_RD_PTR bit in the FIX_RD_POINTER register set to 1

the device will respond to any I²C read command with data from the TMST_VALUE register. No write command

with the register address is required and address auto increment feature is disabled in this mode. Therefore

reading the temperature data is reduced to two steps:

1. Send device address, R/nW set high (read command).

2. Read the data from the slave. The slave will respond with data from TMST_VALUE register address.

Write functionality is not affected by the FIX_RD_PTR bit and the main controller in the system maintains full

control of the PMIC. Interrupts and error flags are issued and need to be handled the same way as for the

TPS65180/TPS65180B with two exceptions:

1. The FIX_RD_PTR bit in the FIX_RD_POINTER register needs to be set to 0 before the main controller can

read any register different from the TMST_VALUE register.

2. Thermal shutdown (TSD), positive boost under voltage (VB_UV), inverting buck-boost under voltage

(VN_UV), and input under voltage lock out (UVLO) interrupt bits do not have to be cleared before output rails

can be re-enabled.

At system power-up the main processor sets up the PMIC by accessing the I²C registers and setting the control

parameters as needed. When the system is setup correctly the main controller sets the FIX_READ_POINTER bit

and the display controller can start accessing the temperature information. During normal operation the main

controller can write to the PMIC at any time but before it can read access registers the FIX_READ_POINTER bit

must be written 0.

The temperature range and representation of the temperature data is the same between the

TPS65180/TPS65180B and TPS65181/TPS65181B.

THE FIX_RD_PTR BIT

The TPS65181/TPS65181B supports a special I²C mode making it compatible with the EPSON Broadsheet

S1D13521 timing controller. Standard I²C protocol requires the following steps to read data from a register:

1. Send device slave address, R/nW bit set low (write command)

2. Send register address

3. Send device slave address, R/nW set high (read command)

4. The slave will respond with data from the specified register address.

The EPSON Broadsheet S1D13521 controller does not support I²C writes nor I²C reads from addressed

registers (step 1. and 2. above) but needs to access the temperature data from the TPS65181/TPS65181B’s

TMST_VALUE register. To support Broadsheet based systems, the TPS65181/TPS65181B automatically

triggers temperature acquisition every 60s and stores the result in TMST_VALUE register. With the FIX_RD_PTR

bit in the FIX_RD_POINTER register set to 1 the device will respond to any I²C read command with data from

the TMST_VALUE register. No write command with the register address is required and address auto increment

feature is disabled in this mode. Therefore reading the temperature data is reduced to two steps:

1. Send device address, R/nW set high (read command)

2. Read the data from the slave. The slave will respond with data from TMST_VALUE register address.

Write functionality is not affected by the FIX_RD_PTR bit and the main controller in the system maintains full

control of the PMIC. Interrupts and error flags are issued and need to be handled the same way as for the

TPS65180/TPS65180B with two exceptions:

1. The FIX_RD_PTR bit in the FIX_RD_POINTER register needs to be set to 0 before the main controller can

read any register different from the TMST_VALUE register.

2. Thermal Shutdown (TSD), positive boost Under Voltage (VB_UV), inverting buck-boost Under Voltage

(VN_UV), and input Under Voltage Lock Out (UVLO) interrupt bits do not have to be cleared before output

rails can be re-enabled.

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At system power-up the main processor sets up the PMIC by accessing the I²C registers and setting the control

parameters as needed. When the system is setup correctly the main controller sets the FIX_READ_POINTER bit

and the display controller can start accessing the temperature information. During normal operation the main

controller can write to the PMIC at any time but before it can read access registers the FIX_READ_POINTER bit

must be written 0.

I²C BUS OPERATION

The TPS65180/TPS65181 and TPS65180B/TPS65181B host a slave I²C interface that supports data rates up to

400 kbit/s and auto-increment addressing and is compliant to I²C standard 3.0.

Slave Address + R/nW

Sub Address

Data

R/nW

S

A6 A5 A4 A3 A2 A1 A0

A

S7 S6 S5 S4 S3 S2 S1 S0

A

D7 D6 D5 D4 D3 D2 D1 D0

A

P

S

Start Condition

Read / not Write

A

P

Acknowledge

A6 ... A0 Device Address

S7 ... S0 Sub-Address

D7 ... D0 Data

R/nW

Stop Condition

Figure 6. Subaddress in I²C Transmission

Start – Start condition

G(3:0) – Group ID: Address fixed at 1001.

ACK – Acknowledge

S(7:0) – Subaddress: defined per register map.

A(2:0) – Device Address: Address fixed at 000.

R/nW – Read / not Write Select Bit

D(7:0) – Data; Data to be loaded into the device.

Stop – Stop condition

The I²C Bus is a communications link between a controller and a series of slave terminals. The link is established

using a two-wired bus consisting of a serial clock signal (SCL) and a serial data signal (SDA). The serial clock is

sourced from the controller in all cases where the serial data line is bi-directional for data communication

between the controller and the slave terminals. Each device has an open Drain output to transmit data on the

serial data line. An external pull-up resistor must be placed on the serial data line to pull the drain output high

during data transmission.

Data transmission is initiated with a start bit from the controller as shown in Figure 8. The start condition is

recognized when the SDA line transitions from high to low during the high portion of the SCL signal. Upon

reception of a start bit, the device will receive serial data on the SDA input and check for valid address and

control information. If the appropriate group and address bits are set for the device, then the device will issue an

acknowledge pulse and prepare the receive subaddress data. Subaddress data is decoded and responded to as

per the Register Map section of this document. Data transmission is completed by either the reception of a stop

condition or the reception of the data word sent to the device. A stop condition is recognized as a low to high

transition of the SDA input during the high portion of the SCL signal. All other transitions of the SDA line must

occur during the low portion of the SCL signal. An acknowledge is issued after the reception of valid address,

sub-address and data words. The I²C interface will auto-sequence through register addresses, so that multiple

data words can be sent for a given I²C transmission. Reference Figure 8. Please note that auto-increment is not

supported when the FIX_RD_PTR bit is set (TPS65181/TPS65181B only).

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SLVSA76F –MARCH 2010–REVISED FEBRUARY 2011

S

SLAVE ADDRESS

W A

SUB ADDRESS

A

S

SLAVE ADDRESS

R

A

DATA _SUBADDR

A

Ā

DATA _{SUBADDR +n}

n bytes + ACK

DATA _{SUBADDR +n+1}

P

S

SLAVE ADDRESS

R

A

DATA₀

A

DATA₀

A

DATA₀

Ā

P

n bytes + ACK

From master to slave

From slave to master

R Read

S Start

P Stop

Ā

Not Acknowlege

W Write (not read)

A Acknowlege

Figure 7. TOP: Standard I²C READ data transmission with address auto-increment. Bottom: I²C READ

data transmission with FIX_RD_PTR bit set for EPSON Broadsheet support. Only address 0x00h can be

read. FIX_RD_PTR bit has no impact on WRITE transaction.

SDA

SCL

1-7

8

9

1-7

8

9

1-7

8

9

S

P

START

ADDRESS R/W ACK

DATA

ACK

DATA

STOP

ACK/

nACK

Figure 8. I²C Start/Stop/Acknowledge Protocol

SDA

SCL

t_SU;DAT

t_f

t_LOW

t_r

t_HD;STA

t_SP

t_r

t_BUF

t_HD;STA

t_SU;STA

t_SU;STO

t_f

t_HD;DATt_HIGH

S

S_r

P

S

Figure 9. I²C Data Transmission Timing

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DATA TRANSMISSION TIMING

V_BAT= 3.6 V ±5%, T_A= 25ºC, C_L= 100 pF (unless otherwise noted)

PARAMETER

Serial clock frequency

TEST CONDITIONS

MIN

100

TYP

MAX

UNIT

400 KHz

µs

f_(SCL)

SCL = 100 KHz

SCL = 400 KHz

SCL = 100 KHz

SCL = 400 KHz

SCL = 100 KHz

SCL = 400 KHz

SCL = 100 KHz

SCL = 400 KHz

SCL = 100 KHz

SCL = 400 KHz

SCL = 100 KHz

SCL = 400 KHz

SCL = 100 KHz

SCL = 400 KHz

SCL = 100 KHz

SCL = 400 KHz

SCL = 100 KHz

SCL = 400 KHz

SCL = 100 KHz

SCL = 400 KHz

SCL = 100 KHz

SCL = 400 KHz

SCL = 100 KHz

SCL = 400 KHz

4

600

4.7

1.3

4

Hold time (repeated) START condition. After this

period, the first clock pulse is generated.

t_HD;STA

ns

t_LOW

t_HIGH

t_SU;STA

t_HD;DAT

t_SU;DAT

t_r

LOW period of the SCL clock

µs

ns

µs

ns

HIGH period of the SCL clock

Set-up time for a repeated START condition

Data hold time

600

4.7

600

0

3.45

900

µs

0

ns

250

100

Data set-up time

ns

1000

300

Rise time of both SDA and SCL signals

Fall time of both SDA and SCL signals

Set-up time for STOP condition

Bus Free Time Between Stop and Start Condition

t_f

4

600

4.7

1.3

n/a

0

µs

t_SU;STO

t_BUF

t_SP

ns

µs

ns

pF

n/a

50

Pulse width of spikes which mst be suppressed

by the input filter

400

C_b

Capacitive load for each bus line

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SLVSA76F –MARCH 2010–REVISED FEBRUARY 2011

REGISTER ADDRESS MAP

DEFAULT

DESCRIPTION

VALUE

REGISTER

ADDRESS (HEX)

NAME

0

1

0x00

0x01

0x02

0x03

0x04

0x05

0x06

0x07

0x08

0x09

0x0A

0x0B

0x0C

0x0D

0x0E

0x0F

0x10

0x11

TMST_VALUE

ENABLE

N/A

Thermistor value read by ADC

Enable/disable bits for regulators

Voltage settings for VPOS, VDDH

Voltage settings for VNEG, VEE

Voltage settings for VCOM

Interrupt enable group1

0001 1111

0010 0011

1010 0011

0111 0100

1111 1011

0xxx xx00

xxxx x0xx

1110 0100

0010 0010

0010 0000

0011 0010

0010 1101

0000 0000

0100 0001

0000 0000

2

VP_ADJUST

VN_ADJUST

VCOM_ADJUST

INT_ENABLE1

INT_ENABLE2

INT_STATUS1

INT_STATUS2

PWR_SEQ0

3

4

5

6

Interrupt enable group2

7

Interrupt status group1

8

Interrupt status group2

9

Power up sequence

10

11

12

13

14

15

16

17

PWR_SEQ1

DLY0, DLY1 time set

PWR_SEQ2

DLY2, DLY3 time set

TMST_CONFIG

TMST_OS

Thermistor configuration

Thermistor hot temp set

Thermistor cool temp set

Power good status each rails

Device revision ID information

I²C read pointer control

TMST_HYST

PG_STATUS

REVID

FIX_READ_POINTER

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THERMISTOR READOUT (TMST_VALUE)

Address – 0x00h

DATA BIT

FIELD NAME

READ/WRITE

RESET VALUE

D7

D6

D5

D4

D3

D2

D1

D0

TMST_VALUE[7:0]

R

N/A

FIELD NAME

BIT DEFINITION

Temperature read-out

1111 0110 – < -10°C

1111 0110 – -10°C

1111 0111 – -9°C

...

1111 1110 – -2°C

1111 1111 – -1 °C

0000 0000 – 0 °C

0000 0001 – 1°C

0000 0010 – 2°C

...

TMST_VALUE[7:0]

0001 1001 – 25°C

...

0101 0101 – 85°C

0101 0101 – > 85°C

ENABLE (ENABLE)

Address – 0x01h

DATA BIT

D7

D6

D5

D4

D3

D2

D1

D0

V3P3_SW

_EN

FIELD NAME

ACTIVE

STANDBY

VCOM_EN VDDH_EN

VPOS_EN

VEE_EN

VNEG_EN

READ/WRITE

R/W

0

R/W

0

R/W

0

R/W

1

R/W

1

R/W

1

R/W

1

R/W

1

RESET VALUE

FIELD NAME

BIT DEFINITION⁽¹⁾

STANDBY to ACTIVE transition bit

1 – Transition from STANDBY to ACTIVE mode. Rails power up as defined by PWR_SEQx registers.

ACTIVE

0 – No effect

NOTE: After transition bit is cleared automatically.

ACTIVE to STANDBY transition bit

1 – Transition from ACTIVE to STANDBY mode. Rails power down as defined by PWR_SEQx

registers.

STANDBY

0 – No effect

NOTE: After transition bit is cleared automatically. STANDBY bit has priority over AVTIVE.

VIN3P3 to V3P3 switch enable

1 – Switch is ON

V3P3_SW_EN

VCOM_EN

0 – Switch id OFF

VCOM buffer enable

1 – Enabled

0 – Disabled

(1) Enable/disable bits for regulators are AND’d with PWRx signals.

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FIELD NAME

BIT DEFINITION⁽¹⁾

VDDH charge pump enable

1 – Enabled

VDDH_EN

0 – Disabled

VPOS LDO regulator enable

1 – Enabled

VPOS_EN

VEE_EN

0 – Disabled

NOTE: VPOS cannot be enabled before VNEG is enabled.

VEE charge pump enable

1 – Enabled

0 – Disabled

VNEG LDO regulator enable

1 – Enabled

VNEG_EN

0 – Disabled

NOTE: When VNEG is disabled VPOS will also be disabled.

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POSITIVE VOLTAGE RAIL ADJUSTMENT (VP_ADJUST)

Address – 0x02h

DATA BIT

FIELD NAME

READ/WRITE

RESET VALUE

D7

D6

D5

D4

D3

D2

D1

D0

Not used

VDDH_SET[2:0]

not used

VPOS_SET[2:0]

R

0

R/W

0

R/W

1

R/W

0

R

0

R/W

0

R/W

1

R/W

1

FIELD NAME

BIT DEFINITION⁽¹⁾

Not used

N/A

VDDH voltage setting

000 – VDDH increase by 10%

001 – VDDH increase by 5%

010 – Nominal

VDDH_SET[2:0]

011 – VDDH decrease by 5%

100 – VDDH decrease by 10%

101 – Reserved

110 – Reserved

111 – Reserved

Not used

N/A

VPOS voltage setting

000 : |VNEG| - 0.75 V

001 : |VNEG| - 0.5 V

010 : |VNEG| - 0.25 V

011 : |VNEG|

100 : |VNEG| + 0.25 V

101 : |VNEG| + 0.5 V

110 : |VNEG| + 0.75 V

111 – Reserved

VPOS_SET[2:0]

NOTE: For proper tracking of the VPOS and VNEG supply these bits must remain set at their default

value of 011b. VPOS will track VNEG automatically when VNEG_SET[2:0] bits of VN_ADJUST

register are changed.

(1) VDDH will be decreased from set value defined by resistor divider. Decreased VDDH value should be within spec range.

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NEGATIVE VOLTAGE RAIL ADJUSTMENT (VN_ADJUST)

Address – 0x03h

DATA BIT

FIELD NAME

READ/WRITE

RESET VALUE

D7

VCOM_ADJ

R/W

D6

D5

D4

D3

D2

D1

D0

VEE_SET[2:0]

Not used

VNEG_SET[2:0]

R/W

0

R/W

1

R/W

0

R

0

R/W

0

R/W

1

R/W

1

1⁽¹⁾

(1) TPS65180/TPS65180B: Bit defaults to 1; TPS65181/TPS65181B: Bit defaults to 0

FIELD NAME

BIT DEFINITION

VCOM output adjustment method

0 – VCOM_XADJ pin

1 – I²C interface

VCOM_ADJ

VDDH voltage setting

000 – VEE decrease by 10%

001 – VEE decrease by 5%

010 – Nominal

VEE_SET[2:0]⁽¹⁾

011 – VEE increase by 5%

100 – VEE increase by 10%

101 – Reserved

110 – Reserved

111 – Reserved

not used

N/A

VNEG voltage setting

000 – -15.75 V

001 – -15.50 V

010 – -15.25 V

VNEG_SET[2:0]

011 – -15.00 V

100 – -14.75 V

101 – -14.50 V

110 – -14.25 V

111 – Reserved

(1) VEE will be decreased from set value defined by resistor divider. Decreased VEE value should be within spec range.

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VCOM ADJUSTMENT (VCOM_ADJUST)

Address – 0x04h

DATA BIT

FIELD NAME

READ/WRITE

RESET VALUE

D7

D6

D5

D4

D3

D2

D1

D0

VCOM_SET[7:0]

R/W

0

R/W

1

R/W

1

R/W

1

R/W

0

R/W

1

R/W

0

R/W

0

FIELD NAME

BIT DEFINITION

VCOM voltage adjustment

0000 0000 – 0 V

0000 0001 – 11 mV

0000 0010 – 22 mV

...

0111 0011 – 1239 mV

0111 0100 – 1250 mV

0111 0101 – 1261 mV

...

VCOM_SET[7:0]

1111 1111 – 2750 mV

NOTE: step size is rounded to 11 mV. Theoretical step size is 2750 mV / 255 mV = 10.78 mV.

Parametric performance is guranteed from -0.3 V to -2.5 V only.

INTERRUPT ENABLE 1 (INT_ENABLE1)

Address – 0x05h

DATA BIT

D7

D6

D5

D4

D3

D2

D1

D0

TMST_HOT TMST_COOL

FIELD NAME

Not used

TSD_EN

HOT_EN

UVLO_EN Not used

Not used

_EN

R/W

1

_EN

R/W

0

READ/WRITE

R

0

R/W

1

R/W

1

R/W

1

R

0

R

0

RESET VALUE

FIELD NAME

BIT DEFINITION

Not used

N/A

Thermal shutdown interrupt enable

1 – Enabled

TSD_EN

HOT_EN

0 – Disabled

Thermal shutdown early warning enable

1 – Enabled

0 – Disabled

Thermistor hot warning enable

TMST_HOT_EN

TMST_COOL_EN

UVLO_EN

1 – Enabled

0 – Disabled

Thermistor hot escape interrupt enable

1 – Enabled

0 – Disabled

VIN under voltage detect interrupt enable

1 – Enabled

0 – Disabled

N/A

Not used

N/A

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INTERRUPT ENABLE 2 (INT_ENABLE2)

Address – 0x06h

DATA BIT

D7

D6

D5

D4

D3

D2

D1

D0

VDDH_UV

_EN

VPOS_UV

_EN

VEE_UV

_EN

VNEG_UV

_EN

FIELD NAME

VB_UV_EN

VN_UV_EN

not used

EOC_EN

READ/WRITE

R/W

1

R/W

1

R/W

1

R/W

1

R/W

1

R

0

R/W

1

R/W

1

RESET VALUE

FIELD NAME

BIT DEFINITION

Positive boost converter under voltage detect interrupt enable

VB_UV_EN

1 – Enabled

0 – Disabled

VDDH under voltage detect interrupt enable

VDDH_UV_EN

VN_UV_EN

1 – Enabled

0 – Disabled

Inverting buck-boost converter under voltage detect interrupt enable

1 – Enabled

0 – Disabled

VPOS under voltage detect interrupt enable

VPOS_UV_EN

1 – Enabled

0 – Disabled

VEE under voltage detect interrupt enable

VEE_UV_EN

not used

1 – Enabled

0 – Disabled

N/A

VNEG under voltage detect interrupt enable

1 – Enabled

VNEG_UV_EN

0 – Disabled

ADC end of conversion interrupt enable

1 – Enabled

EOC_EN

0 – Disabled

INTERRUPT INT_STATUS1 (INT_STATUS1)

Address – 0x07h

DATA BIT

FIELD NAME

READ/WRITE

RESET VALUE

D7

D6

TSDN

R

D5

HOT

R

D4

D3

D2

UVLO

R

D1

D0

Not used

TMST_HOT TMST_COOL

Not used

R

0

R

0

R

0

N/A

FIELD NAME

Not used

TSD

BIT DEFINITION

N/A

Thermal shutdown interrupt

Thermal shutdown early warning

Thermistor hot warning

Thermistor hot escape interrupt

VIN under voltage detect interrupt

N/A

HOT

TMST_HOT

TMST_COOL

UVLO

Not used

N/A

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INTERRUPT STATUS 2 (INT_STATUS2)

Address – 0x08h

DATA BIT

FIELD NAME

READ/WRITE

RESET VALUE

D7

VB_UV

R

D6

VDDH_UV

R

D5

VN_UV

R

D4

VPOS_UV

R

D3

VEE_UV

R

D2

D1

VNEG_UV

R

D0

EOC

R

Not used

R

0

N/A

FIELD NAME

VB_UV

BIT DEFINITION⁽¹⁾

Positive boost converter under voltage detect interrupt

VDDH under voltage detect interrupt

Inverting buck-boost converter under voltage detect interrupt

VPOS under voltage detect interrupt

VEE under Voltage detect interrupt

N/A

VDDH_UV

VN_UV

VPOS_UV

VEE_UV

not used

VNEG_UV

EOC

VNEG under voltage detect interrupt

ADC end of conversion interrupt

(1) Under voltage detect bit is set if the corresponding rail does not come up 5 ms after it is enabled except for DCDC1 and 2 which are set

10 ms after they are enabled.

POWER SEQUENCE REGISTER 0 (PWR_SEQ0)

Address – 0x09h

DATA BIT

FIELD NAME

READ/WRITE

RESET VALUE

D7

D6

D5

D4

D3

VEE_SEQ[1:0]

R/W R/W

D2

D1

D0

VDDH_SEQ[1:0]

VPOS_SEQ[1:0]

VNEG_SEQ[1:0]

R/W

1

R/W

1

R/W

1

R/W

0

R/W

0

R/W

0

1

FIELD NAME

BIT DEFINITION⁽¹⁾

VDDH power-up/down order

00 – Power-up/down on STROBE1

01 – Power-up/down on STROBE2

10 – Power-up/down on STROBE3

11 – Power-up/down on STROBE4

VPOS power-up/down order

VDDH_SEQ[1:0]

00 – Power-up/down on STROBE1

01 – Power-up/down on STROBE2

10 – Power-up/down on STROBE3

11 – Ppower-up/down on STROBE4

VEE power-up/down order

VPOS_SEQ[1:0]

VEE_SEQ[1:0]

VNEG_SEQ[1:0]

00 – Power-up/down on STROBE1

01 – Power-up/down on STROBE2

10 – Power-up/down on STROBE3

11 – Power-up/down on STROBE4

VNEG power-up/down order

00 – Power-up/down on STROBE1

01 – Power-up/down on STROBE2

10 – Power-up/down on STROBE3

11 – Power-up/down on STROBE4

(1) Power-down sequence follows the reverse order of power-up.

30

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TPS65180, TPS65181, TPS65180B, TPS65181B

www.ti.com

SLVSA76F –MARCH 2010–REVISED FEBRUARY 2011

POWER SEQUENCE REGISTER 1 (PWR_SEQ1)

Address – 0x0Ah

DATA BIT

FIELD NAME

READ/WRITE

RESET VALUE

D7

D6

D5

D4

D3

D2

D1

D0

DLY1[3:0]

DLY0[3:0]

R/W

0

R/W

0

R/W

1

R/W

0

R/W

0

R/W

0

R/W

1

R/W

0

FIELD NAME

BIT DEFINITION

DLY1 delay time set; defines the delay time from STROBE1 to STROBE2 during power-up and from

STROBE2 to STROBE1 during power-down.

0000 – 0 ms

0001 – 1 ms

0010 – 2 ms

0011 – 3 ms

...

DLY1[3:0]

1110 – 14 ms

1111 – 15 ms

DLY0 delay time set; defines the delay time from WAKEUP high to STROBE1 during power-up and

from WAKEUP low to STROBE4 during power-down.

0000 – 0 ms

0001 – 1 ms

0010 – 2 ms

0011 – 3 ms

...

DLY0[3:0]

1110 – 14 ms

1111 – 15 ms

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31

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SLVSA76F –MARCH 2010–REVISED FEBRUARY 2011

www.ti.com

POWER SEQUENCE REGISTER 2 (PWR_SEQ2)

Address – 0x0Bh

DATA BIT

FIELD NAME

READ/WRITE

RESET VALUE

D7

D6

D5

D4

D3

D2

D1

D0

DLY3[3:0]

DLY2[3:0]

R/W

0

R/W

0

R/W

1

R/W

0

R/W

0

R/W

0

R/W

1

R/W

0

FIELD NAME

BIT DEFINITION

DLY3 delay time set; defines the delay time from STROBE3 to STROBE4 during power-up and from

STROBE4 to STROBE3 during power-down.

0000 – 0 ms

0001 – 1 ms

0010 – 2 ms

0011 – 3 ms

...

DLY3[3:0]

1110 – 14 ms

1111 – 15 ms

DLY2 delay time set; defines the delay time from STROBE2 to STROBE3 during power-up and from

STROBE3 to STROBE2 during power-down.

0000 – 0 ms

0001 – 1 ms

0010 – 2 ms

0011 – 3 ms

...

DLY2[3:0]

1110 – 14 ms

1111 – 15 ms

32

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SLVSA76F –MARCH 2010–REVISED FEBRUARY 2011

THERMISTOR CONFIGURATION REGISTER (TMST_CONFIG)

Address – 0x0Ch

DATA BIT

D7

D6

D5

D4

D3

D2

D1

D0

READ_

THERM

FAULT_QUE

_CLR

FIELD NAME

Not used CONV_END

FAULT_QUE [1:0]

Not used

READ/WRITE

R/W

0

R

0

R

1

R/W

0

R/W

0

R/W

0

R

0

R

0

RESET VALUE

FIELD NAME

BIT DEFINITION

Read thermistor value

1 – Initiates temperature acquisition

0 – No effect

READ_THERM

NOTE: bit is self-cleared after acquisition is completed

N/A

Not used

ADC conversion done flag

1 – Conversion is finished

0 – Conversion is not finished

CONV_END

Number of faults to detect before TMST_HOT interrupt is asserted

00 – 1 time

FAULT_QUE [1:0]

01 – 2 times

10 – 4 times

11 – 6 times

Fault counter clear

1 – Clears fault counter

FAULT_QUE_CLR

0 – Fault counter is cleared automatically if thermistor reading is less than TMST_HOT_SET[7:0]

Not used

N/A

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33

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SLVSA76F –MARCH 2010–REVISED FEBRUARY 2011

www.ti.com

THERMISTOR HOT THRESHOLD (TMST_OS)

Address – 0x0Dh

DATA BIT

FIELD NAME

READ/WRITE

RESET VALUE

D7

D6

D5

D4

D3

D2

D1

D0

TMST_HOT_SET[7:0]

R/W

0

R/W

0

R/W

1

R/W

1

R/W

0

R/W

0

R/W

1

R/W

0

FIELD NAME

BIT DEFINITION

Defined the thermistor HOT threshold

1000 0000 – Reserved

...

1111 0101 – Reserved

1111 0110 – -10°C

1111 0111 – -9°C

...

1111 1110 – -2°C

1111 1111 – -1°C

0000 0000 – 0°C

0000 0001 – 1°C

0000 0010 – 2°C

...

TMST_HOT_SET[7:0]

0001 1001 – 25°C

...

0011 0010 – 50°C

...

0101 0101 – 85°C

0101 0110 – Reserved

...

0111 1111 – Reserved

34

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SLVSA76F –MARCH 2010–REVISED FEBRUARY 2011

THERMISTOR COOL THRESHOLD (TMST_HYST)

Address – 0x0Eh

DATA BIT

FIELD NAME

READ/WRITE

RESET VALUE

D7

D6

D5

D4

D3

D2

D1

D0

TMST_COOL_SET[7:0]

R/W

0

R/W

0

R/W

1

R/W

0

R/W

1

R/W

1

R/W

0

R/W

1

FIELD NAME

BIT DEFINITION

Defined the thermistor HOT threshold

1000 0000 – Reserved

...

1111 0101 – Reserved

1111 0110 – -10°C

1111 0111 – -9°C

...

1111 1110 – -2°C

1111 1111 – -1°C

0000 0000 – 0°C

0000 0001 – 1°C

0000 0010 – 2°C

...

TMST_HOT_SET[7:0]

0001 1001 – 25°C

...

0010 1101 – 45°C

...

0101 0101 – 85°C

0101 0110 – Reserved

...

0111 1111 – Reserved

POWER GOOD STATUS (PG_STATUS)

Address – 0x0Fh

DATA BIT

FIELD NAME

READ/WRITE

RESET VALUE

D7

D6

D5

D4

D3

D2

D1

D0

VB_PG

VDDH_PG

VN_PG

VPOS_PG

VEE_PG

Not used VNEG_PG Not used

R

0

R

0

R

0

R

0

R

0

R

0

R

0

R

0

FIELD NAME

VB_PG

BIT DEFINITION

Positive boost converter power good

VDDH power good

Inverting buck-boost power good

VPOS power good

VEE power good

VDDH_PG

VN_PG

VPOS_PG

VEE_PG

not used

N/A

VNEG_PG

not used

VNEG power good

N/A

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35

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TPS65180, TPS65181, TPS65180B, TPS65181B

SLVSA76F –MARCH 2010–REVISED FEBRUARY 2011

www.ti.com

REVISION AND VERSION CONTROL (REVID)

Address – 0x10h

DATA BIT

FIELD NAME

READ/WRITE

RESET VALUE

D7

D6

D5

D4

D3

D2

D1

D0

REVID[7:0]

R

0

R

1

R

1

R

1

R

0

R

0

R

0

R

0

FIELD NAME

BIT DEFINITION

0101 0000 - TPS65180 1p1

0110 0000 - TPS65180 1p2

0111 0000 - TPS65180B (TPS65180 1p3)

1000 0000 - TPS65180B (TPS65180 1p4)

0101 0001 - TPS65181 1p1

REVID [7:0]

0110 0001 - TPS65181 1p2

0111 0001 - TPS65181B (TPS65181 1p3)

1000 0001 - TPS65181B (TPS65181 1p4)

I²C READ POINTER CONTROL (FIX_READ_POINTER) (TPS65181/TPS65181B ONLY)

Address – 0x11h

DATA BIT

FIELD NAME

READ/WRITE

RESET VALUE

D7

D6

D5

D4

D3

D2

D1

D0

Not used

FIX_RD_PTR

R

0

R

0

R

0

R

0

R

0

R

0

R

0

R/W

0

FIELD NAME

Not used

BIT DEFINITION

N/A

I²C read pointer control

FIX_RD_PTR

1 – Read pointer is fixed to 0x00

0 – read pointer is controlled through I²C

36

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PACKAGE MATERIALS INFORMATION

www.ti.com

15-Jun-2011

TAPE AND REEL INFORMATION

*All dimensions are nominal

Device

Package Package Pins

Type Drawing

SPQ

Reel

A0

B0

K0

P1

W

Pin1

Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant

(mm) W1 (mm)

TPS65180BRGZR

TPS65180BRGZT

TPS65180RGZR

TPS65180RGZT

TPS65181BRGZR

TPS65181BRGZT

TPS65181RGZR

TPS65181RGZT

VQFN

RGZ

48

2500

250

330.0

180.0

330.0

180.0

330.0

180.0

330.0

180.0

16.4

7.3

1.5

12.0

16.0

Q2

2500

250

2500

250

2500

250

Pack Materials-Page 1

PACKAGE MATERIALS INFORMATION

www.ti.com

15-Jun-2011

*All dimensions are nominal

Device

Package Type Package Drawing Pins

SPQ

Length (mm) Width (mm) Height (mm)

TPS65180BRGZR

TPS65180BRGZT

TPS65180RGZR

TPS65180RGZT

TPS65181BRGZR

TPS65181BRGZT

TPS65181RGZR

TPS65181RGZT

VQFN

RGZ

48

2500

250

346.0

190.5

346.0

190.5

346.0

190.5

346.0

190.5

346.0

212.7

346.0

212.7

346.0

212.7

346.0

212.7

33.0

31.8

33.0

31.8

33.0

31.8

33.0

31.8

2500

250

2500

250

2500

250

Pack Materials-Page 2

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型号：	TPS65181BRGZT
厂家：	TEXAS INSTRUMENTS
描述：	用于 E Ink Vizplex 电子纸显示的 PMIC \| RGZ \| 48 \| -10 to 85 电子集成电源管理电路电源电路
文件：	总44页 (文件大小：1010K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

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