TPS62315YZ [TI]
500-mA, 3-MHz SYNCHRONOUS STEP-DOWN CONVERTER IN CHIP SCALE PACKAGING; 500毫安， 3 MHz的同步降压转换器芯片级封装
| 型号： | TPS62315YZ |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 500-mA, 3-MHz SYNCHRONOUS STEP-DOWN CONVERTER IN CHIP SCALE PACKAGING |
| 文件： | 总37页 (文件大小：1393K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
TPS62300, TPS62301, TPS62302
TPS62303, TPS62304, TPS62305,
CSP-8
QFN-10
TPS62311, TPS62313, TPS62315, TPS62320, TPS62321
www.ti.com
SLVS528E–JULY 2004–REVISED NOVEMBER 2007
500-mA, 3-MHz SYNCHRONOUS STEP-DOWN CONVERTER
IN CHIP SCALE PACKAGING
1
FEATURES
234
•
Up to 93% Efficiency at 3-MHz Operation
DESCRIPTION
•
•
•
•
•
Up to 500-mA Output Current at VI = 2.7 V
3-MHz Fixed Frequency Operation
The TPS623xx device is
a
high-frequency
synchronous step-down dc-dc converter optimized for
battery-powered portable applications. Intended for
low-power applications, the TPS623xx supports up to
500-mA load current and allows the use of tiny, low
cost chip inductor and capacitors.
Best in Class Load and Line Transient
Complete 1-mm Component Profile Solution
-0.5% / +1.3% PWM DC Voltage Accuracy Over
Temperature
The device is ideal for mobile phones and similar
portable applications powered by a single-cell Li-Ion
battery or by 3-cell NiMH/NiCd batteries. With an
output voltage range from 5.4 V down to 0.6 V, the
device supports the low-voltage TMS320™ DSP
family, processors in smart-phones, PDAs as well as
notebooks, and handheld computers.
•
•
35-ns Minimum On-Time
Power-Save Mode Operation at Light Load
Currents
•
•
•
•
Fixed and Adjustable Output Voltage
Only 86-µA Quiescent Current
100% Duty Cycle for Lowest Dropout
The TPS62300 operates at 3-MHz fixed switching
frequency and enters the power-save mode operation
at light load currents to maintain high efficiency over
the entire load current range. For low noise
applications, the device can be forced into fixed
frequency PWM mode by pulling the MODE/SYNC
pin high. The device can also be synchronized to an
external clock signal in the range of 3 MHz. In the
shutdown mode, the current consumption is reduced
to less than 1 µA.
Synchronizable On the Fly to External
Clock Signal
•
•
Integrated Active Power-Down Sequencing
(TPS6232x only)
Available in a 10-Pin QFN (3 x 3 mm), 8-Pin
NanoFree™, and NanoStar™ (CSP) Packaging
APPLICATIONS
•
•
•
•
•
•
Cell Phones, Smart-Phones
WLAN and Bluetooth™ Applications
Micro DC-DC Converter Modules
PDAs, Pocket PCs
USB-Based DSL Modems
Digital Cameras
The TPS623xx is available in a 10-pin leadless
package (3 x 3 mm QFN) and an 8-pin chip-scale
package (CSP).
100
V = 3.6 V,
I
90
80
70
60
50
40
30
20
V
= 1.8 V
O
TPS62303YZD
L1
2.7 V . . 6 V
V
A2
B2
B1
D1
C2
D2
O
VIN
EN
SW
1.8 V/500 mA
V
C2
1 µH
I
C1
VOUT
4.7 µF
C1
A1
4.7 µF
MODE/SYNC
GND
ADJ
FB
L = 2.2 µH,
Figure 1. Smallest Solution Size Application
(Fixed Output Voltage)
10
0
C
O
= 4.7 µF
0.1
1
10
100
1 k
I
− Load Current − mA
O
Figure 2. Efficiency vs Load Current
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
2
3
4
NanoFree, NanoStar, TMS320 are trademarks of Texas Instruments.
Bluetooth is a trademark of Bluetooth SIG, Inc.
PowerPAD is a trademark of Texas Instsruments.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2004–2007, Texas Instruments Incorporated
TPS62300, TPS62301, TPS62302
TPS62303, TPS62304, TPS62305,
TPS62311, TPS62313, TPS62315, TPS62320, TPS62321
www.ti.com
SLVS528E–JULY 2004–REVISED NOVEMBER 2007
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
ORDERING INFORMATION
PART
NUMBER
OUTPUT
VOLTAGE
UNDERVOLTAGE
LOCKOUT
PACKAGE
MARKING
TA
PACKAGE
ORDERING(1)(2)
2.4 V
2.4 V
2.4 V
2.4 V
2.4 V
2.4 V
2.4 V
2.4 V
2.4 V
2.4 V
2.4 V
2.4 V
2 V
QFN-10
CSP-8
QFN-10
CSP-8
QFN-10
CSP-8
QFN-10
CSP-8
QFN-10
CSP-8
QFN-10
CSP-8
CSP-8
CSP-8
CSP-8
QFN-10
CSP-8
CSP-8
QFN-10
CSP-8
CSP-8
TPS62300DRC
TPS62300YZD
TPS62301DRC
TPS62301YZD
TPS62302DRC
TPS62302YZD
TPS62303DRC
TPS62303YZD
TPS62304DRC
TPS62304YZD
TPS62305DRC
TPS62305YZD
TPS62311YZD
TPS62313YZD
TPS62315YZ
AMN
N/A
TPS62300
TPS62301
TPS62302
TPS62303
TPS62304
TPS62305
Adjustable
1.5 V
AMO
N/A
AMQ
N/A
1.6 V
AMR
N/A
1.8 V
AMS
N/A
1.2 V
-40°C to 85°C
ANU
N/A
1.875 V
TPS62311
TPS62313
TPS62315
1.5 V
1.8 V
N/A
2 V
N/A
1.875 V
2 V
N/A
2.4 V
2.4 V
2.4 V
2.4 V
2.4 V
2.4 V
TPS62320DRC
TPS62320YZD
TPS62320YED
TPS62321DRC
TPS62321YZD
TPS62321YED
AMX
N/A
TPS62320
TPS62321
Adjustable
1.5 V
N/A
AMY
N/A
N/A
(1) The YZD, YED and YZ packages are available in tape and reel. Add a R suffix (e.g. TPS62300YxDR) to order quantities of 3000 parts.
Add a T suffix (e.g. TPS62300YxDT) to order quantities of 250 parts. The DRC package is available in tape and reel. Add a R suffix
(e.g. TPS62300DRCR) to order quantities of 3000 parts.
(2) For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI
website at www.ti.com.
2
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Copyright © 2004–2007, Texas Instruments Incorporated
Product Folder Link(s): TPS62300, TPS62301, TPS62302 TPS62303, TPS62304, TPS62305, TPS62311, TPS62313,
TPS62315, TPS62320, TPS62321
TPS62300, TPS62301, TPS62302
TPS62303, TPS62304, TPS62305,
TPS62311, TPS62313, TPS62315, TPS62320, TPS62321
www.ti.com
SLVS528E–JULY 2004–REVISED NOVEMBER 2007
ABSOLUTE MAXIMUM RATINGS
over operating free-air temperature range (unless otherwise noted)(1)
UNIT
-0.3 V to 7 V
-0.3 V to 7 V
-0.3 V to 3.6 V
-0.3 V to VI + 0.3 V
0.3 V to 5.4 V
500 mA
Voltage at VIN, AVIN(2)
(2)
Voltage at SW
VI
Voltage at FB, ADJ
(2)
Voltage at EN, MODE/SYNC
Voltage at VOUT(2)
IO
Continuous output current
Power dissipation
Internally limited
-40°C to 85°C
150°C
TA
Operating temperature range
TJ (max) Maximum operating junction temperature
Tstg
Storage temperature range
-65°C to 150°C
2 kV
Human body model at AVIN, FB, ADJ, EN, MODE_SYNC, VOUT
Human body model at VIN, SW
ESD
rating(3)
1 kV
Charge device model
1.5 kV
(1) Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings
only and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating
conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) All voltage values are with respect to network ground terminal.
(3) The human body model is a 100-pF capacitor discharged through a 1.5-kΩ resistor into each pin.
Copyright © 2004–2007, Texas Instruments Incorporated
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Product Folder Link(s): TPS62300, TPS62301, TPS62302 TPS62303, TPS62304, TPS62305, TPS62311, TPS62313,
TPS62315, TPS62320, TPS62321
TPS62300, TPS62301, TPS62302
TPS62303, TPS62304, TPS62305,
TPS62311, TPS62313, TPS62315, TPS62320, TPS62321
www.ti.com
SLVS528E–JULY 2004–REVISED NOVEMBER 2007
DISSIPATION RATINGS(1)
POWER RATING
DERATING FACTOR
(2)
PACKAGE
RθJA
FOR TA≤ 25°C
2050 mW
400 mW
ABOVE TA = 25°C
21 mW/°C
4 mW/°C
DRC
YZD
YED
YZ
49°C/W
250°C/W
250°C/W
250°C/W
400 mW
4 mW/°C
400 mW
4 mW/°C
(1) Maximum power dissipation is a function of TJ(max), θJA and TA. The maximum allowable power dissipation at any allowable ambient
temperature is PD = [TJ(max)-TA] / θJA
(2) This thermal data is measured with low-K board (1 layer board according to JESD51-7 JEDEC standard).
ELECTRICAL CHARACTERISTICS
VI = 3.6 V, VO = 1.6 V, EN = VI, MODE/SYNC = GND, L = 1 µH, CO = 10 µF, TA = -40°C to 85°C, typical values are at
TA = 25°C (unless otherwise noted)
PARAMETER
SUPPLY CURRENT
TEST CONDITIONS
MIN
TYP
MAX
UNIT
VI
Input voltage range
2.7
6
105
120
V
TPS6230x
TPS6232x
IO = 0 mA. PFM mode enabled, device not switching
IO = 0 mA. PFM mode enabled, device not switching
86
86
µA
µA
Operating
quiescent
current
TPS6231x
IQ
TPS6230x
TPS6231x
TPS6232x
IO = 0 mA. Switching with no load
(MODE/SYNC = VIN)
3.6
mA
I(SD)
Shutdown current
EN = GND
0.1
2.40
2.00
1
2.55
2.20
µA
V
TPS6230x
TPS6232x
Undervoltage
lockout threshold
UVLO
TPS6231x
V
ENABLE, MODE/SYNC
V(EN)
EN high-level input voltage
1.2
1.3
V
V
V(MODE/SYNC)
MODE/SYNC high-level input voltage
V(EN)
V(MODE/SYNC)
,
EN, MODE/SYNC low-level input
voltage
0.4
1
V
I(EN)
,
EN, MODE/SYNC input leakage
current
EN, MODE/SYNC = GND or VIN
0.01
µA
I(MODE/SYNC)
POWER SWITCH
TPS6230x
TPS6231x
TPS6232x
VI = V(GS) = 3.6 V
VI = V(GS) = 2.8 V
420
520
750
mΩ
mΩ
P-channel MOSFET
on resistance
rDS(on)
1000
Ilkg
P-channel leakage current, PMOS
N-channel MOSFET on resistance
V(DS) = 6 V
1
750
µA
mΩ
mΩ
VI = V(GS) = 3.6 V
VI = V(GS) = 2.8 V
330
400
rDS(on)
1000
Discharge resistor for power-down
sequence (TPS6232x only)
R(DIS)
Ilkg
30
50
Ω
N-channel leakage current, NMOS
P-MOS current limit
V(DS) = 6 V
1
890
µA
mA
mA
mA
2.7 V ≤ VI ≤ 6 V
2.7 V ≤ VI ≤ 6 V
2.7 V ≤ VI ≤ 6 V
670
550
780
720
N-MOS current limit - sourcing
N-MOS current limit - sinking
890
–460
–600
–740
Input current limit under short-circuit
conditions
VO = 0 V
390
mA
Thermal shutdown
150
20
°C
°C
Thermal shutdown hysteresis
4
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Copyright © 2004–2007, Texas Instruments Incorporated
Product Folder Link(s): TPS62300, TPS62301, TPS62302 TPS62303, TPS62304, TPS62305, TPS62311, TPS62313,
TPS62315, TPS62320, TPS62321
TPS62300, TPS62301, TPS62302
TPS62303, TPS62304, TPS62305,
TPS62311, TPS62313, TPS62315, TPS62320, TPS62321
www.ti.com
SLVS528E–JULY 2004–REVISED NOVEMBER 2007
ELECTRICAL CHARACTERISTICS (continued)
VI = 3.6 V, VO = 1.6 V, EN = VI, MODE/SYNC = GND, L = 1 µH, CO = 10 µF, TA = -40°C to 85°C, typical values are at
TA = 25°C (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
OSCILLATOR
fSW
Oscillator frequency
2.65
2.65
20%
3
3.35
3.35
80%
MHz
MHz
f(SYNC)
Synchronization range
Duty cycle of external clock signal
OUTPUT
Adjustable output
voltage range
TPS62300
TPS62320
VO
0.6
5.4
V
V
Regulated feedback
voltage
TPS62300
TPS62320
V(FB)
0.4
1.5
35
DC power train amplification
(VO/V(ADJ)
A(PT)
1.496
1.504
)
Minimum on-time (P-channel
MOSFET)
ton(MIN)
ns
Resistance into VOUT sense pin
Resistance into ADJ pin
700
700
1000
1000
kΩ
kΩ
V(FB) > 0.4 V
V(FB) = 0.4 V
1300
Feedback input bias
current
TPS62300
TPS62320
I(FB)
1
nA
Adjustable output
voltage(1)
TPS62300
TPS62320
–2%
–2%
+2%
+2%
TPS6230x
TPS62311
TPS62313
TPS6232x
2.7 V ≤ VI ≤ 6 V, 0 mA ≤ IO(DC) ≤ 500 mA
PFM/PWM mode operation
Fixed output voltage
TPS62304
-2%
+2.5%
+2.7%
TPS62305
TPS62315
–2%
TA = 25°C
–0.5%
–0.5%
–0.5%
+1.3%
+1.3%
+1.3%
Adjustable output
TPS62300
VO
voltage dc accuracy(1) TPS62320
–40°C ≤ TA ≤ 85°C
TPS6230x
TPS62311
TA = 25°C
TPS62313
TPS6232x
–40°C ≤ TA ≤ 85°C
–0.5%
+1.3%
PWM mode operation,
VI = 3.6 V, No Load
Fixed output voltage
dc accuracy
TA = 25°C
-0.5%
-0.5%
–0.3%
–0.5%
+1.8%
+1.8%
+1.7%
+2%
TPS62304
–40°C ≤ TA ≤ 85°C
TA = 25°C
TPS62305
TPS62315
–40°C ≤ TA ≤ 85°C
DC output voltage load regulation
IO = 0 mA to 500 mA, MODE/SYNC = VI
–0.001
–0.002
%/mA
%/mA
DC output voltage load regulation
(power train in direct drive mode)
V(ADJ) externally forced to 1.067 V,
IO = 0 mA to 500 mA, MODE/SYNC = VI
–0.0003 –0.0006
VI = VO + 0.5 V (min 2.7 V) to
6 V, IO = 100 mA, MODE/SYNC = VI
DC output voltage line regulation
0.11
0.2
%/V
%/V
V(ADJ) externally forced to 1.067 V,
VI = VO + 0.5 V (min 2.7 V) to 6 V
IO = 100 mA, MODE/SYNC = VI
DC output voltage line regulation
(power train in direct drive mode)
0.035
0.1
Integrator slew rate
100
150
0.025 VO
250
200
µV/µs
VP-P
µs
ΔVO
Power-save mode ripple voltage
Start-up time
IO = 1 mA, MODE/SYNC = GND
IO = 200 mA, Time from active EN to VO
VI > VO, 0 V ≤ V(SW) ≤ VIN, EN = GND
VI = open, V(SW) = 6 V, EN = GND
Leakage current into SW pin
Reverse leakage current into SW pin
0.1
1
1
Ilkg
µA
0.1
(1) Output voltage specification for the adjustable version does not include tolerance of external voltage programming resistors.
Copyright © 2004–2007, Texas Instruments Incorporated
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Product Folder Link(s): TPS62300, TPS62301, TPS62302 TPS62303, TPS62304, TPS62305, TPS62311, TPS62313,
TPS62315, TPS62320, TPS62321
TPS62300, TPS62301, TPS62302
TPS62303, TPS62304, TPS62305,
TPS62311, TPS62313, TPS62315, TPS62320, TPS62321
www.ti.com
SLVS528E–JULY 2004–REVISED NOVEMBER 2007
PIN ASSIGNMENTS
TPS62300, TPS62320
QFN-10
(TOP VIEW)
TPS6230x, TPS6232x
FIXED OUTPUT VOLTAGE (QFN-10)
(TOP VIEW)
VIN
SW
VIN
AVIN
EN
SW
AVIN
EN
ADJ
FB
PGND
PGND
MODE/SYNC
AGND
VOUT
MODE/SYNC
AGND
VOUT
NC
NC
TPS6230x, TPS6231x, TPS6232x
CSP-8
(TOP VIEW)
TPS6230x, TPS6231x, TPS6232x
CSP-8
(BOTTOM VIEW)
A2
B2
C2
D2
A1
B1
C1
D1
A1
A2
GND
SW
VIN
EN
GND
VIN
EN
B1
C1
D1
B2
C2
D2
SW
MODE/SYNC
VOUT
ADJ
FB
MODE/SYNC
VOUT
ADJ
FB
TERMINAL FUNCTIONS
TERMINAL
I/O
DESCRIPTION
NO.
QFN
NO.
CSP
NAME
VIN
1
2
A2
I
I
Supply voltage for output power stage.
AVIN
This is the input voltage pin of the device. Connect directly to the input bypass capacitor.
This is the enable pin of the device. Connecting this pin to ground forces the device into shutdown
mode. Pulling this pin to VI enables the device. This pin must not be left floating and must be
terminated.
EN
3
B2
I
This is the internal reference voltage used to regulate VO. This pin is not connected on fixed output
voltage version of TPS6230xDRC and TPS6232xDRC. Do not connect ADJ pin on fixed output
voltage version of TPS6230xYZD, TPS6231xYZD, TPS6231xYZ and TPS6232xYxD.
ADJ
4
C2
I/O
On TPS62300 and TPS62320, this pin can also be used as an external control input. The output
voltage is 1.5x the applied voltage at ADJ.
This is the feedback pin of the device. For the adjustable version, an external resistor divider is
connected to this pin. The internal voltage divider is disabled for the adjustable version. This pin is
not connected on fixed output voltage version of TPS6230xDRC and TPS6232xDRC. Do not
connect the FB pin on the fixed output voltage version of TPS6230xYZD, TPS6231xYZD,
TPS6231xYZ and TPS6232xYxD.
FB
5
D2
D1
I
I
VOUT
AGND
6
7
Output feedback sense input. Connect VOUT to the converter’s output.
Analog ground. Connect to PGND via the PowerPAD™ underneath IC.
Input for synchronization to external clock signal. This pin must not be left floating and must be
terminated. Synchronizes the converter switching frequency to an external clock signal
MODE/SYNC = LOW (GND): The device is operating in fixed frequency pulse width modulation
mode (PWM) at high-load currents and in pulse frequency modulation mode (PFM) at light load
currents.
MODE/SYNC
8
C1
I
MODE/SYNC = HIGH (VIN): Low-noise mode enabled, fixed frequency PWM operation forced.
Power ground.
PGND
9
A1
B1
This is the switch pin of the converter and is connected to the drain of the internal Power
MOSFETs.
SW
10
I/O
PowerPAD™
N/A Internally connected to PGND.
6
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Copyright © 2004–2007, Texas Instruments Incorporated
Product Folder Link(s): TPS62300, TPS62301, TPS62302 TPS62303, TPS62304, TPS62305, TPS62311, TPS62313,
TPS62315, TPS62320, TPS62321
TPS62300, TPS62301, TPS62302
TPS62303, TPS62304, TPS62305,
TPS62311, TPS62313, TPS62315, TPS62320, TPS62321
www.ti.com
SLVS528E–JULY 2004–REVISED NOVEMBER 2007
FUNCTIONAL BLOCK DIAGRAM
MODE/SYNC
EN
VIN
N-MOS Current Limit
Compator
Undervoltage
Lockout
Bias Supply
AVIN
_
Soft-Start
V
= 0.4 V
REF
Band Gap
REF
+
Power-Save
Mode
3-MHz
Oscillator + PLL
Sawtooth
Thermal
+
Comp Low
Shutdown
Generator
Switching
Logic
REF
_
P-MOS Current Limit
Compator
RAMP HEIGHT
:
0.1 V
IN
2R
R
C
-
-
+
-
VOUT
-
+
+
-
SW
Gate Driver
Anti
2C
R
(DIS)
+
+
+
+
V
REF
Shoot-Through
+
EN
Summing
Comparator
_
A
= 3
FB
(DC)
P
TPS6232x
Only
Mid-, High-Frequency
Zero-Pole Pair
P
R2
See note A
R1
A
VOUT
Comparator Low
ADJ
+
_
A
-1.5% V
OUT(NOMINAL)
AGND
PGND
NOTE A:
PARAMETER MEASUREMENT INFORMATION
U1
L1
V
1
10
O
1.6 V/500 mA
VIN
SW
C2
2.7 V . . 6 V
2
6
AVIN
VOUT
10 mF
R1
C1
3
8
7
4
V
EN
ADJ
I
5
MODE/SYNC
FB
9
AGND
PGND
R2
A
A
A
List of Components:
U1 = TPS6230x
L1 = FDK MIPW3226 Series
C1, C2 = X5R/X7R
Copyright © 2004–2007, Texas Instruments Incorporated
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Product Folder Link(s): TPS62300, TPS62301, TPS62302 TPS62303, TPS62304, TPS62305, TPS62311, TPS62313,
TPS62315, TPS62320, TPS62321
TPS62300, TPS62301, TPS62302
TPS62303, TPS62304, TPS62305,
TPS62311, TPS62313, TPS62315, TPS62320, TPS62321
www.ti.com
SLVS528E–JULY 2004–REVISED NOVEMBER 2007
TYPICAL CHARACTERISTICS
Table of Graphs
FIGURE
vs Load current
3, 4, 5, 6
η
Efficiency
vs Input voltage
7
8
Line transient response
Load transient response
9, 10, 11, 12,
13, 14, 15, 16
VO
VFB
IQ
DC output voltage
vs Load current
vs Temperature
vs Input voltage
vs Temperature
17
18
Regulated feedback voltage
No load quiescent current
Switching frequency
19
fs
20
Duty cycle jitter
21
P-channel MOSFET rDS(on)
N-channel MOSFET rDS(on)
PWM operation
vs Input voltage
vs Input voltage
22
rDS(on)
23
24
Power-save mode operation
Dynamic voltage management
Start-up
25
26, 27
28, 29
30
Power down (TPS6232x)
EFFICIENCY
vs
LOAD CURRENT
EFFICIENCY
vs
LOAD CURRENT
100
90
80
70
60
50
40
30
20
100
90
80
70
60
50
40
30
20
10
0
PFM/PWM Operation
L = 2.2 mH
V = 3.6 V,
PFM/PWM Operation
L = 2.2 mH
V = 3.6 V,
I
I
V
O
= 1.6 V
V
O
= 1.8 V
PFM/PWM Operation
L = 0.9 mH
PWM Operation
L = 0.9 mH
PWM Operation
L = 2.2 mH
10
0
0.1
1
10
100
1000
0.1
1
10
100
1000
I
O
− Load Current − mA
I
O
− Load Current − mA
Figure 3.
Figure 4.
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TPS62315, TPS62320, TPS62321
TPS62300, TPS62301, TPS62302
TPS62303, TPS62304, TPS62305,
TPS62311, TPS62313, TPS62315, TPS62320, TPS62321
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SLVS528E–JULY 2004–REVISED NOVEMBER 2007
EFFICIENCY
vs
LOAD CURRENT
EFFICIENCY
vs
LOAD CURRENT
90
80
70
60
50
40
30
20
10
100
PFM/PWM Operation
PFM/PWM Operation
L = 2.2 mH
L = 2.2 mH
90
80
70
60
PWM Operation
L = 2.2 mH
PWM Operation
L = 0.9 mH
50
40
30
20
10
0
V = 3.6 V,
I
V = 5 V,
I
V
O
= 1.2 V
V
O
= 3.3 V
0
0.1
1
10
100
1000
0.1
1
10
100
1000
I
O
− Load Current − mA
I
O
− Load Current − mA
Figure 5.
Figure 6.
EFFICIENCY
vs
INPUT VOLTAGE
LINE TRANSIENT RESPONSE
100
I
= 100 mA
V
O
= 1.6 V
O
L = 0.9 mH, C = 10 mF
O
I
O
= 400 mA
90
80
70
60
50
40
30
20
10
0
I
= 1 mA
O
I
= 10 mA
O
PFM/PWM Operation
= 1.8 V
V
O
2.7 3
3.3 3.6 3.9 4.2 4.5 4.8 5.1 5.4 5.7 6
t − Time − 100 ms/div
V − Input Voltage − V
I
Figure 7.
Figure 8.
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TPS62300, TPS62301, TPS62302
TPS62303, TPS62304, TPS62305,
TPS62311, TPS62313, TPS62315, TPS62320, TPS62321
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SLVS528E–JULY 2004–REVISED NOVEMBER 2007
LOAD TRANSIENT RESPONSE IN
PWM OPERATION
LOAD TRANSIENT RESPONSE IN
PWM OPERATION
V = 3.6 V,
MODE/SYNC = HIGH
L = 0.9 mH, C = 10 mF
V = 3.6 V,
I
V = 1.6 V
O
I
V
O
= 1.6 V
O
MODE/SYNC = HIGH
L = 0.9 mH, C = 10 mF
O
I
O
= 10 to 100 mA Load Step
I
O
= 10 to 100 mA Load Step
I
O
= 10 to 400 mA Load Step
I
O
= 10 to 400 mA Load Step
t − Time − 2 ms/div
t − Time − 50 ms/div
Figure 9.
Figure 10.
LOAD TRANSIENT RESPONSE IN
PWM OPERATION
LOAD TRANSIENT RESPONSE
IN PFM MODE
V = 3.6 V,
V = 3.6 V,
I
V = 1.6 V
O
L = 0.9 mH, C = 10 mF
I
MODE/SYNC = HIGH
L = 0.9 mH, C = 10 mF
O
V
O
= 1.6 V
O
I
O
= 400 to 10 mA Load Step
I
O
= 100 to 10 mA Load Step
PFM Operation
t - Time - 2 ms/div
t − Time − 50 ms/div
Figure 11.
Figure 12.
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TPS62315, TPS62320, TPS62321
TPS62300, TPS62301, TPS62302
TPS62303, TPS62304, TPS62305,
TPS62311, TPS62313, TPS62315, TPS62320, TPS62321
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SLVS528E–JULY 2004–REVISED NOVEMBER 2007
LOAD TRANSIENT RESPONSE IN
PWM OPERATION
LOAD TRANSIENT RESPONSE IN
PWM OPERATION
V = 3.6 V,
O
V = 3.6 V,
O
I
I
MODE/SYNC = HIGH
V
= 1.6 V
V
= 1.6 V
L = 0.9 mH, C = 4.7 mF
O
MODE/SYNC = HIGH
L = 0.9 mH, C = 4.7 mF
O
I
O
= 10 to 100 mA Load Step
I
O
= 10 to 100 mA Load Step
I
O
= 10 to 400 mA Load Step
I
O
= 10 to 400 mA Load Step
t - Time - 2 ms/div
t - Time - 50 ms/div
Figure 13.
Figure 14.
LOAD TRANSIENT RESPONSE IN
PFM OPERATION
LOAD TRANSIENT RESPONSE IN
PFM OPERATION
V = 3.6 V,
O
V = 3.6 V,
O
I
I
MODE/SYNC = HIGH
L = 0.9 mH, C = 4.7 mF
L = 0.9 mH, C = 4.7 mF
O
V
= 1.6 V
V
= 1.6 V
O
I
O
= 400 to 10 mA Load Step
I
O
= 100 to 10 mA Load Step
PFM Operation
t - Time - 2 ms/div
t - Time - 50 ms/div
Figure 15.
Figure 16.
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TPS62300, TPS62301, TPS62302
TPS62303, TPS62304, TPS62305,
TPS62311, TPS62313, TPS62315, TPS62320, TPS62321
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SLVS528E–JULY 2004–REVISED NOVEMBER 2007
OUTPUT VOLTAGE
vs
LOAD CURRENT
REGULATED FEEDBACK VOLTAGE
vs
TEMPERATURE
1.628
1.618
406
405.5
405
V = 3.6 V, V = 1.6 V,
L = 2.2 mH
I
O
TPS62300
1.608
PWM Operation
404.5
404
V = 3.6 V
I
V = 4.2 V
I
1.598
1.588
403.5
403
PFM/PWM Operation
V = 2.7 V
I
1.578
1.568
402.5
402
0.1
1
10
100
1000
-40 -30 -20 -10
0 10 20 30 40 50 60 70 80 85
I
O
− Load Current − mA
T
A
- Ambient Temperature - 5C
Figure 17.
Figure 18.
QUIESCENT CURRENT
vs
OSCILLATOR FREQUENCY
vs
INPUT VOLTAGE
INPUT VOLTAGE
3.3
3.25
3.2
96
94
92
90
88
86
84
82
80
T
= −405C
A
T
= 255C
A
T
= 855C
A
3.15
3.1
T
A
= 255C
= 855C
T
A
3.05
3
T
= −405C
A
MODE/SYNC = HIGH
2.95
2.9
2.7
3
3.3 3.6 3.9 4.2 4.5 4.8 5.1 5.4 5.7
6
2.7
3
3.3 3.6 3.9 4.2 4.5 4.8 5.1 5.4 5.7
6
V − Input Voltage − V
I
V − Input Voltage − V
I
Figure 19.
Figure 20.
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TPS62315, TPS62320, TPS62321
TPS62300, TPS62301, TPS62302
TPS62303, TPS62304, TPS62305,
TPS62311, TPS62313, TPS62315, TPS62320, TPS62321
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SLVS528E–JULY 2004–REVISED NOVEMBER 2007
P-CHANNEL rDS(ON)
vs
DUTY CYCLE JITTER
V = 3.6 V, V = 1.6 V,
INPUT VOLTAGE
700
650
600
I
O
L = 0.9 mH, C = 10 mF
O
I
O
= 320 mA
TRIGGER ON RISING EDGE
T
A
= 855C
550
500
450
400
350
300
250
200
150
T
= 255C
A
T
A
= −405C
MODE/SYNC = HIGH
2.5
3
3.5
4
4.5
5
5.5
6
t - Time - 25 ns/div
V − Input Voltage − V
I
Figure 21.
Figure 22.
N-CHANNEL rDS(ON)
vs
INPUT VOLTAGE
PWM OPERATION
550
500
450
400
350
300
250
200
150
I
= 200 mA
O
L = 0.9 mH, C = 10 mF
O
T
= 855C
A
T
= 255C
A
T
A
= −405C
V = 3.6 V, V = 1.6 V
I
O
2.5
3
3.5
4
4.5
5
5.5
6
t − Time − 200 ns/div
V − Input Voltage − V
I
Figure 23.
Figure 24.
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TPS62300, TPS62301, TPS62302
TPS62303, TPS62304, TPS62305,
TPS62311, TPS62313, TPS62315, TPS62320, TPS62321
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SLVS528E–JULY 2004–REVISED NOVEMBER 2007
POWER-SAVE MODE OPERATION
DYNAMIC VOLTAGE MANAGEMENT
V = 3.6 V,
I
O
V
= 1 V / 1.5 V
V = 1.5 V
O
V
O
= 1 V
V
(ADJ)
= 1 V
V
(ADJ)
= 0.67 V
L = 0.9 mH, C = 10 mF,
V = 3.6 V, V = 1.6 V
O
I
O
MODE/SYNC = LOW
L = 0.9 mH, C = 10 mF
O
I
O
= 40 mA
R
L
= 270 W
t − Time − 20 ms/div
t − Time − 2 ms/div
Figure 25.
Figure 26.
DYNAMIC VOLTAGE MANAGEMENT
V = 3.6 V,
START-UP
I
V
V = 3.6 V,
I
= 1 V / 1.5 V
O
V = 1.5 V
O
V
= 1.6 V,
O
I
= 0 mA
O
V
O
= 1 V
V
(ADJ)
= 0.67 V
V
(ADJ)
= 1 V
R
L
= 5 W
L = 0.9 mH, C = 10 mF,
O
MODE/SYNC = HIGH
L = 2.2 mH, C = 4.7 mF,
O
t − Time − 20 ms/div
t − Time − 50 ms/div
Figure 27.
Figure 28.
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TPS62315, TPS62320, TPS62321
TPS62300, TPS62301, TPS62302
TPS62303, TPS62304, TPS62305,
TPS62311, TPS62313, TPS62315, TPS62320, TPS62321
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SLVS528E–JULY 2004–REVISED NOVEMBER 2007
START-UP
POWER DOWN (TPS62321)
V = 3.6 V,
I
V = 3.6 V,
V
I
= 1.5 V,
I
O
V
= 1.6 V,
= 0 mA
O
O
I
= 320 mA
O
L = 0.9 mH, C = 10 mF
O
L = 2.2 mH, C = 4.7 mF,
O
t − Time − 400 ms/div
Figure 30.
t − Time − 50 ms/div
Figure 29.
DETAILED DESCRIPTION
OPERATION
The TPS6230x, TPS6231x, and TPS6232x are synchronous step-down converters typically operating with a
3-MHz fixed frequency pulse width modulation (PWM) at moderate to heavy load currents. At light load currents,
the converter operates in power-save mode with pulse frequency modulation (PFM). The operating frequency is
set to 3 MHz and can be synchronized on-the-fly to an external oscillator.
During PWM operation, the converter uses a unique fast response, voltage mode, controller scheme with input
voltage feed-forward. This achieves best-in-class load and line response and allows the use of tiny inductors and
small ceramic input and output capacitors. At the beginning of each switching cycle, the P-channel MOSFET
switch is turned on and the inductor current ramps up until the comparator trips and the control logic turns off the
switch.
The device integrates two current limits, one in the P-channel MOSFET and another one in the N-channel
MOSFET. When the current in the P-channel MOSFET reaches its current limit, the P-channel MOSFET is
turned off and the N-channel MOSFET is turned on. When the current in the N-channel MOSFET is above the
N-MOS current limit threshold, the N-channel MOSFET remains on until the current drops below its current limit.
The current limit in the N-channel MOSFET is important for small duty-cycle operation when the current in the
inductor does not decrease because of the P-channel MOSFET current limit delay, or because of start-up
conditions where the output voltage is low.
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TPS62300, TPS62301, TPS62302
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SLVS528E–JULY 2004–REVISED NOVEMBER 2007
POWER-SAVE MODE
With decreasing load current, the device automatically switches into pulse skipping operation in which the power
stage operates intermittently based on load demand. By running cycles periodically, the switching losses are
minimized, and the device runs with a minimum quiescent current and maintaining high efficiency.
In power-save mode, the converter only operates when the output voltage trips below a set threshold voltage
(-1.5% VO(NOMINAL)). It ramps up the output voltage with several pulses and goes into power-save mode once the
output voltage exceeds the nominal output voltage. As a consequence, the average output voltage is slightly
lower than its nominal value in the power-save mode operation.
The output current at which the PFM/PWM transition occurs is approximated by Equation 1:
V
V * V
O
I
O
I
+
PFMńPWM
V
2 L f
sw
I
(1)
•
•
•
IPFM/PWM : output current at which PFM/PWM transition occurs
fSW : switching frequency (3-MHz typical)
L : inductor value
V
O(NOMINAL)
3-MHz Operation
Comp Low Thershold
−1.5% V
O(NOMIAL)
Figure 31. Power-Save Mode Threshold
MODE SELECTION AND FREQUENCY SYNCHRONIZATION
The MODE/SYNC pin is a multipurpose pin which allows mode selection and frequency synchronization.
Connecting this pin to GND enables the automatic PWM and power-save mode operation. The converter
operates in fixed frequency PWM mode at moderate to heavy loads and in the PFM mode during light loads,
which maintains high efficiency over a wide load current range.
Pulling the MODE/SYNC pin high forces the converter to operate in the PWM mode even at light load currents.
The advantage is that the converter operates with a fixed frequency that allows simple filtering of the switching
frequency for noise-sensitive applications. In this mode, the efficiency is lower compared to the power-save
mode during light loads. For additional flexibility, it is possible to switch from power-save mode to forced PWM
mode during operation. This allows efficient power management by adjusting the operation of the converter to
the specific system requirements.
The TPS6230x, TPS6231x, and TPS6232x can also be synchronized to an external 3-MHz clock signal by the
MODE/SYNC pin. During synchronization, the mode is set to fixed-frequency operation and the P-channel
MOSFET turnon is synchronized to the falling edge of the external clock. This creates the ability for multiple
converters to be connected together in a master-slave configuration for frequency matching of the converters
(see the application section for more details, Figure 37).
SOFT START
The TPS6230x, TPS6231x, and TPS6232x have an internal soft-start circuit that limits the inrush current during
start-up. This prevents possible input voltage drops when a battery or a high-impedance power source is
connected to the input of the converter. The soft start is implemented as a digital circuit increasing the switch
current in steps of typically 195 mA, 390 mA, 585 mA, and the typical switch current limit of 780 mA.
The current limit transitions to the next step every 256 clocks (≈88µs). To be able to switch from 390 mA to 585
mA current limit step, the output voltage needs to be higher than 0.5 x VO(NOM), otherwise, the parts continues to
operate at the 390-mA current limit. This mechanism is used to limit the output current under short-circuit
conditions. Therefore, the start-up time mainly depends on the output capacitor and load current.
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LOW-DROPOUT OPERATION 100% DUTY CYCLE
In 100% duty cycle mode, the TPS6230x, TPS6231x, and TPS6232x offer a low input-to-output voltage
difference. In this mode, the P-channel MOSFET is constantly turned on. This is particularly useful in
battery-powered applications to achieve the longest operation time by taking full advantage of the whole battery
voltage range. The minimum input voltage to maintain regulation, depending on the load current and output
voltage, can be calculated as:
•
•
•
•
•
VI(MIN) = VO(MAX) + IO(MAX) x (rDS(on) MAX + RL)
IO(MAX) : Maximum output current
rDS(on) MAX : Maximum P-channel switch rDS(on)
RL : DC resistance of the inductor
VO(MAX) : nominal output voltage plus maximum output voltage tolerance
ENABLE
The device starts operation when EN is set high and starts up with the soft start as previously described.
Pulling the EN pin low forces the device into shutdown, with a shutdown quiescent current of typically 0.1 µA. In
this mode, the P and N-channel MOSFETs are turned off, the internal resistor feedback divider is disconnected,
and the entire internal-control circuitry is switched off. When an output voltage is present during shutdown mode,
which can be caused by an external voltage source or super capacitor, the reverse leakage is specified under
electrical characteristics. For proper operation, the EN pin must be terminated and must not be left floating.
In addition, the TPS6232x devices integrate a resistor, typically 35 Ω, to actively discharge the output capacitor
when the device turns off. The required time to discharge the output capacitor at VO depends on load current.
UNDERVOLTAGE LOCKOUT
The undervoltage lockout circuit prevents the device from misoperation at low input voltages. It prevents the
converter from turning on the switch or rectifier MOSFET under undefined conditions.
The TPS6231x devices have a UVLO threshold set to 2 V (typical). Fully functional operation is permitted down
to 2.4 V input voltage. EN is set low for input voltages lower than 2.4 V to avoid the possibility of misoperation.
TPS6231x devices are to be considered where the user requires direct control of the turn-off sequence as part of
a larger power management system.
SHORT-CIRCUIT PROTECTION
As soon as the output voltage falls below 50% of the nominal output voltage, the converter current limit is
reduced by 50% of the nominal value. Because the short-circuit protection is enabled during start-up, the device
does not deliver more than half of its nominal current limit until the output voltage exceeds 50% of the nominal
output voltage. This needs to be considered when a load acting as a current sink is connected to the output of
the converter.
THERMAL SHUTDOWN
As soon as the junction temperature, TJ, exceeds typically 150°C, the device goes into thermal shutdown. In this
mode, the P- and N-channel MOSFETs are turned off. The device continues its operation when the junction
temperature falls below typically 130°C again.
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TPS62300, TPS62301, TPS62302
TPS62303, TPS62304, TPS62305,
TPS62311, TPS62313, TPS62315, TPS62320, TPS62321
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SLVS528E–JULY 2004–REVISED NOVEMBER 2007
APPLICATION INFORMATION
ADJUSTABLE OUTPUT VOLTAGE
When the adjustable output voltage versions, TPS62300 or TPS62320, are used, the output voltage is set by the
external resistor divider (see Figure 32).
The output voltage is calculated as:
R1
R2
ǒ1 ) Ǔwith an internal reference voltage V
V
+ 1.5 V
typical + 0.4 V
O
ref
ref
(2)
To keep the operating quiescent current to a minimum, it is recommended that R2 be set in the range of 75 kΩ to
130 kΩ. Route the FB line away from noise sources, such as the inductor or the SW line.
TPS62300
L1
1
2
3
8
7
10
V
O
VIN
AVIN
EN
SW
2.7 V . . 6 V
C2 1.6 V/500 mA
6
VOUT
R1
4.7 mF
C1
4
V
I
ADJ
5
4.7 mF
MODE/SYNC
FB
9
AGND
PGND
R2
A
A
A
Figure 32. Adjustable Output Voltage Version
OUTPUT FILTER DESIGN (INDUCTOR AND OUTPUT CAPACITOR)
The TPS6230x, TPS6231x, and TPS6232x series of step-down converters have internal loop compensation.
Therefore, the external L-C filter must be selected to work with the internal compensation.
The device has been designed to operate with inductance values between a minimum of 0.7 µH and maximum of
6.2 µH. The internal compensation is optimized to operate with an output filter of L = 1 µH and CO = 10 µF. Such
an output filter has its corner frequency at:
1
1
ƒ +
+
+ 50.3 kHz
c
Ǹ
2p ǸL C
2p 1 mH 10 mF
O
(3)
Operation with a higher corner frequency (e.g., L = 1 µH, CO = 4.7 µF) is possible. However, it is recommended
the loop stability be checked in detail. Selecting a larger output capacitor value (e.g., 22 µF) is less critical
because the corner frequency moves to lower frequencies with fewer stability problems. The possible output filter
combinations are listed in Table 1.
Regardless of the inductance value, operation is recommended with 10-µF output capacitor in applications with
high-load transients (e.g., ≥ 1600 mA/µs).
Table 1. Output Filter Combinations
INDUCTANCE (L)
1 µH
OUTPUT CAPACITANCE (CO)
≥ 4.7 µF (ceramic capacitor)
≥ 2.2 µF (ceramic capacitor)
2.2 µH
The inductor value also has an impact on the pulse skipping operation. The transition into power-save mode
begins when the valley inductor current goes below a level set internally. Lower inductor values result in higher
ripple current which occurs at lower load currents. This results in a dip in efficiency at light load operations.
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Product Folder Link(s): TPS62300, TPS62301, TPS62302 TPS62303, TPS62304, TPS62305, TPS62311, TPS62313,
TPS62315, TPS62320, TPS62321
TPS62300, TPS62301, TPS62302
TPS62303, TPS62304, TPS62305,
TPS62311, TPS62313, TPS62315, TPS62320, TPS62321
www.ti.com
SLVS528E–JULY 2004–REVISED NOVEMBER 2007
INDUCTOR SELECTION
Even though the inductor does not influence the operating frequency, the inductor value has a direct effect on the
ripple current. The selected inductor has to be rated for its dc resistance and saturation current. The inductor
ripple current (ΔIL) decreases with higher inductance and increases with higher VI or VO.
V
V * V
DI
O
I
O
L
DI +
DI
+ I
)
L
L(MAX)
O(MAX)
2
V
L ƒ
sw
I
(4)
with: fSW = switching frequency (3 MHz typical)
L = inductor value
ΔIL = peak-to-peak inductor ripple current
IL(MAX) = maximum inductor current
Normally, it is advisable to operate with a ripple of less than 30% of the average output current. Accepting larger
values of ripple current allows the use of low inductances, but results in higher output voltage ripple, greater core
losses, and lower output current capability.
The total losses of the coil consist of both the losses in the DC resistance (R(DC)) and the following
frequency-dependent components:
•
•
•
•
The losses in the core material (magnetic hysteresis loss, especially at high switching frequencies)
Additional losses in the conductor from the skin effect (current displacement at high frequencies)
Magnetic field losses of the neighboring windings (proximity effect)
Radiation losses
The following inductor series from different suppliers have been used with the TPS6230x, TPS6231x, and
TPS6232x converters.
Table 2. List of Inductors
MANUFACTURER
SERIES
MIPW3226
MIPSA2520
LQM2HP
DIMENSIONS
FDK
3.2 x 2.6 x 1 = 8.32 mm3
2.5 x 2.0 x 1.2 = 6 mm3
2.5 x 2.0 x 1.2 = 6 mm3
2 x 1.6 x 1.6 = 5.12 mm3
2 x 1.2 x 1.2 = 2.88 mm3
2 x 1.2 x 1 = 2.40 mm3
2.8 x 2.6 x 1 = 7.28 mm3
3.3 x 3.3 x 1 = 10.89 mm3
3.2 x 2.5 x 0.6 = 4.8 mm3
Murata
LQ CB2016
LQ CB2012
LQ CBL2012
VLF3010AT
LPS3010
Taiyo Yuden
TDK
Coilcraft
JFE
32R1560
OUTPUT CAPACITOR SELECTION
The advanced fast-response voltage mode control scheme of the TPS6230x, TPS6231x, and TPS6232x allows
the use of tiny ceramic capacitors. Ceramic capacitors with low ESR values have the lowest output voltage ripple
and are recommended. The output capacitor requires either an X7R or X5R dielectric. Y5V and Z5U dielectric
capacitors, aside from their wide variation in capacitance over temperature, become resistive at high frequencies.
At nominal load current, the device operates in PWM mode and the overall output voltage ripple is the sum of the
voltage spike caused by the output capacitor ESR plus the voltage ripple caused by charging and discharging the
output capacitor:
V
V * V
O
I
O
1
DV
+
) ESR , maximum for high V
ǒ
Ǔ
O
I
V
L ƒ
8 C ƒ
sw
sw
I
O
(5)
At light loads, the device operates in power-save mode and the output voltage ripple is independent of the output
capacitor value. The output voltage ripple is set by the internal comparator thresholds and propagation delays.
The typical output voltage ripple is 1.5% of the nominal output voltage VO.
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Product Folder Link(s): TPS62300, TPS62301, TPS62302 TPS62303, TPS62304, TPS62305, TPS62311, TPS62313,
TPS62315, TPS62320, TPS62321
TPS62300, TPS62301, TPS62302
TPS62303, TPS62304, TPS62305,
TPS62311, TPS62313, TPS62315, TPS62320, TPS62321
www.ti.com
SLVS528E–JULY 2004–REVISED NOVEMBER 2007
INPUT CAPACITOR SELECTION
Because of the nature of the buck converter having a pulsating input current, a low ESR input capacitor is
required to prevent large voltage transients that can cause misbehavior of the device or interferences with other
circuits in the system. For most applications, a 2.2-µF or 4.7-µF capacitor is sufficient.
Take care when using only ceramic input capacitors. When a ceramic capacitor is used at the input and the
power is being supplied through long wires, such as from a wall adapter, a load step at the output can induce
ringing at the VIN pin. This ringing can couple to the output and be mistaken as loop instability or could even
damage the part.
CHECKING LOOP STABILITY
The first step of circuit and stability evaluation is to look from a steady-state perspective at the following signals:
•
•
•
Switching node, SW
Inductor current, IL
Output ripple voltage, VO(AC)
These are the basic signals that need to be measured when evaluating a switching converter. When the
switching waveform shows large duty cycle jitter or the output voltage or inductor current shows oscillations, the
regulation loop may be unstable. This is often a result of board layout and/or L-C combination.
As a next step in the evaluation of the regulation loop, the load transient response is tested. The time between
the application of the load transient and the turn on of the P-channel MOSFET, the output capacitor must supply
all of the current required by the load. VO immediately shifts by an amount equal to ΔI(LOAD) x ESR, where ESR
is the effective series resistance of CO. ΔI(LOAD) begins to charge or discharge CO generating a feedback error
signal used by the regulator to return VO to its steady-state value.
During this recovery time, VO can be monitored for settling time, overshoot or ringing that helps judge the
converter’s stability. Without any ringing, the loop has usually more than 45° of phase margin.
Because the damping factor of the circuitry is directly related to several resistive parameters (e.g., MOSFET
rDS(on)) that are temperature dependant, the loop stability analysis has to be done over the input voltage range,
load current range, and temperature range.
PROGRAMMING THE OUTPUT VOLTAGE WITH A DAC
On TPS62300 and TPS62320 devices, the output voltage can be dynamically programmed to any voltage
between 0.6 V and VI (or 5.4 V whichever is lower) with an external DAC driving the ADJ and FB pins (see
Figure 33). The output voltage is then equal to A(PT) x V(DAC) with a Power Train amplification A(PT) typical = 1.5.
When the output voltage is driven low, the converter reduces its output quickly in forced PWM mode, boosting
the output energy back to the input. If the input is not connected to a low-impedance source capable of absorbing
the energy, the input voltage can rise above the absolute maximum voltage of the part and get damaged. The
faster VO is commanded low, the higher is the voltage spike at the input.
For best results, ramp the ADJ/FB signal as slow as the application allows. To avoid over-slew of the regulation
loop of the converter, avoid abrupt changes in output voltage of > 300 mV/µs (depending on VI , output voltage
step size and L/C combination). If ramp control is unavailable, an RC filter can be inserted between the DAC
output and ADJ/FB pins to slow down the control signal.
V
= 1.5 x V
(DAC)
TPS62300
VIN
O
L
1
2
3
8
7
10
6
SW
VOUT
ADJ
C
O
AVIN
EN
C
I
4
V
I
V
(DAC)
R
F
5
MODE/SYNC FB
10 kW
9
AGND
PGND
C
F
A
A
A
Figure 33. Filtering the DAC Voltage
20
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Product Folder Link(s): TPS62300, TPS62301, TPS62302 TPS62303, TPS62304, TPS62305, TPS62311, TPS62313,
TPS62315, TPS62320, TPS62321
TPS62300, TPS62301, TPS62302
TPS62303, TPS62304, TPS62305,
TPS62311, TPS62313, TPS62315, TPS62320, TPS62321
www.ti.com
SLVS528E–JULY 2004–REVISED NOVEMBER 2007
LAYOUT CONSIDERATIONS
As for all switching power supplies, the layout is an important step in the design. High-speed operation of the
TPS6230x, TPS6231x, and TPS6232x devices demand careful attention to PCB layout. Care must be taken in
board layout to get the specified performance. If the layout is not carefully done, the regulator could show poor
line and/or load regulation, stability issues as well as EMI problems. It is critical to provide a low inductance,
impedance ground path. Therefore, use wide and short traces for the main current paths as indicated in bold on
Figure 34.
The input capacitor should be placed as close as possible to the IC pins as well as the inductor and output
capacitor. Use a common ground node for power ground and a different one for control ground (AGND) to
minimize the effects of ground noise. Connect these ground nodes together (star point) underneath the IC and
make sure that small signal components returning to the AGND pin do not share the high current path of C1 and
C2.
The output voltage sense line (VOUT) should be connected right to the output capacitor and routed away from
noisy components and traces (e.g., SW line). Its trace should be minimized and shielded by a guard-ring
connected to the reference ground. The voltage setting resistive divider should be placed as close as possible to
the AGND pin of the IC.
TPS62300
L1
V
O
1
2
3
8
7
10
6
VIN
AVIN
EN
SW
VOUT
ADJ
V
I
C2
R1
4
C1
5
MODE/SYNC
FB
9
AGND
R2
PGND
Figure 34. Layout Diagram
VO
GND
VI
VO sense signal
EN
MODE / SYNC
GND
Figure 36. Suggested QFN Layout (Bottom)
Figure 35. Suggested QFN Layout (Top)
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Product Folder Link(s): TPS62300, TPS62301, TPS62302 TPS62303, TPS62304, TPS62305, TPS62311, TPS62313,
TPS62315, TPS62320, TPS62321
TPS62300, TPS62301, TPS62302
TPS62303, TPS62304, TPS62305,
TPS62311, TPS62313, TPS62315, TPS62320, TPS62321
www.ti.com
SLVS528E–JULY 2004–REVISED NOVEMBER 2007
THERMAL INFORMATION
Implementation of integrated circuits in low-profile and fine-pitch surface-mount packages typically requires
special attention to power dissipation. Many system-dependant issues such as thermal coupling, airflow, added
heat sinks, and convection surfaces, and the presence of other heat-generating components, affect the
power-dissipation limits of a given component
Three basic approaches for enhancing thermal performance are listed below:
•
•
•
Improving the power dissipation capability of the PCB design
Improving the thermal coupling of the component to the PCB
Introducing airflow in the system
The maximum recommended junction temperature (TJ) of the TPS6230x, TPS6231x, and TPS6232x devices is
125°C. The thermal resistance of the 8-pin CSP package (YZD, YZ and YED) is RθJA = 250°C/W. Specified
regulator operation is specified to a maximum ambient temperature TA of 85°C. Therefore, the maximum power
dissipation is about 160 mW. More power can be dissipated if the maximum ambient temperature of the
application is lower, or if the PowerPAD™ package (DRC) is used.
T
* T
J(MAX)
R
A
125°C * 85°C
250°CńW
P
+
+
+ 160 mW
D(MAX)
qJA
(6)
CHIP SCALE PACKAGE DIMENSIONS
The TPS6230x, TPS6231x, and TPS6232x are also available in an 8-bump chip scale package (YZD, YZ
NanoFree™ and YED, NanoStar™). The package dimensions are given as:
•
•
D = 1.970 ±0.05 mm
E = 0.970 ±0.05 mm
22
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Product Folder Link(s): TPS62300, TPS62301, TPS62302 TPS62303, TPS62304, TPS62305, TPS62311, TPS62313,
TPS62315, TPS62320, TPS62321
TPS62300, TPS62301, TPS62302
TPS62303, TPS62304, TPS62305,
TPS62311, TPS62313, TPS62315, TPS62320, TPS62321
www.ti.com
SLVS528E–JULY 2004–REVISED NOVEMBER 2007
APPLICATION EXAMPLES
TPS62303YZD
A2
B2
D1
2.7 V − 6 V
VIN
EN
VOUT
SW
L
Ch1
Ch2
1
V
C
B1
C2
OUT
IN
V
IN
1.8 V / 500 mA
C
10 µF
1
C1
A1
MODE/SYNC ADJ
10 µF
D2
FB
GND
Ch4
TPS62304YZD
L
2
V
A2
B2
B1
D1
C2
OUT
VIN
EN
SW
1.2 V / 500 mA
C
2
Ch3
VOUT
10 µF
C1
A1
MODE/SYNC ADJ
1G08
Ch1: SW (1.8-V Output), Ch2: I
Ch3: SW (1.2-V Output), Ch4: I
D2
L1
L2
FB
GND
Low: None Synchronized Operation
PFM/PWM Automatic Switch
High: Synchronized Operation
Forced 3 MHz Fixed Frequency Operation
List of Components:
L1, L2 = Taiyo Yuden LQ CB2016
, C1, C2, = X5R/X7R Ceramic Capacitor
C
IN
Figure 37. Dual, Out-of-Phase, 3-MHz, 500-mA Step-Down Regulator
Features Less Than 50-mm2 Total Solution Size
EN
Fast Start−Up LDO
22 nF
10 kΩ
V
= 0.98 x V
OUT(NOM)
OUT(LDO)
EN
EN
VOUT
VIN
GND
2.2 MΩ
TPS62300YZD
2.7 V . . 6 V
V
O
A2
B2
D1
VIN
EN
VOUT
SW
V
OUT
C
B1
C2
IN
10 µF
V
L1
1 µH
IN
C1
1.8 V / 500 mA
I
L1
C1
A1
V = 2.8 V,
I
MODE/SYNC ADJ
FB
10 µF
R
L
= 10 W
D2
GND
Ch1: V
Ch3: Inductor Current: I
Ch3: EN − External Control Signal
O
List of Components:
L1 = Taiyo Yuden LQ CB2016
, C1 = X5R/X7R Ceramic Capacitor
L1
C
IN
Figure 38. Speed-Up Circuitry for Fast Turnon Time
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Product Folder Link(s): TPS62300, TPS62301, TPS62302 TPS62303, TPS62304, TPS62305, TPS62311, TPS62313,
TPS62315, TPS62320, TPS62321
TPS62300, TPS62301, TPS62302
TPS62303, TPS62304, TPS62305,
TPS62311, TPS62313, TPS62315, TPS62320, TPS62321
www.ti.com
SLVS528E–JULY 2004–REVISED NOVEMBER 2007
TPS62300
1.8
1.6
1.4
1.2
1
VIN
EN
VOUT
SW
Default Voltage =
R1
2.7 V − 6 V
L1
C
I
1.5 x V x 1+
ref ( R2)
V
OUT
V
IN
2.2 µH
R1
C1
10 µF
MODE/SYNC ADJ
4.7 µF
9.5 kΩ
FB
GND
R2
8.2 kΩ
0.8
0.6
0.4
DAC6571
2.85 V
VDD
SDA
SCL
A0
DAC Control Range
= 1.5 x 0.98 x V
2
I C I/F
VDAC
0.2
0
V
O
(DAC)
GND
0
0.2
0.4 0.6
0.8
1
1.2
1.4
V
− Control Voltage − V
(DAC)
List of Components:
L1 = Wuerth Elektronik WE-TPC XS
C , C1, = X5R/X7R Ceramic Capacitor
I
Figure 39. Dynamic Voltage Management Using I2C I/F
24
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Product Folder Link(s): TPS62300, TPS62301, TPS62302 TPS62303, TPS62304, TPS62305, TPS62311, TPS62313,
TPS62315, TPS62320, TPS62321
PACKAGE OPTION ADDENDUM
www.ti.com
15-Nov-2007
PACKAGING INFORMATION
Orderable Device
TPS62300DRCR
TPS62300DRCRG4
TPS62300YZDR
TPS62300YZDT
TPS62301DRCR
TPS62301DRCRG4
TPS62301YZDR
TPS62301YZDT
TPS62302DRCR
TPS62302DRCRG4
TPS62302YZDR
TPS62302YZDT
TPS62303DRCR
TPS62303DRCRG4
TPS62303YZDR
TPS62303YZDT
TPS62304DRCR
TPS62304DRCRG4
TPS62304YZDR
TPS62304YZDT
TPS62305DRCR
TPS62305DRCRG4
TPS62305YZDR
TPS62305YZDT
TPS62311YZDR
Status (1)
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
Package Package
Pins Package Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)
Qty
Type
Drawing
SON
DRC
10
10
8
3000 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR
no Sb/Br)
SON
DSBGA
DSBGA
SON
DRC
YZD
YZD
DRC
DRC
YZD
YZD
DRC
DRC
YZD
YZD
DRC
DRC
YZD
YZD
DRC
DRC
YZD
YZD
DRC
DRC
YZD
YZD
YZD
3000 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR
no Sb/Br)
3000 Green (RoHS &
no Sb/Br)
SNAGCU
Level-1-260C-UNLIM
8
250 Green (RoHS &
no Sb/Br)
SNAGCU
Level-1-260C-UNLIM
10
10
8
3000 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR
no Sb/Br)
SON
3000 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR
no Sb/Br)
DSBGA
DSBGA
SON
3000 Green (RoHS &
no Sb/Br)
SNAGCU
Level-1-260C-UNLIM
8
250 Green (RoHS &
no Sb/Br)
SNAGCU
Level-1-260C-UNLIM
10
10
8
3000 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR
no Sb/Br)
SON
3000 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR
no Sb/Br)
DSBGA
DSBGA
SON
3000 Green (RoHS &
no Sb/Br)
SNAGCU
Level-1-260C-UNLIM
8
250 Green (RoHS &
no Sb/Br)
SNAGCU
Level-1-260C-UNLIM
10
10
8
3000 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR
no Sb/Br)
SON
3000 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR
no Sb/Br)
DSBGA
DSBGA
SON
3000 Green (RoHS &
no Sb/Br)
SNAGCU
Level-1-260C-UNLIM
8
250 Green (RoHS &
no Sb/Br)
SNAGCU
Level-1-260C-UNLIM
10
10
8
3000 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR
no Sb/Br)
SON
3000 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR
no Sb/Br)
DSBGA
DSBGA
SON
3000 Green (RoHS &
no Sb/Br)
SNAGCU
Level-1-260C-UNLIM
8
250 Green (RoHS &
no Sb/Br)
SNAGCU
Level-1-260C-UNLIM
10
10
8
3000 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR
no Sb/Br)
SON
3000 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR
no Sb/Br)
DSBGA
DSBGA
DSBGA
3000 Green (RoHS &
no Sb/Br)
SNAGCU
SNAGCU
SNAGCU
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
8
250 Green (RoHS &
no Sb/Br)
8
3000 Green (RoHS &
no Sb/Br)
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
15-Nov-2007
Orderable Device
TPS62311YZDT
TPS62313YZDR
TPS62313YZDT
Status (1)
ACTIVE
ACTIVE
ACTIVE
Package Package
Pins Package Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)
Qty
Type
Drawing
DSBGA
YZD
8
8
8
250 Green (RoHS &
no Sb/Br)
SNAGCU
SNAGCU
SNAGCU
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
DSBGA
DSBGA
YZD
YZD
3000 Green (RoHS &
no Sb/Br)
250 Green (RoHS &
no Sb/Br)
TPS62315YZR
TPS62315YZT
TPS62320DRCR
PREVIEW DIESALE
PREVIEW DIESALE
YZ
YZ
8
8
3000
250
TBD
TBD
Call TI
Call TI
Call TI
Call TI
ACTIVE
SON
DRC
10
3000 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR
no Sb/Br)
TPS62320DRCRG4
ACTIVE
SON
DRC
10
3000 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR
no Sb/Br)
TPS62320YEDR
TPS62320YEDT
TPS62320YZDR
ACTIVE
ACTIVE
ACTIVE
DSBGA
DSBGA
DSBGA
YED
YED
YZD
8
8
8
3000
250
TBD
TBD
SNPB
SNPB
Level-1-240C-UNLIM
Level-1-240C-UNLIM
Level-1-260C-UNLIM
3000 Green (RoHS &
no Sb/Br)
SNAGCU
TPS62320YZDT
TPS62321DRCR
TPS62321DRCRG4
ACTIVE
ACTIVE
ACTIVE
DSBGA
SON
YZD
DRC
DRC
8
250 Green (RoHS &
no Sb/Br)
SNAGCU
Level-1-260C-UNLIM
10
10
3000 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR
no Sb/Br)
SON
3000 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR
no Sb/Br)
TPS62321YEDR
TPS62321YEDT
TPS62321YZDR
ACTIVE
ACTIVE
ACTIVE
DSBGA
DSBGA
DSBGA
YED
YED
YZD
8
8
8
3000
250
TBD
TBD
SNPB
SNPB
Level-1-240C-UNLIM
Level-1-240C-UNLIM
Level-1-260C-UNLIM
3000 Green (RoHS &
no Sb/Br)
SNAGCU
TPS62321YZDT
ACTIVE
DSBGA
YZD
8
250 Green (RoHS &
no Sb/Br)
SNAGCU
Level-1-260C-UNLIM
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and
package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS
compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
Addendum-Page 2
PACKAGE OPTION ADDENDUM
www.ti.com
15-Nov-2007
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
Addendum-Page 3
PACKAGE MATERIALS INFORMATION
www.ti.com
23-Oct-2007
TAPE AND REEL BOX INFORMATION
Device
Package Pins
Site
Reel
Reel
A0 (mm)
B0 (mm)
K0 (mm)
P1
W
Pin1
Diameter Width
(mm) (mm) Quadrant
(mm)
330
178
178
330
178
178
330
178
178
330
178
178
330
178
178
330
178
178
178
(mm)
12
8
TPS62300DRCR
TPS62300YZDR
TPS62300YZDT
TPS62301DRCR
TPS62301YZDR
TPS62301YZDT
TPS62302DRCR
TPS62302YZDR
TPS62302YZDT
TPS62303DRCR
TPS62303YZDR
TPS62303YZDT
TPS62304DRCR
TPS62304YZDR
TPS62304YZDT
TPS62305DRCR
TPS62305YZDR
TPS62305YZDT
TPS62311YZDR
DRC
YZD
YZD
DRC
YZD
YZD
DRC
YZD
YZD
DRC
YZD
YZD
DRC
YZD
YZD
DRC
YZD
YZD
YZD
10
8
SITE 60
SITE 68
SITE 68
SITE 60
SITE 68
SITE 68
SITE 60
SITE 68
SITE 68
SITE 60
SITE 68
SITE 68
SITE 60
SITE 68
SITE 68
SITE 60
SITE 68
SITE 68
SITE 68
3.3
1.12
1.12
3.3
3.3
2.13
2.13
3.3
1.1
0.71
0.71
1.1
8
4
4
8
4
4
8
4
4
8
4
4
8
4
4
8
4
4
4
12
8
Q2
Q1
Q1
Q2
Q1
Q1
Q2
Q1
Q1
Q2
Q1
Q1
Q2
Q1
Q1
Q2
Q1
Q1
Q1
8
8
8
10
8
12
8
12
8
1.12
1.12
3.3
2.13
2.13
3.3
0.71
0.71
1.1
8
8
8
10
8
12
8
12
8
1.12
1.12
3.3
2.13
2.13
3.3
0.71
0.71
1.1
8
8
8
10
8
12
8
12
8
1.12
1.12
3.3
2.13
2.13
3.3
0.71
0.71
1.1
8
8
8
10
8
12
8
12
8
1.12
1.12
3.3
2.13
2.13
3.3
0.71
0.71
1.1
8
8
8
10
8
12
8
12
8
1.12
1.12
1.12
2.13
2.13
2.13
0.71
0.71
0.71
8
8
8
8
8
8
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
23-Oct-2007
Device
Package Pins
Site
Reel
Reel
A0 (mm)
B0 (mm)
K0 (mm)
P1
W
Pin1
Diameter Width
(mm) (mm) Quadrant
(mm)
180
178
178
178
330
178
178
178
178
330
178
178
178
178
(mm)
8
TPS62311YZDR
TPS62311YZDT
TPS62313YZDR
TPS62313YZDT
TPS62320DRCR
TPS62320YEDR
TPS62320YEDT
TPS62320YZDR
TPS62320YZDT
TPS62321DRCR
TPS62321YEDR
TPS62321YEDT
TPS62321YZDR
TPS62321YZDT
YZD
YZD
YZD
YZD
DRC
YED
YED
YZD
YZD
DRC
YED
YED
YZD
YZD
8
8
SITE 12
SITE 68
SITE 68
SITE 68
SITE 60
SITE 68
SITE 68
SITE 68
SITE 68
SITE 60
SITE 68
SITE 68
SITE 68
SITE 68
1.11
1.12
1.12
1.12
3.3
2.11
2.13
2.13
2.13
3.3
0.81
0.71
0.71
0.71
1.1
4
4
4
4
8
4
4
4
4
8
4
4
4
4
8
8
Q1
Q1
Q1
Q1
Q2
Q1
Q1
Q1
Q1
Q2
Q1
Q1
Q1
Q1
8
8
8
8
8
8
8
10
8
12
8
12
8
1.12
1.12
1.12
1.12
3.3
2.13
2.13
2.13
2.13
3.3
0.71
0.71
0.71
0.71
1.1
8
8
8
8
8
8
8
8
8
10
8
12
8
12
8
1.12
1.12
1.12
1.12
2.13
2.13
2.13
2.13
0.71
0.71
0.71
0.71
8
8
8
8
8
8
8
8
8
Device
Package
Pins
Site
Length (mm) Width (mm) Height (mm)
TPS62300DRCR
TPS62300YZDR
TPS62300YZDT
DRC
YZD
YZD
10
8
SITE 60
SITE 68
SITE 68
342.9
195.2
195.2
336.6
193.7
193.7
20.64
34.9
34.9
8
Pack Materials-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
23-Oct-2007
Device
Package
Pins
Site
Length (mm) Width (mm) Height (mm)
TPS62301DRCR
TPS62301YZDR
TPS62301YZDT
TPS62302DRCR
TPS62302YZDR
TPS62302YZDT
TPS62303DRCR
TPS62303YZDR
TPS62303YZDT
TPS62304DRCR
TPS62304YZDR
TPS62304YZDT
TPS62305DRCR
TPS62305YZDR
TPS62305YZDT
TPS62311YZDR
TPS62311YZDR
TPS62311YZDT
TPS62313YZDR
TPS62313YZDT
TPS62320DRCR
TPS62320YEDR
TPS62320YEDT
TPS62320YZDR
TPS62320YZDT
TPS62321DRCR
TPS62321YEDR
TPS62321YEDT
TPS62321YZDR
TPS62321YZDT
DRC
YZD
YZD
DRC
YZD
YZD
DRC
YZD
YZD
DRC
YZD
YZD
DRC
YZD
YZD
YZD
YZD
YZD
YZD
YZD
DRC
YED
YED
YZD
YZD
DRC
YED
YED
YZD
YZD
10
8
SITE 60
SITE 68
SITE 68
SITE 60
SITE 68
SITE 68
SITE 60
SITE 68
SITE 68
SITE 60
SITE 68
SITE 68
SITE 60
SITE 68
SITE 68
SITE 68
SITE 12
SITE 68
SITE 68
SITE 68
SITE 60
SITE 68
SITE 68
SITE 68
SITE 68
SITE 60
SITE 68
SITE 68
SITE 68
SITE 68
342.9
195.2
195.2
342.9
195.2
195.2
342.9
195.2
195.2
342.9
195.2
195.2
342.9
195.2
195.2
195.2
220.0
195.2
195.2
195.2
342.9
195.2
195.2
195.2
195.2
342.9
195.2
195.2
195.2
195.2
336.6
193.7
193.7
336.6
193.7
193.7
336.6
193.7
193.7
336.6
193.7
193.7
336.6
193.7
193.7
193.7
220.0
193.7
193.7
193.7
336.6
193.7
193.7
193.7
193.7
336.6
193.7
193.7
193.7
193.7
20.64
34.9
34.9
20.64
34.9
34.9
20.64
34.9
34.9
20.64
34.9
34.9
20.64
34.9
34.9
34.9
34.0
34.9
34.9
34.9
20.64
34.9
34.9
34.9
34.9
20.64
34.9
34.9
34.9
34.9
8
10
8
8
10
8
8
10
8
8
10
8
8
8
8
8
8
8
10
8
8
8
8
10
8
8
8
8
Pack Materials-Page 3
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Customers should obtain the latest relevant information before placing orders and should verify that such information is current and
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Following are URLs where you can obtain information on other Texas Instruments products and application solutions:
Products
Amplifiers
Data Converters
DSP
Applications
Audio
amplifier.ti.com
dataconverter.ti.com
dsp.ti.com
www.ti.com/audio
Automotive
Broadband
Digital Control
Military
www.ti.com/automotive
www.ti.com/broadband
www.ti.com/digitalcontrol
www.ti.com/military
Interface
interface.ti.com
logic.ti.com
Logic
Power Mgmt
Microcontrollers
RFID
power.ti.com
Optical Networking
Security
www.ti.com/opticalnetwork
www.ti.com/security
www.ti.com/telephony
www.ti.com/video
microcontroller.ti.com
www.ti-rfid.com
www.ti.com/lpw
Telephony
Low Power
Wireless
Video & Imaging
Wireless
www.ti.com/wireless
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