TPS62320DRCT [TI]
IC,SMPS CONTROLLER,VOLTAGE-MODE,CMOS,LLCC,10PIN,PLASTIC;
| 型号： | TPS62320DRCT |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | IC,SMPS CONTROLLER,VOLTAGE-MODE,CMOS,LLCC,10PIN,PLASTIC 光电二极管 |
| 文件： | 总25页 (文件大小：789K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
TPS62300, TPS62301, TPS62302
TPS62303, TPS62304, TPS62305
CSP-8
QFN-10
TPS62306, TPS62320, TPS62321
www.ti.com
SLVS528–JULY 2004
500-mA, 3-MHz SYNCHRONOUS STEP-DOWN CONVERTER
IN CHIP SCALE PACKAGING
FEATURES
DESCRIPTION
•
•
•
•
•
•
Up to 93% Efficiency at 3-MHz Operation
The TPS623xx device is a high-frequency synchron-
ous step-down dc-dc converter optimized for
battery-powered portable applications. Intended for
low-power applications, the TPS623xx supports up to
500-mA load current and allows the use of tiny, low
cost chip inductor and capacitors.
Up to 500-mA Output Current at VI = 2.7 V
3-MHz Fixed Frequency Operation
Best in Class Load and Line Transient
Complete 1-mm Component Profile Solution
-0.5% / +1.3% PWM DC Voltage Accuracy Over
Temperature
The device is ideal for mobile phones and similar
portable applications powered by a single-cell Li-Ion
battery or by 3-cell NiMH/NiCd batteries. With an
output voltage range from 5.4 V down to 0.6 V, the
device supports low-voltage DSPs and processors in
smart-phones, PDAs as well as notebooks, and
handheld computers.
•
•
35-ns Minimum On-Time
Power-Save Mode Operation at Light Load
Currents
•
•
•
•
Fixed and Adjustable Output Voltage
Only 86-µA Quiescent Current
The TPS62300 operates at 3-MHz fixed switching
frequency and enters the power-save mode operation
at light load currents to maintain high efficiency over
the entire load current range. For low noise appli-
cations, the device can be forced into fixed frequency
PWM mode by pulling the MODE/SYNC pin high. The
device can also be synchronized to an external clock
signal in the range of 3 MHz. In the shutdown mode,
the current consumption is reduced to less than 1 µA.
100% Duty Cycle for Lowest Dropout
Synchronizable On the Fly to External
Clock Signal
•
•
Integrated Active Power-Down Sequencing
(TPS6232x only)
Available in a 10-Pin QFN (3 x 3 mm) and
8-Pin NanoFree™ and NanoStar™ (CSP)
Packaging
The TPS623xx is available in a 10-pin leadless
package (3 × 3 mm QFN) and an 8-pin chip-scale
package (CSP).
APPLICATIONS
•
•
•
•
•
•
Cell Phones, Smart-Phones
WLAN and Bluetooth™ Applications
Micro DC-DC Converter Modules
PDAs, Pocket PCs
USB-Based DSL Modems
Digital Cameras
100
V = 3.6 V,
I
90
80
70
60
50
40
30
20
V
= 1.8 V
O
TPS62303YZD
L1
2.7 V . . 6 V
V
A2
B2
B1
D1
C2
D2
O
VIN
EN
SW
1.8 V/500 mA
V
C2
1 µH
I
C1
VOUT
4.7 µF
C1
A1
L = 2.2 µH,
4.7 µF
MODE/SYNC
GND
ADJ
FB
10
0
C
O
= 4.7 µF
0.1
1
10
100
1 k
I
− Load Current − mA
O
Figure 1. Smallest Solution Size Application
(Fixed Output Voltage)
Figure 2. Efficiency vs Load Current
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Bluetooth is a trademark of Bluetooth SIG, Inc.
NanoFree, NanoStar are trademarks of Texas Instruments.
PowerPAD is a trademark of Texas Instsruments.
PRODUCT PREVIEW information concerns products in the forma-
tive or design phase of development. Characteristic data and other
specifications are design goals. Texas Instruments reserves the
right to change or discontinue these products without notice.
Copyright © 2004, Texas Instruments Incorporated
TPS62300, TPS62301, TPS62302
TPS62303, TPS62304, TPS62305
TPS62306, TPS62320, TPS62321
www.ti.com
SLVS528–JULY 2004
ORDERING INFORMATION
PART
OUTPUT
VOLTAGE
PACKAGE
MARKING
TA
PACKAGE
ORDERING
NUMBER(1)
QFN-10
CSP-8 (lead-free)
QFN-10
TPS62300DRC
TPS62300YZD
TPS62301DRC
TPS62301YZD
TPS62302DRC
TPS62302YZD
TPS62303DRC
TPS62303YZD
TPS62304DRC
TPS62304YZD
TPS62305DRC
TPS62306DRC
TPS62320DRC
TPS62320YZD
TPS62320YED
TPS62321DRC
TPS62321YZD
TPS62321YED
AMN
N/A
TPS62300
TPS62301
TPS62302
TPS62303
TPS62304
Adjustable
1.5 V
AMO
N/A
CSP-8 (lead-free)
QFN-10
AMQ
N/A
1.6 V
CSP-8 (lead-free)
QFN-10
AMR
N/A
1.8 V
CSP-8 (lead-free)
QFN-10
AMS
N/A
-40°C to 85°C
1.2 V
CSP-8 (lead-free)
QFN-10
TPS62305
TPS62306
1.875 V
1.9 V
ANU
ANV
AMX
N/A
QFN-10
QFN-10
TPS62320
TPS62321
Adjustable
1.5 V
CSP-8 (lead-free)
CSP-8
N/A
QFN-10
AMY
N/A
CSP-8 (lead-free)
CSP-8
N/A
(1) The YZ package is available in tape and reel. Add R suffix (TPS62300YZR) to order quantities of 3000 parts. Add T suffix
(TPS62300YxDT) to order quantities of 250 parts
ABSOLUTE MAXIMUM RATINGS
over operating free-air temperature range (unless otherwise noted)(1)
UNIT
Voltage at VIN, AVIN(2)
-0.3 V to 7.0 V
(2)
Voltage at SW
-0.3 V to 7.0 V
-0.3V to 3.6 V
-0.3 V to VIN + 0.3 V
0.3 V to 5.4 V
Internally limited
-40°C to 85°C
150°C
VI
Voltage at FB, ADJ
(2)
Voltage at EN, MODE/SYNC
Voltage at VOUT(2)
Power dissipation
TA
Operating temperature range
TJ (max) Maximum operating junction temperature
Tstg Storage temperature range
-65°C to 150°C
(1) Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings
only and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating
conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) All voltage values are with respect to network ground terminal.
DISSIPATION RATINGS(1)
POWER RATING
FOR TA≤ 25°C
DERATING FACTOR
ABOVE TA = 25°C
PACKAGE
RθJA
DRC
YZD
YED
49°C/W
250°C/W
250°C/W
2050 mW
400 mW
400 mW
21 mW/°C
4 mW/°C
4 mW/°C
(1) Maximum power dissipation is a function of TJ(max), θJA and TA. The maximum allowable power dissipation at any allowable ambient
temperature is PD = [TJ(max)-TA] / θJA
2
TPS62300, TPS62301, TPS62302
TPS62303, TPS62304, TPS62305
TPS62306, TPS62320, TPS62321
www.ti.com
SLVS528–JULY 2004
ELECTRICAL CHARACTERISTICS
VI = 3.6 V, VO = 1.6 V, EN = VI, MODE/SYNC = GND, L = 1 µH, CO = 10 µF, TA = -40°C to 85°C, typical values are at
TA = 25°C (unless otherwise noted)
PARAMETER
SUPPLY CURRENT
TEST CONDITIONS
MIN
TYP
MAX
UNIT
VI
Input voltage range
2.7
6.0
V
IO = 0 mA. PFM mode enabled, device not switching
86
105
µA
IQ
Operating quiescent current
IO = 0 mA. Switching with no load
(MODE/SYNC = VIN)
3.6
mA
I(SD)
Shutdown current
EN = GND
0.1
1.0
µA
V
V(UVLO)
Undervoltage lockout threshold
2.40
2.55
ENABLE, MODE/SYNC
V(EN)
EN high-level input voltage
1.2
1.3
V
V
V(MODE/SYNC)
MODE/SYNC high-level input voltage
V(EN)
V(MODE/SYNC)
,
EN, MODE/SYNC low-level input
voltage
0.4
1.0
V
I(EN)
,
EN, MODE/SYNC input leakage
current
EN, MODE/SYNC = GND or VIN
0.01
µA
I(MODE/SYNC)
POWER SWITCH
VI = V(GS) = 3.6 V
VI = V(GS) = 2.8 V
V(DS) = 6.0 V
420
520
750
1000
1
mΩ
mΩ
µA
rDS(on)
P-channel MOSFET on resistance
I(LK_PMOS)
rDS(on)
P-channel leakage current
VI = V(GS) = 3.6 V
VI = V(GS) = 2.8 V
330
400
750
1000
mΩ
mΩ
N-channel MOSFET on resistance
Discharge resistor for power-down
sequence (TPS6232x only)
R(DIS)
30
50
Ω
I(LK_NMOS)
N-channel leakage current
P-MOS current limit
V(DS) = 6.0 V
1
890
µA
mA
mA
mA
2.7 V ≤ VI ≤ 6.0 V
2.7 V ≤ VI ≤ 6.0 V
2.7 V ≤ VI ≤ 6.0 V
670
550
780
720
N-MOS current limit - sourcing
N-MOS current limit - sinking
890
–460
–600
–740
Input current limit under short-circuit
conditions
VO = 0 V
390
mA
Thermal shutdown
150
20
°C
°C
Thermal shutdown hysteresis
OSCILLATOR
fSW
Oscillator frequency
2.65
2.65
20%
3.0
3.35
3.35
80%
MHz
MHz
f(SYNC)
Synchronization range
Duty cycle of external clock signal
3
TPS62300, TPS62301, TPS62302
TPS62303, TPS62304, TPS62305
TPS62306, TPS62320, TPS62321
www.ti.com
SLVS528–JULY 2004
ELECTRICAL CHARACTERISTICS (continued)
VI = 3.6 V, VO = 1.6 V, EN = VI, MODE/SYNC = GND, L = 1 µH, CO = 10 µF, TA = -40°C to 85°C, typical values are at
TA = 25°C (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
OUTPUT
Adjustable output
voltage range
TPS62300
TPS62320
VO
0.6
5.4
V
V
Regulated feedback
voltage
TPS62300
TPS62320
V(FB)
0.4
1.5
35
DC power train amplification
(VO/V(ADJ)
A(PT)
1.496
1.504
1300
)
Minimum on-time (P-channel
MOSFET)
ton(MIN)
ns
Resistance into VOUT sense pin
Resistance into ADJ pin
700
700
1000
1000
kΩ
kΩ
V(FB) > 0.4 V
V(FB) = 0.4 V
Feedback input bias
current
TPS62300
TPS62320
I(FB)
1
nA
Adjustable output
voltage(1)
TPS62300
TPS62320
–2.0%
–2.0%
+2.0%
+2.0%
2.7 V ≤ VI≤ 6.0 V, 0 mA ≤ IO(DC)≤ 500 mA
PFM/PWM mode operation
TPS6230x
TPS6232x
Fixed output voltage
TPS62305
–2.0%
–0.5%
+2.7%
+1.3%
Adjustable output
voltage DC accu-
racy(1)
TA = 25°C
TPS62300
TPS62320
VO
–40°C ≤ TA ≤ 85°C
–0.5%
+1.3%
TA = 25°C
–0.5%
–0.5%
–0.3%
–0.5%
+1.3%
+1.3%
+1.7%
+2.0%
–0.002
PWM mode operation,
VI = 3.6 V, No Load
TPS6230x
TPS6232x
–40°C ≤ TA ≤ 85°C
TA = 25°C
Fixed output voltage
DC accuracy
TPS62305
–40°C ≤ TA ≤ 85°C
DC output voltage load regulation
IO = 0 mA to 500 mA, MODE/SYNC = VI
–0.001
%/mA
%/mA
DC output voltage load regulation
(power train in direct drive mode)
V(ADJ) externally forced to 1.067 V,
IO = 0 mA to 500 mA, MODE/SYNC = VI
–0.0003 –0.0006
VI = VO + 0.5 V (min 2.7 V) to
6.0 V, IO = 100 mA, MODE/SYNC = VI
DC output voltage line regulation
0.11
0.2
%/V
%/V
V(ADJ) externally forced to 1.067 V,
VI = VO + 0.5 V (min 2.7 V) to 6.0 V, IO = 100 mA,
MODE/SYNC = VI
DC output voltage line regulation
(power train in direct drive mode)
0.035
0.1
Integrator slew rate
100
150
0.025 VO
250
200
µV/µs
VP-P
µs
∆VO
Power-save mode ripple voltage
Start-up time
IO = 1 mA, MODE/SYNC = GND
IO = 200 mA, Time from active EN to VO
VI > VO, 0 V ≤ V(SW) ≤ VIN, EN = GND
VI = open, V(SW) = 6.0 V, EN = GND
Leakage current into SW pin
Reverse leakage current into SW pin
0.1
1
1
I(LK_SW)
µA
0.1
(1) Output voltage specification for the adjustable version does not include tolerance of external voltage programming resistors.
4
TPS62300, TPS62301, TPS62302
TPS62303, TPS62304, TPS62305
TPS62306, TPS62320, TPS62321
www.ti.com
SLVS528–JULY 2004
PIN ASSIGNMENTS
TPS62300, TPS62320
QFN−10
TPS6230x, TPS6232x
Fixed Output Voltage (QFN−10)
(TOP VIEW)
(TOP VIEW)
VIN
AVIN
EN
SW
PGND
MODE/SYNC
AGND
VIN
AVIN
EN
SW
PGND
MODE/SYNC
AGND
ADJ
NC
FB
VOUT
NC
VOUT
TPS6230x, TPS6232x
TPS6230x, TPS6232x
CSP−8
CSP−8
(TOP VIEW)
(BOTTOM VIEW)
A2
B2
C2
D2
A1
B1
C1
D1
A1
A2
GND
VIN
EN
GND
VIN
EN
SW
MODE/SYNC
VOUT
B1
C1
D1
B2
C2
D2
SW
ADJ
FB
MODE/SYNC
VOUT
ADJ
FB
TERMINAL FUNCTIONS
TERMINAL
I/O
DESCRIPTION
NO.
QFN
NO.
CSP
NAME
VIN
1
2
A2
I
I
Supply voltage for output power stage.
AVIN
This is the input voltage pin of the device. Connect directly to the input bypass capacitor.
This is the enable pin of the device. Connecting this pin to ground forces the device into shutdown
mode. Pulling this pin to VI enables the device. This pin must not be left floating and must be
terminated.
EN
3
B2
I
This is the internal reference voltage used to regulate VO. This pin is not connected on fixed output
voltage version of TPS6230xDRC and TPS6232xDRC. Do not connect ADJ pin on fixed output
voltage version of TPS6230xYZD and TPS6232xYED.
ADJ
4
C2
I/O
On TPS62300 and TPS62320, this pin can also be used as an external control input. The output
voltage is 1.5x the applied voltage at ADJ.
This is the feedback pin of the device. For the adjustable version, an external resistor divider is
connected to this pin. The internal voltage divider is disabled for the adjustable version. This pin is
not connected on fixed output voltage version of TPS6230xDRC and TPS6232xDRC. Do not
connect the FB pin on the fixed output voltage version of TPS6230xYZD and TPS6232xYED.
FB
5
D2
D1
I
I
VOUT
AGND
6
7
Output feedback sense input. Connect VOUT to the converter’s output.
Analog ground. Connect to PGND via the PowerPAD™ underneath IC.
Input for synchronization to external clock signal. This pin must not be left floating and must be
terminated. Synchronizes the converter switching frequency to an external clock signal
MODE/SYNC = LOW (GND): The device is operating in fixed frequency pulse width modulation
mode (PWM) at high-load currents and in pulse frequency modulation mode (PFM) at light load
currents.
MODE/SYNC
8
C1
I
MODE/SYNC = HIGH (VIN): Low-noise mode enabled, fixed frequency PWM operation forced.
Power ground.
PGND
9
A1
B1
This is the switch pin of the converter and is connected to the drain of the internal Power
MOSFETs.
SW
10
I/O
PowerPAD™
N/A Internally connected to PGND.
5
TPS62300, TPS62301, TPS62302
TPS62303, TPS62304, TPS62305
TPS62306, TPS62320, TPS62321
www.ti.com
SLVS528–JULY 2004
FUNCTIONAL BLOCK DIAGRAM
MODE/SYNC
EN
VIN
N-MOS Current Limit
Compator
Undervoltage
Lockout
AVIN
Bias Supply
_
Soft-Start
V
= 0.4 V
REF
Band Gap
REF
Power-Save
Mode
+
3-MHz
Oscillator + PLL
Sawtooth
Thermal
Shutdown
+
_
Comp Low
Generator
Switching
Logic
REF
P-MOS Current Limit
Compator
RAMP HEIGHT
∫
0.1 V
IN
2R
C
R
−
+
−
VOUT
−
+
+
−
−
SW
Gate Driver
2C
R
(DIS)
Anti
+
+
+
+
V
REF
Shoot-Through
+
EN
Summing
Comparator
_
A
= 3
(DC)
FB
P
TPS6232x
Only
Mid-, High-Frequency
Zero-Pole Pair
P
R2
See note A
R1
A
VOUT
PGND
Comparator Low
ADJ
+
_
A
−1.5% V
OUT(NOMINAL)
AGND
NOTE A: For the adjustable versions (TPS62300 and TPS62320) the internal feedback divider is disabled.
PARAMETER MEASUREMENT INFORMATION
U1
L1
V
1
2
3
10
6
O
AVIN
VIN
SW
VOUT
ADJ
1.6 V/500 mA
C2
2.7 V . . 6 V
C1
10 WF
R1
4
V
EN
I
8
7
5
9
MODE/SYNC
FB
AGND
PGND
R2
A
A
A
List of Components:
U1 = TPS6230x
L1 = FDK MIPW3226 Series
C1, C2 = X5R/X7R
6
TPS62300, TPS62301, TPS62302
TPS62303, TPS62304, TPS62305
TPS62306, TPS62320, TPS62321
www.ti.com
SLVS528–JULY 2004
TYPICAL CHARACTERISTICS
Table of Graphs
FIGURE
vs Load current
vs Input voltage
3, 4, 5, 6
η
Efficiency
7
8
Line transient response
Load transient response
9, 10, 11, 12,
13, 14, 15, 16
VO
VFB
IQ
DC output voltage
vs Load current
vs Temperature
vs Input voltage
vs Temperature
17
18
Regulated feedback voltage
No load quiescent current
Switching frequency
19
fs
20
Duty cycle jitter
21
P-channel MOSFET rDS(on)
N-channel MOSFET rDS(on)
PWM operation
vs Input voltage
vs Input voltage
22
rDS(on)
23
24
Power-save mode operation
Dynamic voltage management
Start-up
25
26, 27
28, 29
30
Power down (TPS6232x)
EFFICIENCY
vs
LOAD CURRENT
EFFICIENCY
vs
LOAD CURRENT
100
90
80
70
60
50
40
30
20
100
90
80
70
60
50
40
30
20
10
0
PFM/PWM Operation
L = 2.2 WH
V = 3.6 V,
PFM/PWM Operation
L = 2.2 WH
V = 3.6 V,
I
I
V
O
= 1.6 V
V
O
= 1.8 V
PFM/PWM Operation
L = 0.9 WH
PWM Operation
L = 0.9 WH
PWM Operation
L = 2.2 WH
10
0
0.1
1
10
100
1000
0.1
1
10
100
1000
I
O
− Load Current − mA
I
O
− Load Current − mA
Figure 3.
Figure 4.
7
TPS62300, TPS62301, TPS62302
TPS62303, TPS62304, TPS62305
TPS62306, TPS62320, TPS62321
www.ti.com
SLVS528–JULY 2004
TYPICAL CHARACTERISTICS (continued)
EFFICIENCY
vs
LOAD CURRENT
EFFICIENCY
vs
LOAD CURRENT
90
100
90
80
70
60
50
40
30
20
10
0
PFM/PWM Operation
L = 2.2 WH
PFM/PWM Operation
L = 2.2 WH
80
70
60
PWM Operation
L = 2.2 WH
50
40
30
20
PWM Operation
L = 0.9 WH
V = 3.6 V,
I
V = 5 V,
I
10
0
V
O
= 1.2 V
V
O
= 3.3 V
0.1
1
10
100
1000
0.1
1
10
100
1000
I
O
− Load Current − mA
I
O
− Load Current − mA
Figure 5.
Figure 6.
EFFICIENCY
vs
INPUT VOLTAGE
LINE TRANSIENT RESPONSE
100
90
80
70
60
50
40
30
20
10
0
I
= 100 mA
V
O
= 1.6 V
O
L = 0.9 WH, C = 10 WF
O
I
= 400 mA
O
I
O
= 1 mA
I
O
= 10 mA
PFM/PWM Operation
= 1.8 V
V
O
2.7
3
3.3 3.6 3.9 4.2 4.5 4.8 5.1 5.4 5.7 6
t − Time − 100 Ws/div
V − Input Voltage − V
I
Figure 7.
Figure 8.
8
TPS62300, TPS62301, TPS62302
TPS62303, TPS62304, TPS62305
TPS62306, TPS62320, TPS62321
www.ti.com
SLVS528–JULY 2004
TYPICAL CHARACTERISTICS (continued)
LOAD TRANSIENT RESPONSE IN
PWM OPERATION
LOAD TRANSIENT RESPONSE IN
PWM OPERATION
V = 3.6 V,
MODE/SYNC = HIGH
L = 0.9 WH, C = 10 WF
V = 3.6 V,
I
I
V
O
= 1.6 V
V
O
= 1.6 V
O
MODE/SYNC = HIGH
L = 0.9 WH, C = 10 WF
O
I
O
= 10 to 100 mA Load Step
I
O
= 10 to 100 mA Load Step
I
O
= 10 to 400 mA Load Step
I
O
= 10 to 400 mA Load Step
t − Time − 2 Ws/div
t − Time − 50 Ws/div
Figure 9.
Figure 10.
LOAD TRANSIENT RESPONSE IN
PWM OPERATION
LOAD TRANSIENT RESPONSE
IN PFM MODE
V = 3.6 V,
V = 3.6 V,
I
V = 1.6 V
O
L = 0.9 WH, C = 10 WF
I
MODE/SYNC = HIGH
L = 0.9 WH, C = 10 WF
O
V
O
= 1.6 V
O
I
O
= 400 to 10 mA Load Step
I
O
= 100 to 10 mA Load Step
PFM Operation
t - Time - 2 Ws/div
t − Time − 50 Ws/div
Figure 11.
Figure 12.
9
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TYPICAL CHARACTERISTICS (continued)
LOAD TRANSIENT RESPONSE IN
PWM OPERATION
LOAD TRANSIENT RESPONSE IN
PWM OPERATION
V = 3.6 V,
O
V = 3.6 V,
I
O
I
MODE/SYNC = HIGH
L = 0.9 WH, C = 4.7 WF
V
= 1.6 V
V
= 1.6 V
O
MODE/SYNC = HIGH
L = 0.9 WH, C = 4.7 WF
O
I
O
= 10 to 100 mA Load Step
I
O
= 10 to 100 mA Load Step
I
O
= 10 to 400 mA Load Step
I
O
= 10 to 400 mA Load Step
t - Time - 2 Ws/div
t - Time - 50 Ws/div
Figure 13.
Figure 14.
LOAD TRANSIENT RESPONSE IN
PFM OPERATION
LOAD TRANSIENT RESPONSE IN
PFM OPERATION
V = 3.6 V,
O
V = 3.6 V,
O
I
I
MODE/SYNC = HIGH
L = 0.9 WH, C = 4.7 WF
L = 0.9 WH, C = 4.7 WF
O
V
= 1.6 V
V
= 1.6 V
O
I
O
= 400 to 10 mA Load Step
I
O
= 100 to 10 mA Load Step
PFM Operation
t - Time - 2 Ws/div
t - Time - 50 Ws/div
Figure 16.
Figure 15.
10
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TYPICAL CHARACTERISTICS (continued)
OUTPUT VOLTAGE
vs
LOAD CURRENT
REGULATED FEEDBACK VOLTAGE
vs
TEMPERATURE
1.628
406
405.5
405
V = 3.6 V, V = 1.6 V,
L = 2.2 WH
I
O
TPS62300
1.618
1.608
PWM Operation
404.5
404
V = 3.6 V
I
V = 4.2 V
I
1.598
1.588
403.5
403
PFM/PWM Operation
V = 2.7 V
I
1.578
1.568
402.5
402
0.1
1
10
100
1000
-40 -30 -20 -10
0
10 20 30 40 50 60 70 80 85
I
O
− Load Current − mA
T
A
- Ambient Temperature - 5C
Figure 17.
Figure 18.
QUIESCENT CURRENT
vs
OSCILLATOR FREQUENCY
vs
INPUT VOLTAGE
INPUT VOLTAGE
3.3
3.25
3.2
96
94
92
90
88
86
84
82
80
T
= −405C
A
T
= 255C
A
T
= 855C
A
3.15
3.1
T
A
= 255C
= 855C
T
A
3.05
3
T
= −405C
A
MODE/SYNC = HIGH
2.95
2.9
2.7
3
3.3 3.6 3.9 4.2 4.5 4.8 5.1 5.4 5.7
6
2.7
3
3.3 3.6 3.9 4.2 4.5 4.8 5.1 5.4 5.7
6
V − Input Voltage − V
I
V − Input Voltage − V
I
Figure 19.
Figure 20.
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TYPICAL CHARACTERISTICS (continued)
P-CHANNEL rDS(ON)
vs
INPUT VOLTAGE
DUTY CYCLE JITTER
700
650
600
550
500
450
400
350
300
250
200
150
V = 3.6 V, V = 1.6 V,
I
O
L = 0.9 WH, C = 10 WF
O
I
= 320 mA
TRIGGER ON RISING EDGE
O
T
= 855C
A
T
= 255C
A
T
= −405C
A
MODE/SYNC = HIGH
2.5
3
3.5
4
4.5
5
5.5
6
t - Time - 25 ns/div
V − Input Voltage − V
I
Figure 21.
Figure 22.
N-CHANNEL rDS(ON)
vs
INPUT VOLTAGE
PWM OPERATION
550
500
450
400
350
300
250
200
150
I
= 200 mA
O
L = 0.9 WH, C = 10 WF
O
T
= 855C
A
T
= 255C
A
T
A
= −405C
V = 3.6 V, V = 1.6 V
I
O
2.5
3
3.5
4
4.5
5
5.5
6
t − Time − 200 ns/div
V − Input Voltage − V
I
Figure 23.
Figure 24.
12
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TYPICAL CHARACTERISTICS (continued)
POWER-SAVE MODE OPERATION
DYNAMIC VOLTAGE MANAGEMENT
V = 3.6 V,
I
O
V
= 1 V / 1.5 V
V = 1.5 V
O
V
O
= 1 V
V
(ADJ)
= 1 V
V
(ADJ)
= 0.67 V
L = 0.9 H, C = 10 F,
O
V = 3.6 V, V = 1.6 V
I
O
MODE/SYNC = LOW
L = 0.9 WH, C = 10 WF
O
I
O
= 40 mA
R
L
= 270 W
t − Time − 20 s/div
t − Time − 2 Ws/div
Figure 25.
Figure 26.
DYNAMIC VOLTAGE MANAGEMENT
V = 3.6 V,
START-UP
I
V
V = 3.6 V,
I
= 1 V / 1.5 V
O
V = 1.5 V
O
V
= 1.6 V,
O
I
= 0 mA
O
V
O
= 1 V
V
(ADJ)
= 0.67 V
V
(ADJ)
= 1 V
R
L
= 5 W
L = 0.9 H, C = 10 F,
O
MODE/SYNC = HIGH
L = 2.2 WH, C = 4.7 WF,
O
t − Time − 20 s/div
t − Time − 50 Ws/div
Figure 28.
Figure 27.
13
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TYPICAL CHARACTERISTICS (continued)
START-UP
POWER DOWN (TPS62321)
V = 3.6 V,
I
V = 3.6 V,
I
V
I
= 1.5 V,
O
V
= 1.6 V,
= 0 mA
O
O
I
= 320 mA
O
L = 0.9 WH, C = 10 WF
O
L = 2.2 WH, C = 4.7 WF,
O
t − Time − 400 Ws/div
Figure 30.
t − Time − 50 Ws/div
Figure 29.
DETAILED DESCRIPTION
OPERATION
The TPS6230x and TPS6232x are synchronous step-down converters typically operating with a 3-MHz fixed
frequency pulse width modulation (PWM) at moderate to heavy load currents. At light load currents, the converter
operates in power-save mode with pulse frequency modulation (PFM). The operating frequency is set to 3 MHz
and can be synchronized on-the-fly to an external oscillator.
During PWM operation, the converter uses a unique fast response, voltage mode, controller scheme with input
voltage feed-forward. This achieves best-in-class load and line response and allows the use of tiny inductors and
small ceramic input and output capacitors. At the beginning of each switching cycle, the P-channel MOSFET
switch is turned on and the inductor current ramps up until the comparator trips and the control logic turns off the
switch.
The device integrates two current limits, one in the P-channel MOSFET and another one in the N-channel
MOSFET. When the current in the P-channel MOSFET reaches its current limit, the P-channel MOSFET is
turned off and the N-channel MOSFET is turned on. When the current in the N-channel MOSFET is above the
N-MOS current limit threshold, the N-channel MOSFET remains on until the current drops below its current limit.
The current limit in the N-channel MOSFET is important for small duty-cycle operation when the current in the
inductor does not decrease because of the P-channel MOSFET current limit delay, or because of start-up
conditions where the output voltage is low.
POWER-SAVE MODE
With decreasing load current, the device automatically switches into pulse skipping operation in which the power
stage operates intermittently based on load demand. By running cycles periodically, the switching losses are
minimized, and the device runs with a minimum quiescent current and maintaining high efficiency.
In power-save mode, the converter only operates when the output voltage trips below a set threshold voltage
(-1.5% VO(NOMINAL)). It ramps up the output voltage with several pulses and goes into power-save mode once the
output voltage exceeds the nominal output voltage. As a consequence, the average output voltage is slightly
lower than its nominal value in the power-save mode operation.
14
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DETAILED DESCRIPTION (continued)
V
O(NOMINAL)
3-MHz Operation
Comp Low Thershold
−1.5% V
O(NOMIAL)
Figure 31. Power-Save Mode Threshold
MODE SELECTION AND FREQUENCY SYNCHRONIZATION
The MODE/SYNC pin is a multipurpose pin which allows mode selection and frequency synchronization.
Connecting this pin to GND enables the automatic PWM and power-save mode operation. The converter
operates in fixed frequency PWM mode at moderate to heavy loads and in the PFM mode during light loads,
which maintains high efficiency over a wide load current range.
Pulling the MODE/SYNC pin high forces the converter to operate in the PWM mode even at light load currents.
The advantage is that the converter operates with a fixed frequency that allows simple filtering of the switching
frequency for noise-sensitive applications. In this mode, the efficiency is lower compared to the power-save
mode during light loads. For additional flexibility, it is possible to switch from power-save mode to forced PWM
mode during operation. This allows efficient power management by adjusting the operation of the converter to
the specific system requirements.
The TPS6230x and TPS6232x can also be synchronized to an external 3-MHz clock signal by the MODE/SYNC
pin. During synchronization, the mode is set to fixed-frequency operation and the P-channel MOSFET turnon is
synchronized to the falling edge of the external clock. This creates the ability for multiple converters to be
connected together in a master-slave configuration for frequency matching of the converters (see the application
section for more details, Figure 37).
SOFT START
The TPS6230x and TPS6232x have an internal soft-start circuit that limits the inrush current during start-up. This
prevents possible input voltage drops when a battery or a high-impedance power source is connected to the
input of the converter. The soft start is implemented as a digital circuit increasing the switch current in steps of
typically 195 mA, 390 mA, 585 mA, and the typical switch current limit of 780 mA. Therefore, the start-up time
mainly depends on the output capacitor and load current.
LOW-DROPOUT OPERATION 100% DUTY CYCLE
In 100% duty cycle mode, the TPS6230x and TPS6232x offer a low input-to-output voltage difference. In this
mode, the P-channel MOSFET is constantly turned on. This is particularly useful in battery-powered applications
to achieve the longest operation time by taking full advantage of the whole battery voltage range. The minimum
input voltage to maintain regulation, depending on the load current and output voltage, can be calculated as:
•
•
•
•
•
VI(MIN) = VO(MAX) + IO(MAX)× (rDS(on) MAX + RL)
IO(MAX) : Maximum output current
rDS(on) MAX : Maximum P-channel switch rDS(on)
RL : DC resistance of the inductor
VO(MAX) : nominal output voltage plus maximum output voltage tolerance
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DETAILED DESCRIPTION (continued)
ENABLE
The device starts operation when EN is set high and starts up with the soft start as previously described.
Pulling the EN pin low forces the device into shutdown, with a shutdown quiescent current of typically 0.1 µA. In
this mode, the P and N-channel MOSFETs are turned off, the internal resistor feedback divider is disconnected,
and the entire internal-control circuitry is switched off. When an output voltage is present during shutdown mode,
which can be caused by an external voltage source or super capacitor, the reverse leakage is specified under
electrical characteristics. For proper operation, the EN pin must be terminated and must not be left floating.
In addition, the TPS6232x devices integrate a resistor, typically 35 Ω, to actively discharge the output capacitor
when the device turns off. The required time to discharge the output capacitor at VO depends on load current.
UNDERVOLTAGE LOCKOUT
The undervoltage lockout circuit prevents the device from misoperation at low input voltages. It prevents the
converter from turning on the switch or rectifier MOSFET under undefined conditions.
SHORT-CIRCUIT PROTECTION
As soon as the output voltage falls below 50% of the nominal output voltage, the converter current limit is
reduced by 50% of the nominal value. Because the short-circuit protection is enabled during start-up, the device
does not deliver more than half of its nominal current limit until the output voltage exceeds 50% of the nominal
output voltage. This needs to be considered when a load acting as a current sink is connected to the output of
the converter.
THERMAL SHUTDOWN
As soon as the junction temperature, TJ, exceeds typically 150°C, the device goes into thermal shutdown. In this
mode, the P- and N-channel MOSFETs are turned off. The device continues its operation when the junction
temperature falls below typically 130°C again.
APPLICATION INFORMATION
ADJUSTABLE OUTPUT VOLTAGE
When the adjustable output voltage versions, TPS62300 or TPS62320, are used, the output voltage is set by the
external resistor divider (see Figure 32).
The output voltage is calculated as:
R1
R2
ǒ1 ) Ǔwith an internal reference voltage V
V
ń 1.5 V
typical ń 0.4 V
O
ref
ref
(1)
To keep the operating quiescent current to a minimum, it is recommended that R2 be set in the range of 300 kΩ
to 500 kΩ. Route the FB line away from noise sources, such as the inductor or the SW line.
TPS62300
L1
1
2
3
8
7
10
6
V
O
AVIN
VIN
EN
SW
2.7 V . . 6 V
C2 1.6 V/500 mA
VOUT
R1
4.7 WF
C1
4
V
I
ADJ
5
4.7 WF
MODE/SYNC
FB
9
AGND
PGND
R2
A
A
A
Figure 32. Adjustable Output Voltage Version
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APPLICATION INFORMATION (continued)
OUTPUT FILTER DESIGN (INDUCTOR AND OUTPUT CAPACITOR)
The TPS6230x and TPS6232x series of step-down converters have internal loop compensation. Therefore, the
external L-C filter must be selected to work with the internal compensation.
The device has been designed to operate with inductance values between a minimum of 0.7 µH and maximum of
6.2 µH. The internal compensation is optimized to operate with an output filter of L = 1 µH and CO = 10 µF. Such
an output filter has its corner frequency at:
1
1
ƒ )
)
) 50.3 kHz
c
ń
2p ńL C
2p 1 qH 10 qF
O
(2)
Operation with a higher corner frequency (e.g., L = 1 µH, CO = 4.7 µF) is possible. However, it is recommended
the loop stability be checked in detail. Selecting a larger output capacitor value (e.g., 22 µF) is less critical
because the corner frequency moves to lower frequencies with fewer stability problems. The possible output filter
combinations are listed in Table 1.
Regardless of the inductance value, operation is recommended with 10-µF output capacitor in applications with
di
)
dt
high-load transients
(e.g., ≥ 1600 mA/µs).
Table 1. Output Filter Combinations
INDUCTANCE (L)
1.0 µH
OUTPUT CAPACITANCE (CO)
≥ 4.7 µF (ceramic capacitor)
≥ 2.2 µF (ceramic capacitor)
2.2 µH
The inductor value also has an impact on the pulse skipping operation. The transition into power-save mode
begins when the valley inductor current goes below a level set internally. Lower inductor values result in higher
ripple current which occurs at lower load currents. This results in a dip in efficiency at light load operations.
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INDUCTOR SELECTION
Even though the inductor does not influence the operating frequency, the inductor value has a direct effect on the
ripple current. The selected inductor has to be rated for its dc resistance and saturation current. The inductor
ripple current (∆IL) decreases with higher inductance and increases with higher VI or VO.
V
V ń V
q I
O
I
O
L
q I
ǒ
q I
ǒ
I
)
L
L(MAX)
O(MAX)
2
V
L ƒ
sw
I
(3)
with: fSW = switching frequency (3 MHz typical)
L = inductor value
∆IL = peak-to-peak inductor ripple current
IL(MAX) = maximum inductor current
Normally, it is advisable to operate with a ripple of less than 30% of the average output current. Accepting larger
values of ripple current allows the use of low inductances, but results in higher output voltage ripple, greater core
losses, and lower output current capability.
The total losses of the coil consist of both the losses in the DC resistance (R(DC)) and the following
frequency-dependent components:
•
•
•
•
The losses in the core material (magnetic hysteresis loss, especially at high switching frequencies)
Additional losses in the conductor from the skin effect (current displacement at high frequencies)
Magnetic field losses of the neighboring windings (proximity effect)
Radiation losses
The following inductor series from different suppliers have been used with the TPS6230x and TPS6232x
converters.
Table 2. List of Inductors
MANUFACTURER
SERIES
DIMENSIONS
FDK
MIPW3226
LQ CB2016
LQ CB2012
LQ CBL2012
VLF3010AT
WE-TPC XS
3.2 × 2.6 × 1.0 = 8.32 mm3
2.0 × 1.6 × 1.6 = 5.12 mm3
2.0 × 1.2 × 1.2 = 2.88 mm3
2.0 × 1.2 × 1.0 = 2.40 mm3
2.8 × 2.6 × 1.0 = 7.28 mm3
3.3 × 3.5 × 0.95 = 10.97 mm3
Taiyo Yuden
TDK
Wuerth Elektronik
OUTPUT CAPACITOR SELECTION
The advanced fast-response voltage mode control scheme of the TPS6230x and TPS6232x allows the use of
tiny ceramic capacitors. Ceramic capacitors with low ESR values have the lowest output voltage ripple and are
recommended. The output capacitor requires either an X7R or X5R dielectric. Y5V and Z5U dielectric capacitors,
aside from their wide variation in capacitance over temperature, become resistive at high frequencies.
At nominal load current, the device operates in PWM mode and the overall output voltage ripple is the sum of the
voltage spike caused by the output capacitor ESR plus the voltage ripple caused by charging and discharging the
output capacitor:
V
V ń V
O
I
O
1
q V
ǒ
) ESR , maximum for high V
Ǔ
O
I
V
L ƒ
8 C ƒ
sw
sw
I
O
(4)
At light loads, the device operates in power-save mode and the output voltage ripple is independent of the output
capacitor value. The output voltage ripple is set by the internal comparator thresholds and propagation delays.
The typical output voltage ripple is 1.5% of the nominal output voltage VO.
18
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INPUT CAPACITOR SELECTION
Because of the nature of the buck converter having a pulsating input current, a low ESR input capacitor is
required to prevent large voltage transients that can cause misbehavior of the device or interferences with other
circuits in the system. For most applications, a 2.2-µF or 4.7-µF capacitor is sufficient.
Take care when using only ceramic input capacitors. When a ceramic capacitor is used at the input and the
power is being supplied through long wires, such as from a wall adapter, a load step at the output can induce
ringing at the VIN pin. This ringing can couple to the output and be mistaken as loop instability or could even
damage the part.
CHECKING LOOP STABILITY
The first step of circuit and stability evaluation is to look from a steady-state perspective at the following signals:
•
•
•
Switching node, SW
Inductor current, IL
Output ripple voltage, VO(AC)
These are the basic signals that need to be measured when evaluating a switching converter. When the
switching waveform shows large duty cycle jitter or the output voltage or inductor current shows oscillations, the
regulation loop may be unstable. This is often a result of board layout and/or L-C combination.
As a next step in the evaluation of the regulation loop, the load transient response is tested. The time between
the application of the load transient and the turn on of the P-channel MOSFET, the output capacitor must supply
all of the current required by the load. VO immediately shifts by an amount equal to ∆I(LOAD) × ESR, where ESR
is the effective series resistance of CO. ∆I(LOAD) begins to charge or discharge CO generating a feedback error
signal used by the regulator to return VO to its steady-state value.
During this recovery time, VO can be monitored for settling time, overshoot or ringing that helps judge the
converter’s stability. Without any ringing, the loop has usually more than 45° of phase margin.
Because the damping factor of the circuitry is directly related to several resistive parameters (e.g., MOSFET
rDS(on)) that are temperature dependant, the loop stability analysis has to be done over the input voltage range,
load current range, and temperature range.
PROGRAMMING THE OUTPUT VOLTAGE WITH A DAC
On TPS62300 and TPS62320 devices, the output voltage can be dynamically programmed to any voltage
between 0.6 V and VI (or 5.4 V whichever is lower) with an external DAC driving the ADJ and FB pins (see
Figure 33). The output voltage is then equal to A(PT)× V(DAC) with a Power Train amplification A(PT) typical = 1.5.
When the output voltage is driven low, the converter reduces its output quickly in forced PWM mode, boosting
the output energy back to the input. If the input is not connected to a low-impedance source capable of absorbing
the energy, the input voltage can rise above the absolute maximum voltage of the part and get damaged. The
faster VO is commanded low, the higher is the voltage spike at the input.
For best results, ramp the ADJ/FB signal as slow as the application allows. To avoid over-slew of the regulation
loop of the converter, avoid abrupt changes in output voltage of > 300 mV/µs (depending on VI , output voltage
step size and L/C combination). If ramp control is unavailable, an RC filter can be inserted between the DAC
output and ADJ/FB pins to slow down the control signal.
V
= 1.5 x V
(DAC)
TPS62300
AVIN
VIN
O
L
1
2
3
8
7
10
6
SW
VOUT
ADJ
C
O
C
I
4
EN
V
I
V
(DAC)
R
F
5
MODE/SYNC FB
10 kW
9
AGND
PGND
C
F
A
A
A
Figure 33. Filtering the DAC Voltage
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LAYOUT CONSIDERATIONS
As for all switching power supplies, the layout is an important step in the design. High-speed operation of the
TPS6230x and TPS6232x devices demand careful attention to PCB layout. Care must be taken in board layout
to get the specified performance. If the layout is not carefully done, the regulator could show poor line and/or
load regulation, stability issues as well as EMI problems. It is critical to provide a low inductance, impedance
ground path. Therefore, use wide and short traces for the main current paths as indicated in bold on Figure 34.
The input capacitor should be placed as close as possible to the IC pins as well as the inductor and output
capacitor. Use a common ground node for power ground and a different one for control ground (AGND) to
minimize the effects of ground noise. Connect these ground nodes together (star point) underneath the IC and
make sure that small signal components returning to the AGND pin do not share the high current path of C1 and
C2.
The output voltage sense line (VOUT) should be connected right to the output capacitor and routed away from
noisy components and traces (e.g., SW line). Its trace should be minimized and shielded by a guard-ring
connected to the reference ground. The voltage setting resistive divider should be placed as close as possible to
the AGND pin of the IC.
TPS62300
L1
V
O
1
2
3
8
7
10
6
AVIN
VIN
EN
SW
VOUT
ADJ
V
I
C2
R1
4
C1
5
MODE/SYNC
FB
9
AGND
R2
PGND
Figure 34. Layout Diagram
VO
GND
VI
VO sense signal
EN
MODE / SYNC
Figure 36. Suggested QFN Layout (Bottom)
GND
Figure 35. Suggested QFN Layout (Top)
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THERMAL INFORMATION
Implementation of integrated circuits in low-profile and fine-pitch surface-mount packages typically requires
special attention to power dissipation. Many system-dependant issues such as thermal coupling, airflow, added
heat sinks, and convection surfaces, and the presence of other heat-generating components, affect the
power-dissipation limits of a given component
Three basic approaches for enhancing thermal performance are listed below:
•
•
•
Improving the power dissipation capability of the PCB design
Improving the thermal coupling of the component to the PCB
Introducing airflow in the system
The maximum recommended junction temperature (TJ) of the TPS6230x and TPS6232x devices is 125°C. The
thermal resistance of the 8-pin CSP package (YZD and YED) is RθJA = 250°C/W. Specified regulator operation is
assured to a maximum ambient temperature TA of 85°C. Therefore, the maximum power dissipation is about
160 mW. More power can be dissipated if the maximum ambient temperature of the application is lower or if the
PowerPAD™ package (DRC) is used.
T
T
J(MAX)
R
A
125°C 85°C
250°CńW
P
)
)
) 160 mW
D(MAX)
qJA
(5)
CHIP SCALE PACKAGE DIMENSIONS
The TPS6230x and TPS6232x are also available in an 8-bump chip scale package (YZD, NanoFree™ and YED,
NanoStar™). The package dimensions are given as:
•
•
D = 1.970 ±0.05 mm
E = 0.970 ±0.05 mm
21
TPS62300, TPS62301, TPS62302
TPS62303, TPS62304, TPS62305
TPS62306, TPS62320, TPS62321
www.ti.com
SLVS528–JULY 2004
APPLICATION EXAMPLES
TPS62303YZD
A2
B2
D1
B1
C2
2.7 V − 6 V
VIN
EN
VOUT
SW
L
Ch1
Ch2
1
V
C
OUT
IN
10 µF
V
IN
1.8 V / 500 mA
C
1
C1
A1
MODE/SYNC ADJ
10 µF
D2
FB
GND
Ch4
TPS62304YZD
L
2
V
A2
B2
B1
D1
C2
OUT
VIN
EN
SW
1.2 V / 500 mA
C
2
Ch3
VOUT
10 µF
C1
A1
MODE/SYNC ADJ
1G08
Ch1: SW (1.8-V Output), Ch2: I
Ch3: SW (1.2-V Output), Ch4: I
D2
L1
L2
FB
GND
Low: None Synchronized Operation
PFM/PWM Automatic Switch
High: Synchronized Operation
Forced 3 MHz Fixed Frequency Operation
List of Components:
L1, L2 = Taiyo Yuden LQ CB2016
, C1, C2, = X5R/X7R Ceramic Capacitor
C
IN
Figure 37. Dual, Out-of-Phase, 3-MHz, 500-mA Step-Down Regulator
Features Less Than 50-mm2 Total Solution Size
EN
Fast Start−Up LDO
22 nF
10 kΩ
V
= 0.98 x V
OUT(NOM)
OUT(LDO)
EN
EN
VOUT
VIN
GND
2.2 MΩ
TPS62300YZD
2.7 V . . 6 V
V
O
A2
B2
D1
VIN
EN
VOUT
SW
V
OUT
C
B1
C2
IN
10 µF
V
L1
1 µH
IN
C1
1.8 V / 500 mA
I
L1
C1
A1
V = 2.8 V,
I
MODE/SYNC ADJ
FB
10 µF
R
L
= 10 W
D2
GND
Ch1: V
Ch3: Inductor Current: I
Ch3: EN − External Control Signal
O
List of Components:
L1 = Taiyo Yuden LQ CB2016
, C1 = X5R/X7R Ceramic Capacitor
L1
C
IN
Figure 38. Speed-Up Circuitry for Fast Turnon Time
22
TPS62300, TPS62301, TPS62302
TPS62303, TPS62304, TPS62305
TPS62306, TPS62320, TPS62321
www.ti.com
SLVS528–JULY 2004
TPS62300
1.8
VIN
VOUT
SW
Default Voltage =
2.7 V − 6 V
L1
R1
1.6
1.4
1.2
1
C
I
1.5 x V x 1+
ref ( R2)
V
EN
OUT
V
IN
2.2 µH
R1
C1
10 µF
MODE/SYNC ADJ
4.7 µF
9.5 kΩ
FB
GND
R2
8.2 kΩ
0.8
0.6
0.4
DAC6571
2.85 V
VDD
SDA
SCL
A0
DAC Control Range
= 1.5 x 0.98 x V
2
I C I/F
VDAC
0.2
0
V
O
(DAC)
GND
0
0.2
0.4 0.6
0.8
1
1.2
1.4
V
− Control Voltage − V
(DAC)
List of Components:
L1 = Wuerth Elektronik WE-TPC XS
C , C1, = X5R/X7R Ceramic Capacitor
I
Figure 39. Dynamic Voltage Management Using I2C I/F
23
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