TPS61325YFF_技术文档

TPS61325

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SLVS977 –FEBRUARY 2010

1.5A/4.1A Multiple LED Camera Flash Driver With I²C^TMCompatible Interface

1

FEATURES

DESCRIPTION

23

•

Four Operational Modes

The TPS6132x device is based on a high-frequency

synchronous boost topology with constant current

sinks to drive up to three white LEDs in parallel

(445mA/890mA/445mA maximum flash current). The

extended high-current mode (HC_SEL) allows up

to 1025mA/2050mA/1025mA flash current out of

the storage capacitor.

–

DC Light and Flashlight

Voltage Regulated Converter: 3.8V...5.7V

Standby: 2mA (typ.)

•

Storage Capacitor Friendly Solution

Automatic V_Fand ESR Calibration

The high-capacity storage capacitor on the output of

the boost regulator provides the high-peak flash LED

current, thereby reducing the peak current demand

from the battery to a minimum.

Power-Save Mode for Improved Efficiency at

Low Output Power, Up to 95% Efficiency

•

Output Voltage Remains Regulated When

Input Voltage Exceeds Nominal Output Voltage

I²C Compatible Interface up to 3.4Mbits/s

Dual Wire Camera Module Interface

Zero Latency Tx-Masking Input

LED Temperature Monitoring

Privacy Indicator LED Output

Integrated LED Safety Timer

The 2-MHz switching frequency allows the use of

small and low profile 2.2mH inductors. To optimize

overall efficiency, the device operates with a 400mV

LED feedback voltage.

•

The TPS6132x device not only operates as a

regulated current source, but also as a standard

voltage boost regulator. The device keeps the output

voltage regulated even when the input voltage

exceeds the nominal output voltage. The device

enters power-save mode operation at light load

currents to maintain high efficiency over the entire

load current range.

GPIO/Flash Ready Output

Total Solution Size of Less Than 25 mm²

(<1mm height)

•

Available in a 20-Pin NanoFree™ (CSP)

To simplify DC light and flashlight synchronization

APPLICATIONS

with the camera module, the device offers

a

dedicated control interface (STRB0, STRB1) for zero

latency LED turn-on time.

•

Single/Dual/Triple White LED Flashlight Supply

for Cell Phones and Smart-Phones

•

LED Based Xenon "Killer" Flashlight

TPS61325

L

SW

VOUT

2.2 mH

AVIN

C_O

10mF

2.5 V..5.5 V

HC_SEL

C_I

BAL

D1

D2

4.7mF

PHONE POWER ON

LED1

LED2

LED3

STRB0

STRB1

SCL

SDA

I²C I/F

INDLED

Privacy

Indicator

1.8V

Tx-MASK

TS

GPIO/PG

NTC

PGND

AGND

FLASH READY

Figure 1. Typical Application

1

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas

Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

2

3

NanoFree is a trademark of Texas Instruments.

I²C is a trademark of NXP Semiconductors.

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of the Texas

Instruments standard warranty. Production processing does not

necessarily include testing of all parameters.

TPS61325

SLVS977 –FEBRUARY 2010

www.ti.com

This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with

appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.

ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more

susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.

AVAILABLE OPTIONS

PART NUMBER⁽¹⁾

PACKAGE MARKING

PACKAGE

DEVICE SPECIFIC FEATURES⁽²⁾

Dual Wire Camera Module Interface (STRB0, STRB1)

LED Temperature Monitoring Input (TS)

TPS61325YFF

61325

CSP-20

(1) The YFF package is available in tape and reel. Add R suffix (TPS6132xYFFR) to order quantities of 3000 parts per reel, T suffix for 250

parts per reel.

(2) For more details, refer to the section Application Diagrams.

ABSOLUTE MAXIMUM RATINGS

over operating free-air temperature range (unless otherwise noted)

(1)

VALUE

–0.3 to 7

±25

UNIT

V

Voltage range on AVIN, VOUT, SW, LED1, LED2, LED3⁽²⁾

Voltage range on SCL, SDA, STRB0, STRB1, GPIO/PG⁽²⁾

V_I

V

(2)

Voltage range on HC_SEL, Tx-MASK, TS, BAL

V

Current on GPIO/PG

mA

Power dissipation

Internally limited

–40 to 85

150

(3)

T_A

Operating ambient temperature range

Maximum operating junction temperature

Storage temperature range

Human body model

°C

kV

V

T_{J (MAX)}

T_stg

–65 to 150

2

(4)

ESD rating

Charge device model

500

Machine model

100

V

(1) Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings

only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating

conditions is not implied. Exposure to absolute–maximum–rated conditions for extended periods may affect device reliability.

(2) All voltage values are with respect to network ground terminal.

(3) In applications where high power dissipation and/or poor package thermal resistance is present, the maximum ambient temperature may

have to be derated. Maximum ambient temperature [T_A(max)] is dependent on the maximum operating junction temperature [T_J(max)], the

maximum power dissipation of the device in the application [P_D(max)], and the junction-to-ambient thermal resistance of the part/package

in the application (q_JA), as given by the following equation: T_A(max)= T_J(max)– (q_JA× P_D(max)

)

(4) The human body model is a 100-pF capacitor discharged through a 1.5-kΩ resistor into each pin. The machine model is a 200-pF

capacitor discharged directly into each pin.

DISSIPATION RATINGS

PACKAGE

THERMAL RESISTANCE⁽¹⁾

POWER RATING

T_A= 25°C

DERATING FACTOR

ABOVE⁽²⁾T_A= 25°C

q_JA

q_JB

YFF

71°C/W

21°C/W

1.4 W

14mW/°C

(1) Simulated with high-K board

(2) Maximum power dissipation is a function of T_J(max), q_JAand T_A. The maximum allowable power dissipation at any allowable ambient

temperature is P_D= (T_J(max)– T_A)/ q_JA

.

2

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SLVS977 –FEBRUARY 2010

ELECTRICAL CHARACTERISTICS

Unless otherwise noted the specification applies for V_IN= 3.6V over an operating junction temp. –40°C ≤ T_J≤ 125°C; Circuit

of Parameter Measurement Information section (unless otherwise noted). Typical values are for T_J= 25°C.

PARAMETER

SUPPLY CURRENT

TEST CONDITIONS

MIN

TYP MAX UNIT

V_IN

Input voltage range

2.5

5.5

V

I_OUT= 0 mA, device not switching

–40°C ≤ T_J≤ +85°C

mA

590

700

I_Q

Operating quiescent current into AVIN

I_OUT(DC)= 0mA, PWM operation

V_OUT= 4.95V, voltage regulation mode

mA

11.3

1

I_SD

Shutdown current

Standby current

Pre-charge current

HC_SEL = 0, –40°C ≤ T_J≤ +85°C

5

mA

HC_SEL = 1, storage capacitor balanced

–40°C ≤ T_J≤ +85°C

I_STBY

2

0V ≤ V_OUT≤ 3.3V, device in pre-charge mode

–40°C ≤ T_J≤ +85°C

mA

80

40

180

220

3.6

Pre-charge termination threshold

V_OUTrising, –40°C ≤ T_J≤ +85°C

3.35

75

V

mV

V

Pre-charge hysteresis (referred to V_OUT

)

V_UVLO

Undervoltage lockout threshold

(analog circuitry)

V_INfalling

2.3

2.4

OUTPUT

Current regulation mode

Voltage regulation mode

VIN

5.5

5.7

V

Output voltage range

3.825

V_OUT

2.5V ≤ V_IN≤ 4.8V, –20°C ≤ T_J≤ +125°C

Boost mode, PWM voltage regulation

Internal feedback voltage accuracy

Power-save mode ripple voltage

–2%

2%

I_OUT= 10 mA

0.015 V_OUT

4.65

V_P-P

V

V_OUTrising, 0000 ≤ OV[3:0] ≤ 0100

V_OUTrising, 0101 ≤ OV[3:0] ≤ 1111

V_OUTfalling, 0101 ≤ OV[3:0] ≤ 1111

4.5

5.8

4.8

6.2

Output overvoltage protection

OVP

6.0

V

Output overvoltage protection hysteresis

POWER SWITCH

r_DS(on)Switch MOSFET on-resistance

0.15

V

V_OUT= V_GS= 3.6 V

90

135

0.3

mΩ

mA

Rectifier MOSFET on-resistance

Leakage into SW

V_OUT= V_GS= 3.6 V

I_lkg(SW)

V_OUT= 0V, SW = 3.6V, –40°C ≤ T_J≤ +85°C

4

VOUT = 4.95V, HC_SEL = 0

–20°C ≤ T_J≤ +85°C

PWM operation, ILIM bit = 0

775

1050

-85

1150 1600

1600 2225

mA

(1)

VOUT = 4.95V, HC_SEL = 0

–20°C ≤ T_J≤ +85°C

PWM operation, ILIM bit = 1⁽¹⁾

I_lim

Rectifier valley current limit (open-loop)

VOUT = 4.95V, HC_SEL = 1, Tx-MASK = 0

–20°C ≤ T_J≤ +85°C

30

150

300

PWM operation, ILIM bit = 0⁽¹⁾

VOUT = 4.95V, HC_SEL = 1, Tx-MASK = 0

–20°C ≤ T_J≤ +85°C

175

250

PWM operation, ILIM bit = 1

OSCILLATOR

f_OSCOscillator frequency

f_ACCOscillator frequency

1.92

MHz

%

–10

140

–8

+7

8

THERMAL SHUTDOWN, HOT DIE DETECTOR

Thermal shutdown⁽¹⁾

160

20

°C

Thermal shutdown hysteresis⁽¹⁾

Hot die detector accuracy⁽¹⁾

(1) Verified by characterization. Not tested in production.

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ELECTRICAL CHARACTERISTICS (Continued)

Unless otherwise noted the specification applies for V_IN= 3.6V over an operating junction temp. –40°C ≤ T_J≤ 125°C; Circuit

of Parameter Measurement Information section (unless otherwise noted). Typical values are for T_J= 25°C.

PARAMETER

LED CURRENT REGULATOR

TEST CONDITIONS

MIN

TYP

MAX UNIT

0.4V ≤ V_LED1/3≤ 2.0V

0mA < ILED1/3 ≤ 111mA, T_J= +85°C

–10

–7.5

–10

–7.5

–10

+10

+7.5

+10

+7.5

+10

%

LED1/3 current accuracy⁽¹⁾

0.4V ≤ V_LED2≤ 2.0V

ILED1/3 > 111mA, T_J= +85°C

HC_SEL = 0

0.4V ≤ V_LED2≤ 2.0V

0mA < ILED2 ≤ 250mA, T_J= +85°C

LED2 current accuracy⁽¹⁾

LED1/3 current accuracy⁽¹⁾

0.4V ≤ V_LED2≤ 2.0V

ILED2 > 250mA, T_J= +85°C

0.4V ≤ V_LED1/3≤ 2.0V

0mA < ILED1/3 ≤ 1027mA, T_J= +85°C

HC_SEL = 1

HC_SEL = 0

0.4V ≤ V_LED2≤ 2.0V

0mA < ILED2 ≤ 2052mA, T_J= +85°C

LED2 current accuracy⁽¹⁾

LED1/3 current matching⁽¹⁾

–10

+10

V_LED1/3= 1.0V, I_LED1/3= 444mA, T_J= +85°C

–7.5

+7.5

%

LED1/2/3 current temperature coefficient

0.05

%/°C

1.5V ≤ (VIN-VINDLED) ≤ 2.5V

0000 ≤ INDC[3:0] ≤ 0111

T_J= +25°C

INDLED current accuracy

–20

+20

%

INDLED current temperature coefficient

LED1/2/3 sense voltage

0.04

400

%/°C

mV

I_LED1-3= full-scale current, HC_SEL = 0

I_LED1-3= full-scale current, HC_SEL = 1

LED1/2/3 sense voltage

450

200

mV

V_DO

I_OUT= -15.8mA, T_J= +25°C, device not

switching

VOUT dropout voltage

mV

LED1/2/3 input leakage current

INDLED input leakage current

V_LED1/2/3= V_OUT= 5V, –40°C ≤ T_J≤ +85°C

V_INDLED= 0V, –40°C ≤ T_J≤ +85°C

0.1

4

1

mA

(1) Verified by characterization. Not tested in production.

4

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SLVS977 –FEBRUARY 2010

ELECTRICAL CHARACTERISTICS

Unless otherwise noted the specification applies for V_IN= 3.6V over an operating junction temp. –40°C ≤ T_J≤ 125°C; Circuit

of Parameter Measurement Information section (unless otherwise noted). Typical values are for T_J= 25°C.

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX UNIT

STORAGE CAPACITOR ACTIVE CELL BALANCING

Active cell balancing circuitry

quiescent current into VOUT

HC_SEL = 1, storage capacitor balanced

–40°C ≤ T_J≤ +85°C

1.7

3.0

mA

(VOUT – BAL) vs. BAL voltage difference

Storage capacitor balanced HC_SEL = 1

V_OUT= 5.7V

Active cell balancing accuracy

–100

±10

100

mV

BAL output drive capability

Active discharge resistor

V_OUT= 4.95V, Sink and source current

±15

mA

HC_SEL = 0, device in shutdown mode

VOUT to BAL and BAL to GND

0.85

1.5

kΩ

LED TEMPERATURE MONITORING

I_O(TS)

Temperature Sense Current Source

Thermistor bias current

23.8

44.5

14.5

mA

kΩ

TS Resistance (Warning Temperature) LEDWARN bit = 1, T_J≥ 25°C

TS Resistance (Hot Temperature) LEDHOT bit = 1, T_J≥ 25°C

SDA, SCL, GPIO/PG, Tx-MASK, STRB0, STRB1, HC_SEL

39

50

12.5

16.5

V_(IH)

V_(IL)

High-level input voltage

1.2

V

Low-level input voltage

0.4

0.3

Low-level output voltage (SDA)

Low-level output voltage (GPIO)

High-level output voltage (GPIO)

I_OL= 8mA

V_(OL)

DIR = 1, I_OL= 5mA

V_(OH)

I_(LKG)

DIR = 1, GPIOTYPE = 0, I_OH= 8mA

V_IN–0.4

Input connected to VIN or GND

–40°C ≤ T_J≤ +85°C

Logic input leakage current

0.01

0.1

mA

STRB0, STRB1 pull-down resistance

Tx-MASK pull-down resistance

HC_SEL pull-down resistance

SDA Input Capacitance

STRB0, STRB1 ≤ 0.4 V

Tx-MASK ≤ 0.4 V

350

9

kΩ

pF

R_PD

HC_SEL ≤ 0.4 V

SDA = VIN or GND

SCL Input Capacitance

SCL = VIN or GND

4

GPIO/PG Input Capacitance

STRB0 Input Capacitance

STRB1 Input Capacitance

HC_SEL Input Capacitance

Tx-MASK Input Capacitance

DIR = 0, GPIO/PG = VIN or GND

STRB0 = VIN or GND

STRB1 = VIN or GND

HC_SEL = VIN or GND

Tx-MASK = VIN or GND

9

C_(IN)

3

3.5

4

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ELECTRICAL CHARACTERISTICS (continued)

Unless otherwise noted the specification applies for V_IN= 3.6V over an operating junction temp. –40°C ≤ T_J≤ 125°C; Circuit

of Parameter Measurement Information section (unless otherwise noted). Typical values are for T_J= 25°C.

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX UNIT

TIMING

From shutdown into DC light mode

HC_SEL = 0, I_LED= 111mA

Start-up time

1.5

400

16

ms

MODE_CTRL[1:0] = 10, HC_SEL = 0

I_LED2= from 0mA to 890mA

LED current settling time⁽¹⁾triggered

by a rising edge on STRB0

MODE_CTRL[1:0] = 10, HC_SEL = 1

I_LED2= from 0mA to 2050mA

LED current settling time⁽¹⁾triggered

by Tx-MASK

MODE_CTRL[1:0] = 10, HC_SEL = 0

I_LED2= from 890mA to 390mA

15

(1) Settling time to ±15% of the target value.

I²C INTERFACE TIMING CHARACTERISTICS⁽¹⁾

PARAMETER

TEST CONDITIONS

Standard mode

Fast mode

MIN

MAX UNIT

100

400

3.4

1.7

kHz

MHz

ms

High-speed mode (write operation), C_B– 100 pF max

High-speed mode (read operation), C_B– 100 pF max

High-speed mode (write operation), C_B– 400 pF max

High-speed mode (read operation), C_B– 400 pF max

Standard mode

f_(SCL)

SCL Clock Frequency

4.7

1.3

4

Bus Free Time Between a STOP and

START Condition

t_BUF

Fast mode

ms

Standard mode

ms

Hold Time (Repeated) START

Condition

t_HD, t_STA

Fast mode

600

160

4.7

1.3

160

320

4

ns

High-speed mode

ns

Standard mode

ms

Fast mode

ms

t_LOW

LOW Period of the SCL Clock

HIGH Period of the SCL Clock

High-speed mode, C_B– 100 pF max

High-speed mode, C_B– 400 pF max

Standard mode

ns

ms

Fast mode

600

60

ns

t_HIGH

High-speed mode, C_B– 100 pF max

High-speed mode, C_B– 400 pF max

Standard mode

ns

120

4.7

600

160

250

100

10

ns

ms

Setup Time for a Repeated START

Condition

t_SU, t_STA

Fast mode

ns

High-speed mode

ns

Standard mode

ns

t_SU, t_DATData Setup Time

t_HD, t_DATData Hold Time

Fast mode

ns

High-speed mode

ns

Standard mode

0

3.45

0.9

ms

Fast mode

0

ms

High-speed mode, C_B– 100 pF max

High-speed mode, C_B– 400 pF max

Standard mode

0

70

ns

0

150

1000

300

40

ns

20 + 0.1 C_B

10

ns

Fast mode

ns

t_RCL

Rise Time of SCL Signal

High-speed mode, C_B– 100 pF max

High-speed mode, C_B– 400 pF max

ns

20

80

ns

(1) Specified by design. Not tested in production.

6

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I²C INTERFACE TIMING CHARACTERISTICS ⁽¹⁾(continued)

PARAMETER

TEST CONDITIONS

MIN

MAX UNIT

Standard mode

20 + 0.1 C_B

1000

300

80

ns

ms

ns

pF

Rise Time of SCL Signal After a

Repeated START Condition and After

an Acknowledge BIT

Fast mode

20 + 0.1 C_B

t_RCL1

High-speed mode, C_B– 100 pF max

High-speed mode, C_B– 400 pF max

Standard mode

10

20

160

300

40

20 + 0.1 C_B

Fast mode

20 + 0.1 C_B

t_FCL

Fall Time of SCL Signal

Rise Time of SDA Signal

Fall Time of SDA Signal

High-speed mode, C_B– 100 pF max

High-speed mode, C_B– 400 pF max

Standard mode

10

20

80

20 + 0.1 C_B

1000

300

80

Fast mode

20 + 0.1 C_B

t_RDA

High-speed mode, C_B– 100 pF max

High-speed mode, C_B– 400 pF max

Standard mode

10

20

160

300

80

20 + 0.1 C_B

Fast mode

20 + 0.1 C_B

t_FDA

High-speed mode, C_B– 100 pF max

High-speed mode, C_B– 400 pF max

Standard mode

10

20

160

4

t_SU, t_STOSetup Time for STOP Condition

Fast mode

600

160

High-speed mode

C_B

Capacitive Load for SDA and SCL

400

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I²C TIMING DIAGRAMS

SDA

t

f

BUF

t

f

t

LOW

t

r

su;DAT

t

r

hd;STA

SCL

t

su;STO

hd;STA

t

su;STA

hd;DAT

HIGH

S

Sr

P

S

Figure 2. Serial Interface Timing for F/S-Mode

Sr

Sr P

t

fDA

t

rDA

SDAH

t

hd;DAT

t

su;STO

t

su;DAT

su;STA

hd;STA

SCLH

t

fCL

t

rCL1

t

rCL

t

HIGH

LOW

See Note A

= MCS Current Source Pull-Up

= R Resistor Pull-Up

See Note A

(P)

Note A: First rising edge of the SCLH signal after Sr and after each acknowledge bit.

Figure 3. Serial Interface Timing for H/S-Mode

8

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DEVICE INFORMATION

PIN FUNCTIONS

I/O

DESCRIPTION

NAME

AVIN

NO.

E4

A2

E2

E1

E3

B4

I

O

I

This is the input voltage pin of the device. Connect directly to the input bypass capacitor.

This is the output voltage pin of the converter.

VOUT

LED1

LED2

LED3

STRB0

LED return input. This feedback pin regulates the LED current through the internal sense resistor by

regulating the voltage across it. The regulation operates with typically 400mV (HC_SEL = L) or 400mV

(HC_SEL = H) dropout voltage. Connect to the cathode of the LEDs.

I

LED1/2/3 enable logic input. This pin can be used to enable/disable the high-power LEDs connected to the

device.

STRB0 = LOW: LED1, LED2 and LED3 current regulators are turned-off.

STRB0 = HIGH: LED2, LED2 and LED3 current regulators are active. The LED current level (DC light or

flashlight current) is defined according to the STRB1 logic level.

HC_SEL

B3

I

Extended high-current mode selection input. This pin must not be left floating and must be terminated.

HC_SEL = LOW: LED direct drive mode. The power stage is active and the maximum LED currents are

defined as 445mA/890mA/445mA (ILED1/ILED2/ILED3).

HC_SEL = HIGH: Energy storage mode. In flash mode, the power stage is either active with reduced

current capability or disabled. The maximum LED current is defined as 1025mA/2050mA/1025mA

(ILED1/ILED2/ILED3).

SCL

B2

B1

D4

I

Serial interface clock line. This pin must not be left floating and must be terminated.

SDA

I/O Serial interface address/data line. This pin must not be left floating and must be terminated.

GPIO/PG

I/O This pin can either be configured as a general purpose input/output pin (GPIO) or either as an open-drain

or a push-pull output to signal when the converters output voltage is within the regulation limits (PG). Per

default, the pin is configured as an open-drain power-good output.

TS

C4

I/O NTC resistor connection. This pin can be used to monitor the LED temperature. Connect a 220kΩ NTC

resistor from the TS input to ground. In case this functionality is not desired, the TS input should be tied to

AVIN or left floating.

INDLED

STRB1

A1

D3

O

I

This pin provides a constant current source to drive low V_FLEDs. Connect to LED anode.

LED current level selection input. Pulling this input high disables the DC light watchdog timer.

STRB1 = LOW: Flash light mode is enabled.

STRB1 = HIGH: DC light mode is enabled.

Tx-MASK

SW

C3

I

RF PA synchronization control input.

C1

C2

I/O Inductor connection. Drain of the internal power MOSFET. Connect to the switched side of the inductor.

SW is high impedance during shutdown.

BAL

A3

O

Balancing output for dual cells super-capacitor. In steady-state operation, this output compensates for

leakage current mismatch between the cells.

PGND

AGND

D1

D2

Power ground. Connect to AGND underneath IC.

A4

Analog ground.

PIN ASSIGNMENTS

CSP-20

(TOP VIEW)

CSP-20

(BOTTOM VIEW)

D4

D3

D2

D1

E4

E3

E2

E1

B4

B3

B2

B1

A4

A3

A2

A1

B4

B3

B2

B1

C4

C3

C2

C1

D4

D3

D2

D1

C4

C3

C2

C1

A4

A3

A2

A1

E4

E3

E2

E1

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FUNCTIONAL BLOCK DIAGRAM

AVIN

SW

Undervoltage

Lockout

Bias Supply

OVP

COMPARATOR

REF

V

REF = 1.238V

Backgate

Control

Bandgap

VOUT

Hot Die

Indicator

T_ON

Control

ERROR

AMPLIFIER

HC_SEL

S

R

Q

VOUT

V_REF

EN

CONTROL LOGIC

P

VOUT

2

Z

COMPARATOR

BAL

VOLTAGE

REGULATION

CURRENT

REGULATION

VLED Sense

SENSE FB

ON/OFF

LED2

Max t_ONTimer

CURRENT

CONTROL

SCL

SDA

I²C I/F

DAC

P

SENSE FB

ON/OFF

LED1

LED3

Slew-Rate

Controller

CURRENT

CONTROL

Oscillator

DAC

P

STRB1

SENSE FB

STRB0

Tx-MASK

P

Low-Side LED Current Regulator

AVIN

HC_SEL

Control

Logic

350 kΩ

INDLED

INDC[1:0]

AVIN

High-Side LED Current Regulator

23µA

TS

WARNING

HOT

V_REF= 1.05V

V_REF= 0.345V

AGND PGND

10

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TIMER BLOCK DIAGRAM

(GPIO Bit)

Tx-MASK

350 kW

Port Direction

(DIR)

GPIO/PG

CURRENT REGULATOR MODE – DC LIGHT / FLASH ACTIVE

MODE 0 = LOW

MODE 1 = HIGH

Port Type

(PG)

MODE 0

MODE 1

STRB1

STRB0

0

1

350 kW

(GPIO Bit)

PWROK

Safety Timer Trigger

(STT)

Edge Detect

Start

Flash/Timer

(SFT)

MODE 0

MODE 1

DC Light

Safety Timer

(11.2s)

0: NORMAL OPERATION

1: DISABLE CURRENT SINK

Start

LED1-3 CURRENT CONTROL

CLOCK

16-bit Prescaler

Safety Timer

Time-Out (TO)

0: DC LIGHT CURRENT LEVEL

1: FLASH CURRENT LEVEL

t_PULSE

Timer

Value

(STIM)

Dimming

(DIM)

LED1-3 ON/OFF CONTROL

Duty-Cycle Generator (5% ... 67%)

0: LED1-3 OFF

1: DC LIGHT CURRENT LEVEL

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PARAMETER MEASUREMENT INFORMATION

TPS61325

L

SW

VOUT

BAL

2.2 mH

AVIN

HC_SEL

C_O

2.5 V..5.5 V

D1

D2

C_I

LED1

LED2

LED3

STRB0

STRB1

SCL

SDA

I²C I/F

INDLED

Privacy

Indicator

Tx-MASK

GPIO/PG

TS

NTC

PGND

AGND

List of Components:

L = 2.2mH, Wuerth Elektronik WE-TPC Series

C_I, C_O= 10mF 6.3V X5R 0603 – TDK C1605X5R0J106MT

Storage Capacitor = TDK EDLC262020-500mF

NTC = 220kΩ, muRata NCP18WM224J03RB

12

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TYPICAL CHARACTERISTICS

Table of Graphs

FIGURE

Figure 4, Figure 5

Figure 6

LED Power Efficiency

DC Input Current

vs. Input Voltage

Figure 7, Figure 8,

Figure 9

LED Current

vs. LED Pin Headroom Voltage

vs. LED Current Digital Code

Figure 10, Figure 11,

Figure 12, Figure 13

INDLED Current

vs. LED Pin Headroom Voltage

vs. Output Current

Figure 14

Figure 15, Figure 16

Figure 17

Voltage Mode Efficiency

vs. Output Current

DC Output Voltage

vs. Input Voltage

Figure 18

Maximum Output Current

DC Pre-Charge Current

Valley Current Limit

vs. Input Voltage

Figure 19

vs. Differential Input-Output Voltage

Figure 20, Figure 21

Figure 22, Figure 23

Figure 24

Balancing Current

vs. Balance Pin Voltage

vs. Input Voltage

Supply Current

Figure 25

Standby Current

vs. Ambient Temperature

Figure 26

Temperature Detection Threshold

Junction Temperature

Flash Sequence (Direct Drive Mode)

Figure 27, Figure 28

Figure 29

vs. Port Voltage

Figure 30

Figure 31, Figure 32,

Figure 33

Tx-Masking Operation

Low-Light Dimming Mode Operation

PWM Operation

Figure 34

Figure 35

Figure 36

Figure 37

Figure 38

Figure 39

Figure 40

Figure 41

PFM Operation

Down-Mode Operation (Voltage Mode)

Voltage Mode Load Transient Response

Start-up Into DC Light Operation

Start-up Into Voltage Mode Operation

Storage Capacitor Pre-Charge

Figure 42, Figure 43,

Figure 44

Storage Capacitor Charge-Up

DC Light Operation (Energy Storage Mode)

Flash Sequence (Energy Storage Mode)

Figure 45

Figure 46, Figure 47,

Figure 48, Figure 49

Junction Temperature Monitoring

Shutdown (Energy Storage Mode)

Figure 50

Figure 51

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TYPICAL CHARACTERISTICS (continued)

100

90

100

ILED1 = ILED3 = 360 mA

ILED2 = 610 mA

90

80

ILED1 = ILED3 = 55 mA

ILED2 = 111 mA

70

ILED2 = 83 mA

ILED1 = ILED3 = 83 mA

ILED2 = 166 mA

60

50

40

30

20

60

ILED2 = 111 mA

ILED2 = 166 mA

ILED2 = 250 mA

ILED1 = ILED3 = 111 mA

ILED2 = 194 mA

50

40

30

20

ILED1 = ILED3 = 250 mA

ILED2 = 444 mA

ILED1 = ILED3 = 250 mA

ILED2 = 555 mA

I

= 1600 mA,

LIM

Tx-MASK = Low

LED2 Channel Only

I

= 1600 mA,

10

0

10

0

LIM

Tx-MASK = Low

2.5

2.9

3.3

3.7

4.1

V - Input Voltage - V

4.5

4.9

5.3

2.5

2.9

3.3

3.7

V - Input Voltage - V

4.1

4.5 4.9 5.3

I

Figure 4. LED Power Efficiency

Figure 5. LED Power Efficiency

vs.

Input Voltage

2000

1750

1500

1250

1000

750

900

ILED2 = 805 mA

ILED2 = 720 mA

ILED1 = ILED3 = 360 mA

ILED2 = 610 mA

800

700

600

500

400

300

200

ILED2 = 555 mA

ILED2 = 470 mA

ILED2 = 360 mA

ILED2 = 277 mA

ILED1 = ILED3 = 250 mA

ILED2 = 555 mA

ILED1 = ILED3 = 250 mA

ILED2 = 444 mA

500

ILED1 = ILED3 = 250 mA

ILED2 = 277 mA

250

0

100

0

I

= 1600 mA,

I

= 1600 mA

LIM

Tx-MASK = Low

LIM

2.5

2.9 3.3

3.7

4.1

4.5

4.9

5.3

400 500 600 700 800 900 1000 1100 1200 1300 1400

V - Input Voltage - V

I

LED2 Pin Headroom Voltage - mV

Figure 6. DC Input Current

Figure 7. LED2 Current

vs.

Input Voltage

LED2 Pin Headroom Voltage (HC_SEL=0)

14

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TYPICAL CHARACTERISTICS (continued)

2400

900

800

700

600

500

400

300

200

ILED1 = ILED3 = 416 mA

ILED1 = ILED3 = 360 mA

ILED2 = 2048 mA, T = 85°C

A

2300

2200

2100

2000

1900

1800

ILED2 = 2048 mA, T = 25°C

A

ILED1 = ILED3 = 305 mA

ILED1 = ILED3 = 250 mA

ILED2 = 2048 mA, T = -40°C

A

ILED2 = 1792 mA,

= 85°C

1700

1600

1500

1400

T

A

ILED2 = 1792 mA,

= -40°C

T

ILED2 = 1792 mA,

= 25°C

A

T

A

I

= 1600 mA

LIM

100

0

V

= 3.6 V, V

= 4.95 V

OUT

IN

HC_SEL = High

300 400 500 600 700 800 900 1000 1100 1200 1300 1400

LED2 Pin Headroom Voltage - mV

400 500 600 700 800 900 1000 1100 1200 1300 1400

LED1, LED3 Pin Headroom Voltage - mV

Figure 8. LED1+LED3 Current

vs.

Figure 9. LED2 Current

vs.

LED1+LED3 Pin Headroom Voltage (HC_SEL=0)

LED2 Pin Headroom Voltage (HC_SEL=1)

300

275

250

225

200

175

150

125

100

75

125

100

I

= 1600 mA

LIM

I

= 1600 mA

LIM

V

= 2.5 V

IN

V

= 3.6 V

IN

V

= 4.5 V

IN

V

= 4.5 V

IN

75

50

25

V

= 2.5 V

IN

V

= 3.6 V

IN

50

25

0

25 50 75 100 125 150 175 200 225 250 275 300

LED2 Current Digital Code - mA

25

50

75

100

125

LED1, LED3 Current Digital Code - mA

Figure 10. LED2 Current

vs.

Figure 11. LED1, LED3 Current

vs.

LED2 Current Digital Code (HC_SEL=0)

LED1, LED3 Current Digital Code (HC_SEL=0)

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TYPICAL CHARACTERISTICS (continued)

450

900

I

= 1600 mA

V

= 2.5 V

850

800

750

700

650

600

550

500

450

400

350

300

250

200

I

= 1600 mA

LIM

IN

LIM

425

400

375

350

325

300

275

V

= 2.5 V

IN

V

= 4.5 V

IN

V

= 3.6 V

IN

V

= 3.6 V

V

= 4.5 V

IN

250

225

200

300

400

500

600

700

800

900

200 225 250 275 300 325 350 375 400 425 450

LED2 Current Digital Code - mA

LED1, LED3 Current Digital Code - mA

Figure 12. LED2 Current

vs.

Figure 13. LED1, LED3 Current

vs.

LED2 Current Digital Code (HC_SEL=0)

LED1, LED3 Current Digital Code (HC_SEL=0)

16

14

12

10

8

100

90

V

= 4.2 V

IN

T

= 40°C,

A

INDLED = 0111

= 25°C,

= 85°C

80

70

60

50

40

30

20

10

0

V

= 3.6 V

IN

V

= 2.5 V

IN

V

= 3 V

INDLED = 0110

IN

PFM/PWM Operation

INDLED = 0011

6

Forced PWM Operation

4

INDLED = 0010

V_OUT= 4.95 V

I_LIM= 1600 mA

2

Voltage Mode Regulation

V

= 3.6 V

INDLED = 0001

1.1 1.3 1.5

IN

0

1

10

I

100

- Output Current - mA

1000

10000

0.5 0.7

0.9

1.7

1.9

2

INDLED Pin Headroom Voltage - V

O

Figure 14. INDLED Current

vs.

Figure 15. Efficiency vs Output Current

INDLED Pin Headroom Voltage

16

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TYPICAL CHARACTERISTICS (continued)

100

90

5.2

V

= 3.6 V

= 3 V

Voltage Mode Regulation

IN

V

I

= 4.95 V,

OUT

5.15

5.1

5.05

5

= 1600 mA

LIM

V

= 2.5 V

IN

80

70

60

50

40

30

20

10

PFM/PWM Operation

Forced PWM Operation

V

= 4.2 V

IN

PFM/PWM Operation

V

= 4.2 V

IN

4.95

4.9

Forced PWM Operation

V

= 3.6 V

= 2.5 V

V_OUT= 3.825 V

IN

I_LIM= 1600 mA

4.85

4.8

Voltage Mode Regulation

V

IN

0

1

10

100

1000

10000

1

10

100

- Output Current - mA

1000

10000

I

- Output Current - mA

O

Figure 16. Efficiency

vs.

Figure 17. DC Output Voltage

vs.

Output Current

Load Current

1200

1100

1000

900

800

700

600

500

400

300

200

100

4.016

3.978

3.94

Voltage Mode Regulation

= 25°C

Voltage Mode Regulation

T

A

I

= 0 mA

OUT

V

= 4.95 V,

OUT

I

= 1150 mA

LIM

V

I

= 5.7 V,

OUT

3.902

3.863

3.825

3.787

= 1150 mA

LIM

I

= 100 mA

OUT

I

= 1000 mA

OUT

V

= 4.95 V, I

= 250 mA

OUT

LIM

V

= 4.95 V, I

= 30 mA

V_OUT= 3.825 V

I_LIM= 1600 mA

OUT

LIM

3.749

3.71

0

2.5 2.7 2.9 3.1 3.3 3.5 3.7 3.9 4.1 4.3 4.5 4.7 4.9 5.1 5.3 5.5

2.5

2.9

3.3

I

3.7

4.1

4.5

- Output Current - mA

4.9

5.3

V - Input Voltage - V

I

O

Figure 18. DC Output Voltage

Figure 19. Maximum Output Current

vs.

Input Voltage

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TYPICAL CHARACTERISTICS (continued)

225

V

= 3.6 V, T = 25°C

A

IN

V

= 3.6 V, T = 25°C

A

IN

200

175

150

125

100

75

200

175

150

125

100

75

V

= 2.5 V, T = 25°C

A

IN

V

= 3.6 V, T = -40°C

A

IN

V

= 4.2 V, T = 25°C

IN

A

V

= 3.6 V, T = 85°C

A

IN

50

25

0

25

0

HC_SEL = 1

0

0.3 0.6 0.9 1.2 1.5 1.8 2.1 2.4 2.7 3.0 3.3 3.6 3.9 4.2 4.5

Differential Input - Output Voltage - V

0

0.3 0.6 0.9 1.2 1.5 1.8 2.1 2.4 2.7 3.0 3.3 3.6 3.9 4.2 4.5

Differential Input - Output Voltage - V

Figure 20. DC Pre-Charge Current

vs.

Figure 21. DC Pre-Charge Current

vs.

Differential Input-Output Voltage (HC_SEL=1)

50

45

40

35

30

25

20

15

10

50

45

40

35

30

25

20

15

10

V

= 3.6 V

V

= 3.6 V

IN

T

= 25°C

T

= 25°C

A

HC_SEL = 1,

Tx-MASK = 0,

ILIM bit = 1

HC_SEL = 1,

Tx-MASK = 0,

ILIM bit = 1

T

= 85°C

A

T

= 85°C

A

T

= -40°C

A

T

= -40°C

A

Sample Size = 74

5

0

5

0

I

- Valley Current Limit - mA

I

- Valley Current Limit - mA

LIM

Figure 22. Valley Current Limit (HC_SEL=1)

Figure 23. Valley Current Limit (HC_SEL=1)

18

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TYPICAL CHARACTERISTICS (continued)

25

20

15

10

5

1500

V

= 4.95 V,

I

= 0 mA

OUT

HC_SEL = 1

OUT

ENPSM bit = ENVM bit = 1

1400

1300

1200

1100

1000

900

T

= 85°C

A

T

= 25°C

A

V

= 4.95 V, T = 85°C

A

OUT

V

= 5.7 V, T = 25°C

T

= -40°C

OUT

A

0

-5

800

V

= 3.825 V,

= 25°C

OUT

T

A

-10

-15

-20

V

= 4.95 V,

OUT

T

700

= -40°C

A

V

= 4.95 V,

= 25°C

OUT

T

A

600

500

2.30 2.35 2.40 2.45 2.50 2.55 2.60 2.65 2.70

2.5

2.9

3.3

3.7

4.1

4.5

V - Input Voltage - V

4.9

5.3

V

- Balance Pin Voltage - V

I

BAL

Figure 24. Balancing Current

vs.

Figure 25. Supply Current

vs.

Balance Pin Voltage

Input Voltage

26

24

22

20

18

16

14

12

10

8

3

2.5

2

V

= 3.6 V

IN

V

= 4.8 V

IN

V

= 3.6 V

IN

1.5

1

V

= 2.5 V

IN

Sample Size = 76

6

0.5

0

4

HC_SEL = 1

= 0 mA)

2

0

Storage capacitor balanced (I

OUT

50 51 52 53 54 55 56 57 58 59 60

Temperature Detection (55°C Threshold)

-35 -25 -15 -5

5

15 25 35 45 55 65 75 85

T

- Ambient Temperature - °C

A

Figure 26. Standby Current

vs.

Figure 27. Temperature Detection Threshold

Ambient Temperature (HC_SEL=1)

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TYPICAL CHARACTERISTICS (continued)

200

28

V

= 3.6 V

Tx-MASK Input

IN

I

= -100 mA

26

24

22

20

18

16

14

12

10

8

PORT

175

150

125

100

75

STRB1 Input

50

Sample Size = 76

Port

Input Buffer

25

6

4

2

0

100 mA

-25

-50

-0.6 -0.55 -0.5 -0.45 -0.4 -0.35 -0.3 -0.25 -0.2 -0.15 -0.1

64 65 66 67 68 69 70 71 72 73 74 75

Temperature Detection (70°C Threshold)

Port Voltage - V

Figure 28. Temperature Detection Threshold

Figure 29. Junction Temperature

vs.

Port Voltage

STRB0

(2V/div)

STRB0

(2V/div)

Tx-MASK

(2V/div)

LED2 Channel Only

I_LED2

DCLC2[2:0] = 000

(500mA/div)

FC2[5:0] = 011110

DCLC13[2:0] = 000

FC13[4:0] = 01011

I_LED1+ I_LED3

(200mA/div)

V_OUT

(1V/div - 3.6V Offset)

LED2 Pin Headroom Voltage

(1V/div)

I_LED2

(200mA/div)

DCLC2[2:0] = 000

FC2[5:0] = 010101

V_IN= 3.6V, V_OUT= 4.95V, I_LIM= 1600mA

t - Time = 500 µs/div

V_IN= 3.6V, V_OUT= 4.95V, I_LIM= 1600mA

t - Time = 1 ms/div

Figure 30. FLASH SEQUENCE (HC_SEL=0)

Figure 31. Tx-MASKING OPERATION (HC_SEL=0)

20

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TYPICAL CHARACTERISTICS (continued)

Tx-MASK

(2V/div)

Tx-MASK

(2V/div)

I_LED2

(200mA/div)

I_LED2

(200mA/div)

I_L

(200mA/div)

I_L

(500mA/div)

LED2 Channel Only

DCLC2[2:0] = 111

FC2[5:0] = 011110

LED2 Channel Only

DCLC2[2:0] = 010

FC2[5:0] = 011110

V_IN= 3.6V, V_OUT= 4.95V

I_LIM= 1600mA

V_IN= 3.6V, V_OUT= 4.95V

I_LIM= 1600mA

t - Time = 5 µs/div

t - Time = 100 µs/div

Figure 32. Tx-MASKING OPERATION (HC_SEL=0)

Figure 33. Tx-MASKING OPERATION (HC_SEL=0)

V_OUT

(20mV/div - 4.95V Offset)

HC_SEL = 1

I

LED2

(20 mA/div)

I_L

(200mA/div)

Frequency = 30 kHz

Duty Cycle = 23 %

SW

(2V/div)

V

= 3.6 V, I

= 75 mA

IN

DCLIGHT2

LED2 Channel Only

INDC[3:0] = 1011

V_IN= 3.6V, V_OUT= 4.95V

I_OUT= 300mA, I_LIM= 1600mA ENPSM bit = 0

Forced PWM Operation

= 4.95 V

OUT

t - Time = 125 ns/div

t - Time = 10 µs/div

Figure 34. LOW-LIGHT DIMMING MODE OPERATION

Figure 35. PWM OPERATION

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TYPICAL CHARACTERISTICS (continued)

V_OUT

(100mV/div - 4.95V Offset)

V_OUT

(100mV/div - 3.825V Offset)

I_L

(200mA/div)

I_L

(200mA/div)

SW

(5V/div)

SW

(5V/div)

V_IN= 4.2V, V_OUT= 3.825V

I_OUT= 50mA, I_LIM= 1600mA

PFM/PWM Operation

ENPSM bit = 1

V_IN= 3.6V, V_OUT= 4.95V

I_OUT= 50mA, I_LIM= 1600mA

PFM/PWM Operation

ENPSM bit = 1

t - Time = 2 ms/div

Figure 36. PFM OPERATION

Figure 37. DOWN-MODE OPERATION (VOLTAGE MODE)

V_IN= 3.6V, V_OUT= 4.95V

I_LIM= 1600mA

MODE_CTRL[1:0] = 01

DC Light Turn-On

I_LED2

(50mA/div)

V_OUT

(500mV/div - 4.95V Offset)

V_OUT

(2V/div)

I_L

(500mA/div)

I_L

(200mA/div)

50mA to 500mA Load Step

I_OUT

(500mA/div)

V_IN= 3.6V, V_OUT= 4.95V

I_LIM= 1600mA

LED2 Channel Only

DCLC2[2:0] = 100

PFM/PWM Operation

ENPSM bit = 1

t - Time = 200 µs/div

t - Time = 50 ms/div

Figure 38. VOLTAGE MODE LOAD TRANSIENT RESPONSE

Figure 39. START-UP INTO DC LIGHT OPERATION

22

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TYPICAL CHARACTERISTICS (continued)

ENVM bit

Voltage Mode Regulation Start

HC_SEL (2V/div)

PG (2V/div)

V_OUT

(2V/div)

V_OUT

(1V/div)

I_L

(200mA/div)

I_L

(50mA/div)

V_IN= 3.6V, V_OUT= 4.95V

I_OUT= 0mA, I_LIM= 1600mA

ENPSM bit = 1

V_IN= 3.6V, I_OUT= 0mA

t - Time = 2 s/div

t - Time = 100 µs/div

Figure 40. START-UP INTO VOLTAGE MODE OPERATION

Figure 41. STORAGE CAPACITOR PRE-CHARGE (HC_SEL=1)

HC_SEL, ENVM (2V/div)

PG (2V/div)

HC_SEL, ENVM (2V/div)

PG (2V/div)

V_OUT

(2V/div)

V_OUT

(2V/div)

I_L

(100mA/div)

I_L

(100mA/div)

V_IN= 3.6V, V_OUT= 4.95V

I_OUT= 0mA

V_IN= 3.6V, V_OUT= 4.95V

I_OUT= 0mA

ENPSM bit = 1, ILIM bit = 0

Tx-MASK = 0

ENPSM bit = 1, ILIM bit = 1

Tx-MASK = 0

t - Time = 2 s/div

t - Time = 5 s/div

Figure 42. STORAGE CAPACITOR CHARGE-UP (HC_SEL=1)

Figure 43. STORAGE CAPACITOR CHARGE-UP (HC_SEL=1)

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TYPICAL CHARACTERISTICS (continued)

PG (2V/div)

PG (2 V/div)

V

ENVM bit = 1

OUT

V_OUT

(1V/div)

(1 V/div)

DCLC13[2:0] = 010

DCLC2[2:0] = 011

I_LED1+ I_LED3

(50mA/div)

DC Light

Turn-On Command

I_LED2

(50mA/div)

I

DC Light

Turn-Off Command

L

(200 mA/div)

V

I

= 3.6 V, V

= 4.95 V,

OUT

IN

ENPSM bit = 1, ILIM bit = 1,

Tx-MASK = 0

V_IN= 3.6V, V_OUT= 4.95V

All LED Channels Active

ENPSM bit = 1, ILIM bit = 1

Tx-MASK = 0

= 0 mA

OUT

t - Time = 1 s/div

t - Time = 500 ms/div

Figure 44. STORAGE CAPACITOR CHARGE-UP (HC_SEL=1)

Figure 45. DC LIGHT OPERATION (HC_SEL=1)

STRB0

(2V/div)

STRB0

(2V/div)

PG (2V/div)

V_OUT

(200mV/div - 4.95V Offset)

V_OUT

(500mV/div - 4.95V Offset)

I_L

(200mA/div)

DCLC2[2:0] = 000

FC2[5:0] = 100000

I_LED2

(1A/div)

ENPSM bit = 1,

I_LED2

ENPSM bit = 1,

ILIM bit = 1,

DCLC2[2:0] = 000

FC2[5:0] = 100000

Tx-MASK = 0

ILIM bit = 1,

(1A/div)

Tx-MASK = 0

V_IN= 3.6V, V_OUT= 4.95V, LED2 Channel Only

t - Time = 50 ms/div

V_IN= 3.6V, V_OUT= 4.95V, LED2 Channel Only

t - Time = 100 ms/div

Figure 46. FLASH SEQUENCE (HC_SEL=1)

Figure 47. FLASH SEQUENCE (HC_SEL=1)

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TYPICAL CHARACTERISTICS (continued)

PG

(2 V/div)

FLASH SYNC

(2 V/div)

LED V Calibrated Circuit,

F

V

OUT

ca. 500 mV LED Pin Headroom Pin (e/o Strobe)

(200 mV/div - 4.95 V Offset)

V

OUT

(200 mV/div - 4.95 V Offset)

I

Tx-MASK Input = 0

L

I

+ I

LED3

LED1

ENPSM bit = 1,

Tx-MASK bit = 0,

ILIM bit = 1

(100 mA/div)

Tx-MASK Input = 1

(1 A/div)

I

LED2

I

LED2

(1 A/div)

ENPSM bit = 1,

Tx-MASK bit = 0,

ILIM bit = 0

DCLC13 [2:0] = 000 DCLC2 [2:0] = 000

FC13 [4:0] = 10000 FC2 [5:0] = 100000

DCLC2[2:0] = 000

FC2[5:0] = 100000

V

= 3.6 V, V

= 4.95 V, All LED Channels Active

V

= 3.6 V, V

= 4.95 V, LED2 Channel Only

IN

OUT

IN

OUT

t - Time = 50 ms/div

t - Time = 10 ms/div

Figure 48. FLASH SEQUENCE (HC_SEL=1)

Figure 49. FLASH SEQUENCE (HC_SEL=1)

ENPSM bit = 1,

Tx-MASK bit = 0,

ILIM bit = 1

HC_SEL (2V/div)

Tx-MASK

(10 mV/div - -0.55 V Offset)

T

= 55°C

J

PG (2V/div)

T

= 25°C

J

V_OUT

(500mV/div)

LED V Calibrated Circuit,

F

ca. 500 mV LED Pin Headroom Pin (e/o Strobe)

DCLC13 [2:0] = 010

I

FC13 [4:0] = 10000

LED2

(1 A/div)

I

+ I

LED3

LED1

DCLC2 [2:0] = 100

FC2 [4:0] = 100000

(1 A/div)

DC Light = 2 s

Flash Strobe = 35 ms

V_IN= 3.6V, I_OUT= 0mA

V

= 3.6 V, V = 4.7 V, All LED Channels Active

IN

OUT

t - Time = 500 ms/div

t - Time = 100 s/div

Figure 50. JUNCTION TEMPERATURE MONITORING

(HC_SEL=1)

Figure 51. SHUTDOWN (HC_SEL=1)

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DETAILED DESCRIPTION

OPERATION

The TPS6132x family employs a 2MHz fixed on-time, PWM current-mode converter to generate the output

voltage required to drive up to three high power LEDs in parallel. The device integrates a power stage based on

an NMOS switch and a synchronous PMOS rectifier. The device also implements a set of linear low-side current

regulators to control the LED current when the battery voltage is higher than the diode forward voltage.

A special circuit is applied to disconnect the load from the battery during shutdown of the converter. In

conventional synchronous rectifier circuits, the back-gate diode of the high-side PMOS is forward biased in

shutdown and allows current flowing from the battery to the output. This device however uses a special circuit

which takes the cathode of the back-gate diode of the high-side PMOS and disconnects it from the source when

the regulator is in shutdown (HC_SEL = L).

The TPS6132x device cannot only operate as a regulated current source but also as a standard voltage boost

regulator featuring power-save mode for improved efficiency at light load. Voltage mode operation can be

enabled/disabled by software control.

The TPS6132x device also supports storage capacitor on its output (so called energy storage mode). In this

operating mode (HC_SEL = H), the inductive power stage is used to charge-up the super-capacitor to a user

selectable value. Once the charge-up is complete, the LEDs can be fired up to 1025mA (LED1 and LED3) and

2050mA (LED2) without causing a battery overload.

In general, a boost converter only regulates output voltages which are higher than the input voltage. This device

operates differently. For example, in the voltage mode operation the device is capable to regulate 4.2V at the

output from a battery voltage pulsing as high 5.5V. To control these applications properly, a down conversion

mode is implemented.

If the input voltage reaches or exceeds the output voltage, the converter changes to a down conversion mode. In

this mode, the control circuit changes the behavior of the rectifying PMOS. It sets the voltage drop across the

PMOS as high as needed to regulate the output voltage. This means the power losses in the converter increase.

This has to be taken into account for thermal consideration.

In direct drive mode (HC_SEL = L), the power stage is capable of supplying a maximum total current of roughly

1300 to 1500mA. The TPS6132x provides three constant current inputs, capable of sinking up to 445mA (LED1

and LED3) and 890mA (LED2) in flashlight mode.

The TPS6132x integrates an I²C compatible interface allowing transfers up to 3.4Mbits/s. This communication

interface can be used to set the operating mode (shutdown, constant output current mode vs. constant output

voltage mode), to control the brightness of the external LED (DC light and flashlight modes), to adjust the output

voltage (between 3.825V and 5.7V in 125mV steps) or to program the safety timer for instance. For more details,

refer to the I²C register description section.

In the TPS6132x device, the DC light and flash can be controlled either by the I²C interface or by the means of

hardware control signals (STRB0 and STRB1). The maximum duration of the flashlight pulse can be limited by

means of an internal user programmable safety timer (STIM). To avoid the LEDs to be kept accidentally on in DC

light mode by software control, the device implements a 13.0s watchdog timer. The DC light watchdog timer can

be disabled by pulling high the STRB1 signal.

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DOWN MODE IN VOLTAGE REGULATION MODE

In general, a boost converter only regulates output voltages which are higher than the input voltage. The featured

devices come with the ability to regulate 4.2 V at the output with an input voltage being has high as 5.5V. To

control these applications properly, a down conversion mode is implemented.

In voltage regulation mode, if the input voltage reaches or exceeds the output voltage, the converter changes to

the down-conversion mode. In this mode, the control circuit changes the behavior of the rectifying PMOS. It sets

the voltage drop across the PMOS as high as needed to regulate the output voltage. This means the power

losses in the converter increase. This has to be taken into account for thermal consideration. The down

conversion mode is automatically turned-off as soon as the input voltage falls about 200mV below the output

voltage.

For proper operation in down conversion mode the output voltage should not be programmed higher than ca.

5.3V. Care should be taken not to violate the absolute maximum ratings at the SW pins.

The TPS6132x device uses a control architecture that allows to “recycle” excessive energy that might be stored

in the output capacitor. By reversing the operation of the boost power stage, the converter is capable of

transferring energy from its output back into the input source.

In high-current mode (HC_SEL = 1), this feature becomes useful to dynamically adjust the output voltage (V_OUT

)

depending on the operating conditions (e.g. +4.95V constant output voltage to support audio applications or

variable storage capacitor pre-charge voltage, refer to “storage capacitor pre-charge voltage calibration” section).

Notice that this reverse operating mode can only perform within an output voltage range higher than the input

supply. For example, if the storage capacitor is initially pre-charged to 4.95V, the input voltage is around 4.1V

and the target output voltage is set to 3.825V, the converter will only be able to lower the output node down to

the input level.

LED HIGH-CURRENT REGULATORS, UNUSED INPUTS

The TPS6132x device utilizes LED forward voltage sensing circuitry on LED1-3 pins to optimize the power stage

boost ratio for maximum efficiency. Due to the nature of the sensing circuitry, it is not recommended to leave any

of the LED1-3 pins unused if the operation has been selected via ENLED[3:1] bits. Leaving LED1-3 pins

unconnected, whilst the respective ENLEDx bits have been set, will force the control loop into high gain and

eventually trip the output over-voltage protection.

The LED1-3 inputs may be connected together to drive one or two LEDs at higher currents. Connecting the

current sink inputs in parallel does not affect the internal operation of the TPS6132x. For best operation, it is

recommended to disabled the LED inputs that are not used (refer to ENLED[3:1] bits description).

To achieve smooth LED current waveforms, the TPS6132x device actively controls the LED current

ramp-up/down sequence.

Table 1. LED Current Ramp-Up/Down Control vs Operating Mode

DIRECT DRIVE MODE (HC_SEL = 0)

I_STEP= 27.5 mA

HIGH-CURRENT MODE (HC_SEL = 1)

I_STEP= 62 mA

LED CURRENT RAMP-UP

t_RISE= 12 ms

t_RISE= 0.5 ms

Slew-rate ≈ 2.3 mA/ms

I_STEP= 27.5 mA

Slew-rate ≈ 124 mA/ms

I_STEP= 62 mA

LED CURRENT RAMP-DOWN

t_FALL= 0.5 ms

Slew-rate ≈ 55 mA/ms

Slew-rate ≈ 124 mA/ms

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LED

CURRENT

I_STEP

Time

t_RISE

t_FALL

Figure 52. LED Current Slew-Rate Control

In high-current mode (HC_SEL = 1), the LED current settings are defined as a fixed ratio (x2.25) versus the

direct drive mode values (HC_SEL = L).

POWER-SAVE MODE OPERATION, EFFICIENCY

The TPS6132x device integrates a power save mode to improve efficiency at light load. In power save mode the

converter only operates when the output voltage trips below a set threshold voltage. It ramps up the output

voltage with one or several pulses and goes again into power save mode once the output voltage exceeds the

set threshold voltage.

Output

Voltage

PFM mode at light load

PFM ripple about 0.015 x V_OUT

1.013 x V_{OUT NOM.}

V_{OUT NOM.}

PWM mode at heavy load

Figure 53. Operation in PFM Mode and Transfer to PWM Mode

The power save mode can be enabled and disabled via the ENPSM bit. In down conversion mode, power save

mode is always active and the device cannot be forced into fixed frequency operation at light loads.

The LED sense voltage has a direct effect on the converter’s efficiency. Because the voltage across the low-side

current regulator does not contribute to the output power (LED brightness), the lower the sense voltage the

higher the efficiency will be.

In direct drive mode (HC_SEL = L), the energy is being directly transferred from the battery to the LEDs. The

integrated current control loop automatically selects the minimum boosting ratio to maintain regulation based on

the LED forward voltage and current requirements. The low-side current regulators will be dropping the voltage

difference between the input voltage and the LEDs forward voltage (V_F(LED)< V_IN). When running in boost mode

(V_F(LED)> V_IN), the voltage present at the LED1-3 pins of the low-side current regulators will be typically 400mV

leading to high power conversion efficiency. Depending on the input voltage and the LEDs forward voltage

characteristic the converter will show efficiency in the range of about 75% to 90%.

In high-current mode (HC_SEL = H), the device is only supplying a limited amount of energy directly from the

battery (i.e. DC light, contribution to flash current or voltage regulation mode). During a flash strobe, the bulk of

the energy supplied to the LEDs is provided by the reservoir capacitor. The low-side current regulators will be

typically operating with 400mV headroom voltage. This means the power losses in the device increase and

special care should be taken for thermal considerations.

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MODE OF OPERATION: DC LIGHT AND FLASHLIGHT

Operation is understood best by referring to the timer block diagram. Depending on the settings of

MODE_CTRL[1:0] bits the device can enter 4 different operating modes.

•

MODE_CTRL[1:0] = 00: The device is in shutdown mode.

MODE_CTRL[1:0] = 01: The STRB0, STRB1 inputs are disabled. The device is regulating the LED current in

DC light mode (DCLC bits) regardless of the STRB0, STRB1 inputs and the START_FLASH/TIMER (SFT) bit.

To avoid device shutdown by DC light safety timeout, MODE_CTRL[1:0] needs to be refreshed within less

than 13.0s (STRB1 = 0). The DC light watchdog timer can be disabled by pulling high the STRB1 signal.

•

MODE_CTRL[1:0] = 10: The STRB0, STRB1 inputs are enabled and the flashlight pulse can either be

triggered by these synchronization signals or by a software command (START_FLASH/TIMER (SFT) bit,

STRB0 = 1). The LEDs operation is enabled/disabled according to the STRB0, STRB1 input, the flashlight

safety timer is activated and the DC light safety timer is disabled.

MODE_CTRL[1:0] = 11: The device is regulating a constant output voltage according to OV[3:0] bits settings.

The low-side LED1-3 current regulators are disabled and the LEDs are disconnected from the output. In this

operating mode, the safety timer is disabled.

FLASH STROBE IS LEVEL SENSITIVE (STT = 0): LED STROBE FOLLOWS STRB0, 1 INPUTS

In this mode, the high-power LEDs are driven at the flashlight current level and the safety timer (STIM) is

running. The maximum duration of the flashlight pulse is defined in the STIM[2:0] register.

The safety timer is triggered on rising edge and stopped either by a negative logic on the synchronization source

(STRB0, STRB1 = 0) or by a timeout event (TO bit).

AF ASSIST LIGHT

STROBE

STRB0

STRB1

TIMER

DURATION < STIM

LED CONTROL

LED OFF

FLASHLIGHT

LED OFF

DC LIGHT

Figure 54. Hardware Synchronized DC Light and Flashlight Strobe

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FLASH STROBE IS LEADING EDGE SENSITIVE (STT = 1): ONE-SHOT LED STROBE

In this mode, the high-power LEDs are driven at the flashlight current level and the safety timer (STIM) is

running. The duration of the flashlight pulse is defined in the STIM[2:0] register.

The flashlight strobe is started either by a rising edge on the synchronization source (STRB0 = 1, STRB1 = 0) or

by a positive transition on the START-FLASH/TIMER (SFT) bit (STRB0 = 1, STRB1 = 0). Once running, the timer

ignores all kind of triggering signals and only stops after a timeout (TO). START-FLASH/TIMER (SFT) bit is being

reset by the timeout (TO) signal.

AF ASSIST LIGHT

STROBE

STRB0

STRB1

TIMER

DURATION = STIM

LED CONTROL

LED OFF

FLASHLIGHT

LED OFF

DC LIGHT

Figure 55. Edge Sensitive Timer

(Single Trigger Event)

SAFETY TIMER ACCURACY

The LED strobe timer uses the internal oscillator as reference clock. As a matter of fact, the timer execution

speed (refer to STIM[2:0]) scales according to the reference clock accuracy.

OSCILLATOR FREQUENCY SAFETY TIMER DURATION

(1)

Minimum

Typical

Maximum = Typical × (1 + f_ACC)

(2)

Typical

(1)

Maximum

Minimum = Typical x (1 - f_ACC)

(1) Refer to REGISTER3, STIM[2:0] definition.

(2) Refer to the Electrical Characteristics table.

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CURRENT LIMIT OPERATION

The current limit circuit employs a valley current sensing scheme. Current limit detection occurs during the off

time through sensing of the voltage drop across the synchronous rectifier. The detection threshold is user

selectable via the ILIM bit. The ILIM bit can only be set before the device enters operation (i.e., initial shutdown

state).

Figure 56 illustrates the inductor and rectifier current waveforms during current limit operation. The output

current, IOUT, is the average of the rectifier ripple current waveform. When the load current is increased such

that the lower peak is above the current limit threshold, the off time is lengthened to allow the current to decrease

to this threshold before the next on-time begins (so called frequency fold-back mechanism).

Both the output voltage and the switching frequency are reduced as the power stage of the device operates in a

constant current mode. The maximum continuous output current (I_OUT(CL)), before entering current limit operation,

can be defined as:

V

- V

OUT IN

1

D

IN

I

= (1 - D) ´ (I

+

DI ) with DI =

´

and D »

OUT(CL)

VALLEY

L

2

L

f

V

OUT

(1)

The TPS6132x device also provides a negative current limit (c.a. 300mA) to prevent an excessive reverse

inductor current when the power stage sinks current from the output (i.e., storage capacitor) in the forced

continuous conduction mode.

I

PEAK

DI

L

Current Limit

Threshold

I

= I

VALLEY LIM

Rectifier

Current

I

OUT (CL)

DI

L

I

(= I

)

OUT(DC)

LED

Increased

Load Current

I

IN (DC)

f

Inductor

Current

I

IN (DC)

DI

L

V

D

f

IN

ΔI

=

×

L

Figure 56. Inductor/Rectifier Currents in Current Limit Operation

To minimize the requirements on the energy storage capacitor present at the output of the driver

(HC_SEL = 1), the TPS6132x device can contribute to a larger extent in supporting directly the

high-current LED flash strobe. In fact, the device can dynamically adjust it’s current limit setting

according to the Tx-MASK input.

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Table 2. Inductor Current Limit Operation vs HC_SEL/Tx-MASK Inputs

VALLEY CURRENT LIMIT

ILIM BIT

HC_SEL INPUT

Tx-MASK INPUT

SETTING

1150 mA

1600 mA

30 mA

Low

High

Low

High

Low

High

Low

High

Low

High

Low

High

Low

High

250 mA

1150 mA

1600 mA

n/a⁽¹⁾

(1) The DC/DC power stage is disabled, zero current is being drained from the input source.

LED FAILURE MODES AND OVER-VOLTAGE PROTECTION

If a high-power LED fails as a short circuit, the low-side current regulator will limit the maximum output current

and the HIGH-POWER LED FAILURE (HPLF) flag will be set.

If a high-power LED fails as an open circuit, the control loop will initially attempt to regulate off of its low-side

current regulator feedback signal. This will drive VOUT higher. As the open circuited LED will never accept its

programmed current, V_OUTmust be voltage-limited by means of a secondary control loop.

The TPS6132x device limits V_OUTaccording to the over-voltage protection settings (refer to OVP specification). In

this failure mode, V_OUTis either limited to 4.65V (typ.) or 6.0V (typ.) and the HIGH-POWER LED FAILURE

(HPLF) flag is set.

OVP THRESHOLD

4.65 V typ

OPERATING CONDITIONS

HC_SEL = L and 0000 ≤ OV[3:0] ≤ 0100

HC_SEL = H or 0101 ≤ OV[3:0] ≤ 1111

6.0 V typ

Refer to the section “LED High-Current Regulators, Unused inputs” for additional information.

OVP Threshold

4.65V 150mV

1.02 V_{OUT (NOM)}

V_{OUT (NOM)}= 4.2V

0.98 V_{OUT (NOM)}

Dynamic Load Transient

LED Disconnect

Figure 57. Over-Voltage Protection Operation (4.65V typ)

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HARDWARE VOLTAGE MODE SELECTION

The TPS6132x device integrates a software control bit (ENVM bit) that can be used to force the converter to run

in voltage mode regulation. Table 3 gives an overview of the different mode of operation.

Table 3. Operating Mode Description

INTERNAL REGISTER

SETTINGS

ENVM BIT

OPERATING MODES

MODE_CTRL[1:0]

00

01

0

The converter is in shutdown mode and the load is disconnected from the battery.

LEDs are turned-on for DC light operation (i.e. movie-light). The converter is operating in

the current regulation mode (CM). The output voltage is controlled by the forward voltage

characteristic of the LED. The energy is being directly transferred from the battery to the output.

10

0

The converter is operating in the current regulation mode (CM). The output voltage is controlled

by the forward voltage characteristic of the LED. LEDs are ready for flashlight operation

supported directly from the battery.

In high-current mode (HC_SEL = H), the energy is supplied by the output reservoir

capacitor and the inductive power stage is turned-off for the flash strobe period of time.

11

00

01

0

1

LEDs are turned-off and the converter is operating in the voltage regulation mode (VM). The

output voltage is set via the register OV[3:0].

LEDs are turned-off and the converter is operating in the voltage regulation mode (VM). The

output voltage is set via the register OV[3:0].

The converter is operating in the voltage regulation mode (VM) and it’s output voltage is

set via the register OV[3:0]. The LEDs are turned-on for DC light operation and the

energy is being directly transferred from the battery to the output. The LED currents are

regulated by the means of the low-side current sinks.

10

1

The converter is operating in the voltage regulation mode (VM) and it’s output voltage is set via

the register OV[3:0]. The LED currents are regulated by the means of the low-side current

sinks. The LEDs are ready for flashlight operation.

In direct drive mode (HC_SEL = L), the energy is being directly transferred from the battery to

the output.

In high-current mode (HC_SEL = H), the energy is largely supplied by the output

reservoir capacitor. Nonetheless, the inductive power stage is active thereby

contributing to the flash power.

11

1

LEDs are turned-off and the converter is operating in the voltage regulation mode (VM). The

output voltage is set via the register OV[3:0].

START-UP SEQUENCE

To avoid high inrush current during start-up, special care is taken to control the inrush current. When the device

enables, the internal startup cycle starts with the first step, the pre-charge phase.

During pre-charge, the rectifying switch is turned on until the output capacitor is either charged to a value close

to the input voltage or ca. 3.3V, whichever occurs first. The rectifying switch is current limited during that phase.

The current limit increases with decreasing input to output voltage difference. This circuit also limits the output

current under short-circuit conditions at the output. Figure 58 shows the typical pre-charge current vs. input

minus the output voltage for a specific input voltage.

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225

200

175

150

125

100

75

V

= 3.6 V, T = 25°C

A

IN

V

= 3.6 V, T = -40°C

A

IN

V

= 3.6 V, T = 85°C

A

IN

50

25

0

HC_SEL = 1

0

0.3 0.6 0.9 1.2 1.5 1.8 2.1 2.4 2.7 3.0 3.3 3.6 3.9 4.2 4.5

Differential Input - Output Voltage - V

Figure 58. Typical DC Pre-charge and Short-Circuit Current

In direct drive mode (HC_SEL = L, TPS6132x), after having pre-charged the output capacitor, the device

starts-up switching and increases its current limit in three steps of typically 30mA, 250mA and full current limit

(ILIM setting). The current limit transitions from the first to the second step occurs after a milli-second operation.

Full current limit operation is set once the output voltage has reached its regulation limits. In this mode, the active

balancing circuit is disabled.

In high-current mode (HC_SEL = H), the pre-charge voltage of the storage capacitor is depending on the input

voltage and operating mode (i.e., voltage regulation vs. current regulation mode). In case the device is set for

exclusive current regulation operation (i.e., MODE_CTRL[1:0] = 01 or 10 and ENVM = 0), the output capacitor

pre-charge voltage will be close to the input voltage. Under all other operating conditions, the pre-charge voltage

will either be close to the input voltage or to approximately 3.3V, whichever is lower. Furthermore, pre-charge

operation can be suspended/resumed via the Tx-MASK input (refer to ILIM setting and Tx-MASK input logic

state).

After having pre-charged the storage capacitor, the device starts-up switching. During down-mode operation, the

inductor valley current is actively limited either to 30mA or 250mA (refer to ILIM setting). As the device enters

boost mode operation, the current limit transitions to its full capability (refer to ILIM setting and Tx-MASK input

logic state). As a consequence, the output voltage ramps-up linearly and the start-up time needed to reach the

programmed output voltage (refer to OV[3:0] bits) will mainly depend on the super-capacitor value and load

current. In this mode, the active balancing circuit is enabled.

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POWER GOOD (FLASH READY)

The TPS6132x integrates a power good circuitry that is activated when the device is operating in voltage

regulation mode (MODE_CTRL[1:0] = 11 or ENVM = 1). In shutdown mode (MODE_CTRL[1:0] = 00) the

GPIO/PG pin state is defined as following:

GPIOTYPE

GPIO/PG SHUTDOWN STATE

Reset/pulled to ground

Open-drain

0

1

Depending on the GPIO/PG output stage type selection (i.e., push-pull or open-drain), the polarity of the

power-good output signal (PG) can be inverted or not. The power-good software bit and hardware signal polarity

is defined as following:

GPIOTYPE

PG BIT

GPIO/PG OUTPUT PORT

COMMENTS

0

1

0

1

0

1

0: push-pull output

Output is active high signal polarity

Open-drain

Low

1: open-drain output

Output is active low signal polarity

The power good signal is valid when the output voltage is within –1.5% and +2.5% of its nominal value.

Conversely, it is asserted low when the voltage mode operation gets suspended (MODE_CTRL[1:0] ≠ 11 and

ENVM = 0).

Forced PWM mode operation

Output Voltage

Down Regulation

Voltage Mode Request

1.025 V

0.985 V

OUT (NOM)

Nom.Voltage

Output Voltage, V

OUT

V

OUT (NOM)

Start-up phase

OUT (NOM)

Output Voltage

Up Regulation

Power Good Bit, (PG)

Forced PWM mode operation

(PG)Bit

Power Good Output,

GPIO/PG

Hi-Z

Figure 59. Power Good Operation (DIR = 1, GPIOTYPE = 1)

The TPS6132x device uses a control architecture that allows to “recycle” excessive energy that might be stored

in the output capacitor. By reversing the operation of the boost power stage, the converter is capable of

transferring energy from its output back into the input source. In this case, the power good signal is de-asserted

whilst the output voltage is decreasing towards its target value (i.e., the closest fit voltage the converter can

support, refer to the section “Down-Mode in Voltage Regulation Mode” for additional information).

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LED TEMPERATURE MONITORING

The TPS6132x devices monitor the LED temperature by measuring the voltage between the TS and AGND pins.

An internal current source provides the bias (c.a. 24 mA) for a negative-temperature coefficient resistor (NTC),

and the TS pin voltage is compared to internal thresholds (1.05V and 0.345V) to protect the LEDs against

overheating.

The temperature monitoring related blocks are always active in DC light or flashlight modes. In voltage mode

operation (MODE_CTRL[1:0] = 11), the device only activates the TS input when the ENTS bit is set to high. In

shutdown mode, the LED temperature supervision is disabled and the quiescent current of the device is

dramatically reduced.

The LEDWARN and LEDHOT bits reflect the LED temperature. The LEDWARN bit is set when the voltage seen

at the TS pin is lower than 1.05V. This threshold corresponds to an LED warning temperature value, the device

operation is still permitted.

While regulating LED current (i.e.. DC light or flashlight modes), the LEDHOT bit is latched when the voltage

seen at the TS pin is lower than 0.345V. This threshold corresponds to an excessive LED temperature value, the

device operation is immediately suspended (MODE_CTRL[1:0] bits are reset and HOTDIE[1:0] bits are set).

HOT DIE DETECTOR

The hot die detector monitors the junction temperature but does not shutdown the device. It provides an early

warning to the camera engine to avoid excessive power dissipation thus preventing from thermal shutdown

during the next high-power flash strobe.

The hot die detector (HOTDIE[1:0] bits) reflects the instantaneous junction temperature and is always enabled

excepted when the device is in shutdown mode (MODE_CTRL[1:0] = 00).

FLASHLIGHT BLANKING (Tx-MASK)

In direct drive mode (HC_SEL = 0), the Tx-MASK input signal can be used to disable the flashlight operation,

e.g., during a RF PA transmission pulse. This blanking function turns the LED from flashlight to DC light thereby

reducing almost instantaneously the peak current loading from the battery. The Tx-MASK function has no

influence on the safety timer duration.

FLASH

LED CURRENT

DC LIGHT

Tx-MASK

STRB0

Figure 60. Synchronized Flashlight With Blanking Periods (STRB1 = 0)

In high-current mode (HC_SEL = 1), the Tx-MASK input pin is also used to dynamically adjusts the device’s

current limit setting (i.e. controls the maximum current drawn from the input source). Refer to the section “Current

Limit Operation” for additional information.

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UNDERVOLTAGE LOCKOUT

The under-voltage lockout circuit prevents the device from mis-operation at low input voltages. It prevents the

converter from turning on the switch–MOSFET, or rectifier–MOSFET for battery voltages below 2.3V. The I2C

compatible interface is fully functional down to 2.1V input voltage.

SHUTDOWN

MODE_CTRL[1:0] bits low force the device into shutdown. The shutdown state can only be entered when voltage

regulation is turned-off (ENVM = 0).

In direct drive mode (HC_SEL = L), the regulator stops switching, the high-side PMOS disconnects the load from

the input and the LEDx pins are high impedance thus eliminating any DC conduction path. The TPS6132x device

actively discharges the output capacitor when it turns off.

The integrated discharge resistor has a typical resistance of 2kΩ equally split-off between VOUT to BAL and BAL

to GND outputs. The required time to discharge the output capacitor at V_OUTdepends on load current and the

effective output capacitance. The active balancing circuit is disabled and the device consumes only a shutdown

current of 1mA (typ).

In high-current mode (HC_SEL = H), the device maintains its output biased at the input voltage level. In this

mode, the synchronous rectifier is current limited (i.e. pre-charge current) allowing external load (e.g. audio

amplifier) to be powered with a restricted supply. The active balancing circuit is enabled and the device

consumes only a standby current of 5mA (typ).

THERMAL SHUTDOWN

As soon as the junction temperature, T_J, exceeds 160°C typical, the device goes into thermal shutdown. In this

mode, the power stage and the low-side current regulators are turned-off, the HOTDIE[1:0] bits are set and can

only be reset by a readout.

In the voltage mode operation (MODE_CTRL[1:0] = 11 or ENVM = 1), the device continues its operation when

the junction temperature falls below 140°C typ. again. In the current regulation mode (i.e., DC light or flashlight

modes) the device operation is suspended.

STORAGE CAPACITOR ACTIVE CELL BALANCING

A fully charged super-capacitor will typically have leakage current of under 1mA. The TPS6132x device integrates

an active balancing feature to cut the total leakage current from the super-capacitor and balance circuit to less

than 1.7mA typ.

The device integrates a window comparator monitoring the tap point of the multi-cell super-capacitor. The

balancing output (BAL) is substantially half the actual output voltage (V_OUT). If the internal leakage current in one

of the capacitors is larger than that in the other, then the voltage at their junction will tend to change in such a

way that the voltage on the capacitor with the larger (or largest) leakage current will reduce.

When this happens, a current will begin to flow from the BAL output in such a direction as to reduce the amount

by which the voltage changes. The current that will flow after a long period of steady-state conditions will be

approximately equal to the difference between the leakage currents of the pair of capacitors which is being

balanced by the circuit. The output resistance of the balancing circuit (c.a. 250Ω) determines how quickly an

imbalance will be corrected.

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RED LIGHT PRIVACY INDICATOR

The TPS6132x device provides a high-side linear constant current source to drive low VF LEDs. The LED current

is directly regulated off the battery and can be controlled via the INDC[3:0] bits. Operation is understood best by

referring to the Figure 61 and Figure 62.

AVIN

Backgate

Control

SW

VOUT

L

VBAT

C_IN

C_O

INDC [3:2] = 01 && INDC[1:0] 00

V_OUT

< TBD V

P

D1

D2

SHUTDOWN ACTIF

P

LED2

ON/OFF

Hi-Z

P

LED1

LED3

ON/OFF

Hi-Z

P

AVIN

INDLED

INDC[3:0]

High-Side LED Current Regulator

Figure 61. RED Light Indicator, Configuration 1

AVIN

Backgate

Control

L

SW

VOUT

VBAT

CIN

CO

INDC[3:2]

=

01 && INDC[1:0] 00

TBD

V_OUT

<

V

P

D1

D2

SHUTDOWN ACTIF

P

LED2

ON/OFF

Hi-Z

P

LED1

LED3

ON/OFF

Hi-Z

P

AVIN

INDLED

INDC[3:0]

High-Side LED Current Regulator

Figure 62. RED Light Indicator, Configuration 2

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The device can provide a path to allow for reverse biasing of white LEDs (refer to Figure 62). To do so, the

output of the converter (VOUT) is pulled to ground thus allowing a reverse current to flow. This mode of

operation is only possible when the converter’s power stage is in shutdown (MODE_CTRL[1:0] = 00, ENVM = 0

and HC_SEL = 0).

WHITE LED PRIVACY INDICATOR

The TPS6132x device features white LED drive capability at low light intensity. To generate a reduced LED

average current, the device employs a 30kHz fixed frequency PWM modulation scheme. The PWM timer uses

the internal oscillator as reference clock, therefore the PWM modulating frequency shows the same accuracy as

the internal reference clock. Operation is understood best by referring to the timer block diagram.

The DC light current is modulated with a duty cycle defined by the INDC[3:0] bits. The low light dimming mode

can only be activated in the software controlled DC light only mode (MODE_CTRL[1:0] = 01, ENVM = 1) and

applies to the LEDs selected via ENLED[3:1] bits. In this mode, the DC light safety timeout feature is disabled.

PWM Dimming Steps

5%, 11%, 17%, 23%, 30%, 36%, 48%, 67%

t1

I

DCLIGHT

0

I

=

I

x PWM Dimming Step

DCLIGHT

LED(DC)

T

PWM

Figure 63. PWM Dimming Principle

STORAGE CAPACITOR, PRE-CHARGE VOLTAGE CALIBRATION

High-power LEDs tend to exhibit a wide forward voltage distribution. The TPS6132x device integrates a

self-calibration procedure that can be used to determine the optimum super-capacitor pre-charge voltage based

on the actual worst case LED forward voltage and ESR of the storage capacitor. This calibration procedure is

meant to start-off at a min. output voltage and can be initiated by setting the SELFCAL bit (preferably with

MODE_CTRL[1:0] = 00, ENVM = 0).

The calibration procedure monitors the sense voltage across the low-side current regulators (according to

ENLED[3:1] bits setting) and registers the worst case LED (i.e. the LED featuring the largest forward voltage).

The TPS6132x device automatically sweeps through its output voltage range and performs a short duration flash

strobe for each step (refer to FC13[1:0] and FC2[2:0] bits settings).

In direct drive mode (HC_SEL = L), the energy is being directly transferred from the battery to the LEDs. In

high-current mode (HC_SEL = H), the energy is supplied exclusively by the output reservoir capacitor and the

inductive power stage is turned-off for the flash strobe period of time.

The sequence is stopped as soon as the device detects that each of the low-side current regulators have enough

headroom voltage (i.e. 400mV typ.). The device returns the according output voltage in the register OV[3:0] and

sets the SELFCAL bit. This bit is only being reset at the (re-)start of a calibration cycle. In other words, when

SELFCAL is asserted the output voltage register (OV[3:0]) returns the result of the last calibration sequence.

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Output Voltage, V_OUT

~200 ms

ESR x I_LED

Feedback Sense

Comparator Information

V_BAT

Power Good, PG

~200 ms

LED Flash Current, I_FLASH

Feedback Sense Comparator Output

V_LED> 400mV

0000

0001 0010 0011 0100

0101

OV[3:0]

Self-Calibration,

SELFCAL bit (write)

Self-Calibration,

SELFCAL bit (read)

X

Figure 64. LED Forward Voltage Self-Calibration Principle

STORAGE CAPACITOR, ADAPTIVE PRE-CHARGE VOLTAGE

In high-power LED camera flash applications, the storage capacitor is supposed to be charged to an optimum

voltage level in order to:

•

Maintain sufficient headroom voltage across the LED current regulators for the entire strobe time.

Minimize the power dissipation in the device.

High-power LEDs tend to exhibit large dynamic forward voltage variation relating to own self-heating effects. In

addition, the energy storage capacitor (i.e., Electrochemical Double-Layer Capacitor or Super-Capacitor) also

shows a relatively large effective capacitance and ESR spread. The main factors contributing to these variations

are:

•

Flash strobe duration

Temperature

Ageing effects

In practice, it normally becomes very challenging to compensate for all these variations and a worst-case design

would presumably be too pessimistic. As a consequence, designers would have to give-up on the benefits

coming along with the “Storage Capacitor, Pre-Charge Voltage Calibration” approach.

The TPS6132x device offers the possibility of controlling the storage capacitor pre-charge voltage in a

closed-loop manner. The principle is to dynamically adjust the initial pre-voltage to the minimum value, as

required for the particular components characteristic and operating conditions.

The reference criteria used to evaluate proper operation is the headroom voltage across the LED current

regulators. In case of a critical headroom voltage (V_LED1-3) at the end of a flash strobe (i.e., n cycle), the

pre-charge voltage should be increased prior to the next capture sequence (i.e., n+1 cycle).

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Output Voltage, V_OUT

ESR x I_LED

Critical Headroom Voltage

LED Flash Current, I_FLASH

Feedback Sense Comparator Output

(V_LED> 400mV)

Power Good, PG

LEDHDR bit

FLASH_SYNC

Figure 65. Storage Capacitor, Simple Adaptive Pre-Charge Voltage

SERIAL INTERFACE DESCRIPTION

I²C™ is a 2-wire serial interface developed by Philips Semiconductor, now NXP Semiconductors (see I2C-Bus

Specification, Version 2.1, January 2000). The bus consists of a data line (SDA) and a clock line (SCL) with

pull-up structures. When the bus is idle, both SDA and SCL lines are pulled high. All the I²C compatible devices

connect to the I²C bus through open drain I/O pins, SDA and SCL. A master device, usually a microcontroller or

a digital signal processor, controls the bus. The master is responsible for generating the SCL signal and device

addresses. The master also generates specific conditions that indicate the START and STOP of data transfer. A

slave device receives and/or transmits data on the bus under control of the master device.

The TPS6132x device works as a slave and supports the following data transfer modes, as defined in the

I²C-Bus Specification: standard mode (100 kbps) and fast mode (400 kbps), and high-speed mode (3.4 Mbps).

The interface adds flexibility to the power supply solution, enabling most functions to be programmed to new

values depending on the instantaneous application requirements. Register contents remain intact as long as

supply voltage remains above 2.1V.

The data transfer protocol for standard and fast modes is exactly the same, therefore they are referred to as

F/S-mode in this document. The protocol for high-speed mode is different from F/S-mode, and it is referred to as

HS-mode. The TPS6132x device supports 7-bit addressing; 10-bit addressing and general call address are not

supported. The device 7bit address is defined as ‘011 0011’.

F/S-MODE PROTOCOL

The master initiates data transfer by generating a start condition. The start condition is when a high-to-low

transition occurs on the SDA line while SCL is high, as shown in Figure 66. All I²C-compatible devices should

recognize a start condition.

DATA

CLK

S

P

START Condition

STOP Condition

Figure 66. START and STOP Conditions

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The master then generates the SCL pulses, and transmits the 7-bit address and the read/write direction bit R/W

on the SDA line. During all transmissions, the master ensures that data is valid. A valid data condition requires

the SDA line to be stable during the entire high period of the clock pulse (see Figure 67). All devices recognize

the address sent by the master and compare it to their internal fixed addresses. Only the slave device with a

matching address generates an acknowledge (see Figure 68) by pulling the SDA line low during the entire high

period of the ninth SCL cycle. Upon detecting this acknowledge, the master knows that communication link with a

slave has been established.

DATA

CLK

Data line

stable;

data valid

Change

of data

allowed

Figure 67. Bit Transfer on the Serial Interface

The master generates further SCL cycles to either transmit data to the slave (R/W bit 1) or receive data from the

slave (R/W bit 0). In either case, the receiver needs to acknowledge the data sent by the transmitter. So an

acknowledge signal can either be generated by the master or by the slave, depending on which one is the

receiver. 9-bit valid data sequences consisting of 8-bit data and 1-bit acknowledge can continue as long as

necessary.

To signal the end of the data transfer, the master generates a stop condition by pulling the SDA line from low to

high while the SCL line is high (see Figure 66). This releases the bus and stops the communication link with the

addressed slave. All I²C compatible devices must recognize the stop condition. Upon the receipt of a stop

condition, all devices know that the bus is released, and they wait for a start condition followed by a matching

address.

Attempting to read data from register addresses not listed in this section will result in 00h being read out.

Figure 68. Acknowledge on the I²C Bus

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Figure 69. Bus Protocol

HS-MODE PROTOCOL

The master generates a start condition followed by a valid serial byte containing HS master code 00001XXX.

This transmission is made in F/S-mode at no more than 400 Kbps. No device is allowed to acknowledge the HS

master code, but all devices must recognize it and switch their internal setting to support 3.4 Mbps operation.

The master then generates a repeated start condition (a repeated start condition has the same timing as the start

condition). After this repeated start condition, the protocol is the same as F/S-mode, except that transmission

speeds up to 3.4 Mbps are allowed. A stop condition ends the HS-mode and switches all the internal settings of

the slave devices to support the F/S-mode. Instead of using a stop condition, repeated start conditions should be

used to secure the bus in HS-mode.

Attempting to read data from register addresses not listed in this section will result in 00h being read out.

TPS6132x I2C UPDATE SEQUENCE

The TPS6132x requires a start condition, a valid I²C address, a register address byte, and a data byte for a

single update. After the receipt of each byte, TPS6132x device acknowledges by pulling the SDA line low during

the high period of a single clock pulse. A valid I²C address selects the TPS6132x. TPS6132x performs an update

on the falling edge of the acknowledge signal that follows the LSB byte.

7

8

1

S

Slave Address

R/W

A

Register Address

A

Data

A

P

“0” Write

A

S

= Acknowledge

= START condition

From Master to TPS6132x

From TPS6132x to Master

Sr = REPEATED START condition

= STOP condition

P

Figure 70. : “Write” Data Transfer Format in F/S-Mode

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7

8

7

8

1

S

Slave Address

R/W

A

Register Address

A

Sr

Slave Address

R/W

A

Data

A

P

“0” Write

“1” Read

From Master to TPS6132x

From TPS6132x to Master

A

S

= Acknowledge

= START condition

Sr = REPEATED START condition

= STOP condition

P

Figure 71. “Read” Data Transfer Format in F/S-Mode

F/S Mode

8

HS Mode

F/S Mode

7

8

1

S

HS-Master Code

A

Sr

Slave Address

R/W

A

Register Address

A

Data

A/A

P

Data Transferred

(n x Bytes + Acknowledge)

HS Mode Continues

Slave Address

Sr

A

S

= Acknowledge

= START condition

From Master to TPS6132x

From TPS6132x to Master

Sr = REPEATED START condition

= STOP condition

P

Figure 72. Data Transfer Format in H/S-Mode

SLAVE ADDRESS BYTE

MSB

LSB

X

A1

A0

The slave address byte is the first byte received following the START condition from the master device.

REGISTER ADDRESS BYTE

MSB

0

LSB

D0

0

00

D2

D1

Following the successful acknowledgement of the slave address, the bus master will send a byte to the

TPS6132x, which will contain the address of the register to be accessed.

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REGISTER0 DESCRIPTION

Memory location: 0x00

Description

Bits

RESET

D7

FREE

D6

DCLC13[2:0]

DCLC2[2:0]

D5

R/W

0

D4

R/W

0

D3

R/W

1

D2

R/W

0

D1

R/W

1

D0

R/W

0

Memory type

Default value

R/W

0

R/W

0

Bit

Description

RESET

Register Reset bit.

0: Normal operation.

1: Default values are set to all internal registers.

DCLC13[2:0]

DC Light Current Control bits (LED1/3).

000: 0mA.

(1) (2)

001: 28.0mA

010: 55.75mA

011: 83.25mA

100: 111.0mA

101: 138.75mA

110: 166.5mA

111: 194.25mA

DCLC2[2:0]

DC Light Current Control bits (LED2).

000: 0mA.

(1) (2)

001: 28.0mA

010: 55.75mA

011: 83.25mA

100: 111.0mA

101: 138.75mA

110: 166.5mA, 249.75mA current level can be activated simultaneously with Tx-MASK = 1

111: 194.25mA, 360.75mA current level can be activated simultaneously with Tx-MASK = 1

(1) LEDs are off, V_OUTset according to OV[3:0].

(2) When DCLC2[2:0] and DCLC13[2:0] are both reset, the device operates in voltage regulation mode. The output voltage is set according

to OV[3:0].

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REGISTER1 DESCRIPTION

Memory location: 0x01

Description

Bits

MODE_CTRL[1:0]

FC2[5:0]

D7

R/W

0

D6

R/W

0

D5

R/W

0

D4

R/W

1

D3

R/W

0

D2

R/W

0

D1

R/W

0

D0

R/W

0

Memory type

Default value

Bit

Description

MODE_CTRL[1:0]

Mode Control bits.

00: Device in shutdown mode.

01: Device operates in DC light mode.

10: Device operates in flashlight mode.

11: Device operates as constant voltage source.

To avoid device shutdown by DC light safety timeout, MODE_CTRL[1:0] bits need to be refreshed within less than

13.0s.

Writing to REGISTER1[7:6] automatically updates REGISTER2[7:6].

FC2[5:0]

Flash Current Control bits (LED2).

HC_SEL = 0

HC_SEL = 1

000000: 0mA.^{(1) (2)}

000001: 28.0mA

000000: 0mA.^{(1) (2)}

000001: 64mA

000010: 55.75mA

000011: 83.25mA

000100: 111.0mA

000101: 138.75mA

000110: 166.5mA

000111: 194.25mA

001000: 222.0mA

001001: 249.75mA

001010: 277.5mA

001011: 305.25mA

001100: 333.0mA

001101: 360.75mA

001110: 388.5mA

001111: 416.25mA

010000: 444.0mA

010001: 471.75mA

010010: 499.5mA

010011: 527.25mA

010100: 555.0mA

010101: 582.75mA

010110: 610.5mA

010111: 638.25mA

011000: 666.0mA

011001: 693.75mA

011010: 721.5mA

011011: 749.25mA

011100: 777.0mA

011101: 804.75mA

011110: 832.5mA

011111: 860.25mA

100000 ... 111111: 888.0mA

000010: 130mA

000011: 196mA

000100: 260mA

000101: 324mA

000110: 388mA

000111: 452mA

001000: 516mA

001001: 580mA

001010: 644mA

001011: 708mA

001100: 772mA

001101: 836mA

001110: 900mA

001111: 964mA

010000: 1028mA

010001: 1092mA

010010: 1156mA

010011: 1220mA

010100: 1284mA

010101: 1348mA

010110: 1412mA

010111: 1476mA

011000: 1540mA

011001: 1604mA

011010: 1668mA

011011: 1732mA

011100: 1796mA

011101: 1860mA

011110: 1924mA

011111: 1988mA

100000 ... 111111: 2052mA

(1) LEDs are off, V_OUTset according to OV[3:0].

(2) When FC13[4:0] and FC2[5:0] are both reset, the device operates in voltage regulation mode. The output voltage is set according to

OV[3:0].

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REGISTER2 DESCRIPTION

Memory location: 0x02

Description

Bits

MODE_CTRL[1:0]

ENVM

D5

FC13[4:0]

D7

R/W

0

D6

R/W

0

D4

R/W

0

D3

R/W

1

D2

R/W

0

D1

R/W

0

D0

R/W

0

Memory type

Default value

R/W

0

Bit

Description

MODE_CTRL[1:0]

Mode Control bits.

00: Device in shutdown mode.

01: Device operates in DC light mode.

10: Device operates in flashlight mode.

11: Device operates as constant voltage source.

To avoid device shutdown by DC light safety timeout, MODE_CTRL[1:0] bits need to be refreshed within less than

13.0s.

Writing to REGISTER2[6:5] automatically updates REGISTER1[6:5].

ENVM

Enable Voltage Mode bit.

0: Normal operation.

1: Forces the device into a constant voltage source.

In read mode, the ENVM bit returns zero.

FC13[4:0]

Flash Current Control bits (LED1/3).

HC_SEL = 0

HC_SEL = 1

00000: 0mA.^{(1) (2)}

00001: 27.75mA

00010: 55.5mA

00000: 0mA.^{(1) (2)}

00001: 64.5mA

00010: 127.0mA

00011: 192.0mA

00100: 256.0mA

00101: 320.25mA

00110: 384.5mA

00111: 448.75mA

01000: 513.0mA

01001: 577.25mA

01010: 641.5mA

01011: 705.75mA

01100: 770.0mA

01101: 834.25mA

01110: 898.5mA

01111: 962.75mA

10000 ... 11111: 1027.0mA

00011: 83.25mA

00100: 111.0mA

00101: 138.75mA

00110: 166.5mA

00111: 194.25mA

01000: 222.0mA

01001: 249.75mA

01010: 277.5mA

01011: 305.25mA

01100: 333.0mA

01101: 360.75mA

01110: 388.5mA

01111: 416.25mA

10000 ... 11111: 444.0mA

(1) LEDs are off, V_OUTset according to OV[3:0].

(2) When FC13[4:0] and FC2[5:0] are both reset, the device operates in voltage regulation mode. The output voltage is set according to

OV[3:0].

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REGISTER3 DESCRIPTION

Memory location: 0x03

Description

Bits

STIM[2:0]

HPLF

SELSTIM (W)

TO (R)

STT

SFT

Tx-MASK

D7

R/W

1

D6

R/W

1

D5

R/W

0

D4

R

D3

R

D2

R/W

0

D1

R/W

0

D0

R/W

1

Memory type

Default value

0

Bit

Description

STIM[2:0]

Safety Timer bits.

STIM[2:0] RANGE 0

RANGE 1

STIM[2:0]

100

RANGE 0

RANGE 1

26.6ms

32.0ms

37.3ms

71.5ms

000

001

010

011

68.2ms

102.2ms

136.3ms

170.4ms

5.3ms

10.7ms

16.0ms

21.3ms

204.5ms

340.8ms

579.3ms

852ms

101

110

111

HPFL

High-Power LED Failure flag.

0: Proper LED operation.

1: LED failed (open or shorted).

High-power LED failure flag is reset after readout

SELSTIM

TO

Safety Timer Selection Range (Write Only).

0: Safety timer range 0.

1: Safety timer range 1.

Time-Out Flag (Read Only).

0: No time-out event occurred.

1: Time-out event occurred. Time-out flag is reset at re-start of the safety timer.

STT

Safety Timer Trigger bit.

0: LED safety timer is level sensitive.

1: LED safety timer is rising edge sensitive.

This bit is only valid for MODE_CTRL[1:0] = 10.

SFT

Start/Flash Timer bit.

In write mode, this bit initiates a flash strobe sequence. Notice that this bit is only active when STRB0 input is high.

0: No change in the high-power LED current.

1: High-power LED current ramps to the flash current level.

In read mode, this bit indicates the high-power LED status.

0: High-power LEDs are idle.

1: Ongoing high-power LED flash strobe.

Tx-MASK

Flash Blanking Control bit.

In write mode, this bit enables/disables the flash blanking/LED current reduction function.

0: Flash blanking disabled.

1: LED current is reduced to DC light level when Tx-MASK input is high.

In read mode, this flag indicates whether or not the flashlight masking input has been activated. Tx-MASK flag is reset

after readout of the flag.

0: No flash blanking event occurred.

1: Tx-MASK input triggered.

48

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REGISTER4 DESCRIPTION

Memory location: 0x04

Description

Bits

PG

D7

R/W

0

HOTDIE[1:0]

ILIM

D4

INC[3:0]

D6

D5

R

D3

R/W

0

D2

R/W

0

D1

R/W

0

D0

R/W

0

Memory type

Default value

R

0

R/W

0

Bit

PG

Description

Power Good bit.

In write mode, this bit selects the functionality of the GPIO/PG output.

0: PG signal is routed to the GPIO port.

1: GPIO PORT VALUE bit is routed to the GPIO port.

In read mode, this bit indicates the output voltage conditions.

0: The converter is not operating within the voltage regulation limits.

1: The output voltage is within its nominal value.

HOTDIE[1:0]

Instantaneous Die Temperature bits.

00: T_J< +55°C

01: +55°C < T_J< +70°C

10: T_J> +70°C

11: Thermal shutdown tripped. Indicator flag is reset after readout.

ILIM

Inductor Valley Current Limit bit.

The ILIM bit can only be set before the device enters operation (i.e. initial shutdown state).

VALLEY

CURRENT

LIMIT

ILIM BIT

SETTING

HC_SEL

INPUT LEVEL

Tx-MASK

INPUT LEVEL

SETTING

1150 mA

1600 mA

30 mA

Low

High

Low

High

Low

High

Low

High

Low

High

Low

High

Low

High

250 mA

1150 mA

1600 mA

n/a⁽¹⁾

INDC[3:0]

Indicator Light Control bits.

PRIVACY INDICATOR

INDLED CHANNEL

PRIVACY INDICATOR

INDC[3:0]

(2)

LED1-3 CHANNELS

5% PWM dimming ratio

11% PWM dimming ratio

17% PWM dimming ratio

23% PWM dimming ratio

30% PWM dimming ratio

36% PWM dimming ratio

48% PWM dimming ratio

67% PWM dimming ratio

0000

0001

0010

0011

0100

0101

0110

0111

Privacy indicator turned-off

INDLED current = 2.6mA⁽³⁾

INDLED current = 5.2mA⁽³⁾

INDLED current = 7.9mA⁽³⁾

Privacy indicator turned-off

INDLED current = 5.2mA⁽³⁾

INDLED current = 10.4mA⁽³⁾

1000

1001

1010

1011

1100

1101

1110

1111

(3)

INDLED current = 15.8mA

(1) The DC/DC power stage is disabled, zero current is being drained from the input source.

(2) This mode of operation can only be activated for MODE_CTRL[1:0] = 01 & ENVM = 1 & STRB1 = 0.

(3) For HC_SEL = L, the output node (VOUT) is internally pulled to ground.

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REGISTER5 DESCRIPTION

Memory location: 0x05

Description

SELFCAL

DIR (W)

STSTRB1 (R)

ENPSM

GPIO

GPIOTYPE

ENLED3

ENLED2

ENLED1

Bits

D7

R/W

0

D6

R/W

1

D5

R/W

1

D4

R/W

0

D3

R/W

1

D2

R/W

0

D1

R/W

1

D0

R/W

0

Memory type

Default value

Bit

Description

SELFCAL

High-Current LED Forward Voltage Self-Calibration Start bit.

In write mode, this bit enables/disables the output voltage vs. LED forward voltage/current self-calibration procedure.

0: Self-calibration disabled.

1: Self-calibration enabled.

In read mode, this bit returns the status of the self-calibration procedure.

0: Self-calibration ongoing

1: Self-calibration done Notice that this bit is only being reset at the (re-)start of a calibration cycle.

ENPSM

Enable / Disable Power-Save Mode bit.

0: Power-save mode disabled.

1: Power-save mode enabled.

STSTRB1

DIR

STRB1 Input Status bit (Read Only).

This bit indicates the logic state on the STRB1 state.

GPIO Direction bit.

0: GPIO configured as input.

1: GPIO configured as output.

GPIO

GPIO Port Value.

This bit contains the GPIO port value.

GPIOTYPE

GPIO Port Type.

0: GPIO is configured as push-pull output.

1: GPIO is configured as open-drain output.

ENLED3

ENLED2

ENLED1

Enable / Disable High-Current LED3 bit.

0: LED3 input is disabled.

1: LED3 input is enabled.

Enable / Disable High-Current LED2 bit.

0: LED2 input is disabled.

1: LED2 input is enabled.

Enable / Disable High-Current LED1 bit.

0: LED1 input is disabled.

1: LED1 input is enabled.

50

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REGISTER6 DESCRIPTION

Memory location: 0x06

Description

Bits

ENTS

D7

LEDHOT

LEDWARN

LEDHDR

OV[3:0]

D6

R/W

0

D5

R

D4

R

D3

R/W

1

D2

R/W

0

D1

R/W

0

D0

R/W

1

Memory type

Default value

R/W

0

Bit

Description

ENTS

Enable / Disable LED Temperature Monitoring.

0: LED temperature monitoring disabled.

1: LED temperature monitoring enabled

LEDHOT

LEDWARN

LEDHDR

LED Excessive Temperature Flag.

This bit can be reset by writing a logic level zero.

0: TS input voltage > 0.345V.

1: TS input voltage < 0.345V.

LED Temperature Warning Flag (Read Only).

This flag is reset after readout.

0: TS input voltage > 1.05V.

1: TS input voltage < 1.05V.

LED High-Current Regulator Headroom Voltage Monitoring bit.

This bit returns the headroom voltage status of the LED high-current regulators. This value is being updated at the end of a

flash strobe, prior to the LED current ramp-down phase.

0: Low headroom voltage.

1: Sufficient headroom voltage.

0V[3:0]

Output Voltage Selection bits.

In read mode, these bits return the result of the high-current LED forward voltage self-calibration procedure.

In write mode, these bits are used to set the target output voltage (refer to voltage regulation mode). In applications

requiring dynamic voltage control, care should be take to set the new target code after voltage mode operation has been

enabled (MODE_CTRL[1:0] = 11 and/or ENVM bit = 1).

OV[3:0]

0000

0001

0010

0011

0100

0101

0110

0111

1000

1001

1010

1011

1100

1101

1110

1111

Target Output Voltage

3.825V

3.950V

4.075V

4.200V

4.325V

4.450V

4.575V

4.700V

4.825V

4.950V

5.075V

5.200V

5.325V

5.450V

5.575V

5.700V

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REGISTER7 DESCRIPTION

Memory location: 0x07

Description

NOT USED

REVID[2:0]

Bits

D7

R/W

0

D6

R/W

0

D5

R/W

0

D4

R/W

0

D3

R/W

0

D2

R

D1

R

D0

R

Memory type

Default value

1

0

Bit

Description

REVID[2:0]

Silicon Revision ID.

52

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APPLICATION INFORMATION

INDUCTOR SELECTION

A boost converter requires two main passive components for storing energy during the conversion. A boost

inductor and a storage capacitor at the output are required. The TPS6132x device integrates a current limit

protection circuitry. The valley current of the PMOS rectifier is sensed to limit the maximum current flowing

through the synchronous rectifier and the inductor. The valley peak current limit (250mA/1150mA/1600mA) is

user selectable via the I²C interface.

In order to optimize solution size the TPS6132x device has been designed to operate with inductance values

between a minimum of 1.3 mH and maximum of 2.9 mH. In typical high current white LED applications a 2.2mH

inductance is recommended.

The highest peak current through the inductor and the power switch depends on the output load, the input and

output voltages. Estimation of the maximum average inductor current and the maximum inductor peak current

can be done using Equation 2 and Equation 3:

V

OUT

I

» I

´

L

OUT

η ´ V

IN

(2)

(3)

V

´ D

I

V - V

OUT IN

IN

OUT

I

=

+

with D =

L(PEAK)

2 ´ f ´ L

(1- D)´ h

V

OUT

With

f = switching frequency (2MHz)

L = inductance value (2.2mH)

h = estimated efficiency (85%)

The losses in the inductor caused by magnetic hysteresis losses and copper losses are a major parameter for

total circuit efficiency.

Table 4. List of Inductors

MANUFACTURER

SERIES

DIMENSIONS

ILIM SETTINGS

MIPST2520

MIP2520

2.5mm x 2.0mm x 0.8mm max. height

2.5mm x 2.0mm x 1.0mm max. height

2.5mm x 2.0mm x 1.2mm max. height

2.5mm x 2.0mm x 1.0mm max. height

2.6mm x 2.8mm x 1.4mm max. height

3.0mm x 3.0mm x 1.5mm max. height

2.5mm x 2.0mm x 1.2mm max. height

3.0mm x 3.0mm x 1.2mm max. height

3.2mm x 2.5mm x 1.2mm max. height

FDK

MIPSA2520

LQM2HP-G0

LQM2HP-GC

VLF3014AT

LPS3015

250mA (typ.)

MURATA

TDK

COILCRAFT

MURATA

TOKO

1150mA (typ.)

1600mA (typ.)

LQH2HPN

FDSE0312

LQM32PN

MURATA

INPUT CAPACITOR

For good input voltage filtering low ESR ceramic capacitors are recommended. A 10-mF input capacitor is

recommended to improve transient behavior of the regulator and EMI behavior of the total power supply circuit.

The input capacitor should be placed as close as possible to the input pin of the converter.

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OUTPUT CAPACITOR

The major parameter necessary to define the output capacitor is the maximum allowed output voltage ripple of

the converter. This ripple is determined by two parameters of the capacitor, the capacitance and the ESR. It is

possible to calculate the minimum capacitance needed for the defined ripple, supposing that the ESR is zero, by

using Equation 4:

IOUT × (VOUT - VIN)

Cmin »

f ´ DV ´ VOUT

(4)

Parameter f is the switching frequency and ΔV is the maximum allowed ripple.

With a chosen ripple voltage of 10mV, a minimum capacitance of 10mF is needed. The total ripple is larger due

to the ESR of the output capacitor. This additional component of the ripple can be calculated using Equation 5:

ΔV_ESR= I_OUT× R_ESR

(5)

The total ripple is the sum of the ripple caused by the capacitance and the ripple caused by the ESR of the

capacitor. Additional ripple is caused by load transients. This means that the output capacitor has to completely

supply the load during the charging phase of the inductor. A reasonable value of the output capacitance depends

on the speed of the load transients and the load current during the load change.

For the standard current white LED application (HC_SEL = 0, TPS6132x), a minimum of 3mF effective output

capacitance is usually required when operating with 2.2mH (typ) inductors. For solution size reasons, this is

usually one or more X5R/X7R ceramic capacitors.

Depending on the material, size and therefore margin to the rated voltage of the used output capacitor,

degradation on the effective capacitance can be observed. This loss of capacitance is related to the DC bias

voltage applied. It is therefore always recommended to check that the selected capacitors are showing enough

effective capacitance under real operating conditions.

To support high-current camera flash application (HC_SEL = 1), the converter is designed to work with a low

voltage super-capacitor on the output to take advantage of the benefits they offer. A low-voltage super-capacitor

in the 0.1F to 1.5F range, and with ESR larger than 40mΩ, is suitable in the TPS6132x application circuit. For

this device the output capacitor should be connected between the VOUT pin and a good ground connection.

54

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NTC SELECTION

The TPS6132x requires a negative thermistor (NTC) for sensing the LED temperature. Once the temperature

monitoring feature is activated, a regulated bias current (c.a. 24mA) will be driven out of the TS port and produce

a voltage across the thermistor.

If the temperature of the NTC-thermistor rises due to the heat dissipated by the LED, the voltage on the TS input

pin decreases. When this voltage goes below the “warning threshold”, the LEDWARN bit in REGISTER6 is set.

This flag is cleared by reading the register.

If the voltage on the TS input decreases further and falls below “hot threshold”, the LEDHOT bit in REGISTER6

is set and the device goes automatically in shutdown mode to avoid damaging the LED. This status is latched

until the LEDHOT flag gets cleared by software.

The selection of the NTC-thermistor value strongly depends on the power dissipated by the LED and all

components surrounding the temperature sensor and on the cooling capabilities of each specific application. With

a 220kΩ (at 25°C) thermistor, the valid temperature window is set between 60°C to 90°C. The temperature

window can be enlarged by adding external resistors to the TS pin application circuit. In order to ensure proper

triggering of the LEDWARN and LEDHOT flags in noisy environments, the TS signal may require additional

filtering capacitance.

Figure 73. Temperature Monitoring Characteristic

Table 5. List of Negative Thermistor (NTC)

MANUFACTURER

PART NUMBER

VALUE

MURATA

NCP18WM224J03RB

220kΩ

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CHECKING LOOP STABILITY

The first step of circuit and stability evaluation is to look from a steady-state perspective at the following signals:

•

Switching node, SW

Inductor current, I_L

Output ripple voltage, V_OUT(AC)

These are the basic signals that need to be measured when evaluating a switching converter. When the

switching waveform shows large duty cycle jitter or the output voltage or inductor current shows oscillations the

regulation loop may be unstable. This is often a result of improper board layout and/or L-C combination.

As a next step in the evaluation of the regulation loop the load transient response needs to be tested. VOUT can

be monitored for settling time, overshoot or ringing that helps judge the converter's stability. Without any ringing,

the loop has usually more than 45° of phase margin.

Because the damping factor of the circuitry is directly related to several resistive parameters (e.g., MOSFET

r_DS(on)) that are temperature dependant, the loop stability analysis has to be done over the input voltage range,

output current range, and temperature range.

LAYOUT CONSIDERATIONS

As for all switching power supplies, the layout is an important step in the design, especially at high peak currents

and high switching frequencies. If the layout is not carefully done, the regulator could show stability problems as

well as EMI problems. Therefore, use wide and short traces for the main current path and for the power ground

tracks.

The input capacitor, output capacitor, and the inductor should be placed as close as possible to the IC. Use a

common ground node for power ground and a different one for control ground to minimize the effects of ground

noise. Connect these ground nodes at any place close to one of the ground pins of the IC.

To lay out the control ground, it is recommended to use short traces as well, separated from the power ground

traces. This avoids ground shift problems, which can occur due to superimposition of power ground current and

control ground current.

L1

B2: SCL

B3: HC_SEL

C3: Tx_MASK

D3: STRB1

SDA

D4: GPIO/PG

C_OUT

INDLED

BAL

STRB0

1

TS

C_IN

GND

V_IN

LED2 LED1 LED3

Figure 74. Suggested Layout (Top)

56

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THERMAL INFORMATION

Implementation of integrated circuits in low-profile and fine-pitch surface-mount packages typically requires

special attention to power dissipation. Many system-dependant issues such as thermal coupling, airflow, added

heat sinks and convection surfaces, and the presence of other heat-generating components affect the

power-dissipation limits of a given component.

Three basic approaches for enhancing thermal performance are listed below:

•

Improving the power dissipation capability of the PCB design

Improving the thermal coupling of the component to the PCB

Introducing airflow in the system

Junction-to-ambient thermal resistance is highly application and board-layout dependent. In applications where

high maximum power dissipation exists, special care must be paid to thermal dissipation issues in board design.

The maximum junction temperature (T_J) of the TPS6132x is 150°C.

The maximum power dissipation is especially critical when the device operates in the linear down mode at high

LED current. For single pulse power thermal analysis (e.g., flashlight strobe), the allowable power dissipation for

the device is given by Figure 75. These values are derived using the reference design.

10

9

8

T

= 65°C rise

7

6

5

J

4

3

2

1

0

T

= 40°C rise

J

No Airflow

0

20 40 60 80 100 120 140 160 180 200

Pulse Width - ms

Figure 75. Single Pulse Power Capability

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TYPICAL APPLICATIONS

TPS61325

L

SW

VOUT

BAL

2.2 mH

AVIN

C_O

HC_SEL

2.5 V..5.5 V

D1

D2

C_I

10 mF

PHONE POWER ON

LED 1

LED 2

LED 3

STRB0

STRB1

CAMERA ENGINE

INDLED

SCL

SDA

Privacy

Indicator

2

I C I/F

1.8V

Tx-MASK

TS

NTC

220k

GPIO/PG

PGND

AGND

FLASH READY

Figure 76. 4100mA Two White High-Power LED Flashlight Featuring Storage Capacitor

TPS61325

L

SW

VOUT

BAL

2.2 mH

C_O

AVIN

10 mF

HC_SEL

2.5 V..5.5 V

D1

D2

C_I

LED 1

LED 2

LED 3

CAMERA ENGINE

FLASH SYNCHRONIZATION

STRB0

STRB1

INDLED

SCL

SDA

Privacy

Indicator

2

I C I/F

RF PA TX ACTIVE

Tx-MASK

TS

NTC

220k

GPIO/PG

PGND

AGND

Figure 77. 2x 600mA High Power White LED Solution Featuring Privacy Indicator

58

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PACKAGE SUMMARY

CHIP SCALE PACKAGE

(BOTTOM VIEW)

CHIP SCALE PACKAGE

(TOP VIEW)

A4

B4

C4

D4

E4

A3

B3

C3

D3

E3

A2

B2

C2

D2

E2

A1

B1

C1

D1

E1

YMLLLLS

TPS613__

D

A1

Code:

•

YM — Year Month date code

LLLL — Lot trace code

E

S — Assembly site code

CHIP SCALE PACKAGE DIMENSIONS

The TPS6132x device is available in a 20-bump chip scale package (YFF, NanoFree™). The package

dimensions are given as:

•

D = 2170 ±30 mm

E = 1928 ±30 mm

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PACKAGE OPTION ADDENDUM

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2-Apr-2010

PACKAGING INFORMATION

Orderable Device

TPS61325YFFR

TPS61325YFFT

Status ⁽¹⁾

ACTIVE

Package Package

Pins Package Eco Plan ⁽²⁾Lead/Ball Finish MSL Peak Temp ⁽³⁾

Qty

Type

Drawing

DSBGA

YFF

20

1

Green (RoHS &

no Sb/Br)

SNAGCU

Level-1-260C-UNLIM

DSBGA

YFF

20

250 Green (RoHS &

no Sb/Br)

SNAGCU

Level-1-260C-UNLIM

⁽¹⁾The marketing status values are defined as follows:

ACTIVE: Product device recommended for new designs.

LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.

NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in

a new design.

PREVIEW: Device has been announced but is not in production. Samples may or may not be available.

OBSOLETE: TI has discontinued the production of the device.

(2)

Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check

http://www.ti.com/productcontent for the latest availability information and additional product content details.

TBD: The Pb-Free/Green conversion plan has not been defined.

Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements

for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered

at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.

Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and

package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS

compatible) as defined above.

Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame

retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)

(3)

MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder

temperature.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is

provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the

accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take

reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on

incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited

information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI

to Customer on an annual basis.

Addendum-Page 1

IMPORTANT NOTICE

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and other changes to its products and services at any time and to discontinue any product or service without notice. Customers should

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sold subject to TI’s terms and conditions of sale supplied at the time of order acknowledgment.

TI warrants performance of its hardware products to the specifications applicable at the time of sale in accordance with TI’s standard

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acknowledge and agree that they are solely responsible for all legal, regulatory and safety-related requirements concerning their products

and any use of TI products in such safety-critical applications, notwithstanding any applications-related information or support that may be

provided by TI. Further, Buyers must fully indemnify TI and its representatives against any damages arising out of the use of TI products in

such safety-critical applications.

TI products are neither designed nor intended for use in military/aerospace applications or environments unless the TI products are

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specifications. Buyers acknowledge and agree that any such use of TI products which TI has not designated as military-grade is solely at

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TI products are neither designed nor intended for use in automotive applications or environments unless the specific TI products are

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products in automotive applications, TI will not be responsible for any failure to meet such requirements.

Following are URLs where you can obtain information on other Texas Instruments products and application solutions:

Products

Applications

Audio

Amplifiers

amplifier.ti.com

dataconverter.ti.com

www.dlp.com

www.ti.com/audio

Data Converters

DLP® Products

Automotive

www.ti.com/automotive

www.ti.com/communications

Communications and

Telecom

DSP

dsp.ti.com

Computers and

Peripherals

www.ti.com/computers

Clocks and Timers

Interface

www.ti.com/clocks

interface.ti.com

logic.ti.com

Consumer Electronics

Energy

www.ti.com/consumer-apps

www.ti.com/energy

Logic

Industrial

www.ti.com/industrial

Power Mgmt

Microcontrollers

RFID

power.ti.com

Medical

www.ti.com/medical

microcontroller.ti.com

www.ti-rfid.com

Security

www.ti.com/security

Space, Avionics &

Defense

www.ti.com/space-avionics-defense

RF/IF and ZigBee® Solutions www.ti.com/lprf

Video and Imaging

Wireless

www.ti.com/video

www.ti.com/wireless-apps

Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265


型号：	TPS61325YFF
厂家：	TEXAS INSTRUMENTS
描述：	1.5A/4.1A Multiple LED Camera Flash Driver With I2CTM Compatible Interface 1.5A / 4.1A多个LED相机闪光灯驱动器，带有I2C？兼容接口显示驱动器驱动程序和接口接口集成电路闪光灯
文件：	总62页 (文件大小：2299K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

TPS61325YFF [TI]

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