TPS61230A [TI]
采用 2.0mm x 2.0mm QFN 封装的 5V/6A 高效率升压转换器;
| 型号： | TPS61230A |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 采用 2.0mm x 2.0mm QFN 封装的 5V/6A 高效率升压转换器 升压转换器 |
| 文件： | 总29页 (文件大小：1646K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
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TPS61230A
ZHCSFD9B –JULY 2016–REVISED OCTOBER 2018
TPS61230A 采用 2.0mm x 2.0mm VQFN 封装的 5V/6A 高效升压转换器
1 特性
典型运行频率为 1.15MHZ，因此可使用小型电感和电
容实现小型封装尺寸。TPS61230A 通过一个外部电阻
分压器提供可调节输出电压。
1
•
•
•
输入电压范围：2.5V 至 4.5V
输出电压范围：2.5V 至 5.5V
两个 21mΩ (LS)/18mΩ (HS) 金属氧化物半导体场
效应晶体管 (MOSFET)
在轻载条件下，TPS61230A 自动进入 PFM 操作模
式，从而在最低静态电流下实现效率最大化。在关断期
间，通过将 EN 引脚拉至逻辑低电平，负载可与输入完
全断开，输入流耗同时降至 1.0µA 以下。
•
•
•
•
•
•
•
•
•
•
•
20µA 静态电流
6A 谷值开关电流限值
1.15MHz 准恒定开关频率
轻负载条件下以脉频调制 (PFM) 模式运行
1.05ms 软启动时间
真正实现负载断开连接
不支持在 Vin > Vout 时运行
输出短路保护
该器件在输出短路时进入断续保护模式并在短路结束后
自动恢复正常。集成了其他 特性， 如输出过压保护和
热关断保护。
该器件采用 2.00mm x 2.00mm x 0.9mm VQFN 封
装，所需外部组件最少。
过压保护
器件信息(1)
热关断
器件号
封装
VQFN (7)
封装尺寸（标称值）
采用 2.0mm x 2.0mm 7 引脚超薄四方扁平无引线
(VQFN) 封装
TPS61230A
2.00mm x 2.00mm
(1) 如需了解所有可用封装，请参阅产品说明书末尾的可订购产品
附录。
2 应用
•
•
•
•
•
移动电源、备用电池
器件比较表
USB 电源
器件型号
输出电压
可调节
平板电脑
TPS61230A
音频功率放大器
电池供电类产品
固定输出电压 3.7、4.3、4.5、4.8、5.0、
5.1、5.4
(1) 产品预览：请联系 TI 工厂获取更多信息。
TPS61230xA(1)
3 说明
TPS61230A 器件是一款高效全集成同步升压转换器。
该器件集成了 6A、21mΩ 和 18mΩ 电源开关。当以
2.5V 输入电源供电时，该开关能够在 5V 输出下提供
高达 2.4A 的输出电流。凭借低 RDS_ON 开关，该器件
的功率转换效率高达 96%，最大限度降低了紧凑型封
装中的热应力。
典型应用
效率
L
1uH
100
VOUT
5V/2.4A
SW
VOUT
90
80
70
60
50
40
C3
10nF
R1
316kΩ
TPS61230A
C2
2x22 uF
VIN
CBST
VIN
FB
R2
100kΩ
C1
10 uF
GND
ON
EN
OFF
Copyright © 2016, Texas Instruments Incorporated
VIN = 3.0 V
VIN = 3.6 V
VIN = 4.3 V
0.0001
0.001
0.01
Load (A)
0.1
1
3
D001
1
本文档旨在为方便起见，提供有关 TI 产品中文版本的信息，以确认产品的概要。 有关适用的官方英文版本的最新信息，请访问 www.ti.com，其内容始终优先。 TI 不保证翻译的准确
性和有效性。 在实际设计之前，请务必参考最新版本的英文版本。
English Data Sheet: SLVSCZ5
TPS61230A
ZHCSFD9B –JULY 2016–REVISED OCTOBER 2018
www.ti.com.cn
目录
1
2
3
4
5
6
特性.......................................................................... 1
应用.......................................................................... 1
说明.......................................................................... 1
修订历史记录 ........................................................... 2
Pin Configuration and Functions......................... 3
Specifications......................................................... 4
6.1 Absolute Maximum Ratings ...................................... 4
6.2 ESD Ratings ............................................................ 4
6.3 Recommended Operating Conditions....................... 4
6.4 Thermal Information.................................................. 4
6.5 Electrical Characteristics........................................... 5
6.6 Typical Characteristics.............................................. 6
Detailed Description .............................................. 8
7.1 Overview ................................................................... 8
7.2 Functional Block Diagram ......................................... 8
7.3 Feature Description................................................... 9
7.4 Device Functional Modes........................................ 11
8
9
Application and Implementation ........................ 12
8.1 Application Information............................................ 12
8.2 Typical Applications ................................................ 12
Power Supply Recommendations...................... 17
10 Layout................................................................... 18
10.1 Layout Guidelines ................................................. 18
10.2 Layout Example .................................................... 18
10.3 Thermal Considerations........................................ 19
11 器件和文档支持 ..................................................... 19
11.1 器件支持 ............................................................... 19
11.2 文档支持................................................................ 19
11.3 接收文档更新通知 ................................................. 19
11.4 社区资源................................................................ 19
11.5 商标....................................................................... 19
11.6 静电放电警告......................................................... 19
11.7 术语表 ................................................................... 19
12 机械、封装和可订购信息....................................... 20
7
4 修订历史记录
Changes from Revision A (July 2016) to Revision B
Page
•
Added thermal information for EVM configuration ................................................................................................................. 4
Changes from Original (July 2016) to Revision A
Page
•
已更改 从“产品预览”改为“生产数据” ....................................................................................................................................... 1
2
Copyright © 2016–2018, Texas Instruments Incorporated
TPS61230A
www.ti.com.cn
ZHCSFD9B –JULY 2016–REVISED OCTOBER 2018
5 Pin Configuration and Functions
RNS Package
7-Pin VQFN
Top View
SW
5
7
VOUT
6
GND
Not to scale
Pin Functions
PIN
I/O
DESCRIPTION
NAME
NUMBER
Boot strap capacitor for the supply of high-side MOSFET driver. An external capacitor is required
between the SW and CBST pins to provide supply voltage to the high-side MOSFET gate driver.
CBST
1
I
I
This is the enable pin of the device. Connecting this pin to ground ( < 0.4 V ) forces the device into
shutdown mode. Pulling this pin to high ( > 1.2 V ) enables the device. This pin must be terminated but
not floating.
EN
2
Voltage feedback of adjustable output voltage. Connecting a resistor divider network from the output of
the converter to the FB pin. Must be connected to VOUT on fixed output voltage version.
FB
VIN
SW
3
4
5
I
I
Supply voltage for the internal circuitry.
Switching node of the boost regulator. It is connected to the drain of the internal low side power FET
and the source of the internal high-side power FET.
I/O
Ground pin. Return for the internal voltage reference and analog circuits, also the source terminal of
the low-side FET switch.
GND
6
7
–
VOUT
O
Boost converter output.
Copyright © 2016–2018, Texas Instruments Incorporated
3
TPS61230A
ZHCSFD9B –JULY 2016–REVISED OCTOBER 2018
www.ti.com.cn
6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)(1)
MIN
-0.3
-0.3
-0.3
-40
MAX
6
UNIT
V
VIN, EN, VOUT, FB
(2)
Voltage range at terminals
SW
7
V
CBST
12
V
Operating junction temperature range, TJ
Storage temperature range, Tstg
150
150
°C
°C
-65
(1) Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating
conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods my affect device reliability.
(2) All voltages are with respect to network ground terminal.
6.2 ESD Ratings
VALUE
UNIT
Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1)
±2000
V(ESD)
Electrostatic discharge
V
Charged-device model (CDM), per JEDEC specification JESD22-
C101(2)
±750
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process. Manufacturing with
less than 500-V HBM is possible with the necessary precautions.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process. Manufacturing with
less than 250-V CDM is possible with the necessary precautions.
6.3 Recommended Operating Conditions
MIN
TYP
MAX
4.5
UNIT
V
VIN
VOUT
L
Input voltage range
2.5
Output voltage range
5.5
V
Effective inductance range
Effective input capacitance range
Effective output capacitance range
Operating junction temperature
0.47
1
1
10
22
1.3
µH
µF
µF
°C
CI
CO
TJ
15
80
-40
125
6.4 Thermal Information
TPS61230A
TPS61230A
THERMAL METRIC(1)
RNS 7 PINS (VQFN)
RNS 7 PINS (VQFN)
EVM(2)
UNIT
Standard
93
RθJA
RθJA
RθJB
RθJC
ψJT
Junction-to-ambient thermal resistance (no vias)
Junction-to-ambient thermal resistance (with vias underneath)
Junction-to-board thermal resistance
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
60.0
56
28.4
57.8
2.0
N/A(3)
N/A(3)
1.9
Junction-to-case thermal resistance
Junction-to-top characterization parameter
Junction-to-board characterization parameter
ψJB
28.1
27.7
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
(2) Measured on the evaluation module (EVM PWR767A), 2-layer 50mm × 63mm PCB (2 oz on all layers).
(3) N/A - Dose not apply for EVM configuration.
4
Copyright © 2016–2018, Texas Instruments Incorporated
TPS61230A
www.ti.com.cn
ZHCSFD9B –JULY 2016–REVISED OCTOBER 2018
6.5 Electrical Characteristics
TJ = -40 °C to 125 °C and VIN = 3.6 V. Typical values are at TJ = 25 °C, unless otherwise noted.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX UNIT
Power Supply
VIN
Input voltage range
2.5
4.5
2.5
V
V
VVIN_UVLO
VVIN_HYS
Input under voltage lockout
VIN UVLO hysteresis
VIN rising
150
20
mV
IC enabled, No load , No Switching, VOUT = 5 V,
VIN = 4.2 V
IQ_VIN
Quiescent current into VIN pin
50
µA
IQ_VOUT
ISD
Quiescent current into VOUT pin
Shutdown current into VIN
IC enabled, No load, No Switching VOUT = 5 V
IC disabled, TJ < 85°C, VIN = 4.2 V
25
55
1
µA
µA
0.2
Output
VOUT
Output voltage range
2.5
5.5
V
V
VFB_PWM
VFB_PFM
VOVP
Feedback voltage
PWM mode
PFM mode
1.171 1.195 1.219
101.2
Feedback voltage
% VFB
V
Output overvoltage protection threshold
Leakage current into FB pin
5.7
5.8
5.99
20
ILKG_FB
Power Switch
RDS(on)
RDS(on)
fsw
VFB = 1.2 V
nA
High-side MOSFET on resistance
Low-side MOSFET on resistance
Switching frequency
VIN = 3.6 V, VOUT = 5 V, CBST = 10 nF,
VIN = 3.6 V, VOUT = 5 V, CBST = 10 nF
VIN = 3.6 V, VOUT = 5 V, PWM Operation
18
21
35 mΩ
36 mΩ
805
1150
1495 kHz
tON_min
Minimum on time
180
ns
A
Linear mode, VOUT = 2.5 V
Linear mode, VOUT = 0 V
1.02
0.06
4.8
Pre-charge mode and short circuit
current limit (DC charge mode)
ILIM_PRE
0.6
7.8
1.9
A
ILIMIT
tstartup
TSD
Switching valley current limit
Soft Start time (boost)
6.3
1.05
160
10
A
VIN = 3.6 V, VOUT = 5 V
TJ rising
0.3
ms
°C
°C
Thermal shutdown threshold
Thermal shutdown hysteresis
TJ falling below TSD
Protection
THC_OFF
THC_ON
Time for the hiccup off time
Time for the hiccup on time
VIN = 3.6 V
VIN = 3.6 V
23
ms
ms
3.5
Logic Interface
VEN_H
EN Logic high threshold
EN Logic low threshold
EN pin input leakage current
1.0
0.3
V
V
VEN_L
0.4
ILKG_EN
Connected to 3.6V VIN
0.1
µA
版权 © 2016–2018, Texas Instruments Incorporated
5
TPS61230A
ZHCSFD9B –JULY 2016–REVISED OCTOBER 2018
www.ti.com.cn
6.6 Typical Characteristics
VIN = 3.6 V, VOUT = 5.0 V, TJ = -40°C to 125 °C, unless otherwise noted.
100
90
80
70
60
50
40
100
95
90
85
80
75
70
Load = 10 mA
Load = 100 mA
Load = 1 A
VIN = 3.0 V
VIN = 3.6 V
VIN = 4.3 V
Load = 2A
0.0001
0.001
0.01
Load (A)
0.1
1
3
2.5 2.7 2.9 3.1 3.3 3.5 3.7 3.9 4.1 4.34.4
Input Voltage (V)
D001
D001
TA = 25 ºC
图 1. Efficiency vs. Output Current
TA = 25 ºC
图 2. Efficiency vs. Input Voltage
5.20
5.16
5.12
5.08
5.04
5.00
4.96
5.15
5.10
5.05
5.00
4.95
4.90
Load = 10 mA
Load = 100 mA
Load = 1 A
Load = 2 A
VIN = 3.0 V
VIN = 3.6 V
VIN = 4.3 V
2.5
3
3.5
4
4.5
0.0001
0.001
0.01
Load (A)
0.1
1
3
Input Voltage (V)
D001
D001
TA = 25 ºC
TA = 25 ºC
图 3. Line Regulation
图 4. Load Regulation
1.8
1.7
1.6
1.5
1.4
1.3
1.2
1.1
1.0
30
25
20
15
10
VIN = 3.0 V
VIN = 3.6 V
VIN = 4.2 V
0.3
0.5
0.7
0.9
1.1
Load (A)
1.3
1.5
1.7
1.9 2
-40
-20
0
20
40
60
80
100
120
Junction Temperature (oC)
D001
D001
TA = 25 ºC
VOUT = 5 V
VIN = 3.6V
图 5. Frequency vs. Load
图 6. High-Side FET Rdson vs Junction Temperature
6
版权 © 2016–2018, Texas Instruments Incorporated
TPS61230A
www.ti.com.cn
ZHCSFD9B –JULY 2016–REVISED OCTOBER 2018
Typical Characteristics (接下页)
VIN = 3.6 V, VOUT = 5.0 V, TJ = -40°C to 125 °C, unless otherwise noted.
30
25
20
15
10
1.210
1.205
1.200
1.195
1.190
1.185
1.180
-40
-20
0
20
40
60
80
100
120
-40
-20
0
20
40
60
80
100
120
Junction Temperature (oC)
Junction Temperature (oC)
D001
D001
VOUT = 5 V
VIN = 3.6V
图 7. Low-Side FET Rdson vs Junction Temperature
图 8. Voltage Reference vs Junction Temperature
40
35
30
25
20
15
10
5
6.5
6
5.5
5
4.5
TJ = -40oC
TJ = 25oC
TJ = 85oC
TJ = -40oC
TJ = 25oC
TJ = 125oC
4
2.5
3
3.5
4
4.5
2.5
3
3.5
4
4.5
Input Voltage (V)
Input Voltage (V)
D001
D001
图 9. Quiescent Current vs Input Voltage
图 10. Switch Valley Current Limit vs Input Voltage
2.4
2.3
2.2
2.1
1.2
1.1
1.0
0.9
0.8
0.7
0.6
0.5
0.4
0.3
0.2
VIN Rising
VIN Falling
EN Rising
EN Falling
-40
-20
0
20
40
60
80
100
120
-40
-20
0
20
40
60
80
100
120
Junction Temperature (oC)
Junction Temperature (oC)
D001
D001
图 11. Vin UVLO Threshold vs Junction Temperature
图 12. EN logic Threshold vs Junction Temperature
版权 © 2016–2018, Texas Instruments Incorporated
7
TPS61230A
ZHCSFD9B –JULY 2016–REVISED OCTOBER 2018
www.ti.com.cn
7 Detailed Description
7.1 Overview
The TPS61230A is a high efficiency synchronous boost converter with integrating the 21-mΩ low side FET and
18-mΩ high side FET. The device could deliver up to 12-W output power with 5.5-V maximum output voltage
from single cell Li-Iron battery. TPS61230A uses a quasi constant on-time valley current mode which provides an
excellent transient response. The TPS61230xA typically operates at a quasi-constant 1.15-MHz frequency pulse
width modulation (PWM) at the moderate to heavy load currents, allows the use of small inductor and capacitors
to achieve a compact solution size.
During the PWM operation, a simple circuit predicts the required on time (with the VIN / VOUT ratio) of the ow-
side FET. At the beginning of each switching cycle, the low-side FET turns on and the inductor current ramps up
to the peak current determined by the on-time and the inductance. Once the on-timer expires, the high-side FET
turns on and the inductor current decays to a preset valley current threshold determined by the Error Amplifier’s
output. The switching cycle repeats again by calculating the on time and activating the low-side FET.
At the light load currents, TPS61230A operates in Power Save Mode with pulse frequency modulation (PFM) and
improves the efficiency under the light load.
Internal soft-start and loop compensation simplifies the design process and minimizes the number of external
components.
7.2 Functional Block Diagram
L
VIN
CIN
VIN
CBST
SW
4
5
1
VOUT
7
UVLO
Thermal
Shutdown
VIN
VOUT
COUT
ON
EN
Current Sense
2
OFF
Gate Driver
Logic
VOUT
R2
R1
REF
FB
3
Soft Start
Control
Pulse Modulator
VOUT
OVP & Short
Protection
GND
6
Copyright © 2016, Texas Instruments Incorporated
8
版权 © 2016–2018, Texas Instruments Incorporated
TPS61230A
www.ti.com.cn
ZHCSFD9B –JULY 2016–REVISED OCTOBER 2018
7.3 Feature Description
7.3.1 Startup
When the device is enabled, the high-side FET turns on to charge the output capacitor linearly by a DC current
which is called the pre-charge phase. The pre-charge startup phase terminates until the output voltage being
close to the input voltage (typically VOUT = VIN -115mV). Once the output capacitor has been biased close to
the input voltage (VOUT = VIN -115mV), the device starts switching which is called the boost soft start phase.
During the soft start phase, there is a soft start voltage controlling the FB pin voltage, and the output voltage
rising slope follows the soft start voltage slew rate (typically). The soft start phase completes when the soft start
voltage reaches the internal reference voltage. The device begins to operate normally and regulates the output
voltage at the pre-set target value.
表 1. Start-up Mode Description
MODE
DESCRIPTION
CONDITION
Pre-charge
Vout linearly startup without switching
Vout startup with switching phase
VOUT < VIN – 115mV
VOUT > VIN -115mV
Boost Soft Start
7.3.2 Enable and Disable
The device is enabled by setting EN pin to a voltage above 1.2V. At first, the internal reference is activated and
the internal analog circuits are settled. Afterwards, the startup is activated and the output voltage ramps up. With
the EN pin pulled to ground, the device enters into the shutdown mode. In the shutdown mode, the TPS61230A
stops switching and the internal control circuitry is turned off.
7.3.3 Under-Voltage Lockout (UVLO)
The under voltage lockout circuit prevents the device from malfunctioning at the low input voltage of the battery
from the excessive discharge. The device starts operation once the rising VIN trips the under-voltage lockout
threshold (UVLO) , and it disables the output stage of the converter once the VIN is below UVLO falling
threshold.
7.3.4 Current Limit Operation
During the startup phase, the output current is limited to the pre-charge current limit which is proportional to the
output voltage. The device could support minimum 1.0A output current at 2.5V input.
The TPS61230A employs a valley current sensing scheme at the normal boost switching phase. The switch
valley current limit detection occurs during the off time through the sensing the voltage drop across the rectifier
FET. If the switch valley current is lower than the valley current limit level, the device turns off the rectifier FET.
The maximum continuous output current (IOUT_LIM), prior to entering current limit operation, can be defined by:
1
IOUT _LIM = (1-D)ì(IVALLEY _LIM
+
DIL )
2
(1)
V ì h
VOUT
IN
D = 1-
(2)
(3)
V
D
f
IN
DIL =
ì
L
If the output current is further increased and the output voltage is pulled blow the input voltage, the TPS61230A
enters into the hiccup protection mode. The average current and thermal will be much lowered at the hiccup
steady state and the device could recovery automatically as long as the over load condition being released.
版权 © 2016–2018, Texas Instruments Incorporated
9
TPS61230A
ZHCSFD9B –JULY 2016–REVISED OCTOBER 2018
www.ti.com.cn
Load
increasing
IVALLEY_LIM
IOUT_LIM
IOUT
(1-D)T
DT
T = 1 / f
∆IL = (VIN / L) x (D / f)
图 13. Current Limit Operation
7.3.5 Over Voltage Protection
The device stops switching as soon as the output voltage exceeds the over voltage protection (OVP) threshold.
Both of the low side FET and high side FET turn off. The device resumes the normal operation when the output
voltage is below the OVP threshold.
7.3.6 Load Disconnect
The TPS61230A disconnects the output from the input of the power supply when the device is shutdown. In case
of a connected battery it prevents it from being discharged during the shutdown of the converter.
7.3.7 Thermal Shutdown
The TPS61230A has a built-in temperature sensor which monitors the internal junction temperature, TJ. If the
junction temperature exceeds the threshold (160 °C typical), the device goes into the thermal shutdown, and the
high-side and low-side FETs turn off. When the junction temperature falls below the thermal shutdown falling
threshold (150 °C typical), the device resumes the operation.
10
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TPS61230A
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ZHCSFD9B –JULY 2016–REVISED OCTOBER 2018
7.4 Device Functional Modes
The TPS61230A has two operation modes, as shown in 表 2.
表 2. Operation Mode Description
MODE
PWM
PFM
DESCRIPTION
Boost in normal switching operation Heavy load
Boost in power save operation Light load
CONDITION
7.4.1 PWM Mode
The TPS61230A typically operates at a quasi-constant 1.15 MHz frequency pulse width modulation (PWM) at
moderate to heavy load currents.
7.4.2 PFM Mode
The device integrates a power save mode with the pulse frequency modulation (PFM) to improve the efficiency at
the light load. In the PFM mode, the device starts to switch when the output voltage trips below a set threshold
voltage. When the output voltage ramping over the PFM threshold, the device stops switching. The DC output
voltage in PFM mode rises above the nominal output voltage in PWM mode by 1.2%.
VOUT
PFM at light load
PWM at medium to
heavy load
∆V=1.012 x VOUT_NORM
VOUT_NORM
t
图 14. Output Voltage in PFM / PWM Mode
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11
TPS61230A
ZHCSFD9B –JULY 2016–REVISED OCTOBER 2018
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8 Application and Implementation
注
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
8.1 Application Information
The TPS61230A is designed to operate from an input voltage supply range between 2.5 V and 4.5 V with a
maximum output current of 2.4 A. The device operates in PWM mode for medium to heavy load conditions and in
the PFM mode at the light load currents. In PWM mode the TPS61230A converter operates with the nominal
switching frequency of 1.15 MHz which provides a controlled frequency variation over the input voltage range. As
the load current decreases, the converter enters into the PFM mode, reducing the switching frequency and
minimizing the quiescent current to achieve the high efficiency over the entire load current range.
8.2 Typical Applications
8.2.1 TPS61230A 2.5-V to 4.5-V Input, 5-V Output Converter
L
1uH
VOUT
5V/2.4A
SW
VOUT
C3
10nF
R1
316kΩ
TPS61230A
C2
2x22 uF
VIN
CBST
VIN
FB
R2
100kΩ
C1
10 uF
GND
ON
EN
OFF
Copyright © 2016, Texas Instruments Incorporated
图 15. TPS61230A 5-V Output Typical Application
8.2.1.1 TPS61230A 5-V Output Design Requirements
Use the following typical application design procedure to select the external components values for the
TPS61230A device.
表 3. TPS61230A 5-V Output Design Parameters
DESIGN PARAMETERS
Input Voltage Range
Output Voltage
EXAMPLE VALUES
2.5 V to 4.5 V
5.0 V
Output Voltage Ripple
Transient Response
Input Voltage Ripple
Output Current Rating
Operating frequency
+/- 3% VOUT
+/- 10% VOUT
+/- 200mV
2.4 A
1.15 MHz
12
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TPS61230A
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ZHCSFD9B –JULY 2016–REVISED OCTOBER 2018
8.2.1.2 TPS61230A 5-V Detailed Design Procedure
表 4. TPS61230A 5-V Output List of Components
REFERENCE
DESCRIPTION
MANUFACTURER
Coilcraft
L
1.0 μH, Power Inductor, XFL4020-102MEB
22 μF 6.3V, 0805, X5R ceramic, GRM21BR61A226ME44
2 × 22 μF 10V, 0805, X5R ceramic, GRM21BR61A226ME44
10 nF, X7R ceramic
CIN
Murata
COUT
CBST
R2
Murata
Murata
316k, Resistor, Chip, 1/10W, 1%
Vishay-Dale
Vishay-Dale
R1
100k,Resistor, Chip, 1/10W, 1%
8.2.1.2.1 Programming The Output Voltage
The TPS61230A's output voltage need to be programmed via an external voltage divider to set the desired
output voltage.
An external resistor divider is used, as shown in 公式 4. By selecting R1 and R2, the output voltage is
programmed to the desired value. When the output voltage is regulated, the typical voltage at the FB pin is VFB
.
The following equation can be used to calculate R1 and R2.
R1
R2
R1
R2
æ
ö
æ
ö
VOUT = VFB ´ 1+
= 1.195V ´ 1+
ç
÷
ç
÷
è
ø
è
ø
(4)
R2 is typically around 100kΩ to ensure that the current following through R2 is at least 100 times larger than FB
pin leakage current. Changing R2 towards a lower value increases the robustness against noise injection.
Changing the R2 towards higher values reduces the quiescent current for achieving highest efficiency at low load
currents.
For the fixed output voltage version, the FB pin must be tied to the output directly.
8.2.1.2.2 Inductor and Capacitor Selection
The second step is the selection of the inductor and capacitor components.
8.2.1.2.2.1 Inductor Selection
A boost converter requires two main passive components for storing energy during the conversion, an inductor
and an output capacitor. It is advisable to select an inductor with a saturation current rating higher than the
possible peak current flowing through the power FETs. The inductor peak current varies as a function of the load,
the input and output voltages and is estimated using 公式 5.
IOUT
V
´D
1
IN
IL(PEAK)
=
+
´
(1- D)´ h
2
L ´ fSW
(5)
Where
η = Power conversion estimated efficiency
Selecting an inductor with the insufficient saturation performance can lead to the excessive peak current in the
converter. This could eventually harm the device and reduce reliability. It's recommended to choose the
saturation current for the inductor 20%~30% higher than the IL(PEAK), from 公式 5. The following inductors are
recommended to be used in designs.
表 5. List of Inductors
INDUCTANCE
[µH]
CURRENT
RATING [A]
DC RESISTANCE
PART NUMBER
MANUFACTURER
[mΩ]
1.0
1.0
9.0
5.1
12
744 383 560 10
Wurth
10.8
XFL4020-102MEB
Coilcraft
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13
TPS61230A
ZHCSFD9B –JULY 2016–REVISED OCTOBER 2018
www.ti.com.cn
8.2.1.2.2.2 Output Capacitor Selection
For the output capacitor, it is recommended to use small X5R or X7R ceramic capacitors placed as close as
possible to the VOUT and GND pins of the IC. If, for any reason, the application requires the use of large
capacitors which can not be placed close to the IC, using a smaller ceramic capacitor of 1 µF in parallel to the
large one is highly recommended. This small capacitor should be placed as close as possible to the VOUT and
GND pins of the IC.
Care must be taken when evaluating a capacitor’s derating under bias. The bias can significantly reduce
capacitance. Ceramic capacitors can loss as much as 50% of their capacitance at rated voltage. Therefore, leave
margin on the voltage rating to ensure adequate effective capacitance.
The ESR impact on the output ripple must be considered as well, if tantalum or electrolytic capacitors are used.
Assuming there is enough capacitance such that the ripple due to the capacitance can be ignored, the ESR
needed to limit the VRipple is:
VRipple(ESR) = IL(PEAK) ´ESR
(6)
8.2.1.2.2.3 Input Capacitor Selection
Multilayer X5R or X7R ceramic capacitors are an excellent choice for input decoupling of the step-up converter
as they have extremely low ESR and are available in small footprints. Input capacitors should be located as
close as possible to the device. While a 10 μF input capacitor is sufficient for most applications, larger values
may be used to reduce input current ripple without limitations. Take care when using only ceramic input
capacitors. When a ceramic capacitor is used at the input and the power is being supplied through long wires,
such as from a wall adapter, a load step at the output can induce ringing at the VIN pin. This ringing can couple
to the output and be mistaken as loop instability or could even damage the part. Additional "bulk" capacitance
(electrolytic or tantalum) should in this circumstance be placed between CIN and the power source to reduce the
ringing that can occur between the inductance of the power source leads and CIN.
8.2.1.2.3 Loop Stability, Feed Forward Capacitor
The third step is to check the loop stability. The stability evaluation is to look from a steady-state perspective at
the following signals:
•
•
•
Switching node, SW
Inductor current, IL
Output ripple, VRipple(OUT)
When the switching waveform shows large duty cycle jitter or the output voltage or inductor current shows
oscillations, the regulation loop may be unstable. This is often a result of board layout and/or L-C combination.
The load transient response is another approach to check the loop stability. During the load transient recovery
time, VOUT can be monitored for settling time, overshoot or ringing that helps judge the converter’s stability.
Without any ringing, the loop has usually more than 45° of phase margin.
As for the heavy load transient applications such as a 2 A load step transient, a feed forward capacitor in parallel
with R1 is recommended. The feed forward capacitor increases the loop bandwidth by adding a zero.
14
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TPS61230A
www.ti.com.cn
ZHCSFD9B –JULY 2016–REVISED OCTOBER 2018
8.2.1.3 TPS61230A 5-V Output Application Performance Plots
VOUT (AC) 20 mV/div
VOUT (AC) 30 mV/div
SW 2 V/div
IL 1 A/div
SW 3 V/div
IL 2 A/div
Time scale: 20 ms/div
Time scale: 20 ms/div
VOUT = 5 V, VIN = 3.6 V, IOUT = 2 A, TA = 25 ºC, L = 1 µH,
COUT = 2x22 µF
VOUT = 5 V, VIN = 3.6 V, IOUT = 10 mA, TA = 25 ºC
图 16. Steady State Switching at PWM
图 17. Steady State Switching at PFM
EN 2 V/div
Load 1.5 A/div
VOUT 5V Offset 100 mV/div
VOUT 2 V/div
IL 1 A/div
IL 1 A/div
Time scale: 500 ms/div
Time scale: 10 ms/div
VOUT = 5 V, VIN = 3.6 V, ROUT = 5 Ω, TA = 25 ºC
图 18. Startup by EN
VOUT = 5 V, VIN = 3.6 V, IOUT = 0 - 2 A Sweep, TA = 25 ºC
图 19. Load Sweep
Load 500 mA/div
Load 200 mA/div
VOUT (AC) 200 mV/div
VOUT AC 200 mV/div
IL 1 A/div
IL 1 A/div
Time scale: 50 ms/div
Time scale: 500 ms/div
VOUT = 5 V, VIN = 3.6 V, IOUT = 0.1 - 1 A with 10 µs slew rate,
TA = 25 ºC
VOUT = 5 V, VIN = 3.6 V, IOUT = 0.5 - 1 A with 10 µs slew rate,
TA = 25 ºC
图 20. Load Transient PFM / PWM
图 21. Load Transient PWM
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TPS61230A
ZHCSFD9B –JULY 2016–REVISED OCTOBER 2018
www.ti.com.cn
VIN 500 mV/div
VOUT 2 V/div
IL 1 A/div
VOUT (AC) 20 mV/div
IL 1 A/div
Time scale: 200 ms/div
Time scale: 20 ms/div
VOUT = 5 V, VIN = 3.6 - 4.2 V, Slew rate 50 µs, IOUT = 1 A,
TA = 25 ºC
VOUT = 5 V, VIN = 3.6 V, IOUT = 1 A before short, TA = 25 ºC
图 22. Line Transient
图 23. Output Short Entry
VOUT 10 mV/div
IL 200 mA/div
Time scale: 10 ms/div
VOUT = 5 V, VIN = 3.6 V, IOUT short, TA = 25 ºC
图 24. Output Short Steady State
16
版权 © 2016–2018, Texas Instruments Incorporated
TPS61230A
www.ti.com.cn
ZHCSFD9B –JULY 2016–REVISED OCTOBER 2018
8.2.2 Systems Example - TPS61230A with Feed Forward Capacitor for Best Transient Response
As for the heavy load transient applications such as a 2 A load step transient, a feed forward capacitor in parallel
with R1 is recommended. The feed forward capacitor increases the loop bandwidth by adding a zero. This results
in a lower output voltage drop, as shown in . See Application Note SLVA289.for the feed forward capacitor
selection.
L
1uH
VOUT
5V/2.4A
SW
VOUT
C3
10nF
R1
316kΩ
TPS61230A
C2
10 pF
C2
2x22 uF
VIN
CBST
VIN
FB
R2
100kΩ
C1
10 uF
GND
ON
EN
OFF
Copyright © 2016, Texas Instruments Incorporated
图 25. TPS61230A 5-V Output with Cff Typical Application
9 Power Supply Recommendations
The device is designed to operate from an input voltage supply range between 2.5 V and 4.5 V. This input supply
must be well regulated. If the input supply is located more than a few inches from the converter, additional bulk
capacitance may be required in addition to the ceramic bypass capacitors. An electrolytic or tantalum capacitor
with a value of 47 μF is a typical choice.
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TPS61230A
ZHCSFD9B –JULY 2016–REVISED OCTOBER 2018
www.ti.com.cn
10 Layout
10.1 Layout Guidelines
For all switching power supplies, the layout is an important step in the design, especially at high peak currents
and high switching frequencies. If the layout is not carefully done, the regulator could show stability problems as
well as EMI problems. Therefore, use wide and short traces for the main current path and for the power ground
tracks. The input capacitor, output capacitor, and the inductor should be placed as close as possible to the IC.
Use a common ground node for power ground and a different one for control ground to minimize the effects of
ground noise. Connect these ground nodes at the GND pin of the IC. The most critical current path for all boost
converters is from the switching FET, through the synchronous FET, then the output capacitors, and back to
ground of the switching FET. Therefore, the output capacitors and their traces should be placed on the same
board layer as the IC and as close as possible between the IC’s VOUT and GND pin.
See 图 26 for the recommended layout.
10.2 Layout Example
Top Layer
Bottom Layer
VIN
L
CIN
SW
GND
GND
VIN
FB
RUP_FB
COUT2
COUT1
EN
RDOWN_FB
GND
CBST
VOUT
SW
VOUT
CBST
图 26. Layout Recommendation
18
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TPS61230A
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ZHCSFD9B –JULY 2016–REVISED OCTOBER 2018
10.3 Thermal Considerations
Implementation of integrated circuits in low-profile and fine-pitch surface-mount packages typically requires
special attention to power dissipation. Many system-dependent issues such as thermal coupling, airflow, added
heat sinks and convection surfaces, and the presence of other heat-generating components affect the power-
dissipation limits of a given component.
Two basic approaches for enhancing thermal performance are listed below.
•
•
Improving the power dissipation capability of the PCB design
Introducing airflow in the system
For more details on how to use the thermal parameters in the dissipation ratings table please check the Thermal
Characteristics Application Note (SZZA017) and the IC Package Thermal Metrics Application Note (SPRA953).
11 器件和文档支持
11.1 器件支持
11.1.1 第三方产品免责声明
TI 发布的与第三方产品或服务有关的信息，不能构成与此类产品或服务或保修的适用性有关的认可，不能构成此类
产品或服务单独或与任何 TI 产品或服务一起的表示或认可。
11.2 文档支持
11.2.1 相关文档
请参阅如下相关文档：
•
•
《散热特性应用手册》（文献编号：SZZA017）
《IC 封装热指标应用手册》（文献编号：SPRA953）
11.3 接收文档更新通知
要接收文档更新通知，请导航至 TI.com.cn 上的器件产品文件夹。单击右上角的通知我 进行注册，即可每周接收产
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11.4 社区资源
下列链接提供到 TI 社区资源的连接。链接的内容由各个分销商“按照原样”提供。这些内容并不构成 TI 技术规范，
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TI E2E™ 在线社区 TI 的工程师对工程师 (E2E) 社区。此社区的创建目的在于促进工程师之间的协作。在
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设计支持
TI 参考设计支持 可帮助您快速查找有帮助的 E2E 论坛、设计支持工具以及技术支持的联系信息。
11.5 商标
E2E is a trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
11.6 静电放电警告
ESD 可能会损坏该集成电路。德州仪器 (TI) 建议通过适当的预防措施处理所有集成电路。如果不遵守正确的处理措施和安装程序 , 可
能会损坏集成电路。
ESD 的损坏小至导致微小的性能降级 , 大至整个器件故障。 精密的集成电路可能更容易受到损坏 , 这是因为非常细微的参数更改都可
能会导致器件与其发布的规格不相符。
11.7 术语表
SLYZ022 — TI 术语表。
这份术语表列出并解释术语、缩写和定义。
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12 机械、封装和可订购信息
以下页面包含机械、封装和可订购信息。这些信息是指定器件的最新可用数据。数据如有变更，恕不另行通知，且
不会对此文档进行修订。如需获取此产品说明书的浏览器版本，请查阅左侧的导航栏。
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PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
TPS61230ARNSR
TPS61230ARNST
ACTIVE
ACTIVE
VQFN-HR
VQFN-HR
RNS
RNS
7
7
3000 RoHS & Green
250 RoHS & Green
NIPDAU
Level-1-260C-UNLIM
Level-1-260C-UNLIM
-40 to 125
-40 to 125
12EI
12EI
NIPDAU
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
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10-Dec-2020
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
29-May-2019
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
TPS61230ARNSR
TPS61230ARNST
VQFN-
HR
RNS
RNS
7
7
3000
250
180.0
8.4
2.3
2.3
1.15
4.0
8.0
Q2
VQFN-
HR
180.0
8.4
2.3
2.3
1.15
4.0
8.0
Q2
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
29-May-2019
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SPQ
Length (mm) Width (mm) Height (mm)
TPS61230ARNSR
TPS61230ARNST
VQFN-HR
VQFN-HR
RNS
RNS
7
7
3000
250
182.0
182.0
182.0
182.0
20.0
20.0
Pack Materials-Page 2
PACKAGE OUTLINE
RNS0007A
VQFN - 1 mm max height
SCALE 4.750
PLASTIC QUAD FLATPACK - NO LEAD
2.1
1.9
A
B
PIN 1 INDEX AREA
2.1
1.9
1 MAX
C
SEATING PLANE
0.08 C
PKG
(0.2) TYP
1.1
0.9
0.8
0.6
0.05
0.00
0.35
2X
0.25
7
6
0.015 PIN 5
PKG
0.54
5
0.3
0.2
0.45
3X
0.35
0.45
0.35
4
1
0.3
4X
0.2
0.1
0.05
3X 0.5
C B
C
A
2X 1.5
ALL PADS
4222253/A 09/2015
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
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EXAMPLE BOARD LAYOUT
RNS0007A
VQFN - 1 mm max height
PLASTIC QUAD FLATPACK - NO LEAD
3X (0.5)
4
PKG
4X (0.25)
4X (0.6)
1
(0.9)
(0.015)
PIN 5
(2.4)
5
PKG
(0.54)
(0.25)
7
6
(R0.05) TYP
2X (0.3)
(0.6)
(0.75)
(0.9)
(1.2)
LAND PATTERN EXAMPLE
SCALE:25X
0.05 MAX
ALL AROUND
0.05 MIN
SOLDER MASK
OPENING
ALL AROUND
METAL
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
SOLDER MASK
DEFINED
NON SOLDER MASK
DEFINED
PADS 5-7
PADS 1-4
SOLDER MASK DETAILS
4222253/A 09/2015
NOTES: (continued)
3. For more information, see Texas Instruments literature number SLUA271 (www.ti.com/lit/slua271).
4. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
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EXAMPLE STENCIL DESIGN
RNS0007A
VQFN - 1 mm max height
PLASTIC QUAD FLATPACK - NO LEAD
3X (0.5)
PKG
4X (0.25)
4X (0.6)
(R0.05) TYP
1
4
4X
EXPOSED METAL
(0.9)
3X
(0.015)
PIN 5
2X (0.86)
3X (0.66)
5
PKG
(0.54)
3X (0.25)
7
6
3X (0.3)
2X (0.525)
(0.8)
SOLDER MASK
EDGE, TYP
METAL UNDER
SOLDER MASK
TYP
(0.263)
(0.938)
(0.8)
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
PRINTED SOLDER COVERAGE BY AREA UNDER PACKAGE
PAD 5: 79%, PADS 6 & 7: 85%
SCALE:30X
4222253/A 09/2015
NOTES: (continued)
5. For alternate stencil design recommendations, see IPC-7525 or board assembly site preference.
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