TPS61230DRCR [TI]
5A 可调节输出电压高效同步升压转换器 | DRC | 10 | -40 to 85;
| 型号： | TPS61230DRCR |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 5A 可调节输出电压高效同步升压转换器 | DRC | 10 | -40 to 85 升压转换器 开关 光电二极管 输出元件 |
| 文件： | 总32页 (文件大小：1822K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
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TPS61230, TPS61231, TPS61232
ZHCS174C –JANUARY 2014–REVISED OCTOBER 2014
TPS6123x 具有 5A 开关的高效同步升压转换器
1 特性
3 说明
1
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输入电压范围：2.3V 至 5.5V
TPS6123x 器件系列是一款采用紧凑解决方案尺寸的高
效同步升压转换器。 它针对由单节锂离子电池或 3.3V
稳压电源轨供电的产品进行了优化。集成电路 (IC) 中
集成了一个 5A 开关，并且能够在由 3.3V 输入电源供
电，输出电压为 5V 时传送高达 2.1A 的输出电流。 此
器件基于准恒定接通时间谷值电流模式控制机制。 典
型运行频率为 2MHZ，这样可使用小型电感器和电容
器来实现小解决方案尺寸。 TPS61230 和 TPS61231
通过一个外部电阻分压器提供可调输出电压，而
TPS61232 提供 5V 的固定输出电压。
输出电压范围：2.5V 至 5.5V
同步升压转换器效率高达 96%
输出电流 2.1A 的 3.3V 至 5V 电源转换
带有可调阀值/滞后的输入电源电压监控器
用于在轻载时实现高效率的省电模式
关断期间负载断开
输出过压保护
可编程软启动
电源正常输出
2MHz 开关频率
轻负载期间，TPS6123x 自动进入省电模式，以最低静
态电流实现最大效率。 在关断期间，负载完全从输入
上断开，并且输入流耗减少至 1.5µA（典型值）。 此
器件集成一个精密低功率 EN 比较器。 EN 阀值以及使
能比较器的滞后可由外部电阻器调节，并且支持应用专
用系统加电和断电要求。 还内置了其他诸如输出过压
保护、热关断保护和电源正常输出等特性。
输出电容器放电 (TPS61231)
3mm x 3mm x 0.9mm 超薄小外形尺寸无引线
(VSON) 封装
2 应用范围
•
•
•
•
•
低压锂离子电池供电类产品
USB 电源
此器件采用 3mm x 3mm x 0.9mm VSON 封装。
平板电脑
移动电源、备用电池
工业仪表计量设备
器件信息(1)
部件号
TPS61230
封装
封装尺寸（标称值）
超薄小外形尺寸无引
线 (VSON) (10)
TPS61231(2)
3.00mm x 3.00mm
TPS61232
(1) 如需了解所有可用封装，请见数据表末尾的可订购产品附录。
(2) 产品预览。 有关更多信息，请联系 TI 厂家
TPS61230 典型应用
TPS61230 典型应用效率
L1
1.0µH
100
90
80
VIN
VIN
EN
SW
VOUT
FB
C1
22µF
VOUT
C2
3x22µF
R1
402k
HYS
SS
R2
100k
70
C3
10nF
Vin = 3.0 V
GND
PG
Vin = 3.6 V
Vin = 4.2 V
Vout = 5.0 V
R3
1.0Meg
60
TPS61230
0.001
0.010
0.100
Iout (A)
1.000
C008
1
UNLESS OTHERWISE NOTED this document contains PRODUCTION DATA information current as of publication date. Products
conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include
testing of all parameters.
English Data Sheet: SLVSAQ2
TPS61230, TPS61231, TPS61232
ZHCS174C –JANUARY 2014–REVISED OCTOBER 2014
www.ti.com.cn
目录
8.4 Device Functional Modes........................................ 11
Applications and Implementation ...................... 12
9.1 Application Information............................................ 12
9.2 Typical Applications ................................................ 12
1
2
3
4
5
6
7
特性.......................................................................... 1
应用范围................................................................... 1
说明.......................................................................... 1
修订历史记录 ........................................................... 2
Device Comparison Table..................................... 3
Pin Configuration and Functions......................... 3
Specifications......................................................... 4
7.1 Absolute Maximum Ratings ...................................... 4
7.2 Handling Ratings....................................................... 4
7.3 Recommended Operating Conditions....................... 4
7.4 Thermal Information.................................................. 4
7.5 Electrical Characteristics........................................... 5
7.6 Typical Characteristics.............................................. 6
Detailed Description .............................................. 8
8.1 Overview ................................................................... 8
8.2 Functional Block Diagram ......................................... 8
8.3 Feature Description................................................... 8
9
10 Power Supply Recommendations ..................... 20
11 Layout................................................................... 21
11.1 Layout Guidelines ................................................. 21
11.2 Layout Example .................................................... 21
11.3 Thermal Considerations........................................ 21
12 器件和文档支持 ..................................................... 23
12.1 器件支持................................................................ 23
12.2 文档支持 ............................................................... 23
12.3 相关链接................................................................ 23
12.4 商标....................................................................... 23
12.5 静电放电警告......................................................... 23
12.6 术语表 ................................................................... 23
13 机械封装和可订购信息 .......................................... 23
8
4 修订历史记录
Changes from Revision B (June 2014) to Revision C
Page
•
已更改 Electrical Characteristics in the IQ row; VOUT = 3.5 V to VOUT = No Supply ............................................................... 5
Changes from Revision A (March 2014) to Revision B
Page
•
•
•
•
已将 TPS61232 添加到数据表................................................................................................................................................ 1
已更改器件信息 ...................................................................................................................................................................... 1
Changed the Device Comparison Table................................................................................................................................. 3
Changed the Handling Ratings table ..................................................................................................................................... 4
Changes from Original (September 2013) to Revision A
Page
•
•
•
•
•
•
已从数据表中删除 TPS61232 ................................................................................................................................................ 1
已将数据表更改为全新的 TI 格式............................................................................................................................................ 1
已将说明从：输入流耗减少至 0.5µA（典型值）更改为：输入流耗减少至 1.5µA（典型值） ................................................ 1
Changed the Functional Block Diagram. Removed Note 2 ................................................................................................... 8
Deleted the Programming The Output Voltage section ....................................................................................................... 13
Changed 图 14 label From: Startup (A) To: Startup (Ω)....................................................................................................... 15
2
Copyright © 2014, Texas Instruments Incorporated
TPS61230, TPS61231, TPS61232
www.ti.com.cn
ZHCS174C –JANUARY 2014–REVISED OCTOBER 2014
5 Device Comparison Table
PART NUMBER
TPS61230DRC
TPS61231DRC(1)
TPS61232DRC
OUTPUT VOLTAGE
Adjustable
OUTPUT DISCHARGE
No
Yes
No
Adjustable
5-V fixed output
(1) Preview product. Contact TI factory for more information
6 Pin Configuration and Functions
11-PIN VSON
DRC PACKAGE
(Top View)
SW
VIN
EN
1
10
9
SW
2
VOUT
HYS
FB
3
8
GND
11
VOUT
4
7
PG
SS
5
6
Pin Functions
PIN
I/O
DESCRIPTION
NAME
SW
NUMBER
1,2
3,4
5
PWR The switch pin of the converter. It is connected to the drain of the internal Power MOSFETs.
PWR Boost converter output pin.
VOUT
PG
OUT Power Good open drain output. Can be left floating if not used.
SS
6
IN
IN
Soft startup pin. A soft startup capacitor connects to this pin to set the soft start time.
FB
7
Voltage feedback of adjustable versions. Must be connected to VOUT on fixed output voltage version.
HYS
EN
8
OUT EN hysteresis program pin. See the application section for details. Can be left floating if not used.
9
IN
Enable logic input. Logic HIGH enables the device. Logic LOW disables the device and turns it into
shutdown mode. This pin must be terminated.
VIN
10
11
IN
Supply voltage pin.
GND
PWR Ground pin.
Copyright © 2014, Texas Instruments Incorporated
3
TPS61230, TPS61231, TPS61232
ZHCS174C –JANUARY 2014–REVISED OCTOBER 2014
www.ti.com.cn
7 Specifications
7.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)(1)
MIN
–0.3
–40
MAX
UNIT
V
Voltage range at pins(2)
EN, FB, PG, SS, HYS, VIN, VOUT, SW
7
Operating junction temperature range, TJ
150
°C
(1) Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating
conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods my affect device reliability.
(2) All voltages are with respect to network ground pin.
7.2 Handling Ratings
MIN
-65
–2
MAX
150
2
UNIT
°C
Tstg
Storage temperature range
Human body model (HBM), per ANSI/ESDA/JEDEC JS-001, all pins(1)
kV
Electrostatic
discharge
VESD
Charged device model (CDM), per JEDEC specification JESD22-C101, all
pins(2)
V
–500
500
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
7.3 Recommended Operating Conditions
MIN
TYP
MAX
UNIT
VIN
Supply voltage at VIN pin
Sink current at PG pin
2.3
5.5
500
5.5
V
µA
V
ISINK_PG
VPG
TJ
Pull-up resistor voltage
Operating junction temperature
-40
125
°C
7.4 Thermal Information
TPS6123x
THERMAL METRIC(1)
UNIT
DRC (11 PINS)
RθJA
Junction-to-ambient thermal resistance
Junction-to-case(top) thermal resistance
49.1
57.2
26.6
0.8
RθJC(top)
RθJB
Junction-to-board thermal resistance
°C/W
ψJT
Junction-to-top characterization parameter
Junction-to-board characterization parameter
Junction-to-case(bottom) thermal resistance
ψJB
23.8
4.5
RθJC(bottom)
(1) For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.
4
版权 © 2014, Texas Instruments Incorporated
TPS61230, TPS61231, TPS61232
www.ti.com.cn
ZHCS174C –JANUARY 2014–REVISED OCTOBER 2014
7.5 Electrical Characteristics
TJ = –40°C to 125°C and VIN = 3.6 V. Typical values are at TJ = 25°C, unless otherwise noted.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
SUPPLY
VIN falling
VIN rising
2.0
2.1
2.1
2.2
VUVLO
Input under voltage lockout
V
IC enabled, No load, No switching
VOUT = 5 V, TJ = –40 °C to 85°C
35
200
1.5
60
IQ
Quiescent current into VIN
µA
IC enabled, No load
VIN = 4.2 V, VOUT = No supply, TJ = –40 °C to
85°C
230
0 V ≤ VEN ≤ 0.4 V, VIN = 2.3 V to 5.5 V, TJ = -40
°C to 85°C
ISD
Shutdown current into VIN
6
µA
µA
Leakage current from SW to VOUT
VEN = 0 V, VOUT = 0 V; VSW = VIN = 3.6 V
2.5
OUTPUT
VOUT
Output voltage range
2.5
4.9
5.5
5.1
V
V
V
VOUT
Output voltage accuracy, TPS61232
Output voltage accuracy, TPS61232
PWM mode
PFM mode(1)
PWM mode
PFM mode(1)
VFB = 1 V
5.0
5.035
1
VOUT
0.985
1.015
100
Feedback voltage, TPS61230 and
TPS61231
VFB
V
1.007
FB pin leakage current
nA
Output discharge resistor
TPS61231
RDIS
VOUT = 5 V
200
Ω
Over voltage protection DC threshold
Over voltage protection hysteresis
Bias current in soft start phase
Line regulation
VOUT rising
5.7
6
6.2
VOVP
ISS
V
VOUT falling below VOVP
After pre-charge phase
IOUT = 1 A, VIN = 2.3 V to 4.5 V
IOUT = 0.5 A to 2 A
0.15
5
µA
0.06
0.15
%/V
%/A
Load regulation
LOGIC INTERFACE
VTH_EN_ON EN pin threshold rising
VIN = 2.3 V to 5.5 V
VIN = 2.3 V to 5.5 V
1.15
1.11
1.19
1.14
1.23
1.18
V
V
VTH_EN_OF
EN pin threshold falling
F
VOL_HYS
VTH_PG
VOL_PG
HYS pin low level voltage
Power good DC threshold
PG pin low level voltage
ISINK_HYS = 1 mA, VEN = 1.1 V
VOUT rising, referenced to VOUT_NOMINAL
VOUT falling referenced to VOUT_NOMINAL
ISINK_PG = 500 µA
0.7
99%
93%
0.4
V
93%
87%
95%
90%
V
A
A
POWER STAGE
ILIM_SW Switch valley current limit
4.0
2.0
1.8
0.4
5.0
2.8
2.6
0.55
50
6.0
3.5
3.3
0.7
75
VOUT = 5 V
ILIM_Pre
Precharge current limit
VOUT = 3.5 V
VOUT = 0 V
High side MOSFET on resistance
Low side MOSFET on resistance
Thermal shutdown threshold
Thermal shutdown hysteresis
VOUT = 5 V
RDS(on)
mΩ
VOUT = 5 V
50
75
TJ rising
150
20
TJSD
°C
TJ falling below TJSD
(1) L = 1 µH, COUT = 20 µF (effective capacitance value)
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TPS61230, TPS61231, TPS61232
ZHCS174C –JANUARY 2014–REVISED OCTOBER 2014
www.ti.com.cn
7.6 Typical Characteristics
VIN = 3.6 V, VOUT = 5.0 V, TJ = -40°C to 125 °C, unless otherwise noted.
70
60
50
40
30
70
60
50
40
30
-40
-20
0
20
40
60
80
100
120
-40
-20
0
20
40
60
80
100
120
C001
C002
Junction Temperature (C)
Junction Temperature (C)
图 1. High-Side MOSFET On Resistance vs Junction
图 2. Low-Side MOSFET On Resistance vs Junction
Temperature
Temperature
1.010
2.20
1.005
1.000
0.995
0.990
2.00
1.80
VIN Rising
V
Falling
IN
-40
-20
0
20
40
60
80
100
120
±40
±20
0
20
40
60
80
100
120
C003
Junction Temperature (C)
Junction Temperature (oC)
C013
图 3. Voltage Reference vs Junction Temperature
图 4. Vin UVLO Threshold vs Junction Temperature
1.30
1.20
1.10
50
40
30
20
o
Tj = 85 C
EN Rising
EN Falling
o
Tj = 25 C
Tj = -40oC
±40
±20
0
20
40
60
80
100
120
2
3
4
5
Junction Temperature (oC)
Input Voltage (V)
C014
C010
图 5. EN Logic Threshold vs Junction Temperature
图 6. Quiescent Current vs Input Voltage (Boost Mode)
6
版权 © 2014, Texas Instruments Incorporated
TPS61230, TPS61231, TPS61232
www.ti.com.cn
ZHCS174C –JANUARY 2014–REVISED OCTOBER 2014
Typical Characteristics (接下页)
VIN = 3.6 V, VOUT = 5.0 V, TJ = -40°C to 125 °C, unless otherwise noted.
4
3
2
1
0
5.0
4.8
4.6
4.4
4.2
4.0
o
Tj = 85 C
o
Tj = 125 C
o
o
Tj = 25 C
Tj = 25 C
Tj = -40oC
Tj = -40oC
2
3
4
5
2
3
4
5
Input Voltage (V)
Input Voltage (V)
C011
C012
图 7. Shutdown Current vs Input Voltage (Boost Mode)
图 8. Switch Valley Current Limit vs Input Voltage (Boost
Mode)
5.1
5.0
4.9
4.8
4.7
4.6
4.5
±40
±20
0
20
40
60
80
100
120
Junction Temperature (oC)
C015
图 9. Soft Start Charge Current vs Junction Temperature
版权 © 2014, Texas Instruments Incorporated
7
TPS61230, TPS61231, TPS61232
ZHCS174C –JANUARY 2014–REVISED OCTOBER 2014
www.ti.com.cn
8 Detailed Description
8.1 Overview
The TPS6123x synchronous step-up converter typically operates at a quasi-constant 2-MHz frequency pulse
width modulation (PWM) at moderate to heavy load currents. At light load currents, the TPS6123x converter
operates in power-save mode with pulse frequency modulation (PFM). The converter uses a novel quasi-
constant on-time valley current mode control scheme which provides excellent transient line / load response with
minimal output capacitance. Internal loop compensation simplifies the design process while minimizing the
number of external components. The TPS6123x device can smoothly transit in and out of zero duty cycle mode
(high side FET full on). Therefore the output can be kept as close as possible to its regulation limits even though
the converter is subject to an input voltage that tends to be excessive.
8.2 Functional Block Diagram
SW
VIN
Supply for
logic circuitry
61230/1
VOUT
Over Voltage
Protection
FB
EA
VOUT
61232
2)
REF
VOUT
Valley
Current
Sense
Pulse
Modulator
Gate
Driver
1)
EN
Thermal
Shutdown
EN
Threshold/
Hysteresis
ON/
OFF
OVP
PG
PG Comparator
EN
FB
REF
REF
Logic
HYS
EN Comparator
Undervoltage
Lockout
Softstart
SS
GND
(1) Output discharge block is implemented in TPS61231 only.
(2) Internal resistor divider is implemented in TPS61232 only. For adjustable output versions, the FB pin is directly
connected to the negative pin of the EA.
8.3 Feature Description
8.3.1 Startup
In boost mode (PWM or PFM), the rectifying switch is turned on first until the output capacitor is charged to 0.5 V
with the current limit of 550 mA after the device is enabled. Then, the output capacitor is continuously charged to
a value close to the input voltage. This is called the pre-charge phase. During the pre-charge phase, the output
current is limited by the pre-charge current limit of the high side rectifying switch and the SS pin voltage follows
the FB voltage (in the TPS61232, the SS pin follows the internal FB voltage). Once the output capacitor has
been biased to the input voltage, the device starts switching. This is called the soft start phase. During the soft
8
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TPS61230, TPS61231, TPS61232
www.ti.com.cn
ZHCS174C –JANUARY 2014–REVISED OCTOBER 2014
Feature Description (接下页)
start phase, the SS pin voltage limits the FB pin voltage, and the output voltage rising slope follows the SS pin
voltage slope. The capacitor connected to the SS pin is charged by the internal bias current of ISS, giving the time
of the soft start phase shown in 公式 1. The larger the soft start capacitor, the longer the soft start phase time.
Leaving the SS pin floating sets the minimum soft startup phase time. The device finishes the soft start phase
and operates normally when the nominal output voltage is reached.
æ
ç
è
ö
C SS
VIN
ç
÷
÷
tSS
=
´ 1 -
´ VR EF
5mA
VO U T
ø
(1)
The SS pin voltage is discharged in the cases when the device gets disabled by the EN pin, thermal shutdown
and undervoltage lockout. The SS pin may be left floating to disable the soft start phase and start up with the
fastest time. In zero duty cycle mode, only the pre-charge phase works during startup.
8.3.2 Current Limit Operation
The device employs a valley current sensing scheme. Switch valley current limit detection occurs during the off
time through sensing of the voltage drop across the synchronous rectifier. If the current is above the valley
current limit level when it is time to turn off the synchronous rectifier, the device instead keeps the synchronous
rectifier on until its current decreases below the valley current limit level. The maximum continuous output current
IOUT(MAX), before entering switch valley current limit operation, is defined by 公式 2.
1
2
æ
ö
÷
ø
IOUT(MAX) = (1- D)´ I
ç LIM_ SW
+
DIL
è
VOUT - V
IN
D =
VOUT
V
D
IN
DIL =
´
L
fSW
(2)
Where
ILIM_SW = Switch valley current limit
L = Inductor value
fSW = Switching frequency
When the switch current limit is reached, the output voltage decreases from further load increase. The switch
valley current limit works in PWM, PFM and Zero Duty Cycle Mode operations.
Another current limit scheme, pre-charge current limit, ILIM_Pre is implemented. Pre-charge current limit detection
works when VOUT < VOUT_NOM and VOUT < VIN . It can happen when the device is in the pre-charge phase or an
over load condition. It impacts the minimum load resistance at startup as shown in 图 14 and 图 27.
8.3.3 Enable/Disable
The EN pin is connected to an ON/OFF detector (ON/OFF) and an input of the Enable Comparator, shown in the
functional block diagram. With a voltage level of 0.4 V or less at the EN pin, the ON/OFF detector turns the
device into Shutdown mode and the quiescent current is reduced to typically 1.5 uA. In this mode, the EN
comparator and the entire internal control circuitry are switched off. A voltage level of typically 0.9 V at the EN
pin triggers the ON/OFF detector and activates the internal reference, the EN comparator and the UVLO
comparator. Once the ON/OFF detector has tripped, the quiescent current into the VIN pin is typically 1.5 μA.
The TPS6123x starts regulation once the voltage at the EN pin trips the threshold VEN_TH_ON and the VIN pin
voltage is above the UVLO threshold. The device enters startup and ramps up the output voltage. The TPS6123x
stops regulation once the voltage on the EN pin falls blow the threshold VEN_TH_OFF or the VIN pin voltage falls
below the UVLO threshold. For proper operation, The EN pin must be terminated and must not be left floating.
An external logic signal applied directly to the EN pin can enable/disable the device. The device can be driven
into shutdown mode by pulling the EN pin to GND. In this mode, true load disconnect between the battery and
load prevents current flow from VIN to VOUT, as well as reverse flow from VOUT to VIN.
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TPS61230, TPS61231, TPS61232
ZHCS174C –JANUARY 2014–REVISED OCTOBER 2014
www.ti.com.cn
Feature Description (接下页)
8.3.4 Undervoltage Lockout
An under voltage lockout is implemented to avoid mis-operation of the device at low input voltages. It shuts down
the device with voltages lower than VUVLO
.
Use the HYS pin to configure a new undervoltage lockout threshold and hysteresis shown in 图 10 and 公式 3.
The new thresholds must be higher than VUVLO; otherwise it does not work. The devices holds the HYS pin low
until the EN voltage rises above VEN_TH_ON. Then, the HYS pin goes high impedance.
VIN
EN
Threshold/
Hysteresis
ON/
OFF
REN1
EN
REF
REN2
REN3
EN Comparator
HYS
图 10. EN Comparator threshold and hysteresis setting
REN1
REN1
æ
ö
÷
ø
æ
ö
÷
ø
V
= VTH_EN_OFF ´ 1+
= 1.14V ´ 1+
ç
ç
IN_OFF
REN2 + REN3
REN2 + REN3
è
è
REN1
REN1
REN2
æ
ö
÷
ø
æ
ö
÷
ø
V
= VTH_EN_ ON ´ 1+
= 1.19V ´ 1+
ç
ç
IN_ ON
REN2
è
è
(3)
8.3.5 Output Capacitor Discharge, TPS61231
To make sure the device starts up under defined conditions, the output capacitor of the TPS61231 gets
discharged by the VOUT pin with a typical discharge resistor of RDIS in the cases when the device gets disabled
by the EN pin, thermal shutdown, and undervoltage lockout.
8.3.6 Power Good Output
The PG output is low when the output voltage is below 90% of its nominal value. The PG pin becomes high
impedance once the output is higher than 95% of its nominal voltage. The PG pin is an open drain output and is
specified to sink up to 500 µA. This PG output requires a pull-up resistor that cannot be connected to any voltage
higher than 5.5 V. PG is held low when the device is disabled by the EN pin and thermal shutdown.
8.3.7 Over Voltage Protection
The device stops switching as soon as the output voltage exceeds VOVP. When the output voltage falls 0.15V
below the OVP threshold, the device resumes normal operation until the output voltage exceeds the OVP
threshold again.
8.3.8 Thermal Shutdown
The device goes into thermal shutdown and stops switching once the junction temperature exceeds TJSD. Once
the junction temperature falls below the threshold, it returns to normal operation automatically.
10
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8.4 Device Functional Modes
The TPS6123x boost converter family has three operation modes, as shown in 表 1.
表 1. Operation Mode Description
MODE
PWM
PFM
DESCRIPTION
CONDITION
Boost in normal switching operation VIN < VOUT + 0.2 V, heavy load
Boost in power save operation
Zero duty cycle operation
VIN < VOUT + 0.2 V, light load
VOUT < VIN ≤ VOUT + 0.24 V and VOUT
≥
Zero Duty Cycle
VOUT_NOM
8.4.1 Boost Normal Mode
The TPS6123x boost converter family typically operates at a quasi-constant 2-MHz frequency pulse width
modulation (PWM) at moderate to heavy load currents. Based on the VIN/VOUT ratio, a simple circuit predicts the
required on-time. At the beginning of the switching cycle, the low-side N-MOS switch, shown in the functional
block diagram, is turned on and the inductor current ramps up to a peak current that is defined by the on-time
and the inductance. In the second phase, once this peak current is reached, the current comparator trips, the on-
timer is reset turning off the low-side N-MOS switch and turning on the high-side rectifying switch. The current
through the inductor then decays to an internally set valley current. Once this occurs, the on-timer is set to turn
the boost switch back on again and the cycle is repeated.
8.4.2 Boost Power Save Mode
The device integrates a power save mode with pulse frequency modulation (PFM) to improve efficiency at light
load. In power save mode, the device only switches when the output voltage trips below a set threshold voltage.
It ramps up the output with several pulses and enters the power save mode when the output voltage exceeds the
set threshold voltage. PFM is left and PWM mode entered when the inductor current becomes discontinuous.
The DC output voltage in PFM mode rises above the nominal output voltage in PWM mode by 0.7%.
Output Voltage
PFM mode at light load
VOUT_DC = 1.007 x VOUT_NOM
VOUT_NOM
PWM mode at heavy load
t
图 11. Output Voltage in PFM/PWM Mode
8.4.3 Zero Duty Cycle Mode
When the input voltage is lower than VOUT + 0.24 V and VOUT is higher than the nominal output voltage, the
device automatically changes to a Zero Duty Cycle Mode. In Zero Duty Cycle Mode, the rectifying switch is
constantly turned on and the low side switch is turned off. The output voltage in this mode depends on the
resistance between the input and the output, calculated as:
VOUT = VIN -IOUT ´(RDS(on) + RL )
(4)
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9 Applications and Implementation
注
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
9.1 Application Information
The devices are designed to operate from an input voltage supply range between 2.3 V and 5.5 V with a
maximum output current of 2.1 A. The devices operate in PWM mode for medium to heavy load conditions and in
power save mode at light load currents. In PWM mode the TPS6123x converter operates with the nominal
switching frequency of 2 MHz which provides a controlled frequency variation over the input voltage range. As
the load current decreases, the converter enters power save mode, reducing the switching frequency and
minimizing the IC quiescent current to achieve high efficiency over the entire load current range. The WEBENCH
software uses an iterative design procedure and accesses a comprehensive database of components when
generating a design. See the 相关文档ꢀ section for additional documentation.
9.2 Typical Applications
9.2.1 TPS61230 2.3-V to 5.5-V Input, 5-V Output Converter
L1
1.0µH
VIN
VIN
EN
SW
VOUT
FB
C1
22µF
VOUT
C2
3x22µF
R1
402k
HYS
SS
R2
100k
C3
10nF
GND
PG
R3
1.0Meg
TPS61230
图 12. TPS61230 5-V Output Typical Application
9.2.1.1 TPS61230 5-V Output Design Requirements
Use the following typical application design procedure to select external components values for the TPS61230
device.
表 2. TPS61230 5-V Output Design Parameters
DESIGN PARAMETERS
Input Voltage Range
Output Voltage
EXAMPLE VALUES
2.3 V to 5.5 V
5.0 V
Output Voltage Ripple
Transient Response
Input Voltage Ripple
Output Current Rating
Operating Frequency
±3% VOUT
±10% VOUT
±200 mV
2.1 A
2 MHz
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9.2.1.2 TPS61230 5-V Detailed Design Procedure
表 3. TPS61230 5-V Output List of Components
REFERENCE
DESCRIPTION
MANUFACTURER
Coilcraft
Murata
L1
C1
C2
C3
R1
R2
1.0 μH, power inductor, XFL4020-102MEB
2 μF 6.3 V, 0805, X5R ceramic, GRM21BR60J226ME39
3 × 22 μF 10 V, 0805, X5R ceramic, LMK212BBJ226MG
10 nF, X7R ceramic
YUDEN
Murata
402 k, resistor, chip, 1/10W, 1%
Rohm
100 k, resistor, chip, 1/10W, 1%
Rohm
9.2.1.2.1 Programming the Output Voltage
The TPS6123x device family's output voltage need to be programmed via an external voltage divider to set the
desired output voltage.
An external resistor divider is used, as shown in 公式 5. By selecting R1 and R2, the output voltage is
programmed to the desired value. When the output voltage is regulated, the typical voltage at the FB pin is VFB
.
The following equation can be used to calculate R1 and R2.
R1
R2
R1
R2
æ
ö
÷
ø
æ
ö
÷
ø
VOUT = VFB ´ 1+
= 1V ´ 1+
ç
ç
è
è
(5)
For best accuracy, R2 should be kept smaller than 100 kΩ to ensure that the current following through R2 is at
least 100 times larger than FB pin leakage current. Changing R2 towards a lower value increases the robustness
against noise injection. Changing the R2 towards higher values reduces the quiescent current for achieving
highest efficiency at low load currents.
For the fixed output voltage version, TPS61232, the FB pin must be tied to the output directly.
9.2.1.2.2 Inductor and Capacitor Selection
The second step is the selection of the inductor and capacitor components. To simplify this process, 表 4 outlines
possible inductor and output capacitor value combinations.
表 4. Inductor and Output Capacitor Combinations
COUT (µF)(2)
L (µH)(1)
10
20
47
√
100
√
0.47
1.0
√
(3)
√
√
√
1.5
(1) This is the nominal inductance of inductor. Inductor tolerance and current de-rating is anticipated. The
effective inductance can vary by -30%.
(2) This is the effective capacitance of output capacitors. A higher nominal value is required.
(3) Typical application configuration. Other check mark indicates alternative filter combinations.
9.2.1.2.2.1 Inductor Selection
A boost converter requires two main passive components for storing energy during the conversion, an inductor
and an output capacitor. It is advisable to select an inductor with a saturation current rating higher than the
possible peak current flowing through the power switches. The inductor peak current varies as a function of the
load, the input and output voltages and is estimated using 公式 6.
IOUT
V
´D
1
IN
IL(PEAK)
=
+
´
(1- D)´ h
2
L ´ fSW
(6)
Where
η = Power conversion estimated efficiency
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Selecting an inductor with insufficient saturation performance can lead to excessive peak current in the
converter. This could eventually harm the device and reduce reliability. It's recommended to choose the
saturation current for the inductor 20%~30% higher than the IL(PEAK), from 公式 6. The following inductors are
recommended to be used in designs.
表 5. List of Inductors
INDUCTANCE
[µH]
CURRENT
RATING [A]
DC RESISTANCE
PART NUMBER
MANUFACTURER
[mΩ]
1.0
1.0
5.4
7.5
6.6
10.8
9
XFL4020-102ME
LQH6PPN1R0
Coilcraft
muRata
Coilcraft
0.47
7.6
XFL4015-471ME
9.2.1.2.2.2 Output Capacitor Selection
For the output capacitor, it is recommended to use small X5R or X7R ceramic capacitors placed as close as
possible to the VOUT and GND pins of the IC. If, for any reason, the application requires the use of large
capacitors which cannot be placed close to the IC, using a smaller ceramic capacitor of 1 µF in parallel to the
large one is highly recommended. This small capacitor should be placed as close as possible to the VOUT and
GND pins of the IC.
Care must be taken when evaluating a capacitor’s derating under bias. The bias can significantly reduce
capacitance. Ceramic capacitors can loss as much as 50% of their capacitance at rated voltage. Therefore, leave
margin on the voltage rating to ensure adequate effective capacitance.
The ESR impact on the output ripple must be considered as well, if tantalum or electrolytic capacitors are used.
Assuming there is enough capacitance such that the ripple due to the capacitance can be ignored, the ESR
needed to limit the VRipple is:
VRipple(ESR) = IL(PEAK) ´ESR
(7)
9.2.1.2.2.3 Input Capacitor Selection
Multilayer X5R or X7R ceramic capacitors are an excellent choice for input decoupling of the step-up converter
as they have extremely low ESR and are available in small footprints. Input capacitors should be located as
close as possible to the device. While a 22-μF input capacitor is sufficient for most applications, larger values
may be used to reduce input current ripple without limitations. Take care when using only ceramic input
capacitors. When a ceramic capacitor is used at the input and the power is being supplied through long wires,
such as from a wall adapter, a load step at the output can induce ringing at the VIN pin. This ringing can couple
to the output and be mistaken as loop instability or could even damage the part. Additional "bulk" capacitance
(electrolytic or tantalum) should in this circumstance be placed between CIN and the power source to reduce
ringing than can occur between the inductance of the power source leads and CIN.
9.2.1.2.3 Loop Stability, Feed Forward Capacitor
The third step is to check the loop stability. The stability evaluation is to look from a steady-state perspective at
the following signals:
•
•
•
Switching node, SW
Inductor current, IL
Output ripple, VRipple(OUT)
When the switching waveform shows large duty cycle jitter or the output voltage or inductor current shows
oscillations, the regulation loop may be unstable. This is often a result of board layout and/or L-C combination.
The load transient response is another approach to check the loop stability. During the load transient recovery
time, VOUT can be monitored for settling time, overshoot or ringing that helps judge the converter’s stability.
Without any ringing, the loop has usually more than 45° of phase margin.
As for the heavy load transient applications such as a 2 A load step transient, a feed forward capacitor in parallel
with R1 is recommended. The feed forward capacitor increases the loop bandwidth by adding a zero. This results
in a lower output voltage drop, as shown in 图 36. Set the feed forward capacitor zero near 20 kHz for most
applications. See application report Optimizing Transient Response of Internally Compensated dc-dc Converters
With Feedforward Capacitor (SLVA289).
14
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9.2.1.3 TPS61230 5-V Output Application Performance Plots
4.0
3.0
2.0
1.0
0.0
6.0
5.0
4.0
3.0
2.0
1.0
Vout = 5 V
Vout = 5 V
TA = -40 °C
TA = 25 °C
TA = 85 °C
TA = -40 C
TA = 25 C
TA = 85 C
2.3
2.8
3.3
3.8
4.3
4.8
5.3
2.3
2.8
3.3
3.8
4.3
4.8
5.3
C004
C006
Vin (V)
Vin (V)
图 13. Maximum Load Current after Startup
图 14. Minimum Resistance at Startup
100
90
5.20
5.10
5.00
4.90
4.80
80
70
TA = -40 °C
Vin = 3.0 V
Vin = 3.6 V
Vin = 4.2 V
TA = 25 °C
TA = 85 °C
Vout = 5 V, Vin = 3.6 V
0.010
Vout = 5.0 V
60
0.001
0.010
0.100
Iout (A)
1.000
0.001
0.100
Iout (A)
1.000
C008
C0011
图 15. Efficiency
图 16. Load Regulation
5.20
10,000K
Vout = 5.0 V
5.10
5.00
4.90
4.80
1,000K
100K
10K
TA = -40 °C
TA = 25 °C
TA = 85 °C
Vin = 2.3 V
Vin = 3.6 V
Vin = 4.2 V
Vout = 5 V, Iout = 1 A
2.8
1K
0.001
2.3
3.3
3.8
4.3
4.8
0.010
0.100
Iout (A)
1.000
C0013
C0015
Vin (V)
图 17. Line Regulation
图 18. Switching Frequency
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t -- 300 ns/div
t -- 10 µs/div
Vout (AC, 50 mV/div)
Vout (AC, 50 mV/div)
Icoil (DC, 1 A/div)
SW (DC, 5 V/div)
Icoil (DC, 1 A/div)
SW (DC, 5 V/div)
图 19. PWM Operation (VOUT = 5 V, IOUT = 2 A)
图 20. PFM Operation (VOUT = 5 V, IOUT = 50 mA)
t -- 50 µs/div
t -- 10 µs/div
Vout (DC, 1 V/div)
Load (DC, 2 A/div)
PG (DC, 5 V/div)
PG (LOW, 0 V)
SW (DC, 5 V/div)
Vout (AC, 0.5 V/div)
Icoil (DC, 5 A/div)
Icoil (DC, 5 A/div)
图 21. Load Transient (VOUT = 5 V, IOUT = 0.5 A to 2 A)
图 22. Output Over Voltage Protection (FB = 0 V, ROUT = 30
Ω)
t -- 300 µs/div
t -- 100 µs/div
EN (DC, 5 V/div)
EN (DC, 5 V/div)
PG (DC, 5 V/div)
PG (DC, 5 V/div)
Vout (DC, 2 V/div)
Icoil (DC, 2 A/div)
Vout (DC, 2 V/div)
Icoil (DC, 2 A/div)
图 23. Startup (VOUT = 5 V, ROUT = 2.5 Ω)
图 24. Shutdown (VOUT = 5 V, ROUT = 2.5 Ω)
16
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9.2.2 TPS61230 2.3-V to 5.5-V Input, 3.5-V Output Converter
L1
1.0µH
VIN
VIN
EN
SW
VOUT
FB
C1
22µF
VOUT
C2
3x22µF
R1
250k
HYS
SS
R2
100k
C3
10nF
GND
PG
R3
1.0Meg
TPS61230
图 25. TPS61230 3.5-V Output Typical Application
9.2.2.1 TPS61230 3.5-V Output Design Requirements
表 6. TPS61230 3.5-V Output Design Parameters
DESIGN PARAMETERS
Input Voltage Range
Output Voltage
EXAMPLE VALUES
2.3 V to 5.5 V
3.5 V
Output Voltage Ripple
Transient Response
Input Voltage Ripple
Output Current Rating
Operating Frequency
±3% VOUT
±10% VOUT
±200 mV
2.1 A
2 MHz
9.2.2.2 Detailed Design Procedure
Refer to the TPS61230 5-V Detailed Design Procedure section for the 3.5-V detailed design procedures.
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9.2.2.3 TPS61230 3.5-V Output Application Performance Plots
5.0
4.0
3.0
2.0
1.0
3.0
2.5
2.0
1.5
1.0
Vout = 3.5 V
Vout = 3.5 V
TA = -40 °C
TA = 25 °C
TA = 85 °C
TA = -40 °C
TA = 25 °C
TA = 85 °C
2.3
2.8
3.3
3.8
4.3
2.3
2.5
2.7
2.9
3.1
3.3
3.5
C003
C005
Vin (V)
Vin (V)
图 26. Maximum Load Current after Startup
图 27. Minimum Resistance at Startup
100
90
3.64
3.57
3.50
3.43
3.36
80
70
Vin = 2.5 V
TA = -40 °C
Vin = 3.0 V
Vin = 3.3 V
TA = 25 °C
TA = 85 °C
Vout = 3.5 V, Vin = 3.0 V
0.010
Vout = 3.5 V
60
0.001
0.010
0.100
Iout (A)
1.000
0.001
0.100
Iout (A)
1.000
C007
C0010
图 28. Efficiency
图 29. Load Regulation
3.64
10,000K
Vout = 3.5 V
3.57
3.50
3.43
3.36
1,000K
100K
10K
TA = -40 °C
TA = 25 °C
TA = 85 °C
Vin = 2.3 V
Vin = 2.7 V
Vin = 3.0 V
Vout = 3.5 V, Iout = 1 A
2.5
1K
0.001
2.3
2.7
2.9
3.1
3.3
0.010
0.100
Iout (A)
1.000
C0012
C0014
Vin (V)
图 30. Line Regulation
图 31. Switching Frequency
18
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t -- 2 ms/div
t -- 200 µs/div
PG (DC, 2 V/div)
EN (DC, 5 V/div)
PG (DC, 5 V/div)
Vin (DC, 1 V/div)
Vout (DC, 1 V/div)
Icoil (DC, 1.5 A/div)
Vout (DC, 2 V/div)
Icoil (DC, 1 A/div)
图 32. Input Sweep (VOUT = 3.5 V, VIN = 2.7 V to 4.2 V, IOUT
=
图 33. Startup (VOUT = 3.5 V, VIN = 3.0 V, ROUT = 2.3 Ω)
1.5 A)
t -- 75 µs/div
EN (DC, 5 V/div)
PG (DC, 5 V/div)
Vout (DC, 2 V/div)
Icoil (DC, 1 A/div)
图 34. Shutdown (VOUT = 3.5 V, VIN = 3.0 V, ROUT = 2.3 Ω)
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9.2.3 TPS61230 Application with Feed Forward Capacitor for Best Transient Response
As for the heavy load transient applications such as a 2-A load step transient, a feed forward capacitor in parallel
with R1 is recommended. The feed forward capacitor increases the loop bandwidth by adding a zero. This results
in a lower output voltage drop, as shown in 图 36. Set the feed forward capacitor zero near 20 kHz for most
applications. See application report Optimizing Transient Response of Internally Compensated dc-dc Converters
With Feedforward Capacitor (SLVA289).
L1
1.0µH
VIN
VIN
EN
SW
VOUT
FB
C1
22µF
VOUT
C2
3x22µF
R1
402k
C4
18pF
HYS
SS
R2
100k
C3
10nF
GND
PG
R3
1.0Meg
TPS61230
图 35. TPS61230 5-V Output with Cff Typical Application
9.2.3.1 Design Requirements
Refer to the TPS61230 5-V Output Design Requirements section for the design requirements.
9.2.3.2 Detailed Design Procedure
Refer to the TPS61230 5-V Detailed Design Procedure section for the detailed design procedures.
9.2.3.3 Application Curve
t -- 50 µs/div
Load (DC, 2 A/div)
PG (DC, 5 V/div)
Vout (AC, 0.5 V/div)
Icoil (DC, 5 A/div)
图 36. Load Transient (VOUT = 5 V, IOUT = 0.5 A to 2 A, CFF = 18 pF)
10 Power Supply Recommendations
The device is designed to operate from an input voltage supply range between 2.3 V and 5.5 V. This input supply
must be well regulated. If the input supply is located more than a few inches from the converter, additional bulk
capacitance may be required in addition to the ceramic bypass capacitors. An electrolytic or tantalum capacitor
with a value of 47 μF is a typical choice.
20
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ZHCS174C –JANUARY 2014–REVISED OCTOBER 2014
11 Layout
11.1 Layout Guidelines
For all switching power supplies, the layout is an important step in the design, especially at high peak currents
and high switching frequencies. If the layout is not carefully done, the regulator could show stability problems as
well as EMI problems. Therefore, use wide and short traces for the main current path and for the power ground
tracks. The input capacitor, output capacitor, and the inductor should be placed as close as possible to the IC.
Use a common ground node for power ground and a different one for control ground to minimize the effects of
ground noise. Connect these ground nodes at the GND pin of the IC. The most critical current path for all boost
converters is from the switching FET, through the synchronous FET, then the output capacitors, and back to
ground of the switching FET. Therefore, the output capacitors and their traces should be placed on the same
board layer as the IC and as close as possible between the IC’s VOUT and GND pin.
See 图 37 for the recommended layout.
11.2 Layout Example
Top Layer
Bottom Layer
R1
R2
GND
C3
GND
C1 1
VIN
C2
VOUT
L1
R3
图 37. Layout Recommendation
11.3 Thermal Considerations
Implementation of integrated circuits in low-profile and fine-pitch surface-mount packages typically requires
special attention to power dissipation. Many system-dependent issues such as thermal coupling, airflow, added
heat sinks and convection surfaces, and the presence of other heat-generating components affect the power-
dissipation limits of a given component.
Two basic approaches for enhancing thermal performance are listed below.
•
•
Improving the power dissipation capability of the PCB design
Introducing airflow in the system
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Thermal Considerations (接下页)
For more details on how to use the thermal parameters in the dissipation ratings table please check the
application report Thermal Characteristics of Linear and Logic Packages Using JEDEC PCB Designs (SZZA017)
and the application report Semiconductor and IC Package Thermal Metrics (SPRA953).
22
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12 器件和文档支持
12.1 器件支持
12.1.1 第三方产品免责声明
TI 发布的与第三方产品或服务有关的信息，不能构成与此类产品或服务或保修的适用性有关的认可，不能构成此类
产品或服务单独或与任何 TI 产品或服务一起的表示或认可。
12.2 文档支持
12.2.1 相关文档ꢀ
《采用前馈电容优化内部补偿 DC-DC 转换器的瞬态响应》SLVA289
《采用 JEDEC PCB 设计的线性和逻辑封装散热特性》(SZZA017)
《半导体和 IC 封装热指标》(SPRA953)
12.3 相关链接
以下表格列出了快速访问链接。 范围包括技术文档、支持与社区资源、工具和软件，并且可以快速访问样片或购买
链接。
表 7. 相关链接
部件
产品文件夹
请单击此处
请单击此处
请单击此处
样片与购买
请单击此处
请单击此处
请单击此处
技术文档
请单击此处
请单击此处
请单击此处
工具与软件
请单击此处
请单击此处
请单击此处
支持与社区
请单击此处
请单击此处
请单击此处
TPS61230
TPS61231
TPS61232
12.4 商标
All trademarks are the property of their respective owners.
12.5 静电放电警告
这些装置包含有限的内置 ESD 保护。 存储或装卸时，应将导线一起截短或将装置放置于导电泡棉中，以防止 MOS 门极遭受静电损
伤。
12.6 术语表
SLYZ022 — TI 术语表。
这份术语表列出并解释术语、首字母缩略词和定义。
13 机械封装和可订购信息
以下页中包括机械封装和可订购信息。 这些信息是针对指定器件可提供的最新数据。 这些数据会在无通知且不对
本文档进行修订的情况下发生改变。 欲获得该数据表的浏览器版本，请查阅左侧的导航栏。
版权 © 2014, Texas Instruments Incorporated
23
PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
TPS61230DRCR
TPS61230DRCT
TPS61232DRCR
TPS61232DRCT
ACTIVE
ACTIVE
ACTIVE
ACTIVE
VSON
VSON
VSON
VSON
DRC
DRC
DRC
DRC
10
10
10
10
3000 RoHS & Green
250 RoHS & Green
3000 RoHS & Green
250 RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
-40 to 85
-40 to 85
-40 to 85
-40 to 85
SBK
SBK
SBL
SBL
NIPDAU
NIPDAU
NIPDAU
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
20-Apr-2023
TAPE AND REEL INFORMATION
REEL DIMENSIONS
TAPE DIMENSIONS
K0
P1
W
B0
Reel
Diameter
Cavity
A0
A0 Dimension designed to accommodate the component width
B0 Dimension designed to accommodate the component length
K0 Dimension designed to accommodate the component thickness
Overall width of the carrier tape
W
P1 Pitch between successive cavity centers
Reel Width (W1)
QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE
Sprocket Holes
Q1 Q2
Q3 Q4
Q1 Q2
Q3 Q4
User Direction of Feed
Pocket Quadrants
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
TPS61230DRCR
TPS61230DRCT
TPS61232DRCR
TPS61232DRCT
VSON
VSON
VSON
VSON
DRC
DRC
DRC
DRC
10
10
10
10
3000
250
330.0
180.0
330.0
180.0
12.4
12.4
12.4
12.4
3.3
3.3
3.3
3.3
3.3
3.3
3.3
3.3
1.1
1.1
1.1
1.1
8.0
8.0
8.0
8.0
12.0
12.0
12.0
12.0
Q2
Q2
Q2
Q2
3000
250
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
20-Apr-2023
TAPE AND REEL BOX DIMENSIONS
Width (mm)
H
W
L
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SPQ
Length (mm) Width (mm) Height (mm)
TPS61230DRCR
TPS61230DRCT
TPS61232DRCR
TPS61232DRCT
VSON
VSON
VSON
VSON
DRC
DRC
DRC
DRC
10
10
10
10
3000
250
346.0
210.0
346.0
210.0
346.0
185.0
346.0
185.0
33.0
35.0
33.0
35.0
3000
250
Pack Materials-Page 2
GENERIC PACKAGE VIEW
DRC 10
3 x 3, 0.5 mm pitch
VSON - 1 mm max height
PLASTIC SMALL OUTLINE - NO LEAD
This image is a representation of the package family, actual package may vary.
Refer to the product data sheet for package details.
4226193/A
www.ti.com
PACKAGE OUTLINE
VSON - 1 mm max height
DRC0010G
PLASTIC QUAD FLATPACK-NO LEAD
3.1
2.9
B
A
PIN 1 INDEX AREA
3.1
2.9
1.0
0.8
C
SEATING PLANE
0.08 C
0.05
0.00
1.6±0.1
(0.2) TYP
6X 0.41
(0.18) TYP
8X 0.5
5
6
11
SYMM
2X
2
2.1±0.1
(R0.15)
TYP
1
10
0.3
10X
PIN1 ID
OPTIONAL
0.2
0.1
0.05
C A B
C
0.5
0.3
10X
SYMM
4218882/A 12/2020
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. The package thermal pad must be soldered to the printed circuit board for optimal thermal and mechanical performance.
www.ti.com
EXAMPLE BOARD LAYOUT
VSON - 1 mm max height
DRC0010G
PLASTIC QUAD FLATPACK-NO LEAD
(2.8)
SYMM
8X
(0.18)
TYP
6X (0.41)
(0.625)
TYP
10X (0.6)
10X (0.24)
1
10
8X (0.5)
SYMM
11
(2.15)
2X
(0.825)
6
5
(R0.05) TYP
2X (0.55)
(Ø 0.2) VIA
TYP
(1.6)
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE: 20X
0.07 MAX
ALL AROUND
0.07 MIN
ALL AROUND
METAL UNDER
SOLDER MASK
METAL
EXPOSED METAL
SOLDER MASK
OPENING
SOLDER MASK
OPENING
EXPOSED METAL
NON- SOLDER MASK
SOLDER MASK
DEFINED
DEFINED
(PREFERRED)
SOLDER MASK DETAILS
4218882/A 12/2020
NOTES: (continued)
4. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature
number SLUA271 (www.ti.com/lit/slua271)
.
5. Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to their locations shown
on this view. It is recommended that vias under paste be filled, plugged or tented.
www.ti.com
EXAMPLE STENCIL DESIGN
VSON - 1 mm max height
DRC0010G
PLASTIC QUAD FLATPACK-NO LEAD
(2.8)
SYMM
8X
(0.18)
6X (0.41)
8X (0.44)
10X (0.6)
10X (0.24)
1
10
2X
(1)
2X
(0.96)
8X (0.5)
11
SYMM
2X
(0.58)
6
5
(R0.05) TYP
EXPOSED METAL
TYP
2X (1.47)
SOLDER PASTE EXAMPLE
BASED ON 0.1 mm THICK STENCIL
EXPOSED PAD
79% PRINTED COVERAGE BY AREA
SCALE: 20X
4218882/A 12/2020
NOTES: (continued)
6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
www.ti.com
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