TPS56637RPAR [TI]
具有 ULQ-Mode 的 4.5V 至 28V、6A 同步降压转换器 | RPA | 10 | -40 to 150;
| 型号： | TPS56637RPAR |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 具有 ULQ-Mode 的 4.5V 至 28V、6A 同步降压转换器 | RPA | 10 | -40 to 150 开关 输出元件 转换器 |
| 文件： | 总36页 (文件大小：2134K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
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TPS56637
ZHCSIH1A –JULY 2018–REVISED SEPTEMBER 2019
TPS56637 4.5V 至 28V 输入、6A 同步降压转换器
1 特性
3 说明
1
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4.5V 至 28V 输入电压范围
TPS56637 是一款配备了集成式 MOSFET 且具有高效
率、高电压输入、易于使用的同步降压转换器。
0.6V 至 13V 输出电压范围
6A 最大连续输出电流
由于具有 4.5V 至 28V 的宽工作输入电压范
围，TPS56637 非常适用于由 12V、19V 和 24V 总线
电源轨供电的系统。其输出电压为 0.6V 至 13V，支持
高达 6A 的持续输出电流。
集成式 26mΩ 和 12mΩ MOSFET
0.6V ±1% 基准电压
D-CAP3™控制模式，用于快速瞬态响应
Eco-mode™和 FCCM（强制持续导通模式）可
选，适用于通过 MODE 引脚的轻负载运行
TPS56637 利用 DCAP3™控制模式提供快速瞬态响
应、良好的线路和负载调节，无需外部补偿，并支持低
等效串联电阻 (ESR) 输出电容器，如 POSCAP 和
MLCC。
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•
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内部 2ms 软启动
内置输出放电功能
500kHz 开关频率
电源正常状态指示器，可监控输出电压
逐周期过流限制
TPS56637 兼具 FCCM 和 Eco-mode™两种运行模
式，可在轻负载条件下通过 MODE 引脚配置进行选
择。要在轻负载条件下实现高效率，可以选择 Eco-
mode™。FCCM 符合严格的输出电压纹波要求。
非闭锁 UV、OV、OT 和 UVLO 保护
–40°C 至 +150°C 的工作结温范围
小型 10 引脚 3.0mm × 3.0mm HotRod™四方扁平
无引线 (QFN) 封装
可使用 WEBENCH® 电源设计器创建定制设计方案
TPS56637 具有完整的非闭锁 OV（过压）、UV（欠
压）、OC（过流）、OT（过热）以及 UVLO（欠压锁
定）保护以及电源正常状态指示器和输出放电功能 特
性。
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2 应用
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企业系统：多功能打印机、存储
TPS56637 采用 10 引脚 3.0mm x 3.0mm
HotRod™QFN 封装，额定结温范围为 –40°C 至 150°
C。
个人电子产品：电视、扬声器、机顶盒、便携式电
子产品
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工业 应用：电子销售终端、工厂自动化和控制、电
机驱动
器件信息(1)
通用 12V、19V、24V 总线电源
器件型号
TPS56637
封装
封装尺寸（标称值）
VQFN-HR (10)
3.00mm × 3.00mm
(1) 如需了解所有可用封装，请参阅数据表末尾的可订购产品附
录。
简化原理图
效率与输出电流间的关系
VOUT = 5V
VIN
CIN
BOOT
VIN
EN
100
98
96
94
92
90
88
CBST
L
VOUT
SW
TPS56637RPA
NC
PG
RFBT
COUT
MODE
AGND
FB
PGND
RFBB
86
VIN=8V
VIN=12V
84
Copyright © 2017, Texas Instruments Incorporated
VIN=19V
VIN=24V
82
80
0.01
0.1
Output Current (A)
1
10
FAD2
1
本文档旨在为方便起见，提供有关 TI 产品中文版本的信息，以确认产品的概要。 有关适用的官方英文版本的最新信息，请访问 www.ti.com，其内容始终优先。 TI 不保证翻译的准确
性和有效性。 在实际设计之前，请务必参考最新版本的英文版本。
English Data Sheet: SLVSEG1
TPS56637
ZHCSIH1A –JULY 2018–REVISED SEPTEMBER 2019
www.ti.com.cn
目录
7.4 Device Functional Modes........................................ 17
Application and Implementation ........................ 18
8.1 Application Information............................................ 18
8.2 Typical Application ................................................. 18
Power Supply Recommendations...................... 24
1
2
3
4
5
6
特性.......................................................................... 1
应用.......................................................................... 1
说明.......................................................................... 1
修订历史记录 ........................................................... 2
Pin Configuration and Functions......................... 3
Specifications......................................................... 4
6.1 Absolute Maximum Ratings ...................................... 4
6.2 Handling Ratings....................................................... 4
6.3 Recommended Operating Conditions....................... 4
6.4 Thermal Information.................................................. 4
6.5 Electrical Characteristics........................................... 5
6.6 Timing Requirements................................................ 6
6.7 Typical Characteristics.............................................. 7
Detailed Description ............................................ 10
7.1 Overview ................................................................. 10
7.2 Functional Block Diagram ....................................... 11
7.3 Feature Description................................................. 12
8
9
10 Layout................................................................... 24
10.1 Layout Guidelines ................................................. 24
10.2 Layout Example .................................................... 25
11 器件和文档支持 ..................................................... 26
11.1 文档支持 ............................................................... 26
11.2 接收文档更新通知 ................................................. 26
11.3 社区资源................................................................ 26
11.4 商标....................................................................... 26
11.5 静电放电警告......................................................... 26
11.6 Glossary................................................................ 26
12 机械、封装和可订购信息....................................... 26
12.1 Package Option Addendum .................................. 27
7
4 修订历史记录
Changes from Original (July 2018) to Revision A
Page
•
已更改 将销售状态从“预告信息”更改为“生产数据”.................................................................................................................. 1
2
Copyright © 2018–2019, Texas Instruments Incorporated
TPS56637
www.ti.com.cn
ZHCSIH1A –JULY 2018–REVISED SEPTEMBER 2019
5 Pin Configuration and Functions
RPA Package
10-Pin VQFN-HR
Top View
VIN
VIN
VIN
VIN
8
7
BOOT
SW
6
9
PGND
MODE
NC
10
5
1
2
3
4
Pin Functions
PIN
TYPE
DESCRIPTION
NAME
NO.
AGND
3
G
I
Ground of internal analog circuitry. Connect AGND to PGND plane at a single point.
Supply input for the gate drive voltage of the high-side MOSFET. Connect a 0.1-µF bootstrap capacitor
between BOOT and SW.
BOOT
EN
7
1
2
Enable input control. Driving EN high or leaving this pin floating enables the converter. A resistor
divider can be used to imply an UVLO function.
I
I
Output feedback. Connect FB to the tap of an external resistor divider from the output to GND to set
the output voltage.
FB
Operation mode selection pin. Leaving this pin floating(≥500 kΩ) forces the TPS56637 into FCCM.
Connecting this pin to GND(≤10 kΩ) forces the TPS56637 into Eco-mode™ under light load.
MODE
NC
10
5
I
N
O
Not Connected, keep this pin floating.
Open Drain Power Good Indicator, it is asserted low if output voltage is out of PG threshold due to
over-voltage, under-voltage, thermal shutdown, EN shutdown or during soft-start.
PG
4
PGND
SW
9
6
G
O
Power GND terminal. Source terminal of low side MOSFET.
Switching node terminal. Connect the output inductor to this pin with wide and short tracks
Input voltage supply pin. Drain terminal of high-side MOSFET. Connect the input decoupling capacitors
between VIN and GND.
VIN
8
P
Copyright © 2018–2019, Texas Instruments Incorporated
3
TPS56637
ZHCSIH1A –JULY 2018–REVISED SEPTEMBER 2019
www.ti.com.cn
6 Specifications
6.1 Absolute Maximum Ratings
Over the recommended operating junction temperature range of –40°C to +150°C (unless otherwise noted)(1)
MIN
–0.3
–0.3
–0.3
–0.3
–0.3
–0.3
–4
MAX
32
UNIT
V
VIN
BOOT
SW+6
6.0
V
Input voltage
BOOT-SW
EN, FB, MODE
PGND, AGND
SW
V
6.0
V
0.3
V
32
V
Output voltage
SW (<10 ns transient)
PG
32.5
6
V
-0.3
–40
–65
V
Operating junction temperature, TJ
Storage temperature, Tstg
150
150
°C
°C
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
6.2 Handling Ratings
VALUE
±2000
±500
UNIT
Human body model (HBM), per ANSI/ESDA/JEDEC JS-001, all pins(1)
Charged device model (CDM), per JEDEC specification JESD22-C101, all pins(2)
Electrostatic
discharge
VESD
V
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
6.3 Recommended Operating Conditions
Over the recommended operating junction temperature range of –40°C to 150°C (unless otherwise noted).(1)
MIN
4.5
NOM
MAX
28
UNIT
V
VIN
BOOT
4.5
33.5
5.5
5.5
0.1
28
V
Input Voltage
BOOT-SW
EN, FB, MODE
PGND, AGND
SW
-0.1
-0.1
-0.1
-0.1
-0.1
-40
V
V
V
V
Output Voltage
PG
5.5
150
V
Operating junction temperature, TJ
°C
(1) Recommended Operating Conditions indicate conditions for which the device is intended to be functional, but do not guarantee specific
performance limits. For guaranteed specifications, see Electrical Characteristics
6.4 Thermal Information
TPS56637
THERMAL METRIC(1)
QFN HOTROD
10 PINS
49.1
UNIT
RθJA
RθJC(top)
RθJB
ΨJT
Junction-to-ambient thermal resistance
Junction-to-case (top) thermal resistance
Junction-to-board thermal resistance
°C/W
°C/W
°C/W
°C/W
°C/W
28.8
16.1
Junction-to-top characterization parameter
Junction-to-board characterization parameter
0.8
ΨJB
16.2
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
4
Copyright © 2018–2019, Texas Instruments Incorporated
TPS56637
www.ti.com.cn
ZHCSIH1A –JULY 2018–REVISED SEPTEMBER 2019
6.5 Electrical Characteristics
The electrical ratings specified in this section apply to all specifications in this document unless otherwise noted. These
specifications are interpreted as conditions that will not degrade the parametric or functional specifications of the device for
the life of the product containing it. Typical values correspond to TJ = 25°C, VIN = 12 V. Minimum and maximum limits are
based on TJ = –40°C to +150°C, VIN = 4.5 V to 28 V(unless otherwise noted).
PARAMETER
SUPPLY CURRENT
TEST CONDITIONS
MIN
TYP
MAX
UNIT
Quiescent current, Operating at ULQ
mode(1)
IQ
140
2
µA
µA
ISD
Shutdown supply current
VIN Under-Voltage Lockout
TJ=25°C, VEN=0 V
UVLO
Wake up VIN voltage
Shut down VIN voltage
Hysteresis VIN voltage
4.0
3.6
4.2
3.7
4.4
3.8
V
V
UVLO
500
mV
ENABLE(EN PIN)
IEN_INPUT
IEN_HYS
VEN(ON)
VEN(OFF)
Input current
VEN = 1.1V
VEN = 1.3V
EN rising
1
4
µA
µA
V
Hysteresis current
1.18
1.12
1.26
Enable threshold
EN failling
1.04
V
FEEDBACK VOLTAGE
VOUT = 5V, continuous mode
operation, TJ=25°C
0.594
0.591
0.6
0.6
0.606
0.609
V
V
VFB
Feedback voltage
VOUT = 5V, continuous mode
operation, TJ=-40°C to 150°C
MOSFET
RDS(on)h
RDS(on)l
High side switch resistance
Low side switch resistance
TJ = 25°C, VBST - VSW = 5 V
TJ = 25°C
26
12
mΩ
mΩ
CURRENT LIMIT
IOCL
Valley current limit
6.3
2.3
7.5
3
8.6
3.7
A
A
IOC_REV
Reverse current limit for FCCM Mode
POWER GOOD
PG lower threshold - falling
PG lower threshold - rising
PG upper threshold - falling
PG upper threshold - rising
PG sink current
% of VFB
85%
90%
% of VFB
VPGTH
% of VFB
110%
115%
1.5
% of VFB
IPGSINK
IPGLK
VFB = 0.5V, VPG = 0.5V
VPG = 5.5V
mA
µA
PG leakage current
-1
1
FREQUENCY
FSW
Switching frequency
VOUT =5V, continuous mode operation
500
kHz
OUTPUT UNDERVOLTAGE AND OVERVOLTAGE PROTECTION
OVP detect(L>H)
Hysteresis
125%
5%
VOVP
Output OVP threshold
Output UVP threshold
Hiccup detect(H>L)
Hysteresis
65%
5%
VUVP
THERMAL SHUTDOWN
Temperature Rising
Hysteresis
165
30
°C
°C
TSDN
Thermal shutdown threshold(2)
SW DISCHARGE RESISTANCE
RDISCHG
VOUT discharge resistance
VEN=0, VSW=0.5V, TJ=25°C
200
Ω
(1) Not representative of the total input current of the system when in regulation. Ensured by design and characterization test.
(2) Not production tested. Ensured by design and engineering sample correlation.
Copyright © 2018–2019, Texas Instruments Incorporated
5
TPS56637
ZHCSIH1A –JULY 2018–REVISED SEPTEMBER 2019
www.ti.com.cn
6.6 Timing Requirements
The electrical ratings specified in this section apply to all specifications in this document unless otherwise noted. These
specifications are interpreted as conditions that will not degrade the parametric or functional specifications of the device for
the life of the product containing it. Typical values correspond to TJ = 25°C, VIN = 12 V. Minimum and maximum limits are
based on TJ = –40°C to +150°C, VIN = 4.5 V to 28 V(unless otherwise noted).
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
ON-TIME TIMER CONTROL
tON(MIN)
Minimum on time(1)
Minimum off time
50
ns
ns
VFB = 0.5 V, measure SW at 50% VIN
Eco-mode
,
tOFF(MIN)
200
300
SOFT START
TSS
Soft start time
Internal soft-start time
2
ms
OUTPUT UNDERVOLTAGE PROTECTION
UV triggered (VFB lower than 65%
TUVP_WAIT
UV protection hiccup wait time
0.25
25
ms
ms
VFB_nom
)
UV protection hiccup time before
recovery
TUVP_HICCUP
(1) Not production tested. Ensured by design and engineering sample correlation.
6
版权 © 2018–2019, Texas Instruments Incorporated
TPS56637
www.ti.com.cn
ZHCSIH1A –JULY 2018–REVISED SEPTEMBER 2019
6.7 Typical Characteristics
VIN = 12 V (unless otherwise noted)
143
142.5
142
4
3.5
3
141.5
141
140.5
140
2.5
2
139.5
139
1.5
1
138.5
138
-40 -20
0
20
40
60
80 100 120 140 160
-40 -20
0
20
40
60
80 100 120 140 160
TJ - Junction Temperature (èC)
TJ - Junction Temperature (èC)
IqTe
IsdT
图 1. Quiescent Current vs Temperature
图 2. Shutdown Current vs Temperature
18
16
14
12
10
8
40
38
36
34
32
30
28
26
24
22
20
-40 -20
0
20
40
60
80 100 120 140 160
-40 -20
0
20
40
60
80 100 120 140 160
TJ - Junction Temperature (èC)
TJ - Junction Temperature (èC)
RdsH
RdsL
图 3. High-Side RDS(on) vs Temperature
图 4. Low-side RDS(on) vs Temperature
0.606
0.604
0.602
0.6
4.6
4.4
4.2
4
VINUVLO_RISE
VINUVLO_FALL
0.598
0.596
0.594
3.8
3.6
3.4
-40 -20
0
20
40
60
80 100 120 140 160
-40 -20
0
20
40
60
80 100 120 140 160
TJ - Junction Temperature (èC)
TJ - Junction Temperature (èC)
Vfb2
UVLO
图 5. Feedback Voltage vs Temperature
图 6. VIN UVLO Threshold vs Temperature
版权 © 2018–2019, Texas Instruments Incorporated
7
TPS56637
ZHCSIH1A –JULY 2018–REVISED SEPTEMBER 2019
www.ti.com.cn
Typical Characteristics (接下页)
VIN = 12 V (unless otherwise noted)
1.26
7.75
7.7
VEN_RISING
VEN_FALLING
1.24
1.22
1.2
7.65
7.6
1.18
1.16
1.14
1.12
1.1
7.55
7.5
7.45
7.4
7.35
7.3
1.08
1.06
-40 -20
0
20
40
60
80 100 120 140 160
-40 -20
0
20
40
60
80 100 120 140 160
TJ - Junction Temperature (èC)
TJ - Junction Temperature (èC)
EN2p
LOC2
图 7. EN Threshold vs Temperature
图 8. Valley Current Limit vs Temperature
625
600
550
500
450
400
350
300
250
200
150
100
50
ECO
FCCM
600
575
550
525
500
475
450
VIN=8V
VIN=12V
VIN=19V
VIN=24V
0
0.001
6
8
10 12 14 16 18 20 22 24 26 28 30
VIN - Input Voltage (V)
0.01
0.1
IOUT - Output Current (A)
1
10
FswV
FswL
VOUT=5 V
IOUT = 6 A
VOUT = 5 V
L = 3.3 µH
Eco-mode™
图 9. Switching Frequency vs Input voltage
图 10. Switching Frequency vs Output Current
100%
90%
80%
70%
60%
50%
40%
30%
20%
10%
0
100%
90%
80%
70%
60%
50%
40%
30%
20%
10%
0
VIN=6V, ECO
VIN=6V, ECO
VIN=6V, FCCM
VIN=12V, ECO
VIN=12V, FCCM
VIN=19V, ECO
VIN=19V, FCCM
VIN=24V, ECO
VIN=24V, FCCM
VIN=6V, FCCM
VIN=12V, ECO
VIN=12V, FCCM
VIN=19V, ECO
VIN=19V, FCCM
VIN=24V, ECO
VIN=24V, FCCM
0.001
0.01
0.1
IOUT - Load Current (A)
1
10
0.001
0.01
0.1
IOUT - Load Current (A)
1
10
1.05
3.3V
图 11. VOUT = 1.05 V Efficiency, L = 1 µH
图 12. VOUT = 3.3 V Efficiency, L = 2.2 µH
8
版权 © 2018–2019, Texas Instruments Incorporated
TPS56637
www.ti.com.cn
ZHCSIH1A –JULY 2018–REVISED SEPTEMBER 2019
Typical Characteristics (接下页)
VIN = 12 V (unless otherwise noted)
100%
90%
80%
70%
60%
50%
40%
30%
20%
10%
0
100%
90%
80%
70%
60%
50%
40%
30%
20%
10%
0
VIN=8V, ECO
VIN=8V, FCCM
VIN=12V, ECO
VIN=12V, FCCM
VIN=19V, ECO
VIN=19V, FCCM
VIN=24V, ECO
VIN=24V, FCCM
VIN=19V, ECO
VIN=19V, FCCM
VIN=24V, ECO
VIN=24V, FCCM
0.001
0.01
0.1
IOUT - Load Current (A)
1
10
0.001
0.01
0.1
IOUT - Load Current (A)
1
10
5Vou
12Vo
图 13. VOUT = 5 V Efficiency, L = 3.3 µH
图 14. VOUT = 12 V Efficiency, L = 5.6 µH
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9
TPS56637
ZHCSIH1A –JULY 2018–REVISED SEPTEMBER 2019
www.ti.com.cn
7 Detailed Description
7.1 Overview
The TPS56637 is a 6-A synchronous buck converter operating from 4.5V to 28V input voltage (VIN), and its
output voltage ranges from 0.6V to 13V. The proprietary D-CAP3™ mode enables low external component
count, ease of design, optimization of the power design for power, size and efficiency. The device employs D-
CAP3™ mode control that provides fast transient response with no external compensation components and an
accurate feedback voltage. The control topology provides seamless transition between CCM operating mode at
higher load condition and DCM operation at lighter load condition. Eco-mode™ allows the TPS56637 to maintain
high efficiency at light load. FCCM mode has the quasi-fixed switching frequency at both light and heavy load.
The TPS56637 is able to adapt both low equivalent series resistance (ESR) output capacitors such as POSCAP
or SP-CAP, and ultra-low ESR ceramic capacitors.
10
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TPS56637
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ZHCSIH1A –JULY 2018–REVISED SEPTEMBER 2019
7.2 Functional Block Diagram
PG rising threshold
+
PG
PG
Logic
UV threshold
OV threshold
+
+
UV
OV
+
PG falling threshold
Regulator
VREG5
VIN
+
UVLO
4.2V/3.7V
FB
0.6V
Reference
Soft Start
+
+
BOOT
SS
Control Logic
ñ
ñ
ñ
ñ
ñ
ñ
ñ
On/Off time
Min On/Off time
FCCM/Eco-mode
Soft-start
One Shot
TSD
+
165°C /
30°C
SW
Power Good
OCL
UVP/OVP/TSD
XCON
VREG5
Ih
Ip
PGND
EN
+
+
OCL
Enable
Threshold
Light Load
Operation
+
MODE
NC
ZC
+
NOCL
AGND
Discharge Control
Copyright © 2017, Texas Instruments Incorporated
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7.3 Feature Description
7.3.1 The Adaptive On-Time Control and PWM Operation
The main control loop of the TPS56637 is adaptive on-time pulse width modulation (PWM) controller that
supports a proprietary DCAP3™ mode control. The DCAP3™ mode control combines adaptive on-time control
with an internal compensation circuit for quasi-fixed frequency and low external component count configuration
with both low-ESR and ceramic output capacitors. It is stable even with virtually no ripple at the output. The
TPS56637 also includes an error amplifier that makes the output voltage very accurate. No external current
sense network or loop compensation is required for DCAP3™ control topology.
At the beginning of each cycle, the high-side MOSFET is turned on. This MOSFET is turned off after internal
one-shot timer expires. This one-shot duration is set proportional to the output voltage, VOUT, and is inversely
proportional to the converter input voltage, VIN, to maintain a pseudo-fixed frequency over the input voltage
range, hence it is called adaptive on-time control. When the feedback voltage falls below the reference voltage,
the one-shot timer is reset and the high-side MOSFET is turned on again . An internal ripple generation circuit is
added to reference voltage for emulating the output ripple, and this enables the use of very low-ESR output
capacitors such as multi-layered ceramic caps (MLCC).
7.3.2 Mode Selection
TPS56637 has a MODE pin that can offer 2 different states of operations under light load condition. If MODE pin
is short to GND(≤10kΩ), TPS56637 works under Eco-mode™ control scheme. If MODE pin is floating(≥500kΩ),
TPS56637 works under FCCM mode.
图 15 below shows the typical start-up sequence of the device once the enable signal triggers the EN turn-on
threshold. After the voltage of internal VCC crosses the UVLO rising threshold, it takes about 64µs to finish the
reading and setting of MODE. After this process, the MODE is latched and will not change until VIN or EN toggles
to restart-up this device. Then after a delay of around 650µs the internal soft-start function begins to ramp up the
reference voltage to the PWM comparator.
表 1. MODE Pin Settings
MODE Pin
Light Load Operation Mode
Eco-mode™
Short to GND (≤10kΩ)
Floating (≥500kΩ)
FCCM
EN Threshold
1.18V
EN
VCC UVLO
4.2V
MODE
Detection
Internal
VCC
MODE
100µs 64µs 650µs
Tss= 2ms
90%
VOUT
VOUT
1ms
PGOOD
图 15. Power-Up Sequence
12
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7.3.2.1 Eco-mode™ Control Scheme
When MODE pin is short to GND(≤10kΩ), the TPS56637 is set to Eco-mode™ control scheme to maintain high
light load efficiency. As the output current decreases from heavy load condition, the inductor current is also
reduced and eventually comes to a point that its rippled valley touches zero level, which is the boundary between
continuous conduction and discontinuous conduction modes. The rectifying MOSFET is turned off when the zero
inductor current is detected. As the load current further decreases the converter runs into discontinuous
conduction mode. The on-time is kept almost the same as it was in the continuous conduction mode so that
longer time is needed to discharge the output capacitor with smaller load current to the level of the reference
voltage. This process makes the switching frequency lower, proportional to the load current, and keeps the light
load efficiency high. The transition point to the light load operation IOUT(LL) current can be calculated by 公式 1.
1
(V - VOUT )∂VOUT
IN
IOUT(LL)
=
∂
2∂L∂fSW
V
IN
(1)
7.3.2.2 FCCM Control
When MODE pin is floating(≥500kΩ), the TPS56637 is set to operate in forced continuous conduction mode
(FCCM) in light load conditions and allows the inductor current to become negative. In FCCM, the switching
frequency is maintained at a quasi-fixed level over the entire load range which is suitable for applications
requiring tight control of the switching frequency and output voltage ripple at the cost of lower efficiency under
light load compared with which under Eco-mode™. This mode also can help to avoid switching frequency
dropping into audible range that may introduces some audible "noise".
7.3.3 Soft Start and Pre-Biased Soft Start
The TPS56637 features an internal 2-ms soft-start function. The internal soft start circuitry controls the output
voltage slope during startup. This avoids excessive inrush current and ensures a controlled output voltage rise
time. It also prevents unwanted voltage drops from high impedance power sources or batteries. When EN pin is
set to start device operation, the internal soft-start circuitry will begin ramping up the reference voltage to the
PWM comparator with a controlled slope. If the output capacitor is pre-biased at startup, the device initiates
switching and start ramping up only after the internal reference voltage becomes greater than the feedback
voltage VFB. This scheme ensures that the converters ramp up smoothly into regulation point.
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7.3.4 Enable and Adjusting Undervoltage Lockout
The EN pin provides electrical on and off control of the device. When the EN pin voltage exceeds the threshold
voltage, the device begins operating. If the EN pin voltage is pulled below the threshold voltage, the regulator
stops switching and enters the standby operation.
The EN pin has an internal pull-up current source which allows the user to float the EN pin to enable the device.
If an application requires control of the EN pin, open-drain or open-collector output logic can be used to interface
with the pin.
The TPS56637 implements internal undervoltage-lockout (UVLO) circuitry on the VIN pin. The device is disabled
when the VIN pin voltage falls below the internal VIN UVLO threshold. The internal VIN UVLO threshold has a
hysteresis of 500 mV.
If an application requires a higher UVLO threshold on the VIN pin, then the EN pin can be configured as shown
in 图 16. When using the external UVLO function, setting the hysteresis at a value greater than 500 mV is
recommended.
The EN pin has a small pull-up current, Ip, which sets the default state of the pin to enable when no external
components are connected. The pull-up current is also used to control the voltage hysteresis for the UVLO
function because it increases by Ih when the EN pin crosses the enable threshold. Use 公式 2 , and 公式 3 to
calculate the values of R1 and R2 for a specified UVLO threshold. Once R1, R2 were settled down, the VEN
voltage can be calculated by 公式 4, which should be lower than 5.5V with max VIN.
VIN
Device
R1
R2
Ip
Ih
EN
图 16. Adjustable VIN Undervoltage Lockout
VENfalling
VSTART
- VSTOP
VENrisig
R1 =
≈
∆
«
’
÷
÷
◊
VENfalling
∆
Ip 1-
+ Ih
VENrising
(2)
(3)
R1 ìVENfalling
R2 =
VSTOP - VENfalling + R1 Ip + Ih
R ìV + R R I + I
(
)
2
IN
1
2
p
h
VEN =
R1 + R2
(4)
Where
•
•
•
•
Ip = 1 µA
Ih = 4 µA
VENfalling = 1.12 V
VENrising = 1.18 V
14
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7.3.5 Output Overcurrent Limit and Undervoltage Protection
The output overcurrent limit (OCL) is implemented using a cycle by cycle valley detect control circuit. The
switching current is monitored during off state by measuring the low-side FET drain to source voltage. This
voltage is proportional to the switching current. To improve accuracy, the voltage sensing is temperature
compensated.
During the on-time of the high-side FET switch, the switching current increases at a linear rate determined by
VIN, VOUT, the on-time and the output inductor value. During the on-time of the low-side FET switch, this current
decreases linearly. The average value of the switch current is the load current IOUT. If the monitored current is
above the OCL level, the converter maintains low-side FET on and delays the creation of a new set pulse, even
the voltage feedback loop requires one, until the current level becomes OCL level or lower. In subsequent
switching cycles, the on-time is set to a fixed value and the current is monitored in the same manner.
There are some important considerations for this type of over current limit. When the load current is higher than
the over current threshold by one half of the peak-to-peak inductor ripple current, the OCL is triggered and the
current is being limited, output voltage tends to drop because the load demand is higher than what the converter
can support. When the output voltage falls below 65% of the target voltage, the UVP comparator detects it and
shuts down the device after a deglitch wait time of 0.25ms and then re-start after the hiccup time of 25ms. When
the over current condition is removed, the output will be recovered.
7.3.6 Overvoltage Protection
When the output voltage becomes higher than 125% of the target voltage, the OVP comparator output goes high
after a deglitch time of 256µs and then the output will be discharged. When the over voltage condition is
removed, the discharge path will still be on for a hiccup time of 25ms before a re-soft-start process to recover the
output voltage.
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7.3.7 UVLO Protection
Undervoltage Lockout protection(UVLO) monitors the internal regulator voltage. When the voltage is lower than
UVLO threshold voltage, the device is shut down. This protection is non-latched.
7.3.8 Thermal Shutdown
The junction temperature (Tj) of the device is monitored by an internal temperature sensor. If Tj exceeds 165°C
(typical), the device goes into thermal shut down. Both the high-side and low-side power FETs are turned off and
the discharge path is turned on. When Tj decreases below the hysteresis amount, the converter resumes normal
operation, beginning with Soft Start. To avoid unstable conditions, a hysteresis of typically 30°C is implemented
on the thermal shut down temperature.
7.3.9 Output Voltage Discharge
The TPS56637 has a built in discharge function by using an integrated MOSFET with 200-Ω RDS(on), which is
connected to the output terminal SW. The discharge is slow due to the lower current capability of the MOSFET.
The discharge path will be turned on when the device is turned off due to UV, OV, OT and EN shut down
conditions.
7.3.10 Power Good
The TPS56637 has a built in power good (PG) function to indicate whether the output voltage has reached its
appropriate level or not. The PG signal can be used for startup sequencing of multiple rails. The PG pin is an
open-drain output that requires a pull-up resistor (to any voltage below 5.5 V). A pull-up resistor of 100kΩ is
recommended to pull it up to 5V voltage. It can sink 1.5mA of current and maintain its specified logic low level.
Once the FB pin voltage is between 90% and 110% of the internal reference voltage (VREF) and after a deglitch
time of 64µs, the PG turns to high impedance status. The PG pin is pulled low after a deglitch time of 32µs when
FB pin voltage is lower than 85% of the internal reference voltage or greater than 115% of the internal reference
voltage, or in events of thermal shutdown, EN shutdown, UVLO conditions. VIN must remain present for the PG
pin to stay Low.
表 2. Power Good Pin Logic Table (TPS56637)
PG Logic Status
Device State
High Impedance
Low
VFB doesn't trigger VPGTH
VFB triggers VPGTH
√
Enable (EN=High)
√
√
√
√
Shutdown (EN=Low)
UVLO
2 V < VIN < VUVLO
TJ > TSD
Thermal Shutdown
Power Supply Removal
VIN < 2 V
√
16
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7.4 Device Functional Modes
7.4.1 Standby Operation
The TPS56637 can be placed in standby mode by pulling the EN pin low. The device operates with a shutdown
current of 2µA(typical) when in standby condition.
7.4.2 Normal Operation
When the input voltage is above the UVLO threshold voltage and EN pin is high, TPS56637 can operate in its
normal switching modes. Normal continuous conduction mode (CCM) occurs when the minimum switch current is
above 0 A. In CCM, the TPS56637 operates at a quasi-fixed frequency of 500kHz (typical).
7.4.3 Light Load Operation
When the MODE pin is selected to operate in FCCM mode, the converter operates in continuous conduction
mode (FCCM) during light-load conditions. During FCCM, the switching frequency is maintained at an almost
constant level over the entire load range which is suitable for applications requiring tight control of the switching
frequency and output voltage ripple at the cost of lower efficiency under light load. If the MODE pin is selected to
operate in Eco-mode™ control scheme, the device enters pulse skip mode after the valley of the inductor ripple
current crosses zero. The Eco-mode™ control scheme maintains higher efficiency at light load with a lower
switching frequency. If the TPS56637 works at Eco-mode™ and the load current is light enough to a specific
value, the TPS56637 will enter ULQ mode that the TPS56637 will disable some internal circuits to further
increase the light load efficiency.
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8 Application and Implementation
注
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
8.1 Application Information
The schematic of 图 17 shows a typical application for TPS56637. This design converts an input voltage range of
8V to 28V down to 5V with a maximum output current of 6 A.
8.2 Typical Application
The application schematic in 图 17 shows the TPS56637 8-V to 28-V Input, 5-V output converter design meeting
the requirements for 6-A output. This circuit is available as the evaluation module (EVM). The sections provide
the design procedure.
U1
C4
0.1uF
SW
L1
3.3uH
R4
0
VIN
VOUT
8
1
7
VIN
EN
BOOT
J1
DNP
C8
22uF
1
2
DNP
C7
22uF
2
1
C1
10uF
C2
10uF
C3
0.1uF
R5
49.9
C5
22uF
C6
22uF
J2
6
4
2
9
3
R1
169k
VCC
SW
PG
R9
R8
20.0k
100pF
100k
C9
R6
73.2k
5
NC
FB
PGND
PGND
FB
PGND
AGND
R2
36.1k
R7
10.0k
10
MODE
PGND
TPS56637
AGND
AGND
AGND PGND
AGND
Copyright © 2017, Texas Instruments Incorporated
图 17. TPS56637 5-V, 6-A Reference Design
8.2.1 Design Requirements
表 3 shows the design parameters for this application.
表 3. Design Parameters
PARAMETER
Input voltage range
EXAMPLE VALUE
24V nominal, 8V to 28V
Output voltage
5V
ΔVOUT = ±5%
<30 mV @ CCM
6A
Transient response, 6-A load step
Output ripple voltage
Output current rating
Operating frequency
500 kHz
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8.2.2 Detailed Design Procedure
8.2.2.1 Output Voltage Resistors Selection
The output voltage is set with a resistor divider from the output node to the VFB pin. TI recommends to use 1%
tolerance or better divider resistors. Start by using 公式 5 to calculate VOUT. R5 is optional and can be used to
measure the control loop's frequency response.
To improve efficiency at very light loads consider using larger value resistors. If the resistance is too high the
device will be more susceptible to noise and voltage errors from the VFB input current will be more noticeable.
Please note that dynamically adjusting output voltage is not recommended.
R6
≈
«
’
÷
VOUT = 0.6ì 1+
∆
R7
◊
(5)
8.2.2.2 Output Filter Selection
The LC filter used as the output filter has double pole at:
1
fP =
2Œ LOUT ìCOUT
(6)
At low frequencies, the overall loop gain is set by the output set-point resistor divider network and the internal
gain of the device. The low frequency phase is 180 degrees. At the output filter pole frequency, the gain rolls off
at a –40 dB per decade rate and the phase drops rapidly. D-CAP3 introduces a high frequency zero that reduces
the gain roll off to –20 dB per decade and increases the phase to 90 degrees one decade above the zero
frequency. The inductor and capacitor for the output filter must be selected so that the double pole of 公式 6 is
located below the high frequency zero but close enough that the phase boost provided be the high frequency
zero provides adequate phase margin for a stable circuit. To meet this requirement use the values recommended
in 表 4.
表 4. Recommended Component Values
(3)
COUT
(µF)
C9 (pF)(4) R8 (kΩ)(4)
OUTPUT
VOLTAGE(1)
(V)
R6(2)
(kΩ)
R7
(kΩ)
L1
(µH)
MIN
30
30
30
20
20
25
TYP
35
MAX
100
100
100
100
100
100
1.05
1.2
1.8
3.3
5
7.5
10
10.0
10.0
10.0
10.0
10.0
10.0
1
1
35
20
1.2
2.2
3.3
5.6
35
45.3
73.2
191
35
100 to 220
100 to 220
100 to 220
20
20
20
30
12
30
(1) Please use the recommended L1 and COUT combination of the higher and closest output rail for
unlisted output rails.
(2) R6=0Ω for VOUT=0.6V
(3) COUT is the sum of effective output capacitance. In this datasheet the effective capacitance is defined
as the actual capacitance under DC bias and temperature, not the rated or nameplate values. All high
value ceramic capacitors have a large voltage coefficient in addition to normal tolerances and
temperature effects. A careful study of bias and temperature variation of any capacitor bank should be
made in order to ensure that the minimum value of effective capacitance is provided. Refer to the
information of DC bias and temperature characteristics from manufacturers of ceramic capacitors.
(4) R8 and C9 can be used to improve the load transient response or improve the loop-phase margin. The
application report Optimizing Transient Response of Internally Compensated DCDC Converters with
Feed-forward Capacitor is helpful when experimenting with a feed-forward capacitor.
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The inductor peak-to-peak ripple current, peak current and RMS current are calculated using 公式 7, 公式 8, and
公式 9. The inductor saturation current rating must be greater than the calculated peak current and the RMS or
heating current rating must be greater than the calculated RMS current.
Use 500 kHz for fSW. Make sure the chosen inductor is rated for the peak current of 公式 8 and the RMS current
of 公式 9.
V
IN(MAX) - VOUT
VOUT
IlP-P
=
∂
V
LO ∂fSW
IN(MAX)
(7)
(8)
IlP-P
IlPEAK = IO +
2
1
2
2
ILO(RMS) = IO
+
IlP-P
12
(9)
For this design example, the calculated peak current is 7.28A and the calculated RMS current is 6.05 A. The
inductor used is IHLP3232DZER3R3M11 with a peak current rating of 10.5A and an RMS current rating of 9.7A.
The capacitor value and ESR determines the amount of output voltage ripple. TheTPS56637 is intended for use
with ceramic or other low ESR capacitors. Recommended values range from 20 µF to 100 µF. Use 公式 10 to
determine the required RMS current rating for the output capacitor.
VOUT
∂
(
V - VOUT
)
IN
ICO(RMS)
=
12 ∂V ∂LO ∂fSW
IN
(10)
For this design two MuRata GRM32ER71E226KE15L 22-µF output capacitors are used so that the effective
capacitance is 31.08 µF at DC biased voltage of 5V. The calculated RMS current is 0.738A and each output
capacitor is rated for 4 A.
8.2.2.3 Input Capacitor Selection
The TPS56637 requires an input decoupling capacitor and a bulk capacitor is needed depending on the
application. TI recommends a ceramic capacitor over 10 µF for the decoupling capacitor. An additional 0.1-µF
capacitor (C3) from VIN to PGND pin is recommended to provide additional high frequency filtering. The
capacitor voltage rating needs to be greater than the maximum input voltage. The input voltage ripple can be
calculated using 公式 11.
Ioutmax ∂0.25
Cin ∂fSW
ûV =
in
(11)
The capacitor must also have a ripple current rating greater than the maximum input current ripple of the
application. The input ripple current is calculated by 公式 12:
VIN(min)-VOUT
(
)
VOUT
ICIN(rms) = IOUT ×
×
VIN(min)
VIN(min)
(12)
8.2.2.4 Bootstrap Capacitor Selection
A 0.1-µF ceramic capacitor(C4) must be connected between the BOOT to SW pin for proper operation. TI
recommends to use a ceramic capacitor with X5R or better grade dielectric. The capacitor must have a 10-V or
higher voltage rating.
20
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8.2.3 Application Curves
100%
95%
90%
85%
80%
75%
70%
65%
60%
55%
50%
5.032
5.028
5.024
5.02
5.016
5.012
5.008
5.004
5
VIN=8V, VOUT=5V
VIN=12V, VOUT=5V
VIN=19V, VOUT=5V
VIN=24V, VOUT=5V
VIN=8V
VIN=12V
VIN=19V
VIN=24V
4.996
4.992
0.001
0.01
0.1
IOUT - Load Current (A)
1
10
0.001
0.01
0.1
IOUT (A)
1
10
5Vou
Load
图 18. Efficiency
图 19. Load Regulation
5.056
60
50
240
Magnitude
Phase
200
160
120
80
5.048
5.04
40
30
5.032
5.024
5.016
5.008
5
20
10
40
0
0
-10
-20
-30
-40
-50
-60
-40
-80
-120
-160
-200
-240
IOUT = 0.01A
IOUT = 0.6A
IOUT = 3A
4.992
4.984
4.976
IOUT = 6A
1x103
1x104
VIN = 24V
1x105
Frequency (Hz)
1x106 3x106
8
10
12
14
16
18
VIN (V)
20
22
24
26
28
Bode
Line
VOUT = 5V
IOUT = 6A
图 21. Bode Plot
图 20. Line Regulation
Vin = 200 mV/div
Vout = 50 mV/div
VIN = 300 mV/div
VOUT = 40 mV/div
IL = 3 A/div
IL = 3 A/div
SW = 8 V/div
SW = 7 V/div
5 µs/div
100 µs/div
图 22. Steady State Waveforms, IOUT = 0.01 A
图 23. Steady State Waveforms, IOUT= 0.6 A
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VIN = 300 mV/div
VOUT = 40 mV/div
VIN = 300 mV/div
VOUT = 40 mV/div
IL = 3 A/div
IL = 3 A/div
SW = 8 V/div
SW = 8 V/div
2 µs/div
2 µs/div
图 24. Steady State Waveforms, IOUT= 3 A
图 25. Steady State Waveforms, IOUT= 6 A
VOUT = 200 mV/div
VOUT = 200 mV/div
ILOAD = 3 A/div
ILOAD = 3 A/div
500 µs/div
500 µs/div
图 26. Transient Response 0 to 3 A
图 27. Transient Response 0 to 6 A
VOUT = 200 mV/div
VOUT = 200 mV/div
ILOAD = 3 A/div
ILOAD = 3 A/div
500 µs/div
500 µs/div
图 28. Transient Response 0.6 to 5.4 A
图 29. Transient Response 3 to 6 A
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Vin = 20 V/div
Vout = 5 V/div
Vin = 20 V/div
Vout = 5 V/div
PG = 5 V/div
PG = 5 V/div
SW = 20 V/div
SW = 20 V/div
10 ms/div
10 ms/div
图 30. Startup Relative to VIN
图 31. Shutdown Relative to VIN
EN = 5 V/div
EN = 5 V/div
Vout = 5 V/div
Vout = 5 V/div
PG = 5 V/div
PG = 5 V/div
SW = 20 V/div
SW = 20 V/div
200 µs/div
5 ms/div
图 32. Enable Relative to EN
图 33. Disable Relative to EN
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9 Power Supply Recommendations
The TPS56637 is designed to operate from input supply voltage in the range of 4.5 V to 28 V. Buck converters
require the input voltage to be higher than the output voltage for proper operation. Input supply current must be
appropriate for the desired output current. If the input voltage supply is located far from the TPS56637 circuit,
some additional input bulk capacitance is recommended.
10 Layout
10.1 Layout Guidelines
1. Recommend a four-layer PCB for good thermal performance and with maximum ground plane.
2. VIN and GND traces should be as wide as possible to reduce trace impedance. The wide areas are also of
advantage from the view point of heat dissipation.
3. Putting at least two vias for VIN and GND traces, and as close as possible to the pins.
4. The input capacitor and output capacitor should be placed as close to the device as possible to minimize
trace impedance.
5. Provide sufficient vias for the input capacitor and output capacitor.
6. Keep the SW trace as physically short and wide as practical to minimize radiated emissions.
7. Do not allow switching current to flow under the device.
8. A separate VOUT path should be connected to the upper feedback resistor.
9. Make a Kelvin connection to the GND pin for the feedback path.
10. Voltage feedback loop should be placed away from the high-voltage switching trace, and preferably has
ground shield.
11. The trace of the VFB node should be as small as possible to avoid noise coupling.
12. The GND trace between the output capacitor and the GND pin should be as wide as possible to minimize
its trace impedance.
24
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10.2 Layout Example
VIN
CBST
INDUCTOR
VOUT
8
7
5
CHF
CIN
6
9
COUT
COUT
10
AGND
1
2
3
4
RFBB
RENB
RPG
CFF
VCC
RENT
RFBT
RFF
PGND
PGND
Top Trace/Plane
AGND Plane
Top
PGND Plane
Inner PGND and AGND Plane
Inner PGND and AGND Plane
VIA to Signal Plane
VIA to PGND Planes
VIA to AGND Planes
Signal traces and PGND and AGND Plane
Trace on Signal Layer
图 34. TPS56637 Layout
版权 © 2018–2019, Texas Instruments Incorporated
25
TPS56637
ZHCSIH1A –JULY 2018–REVISED SEPTEMBER 2019
www.ti.com.cn
11 器件和文档支持
11.1 文档支持
11.1.1 相关文档
请参阅如下相关文档：德州仪器 (TI)，《TPS56637EVM-029 6A 稳压器评估模块》 用户指南
•
•
德州仪器 (TI)，《TPS56637EVM-029 6A 稳压器评估模块》 用户指南
11.2 接收文档更新通知
要接收文档更新通知，请导航至 ti.com. 上的器件产品文件夹。单击右上角的通知我进行注册，即可每周接收产品
信息更改摘要。有关更改的详细信息，请查看任何已修订文档中包含的修订历史记录。
11.3 社区资源
TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help — straight
from the experts. Search existing answers or ask your own question to get the quick design help you need.
Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do
not necessarily reflect TI's views; see TI's Terms of Use.
11.4 商标
D-CAP3, Eco-mode, HotRod, DCAP3, E2E are trademarks of Texas Instruments.
WEBENCH is a registered trademark of Texas Instruments.
11.5 静电放电警告
ESD 可能会损坏该集成电路。德州仪器 (TI) 建议通过适当的预防措施处理所有集成电路。如果不遵守正确的处理措施和安装程序 , 可
能会损坏集成电路。
ESD 的损坏小至导致微小的性能降级 , 大至整个器件故障。 精密的集成电路可能更容易受到损坏 , 这是因为非常细微的参数更改都可
能会导致器件与其发布的规格不相符。
11.6 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
12 机械、封装和可订购信息
以下页面包含机械、封装和可订购信息。这些信息是指定器件的最新可用数据。数据如有变更，恕不另行通知，且
不会对此文档进行修订。如需获取此数据表的浏览器版本，请查阅左侧的导航栏。
26
版权 © 2018–2019, Texas Instruments Incorporated
TPS56637
www.ti.com.cn
ZHCSIH1A –JULY 2018–REVISED SEPTEMBER 2019
12.1 Package Option Addendum
12.1.1 Packaging Information
Package
Type
Package
Drawing
Package
Qty
Lead/Ball
Finish(3)
(1)
(2)
(4)
Orderable Device
Status
Pins
Eco Plan
MSL Peak Temp
Op Temp (°C)
Device Marking(5)(6)
Green (RoHS
& no Sb/Br)
Level-2-260C-1
YEAR
TPS56637RPAR
ACTIVE
VQFN-HR
RPA
10
3000
CU NIPDAU
-40 to 150
P56637
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PRE_PROD Unannounced device, not in production, not available for mass market, nor on the web, samples not available.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
space
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest
availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the
requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified
lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used
between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by
weight in homogeneous material)
space
(3) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the
finish value exceeds the maximum column width.
space
(4) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
space
(5) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device
space
(6) Multiple Device markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a
continuation of the previous line and the two combined represent the entire Device Marking for that device.
Important Information and Disclaimer: The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief
on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third
parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for
release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
版权 © 2018–2019, Texas Instruments Incorporated
27
TPS56637
ZHCSIH1A –JULY 2018–REVISED SEPTEMBER 2019
www.ti.com.cn
12.1.2 Tape and Reel Information
REEL DIMENSIONS
TAPE DIMENSIONS
K0
P1
W
B0
Reel
Diameter
Cavity
A0
A0 Dimension designed to accommodate the component width
B0 Dimension designed to accommodate the component length
K0 Dimension designed to accommodate the component thickness
Overall width of the carrier tape
W
P1 Pitch between successive cavity centers
Reel Width (W1)
QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE
Sprocket Holes
Q1 Q2
Q3 Q4
Q1 Q2
Q3 Q4
User Direction of Feed
Pocket Quadrants
Reel
Diameter
(mm)
Reel
Width W1
(mm)
Package
Type
Package
Drawing
A0
(mm)
B0
(mm)
K0
(mm)
P1
(mm)
W
(mm)
Pin1
Quadrant
Device
Pins
SPQ
TPS56637RPAR
VQFN-HR
RPA
10
3000
330
12
3.3
3.3
1.1
8
9.1
2
28
版权 © 2018–2019, Texas Instruments Incorporated
TPS56637
www.ti.com.cn
ZHCSIH1A –JULY 2018–REVISED SEPTEMBER 2019
TAPE AND REEL BOX DIMENSIONS
Width (mm)
H
W
L
Device
Package Type
VQFN-HR
Package Drawing Pins
RPA 10
SPQ
Length (mm) Width (mm)
367 367
Height (mm)
TPS56637RPAR
3000
35
版权 © 2018–2019, Texas Instruments Incorporated
29
PACKAGE OPTION ADDENDUM
www.ti.com
12-Nov-2022
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
TPS56637RPAR
ACTIVE
VQFN-HR
RPA
10
3000 RoHS & Green
Call TI | NIPDAU
Level-2-260C-1 YEAR
-40 to 150
T56637
Samples
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
20-Apr-2023
TAPE AND REEL INFORMATION
REEL DIMENSIONS
TAPE DIMENSIONS
K0
P1
W
B0
Reel
Diameter
Cavity
A0
A0 Dimension designed to accommodate the component width
B0 Dimension designed to accommodate the component length
K0 Dimension designed to accommodate the component thickness
Overall width of the carrier tape
W
P1 Pitch between successive cavity centers
Reel Width (W1)
QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE
Sprocket Holes
Q1 Q2
Q3 Q4
Q1 Q2
Q3 Q4
User Direction of Feed
Pocket Quadrants
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
TPS56637RPAR
VQFN-
HR
RPA
10
3000
330.0
12.4
3.3
3.3
1.1
8.0
12.0
Q2
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
20-Apr-2023
TAPE AND REEL BOX DIMENSIONS
Width (mm)
H
W
L
*All dimensions are nominal
Device
Package Type Package Drawing Pins
VQFN-HR RPA 10
SPQ
Length (mm) Width (mm) Height (mm)
346.0 346.0 33.0
TPS56637RPAR
3000
Pack Materials-Page 2
PACKAGE OUTLINE
VQFN-HR - 1 mm max height
PLASTIC QUAD FLAT-NO LEAD
RPA0010A
3.1
2.9
A
B
3.1
2.9
PIN 1 INDEX AREA
1.00
0.80
C
SEATING PLANE
0.08 C
0.05
0.00
PKG
0.37
7
0.87
2X 0.93
5
(0.1) TYP
5X 0.5
4
1.6
1.4
PKG
0.3
3X
2
2X
0.2
1.8
0.1
C A B
1
0.05
C
10
8
REF (0.36)
0.5
7X
0.205
0.3
0.3
0.945
8X
0.45
0.35
0.2
2X
0.1
C A B
0.1
C A B
0.05
C
0.05
C
4224047/A 01/2018
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
www.ti.com
EXAMPLE BOARD LAYOUT
VQFN-HR - 1 mm max height
PLASTIC QUAD FLAT-NO LEAD
RPA0010A
(1.42)
(0.95)
(1.4)
(0.21)
2X (0.93)
2X (0.4)
10
8
(0.56)
3X (0.25)
1
2X
(2.1)
2X
(0.65)
PKG
(2.8)
(0.85)
(1.7)
4
5X (0.5)
(R0.05) TYP
5
7
7X
(0.6)
(0.37)
8X (0.25)
(0.87)
PKG
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE: 20X
SOLDER MASK
OPENING
0.07 MIN
ALL AROUND
METAL EDGE
EXPOSED METAL
NON SOLDER MASK
DEFINED
4224047/A 01/2018
NOTES: (continued)
3. For more information, see Texas Instruments literature number SLUA271 (www.ti.com/lit/slua271).
4. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
www.ti.com
EXAMPLE STENCIL DESIGN
VQFN-HR - 1 mm max height
PLASTIC QUAD FLAT-NO LEAD
RPA0010A
(1.42)
(0.95)
(1.4)
(0.21)
2X (0.93)
2X (0.4)
METAL
8
10
TYP
2X
(0.56)
(0.95)
1
3X (0.25)
(1.15)
PKG
(2.8)
(0.38)
(0.08)
4
2X (0.75)
(0.95)
5X (0.5)
(R0.05) TYP
5
7
7X
(0.6)
(0.37)
8X (0.25)
(0.87)
PKG
SOLDER PASTE EXAMPLE
BASED ON 0.1 mm THICK STENCIL
EXPOSED PAD
PADS 6 and 9: 89% PRINTED COVERAGE BY
AREA
SCALE: 20X
4224047/A 01/2018
NOTES: (continued)
5.
Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
www.ti.com
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Copyright © 2023，德州仪器 (TI) 公司
相关型号：
TPS568215OARNNR
具有 D-CAP3 控制功能和 Out-of-Audio™ 模式的 4.5V 至 17V、8A 同步 SWIFT™ 降压转换器 | RNN | 18 | -40 to 125
TI
TPS568215OARNNT
具有 D-CAP3 控制功能和 Out-of-Audio™ 模式的 4.5V 至 17V、8A 同步 SWIFT™ 降压转换器 | RNN | 18 | -40 to 125
TI
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