TPS55288-Q1 [TI]
TPS55288-Q1 36-V, 16-A Buck-boost Converter with I2C Interface;型号: | TPS55288-Q1 |
厂家: | TEXAS INSTRUMENTS |
描述: | TPS55288-Q1 36-V, 16-A Buck-boost Converter with I2C Interface |
文件: | 总60页 (文件大小:3870K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
TPS55288-Q1
SLVSFQ7A – DECEMBER 2020 – REVISED DECEMBER 2021
TPS55288-Q1 36-V, 16-A Buck-boost Converter with I2C Interface
1 Features
3 Description
•
AEC-Q100 qualified:
The TPS55288-Q1 is a synchronous four-switch buck-
boost converter capable of regulating the output
voltage at, above, or below the input voltage. The
TPS55288-Q1 operates over 2.7-V to 36-V wide input
voltage and is capable of outputing 0.8-V to 22-V
voltage to support a variety of applications.
– Device temperature grade 1: –40°C to +125°C
ambient operating temperature range
Programmable power supply (PPS) support for
USB power delivery (USB PD)
– Wide input voltage range: 2.7 V to 36 V
– Programmable output voltage range: 0.8 V to
22 V with 20-mV step
– ±1% reference voltage accuracy
– Adjustable output voltage compensation for
voltage droop over the cable
•
The TPS55288-Q1 integrates two 16-A MOSFETs
of the boost leg to balance the solution size and
efficiency. With the programmable output voltage
and output current limit through I2C interface,
the TPS55288-Q1 is fully compliant to the USB
PD specification. The TPS55288-Q1 is capable of
delivering 100 W from 12-V input voltage.
– Programmable output current limit up to 6.35 A
with 50-mA step
– ±5% accurate output current monitoring
– I2C interface
The TPS55288-Q1 employs an average current-
mode control scheme. The switching frequency is
programmable from 200 kHz to 2.2 MHz by an
external resistor and can be synchronized to an
external clock. The TPS55288-Q1 also provides
optional spread spectrum to minimize peak EMI.
•
•
High efficiency over entire load range
– 97% efficiency at VIN = 12 V, VOUT = 20 V and
IOUT = 3 A
– Programmable PFM and FPWM mode at light
load
Avoid frequency interference and crosstalk
– Optional clock synchronization
– Programmable switching frequency from 200
kHz to 2.2 MHz
The TPS55288-Q1 offers output over-voltage
protection, average inductor current limit, cycle-by-
cycle peak current limit and output short circuit
protection. The TPS55288-Q1 also ensures safe
operating with optional output current limit and hiccup-
mode protection in sustained overload conditions.
•
•
EMI mitigation
– Optional programmable spread spectrum
– Lead-less package
The TPS55288-Q1 can use a small inductor and
small capacitors with high switching frequency. It is
available in a 4.0-mm × 3.5-mm QFN package.
Rich protection features
– Output overvoltage protection
– Hiccup mode for output short-circuit protection
– Thermal shutdown protection
– Programmable average inductor current limit up
to 16 A
Device Information
PART NUMBER
PACKAGE(1)
BODY SIZE
TPS55288-Q1
VQFN-HR
4.00 mm × 3.50 mm
•
•
Small solution size
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
– Maximum switching frequency up to 2.2 MHz
– 4.0-mm × 3.5-mm HotRod™ QFN package with
wettable flank option
Create a custom design using the TPS55288-Q1
with the WEBENCH® Power Designer
L1
4.7µH
C5
0.1µF
C4
0.1µF
VIN = 2.7V to 36V
SW1
SW2
BOOT2
DR1H DR1L BOOT1
VIN
VOUT =0.8V to 22V
VOUT
C1
R1
10mΩ
C2
2 Applications
C3
4.7µF
VCC
PGND
AGND
ISP
SCL
•
•
•
USB PD
SDA
ON
EN/UVLO
TPS55288-Q1
Automotive infotainment and cluster
Car charger
ISN
OFF
MODE
FB/INT
COMP
CDC
R6
DITH/SYNC
FSW
C6
R3
C7
R4
C8
ILIM
R5
R2
Typical Application Circuit
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
TPS55288-Q1
SLVSFQ7A – DECEMBER 2020 – REVISED DECEMBER 2021
www.ti.com
Table of Contents
1 Features............................................................................1
2 Applications.....................................................................1
3 Description.......................................................................1
4 Revision History.............................................................. 2
5 Pin Configuration and Functions...................................3
6 Specifications.................................................................. 5
6.1 Absolute Maximum Ratings........................................ 5
6.2 ESD Ratings .............................................................. 5
6.3 Recommended Operating Conditions.........................5
6.4 Thermal Information....................................................6
6.5 Electrical Characteristics.............................................6
6.6 I2C Timing Characteristics.......................................... 9
6.7 Typical Characteristics.............................................. 11
7 Detailed Description......................................................15
7.1 Overview...................................................................15
7.2 Functional Block Diagram.........................................16
7.3 Feature Description...................................................16
7.4 Device Functional Modes..........................................23
7.5 Programming............................................................ 23
7.6 Register Maps...........................................................27
8 Application and Implementation..................................36
8.1 Application Information............................................. 36
8.2 Typical Application.................................................... 36
9 Power Supply Recommendations................................45
10 Layout...........................................................................45
10.1 Layout Guidelines................................................... 45
10.2 Layout Example...................................................... 46
11 Device and Documentation Support..........................47
11.1 Device Support........................................................47
11.2 Receiving Notification of Documentation Updates..47
11.3 Support Resources................................................. 47
11.4 Trademarks............................................................. 47
11.5 Electrostatic Discharge Caution..............................47
11.6 Glossary..................................................................47
12 Mechanical, Packaging, and Orderable
Information.................................................................... 48
4 Revision History
Changes from Revision * (December 2020) to Revision A (December 2021)
Page
•
Added wettable flank option................................................................................................................................1
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5 Pin Configuration and Functions
1
2
19
18
DR1L
DR1H
VCC
COMP
ILIM
3
4
5
6
17
16
15
14
VIN
EN/UVLO
CDC
SCL
MODE
SDA
FB/INT
7
13
DITH/SYNC
ISN
Figure 5-1. 26-pin VQFN-HR, RPM Package (Transparent Top View)
Table 5-1. Pin Functions
PIN
NAME
I/O
DESCRIPTION
NO.
1
DR1L
DR1H
VIN
O
O
Gate driver output for low-side MOSFET in buck side
2
Gate driver output for high-side MOSFET in buck side
Input power supply for the IC
3
PWR
Enable logic input and programmable input voltage undervoltage lockout (UVLO) input. Logic high
level enables the device. Logic low level disables the device and turns it into shutdown mode.
After the voltage at the EN/UVLO pin is above the logic high voltage of 1.15 V, this pin acts as
programmable UVLO input with 1.23-V internal reference.
4
EN/UVLO
I
5
6
SCL
SDA
I
Clock of I2C interface
Data of I2C interface
I/O
Dithering frequency setting and synchronous clock input. Use a capacitor between this pin and
ground to set the dithering frequency. When this pin is short to ground or pulled above 1.2 V, there
is no dithering function. An external clock can be applied at this pin to synchronize the switching
frequency.
7
DITH/SYNC
I
8
FSW
PGND
AGND
VOUT
O
The switching frequency is programmed by a resistor between this pin and the AGND pin.
Power ground of the IC. It is connected to the source of the low-side MOSFET.
Signal ground of the IC
9, 24
10
PWR
PWR
PWR
11, 26
Output of the buck-boost converter
Positive input of the current sense amplifier. An optional current sense resistor connected between
the ISP pin and the ISN pin can limit the output current. If the sensed voltage reaches the current
limit setting value in the register, a slow constant current control loop becomes active and starts to
regulate the voltage between the ISP pin and the ISN pin. Connecting the ISP pin and the ISN pin
together with the VOUT pin can disable the output current limit function.
12
ISP
I
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Table 5-1. Pin Functions (continued)
PIN
NAME
I/O
DESCRIPTION
NO.
Negative input of the current sense amplifier. An optional current sense resistor connected between
the ISP pin and the ISN pin can limit the output current. If the sensed voltage reaches the current
limit setting value in the register, a slow constant current control loop becomes active and starts to
regulate the voltage between the ISP pin and the ISN pin. Connecting the ISP pin and the ISN pin
together with the VOUT pin can disable the output current limit function.
13
ISN
I
When the device is set to use external output voltage feedback, connect to the center tap of a
resistor divider to program the output voltage. When the device is set to use internal feedback, this
pin is a fault indicator output. When there is an internal fault happening, this pin outputs logic low
level.
14
FB/INT
I/O
Set the operation modes of the TPS55288-Q1 by a resistor between this pin and AGND to select
PFM mode, forced PWM mode in light load condition to select the internal LDO, or external 5 V for
VCC, and to select different I2C address.
15
16
MODE
CDC
I
Voltage output proportional to the sensed voltage between the ISP pin and the ISN pin. Use a
resistor between this pin and AGND to increase the output voltage to compensate voltage droop
across the cable caused by the cable resistance.
O
Average inductor current limit setting pin. Connect an external resistor between this pin and the
AGND pin.
17
ILIM
COMP
VCC
O
I
Output of the internal error amplifier. Connect the loop compensation network between this pin and
the AGND pin.
18
Output of the internal regulator. A ceramic capacitor of more than 4.7 μF is required between this pin
and the AGND pin.
19
O
O
I
Power supply for high-side MOSFET gate driver in boost side. A ceramic capacitor of 0.1 µF must be
connected between this pin and the SW2 pin.
20
BOOT2
SW2
The switching node pin of the boost side. It is connected to the drain of the internal low-side power
MOSFET and the source of internal high-side power MOSFET.
21, 25
22
Power supply for high-side MOSFET gate driver in buck side. A ceramic capacitor of 0.1 µF must be
connected between this pin and the SW1 pin.
BOOT1
SW1
I
The switching node pin of the buck side. It is connected to the drain of the external low-side power
MOSFET and the source of external high-side power MOSFET.
23
I
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6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)(1)
MIN
–0.3
MAX
40
UNIT
V
VIN, SW1
DRH1, BOOT1
SW1–0.3
SW1+6
V
VCC, DRL1, SCL, SDA, ILIM, FSW, COMP, FB/INT, MODE,
CDC, DITH/SYNC
–0.3
6
V
VOUT, SW2, ISP, ISN
–0.3
VOUT-6
-0.3
25
VOUT+6
20
V
V
V
V
Voltage range
at terminals(2)
ISP, ISN
EN
BOOT2
SW2–0.3
SW2+6
DRL1, SCL, SDA, ILIM, FSW, COMP, FB/INT, MODE, CDC, DITH/
SYNC
–0.3
VCC+0.3
V
(3)
TJ
Operating Junction, TJ
–40
–65
150
150
°C
°C
Tstg
Storage temperature
(1) Stresses beyond those listed under Absolute Maximum Rating may cause permanent damage to the device. These are stress
ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated
under Recommended Operating Condition. Exposure to absolute-maximum-rated conditions for extended periods may affect device
reliability.
(2) All voltage values are with respect to network ground terminal.
(3) High junction temperatures degrade operating lifetimes. Operating lifetime is de-rated for junction temperatures greater than 125°C.
6.2 ESD Ratings
VALUE
±2000
±500
UNIT
V
Human-body model (HBM), per AEC Q100-002(2)
(1)
(1)
V(ESD)
V(ESD)
Electrostatic discharge
Electrostatic discharge
Charged-device model (CDM), per AEC Q100-011, all pins(3)
Charged-device model (CDM), per AEC Q100-011, corner pins(3)
±750
V
(1) Electrostatic discharge (ESD) to measure device sensitivity and immunity to damage caused by assembly line electrostatic discharges
in to the device.
(2) Level listed above is the passing level per ANSI, ESDA, and JEDEC JS-001. JEDEC document JEP155 states that 500-V HBM allows
safe manufacturing with a standard ESD control process. Manufacturing with less than 500-V HBM is possible with the necessary
precautions.
(3) Level listed above is the passing level per EIA-JEDEC JESD22-C101. JEDEC document JEP157 states that 250-V CDM allows
safe manufacturing with a standard ESD control process. Manufacturing with less than 250-V CDM is possible with the necessary
precautions.
6.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
MIN
2.7
0.8
0.7
4.7
10
NOM
MAX
36
UNIT
V
VIN
VOUT
L
Input voltage range
Output voltage range
22
V
Effective inductance range
Effective input capacitance range
Effective output capacitance range
Operating junction temperature
4.7
22
13
µH
µF
µF
°C
CIN
COUT
TJ
100
1000
150
–40
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6.4 Thermal Information
TPS55288-Q1
TPS55288-Q1
THERMAL METRIC(1)
VQFN-HR (RPM)-26 PINS VQFN-HR (RPM)-26 PINS
UNIT
Standard
47.5
23.8
12.8
0.5
EVM(2)
25.8
N/A
RθJA
Junction-to-ambient thermal resistance
Junction-to-case (top) thermal resistance
Junction-to-board thermal resistance
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
RθJC(top)
RθJB
N/A
ΨJT
Junction-to-top characterization parameter
Junction-to-board characterization parameter
Junction-to-case (bottom) thermal resistance
0.6
ΨJB
12.7
7.8
11.6
N/A
RθJC(bot)
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
(2) Measured on TPS55288-Q1EVM-045, 4-layer, 2-oz/2-oz/2-oz/2-oz copper 112-mm×71-mm PCB.
6.5 Electrical Characteristics
TJ = -40°C to 125°C, VIN = 12 V and VOUT = 20 V. Typical values are at TJ = 25°C, unless otherwise noted.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
POWER SUPPLY
VIN
Input voltage range
2.7
2.8
2.6
36
3.0
2.7
V
V
V
VIN rising
2.9
VVIN_UVLO
Under voltage lockout threshold
VIN falling
2.65
IC enabled, no load, no switching. VIN
= 3 V to 24 V, VOUT = 0.8 V, VFB
VREF + 0.1 V, RFSW = 100 kΩ, TJ up to
125°C
=
Quiescent current into the VIN pin
Quiescent current into the VOUT pin
760
860
µA
IQ
IC enabled, no load, no switching, VIN
= 2.9 V, VOUT = 3 V to 20 V, VFB
VREF + 0.1 V, RFSW = 100 kΩ, TJ up to
125°C
=
760
6.8
860
10
µA
µA
IC disabled, VIN = 2.9 V to 14 V, TJ up
to 125°C
ISD
Shutdown current into the VIN pin
Internal regulator output
VCC
IVCC = 50 mA, VIN = 8 V, VOUT = 20 V
VIN = 5.0 V, VOUT = 20 V, IVCC = 60 mA
VIN = 14 V, VOUT = 5.0 V, IVCC = 60 mA
5.0
5.2
200
110
5.4
320
170
V
mV
mV
VCC_DO
VCC dropout
EN/UVLO
VEN_H
EN Logic high threshold
EN Logic low threshold
Enable threshold hysteresis
VCC = 2.7 V to 5.5 V
VCC = 2.7 V to 5.5 V
VCC = 2.7 V to 5.5 V
1.15
V
V
V
VEN_L
0.4
VEN_HYS
0.05
0.12
1.23
UVLO rising threshold at the EN/UVLO
pin
VUVLO
VCC = 3.0 V to 5.5 V
VCC = 3.0 V to 5.5 V
1.20
1.26
V
VUVLO_HYS
IUVLO
UVLO threshold hysteresis
8
14
5
20
mV
µA
Sourcing current at the EN/UVLO pin VEN/UVLO = 1.3 V
4.5
5.5
OUTPUT
VOUT
Output voltage range
0.8
22
V
V
Output overvoltage protection
threshold
VOVP
22.5
23.5
1
24.5
VOVP_HYS
IFB_LKG
Over voltage protection hysteresis
V
Leakage current at the FB pin
TJ up to 125°C
100
20
nA
IC disabled, VOUT = 20 V, VSW2 = 0 V,
TJ up to 125°C
IVOUT_LKG
Leakage current into the VOUT pin
1
µA
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6.5 Electrical Characteristics (continued)
TJ = -40°C to 125°C, VIN = 12 V and VOUT = 20 V. Typical values are at TJ = 25°C, unless otherwise noted.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
IDISCHG
Output discharge current
VOUT = 20 V, VCC = 5.2 V
40
100
170
mA
INTERNAL REFERENCE DAC
Resolution of reference voltage DAC
Integral non-linearity
10
bits
LSB
LSB
INL
–4
–1
4
2
DNL
Differential non-linearity
VOUT_FS=03h, REF=03C0h, VREF
1.129 V
=
19.7
14.78
9.85
4.93
0.74
0.56
0.37
0.18
20
15
10
5
20.3
15.22
10.15
5.07
V
V
V
V
V
V
V
V
VOUT_FS=02h, REF=03C0h,
VREF=1.129V
Output voltage when VREF is set to
1.129V
VOUT_FULL
VOUT_FS=01h, REF=03C0h, VREF
1.129 V
=
=
VOUT_FS=00h, REF=03C0h, VREF
1.129 V
VOUT_FS=03h, REF=0000h, VREF
45 mV
=
0.8
0.6
0.4
0.2
0.86
VOUT_FS=02h, REF=0000h, VREF
45 mV
=
=
=
0.64
Output voltage when VREF is set to
45mV
VOUT_ZERO
VOUT_FS=01h, REF=0000h, VREF
45 mV
0.43
VOUT_FS=00h, REF=0000h, VREF
45 mV
0.22
REFERENCE VOLTAGE
External feedback with REF=03C0h
External feedback with REF=02C6h
External feedback with REF=019Ah
External feedback with REF=00D2h
1.117
0.837
0.502
0.276
1.129
0.846
0.508
0.282
1.141
0.855
0.514
0.288
V
V
V
V
Reference voltage at the FB/INT pin
when using external feedback
VREF
POWER SWITCH
Low-side MOSFET on resistance on
VOUT = 20 V, VCC= 5.2 V
VOUT = 20 V, VCC= 5.2 V
7.1
7.6
mΩ
mΩ
boost side
RDS(on)
High-side MOSFET on resistance on
boost side
INTERNAL CLOCK
RFSW = 100 kΩ
RFSW = 9.09 kΩ
Boost mode
180
200
2200
100
90
220
2400
145
kHz
kHz
ns
fSW
Switching frequency
2000
tOFF_min
tON_min
VFSW
Min. off time
Min. on time
Buck mode
130
ns
Voltage at the FSW pin
1
V
CURRENT LIMIT
RILIM = 20 kΩ, VIN = 8 V, VOUT = 20 V,
fSW = 400 kHz, FPWM
14
14
4
16.5
16.5
5.5
19
19
A
A
A
A
RILIM = 20 kΩ, VIN = 8 V, VOUT = 20 V,
fSW = 400 kHz, PFM
ILIM_AVG
Average inductor current limit
RILIM = 60 kΩ, VIN = 5 V, VOUT = 14 V,
fSW = 2.2 MHz, FPWM
RILIM = 60 kΩ, VIN = 5 V, VOUT = 14 V,
fSW = 2.2 MHz, PFM
4
5.5
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6.5 Electrical Characteristics (continued)
TJ = -40°C to 125°C, VIN = 12 V and VOUT = 20 V. Typical values are at TJ = 25°C, unless otherwise noted.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
RILIM = 20 kΩ, VIN = 8 V, VOUT = 20 V,
fSW = 400 kHz, FPWM
25
A
ILIM_PK
Peak inductor current limit at high side
Voltage at the ILIM pin
RILIM = 20 kΩ, VIN = 8 V, VOUT = 20 V,
fSW = 400 kHz, PFM
25
0.6
50
A
V
VILIM
VOUT = 3 V
VISN = 2 V to 21 V,IOUT_LIMIT
Register = 11100100b
48
28
52
32
mV
Current loop regulation voltage
between the ISP and ISN pins
VSNS
VISN = 2 V to 21 V,IOUT_LIMIT
Register = 10111100b
30
mV
CABLE VOLTAGE DROOP COMPENSATION
RCDC = 20 kΩ or floating, VISP – VISN
50 mV
=
0.95
650
70
1
40
1.05
75
V
VCDC
Voltage at the CDC pin
RCDC = 20 kΩ or floating, VISP – VISN
2 mV
=
mV
mV
mV
mV
mV
µA
Internal output feedback,
CDC[2:0]=111, VISP – VISN = 50 mV
700
30
750
60
Internal output feedback,
CDC[2:0]=111, VISP – VISN = 2 mV
VOUT increase for cable droop
compensation
VOUT_CDC
Internal output feedback,
CDC[2:0]=001, VISP – VISN = 50 mV
100
20
130
40
Internal output feedback,
CDC[2:0]=001, VISP – VISN = 10 mV
External output feedback, RCDC
20kΩ, VISP – VISN = 50 mV
=
7.23
7.5
0.05
0
7.87
0.32
0.3
External output feedback, RCDC = 20
kΩ, VISP – VISN = 0 mV
IFB_CDC
FB/INT pin sinking current
µA
External output feedback, RCDC
floating, VISP – VISN = 50 mV
=
µA
ERROR AMPLIFIER
VFB = VREF + 400 mV, VCOMP = 1.5 V,
VCC = 5 V
ISINK
COMP pin sink current
20
60
µA
µA
VFB = VREF - 400 mV, VCOMP = 1.5 V,
VCC = 5 V
ISOURCE
COMP pin source current
VCCLPH
VCCLPL
GEA
High clamp voltage at the COMP pin
Low clamp voltage at the COMP pin
Error amplifier transconductance
1.8
0.7
V
V
190
µA/V
SOFT START
tSS
Soft-start time
3
4
5
ms
DR1H GATE DRIVER
VDR1H_L Low-state voltage drop
VDR1H_H High-state voltage drop
DR1L GATE DRIVER
VDR1L_L Low-state voltage drop
VDR1L_H High-state voltage drop
SPREAD SPECTRUM
VDR1H – VSW1, 100-mA sinking
0.1
0.2
V
V
VBOOT1 – VDR1H, 100-mA sourcing
100-mA sinking
0.1
0.2
V
V
VCC – VDR1L, 100-mA sourcing
VDITH/SYNC = 1.0 V, RFSW = 49.9 kΩ,
voltage rising from 0.85 V
IDITH_CHG
Dithering charge current
2
µA
VDITH/SYNC = 1.0 V, RFSW = 49.9 kΩ,
voltage falling from 1.15 V
IDITH_DIS
VDITH_H
Dithering discharge current
Dither high threshold
2
µA
V
1.07
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6.5 Electrical Characteristics (continued)
TJ = -40°C to 125°C, VIN = 12 V and VOUT = 20 V. Typical values are at TJ = 25°C, unless otherwise noted.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
VDITH_L
Dither low threshold
0.93
V
SYNCHRONOUS CLOCK
VSNYC_H
VSYNC_L
tSYNC_MIN
HICCUP
tHICCUP
Sync clock high voltage threshold
1.2
V
V
Sync clock low voltage threshold
Minimum sync clock pulse width
0.4
50
ns
Hiccup off time
76
ms
MODE RESISTANCE DETECTION
IMODE
Sourcing current from the MODE pin
VMODE = 2.5 V
9
1.147
0.824
0.571
0.321
0.168
0.080
0.014
10
1.220
0.88
11
1.293
0.936
0.657
0.381
0.210
0.114
0.040
µA
V
VMODE_DT1
VMODE_DT2
VMODE_DT3
VMODE_DT4
VMODE_DT5
VMODE_DT6
VMODE_DT7
V
0.614
0.351
0.189
0.097
0.027
V
Detection threshold voltage at the
MODE pin
V
V
V
V
LOGIC INTERFACE
VI2C_IO
VI2C_H
VI2C_L
IO voltage range for I2C
1.7
0.4
5.5
1.2
V
V
V
I2C input high threshold
I2C input low threshold
VCC = 2.7 V to 5.5 V
VCC = 2.7 V to 5.5 V
Leakage current into FB/INT pin when
outputting high impedance
IFB/INT_H
VFB/INT_L
VFB/INT = 5 V
100
0.1
nA
V
Output low voltage range of the FB/
INT pin
Sinking 4-mA current
0.03
PROTECTION
TSD
Thermal shutdown threshold
Thermal shutdown hysteresis
TJ rising
175
20
°C
°C
TSD_HYS
TJ falling below TSD
6.6 I2C Timing Characteristics
TJ = -40°C to 125°C, VIN = 12 V and VOUT = 20 V. Typical values are at TJ = 25°C, unless otherwise noted.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
I2C TIMING
fSCL
SCL clock frequency
100
0.5
1000
kHz
µs
Bus free time between a STOP and
START condition
tBUF
Fast mode plus
tHD(STA)
tLOW
Hold time (repeated) START condition
Low period of the SCL clock
260
0.5
ns
µs
ns
tHIGH
High period of the SCL clock
260
Setup time for a repeated START
condition
tSU(STA)
260
ns
tSU(DAT)
tHD(DAT)
tRCL
Data setup time
50
0
ns
µs
ns
Data hold time
Rise time of SCL signal
120
120
Rise time of SCL signal after a
repeated START condition and after
an ACK bit
tRCL1
ns
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TJ = -40°C to 125°C, VIN = 12 V and VOUT = 20 V. Typical values are at TJ = 25°C, unless otherwise noted.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
120
120
120
UNIT
ns
tFCL
Fall time of SCL signal
tRDA
tFDA
tSU(STO)
CB
Rise time of SDA signal
Fall time of SDA signal
ns
ns
Setup time of STOP condition
Capacitive load for SDA and SCL
260
ns
200
pF
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6.7 Typical Characteristics
VIN = 12 V, TA = 25°C, fSW = 400 kHz, unless otherwise noted.
100%
90%
80%
70%
60%
50%
40%
100%
90%
80%
70%
60%
50%
40%
30%
20%
10%
0
30%
VIN = 5 V
VIN = 9 V
VIN = 12 V
VIN = 20 V
VIN = 5 V
VIN = 9 V
VIN = 12 V
VIN = 20 V
20%
10%
0
0.0001
0.001
0.01 0.1 0.2 0.5
Output Current (A)
1
2 3 5 710
0.0001
0.001
0.01 0.1 0.2 0.5
Output Current (A)
1
2 3 5 710
D001
D002
Figure 6-1. Efficiency vs Output Current,
VOUT = 5 V, FPWM
Figure 6-2. Efficiency vs Output Current,
VOUT = 5 V, PFM
100%
100%
90%
80%
70%
60%
50%
40%
30%
20%
10%
0
90%
80%
70%
60%
50%
40%
30%
20%
10%
0
VIN = 5 V
VIN = 9 V
VIN = 12 V
VIN = 20 V
VIN = 5 V
VIN = 9 V
VIN = 12 V
VIN = 20 V
0.0001
0.001
0.01 0.1 0.2 0.5
Output Current (A)
1
2 3 5 710
0.0001
0.001
0.01 0.1 0.2 0.5
Output Current (A)
1
2 3 5 710
D003
D004
Figure 6-3. Efficiency vs Output Current,
VOUT = 9 V, FPWM
Figure 6-4. Efficiency vs Output Current,
VOUT = 9 V, PFM
100%
100%
90%
80%
70%
60%
50%
40%
30%
20%
10%
0
90%
80%
70%
60%
50%
40%
30%
20%
10%
0
VIN = 5 V
VIN = 9 V
VIN = 12 V
VIN = 20 V
VIN = 5 V
VIN = 9 V
VIN = 12 V
VIN = 20 V
0.0001
0.001
0.01 0.1 0.2 0.5
Output Current (A)
1
2 3 5 710
0.0001
0.001
0.01 0.1 0.2 0.5
Output Current (A)
1
2 3 5 710
D005
D006
Figure 6-5. Efficiency vs Output Current,
VOUT = 12 V, FPWM
Figure 6-6. Efficiency vs Output Current,
VOUT = 12 V, PFM
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100%
90%
80%
70%
60%
50%
40%
30%
20%
10%
0
100%
90%
80%
70%
60%
50%
40%
30%
20%
10%
0
VIN = 5 V
VIN = 9 V
VIN = 12 V
VIN = 20 V
VIN = 5 V
VIN = 9 V
VIN = 12 V
VIN = 20 V
0.0001
0.001
0.01 0.1 0.2 0.5
Output Current (A)
1
2 3 5 710
0.0001
0.001
0.01 0.1 0.2 0.5
Output Current (A)
1
2 3 5 710
D007
D008
Figure 6-7. Efficiency vs Output Current,
VOUT = 15 V, FPWM
Figure 6-8. Efficiency vs Output Current,
VOUT = 15 V, PFM
100%
100%
90%
80%
70%
60%
50%
40%
30%
20%
10%
0
90%
80%
70%
60%
50%
40%
30%
20%
10%
0
VIN = 5 V
VIN = 9 V
VIN = 12 V
VIN = 20 V
VIN = 5 V
VIN = 9 V
VIN = 12 V
VIN = 20 V
0.0001
0.001
0.01 0.1 0.2 0.5
Output Current (A)
1
2 3 5 710
0.0001
0.001
0.01 0.1 0.2 0.5
Output Current (A)
1
2 3 5 710
D009
D010
Figure 6-9. Efficiency vs Output Current,
VOUT = 20 V, FPWM
Figure 6-10. Efficiency vs Output Current,
VOUT = 20 V, PFM
18
2200
2000
1800
1600
1400
1200
1000
800
VIN = 20 V, VOUT = 5 V
VIN = 12 V, VOUT = 12 V
VIN = 5 V, VOUT = 20 V
17
16
15
14
13
12
11
10
9
8
7
600
6
5
400
4
200
3
2
0
20
30
40
50
60
70
80
90
100
0
10
20
30
40
50
60
70
80
90 100
Resistance (kW)
Resistance (kW)
Figure 6-11. Average Inductor Current Limit vs
Setting Resistance
Figure 6-12. Switching Frequency vs Setting
Resistance
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0.2865
0.514
0.512
0.51
0.285
0.2835
0.282
0.508
0.506
0.504
0.502
0.2805
0.279
0.2775
-40
-20
0
20
40
60
80
100 120 140
-40
-20
0
20
40
60
80
100 120 140
Temperature (èC)
Temperature (èC)
D013
D014
Figure 6-13. Reference Voltage vs Temperature
(VREF = 0.282 V)
Figure 6-14. Reference Voltage vs Temperature
(VREF = 0.508 V)
0.855
0.852
0.849
0.846
0.843
0.84
1.146
1.14
1.134
1.128
1.122
1.116
1.11
0.837
-40
-20
0
20
40
60
80
100 120 140
-40
-20
0
20
40
60
80
100 120 140
Temperature (èC)
Temperature (èC)
D015
D016
Figure 6-15. Reference Voltage vs Temperature
(VREF = 0.846 V)
Figure 6-16. Reference Voltage vs Temperature
(VREF = 1.129 V)
780
775
770
765
760
755
7.5
7.25
7
6.75
6.5
6.25
6
750
Into VIN, VIN = 24 V, VOUT = 3 V
Into VOUT, VIN = 3.1 V, VIN = 20 V
745
-40
5.75
-20
0
20
40
60
80
100 120 140
-40
-20
0
20
40
60
80
100 120 140
Temperature (èC)
Temperature (èC)
D017
D018
Figure 6-17. Quiescent Current vs Temperature
Figure 6-18. Shutdown Current vs Temperature
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1.2355
1.235
1.2345
1.234
1.2335
1.233
1.2325
1.232
1.2315
1.231
1.2305
1.23
2500
2000
1500
1000
500
fSW = 200 kHz
fSW = 2200 kHz
0
-40
-20
0
20
40
60
80
100 120 140
-40
-20
0
20
40
60
80
100 120 140
Temperature (èC)
Temperature (èC)
D019
D020
Figure 6-19. ENABLE/UVLO Rising Threshold vs
Temperature
Figure 6-20. Switching Frequency vs Temperature
1.6
1.4
1.2
1
0.8
0.6
0.4
0.2
0
0
1
2
3
4
5
Output Current (A)
6
7
8
D021
Figure 6-21. CDC Voltage vs Output Current with RSENSE = 10 mΩ
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7 Detailed Description
7.1 Overview
The TPS55288-Q1 is a 16-A buck-boost DC-to-DC converter with the two boost MOSFETs integrated. The
TPS55288-Q1 can operate over a wide range of 2.7-V to 36-V input voltage and an output voltage of 0.8 V to
22 V. It can transition among buck mode, buck-boost mode, and boost mode smoothly according to the input
voltage and the set output voltage. The TPS55288-Q1 operates in buck mode when the input voltage is greater
than the output voltage and in boost mode when the input voltage is less than the output voltage. When the input
voltage is close to the output voltage, the TPS55288-Q1 operates in one-cycle buck and one-cycle boost mode
alternately.
The TPS55288-Q1 uses an average current mode control scheme. Current mode control provides simplified
loop compensation, rapid response to the load transients, and inherent line voltage rejection. An error amplifier
compares the feedback voltage with the internal reference voltage. The output of the error amplifier determines
the average inductor current.
An internal oscillator can be configured to operate over a wide range of frequency from 200 kHz to 2.2 MHz. The
internal oscillator can also synchronize to an external clock applied to the DITH/SYNC pin. To minimize EMI, the
TPS55288-Q1 can dither the switching frequency at ±7% of the set frequency.
The TPS55288-Q1 works in fixed-frequency PWM mode at moderate to heavy load currents. In light load
condition, the TPS55288-Q1 can be configured to automatically transition to PFM mode or be forced in PWM
mode by either connecting a resistor at the MODE pin or setting the corresponding bit in an internal register.
The output voltage of the TPS55288-Q1 is adjustable by setting the internal register through I2C interface. An
internal 10-bit DAC adjusts the reference voltage related to the value written into the REF register. The device
can also limit the output current by placing a current sense resistor in the output path. These two functions
support the programmable power supply (PPS) feature of the USB PD.
The TPS55288-Q1 provides average inductor current limit set by a resistor at the ILIM pin. In addition, it provides
cycle-by-cycle peak inductor current limit during transient to protect the device against overcurrent condition
beyond the capability of the device.
A precision voltage threshold of 1.23 V with 5-µA sourcing current at the EN/UVLO pin supports programmable
input undervoltage lockout (UVLO) with hysteresis. The output overvoltage protection (OVP) feature turns off the
high-side FETs to prevent damage to the devices powered by the TPS55288-Q1.
The device provides hiccup mode option to reduce the heating in the power components when output short
circuit happens. When the hiccup mode is enabled, the TPS55288-Q1 turns off for 76 ms and restarts at soft
start-up.
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7.2 Functional Block Diagram
L1
VIN
C3
BOOT1
C4
C8
SW1
BOOT2
SW2
R1
VOUT
VOUT
C2
VIN
VOUT
LDO
Current
Sense
C1
VCC
CDC
R7
I-V
C5
DL
I_limit
ISP
ISN
Buck-Boost
Control
DH
Iref
FB/INT
COMP
Gm
Gm
MODE
ADC
BOOST
BUCK
R3
R2
C6
Vref
DAC
SDA
SCL
PGND
AGND
ILIM
Logic Core
EN/UVLO
Iref
Vref
DAC
VSYNC/DITH
1.0V
I_limit
VIN
VCC
VIN UVLO
VOUT OVP
Thermal
FSW
VOUT
R5
fMOD
R4
DITH/SYNC
C7
7.3 Feature Description
7.3.1 VCC Power Supply
An internal LDO to supply the TPS55288-Q1 outputs regulated 5.2-V voltage at the VCC pin with 60-mA output
current capability. When VIN is less than VOUT, the internal LDO selects the power supply source by comparing
VIN to a rising threshold of 6.2 V with 0.3-V hysteresis. When VIN is higher than 6.2 V, the supply for LDO is VIN.
When VIN is lower than 5.9 V, the supply for LDO is VOUT. When VOUT is less than VIN, the internal LDO selects
the power supply source by comparing VOUT to a rising threshold of 6.2 V with 0.3-V hysteresis. When VOUT is
higher than 6.2 V, the supply for LDO is VOUT. When VOUT is lower than 5.9 V, the supply for LDO is VIN. Table
7-1 shows the supply source selection for the internal LDO.
Table 7-1. VCC Power Supply Logic
VIN
VOUT
INPUT for VCC LDO
VIN > 6.2 V
VIN < 5.9 V
VIN > VOUT
VIN > VOUT
VOUT > VIN
VOUT > VIN
VOUT > 6.2 V
VOUT < 5.9 V
VIN
VOUT
VOUT
VIN
To minimize the power dissipation of the internal LDO when both input voltage and output voltage are high, an
external 5-V power source can be applied at the VCC pin to supply the TPS55288-Q1. The external 5-V power
supply must have at least 100-mA output current capability and must be within the 4.75-V to 5.5-V regulation
range. To use an external power supply for VCC, a resistor with proper resistance must be connected to the
MODE pin.
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7.3.2 Operation Mode Setting
By placing different resistors between the MODE pin and AGND pin, the TPS55288-Q1 selects the internal
power supply or external power supply for VCC, selects one of two different I2C addresses, and selects the PFM
mode or the forced PWM mode in light load conditions. Table 7-2 shows the resistance values for each selection.
After the TPS55288-Q1 is enabled, an I2C master device can control these three operating modes by writing the
corresponding value into the internal registers regardless the resistance settings at the MODE pin. See details in
Section 7.6.
Table 7-2. VCC Source, I2C Slave Address and PFM/PWM Programming
RESISTOR VALUE
(kΩ)
OPERATING MODE AT LIGHT
LOAD
VCC SOURCE
I2C SLAVE ADDRESS
0
Internal
Internal
Internal
Internal
External
External
External
External
74h
74h
75h
75h
74h
74h
75h
75h
PWM
PFM
PWM
PFM
PWM
PFM
PWM
PFM
6.19
14.3
24.9
51.1
75.0
105
Open
7.3.3 Input Undervoltage Lockout
When the input voltage is below 2.6 V, the TPS55288-Q1 is disabled. When the input voltage is above 3 V, the
TPS55288-Q1 can be enabled by pulling the EN pin to a high voltage above 1.3 V.
7.3.4 Enable and Programmable UVLO
The TPS55288-Q1 has a dual function enable and undervoltage lockout (UVLO) circuit. When the input voltage
at the VIN pin is above the input UVLO rising threshold of 3 V and the EN/UVLO pin is pulled above 1.15 V
but less than the enable UVLO threshold of 1.23 V, the TPS55288-Q1 is enabled but still in standby mode. The
TPS55288-Q1 starts to detect the resistance between the MODE pin and ground. After that, the TPS55288-Q1
selects the power supply for VCC, the I2C slave address, and the PFM or FPWM mode for light load condition
accordingly.
The EN/UVLO pin has an accurate UVLO voltage threshold to support programmable input undervoltage lockout
with hysteresis. When the EN/UVLO pin voltage is greater than the UVLO threshold of 1.23 V, the TPS55288-Q1
is enabled for I2C communication and switching operation. A hysteresis current IUVLO_HYS is sourced out of
the EN/UVLO pin to provide hysteresis that prevents on/off chattering in the presence of noise with a slowly
changing input voltage.
By using resistor divider as shown in Figure 7-1, the turnon threshold is calculated using Equation 1.
R1
8
= 8
× (1 +
)
+0(78.1 _10)
78.1
42
(1)
where
VUVLO is the UVLO threshold of 1.23 V at the EN/UVLO pin
•
The hysteresis between the UVLO turnon threshold and turnoff threshold is set by the upper resistor in the
EN/UVLO resistor divider and is given by the Equation 2.
¿8
= +78.1_*;5 × 41
+0(78.1)
(2)
where
•
IUVLO_HYS is the sourcing current from the EN/UVLO pin when the voltage at the EN/UVLO pin is above
VUVLO
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VIN
IUVLO_HYS
R1
EN/UVLO
Enable
R2
C1
UVLO Comparator
1.23V
Figure 7-1. Programmable UVLO With Resistor Divider at the EN/UVLO Pin
Using an NMOSFET together with a resistor divider can implement both logic enable and programmable UVLO
as shown in Figure 7-2. The EN logic high level must be greater than enable threshold plus the Vth of the
NMOSFET Q1. The Q1 also eliminates the leakage current from VIN to ground through the UVLO resistor
divider during shutdown mode.
VIN
R1
IUVLO_HYS
EN
EN/UVLO
Enable
R2
C1
UVLO Comparator
1.23V
Figure 7-2. Logic Enable and Programmable UVLO
7.3.5 Soft Start
When the input voltage is above the UVLO threshold and the voltage at the EN/UVLO pin is above the enable
UVLO threshold, the TPS55288-Q1 is ready to accept the command from I2C master device. An I2C master
device can configure the internal registers of the TPS55288-Q1 before setting the OE bit of the register 06h.
Once an I2C master device sets the OE bit to 1, the TPS55288-Q1 starts to ramp up the output voltage by
ramping an internal reference voltage from 0 V to a voltage set in the internal registers 00h and 01h within typical
4 ms.
7.3.6 Shutdown and Load Discharge
When the EN/UVLO pin voltage is pulled below 0.4 V, the TPS55288-Q1 is in shutdown mode, and all functions
are disabled. All internal registers are reset to default values.
When the EN/UVLO pin is at high logic level and the OE bit is cleared to 0, the TPS55288-Q1 turns off the
switching operation but keeps the I2C interface active. Simultaneously, if the DISCHG bit in the register 06h is
set to 1, the TPS55288-Q1 discharges the output voltage below 0.8 V by an internal constant current.
7.3.7 Switching Frequency
The TPS55288-Q1 uses a fixed frequency average current control scheme. The switching frequency is between
200 kHz and 2.2 MHz set by placing a resistor at the FSW pin. An internal amplifier holds this pin at a fixed
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voltage of 1 V. The setting resistance is between maximum of 100 kΩ and minimum of 9.09 kΩ. Use Equation 3
to calculate the resistance by a given switching frequency.
1000
B
=
(MHz)
59
0.05 × 4(59 + 20
(3)
where
RFSW is the resistance at the FSW pin
•
For noise-sensitive applications, the TPS55288-Q1 can be synchronized to an external clock signal applied to
the DITH/SYNC pin. The duty cycle of the external clock is recommended in the range of 30% to 70%. A resistor
also must be connected to the FSW pin when the TPS55288-Q1 is switching by the external clock. The external
clock frequency at the DITH/SYNC pin must have lower than 0.4-V low level voltage and must be within ±30% of
the corresponding frequency set by the resistor. Figure 7-3 is a recommended configuration.
External Clock
DITH/SYNC
FSW
RFSW
Figure 7-3. External Clock Configuration
7.3.8 Switching Frequency Dithering
The TPS55288-Q1 provides an optional switching frequency dithering that is enabled by connecting a capacitor
from the DITH/SYNC pin to ground. Figure 7-4 illustrates the dithering circuit. By charging and discharging the
capacitor, a triangular waveform centered at 1 V is generated at the DITH/SYNC pin. The triangular waveform
modulates the oscillator frequency by ±7% of the nominal frequency set by the resistance at the FSW pin. The
capacitance at the DITH/SYNC pin sets the modulation frequency. A small capacitance modulates the oscillator
frequency at a fast rate than a large capacitance. For the dithering circuit to effectively reduce peak EMI, the
modulation rate normally is below 1 kHz. Equation 4 calculates the capacitance required to set the modulation
frequency, FMOD
.
1
%
=
(()
&+6*
2.8 × 4(59 × (/1&
(4)
where
•
•
RFSW is the switching frequency setting resistance (Ω) at the FSW pin
FMOD is the modulation frequency (Hz) of the dithering
Connecting the DITH/SYNC pin below 0.4 V or above 1.2 V disables switching frequency dithering. The dithering
function also is disabled when an external synchronous clock is used.
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1.07V
1.0V
0.93V
DITH/SYNC
CDITH
FMOD
FSW
RFSW
Figure 7-4. Switching Frequency Dithering
7.3.9 Inductor Current Limit
The TPS55288-Q1 implements both peak current and average inductor current limit by a resistor connected
to the ILIM pin. The average current mode control loop uses the current sense information at the high-side
MOSFET of the boost leg to clamp the maximum average inductor current to 16.5 A (typical) when the resistor
is 20 kΩ. Use large resistance to get smaller average inductor current limit. Use Equation 5 to calculate the
resistance for a desired average inductor current limit.
min(1,0.6 ×8176 )× 330000
+
=
(#)
#8)_.+/+6
4+.+/
(5)
where
•
•
IAVG_LIMIT is the average inductor current limit
RILIM is the resistance (Ω) between the ILIM pin and analog ground
Besides the average current limit, a peak current limit protection is implemented during transient to protect the
device against over current condition beyond the capability of the device.
7.3.10 Internal Charge Path
Each of the two high-side MOSFET drivers is biased from its floating bootstrap capacitor, which is normally
re-charged by VCC through both the external and internal bootstrap diodes when the low-side MOSFET is turned
on. When the TPS55288-Q1 operates exclusively in the buck or boost regions, one of the high-side MOSFETs is
constantly on. An internal charge path, from VOUT and BOOT2 to BOOT1 or from VIN and BOOT1 to BOOT2,
charges the bootstrap capacitor to VCC so that the high-side MOSFET remains on.
7.3.11 Output Voltage Setting
There are two ways to set the output voltage: changing the feedback ratio and changing the reference voltage.
The TPS55288-Q1 has a 10-bit DAC to program the reference voltage from 45 mV to 1.2 V. The TPS55288-Q1
also can select an internal feedback resistor divider or an external resistor divider by setting the FB bit in register
04h. When the FB bit is set to 0, the output voltage feedback ratio is set in internal register 04h. When the FB bit
is set to 1, the output voltage feedback ratio is set by an external resistor divider.
When using internal output voltage feedback settings, there are four feedback ratios programmable by writing
the INTFB[1:0] bits of register 04h. With this function, the TPS55288-Q1 can limit the maximum output voltage
to different values. In addition, the minimum step of the output voltage change is also programmed to 20 mV, 15
mV, 10 mV, and 5 mV, accordingly.
When using an external output voltage feedback resistor divider as shown in Figure 7-5, use Equation 6 to
calculate the output voltage with the reference voltage at the FB/INT pin.
4($_72
V176 = 8 × (1 +
)
4'(
4($_$6
(6)
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RSNS
VOUT
VOUT
ISP
RFB_UP
ISN
FB/INT
RFB_BT
Figure 7-5. Output Voltage Setting by External Resistor Divider
TI recommends using 100 kΩ for the up resistor RFB_UP. The reference voltage VREF at the FB/INT pin is
programmable from 45 mV to 1.2 V by writing a 10-bit data into register 00h and 01h.
7.3.12 Output Current Monitoring and Cable Voltage Droop Compensation
The TPS55288-Q1 outputs a voltage at the CDC pin proportional to the sensed voltage across a output current
sensing resistor between the ISP pin and the ISN pin. Equation 7 shows the exact voltage at the CDC pin related
to the sensed output current.
V%&% = 20 × (8 F 8
)
+52
+50
(7)
To compensate the voltage droop across a cable from the output of the USB port to its powered device,
the TPS55288-Q1 can lift its output voltage in proportion to the load current. There are two methods in the
TPS55288-Q1 to implement the compensation: by setting internal register 05h or by placing a resistor between
the CDC pin and AGND pin.
When using internal output voltage feedback, it is recommended to use the internal compensation setting. When
using an external resistor divider at the FB/INT pin to set the output voltage, it is recommended to use the
external compensation setting by placing a resistor at the CDC pin.
By default, the internal cable voltage droop compensation function is enabled with 0 V added to the output
voltage. Write the value into the bit CDC [2:0] in register 05h to get the desired voltage compensation.
When using external output voltage feedback, external compensation is better than the internal register for its
high accuracy. The output voltage rises in proportion to the current sourcing from the CDC pin through the
resistor at the CDC pin. It is recommended to use 100-kΩ resistance for the up resistor of the feedback resistor
divider. Equation 8 shows the output voltage rise related to the sensed output current, the resistance at the CDC
pin, and the up resistor of the output voltage feedback resistor divider.
8
F 8
+50
+52
V176_%&% = 3 × 4($_72 × (
)
4%&%
(8)
where
•
•
RFB_UP is the up resistor of the resistor divider between the output and the FB/INT pin
RCDC is the resistor at the CDC pin
When RFB_UP is 100 kΩ, the output voltage rise versus the sensed output current and the resistor at the CDC
pin is shown in Figure 7-6.
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VOUT_CDC(V)
0.8
RCDC=20K
0.75V
0.5V
0.7
0.6
0.5
0.4
0.3
0.2
0.1
RCDC=30K
RCDC=75K
0.2V
0.1V
RCDC=150K
RCDC=floating
40
VISP œ VISN
(mV)
10
20
30
50
Figure 7-6. Output Voltage Rise versus Output Current
7.3.13 Integrated Gate Drivers
The TPS55288-Q1 provides two N-channel MOSFET gate drivers for buck side. Each driver is capable of
sourcing 1-A and sinking 1.8-A peak current. In buck operation, the DR1H pin and the DR1L pin are switched by
the PWM controller. In boost mode, the DR1H pin remains at continuously high voltage to turn on the high-side
MOSFET of the buck side, and the DR1L pin remains at continuously low voltage to turn off the low-side
MOSFET of the buck side.
In DCM buck mode operation, the DR1L turns off the low-side FET when the inductor current drops to zero.
The low-side gate driver is powered from the VCC pin, and the high-side gate driver is powered from the
bootstrap capacitor CBOOT1, which is between the BOOT1 pin and the SW1 pin.
7.3.14 Output Current Limit
The output current limit is programmable from 0 A to 6.35 A by placing a 10-mΩ current sensing resistor
between the ISP pin and the ISN pin. Smaller resistance results in a higher current limit and bigger resistance
results in a lower current limit. An internal register sets the current sense voltage across the ISP pin and the ISN
pin. The programmable voltage step between the ISP pin and the ISN pin is 0.5 mV.
Connecting the ISP and the ISN pin together to the VOUT pin disables the output current limit because the
sensed voltage is always zero. The output current limit can also be disabled by reset the Current_Limit_EN bit in
the Current_Limit register to 0.
When the OE bit or the Current_Limit_EN bit is changed from 0 to 1, the OCP_MASK must be 0. After the OE bit
and the Current_Limit_EN bit are set, set the OCP_MASK to 1 to enable the OCP fault indication output.
7.3.15 Overvoltage Protection
The TPS55288-Q1 has output overvoltage protection. When the output voltage at the VOUT pin is detected
above 23.5 V typically, the TPS55288-Q1 turns off two high-side FETs and turns on two low-side FETs until its
output voltage drops the hysteresis value lower than the output overvoltage protection threshold. This function
prevents overvoltage on the output and secures the circuits connected to the output from excessive overvoltage.
7.3.16 Output Short Circuit Protection
In addition to the average inductor current limit, the TPS55288-Q1 implements the output short-circuit protection
by entering hiccup mode. To enable hiccup mode, the HICCUP bit in register 06h must be set. After soft start-up
time of 4 ms, the TPS55288-Q1 monitors the average inductor current and output voltage. Whenever the output
short circuit happens, causing the average inductor current hitting the set limit and the output voltage below
0.8 V, the TPS55288-Q1 shuts down the switching for 76 ms (typical) and then repeats the soft start for 4 ms.
The hiccup mode helps reduce the total power dissipation on the TPS55288-Q1 in the output short-circuit or
overcurrent condition.
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7.3.17 Thermal Shutdown
The TPS55288-Q1 is protected by a thermal shutdown circuit that shuts down the device when the internal
junction temperature exceeds 175°C (typical). The internal soft-start circuit is reset but all internal registers
values remain unchanged when thermal shutdown is triggered. The converter automatically restarts when
the junction temperature drops below the thermal shutdown hysteresis of 20°C below the thermal shutdown
threshold.
7.4 Device Functional Modes
In light load condition, the TPS55288-Q1 can work in PFM or forced PWM mode to meet different application
requirements. PFM mode decreases switching frequency to reduce the switching loss thus it gets high efficiency
at light load condition. The FPWM mode keeps the switching frequency unchanged to avoid undesired low
switching frequency but the efficiency becomes lower than that of PFM mode.
7.4.1 PWM Mode
In FPWM mode, the TPS55288-Q1 keeps the switching frequency unchanged in light load condition. When
the load current decreases, the output of the internal error amplifier decreases as well to reduce the average
inductor current down to deliver less power from input to output. When the output current further reduces, the
current through the inductor decreases to zero during the switch-off time. The high-side N-MOSFET is not turned
off even if the current through the MOSFET is zero. Thus, the inductor current changes its direction after it runs
to zero. The power flow is from output side to input side. The efficiency is low in this condition. However, with
the fixed switching frequency, there is no audible noise or other problems that might be caused by low switching
frequency in light load condition.
7.4.2 Power Save Mode
The TPS55288-Q1 improves the efficiency at light load condition with PFM mode. By connecting an appropriate
resistor at the MODE pin or enabling the PFM function in the internal register, the TPS55288-Q1 can work
in PFM mode at light load condition. When the TPS55288-Q1 operates at light load condition, the output of
the internal error amplifier decreases to make the inductor peak current down to deliver less power to the
load. When the output current further reduces, the current through the inductor will decrease to zero during
the switch-off time. When the TPS55288-Q1 works in buck mode, once the inductor current becomes zero, the
low-side switch of the buck side is turned off to prevent the reverse current from output to ground. When the
TPS55288-Q1 works in boost mode, once the inductor current becomes zero, the high side-switch of the boost
side is turned off to prevent the reverse current from output to input. The TPS55288-Q1 resumes switching
until the output voltage drops. Thus PFM mode reduces switching cycles and eliminates the power loss by the
reverse inductor current to get high efficiency in light load condition.
7.5 Programming
The TPS55288-Q1 uses I2C interface for flexible converter parameter programming. I2C is a bi-directional 2-wire
serial interface. Only two bus lines are required: a serial data line (SDA) and a serial clock line (SCL). I2C
devices can be considered as masters or slaves when performing data transfers. A master is the device that
initiates a data transfer on the bus and generates the clock signals to permit that transfer. At that time, any
device addressed is considered a slave.
The TPS55288-Q1 operates as a slave device with address 74h and 75h set by a different resistor at the MODE
pin. Receiving control inputs from the master device like a microcontroller or a digital signal processor reads
and writes the internal registers 00h through 07h. The I2C interface of the TPS55288-Q1 supports both standard
mode (up to 100 kbit/s) and fast mode plus (up to 1000 kbit/s). Both SDA and SCL must be connected to the
positive supply voltage through current sources or pullup resistors. When the bus is free, both lines are in high
voltage.
7.5.1 Data Validity
The data on the SDA line must be stable during the high level period of the clock. The high level or low level
state of the data line can only change when the clock signal on the SCL line is low level. One clock pulse is
generated for each data bit transferred.
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SDA
SCL
Data line stable
Data valid
Change of data
allowed
Figure 7-7. I2C Data Validity
7.5.2 START and STOP Conditions
All transactions begin with a START (S) and can be terminated by a STOP (P). A high level to low level transition
on the SDA line while SCL is at high level defines a START condition. A low level to high level transition on the
SDA line when the SCL is at high level defines a STOP condition.
START and STOP conditions are always generated by the master. The bus is considered busy after the START
condition, and free after the STOP condition.
SDA
SCL
START (S)
STOP (P)
Figure 7-8. I2C START and STOP Conditions
7.5.3 Byte Format
Every byte on the SDA line must be eight bits long. The number of bytes to be transmitted per transfer is
unrestricted. Each byte has to be followed by an acknowledge bit. Data is transferred with the most significant bit
(MSB) first. If a slave cannot receive or transmit another complete byte of data until it has performed some other
function, it can hold the clock line SCL low to force the master into a wait state (clock stretching). Data transfer
then continues when the slave is ready for another byte of data and release the clock line SCL.
Acknowledgement signal
from slave
Acknowledgement signal
from receiver
MSB
SDA
SCL
1
2
7
8
9
1
2
8
9
S or Sr
P or Sr
START or
Repeated
START
STOP or
Repeated
START
Figure 7-9. Byte Format
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7.5.4 Acknowledge (ACK) and Not Acknowledge (NACK)
The acknowledge takes place after every byte. The acknowledge bit allows the receiver to signal the transmitter
that the byte was successfully received and another byte may be sent. All clock pulses, including the
acknowledge 9th clock pulse, are generated by the master.
The transmitter releases the SDA line during the acknowledge clock pulse so the receiver can pull the SDA line
to low level and it remains stable low level during the high level period of this clock pulse.
The Not Acknowledge signal is when SDA remains high level during the 9th clock pulse. The master can then
generate either a STOP to abort the transfer or a repeated START to start a new transfer.
7.5.5 Slave Address and Data Direction Bit
After the START, a slave address is sent. This address is seven bits long followed by the eighth bit as a data
direction bit (bit R/W). A zero indicates a transmission (WRITE) and a one indicates a request for data (READ).
SDA
SCL
1 - 7
8
9
1 - 7
8
9
1 - 7
8
9
S
P
START
ADDRESS
R/W
ACK
DATA
ACK
DATA
ACK
STOP
Figure 7-10. Slave Address and Data Direction
7.5.6 Single Read and Write
Figure 7-11 and Figure 7-12 show the single-byte write and single-byte read format of the I2C communication.
1
7
1
1
8
1
8
1
1
S
Slave Address
0
ACK
Register Address
ACK
Data to Address
ACK
P
Figure 7-11. Single-byte Write
1
7
1
0
1
8
1
1
7
1
1
1
S
Slave Address
ACK
Register Address
ACK
S
Slave Address
ACK
From master to slave
From slave to master
8
1
1
Data from Address
NACK
P
Figure 7-12. Single-byte Read
If the register address is not defined, the TPS55288-Q1 sends back NACK and goes back to the idle state.
7.5.7 Multi-Read and Multi-Write
The TPS55288-Q1 supports multi-read and multi-write.
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1
7
1
0
1
8
1
S
Slave Address
ACK
Register Address
ACK
8
1
8
1
8
1
1
Data to Address
ACK Data to Address + 1 ACK
······
Data to Address + N ACK
P
Figure 7-13. Multi-byte Write
1
7
1
0
1
8
1
1
7
1
1
1
S
Slave Address
ACK
Register Address
ACK
S
Slave Address
ACK
8
1
8
1
8
1
1
NACK
Data from Address
ACK Data from Address + 1 ACK
······
Data from Address + N
P
Figure 7-14. Multi-byte Read
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7.6 Register Maps
Table 7-3 lists the memory-mapped registers for the device registers. All register offset addresses not listed in
Table 7-3 should be considered as reserved locations, and the register contents should not be modified.
Table 7-3. Device Registers
Address
0h, 1h
2h
Acronym
REF
Register Name
Reference Voltage
Current Limit Setting
Slew Rate
Section
Go
IOUT_LIMIT
VOUT_SR
VOUT_FS
CDC
Go
3h
Go
4h
Feedback Selection
Cable Compensation
Mode Control
Go
5h
Go
6h
MODE
Go
7h
STATUS
Operating Status
Go
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7.6.1 REF Register (Address = 0h, 1h) [reset = 11010010h, 00000000h]
REF is shown in Figure 7-15 and Figure 7-16 described in Table 7-4.
Return to Summary Table.
REF sets the internal reference voltage of the TPS55288-Q1. The 01h register is the high byte and the 00h
register is the low byte. One LSB of register 00h stands for 1.129 mV of the internal reference voltage. The
default register value is 00000000 11010010b of 282 mV. When the register value is 00000000 00000000b, the
reference voltage is 45 mV. When the register value is 00000011 11000000b, the reference voltage is 1.129 V.
The output voltage of the TPS55288-Q1 also depends on the output feedback ratio, which is either set in register
04h or set by an external resistor divider.
Writing register 01h enables the TPS55288-Q1 to load the 01h and 00h data into the internal 10-bit DAC. Writing
the register 00h does not impact the internal reference voltage.
Figure 7-15. REF_LSB
7
6
5
4
3
2
1
0
VREF
R/W-11010010b
Figure 7-16. REF_MSB
15
14
13
12
11
10
9
8
Reserved
VREF
R/W-000000b
R/W-00b
Table 7-4. REF Register Field Descriptions
Bit
Field
Type
R/W
R/W
Reset
Description
15-10
9-0
Reserved
VREF
000000b
Reserved
00 11010010b Sets the internal reference voltage
00 00000000b = 45-mV reference voltage
00 00000001b = 46.129-mV reference voltage
00 00000010b = 47.258-mV reference voltage
...... = ......
00 11010010b = 282-mV reference voltage (Default)
...... = ......
01 10011010b = 508-mV reference voltage
...... = ......
10 11000110b = 846-mV reference voltage
...... = ......
11 11000000b = 1129-mV reference voltage
...... = ......
11 11111111b = 1200-mV reference voltage
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7.6.2 IOUT_LIMIT Register (Address = 2h) [reset = 11100100h]
IOUT_LIMIT is shown in Figure 7-17 and described in Table 7-5.
Return to Summary Table.
IOUT_LIMIT sets the current limit target voltage between the ISP pin and the ISN pin. The default value in the
current limit register is 11100100b standing for 50 mV. 1 LSB stands for 0.5 mV. The bit7 enables the current limit
or disables the current limit.
Figure 7-17. IOUT_LIMIT Register
7
6
5
4
3
2
1
0
Current_Limit_EN
R/W-1b
Current_Limit_Setting
R/W-1100100b
Table 7-5. IOUT_LIMIT Register Field Descriptions
Bit
Field
Type
Reset
Description
7
Current_Limit_EN
R/W
1b
Enable or disable current limit.
0b = Current limit disabled
1b = Current limit enabled (Default)
6-0
Current_Limit_Setting
R/W
1100100b
Sets the current limit target voltage between the ISP pin and the ISN
pin
0000000b = VISP-VISN = 0 (mV)
0000001b = VISP-VISN = 0.5 (mV)
0000010b = VISP-VISN = 1 (mV)
0000011b = VISP-VISN = 1.5 (mV)
0000100b = VISP-VISN = 2.0 (mV)
1100100b = VISP-VISN = 50.0 (mV) (Default)
1111111b = VISP-VISN = 63.5 (mV)
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7.6.3 VOUT_SR Register (Address = 3h) [reset = 00000001h]
VOUT_SR is shown in Figure 7-18 and described in Table 7-6.
Return to Summary Table.
Register 03h sets the slew rate of the output voltage change and the response delay time after the output current
exceeds the setting output current limit.
The OCP_DELAY [1:0] bits set the response time of the TPS55288-Q1 when the output overcurrent limit is hit.
This allows the TPS55288-Q1 to output high current in a relative short duration time. The default setting is 128
µs so that the TPS55288-Q1 immediately limits the output current.
The SR [1:0] bits set 1.25 mV/μs, 2.5 mV/μs, 5 mV/μs, and 10 mV/μs slew rate for output voltage change.
Figure 7-18. VOUT_SR Register
7
6
5
4
3
2
1
0
RESERVED
R/W-0b
OCP_DELAY
R/W-00b
RESERVED
R/W-00b
SR
R/W-01b
Table 7-6. VOUT_SR Register Field Descriptions
Bit
7-6
5-4
Field
Type
R/W
R/W
Reset
Description
RESERVED
OCP_DELAY
00b
Reserved
00b
Sets the response time of the device when the output overcurrent
limit is reached.
00b = 128 µs (Default)
01b = Delay 1.024 x 3 ms
10b = Delay 1.024 x 6 ms
11b = Delay 1.024 x 12 ms
3-2
1-0
RESERVED
SR
R/W
R/W
00b
01b
Reserved
Sets slew rate for output voltage change.
00b = 1.25 mV/µs output change slew rate
01b = 2.5 mV/µs output change slew rate (Default)
10b = 5 mV/µs output change slew rate
11b = 10 mV/µs output change slew rate
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7.6.4 VOUT_FS Register (Address = 4h) [reset = 00000011h]
VOUT_FS is shown in Figure 7-19 and described in Table 7-7.
Return to Summary Table.
Register 04h sets the selection for the output feedback voltage, either by an internal resistor divider or external
resistor divider, and sets the internal feedback ratio when using internal feedback resistor divider.
Figure 7-19. VOUT_FS Register
7
6
5
4
3
2
1
0
FB
RESERVED
R/W-00000b
INTFB
R/W-0b
R/W-11b
Table 7-7. VOUT_FS Register Field Descriptions
Bit
Field
Type
Reset
Description
7
FB
R/W
0b
Output feedback voltage
0b = Use internal output voltage feedback. The FB/INT pin is the
indicator for output short circuit protection, overcurrent status, and
overvoltage status (Default).
1b = Use external output voltage feedback. The FB/INT pin is the
feedback input of the output voltage.
6-2
1-0
RESERVED
INTFB
R
00000b
11b
Reserved
R/W
Internal feedback ratio
00b = Set internal feedback ratio to 0.2256
01b = Set internal feedback ratio to 0.1128
10b = Set internal feedback ratio to 0.0752
11b = Set internal feedback ratio to 0.0564(Default)
Table 7-8. Output Voltage vs Internal Reference
INTFB1 INTFB0
REF=0000h
REF=000Dh
REF=0028h
REF=0078h
REF=03C0h
Output Voltage Step
0
0
1
1
0
1
0
1
0.8 V
5 V
5 mV
10 mV
15 mV
20 mV
0.8 V
10 V
0.8 V
15 V
0.8 V
20 V
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7.6.5 CDC Register (Address = 5h) [reset = 11100000h]
CDC is shown in Figure 7-20 and described in Table 7-9.
Return to Summary Table.
Register 05h sets masks for SC bit, OCP bit, and OVP bit in register 07h. In addition, register 05h sets the
voltage rise added to the setting output voltage with respect to the sensed differential voltage between the ISP
pin and the ISN pin.
The OCP_MASK must be 0 when the OE bit or the Current_Limit_EN bit is changed from 0 to 1. After the OE bit
and the Current_Limit_EN bit are set, set the OCP_MASK to 1 to enable the OCP fault indication output.
Figure 7-20. CDC Register
7
6
5
4
3
2
1
0
SC_MASK
R/W-1b
OCP_MASK
R/W-1b
OVP_MASK
R/W-1b
RESERVED
R/W-0b
CDC_OPTION
R/W-0b
CDC
R/W-000b
Table 7-9. CDC Register Field Descriptions
Bit
Field
Type
Reset
Description
7
6
5
SC_MASK
R/W
1b
Short circuit mask
0b = Disabled SC indication
1b = Enable SC indication (Default)
OCP_MASK
OVP_MASK
R/W
R/W
1b
1b
Over current mask
0b = Disabled OCP indication
1b = Enable OCP indication (Default)
Over voltage mask
0b = Disabled OVP indication
1b = Enable OVP indication (Default)
4
3
RESERVED
R/W
R/W
0b
0b
Reserved
CDC_OPTION
Select the cable voltage droop compensation approach.
0b = Internal CDC compensation by the register 05H (Default)
1b = External CDC compensation by a resistor at the CDC pin
2-0
CDC
R/W
000b
Compensation for voltage droop over the cable
000b = 0-V output voltage rise with 50 mV at VISP - VISN (Default)
001b = 0.1-V output voltage rise with 50 mV at VISP - VISN
010b = 0.2-V output voltage rise with 50 mV at VISP - VISN
011b = 0.3-V output voltage rise with 50 mV at VISP - VISN
100b = 0.4-V output voltage rise with 50 mV at VISP - VISN
101b = 0.5-V output voltage rise with 50 mV at VISP - VISN
110b = 0.6-V output voltage rise with 50 mV at VISP - VISN
111b = 0.7-V output voltage rise with 50 mV at VISP - VISN
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7.6.6 MODE Register (Address = 6h) [reset = 00100000h]
MODE is shown in Figure 7-21 and described in Table 7-10.
Return to Summary Table.
MODE controls the operating mode of the TPS55288-Q1.
Figure 7-21. MODE Register
7
6
5
4
3
2
1
0
OE
FSW
HICCUP
R/W-1b
DISCHG
R/W-0b
VCC
I2CADD
R/W-0b
PFM
MODE
R/W-0b
R/W-0b
R/W-0b
R/W-0b
R/W-0b
Table 7-10. MODE Register Field Descriptions
Bit
Field
Type
Reset
Description
7
OE
R/W
0b
Output enable
0b = Output disabled (Default)
1b = Output enable
6
FSWDBL
R/W
0b
Switching frequency doubling in buck-boost mode
TI does not recommend using double frequency function at switching
frequency above 1.6 MHz.
0b = Keep the switching frequency unchanged during buck-boost
mode (Default)
1b = Double the switching frequency during buck-boost mode
5
4
HICCUP
DISCHG
R/W
R/W
1b
0b
Hiccup mode
0b = Disable the hiccup during output short circuit protection.
1b = Enable the hiccup during output short circuit protection (Default)
Output discharge
0b = Disabled VOUT discharge when the device is in shutdown
mode (Default)
1b = Enable VOUT discharge. VOUT is discharged to ground by an
internal 100-mA current sink
3
2
1
0
VCC
R/W
R/W
R/W
R/W
0b
0b
0b
0b
VCC option
0b = Select internal LDO for VCC (Default)
1b = Select external 5-V power supply for VCC
I2CADD
PFM
I2C address
0b = Set I2C slave address to 74h (Default)
1b = Set I2C slave address to 75h
Select operating mode at light load condition
0b = PFM operating mode at light load condition (Default)
1b = FPWM operating mode at light load condition
MODE
Mode control approach
0b = Set VCC, I2CADD, and PFM controlled by external resistor
(Default)
1b = Set VCC, I2CADD, and PFM controlled by internal register
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7.6.7 STATUS Register (Address = 7h) [reset = 00000011h]
STATUS is shown in Figure 7-22 and described in Table 7-11.
Return to Summary Table.
The STATUS register stores the operating status of the TPS55288-Q1. When any of the SCP bit, the OCP bit,
or the OVP bit are set, and the corresponding mask bit in register 05h is set as well, the FB/INT pin outputs
̅
low logic level to indicate the situation. Reading register 07h clears the SCP bit, OCP bit, and OVP bit. After
the SCP bit, OCP bit, or OVP bit is set, it does not reset until the register is read. If the situation still exists, the
corresponding bit is set again.
Figure 7-22. STATUS Register
7
6
5
4
3
2
1
0
SCP
R-0b
OCP
R-0b
OVP
R-0b
Reserved
R/W-0b
Reserved
R/W-0b
Reserved
R/W-0b
STATUS
R-11b
Table 7-11. STATUS Register Field Descriptions
Bit
Field
Type
Reset
Description
7
SCP
R
0b
Short circuit protection
0b = No short circuit
1b = Short circuit happens. Does not reset until it is read.
6
5
OCP
OVP
R
R
0b
0b
Overcurrent protection
0b = No output overcurrent
1b = Output current hits the current limit sensed at the ISP and the
ISN pin. Does not reset until it is read.
Overvoltage protection
0b = No OVP
1b = Output voltage exceeds the OVP threshold. Does not reset until
it is read.
4
RESERVED
RESERVED
RESERVED
STATUS
R
R
R
R
0b
Reserved
Reserved
Reserved
3
0b
2
0b
1-0
11b
Operating status
00b = Boost
01b = Buck
10b = Buck-Boost
11b = Reserved
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7.6.8 Register Summary
The Table 7-12 summarizes the default settings of the registers in the TPS55288-Q1.
Table 7-12. Default Settings of Registers
Register Address
Register Name
VREF_LSB
VREF_MSB
IOUT_LIMIT
VOUT_SR
VOUT_FS
CDC
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R
Default Values
11010010
00000000
11100100
00000001
00000011
11100000
00100000
00000011
00h
01h
02h
03h
04h
05h
06h
07h
MODE
STATUS
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8 Application and Implementation
Note
Information in the following applications sections is not part of the TI component specification,
and TI does not warrant its accuracy or completeness. TI’s customers are responsible for
determining suitability of components for their purposes, as well as validating and testing their design
implementation to confirm system functionality.
8.1 Application Information
The TPS55288-Q1 can operate over a wide range of 2.7-V to 36-V input voltage and output 0.8 V to 22 V. It
can transition among buck mode, buck-boost mode, and boost mode smoothly according to the input voltage
and the setting output voltage. The TPS55288-Q1 operates in buck mode when the input voltage is greater than
the output voltage and in boost mode when the input voltage is less than the output voltage. When the input
voltage is close to the output voltage, the TPS55288-Q1 operates in one-cycle buck and one-cycle boost mode
alternately. The switching frequency is set by an external resistor. To reduce the switching power loss in high
power conditions, it is recommended to set the switching frequency below 500 kHz. If a system requires higher
switching frequency above 500 kHz, it is recommended to set the lower switch current limit for better thermal
performance.
8.2 Typical Application
The TPS55288-Q1 provides a small size solution for USB PD power supply application with the input voltage
ranging from 9 V to 36 V.
L1
4.7µH
C5
C4
0.1µF
0.1µF
SW1
BOOT2
DR1H
VIN
DR1L BOOT1
SW2
VIN = 9V to 36V
VOUT = 5V to 20V
VOUT
R1
10mΩ
C1
C2
4 x 10µF
VCC
C3
4.7µF
4 x 22µF
PGND
AGND
ISP
SCL
SDA
ON
EN/UVLO
MODE
TPS55288-Q1
ISN
OFF
FB/INT
COMP
CDC
R6
20kΩ
DITH/SYNC
FSW
C6
R3
C7
R4
C8
0.01µF
100kΩ
ILIM
R5
R2
49.9kΩ
20kΩ
Figure 8-1. USB PD Power Supply With 9-V to 36-V Input Voltage
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8.2.1 Design Requirements
The design parameters are listed in Table 8-1:
Table 8-1. Design Parameters
PARAMETERS
Input voltage
VALUES
9 V to 36 V
5 V to 20 V
5 A
Output voltage
Output current limit
Output voltage ripple
Operating mode at light load
±50 mV
PFM
8.2.2 Detailed Design Procedure
8.2.2.1 Custom Design With WEBENCH® Tools
Click here to create a custom design using the TPS55288-Q1 device with the WEBENCH® Power Designer.
1. Start by entering the input voltage (VIN), output voltage (VOUT), and output current (IOUT) requirements.
2. Optimize the design for key parameters such as efficiency, footprint, and cost using the optimizer dial.
3. Compare the generated design with other possible solutions from Texas Instruments.
The WEBENCH Power Designer provides a customized schematic along with a list of materials with real-time
pricing and component availability.
In most cases, these actions are available:
•
•
•
•
Run electrical simulations to see important waveforms and circuit performance
Run thermal simulations to understand board thermal performance
Export customized schematic and layout into popular CAD formats
Print PDF reports for the design, and share the design with colleagues
Get more information about WEBENCH tools at www.ti.com/WEBENCH.
8.2.2.2 Switching Frequency
The switching frequency of the TPS55288-Q1 is set by a resistor at the FSW pin. Use Equation 3 to calculate the
resistance for the desired frequency. To reduce the switching power loss with such a high current application, a
1% standard resistor of 49.9 kΩ is selected for 400-kHz switching frequency for this application.
8.2.2.3 Output Voltage Setting
The TPS55288-Q1 has I2C interface to set the internal reference voltage. A microcontroller can easily set the
desired output voltage by writing the proper data into the reference voltage registers through I2C bus.
8.2.2.4 Inductor Selection
Since the selection of the inductor affects steady state operation, transient behavior, and loop stability, the
inductor is the most important component in power regulator design. There are three important inductor
specifications: inductance, saturation current, and DC resistance.
The TPS55288-Q1 is designed to work with inductor values between 1 µH and 10 µH. The inductor selection is
based on consideration of both buck and boost modes of operation.
For buck mode, the inductor selection is based on limiting the peak-to-peak current ripple to the maximum
inductor current at the maximum input voltage. In CCM, Equation 9 shows the relationship between the
inductance and the inductor ripple current.
k
o
VIN(MAX)-VOUT ×VOUT
L=
∆IL(P-P)×fSW×VIN MAX
:
;
(9)
where
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•
•
•
•
VIN(MAX) is the maximum input voltage
VOUT is the output voltage
ΔIL(P-P) is the peak to peak ripple current of the inductor
fSW is the switching frequency
For a certain inductor, the inductor ripple current achieves maximum value when VOUT equals half of
the maximum input voltage. Choosing higher inductance gets smaller inductor current ripple while smaller
inductance gets larger inductor current ripple.
For boost mode, the inductor selection is based on limiting the peak-to-peak current ripple to the maximum
inductor current at the maximum output voltage. In CCM, Equation 10 shows the relationship between the
inductance and the inductor ripple current.
k
VIN× VOUT(MAX)-VIN
o
L=
∆IL(P-P)×fSW×VOUT(MAX)
(10)
where
•
•
•
•
VIN is the input voltage
VOUT(MAX) is the maximum output voltage
ΔIL(P-P) is the peak to peak ripple current of the inductor
fSW is the switching frequency
For a certain inductor, the inductor ripple current achieves maximum value when VIN equals to the half of
the maximum output voltage. Choosing higher inductance gets smaller inductor current ripple while smaller
inductance gets larger inductor current ripple.
For this application example, a 4.7-µH inductor is selected, which produces approximate maximum inductor
current ripple of 50% of the highest average inductor current in buck mode and 50% of the highest average
inductor current in boost mode.
In buck mode, the inductor DC current equals to the output current. In boost mode, the inductor DC current can
be calculated with Equation 11.
VOUT×IOUT
IL(DC)
=
VIN×ꢀ
(11)
where
•
•
•
•
VOUT is the output voltage
IOUT is the output current
VIN is the input voltage
η is the power conversion efficiency
For a given maximum output current of the buck-boost converter TPS55288-Q1, the maximum inductor DC
current happens at the minimum input voltage and maximum output voltage. Set the inductor current limit of the
TPS55288-Q1 higher than the calculated maximum inductor DC current to make sure the TPS55288-Q1 has the
desired output current capability.
In boost mode, the inductor ripple current is calculated with Equation 12.
:
VIN× VOUT-VIN
;
∆IL(P-P)
=
L×fSW×VOUT
(12)
where
•
•
•
ΔIL(P-P) is the inductor ripple current
L is the inductor value
fSW is the switching frequency
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•
•
VOUT is the output voltage
VIN is the input voltage
Therefore, the inductor peak current is calculated with Equation 13.
∆IL(P-P)
IL(P) = IL(DC)
+
2
(13)
Normally, it is advisable to work with an inductor peak-to-peak current of less than 40% of the average inductor
current for maximum output current. A smaller ripple from a larger valued inductor reduces the magnetic
hysteresis losses in the inductor and EMI, but in the same way, load transient response time is increased. The
selected inductor must have higher saturation current than the calculated peak current.
The conversion efficiency is dependent on the resistance of its current path. The switching loss associated
with the switching MOSFETs, and the inductor core loss. Therefore, the overall efficiency is affected by the
inductor DC resistance (DCR), equivalent series resistance (ESR) at the switching frequency, and the core loss.
Table 8-2 lists recommended inductors for the TPS55288-Q1. In this application example, the Coilcraft inductor
XAL1010-472 is selected for its small size, high saturation current, and small DCR.
Table 8-2. Recommended Inductors
DCR
(MAXIMUM)
(mΩ)
SATURATION
CURRENT / HEAT
RATING CURRENT (A)
PART NUMBER
L (µH)
SIZE (L x W x H mm)
VENDOR(1)
XAL1010-472ME
IHLP5050EZER4R7
125CDMCCDS-4R7MC
4.7
4.7
4.7
10
10.1
10
25.4/17.5
17.8/15.3
22/14
11.3 × 10 × 10
13.5 × 12.9 × 5
13.5 × 12.6 × 5
Coilcraft
Vishay
Sumida
(1) See the Third-party Products disclaimer.
8.2.2.5 Input Capacitor
In buck mode, the input capacitor supplies high ripple current. The RMS current in the input capacitors is given
by Equation 14.
:
VOUT× VIN-VOUT
;
¨
ICIN RMS; = I
:
×
OUT
VIN×VIN
(14)
where
•
•
ICIN(RMS) is the RMS current through the input capacitor
IOUT is the output current
The maximum RMS current occurs at the output voltage is half of the input voltage, which gives ICIN(RMS) = IOUT
/
2. Ceramic capacitors are recommended for their low ESR and high ripple current capability. A total of 20 µF
effective capacitance is a good starting point for this application.
8.2.2.6 Output Capacitor
In boost mode, the output capacitor conducts high ripple current. The output capacitor RMS ripple current is
given by Equation 15, where the minimum input voltage and the maximum output voltage correspond to the
maximum capacitor current.
VOUT
¨
ICOUT RMS; = I
:
×
-1
OUT
VIN
(15)
where
ICOUT(RMS) is the RMS current through the output capacitor
•
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•
IOUT is the output current
In this example, the maximum output ripple RMS current is 5.5 A.
The ESR of the output capacitor causes an output voltage ripple given by Equation 16 in boost mode.
IOUT×VOUT
VRIPPLE(ESR)
=
×RCOUT
VIN
(16)
where
RCOUT is the ESR of the output capacitance
•
The capacitance also causes a capacitive output voltage ripple given by Equation 17 in boost mode. When input
voltage reaches the minimum value and the output voltage reaches the maximum value, there is the largest
output voltage ripple caused by the capacitance.
VIN
VOUT
l
IOUT× 1-
p
VRIPPLE(CAP)
=
COUT×fSW
(17)
Typically, a combination of ceramic capacitors and bulk electrolytic capacitors is needed to provide low ESR,
high ripple current, and small output voltage ripple. From the required output voltage ripple, use Equation 16 and
Equation 17 to calculate the minimum required effective capacitance of the COUT
.
8.2.2.7 Output Current Limit
The output current limit is implemented by putting a current sense resistor between the ISP and ISN pins along
with setting a limit voltage between the ISP pin and the ISN pin through register 02h. The maximum value of the
limit voltage between the ISP and ISN pins is 63.5 mV. The default limit voltage is 50 mV. The current sense
resistor between the ISP and ISN pins should be selected to ensure that the output current limit is set high
enough for output. The output current limit setting resistor is given by Equation 18.
VSNS
RSNS
=
IOUT_LIMIT
(18)
where
•
•
VSNS is the current limit setting voltage between the ISP and ISN pins
IOUT_LIMIT is the desired output current limit
Because the power dissipation is large, make sure the current sense resistor has enough power dissipation
capability with large package.
8.2.2.8 Loop Stability
The TPS55288-Q1 uses average current control scheme. The inner current loop uses internal compensation
and requires the inductor value must be larger than 1.2/fSW. The outer voltage loop requires an external
compensation. The COMP pin is the output of the internal voltage error amplifier. An external compensation
network comprised of resistor and ceramic capacitors is connected to the COMP pin.
The TPS55288-Q1 operates in buck mode or boost mode. Therefore, both buck and boost operating modes
require loop compensations. The restrictive one of both compensations is selected as the overall compensation
from a loop stability point of view. Typically for a converter designed either work in buck mode or boost mode, the
boost mode compensation design is more restrictive due to the presence of a right half plane zero (RHPZ).
The power stage in boost mode can be modeled by Equation 19.
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s
s
l
p l
× 1-
p
1+
:
RLOAD× 1-D
;
2N×fESRZ
2N×fRHPZ
GPS(s) =
×
s
2×RSENSE
1+
2N×fP
(19)
where
•
•
•
RLOAD is the output load resistance
D is the switching duty cycle in boost mode
RSENSE is the equivalent internal current sense resistor, which is 0.055 Ω
The power stage has two zeros and one pole generated by the output capacitor and load resistance. Use
Equation 20 to Equation 22 to calculate them.
2
fP =
2N×RLOAD×COUT
(20)
(21)
(22)
1
fESRZ
=
2N×RCOUT×COUT
2
:
RLOAD× 1-D
;
fRHPZ
=
2N×L
The internal transconductance amplifier together with the compensation network at the COMP pin constitutes the
control portion of the loop. The transfer function of the control portion is shown by Equation 23.
s
l
p
1+
GEA×REA×VREF
VOUT
2N×fCOMZ
GC(s) =
×
s
s
l
p
l
× 1 +
p
1+
2N×fCOMP1
2N×fCOMP2
(23)
where
•
•
•
•
•
•
GEA is the transconductance of the error amplifier
REA is the output resistance of the error amplifier
VREF is the reference voltage input to the error amplifier
VOUT is the output voltage
fCOMP1 and fCOMP2 are the pole’s frequency of the compensation network
fCOMZ is the zero’s frequency of the compensation network
The total open-loop gain is the product of GPS(s) and GC(s). The next step is to choose the loop crossover
frequency, fC, at which the total open-loop gain is 1, namely 0 dB. The higher in frequency that the loop gain
stays above 0 dB before crossing over, the faster the loop response. It is generally accepted that the loop gain
cross over 0 dB at the frequency no higher than the lower of either 1/10 of the switching frequency, fSW or 1/5 of
the RHPZ frequency, fRHPZ
.
Then, set the value of RC, CC, and CP by Equation 24 to Equation 26.
2N×VOUT×R
×COUT×fC
SENSE
RC =
: ;
1-D ×VREF×GEA
(24)
where
•
fC is the selected crossover frequency
RLOAD×COUT
CC =
2×RC
(25)
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RCOUT×COUT
CP=
RC
(26)
If the calculated CP is less than 10 pF, it can be left open.
Designing the loop for greater than 45° of phase margin and greater than 10-dB gain margin eliminates output
voltage ringing during the line and load transient.
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8.2.3 Application Curves
Figure 8-2. Switching Waveforms in VIN = 12 V,
VOUT = 5 V, IO = 5 A, FPWM
Figure 8-3. Switching Waveforms in VIN = 12 V,
VOUT = 5 V, IO = 0 A, PFM
Figure 8-4. Switching Waveforms in VIN = 12 V,
VOUT = 12 V, IO = 5 A, FPWM
Figure 8-5. Switching Waveforms in VIN = 12 V,
VOUT = 12 V, IO = 0 A, PFM
Figure 8-7. Switching Waveforms in VIN = 12 V,
VOUT = 20 V, IO = 0 A, PFM
Figure 8-6. Switching Waveforms in VIN = 12 V,
VOUT = 20 V, IO = 5 A, FPWM
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Figure 8-9. Shutdown Waveforms in VIN = 12 V,
Figure 8-8. Start-up Waveforms in VIN = 12 V, VOUT
= 5 V, IO = 5 A, FPWM
VOUT = 5 V, IO = 5 A, FPWM
Figure 8-10. Line Transient Waveforms in VIN = 9 V
to 20 V, VOUT = 12 V, IO = 5 A with 200-μs Slew Rate,
FPWM
Figure 8-11. Load Transient Waveforms in VIN = 12
V, VOUT = 5 V, IO = 2.5 A to 5 A with 20-μs Slew
Rate, FPWM
Figure 8-12. 3-A Output Current Limit Waveforms in VIN = 12 V,
VOUT = 5 V, RLOAD = 1.2 Ω, FPWM
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9 Power Supply Recommendations
The device is designed to operate from an input voltage supply range between 2.7 V to 36 V. This input supply
must be well regulated. If the input supply is located more than a few inches from the converter, additional
bulk capacitance can be required in addition to the ceramic bypass capacitors. A typical choice is an aluminum
electrolytic capacitor with a value of 100 μF.
10 Layout
10.1 Layout Guidelines
As for all switching power supplies, especially those running at high switching frequency and high currents,
layout is an important design step. If layout is not carefully done, the regulator can suffer from instability and
noise problems. To maximize efficiency, switching rise time and fall time are very fast. To prevent radiation
of high-frequency noise (for example, EMI), proper layout of the high-frequency switching path is essential.
Minimize the length and area of all traces connected to the SW1 and SW2 pins, and always use a ground plane
under the switching regulator to minimize interplane coupling. The input capacitor needs to be close to the VIN
pin and the PGND to reduce the input supply current ripple.
The most critical current path for buck converter portion is from the switching FET at the buck side, through the
rectifier FET at the buck side to the PGND, then the input capacitors, and back to the input of the switching FET.
This high current path contains nanosecond rise time and fall time, and should be kept as short as possible.
Therefore, the input capacitor for power stage must be close to the input of the switching FET and the PGND
terminal of the rectifier FET.
The most critical current path for boost converter portion is from the switching FET at the boost side, through the
rectifier FET at boost side, then the output capacitors, and back to ground of the switching FET. This high current
path contains nanosecond rise time and fall time, and should be kept as short as possible. Therefore, the output
capacitor needs not only to be close to the VOUT pin, but also to the PGND pin to reduce the overshoot at the
SW2 pin and the VOUT pin.
The traces from the output current sensing resistor to the ISP pin and the ISN pin must be in parallel and close
to each other to avoid noise coupling.
The PGND plane and the AGND plane are connected at the terminal of the capacitor at the VCC pin. Thus the
noise caused by the MOSFET driver and parasitic inductance does not interfere with the AGND and internal
control circuit.
To get good thermal performance, it is recommended to use thermal vias beneath the TPS55288-Q1 connecting
the PGND pin to the PGND plane, and the VOUT pin to a large VOUT area separately.
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SLVSFQ7A – DECEMBER 2020 – REVISED DECEMBER 2021
www.ti.com
10.2 Layout Example
trace on bottom layer
AGND plane on an inner layer
The first inner layer is the PGND plane
VOUT
AGND plane connects to PGND plane at the terminal of the capacitor at the VCC pin
AGND
PGND
18 17 16 15 14 13
19
12
11
20
26
25
24
21
22
10
9
23
1
8
VIN
2
3
4
5
6
7
NMOSFET
PGND
AGND
Figure 10-1. Layout Example
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TPS55288-Q1
SLVSFQ7A – DECEMBER 2020 – REVISED DECEMBER 2021
www.ti.com
11 Device and Documentation Support
11.1 Device Support
11.1.1 Third-Party Products Disclaimer
TI'S PUBLICATION OF INFORMATION REGARDING THIRD-PARTY PRODUCTS OR SERVICES DOES NOT
CONSTITUTE AN ENDORSEMENT REGARDING THE SUITABILITY OF SUCH PRODUCTS OR SERVICES
OR A WARRANTY, REPRESENTATION OR ENDORSEMENT OF SUCH PRODUCTS OR SERVICES, EITHER
ALONE OR IN COMBINATION WITH ANY TI PRODUCT OR SERVICE.
11.1.2 Development Support
11.1.2.1 Custom Design With WEBENCH® Tools
Click here to create a custom design using the TPS55288-Q1 device with the WEBENCH® Power Designer.
1. Start by entering the input voltage (VIN), output voltage (VOUT), and output current (IOUT) requirements.
2. Optimize the design for key parameters such as efficiency, footprint, and cost using the optimizer dial.
3. Compare the generated design with other possible solutions from Texas Instruments.
The WEBENCH Power Designer provides a customized schematic along with a list of materials with real-time
pricing and component availability.
In most cases, these actions are available:
•
•
•
•
Run electrical simulations to see important waveforms and circuit performance
Run thermal simulations to understand board thermal performance
Export customized schematic and layout into popular CAD formats
Print PDF reports for the design, and share the design with colleagues
Get more information about WEBENCH tools at www.ti.com/WEBENCH.
11.2 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. Click on
Subscribe to updates to register and receive a weekly digest of any product information that has changed. For
change details, review the revision history included in any revised document.
11.3 Support Resources
TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help — straight
from the experts. Search existing answers or ask your own question to get the quick design help you need.
Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do
not necessarily reflect TI's views; see TI's Terms of Use.
11.4 Trademarks
HotRod™ and TI E2E™ are trademarks of Texas Instruments.
WEBENCH® is a registered trademark of Texas Instruments.
All trademarks are the property of their respective owners.
11.5 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled
with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may
be more susceptible to damage because very small parametric changes could cause the device not to meet its published
specifications.
11.6 Glossary
TI Glossary
This glossary lists and explains terms, acronyms, and definitions.
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TPS55288-Q1
SLVSFQ7A – DECEMBER 2020 – REVISED DECEMBER 2021
www.ti.com
12 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
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PACKAGE OPTION ADDENDUM
www.ti.com
12-Dec-2021
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
TPS55288QRPMRQ1
TPS55288QWRPMRQ1
ACTIVE
ACTIVE
VQFN-HR
VQFN-HR
RPM
RPM
26
26
3000 RoHS & Green
3000 RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
-40 to 150
-40 to 150
55288Q
55288W
NIPDAU
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
12-Dec-2021
OTHER QUALIFIED VERSIONS OF TPS55288-Q1 :
Catalog : TPS55288
•
NOTE: Qualified Version Definitions:
Catalog - TI's standard catalog product
•
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
13-Dec-2021
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
TPS55288QRPMRQ1
VQFN-
HR
RPM
RPM
26
26
3000
3000
330.0
12.4
3.8
4.3
1.5
8.0
12.0
Q2
TPS55288QWRPMRQ1 VQFN-
HR
330.0
12.4
3.8
4.3
1.5
8.0
12.0
Q2
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
13-Dec-2021
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SPQ
Length (mm) Width (mm) Height (mm)
TPS55288QRPMRQ1
TPS55288QWRPMRQ1
VQFN-HR
VQFN-HR
RPM
RPM
26
26
3000
3000
367.0
367.0
367.0
367.0
35.0
35.0
Pack Materials-Page 2
GENERIC PACKAGE VIEW
RPM 26
3.5 x 4, 0.5 mm pitch
VQFN-HR - 1 mm max height
VERY THIN QUAD FLATPACK-HotRod
This image is a representation of the package family, actual package may vary.
Refer to the product data sheet for package details.
4226451/A
www.ti.com
PACKAGE OUTLINE
VQFN-HR - 1 mm max height
PLASTIC QUAD FLATPACK-NO LEAD
RPM0026A
A
4.1
3.9
B
3.6
3.4
PIN 1 INDEX AREA
1.0
0.8
C
SEATING PLANE
0.08 C
0.05
0.00
5X 0.25±0.05
2X 0.35±0.05
0.1
C A B
0.1
C A B
0.05
C
0.05
C
5X
6X 0.4±0.1
0.425±0.1
2X (0.150 X 0.150)
TYP
(0.1) TYP
6X 0.525±0.1
7
2X 1.4875
13
6X 0.25±0.05
0.1
C A B
2X 0.225±0.05
2X 1
0.05
C
2X 0.5
PKG
6X 0.25±0.05
3X
0.1
C A B
1.425±0.1
24
25
26
0.05
C
2X 0.225±0.05
2X 1.4875
19
1
2X (0.175 X 0.150)
TYP
2X 0.475±0.1
PKG
2X 0.25±0.05
2X 0.4±0.05
0.1
C
A
B
3X 0.375±0.05
0.05
C
0.1
C A B
0.05
C
4224618/A 10/2018
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
www.ti.com
EXAMPLE BOARD LAYOUT
VQFN-HR - 1 mm max height
PLASTIC QUAD FLATPACK-NO LEAD
RPM0026A
3X (0.375)
PKG
2X (0.4)
1
2X (0.25)
2X (0.675)
19
2X (1.4875)
2X (0.225)
(R0.05) TYP
(1.6125)
(1.65)
3X (1.425)
PKG
24
25
26
2X (0.5)
2X (1)
(1.6375)
6X (0.25)
6X (0.25)
13
2X (1.4875)
2X (0.225)
7
6X (0.725)
6X (0.6)
5X (0.625)
5X (0.25)
2X (0.35)
(3.675)
(3.8)
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE: 20X
0.05 MAX
ALL AROUND
METAL EDGE
EXPOSED METAL
SOLDER MASK
OPENING
NON SOLDER MASK
DEFINED
SOLDER MASK DETAIL
4224618/A 10/2018
NOTES: (continued)
3. For more information, see Texas Instruments literature number SLUA271 (www.ti.com/lit/slua271) .
www.ti.com
EXAMPLE STENCIL DESIGN
VQFN-HR - 1 mm max height
PLASTIC QUAD FLATPACK-NO LEAD
RPM0026A
3X (0.375)
PKG
2X (0.4)
1
2X (0.25)
2X (0.675)
19
2X (1.4875)
2X (0.225)
(R0.05) TYP
(1.6125)
(1.65)
3X (1.425)
PKG
24
25
26
2X (0.5)
2X (1)
(1.6375)
6X (0.25)
6X (0.25)
13
2X (1.4875)
2X (0.225)
7
6X (0.725)
6X (0.6)
5X (0.625)
5X (0.25)
2X (0.35)
(3.675)
(3.8)
SOLDER PASTE EXAMPLE
BASED ON 0.1 mm THICK STENCIL
SCALE: 20X
4224618/A 10/2018
NOTES: (continued)
4. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
www.ti.com
PACKAGE OUTLINE
VQFN-HR - 1 mm max height
PLASTIC QUAD FLATPACK-NO LEAD
RPM0026B
A
4.1
3.9
B
0.100 MIN
3.6
3.4
PIN 1 INDEX AREA
(0.130)
SECTION A-A
TYPICAL
1.0
0.8
C
SEATING PLANE
0.08
C
0.05
0.00
0.525
0.325
5X
3X 0.375±0.05
0.5
0.3
10X
0.1
C A B
(0.2) TYP
0.05
C
7
13
(0.16)
6
14
2X 1
2X 0.5
3X
1.425±0.1
PKG
0
2X 0.5
2X 1
26
25
24
0.3
23X
0.2
0.1
0.05
C
A B
18
2
C
PIN 1 ID
(OPTIONAL)
1
19
23
0.575
0.375
2X
0.625
0.425
6X
4226413/A 11/2020
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
www.ti.com
EXAMPLE BOARD LAYOUT
VQFN-HR - 1 mm max height
PLASTIC QUAD FLATPACK-NO LEAD
RPM0026B
3X 0.375
10X (0.6)
19
23
1
(1.65)
2X (0.675)
(1.6125)
2
18
2X (1)
2X (0.5)
(0)
PKG
3X
1.425
25
26
24
2X (0.5)
2X (1)
14
6
(1.65)
(1.6375)
13
7
5X (0.625)
(R 0.05) TYP
6X (0.725)
23X (0.25)
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE: 20X
0.05 MAX
ALL AROUND
METAL EDGE
EXPOSED METAL
SOLDER MASK
OPENING
NON SOLDER MASK
DEFINED
SOLDER MASK DETAIL
4226413/A 11/2020
NOTES: (continued)
3. For more information, see Texas Instruments literature number SLUA271 (www.ti.com/lit/slua271) .
4. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
www.ti.com
EXAMPLE STENCIL DESIGN
VQFN-HR - 1 mm max height
PLASTIC QUAD FLATPACK-NO LEAD
RPM0026B
3X 0.375
10X (0.6)
19
23
1
(1.65)
2X (0.675)
(1.6125)
2
18
2X (1)
2X (0.5)
(0)
PKG
3X
1.425
25
26
24
2X (0.5)
2X (1)
14
6
(1.65)
(1.6375)
13
7
5X (0.625)
(R 0.05) TYP
6X (0.725)
23X (0.25)
SOLDER PASTE EXAMPLE
BASED ON 0.1 mm THICK STENCIL
SCALE: 20X
4226413/A 11/2020
NOTES: (continued)
5.
Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
www.ti.com
IMPORTANT NOTICE AND DISCLAIMER
TI PROVIDES TECHNICAL AND RELIABILITY DATA (INCLUDING DATA SHEETS), DESIGN RESOURCES (INCLUDING REFERENCE
DESIGNS), APPLICATION OR OTHER DESIGN ADVICE, WEB TOOLS, SAFETY INFORMATION, AND OTHER RESOURCES “AS IS”
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IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NON-INFRINGEMENT OF THIRD
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