TPS552882QWRPMRQ1_技术文档

TPS552882-Q1

SLVSFQ8A – DECEMBER 2020 – REVISED DECEMBER 2021

TPS552882-Q1 36-V, 16-A Buck-boost Converter

1 Features

3 Description

•

AEC-Q100 qualified:

The TPS552882-Q1 is a synchronous four-switch

buck-boost converter capable of regulating the output

voltage at, above, or below the input voltage. The

TPS552882-Q1 operates over 2.7-V to 36-V wide

input voltage and is capable of outputing 0.8-V to 22-

V voltage to support a variety of applications.

– Device temperature grade 1: –40°C to +125°C

ambient operating temperature range

Wide input and output voltage range

– Wide input voltage range: 2.7 V to 36 V

– Wide output voltage range: 0.8 V to 22 V

High efficiency over entire load range

– 97% efficiency at V_IN= 12 V, V_OUT= 20 V and

I_OUT= 3 A

Avoid frequency interference and crosstalk

– Optional clock synchronization

– Programmable switching frequency from 200

kHz to 2.2 MHz

The TPS552882-Q1 integrates two 16-A MOSFETs

of the boost leg to balance the solution size and

efficiency. The TPS552882-Q1 uses external resistor

divider to set the output voltage with 1.2-V intenral

reference voltage. The TPS552882-Q1 is capable of

delivering 100 W from 12-V input voltage.

The TPS552882-Q1 employs an average current-

mode control scheme. The switching frequency is

programmable from 200 kHz to 2.2 MHz by an

external resistor and can be synchronized to an

external clock. The TPS552882-Q1 also provides

optional spread spectrum to minimize peak EMI.

•

EMI mitigation

– Optional programmable spread spectrum

– Lead-less package

Rich protection features

– Output overvoltage protection

– Hiccup mode for output short-circuit protection

– Thermal shutdown protection

– Programmable average inductor current limit up

to 16 A

The TPS552882-Q1 offers output overvoltage

protection, average inductor current limit, cycle-by-

cycle peak current limit, and output short circuit

protection. The TPS552882-Q1 also ensures safe

operating with optional output current limit and hiccup-

mode protection in sustained overload conditions.

•

Small solution size

– Maximum switching frequency up to 2.2 MHz

– 4.0-mm × 3.5-mm HotRod^™QFN package with

wettable flank option

Adjustable output voltage compensation for

voltage droop over the cable

The TPS552882-Q1 can use a small inductor and

small capacitors with high switching frequency. It is

available in a 4.0-mm × 3.5-mm QFN package.

•

Programmable PFM and FPWM mode at light load

Programmable output current limit by sensing

resistor

±1% reference voltage accuracy

Fixed 4-ms soft-start time

Device Information

PART NUMBER

PACKAGE⁽¹⁾

BODY SIZE

TPS552882-Q1

VQFN-HR

4.00 mm × 3.50 mm

•

(1) For all available packages, see the orderable addendum at

the end of the data sheet.

Create a custom design using the TPS552882-Q1

with the WEBENCH^®Power Designer

L1

4.7µH

2 Applications

C5

0.1µF

C4

0.1µF

•

USB PD

DR1H DR1LBOOT1SW1

SW2 BOOT2

VIN = 2.7V to 36V

C1

VOUT = 0.8V to 20V

Automotive infotainment and cluster

Car charger

VIN

VOUT

R7

10mΩ

C2

C3

4.7µF

VCC

PGND

AGND

ISP

R1

PG

CC

ON

EN/UVLO

MODE

TPS552882-Q1

ISN

OFF

FB

R8

COMP

CDC

ILIM

DITH/SYNC

FSW

C6

R3

C7

R2

R4

C8

R5

R2

Typical Application Circuit

An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,

intellectual property matters and other important disclaimers. PRODUCTION DATA.

TPS552882-Q1

SLVSFQ8A – DECEMBER 2020 – REVISED DECEMBER 2021

www.ti.com

Table of Contents

1 Features............................................................................1

2 Applications.....................................................................1

3 Description.......................................................................1

4 Revision History.............................................................. 2

5 Pin Configuration and Functions...................................3

6 Specifications.................................................................. 5

6.1 Absolute Maximum Ratings........................................ 5

6.2 ESD Ratings .............................................................. 5

6.3 Recommended Operating Conditions.........................5

6.4 Thermal Information....................................................5

6.5 Electrical Characteristics.............................................6

6.6 Typical Characteristics................................................9

7 Detailed Description......................................................12

7.1 Overview...................................................................12

7.2 Functional Block Diagram.........................................13

7.3 Feature Description...................................................13

7.4 Device Functional Modes..........................................19

8 Application and Implementation..................................20

8.1 Application Information............................................. 20

8.2 Typical Application.................................................... 20

9 Power Supply Recommendations................................28

10 Layout...........................................................................29

10.1 Layout Guidelines................................................... 29

10.2 Layout Example...................................................... 30

11 Device and Documentation Support..........................31

11.1 Device Support........................................................31

11.2 Receiving Notification of Documentation Updates..31

11.3 Support Resources................................................. 31

11.4 Trademarks............................................................. 31

11.5 Glossary..................................................................31

11.6 Electrostatic Discharge Caution..............................31

12 Mechanical, Packaging, and Orderable

Information.................................................................... 32

4 Revision History

Changes from Revision * (December 2020) to Revision A (December 2021)

Page

•

Added wettable flank option................................................................................................................................1

2

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5 Pin Configuration and Functions

1

19

DR1L

VCC

2

18

DR1H

COMP

3

17

VIN

ILIM

4

16

EN/UVLO

CDC

5

15

PG

MODE

6

14

CC

FB

7

13

DITH/SYNC

ISN

Figure 5-1. 26-pin VQFN-HR RPM Transparent (Top View)

Table 5-1. Pin Functions

NAME

I/O

DESCRIPTION

NO.

1

DR1L

DR1H

VIN

O

Gate driver output for low-side MOSFET in buck side

Gate driver output for high-side MOSFET in buck side

Power supply to the IC from input voltage

2

3

PWR

Enable logic input and programmable input voltage undervoltage lockout (UVLO) input. Logic high

level enables the device. Logic low level disables the device and turns it into shutdown mode.

After the voltage at the EN/UVLO pin is above the logic high voltage of 1.15 V, this pin acts as

programmable UVLO input with 1.23-V internal reference.

4

EN/UVLO

I

Power good indication. When the output voltage is above 95% of the setting output voltage, this pin

outputs high impedance. When the output voltage is below 90% of the setting output voltage, this pin

outputs low level

5

6

PG

CC

O

Constant current output indication

Dithering frequency setting and synchronous clock input. Use a capacitor between this pin and

ground to set the dithering frequency. When this pin is short to ground or pulled above 1.2 V, there

is no dithering function. An external clock can be applied at this pin to synchronize the switching

frequency.

7

DITH/SYNC

I

8

FSW

PGND

AGND

VOUT

I

The switching frequency is programmed by a resistor between this pin and the AGND pin.

Power ground of the IC. It is connected to the source of the low-side MOSFET.

Signal ground of the IC

9, 24

10

PWR

11, 26

Output of the buck-boost converter

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Table 5-1. Pin Functions (continued)

NAME

I/O

DESCRIPTION

NO.

Positive input of the current sense amplifier. An optional current sense resistor connected between

the ISP pin and the ISN pin can limit the output current. If the sensed voltage reaches the current

limit setting value in the register, a slow constant current control loop becomes active and starts to

regulate the voltage between the ISP pin and the ISN pin. Connecting the ISP pin and the ISN pin

together with the VOUT pin can disable the output current limit function.

12

ISP

ISN

I

Negative input of the current sense amplifier. An optional current sense resistor connected between

the ISP pin and the ISN pin can limit the output current. If the sensed voltage reaches the current

limit setting value in the register, a slow constant current control loop becomes active and starts to

regulate the voltage between the ISP pin and the ISN pin. Connecting the ISP pin and the ISN pin

together with the VOUT pin can disable the output current limit function.

13

I

14

15

FB

I

Connect to the center of a resistor divider to program the output voltage.

Setting the operation modes of the TPS55288x to select PFM mode or forced PWM mode in light

load condition and to select the internal LDO or external 5 V for VCC by a resistor between this pin

and AGND.

MODE

Voltage output proportional to the sensed voltage between the ISP pin and the ISN pin. Use a

resistor between this pin and AGND to increase the output voltage to compensate voltage droop

across the cable caused by the cable resistance.

16

CDC

O

Average inductor current limit setting pin. Connect an external resistor between this pin and the

AGND pin.

17

ILIM

COMP

VCC

O

I

Output of the internal error amplifier. Connect the loop compensation network between this pin and

the AGND pin.

18

Output of the internal regulator. A ceramic capacitor of more than 4.7 μF is required between this pin

and the AGND pin.

19

O

I

Power supply for high-side MOSFET gate driver in boost side. A ceramic capacitor of 0.1 µF must be

connected between this pin and the SW2 pin.

20

BOOT2

SW2

The switching node pin of the boost side. It is connected to the drain of the internal low-side power

MOSFET and the source of internal high-side power MOSFET.

21, 25

22

Power supply for high-side MOSFET gate driver in buck side. A ceramic capacitor of 0.1 µF must be

connected between this pin and the SW1 pin.

BOOT1

SW1

I

The switching node pin of the buck side. It is connected to the drain of the external low-side power

MOSFET and the source of external high-side power MOSFET.

23

I

4

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6 Specifications

6.1 Absolute Maximum Ratings

over operating free-air temperature range (unless otherwise noted)⁽¹⁾

MIN

–0.3

MAX

40

UNIT

V

VIN, SW1

DRH1, BOOT1

SW1–0.3

SW1+6

V

VCC, DRL1, PG, CC, ILIM, FSW, COMP, FB, MODE, CDC, DITH/

SYNC

–0.3

6

V

Voltage range

VOUT, SW2, ISP, ISN

–0.3

VOUT-6

-0.3

25

VOUT+6

20

V

at terminals⁽²⁾

ISP, ISN

EN

V

BOOT2

SW2–0.3

–0.3

SW2+6

VCC+0.3

150

V

DRL1, CC, ILIM, FSW, COMP, FB, MODE, CDC, DITH/SYNC

V

(3)

T_J

Operating Junction, T_J

Storage temperature

–40

°C

T_stg

–65

150

(1) Stresses beyond those listed under Absolute Maximum Rating may cause permanent damage to the device. These are stress

ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated

under Recommended Operating Condition. Exposure to absolute-maximum-rated conditions for extended periods may affect device

reliability.

(2) All voltage values are with respect to network ground terminal.

(3) High junction temperatures degrade operating lifetimes. Operating lifetime is de-rated for junction temperatures greater than 125°C.

6.2 ESD Ratings

VALUE

±2000

±500

UNIT

V

Human-body model (HBM), per AEC Q100-002⁽²⁾

(1)

V_(ESD)

Electrostatic discharge

Charged-device model (CDM), per AEC Q100-011, all pins ⁽³⁾

Charged-device model (CDM), per AEC Q100-011, corner pins ⁽³⁾

±750

V

(1) Electrostatic discharge (ESD) to measure device sensitivity and immunity to damage caused by assembly line electrostatic discharges

in to the device.

(2) Level listed above is the passing level per ANSI, ESDA, and JEDEC JS-001. JEDEC document JEP155 states that 500-V HBM allows

safe manufacturing with a standard ESD control process. Manufacturing with less than 500-V HBM is possible with the necessary

precautions.

(3) Level listed above is the passing level per EIA-JEDEC JESD22-C101. JEDEC document JEP157 states that 250-V CDM allows

safe manufacturing with a standard ESD control process. Manufacturing with less than 250-V CDM is possible with the necessary

precautions.

6.3 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted)

MIN

2.7

0.8

1

NOM

MAX

36

UNIT

V

V_IN

V_OUT

L

Input voltage range

Output voltage range

22

V

Effective inductance range

Effective input capacitance range

Effective output capacitance range

Operating junction temperature

4.7

22

10

µH

µF

°C

C_IN

C_OUT

T_J

4.7

10

100

1000

150

–40

6.4 Thermal Information

TPS552882-Q1

THERMAL METRIC⁽¹⁾

VQFN-HR (RPM)-26 PINS VQFN-HR (RPM)-26 PINS

UNIT

Standard

EVM⁽²⁾

R_θJA

Junction-to-ambient thermal resistance

47.5

25.8

°C/W

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UNIT

SLVSFQ8A – DECEMBER 2020 – REVISED DECEMBER 2021

TPS552882-Q1

THERMAL METRIC⁽¹⁾

VQFN-HR (RPM)-26 PINS VQFN-HR (RPM)-26 PINS

Standard

23.8

EVM⁽²⁾

N/A

R_θJC(top)

R_θJB

Junction-to-case (top) thermal resistance

Junction-to-board thermal resistance

°C/W

12.8

N/A

Ψ_JT

Junction-to-top characterization parameter

Junction-to-board characterization parameter

Junction-to-case (bottom) thermal resistance

0.5

0.6

Ψ_JB

12.7

11.6

N/A

R_θJC(bot)

7.8

(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application

report.

(2) Simulated on TPS552882-Q1EVM-045, 4-layer, 2-oz/2-oz/2-oz/2-oz copper 112-mm×71-mm PCB.

6.5 Electrical Characteristics

T_J= -40°C to 125°C, V_IN= 12 V and V_OUT= 20 V. Typical values are at T_J= 25°C, unless otherwise noted.

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

POWER SUPPLY

V_IN

Input voltage range

2.7

2.8

2.6

36

3.0

2.7

V

V_INrising

2.9

V_{VIN_UVLO}

Under voltage lockout threshold

V_INfalling

2.65

IC enabled, no load, no switching. V_IN

= 3 V to 24 V, V_OUT= 0.8 V, V_FB

V_REF+ 0.1 V, R_FSW=100 kΩ, T_Jup to

125°C

=

Quiescent current into the VIN pin

Quiescent current into the VOUT pin

760

860

µA

I_Q

IC enabled, no load, no switching, V_IN

= 2.9 V, V_OUT= 3 V to 20 V, V_FB

V_REF+ 0.1 V, R_FSW=100 kΩ, T_Jup to

125°C

=

760

7

860

10

µA

IC disabled, V_IN= 2.9 V to 14 V, T_Jup

to 125°C

I_SD

Shutdown current into VIN pin

Internal regulator output

V_CC

I_VCC= 50 mA, V_IN= 8 V, V_OUT= 20 V

V_IN= 5.0 V, V_OUT= 20 V, I_VCC= 60 mA

V_IN= 14 V, V_OUT= 5.0 V, I_VCC= 60 mA

5.0

5.2

200

110

5.4

320

170

V

mV

V_{CC_DO}

VCC dropout

EN/UVLO

V_{EN_H}

EN Logic high threshold

EN Logic low threshold

Enable threshold hysteresis

VCC = 2.7 V to 5.5 V

1.15

V

V_{EN_L}

0.4

V_{EN_HYS}

0.05

0.12

1.23

UVLO rising threshold at the EN/UVLO

V_UVLO

VCC = 3.0 V to 5.5 V

1.20

1.26

V

V_{UVLO_HYS}

I_UVLO

UVLO threshold hysteresis

8

14

5

20

mV

µA

Sourcing current at the EN/UVLO pin V_UVLO= 1.3 V

4.5

5.5

OUTPUT

V_OUT

Output voltage range

0.8

22

V

Output overvoltage protection

threshold

V_OVP

22.5

23.5

1

24.5

V_{OVP_HYS}

I_{FB_LKG}

Over voltage protection hysteresis

V

Leakage current at the FB pin

T_Jup to 125°C

100

20

nA

IC disabled, V_OUT= 20 V, V_SW2= 0 V,

T_Jup to 125°C

I_{VOUT_LKG}

Leakage current into the VOUT pin

1

µA

REFERENCE VOLTAGE

V_REF

Reference voltage at the FB pin

1.188

1.2

1.212

V

POWER SWITCH

6

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6.5 Electrical Characteristics (continued)

T_J= -40°C to 125°C, V_IN= 12 V and V_OUT= 20 V. Typical values are at T_J= 25°C, unless otherwise noted.

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

Low-side MOSFET on resistance on

boost side

V_OUT= 20 V, V_CC= 5.2 V

7.1

mΩ

R_DS(on)

High-side MOSFET on resistance on

boost side

V_OUT= 20 V, V_CC= 5.2 V

7.6

mΩ

INTERNAL CLOCK

R_FSW= 100 kΩ

R_FSW= 9.09 kΩ

Boost mode

180

200

2200

100

90

220

2400

145

kHz

ns

f_SW

Switching frequency

2000

t_{OFF_min}

t_{ON_min}

V_FSW

Min. off time

Min. on-time

Buck mode

130

ns

Voltage at the FSW pin

1

V

CURRENT LIMIT

R_ILIM= 20 kΩ, V_IN= 8 V, V_OUT= 20 V,

f_SW= 500 kHz, FPWM

14

4

16.5

5.5

25

19

A

R_ILIM= 20 kΩ, V_IN= 8 V, V_OUT= 20 V,

f_SW= 500 kHz, PFM

I_{LIM_AVG}

Average inductor current limit

R_ILIM= 60 kΩ, V_IN= 5 V, V_OUT= 14 V,

f_SW= 2.2 MHz, FPWM

R_ILIM= 60 kΩ, V_IN= 5 V, V_OUT= 14 V,

f_SW= 2.2 MHz, PFM

4

R_ILIM= 20 kΩ, V_IN= 8 V, V_OUT= 20 V,

f_SW= 500 kHz, FPWM

I_{LIM_PK}

Peak inductor current limit at high side

Voltage at the ILIM pin

R_ILIM= 20 kΩ, V_IN= 8 V, V_OUT= 20 V,

f_SW= 500 kHz, PFM

25

V_ILIM

V_SNS

VOUT = 3 V

0.6

50

30

V

V_ISN= 2 V to 21 V

48

28

52

32

mV

Current loop regulation voltage

between the ISP and ISN pins

CABLE VOLTAGE DROP COMPENSATION

R_CDC= 20 kΩ or floating, V_ISP– V_ISN

50 mV

=

0.95

7.23

1

40

7.5

0

1.05

75

V

V_CDC

Voltage at the CDC pin

FB pin sinking current

R_CDC= 20 kΩ or floating, V_ISP– V_ISN

2 mV

=

mV

µA

External output feedback, R_CDC= 20

kΩ, V_ISP– V_ISN= 50 mV

7.87

0.3

External output feedback, R_CDC= 20

kΩ, V_ISP– V_ISN= 0 mV

I_{FB_CDC}

External output feedback, R_CDC

floating, V_ISP– V_ISN= 50 mV

=

0

0.3

ERROR AMPLIFIER

V_FB= V_REF+ 400 mV, V_COMP= 1.5 V,

VCC = 5 V

I_SINK

COMP pin sink current

20

60

µA

V_FB= V_REF- 400 mV, V_COMP= 1.5 V,

VCC = 5 V

I_SOURCE

COMP pin source current

V_CCLPH

V_CCLPL

G_EA

High clamp voltage at the COMP pin

Low clamp voltage at the COMP pin

Error amplifier transconductance

1.8

0.7

V

190

µA/V

SOFT START

t_SS

Soft-start time

3

4

5

ms

V

DR1H GATE DRIVER

V_{DR1H_L}

Low-state voltage drop

V_DR1H– V_SW1, 100-mA sinking

0.1

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6.5 Electrical Characteristics (continued)

T_J= -40°C to 125°C, V_IN= 12 V and V_OUT= 20 V. Typical values are at T_J= 25°C, unless otherwise noted.

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

V_{DR1H_H}

High-state voltage drop

V_BOOT1– V_DR1H, 100-mA sourcing

0.2

V

DR1L GATE DRIVER

V_{DR1L_L}Low-state voltage drop

V_{DR1L_H}High-state voltage drop

SPREAD SPECTRUM

100-mA sinking

0.1

0.2

V

V_CC– V_DR1L, 100-mA sourcing

V_DITH/SYNC= 1.0 V, R_FSW= 49.9 kΩ;

voltage rising from 0.85 V

I_{DITH_CHG}

I_{DITH_DIS}

Dithering charge current

2

µA

V_DITH/SYNC= 1.0 V, R_FSW= 49.9 kΩ;

voltage falling from 1.15 V

Dithering discharge current

V_{DITH_H}

V_{DITH_L}

Dither high threshold

Dither low threshold

1.07

0.93

V

SYNCHRONOUS CLOCK

V_{SNYC_H}

V_{SYNC_L}

t_{SYNC_MIN}

HICCUP

t_HICCUP

Sync clock high voltage threshold

1.2

V

Sync clock low voltage threshold

Minimum sync clock pulse width

0.4

50

ns

Hiccup off time

76

ms

MODE RESISTANCE DETECTION

I_MODE

Sourcing current from the MODE pin

V_MODE= 2.5 V

9

0.571

0.322

0.169

10

0.614

0.351

0.189

11

0.657

0.380

0.209

µA

V

V_{MODE_DT1}

V_{MODE_DT2}

V_{MODE_DT3}

Detection threshold voltage at the

MODE pin

V

LOGIC INTERFACE

Leakage current into PG pin when

outputting high impedance

I_{PG_H}

V_{PG_L}

I_{CC_H}

V_PG= 5 V

100

0.2

100

0.2

nA

V

Output low voltage range of the PG pin Sinking 4-mA current

0.1

Leakage current into CC pin when

V_CC= 5 V

nA

V

outputting high impedance

V_{CC_L}

Output low voltage range of the CC pin Sinking 4-mA current

PROTECTION

T_SD

Thermal shutdown threshold

Thermal shutdown hysteresis

T_Jrising

175

20

°C

T_{SD_HYS}

T_Jfalling below TSD

8

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6.6 Typical Characteristics

V_IN= 12 V, T_A= 25°C, f_SW= 400 kHz, unless otherwise noted.

100%

90%

80%

70%

60%

50%

40%

100%

90%

80%

70%

60%

50%

40%

30%

20%

10%

0

30%

V_IN= 5 V

V_IN= 9 V

V_IN= 12 V

V_IN= 20 V

V_IN= 5 V

V_IN= 9 V

V_IN= 12 V

V_IN= 20 V

20%

10%

0

0.0001

0.001

0.01 0.1 0.2 0.5

Output Current (A)

1

2 3 5 710

0.0001

0.001

0.01 0.1 0.2 0.5

Output Current (A)

1

2 3 5 710

D001

D002

Figure 6-1. Efficiency vs Output Current,

V_OUT= 5 V, FPWM

Figure 6-2. Efficiency vs Output Current,

V_OUT= 5 V, PFM

100%

90%

80%

70%

60%

50%

40%

30%

20%

10%

0

90%

80%

70%

60%

50%

40%

30%

20%

10%

0

V_IN= 5 V

V_IN= 9 V

V_IN= 12 V

V_IN= 20 V

V_IN= 5 V

V_IN= 9 V

V_IN= 12 V

V_IN= 20 V

0.0001

0.001

0.01 0.1 0.2 0.5

Output Current (A)

1

2 3 5 710

0.0001

0.001

0.01 0.1 0.2 0.5

Output Current (A)

1

2 3 5 710

D003

D004

Figure 6-3. Efficiency vs Output Current,

V_OUT= 9 V, FPWM

Figure 6-4. Efficiency vs Output Current,

V_OUT= 9 V, PFM

100%

90%

80%

70%

60%

50%

40%

30%

20%

10%

0

90%

80%

70%

60%

50%

40%

30%

20%

10%

0

V_IN= 5 V

V_IN= 9 V

V_IN= 12 V

V_IN= 20 V

V_IN= 5 V

V_IN= 9 V

V_IN= 12 V

V_IN= 20 V

0.0001

0.001

0.01 0.1 0.2 0.5

Output Current (A)

1

2 3 5 710

0.0001

0.001

0.01 0.1 0.2 0.5

Output Current (A)

1

2 3 5 710

D005

D006

Figure 6-5. Efficiency vs Output Current,

V_OUT= 12 V, FPWM

Figure 6-6. Efficiency vs Output Current,

V_OUT= 12 V, PFM

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100%

90%

80%

70%

60%

50%

40%

30%

20%

10%

0

100%

90%

80%

70%

60%

50%

40%

30%

20%

10%

0

V_IN= 5 V

V_IN= 9 V

V_IN= 12 V

V_IN= 20 V

V_IN= 5 V

V_IN= 9 V

V_IN= 12 V

V_IN= 20 V

0.0001

0.001

0.01 0.1 0.2 0.5

Output Current (A)

1

2 3 5 710

0.0001

0.001

0.01 0.1 0.2 0.5

Output Current (A)

1

2 3 5 710

D007

D008

Figure 6-7. Efficiency vs Output Current,

V_OUT= 15 V, FPWM

Figure 6-8. Efficiency vs Output Current,

V_OUT= 15 V, PFM

100%

90%

80%

70%

60%

50%

40%

30%

20%

10%

0

90%

80%

70%

60%

50%

40%

30%

20%

10%

0

V_IN= 5 V

V_IN= 9 V

V_IN= 12 V

V_IN= 20 V

V_IN= 5 V

V_IN= 9 V

V_IN= 12 V

V_IN= 20 V

0.0001

0.001

0.01 0.1 0.2 0.5

Output Current (A)

1

2 3 5 710

0.0001

0.001

0.01 0.1 0.2 0.5

Output Current (A)

1

2 3 5 710

D009

D010

Figure 6-9. Efficiency vs Output Current,

V_OUT= 20 V, FPWM

Figure 6-10. Efficiency vs Output Current,

V_OUT= 20 V, PFM

18

2200

2000

1800

1600

1400

1200

1000

800

V_IN= 20 V, V_OUT= 5 V

V_IN= 12 V, V_OUT= 12 V

V_IN= 5 V, V_OUT= 20 V

17

16

15

14

13

12

11

10

9

8

7

600

6

5

400

4

200

3

2

0

20

30

40

50

60

70

80

90

100

0

10

20

30

40

50

60

70

80

90 100

Resistance (kW)

Figure 6-11. Average Inductor Current Limit vs

Setting Resistance

Figure 6-12. Switching Frequency vs Setting

Resistance

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1.218

780

775

770

765

760

755

750

745

1.212

1.206

1.2

1.194

1.188

1.182

Into V_IN, V_IN= 24 V, V_OUT= 3 V

Into V_OUT, V_IN= 3.1 V, V_IN= 20 V

-40

-20

0

20

40

60

80

100 120 140

-40

-20

0

20

40

60

80

100 120 140

Temperature (èC)

D017

Figure 6-13. Reference Voltage vs Temperature

(V_REF= 1.2 V)

Figure 6-14. Quiescent Current vs Temperature

7.5

7.25

7

1.2355

1.235

1.2345

1.234

1.2335

1.233

1.2325

1.232

1.2315

1.231

1.2305

1.23

6.75

6.5

6.25

6

5.75

-40

-20

0

20

40

60

80

100 120 140

-40

-20

0

20

40

60

80

100 120 140

Temperature (èC)

D018

D019

Figure 6-15. Shutdown Current vs Temperature

Figure 6-16. ENABLE/UVLO Rising Threshold vs

Temperature

2500

2000

1500

1.6

1.4

1.2

1

0.8

0.6

0.4

0.2

0

1000

f_SW= 200 kHz

f_SW= 2200 kHz

500

0

-40

-20

0

20

40

60

80

100 120 140

0

1

2

3

Output Current (A)

4

5

6

7

8

Temperature (èC)

D020

D021

Figure 6-17. Switching Frequency vs Temperature

Figure 6-18. CDC Voltage vs Output Current with

R_SENSE= 10 mΩ

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7 Detailed Description

7.1 Overview

The TPS552882-Q1 is a 16-A buck-boost DC-to-DC converter with the two boost MOSFETs integrated. The

TPS552882-Q1 can operate over a wide range of 2.7-V to 36-V input voltage and 0.8-V to 22-V output voltage.

It can transition among buck mode, buck-boost mode, and boost mode smoothly according to the input voltage

and the set output voltage. The TPS552882-Q1 operates in buck mode when the input voltage is greater than

the output voltage and in boost mode when the input voltage is less than the output voltage. When the input

voltage is close to the output voltage, the TPS552882-Q1 operates in one-cycle buck and one-cycle boost mode

alternately.

The TPS552882-Q1 uses an average current mode control scheme. Current mode control provides simplified

loop compensation, rapid response to the load transients, and inherent line voltage rejection. An error amplifier

compares the feedback voltage with the internal reference voltage. The output of the error amplifier determines

the average inductor current.

An internal oscillator can be configured to operate over a wide range of frequency from 200 kHz to 2.2 MHz. The

internal oscillator can also synchronize to an external clock applied to the DITH/SYNC pin. To minimize EMI, the

TPS552882-Q1 can dither the switching frequency at ±7% of the set frequency.

The TPS552882-Q1 works in fixed-frequency PWM mode at moderate to heavy load currents. In light load

condition, the TPS552882-Q1 can be configured to automatically transition to PFM mode or be forced in PWM

mode by either connecting a resistor at the MODE pin or setting the corresponding bit in an internal register.

On TPS552882-Q1, you can use an external resistor divider to program the output voltage. The TPS552882-Q1

also can limit the output current by placing a current sense resistor in the output path. These two functions

support the programmable power supply (PPS) feature of the USB-PD.

The TPS552882-Q1 provides average inductor current limit set by a resistor at the ILIM pin. In addition, it

provides cycle-by-cycle peak inductor current limit during transient to protect the device against overcurrent

condition beyond the capability of the device.

A precision voltage threshold of 1.23 V with 5-µA sourcing current at the EN/UVLO pin supports programmable

input undervoltage lockout (UVLO) with hysteresis. The output overvoltage protection (OVP) feature turns off the

high-side FETs to prevent damage to the devices powered by the TPS552882-Q1.

The device provides hiccup mode option to reduce the heating in the power components when output short

circuit happens. When the hiccup mode is enabled, the TPS552882-Q1 turns off for 76 ms and restarts at soft

start-up.

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7.2 Functional Block Diagram

L1

VIN

C3

C4

C8

SW1

BOOT1

BOOT2

SW2

R1

VOUT

C2

VIN

VOUT

LDO

Current

Sense

C1

VCC

CDC

R7

I-V

C5

DL

I_limit

ISP

ISN

Buck-Boost

Control

DH

Iref

CC or FB

COMP

Gm

MODE

ADC

BOOST

BUCK

R3

R2

C6

Vref

DAC

CC

PG

PGND

AGND

ILIM

Logic Core

EN/UVLO

Iref

Vref

DAC

V_SYNC/DITH

1.0V

I_limit

VIN

VCC

VIN UVLO

VOUT OVP

Thermal

FSW

VOUT

R5

f_MOD

R4

DITH/SYNC

C7

7.3 Feature Description

7.3.1 VCC Power Supply

An internal LDO to supply the TPS552882-Q1 outputs regulated 5.2-V voltage at the VCC pin with 60-mA output

current capability. When V_INis less than V_OUT, the internal LDO selects the power supply source by comparing

V_INto a rising threshold of 6.2 V with 0.3-V hysteresis. When V_INis higher than 6.2 V, the supply for LDO is V_IN.

When V_INis lower than 5.9 V, the supply for LDO is V_OUT. When V_OUTis less than V_IN, the internal LDO selects

the power supply source by comparing V_OUTto a rising threshold of 6.2 V with 0.3-V hysteresis. When V_OUTis

higher than 6.2 V, the supply for LDO is V_OUT. When V_OUTis lower than 5.9 V, the supply for LDO is V_IN. Table

7-1 shows the supply source selection for the internal LDO.

Table 7-1. V_CCPower Supply Logic

V_IN

V_OUT

INPUT for V_CCLDO

V_IN> 6.2 V

V_IN< 5.9 V

V_IN> V_OUT

V_OUT>V_IN

V_OUT> 6.2 V

V_OUT< 5.9 V

V_IN

V_OUT

V_IN

To minimize the power dissipation of the internal LDO when both input voltage and output voltage are high, an

external 5-V power source can be applied at the VCC pin to supply the TPS552882-Q1. The external 5-V power

supply must have at least 100-mA output current capability and must be within the 4.75-V to 5.5-V regulation

range. To use an external power supply for V_CC, a resistor with proper resistance must be connected to the

MODE pin.

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7.3.2 Operation Mode Setting

By placing different resistors between the MODE pin and the AGND pin, the TPS552882-Q1 selects the internal

power supply or external power supply for V_CC, and also selects the PFM mode or forced PWM mode in light

load conditions.Table 7-2 shows the resistance values for each selection.

Table 7-2. V_CCSource and PFM/PWM Programming

RESISTOR VALUE (kΩ)

V_CCSOURCE

OPERATING MODE AT LIGHT LOAD

0

Internal

PWM

PFM

PWM

PFM

24.9

51.1

Open

Internal

External

7.3.3 Input Undervoltage Lockout

When the input voltage is below 2.6 V, the TPS552882-Q1 is disabled. When the input voltage is above 3 V, the

TPS552882-Q1 can be enabled by pulling the EN pin to a high voltage above 1.3 V.

7.3.4 Enable and Programmable UVLO

The TPS552882-Q1 has a dual function enable and undervoltage lockout (UVLO) circuit. When the input voltage

at the VIN pin is above the input UVLO rising threshold of 3 V and the EN/UVLO pin is pulled above 1.15 V but

less than the enable UVLO threshold of 1.23 V, the TPS552882-Q1 is enabled but still in standby mode. The

TPS552882-Q1 starts to detect the resistance between the MODE pin and ground. After that, the TPS55288x

selects the power supply for V_CCand the PFM or FPWM mode for light load condition accordingly.

The EN/UVLO pin has an accurate UVLO voltage threshold to support programmable input undervoltage lockout

with hysteresis. When the EN/UVLO pin voltage is greater than the UVLO threshold of 1.23 V, the TPS552882-

Q1 is enabled for switching operation. A hysteresis current I_{UVLO_HYS}of 5 μA is sourced out of the EN/UVLO

pin to provide hysteresis that prevents on/off chattering in the presence of noise with a slowly changing input

voltage.

By using resistor divider as shown in Figure 7-1, the turnon threshold is calculated using Equation 1.

R1

8

= 8

× (1 +

)

+0(78.1 _10)

78.1

4

2

(1)

where

V_UVLOis the UVLO threshold of 1.23 V at the EN/UVLO pin

•

The hysteresis between the UVLO turnon threshold and turnoff threshold is set by the upper resistor in the

EN/UVLO resistor divider and is given by the Equation 2.

¿8

= +_{78.1_*;5}× 41

+0(78.1)

(2)

where

•

I_{UVLO_HYS}is the sourcing current from the EN/UVLO pin when the voltage at the EN/UVLO pin is above

V_UVLO

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VIN

I_{UVLO_HYS}

R1

EN/UVLO

Enable

R2

C1

UVLO Comparator

1.23V

Figure 7-1. Programmable UVLO With Resistor Divider at the EN/UVLO Pin

Using an NMOS FET together with resistor divider can implement both logic enable and programmable UVLO

as shown in Figure 7-2. The EN logic high level must be greater than enable threshold plus the V_thof the

NMOSFET Q1. The Q1 also eliminates the leakage current from VIN to ground through the UVLO resistor

divider during shutdown mode.

VIN

R1

I_{UVLO_HYS}

EN

EN/UVLO

Enable

R2

C1

UVLO Comparator

1.23V

Figure 7-2. Logic Enable and Programmable UVLO

7.3.5 Soft Start

When the input voltage is above the UVLO threshold and the voltage at the EN/UVLO pin is above the enable

UVLO threshold, the TPS552882-Q1 starts to ramp up the output voltage by ramping an internal reference

voltage from 0 V to a voltage which is set by 1.2 V on the TPS552882-Q1 within 4 ms.

7.3.6 Shutdown

When the EN pin voltage is pulled below 0.4 V, the TPS552882-Q1 is in shutdown mode, and all functions are

disabled.

7.3.7 Switching Frequency

The TPS552882-Q1 uses a fixed frequency average current control scheme. The switching frequency is

between 200 kHz and 2.2 MHz set by placing a resistor at the FSW pin. An internal amplifier holds this pin

at a fixed voltage of 1 V. The setting resistance is between maximum of 100 kΩ and minimum of 9.09 kΩ. Use

Equation 3 to calculate the resistance by a given switching frequency.

1000

B

=

(MHz)

59

0.05 × 4₍₅₉+ 20

(3)

where

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•

R_FSWis the resistance at the FSW pin

For noise-sensitive applications, the TPS552882-Q1 can be synchronized to an external clock signal applied

to the DITH/SYNC pin. The duty cycle of the external clock is recommended in the range of 30% to 70%. A

resistor also must be connected to the FSW pin when the TPS552882-Q1 is switching by the external clock. The

external clock frequency at the DITH/SYNC pin must have lower than 0.4-V low level voltage and must be within

±30% of the corresponding frequency set by the resistor. Figure 7-3 is a recommended configuration.

External Clock

DITH/SYNC

FSW

R_FSW

Figure 7-3. External Clock Configuration

7.3.8 Switching Frequency Dithering

The TPS552882-Q1 provides an optional switching frequency dithering that is enabled by connecting a capacitor

from the DITH/SYNC pin to ground. Figure 7-4 illustrates the dithering circuit. By charging and discharging the

capacitor, a triangular waveform centered at 1 V is generated at the DITH/SYNC pin. The triangular waveform

modulates the oscillator frequency by ±7% of the nominal frequency set by the resistance at the FSW pin. The

capacitance at the DITH/SYNC pin sets the modulation frequency. A small capacitance modulates the oscillator

frequency at a fast rate than a large capacitance. For the dithering circuit to effectively reduce peak EMI, the

modulation rate normally is below 1 kHz. Equation 4 calculates the capacitance required to set the modulation

frequency, F_MOD

.

1

%

=

(()

&+6*

2.8 × 4₍₅₉× (_/1&

(4)

where

•

R_FSWis the switching frequency setting resistance (Ω) at the FSW pin

F_MODis the modulation frequency (Hz) of the dithering

Connecting the DITH/SYNC pin below 0.4 V or above 1.2 V disables switching frequency dithering. The dithering

function also is disabled when an external synchronous clock is used.

1.07V

1.0V

0.93V

DITH/SYNC

C_DITH

F_MOD

FSW

R_FSW

Figure 7-4. Switching Frequency Dithering

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7.3.9 Inductor Current Limit

The TPS552882-Q1 implements both peak current and average inductor current limit by a resistor connected

to the ILIM pin. The average current mode control loop uses the current sense information at the high-side

MOSFET of the boost leg to clamp the maximum average inductor current to 16.5 A (typical) when the resistor

is 20 kΩ. Use large resistance to get smaller average inductor current limit. Use Equation 5 to calculate the

resistance for a desired average inductor current limit.

min(1,0.6 ×8₁₇₆)× 330000

+

=

(#)

#8)_.+/+6

4_+.+/

(5)

where

•

I_{AVG_LIMIT}is the average inductor current limit

R_ILIMis the resistance (Ω) between the ILIM pin and analog ground

Besides the average current limit, a peak current limit protection is implemented during transient to protect the

device against over current condition beyond the capability of the device.

7.3.10 Internal Charge Path

Each of the two high-side MOSFET drivers is biased from its floating bootstrap capacitor, which is normally

re-charged by V_CCthrough both the external and internal bootstrap diodes when the low-side MOSFET is turned

on. When the TPS55288 operates exclusively in the buck or boost regions, one of the high-side MOSFETs is

constantly on. An internal charge path, from VOUT and BOOT2 to BOOT1 or from VIN and BOOT1 to BOOT2,

charges the bootstrap capacitor to V_CCso that the high-side MOSFET remains on.

7.3.11 Output Voltage Setting

There are two ways to set the output voltage: changing the feedback ratio and changing the reference voltage.

The TPS552882-Q1 uses an external resistor divider to change the feedback ratio with fixed 1.2-V reference

voltages at the FB pin.

When using external output voltage feedback resistor divider as shown in Figure 7-5. Use Equation 6 to

calculate the output voltage with the reference voltage at the FB pin.

4_{($_72}

V₁₇₆= 8 × (1 +

)

4'(

4_{($_$6}

(6)

R_SNS

V_OUT

VOUT

ISP

R_{FB_UP}

ISN

FB

R_{FB_BT}

Figure 7-5. Output Voltage Setting by External Resistor Divider

TI recommends using 100 kΩ for the up resistor R_{FB_UP}. The reference voltage V_REFat the FB pin is 1.2 V.

7.3.12 Output Current Indication and Cable Voltage Drop Compensation

The TPS55288 outputs a voltage at the CDC pin proportional to the sensed voltage across a output current

sensing resistor between the ISP pin and the ISN pin. Equation 7 shows the exact voltage at the CDC pin related

to the sensed output current.

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V_%&%= 20 × (8 F 8

)

+52

+50

(7)

To compensate the voltage drop across a cable from the terminal of the USB port to its powered device, the

TPS552882-Q1 can lift its output voltage in proportion to the load current by placing a resistor between the CDC

pin and AGND pin.

When using external output voltage feedback on the TPS552882-Q1, the output voltage rises in proportional to

the current sourcing from the CDC pin through the resistor at the CDC pin. It is recommended to use 100-kΩ

resistance for the up resistor of the resistor divider. Equation 8 shows the output voltage rise versus the sensed

output current, resistance at the CDC pin and the up resistor of the output voltage feedback resistor divider.

8

F 8

+50

+52

V_{176_%&%}= 3 × 4_{($_72}× (

)

4_%&%

(8)

where

•

R_{FB_UP}is the up resistor of the resistor divider between the output and the FB/INT pin

R_CDCis the resistor at the CDC pin

When RFB_UP is 100 kΩ, the output voltage rise versus the sensed output current and the resistor at the CDC

pin is shown in Figure 7-6

V_{OUT_CDC}(V)

0.8

R_CDC=20K

0.75V

0.5V

0.7

0.6

0.5

0.4

0.3

0.2

0.1

R_CDC=30K

R_CDC=75K

0.2V

0.1V

R_CDC=150K

R_CDC=floating

40

V_ISPœ V_ISN

(mV)

10

20

30

50

Figure 7-6. Output Voltage Rise versus Output Current

7.3.13 Integrated Gate Drivers

The TPS552882-Q1 provides two N-channel MOSFET gate drivers for buck side. Each driver is capable of

sourcing 1-A and sinking 1.8-A peak current. In buck operation, the DR1H pin and the DR1L pin are switched by

the PWM controller. In boost mode, the DR1H pin remains at continuously high voltage to turn on the high-side

MOSFET of the buck side, and the DR1L pin remains at continuously low voltage to turn off the low-side

MOSFET of the buck side.

In DCM buck mode operation, the DR1L turns off the low-side FET when the inductor current drops to zero.

The low-side gate driver is powered from the VCC pin, and the high-side gate driver is powered from the

bootstrap capacitor C_BOOT1, which is between the BOOT1 pin and the SW1 pin.

7.3.14 Output Current Limit

The output current limit is programmable by placing a current sensing resistor between the ISP pin and ISN pin.

The voltage limit between the ISP pin and the ISN pin is set to 50 mV. Thus a smaller resistance gets higher

current limit and a bigger resistance gets lower current limit.

Connecting the ISP pin and ISN pin together to the VOUT pin disables the current limit function.

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7.3.15 Overvoltage Protection

The TPS552882-Q1 has output overvoltage protection. When the output voltage at the VOUT pin is detected

above 23.5 V typically, the TPS552882-Q1 turns off two high-side FETs and turns on two low-side FETs until its

output voltage drops the hysteresis value lower than the output overvoltage protection threshold. This function

prevents overvoltage on the output and secures the circuits connected to the output from excessive overvoltage.

7.3.16 Output Short Circuit Protection

In addition to the average inductor current limit, the TPS552882-Q1 implements the output short-circuit

protection by entering the hiccup mode. When the output short circuit happens, the TPS552882-Q1 goes into

output current limit first. If the output voltage is below 0.8 V and the average inductor current is above the setting

value, the TPS552882-Q1 shuts down the switching for 76 ms (typical) and restarts the soft start repeatedly.

The hiccup mode helps reduce the total power dissipation on the TPS552882-Q1 in the output short-circuit or

overcurrent condition.

7.3.17 Thermal Shutdown

The TPS552882-Q1 is protected by a thermal shutdown circuit that shuts down the device when the internal

junction temperature exceeds 175°C (typical). The internal soft-start circuit is reset but all internal registers

values remain unchanged when thermal shutdown is triggered. The converter automatically restarts when

the junction temperature drops below the thermal shutdown hysteresis of 20°C below the thermal shutdown

threshold.

7.4 Device Functional Modes

In light load condition, the TPS552882-Q1 can work in PFM or forced PWM mode to meet different application

requirements. The PFM mode decreases switching frequency to reduce the switching loss thus it gets high

efficiency at light load condition. The FPWM mode keeps the switching frequency unchanged to avoid undesired

low switching frequency but the efficiency becomes lower than that of PFM mode.

7.4.1 PWM Mode

In FPWM mode, the TPS552882-Q1 keeps the switching frequency unchanged in light load condition. When

the load current decreases, the output of the internal error amplifier decreases as well to reduce the average

inductor current down to deliver less power from input to output. When the output current further reduces, the

current through the inductor decreases to zero during the switch-off time. The high-side N-MOSFET is not turned

off even if the current through the MOSFET is zero. Thus, the inductor current changes its direction after it runs

to zero. The power flow is from output side to input side. The efficiency is low in this condition. However, with

the fixed switching frequency, there is no audible noise or other problems that might be caused by low switching

frequency in light load condition.

7.4.2 Power Save Mode

The TPS552882-Q1 improves the efficiency at light load condition with the PFM mode. By connecting an

appropriate resistor at the MODE pin or enabling the PFM function in the internal register, the TPS552882-Q1

can work in PFM mode at light load condition. When the TPS552882-Q1 operates at light load condition, the

output of the internal error amplifier decreases to make the inductor peak current down to deliver less power to

the load. When the output current further reduces, the current through the inductor will decrease to zero during

the switch-off time. When the TPS552882-Q1 works in buck mode, once the inductor current becomes zero, the

low-side switch of the buck side is turned off to prevent the reverse current from output to ground. When the

TPS552882-Q1 works in boost mode, once the inductor current becomes zero, the high side-switch of the boost

side is turned off to prevent the reverse current from output to input. The TPS552882-Q1 resumes switching until

the output voltage drops. Thus the PFM mode reduces switching cycles and eliminates the power loss by the

reverse inductor current to get high efficiency in light load condition.

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8 Application and Implementation

Note

Information in the following applications sections is not part of the TI component specification,

and TI does not warrant its accuracy or completeness. TI’s customers are responsible for

determining suitability of components for their purposes, as well as validating and testing their design

implementation to confirm system functionality.

8.1 Application Information

The TPS552882-Q1 can operate over a wide range of 2.7-V to 36-V input voltage and output 0.8 V to 22 V. It

can transition among buck mode, buck-boost mode, and boost mode smoothly according to the input voltage

and the setting output voltage. The TPS552882-Q1 operates in buck mode when the input voltage is greater

than the output voltage and in boost mode when the input voltage is less than the output voltage. When the input

voltage is close to the output voltage, the TPS552882-Q1 operates in one-cycle buck and one-cycle boost mode

alternately. The switching frequency is set by an external resistor. To reduce the switching power loss in high

power conditions, it is recommended to set the switching frequency below 500 kHz. If a system requires higher

switching frequency above 500 kHz, it is recommended to set the lower switch current limit for better thermal

performance.

8.2 Typical Application

The TPS552882-Q1 provides a small size solution for USB PD power supply application with the input voltage

ranging from 9 V to 36 V.

L1

4.7µH

C5

C4

0.1µF

SW1

BOOT2

DR1H

VIN

DR1L BOOT1

SW2

VIN = 9V to 36V

VOUT = 5V

VOUT

R7

10mΩ

C1

C2

4 x 10µF

VCC

C3

4.7µF

4 x 22µF

PGND

AGND

ISP

R1

PG

100kΩ

CC

ON

EN/UVLO

MODE

TPS552882-Q1

ISN

OFF

FB

R8

6.19kΩ

COMP

CDC

ILIM

DITH/SYNC

FSW

C6

R3

C7

R2

R4

29.4kΩ

150kΩ

C8

0.01µF

R5

19.9kΩ

R2

49.9kΩ

Figure 8-1. 5-V Power Supply With 9-V to 36-V Input Voltage

8.2.1 Design Requirements

The design parameters are listed in Table 8-1:

20

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Table 8-1. Design Parameters

PARAMETERS

Input voltage

VALUES

9 V to 36 V

5 V to 20 V

5 A

Output voltage

Output current limit

Output voltage ripple

±50 mV

PFM

Operating mode at light load

8.2.2 Detailed Design Procedure

8.2.2.1 Custom Design With WEBENCH® Tools

Click here to create a custom design using the TPS552882-Q1 device with the WEBENCH® Power Designer.

1. Start by entering the input voltage (V_IN), output voltage (V_OUT), and output current (I_OUT) requirements.

2. Optimize the design for key parameters such as efficiency, footprint, and cost using the optimizer dial.

3. Compare the generated design with other possible solutions from Texas Instruments.

The WEBENCH Power Designer provides a customized schematic along with a list of materials with real-time

pricing and component availability.

In most cases, these actions are available:

•

Run electrical simulations to see important waveforms and circuit performance

Run thermal simulations to understand board thermal performance

Export customized schematic and layout into popular CAD formats

Print PDF reports for the design, and share the design with colleagues

Get more information about WEBENCH tools at www.ti.com/WEBENCH.

8.2.2.2 Switching Frequency

The switching frequency of the TPS552882-Q1 is set by a resistor at the FSW pin. Use Equation 3 to calculate

the resistance for the desired frequency. To reduce the switching power loss with such a high current application,

a 1% standard resistor of 49.9 kΩ is selected for 400-kHz switching frequency for this application.

8.2.2.3 Output Voltage Setting

An external resistor divider is used to program the output voltage.

8.2.2.4 Inductor Selection

Since the selection of the inductor affects steady state operation, transient behavior, and loop stability, the

inductor is the most important component in power regulator design. There are three important inductor

specifications: inductance, saturation current, and DC resistance.

The TPS552882-Q1 is designed to work with inductor values between 1 µH and 10 µH. The inductor selection is

based on consideration of both buck and boost modes of operation.

For buck mode, the inductor selection is based on limiting the peak-to-peak current ripple to the maximum

inductor current at the maximum input voltage. In CCM, Equation 9 shows the relationship between the

inductance and the inductor ripple current.

k

o

V_IN(MAX)-V_OUT×V_OUT

L=

∆I_L(P-P)×f_SW×V_{IN MAX}

:

;

(9)

where

•

V_IN(MAX)is the maximum input voltage

V_OUTis the output voltage

ΔI_L(P-P)is the peak to peak ripple current of the inductor

f_SWis the switching frequency

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For a certain inductor, the inductor ripple current achieves maximum value when V_OUTequals half of

the maximum input voltage. Choosing higher inductance gets smaller inductor current ripple while smaller

inductance gets larger inductor current ripple.

For boost mode, the inductor selection is based on limiting the peak-to-peak current ripple to the maximum

inductor current at the maximum output voltage. In CCM, Equation 10 shows the relationship between the

inductance and the inductor ripple current.

k

V_IN× V_OUT(MAX)-V_IN

o

L=

∆I_L(P-P)×f_SW×V_OUT(MAX)

(10)

where

•

V_INis the input voltage

V_OUT(MAX)is the maximum output voltage

ΔI_L(P-P)is the peak to peak ripple current of the inductor

f_SWis the switching frequency

For a certain inductor, the inductor ripple current achieves maximum value when V_INequals to the half of

the maximum output voltage. Choosing higher inductance gets smaller inductor current ripple while smaller

inductance gets larger inductor current ripple.

For this application example, a 4.7-µH inductor is selected, which produces approximate maximum inductor

current ripple of 50% of the highest average inductor current in buck mode and 50% of the highest average

inductor current in boost mode.

In buck mode, the inductor DC current equals to the output current. In boost mode, the inductor DC current can

be calculated with Equation 11.

V_OUT×I_OUT

I_L(DC)

=

V_IN×ꢀ

(11)

where

•

V_OUTis the output voltage

I_OUTis the output current

V_INis the input voltage

η is the power conversion efficiency

For a given maximum output current of the buck-boost converter TPS552882-Q1, the maximum inductor DC

current happens at the minimum input voltage and maximum output voltage. Set the inductor current limit of the

TPS552882-Q1 higher than the calculated maximum inductor DC current to make sure the TPS552882-Q1 has

the desired output current capability.

In boost mode, the inductor ripple current is calculated with Equation 12.

:

V_IN× V_OUT-V_IN

;

∆I_L(P-P)

=

L×f_SW×V_OUT

(12)

where

•

ΔI_L(P-P)is the inductor ripple current

L is the inductor value

f_SWis the switching frequency

V_OUTis the output voltage

V_INis the input voltage

Therefore, the inductor peak current is calculated with Equation 13.

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∆I_L(P-P)

I_L(P)= I_L(DC)

+

2

(13)

Normally, it is advisable to work with an inductor peak-to-peak current of less than 40% of the average inductor

current for maximum output current. A smaller ripple from a larger valued inductor reduces the magnetic

hysteresis losses in the inductor and EMI, but in the same way, load transient response time is increased. The

selected inductor must have higher saturation current than the calculated peak current.

The conversion efficiency is dependent on the resistance of its current path. The switching loss associated

with the switching MOSFETs, and the inductor core loss. Therefore, the overall efficiency is affected by the

inductor DC resistance (DCR), equivalent series resistance (ESR) at the switching frequency, and the core loss.

Table 8-2 lists recommended inductors for the TPS552882-Q1. In this application example, the Coilcraft inductor

XAL1010-472 is selected for its small size, high saturation current, and small DCR.

Table 8-2. Recommended Inductors

DCR

(MAXIMUM)

(mΩ)

SATURATION

CURRENT / HEAT

RATING CURRENT (A)

PART NUMBER

L (µH)

SIZE (L x W x H mm)

VENDOR⁽¹⁾

XAL1010-472ME

IHLP5050EZER4R7

125CDMCCDS-4R7MC

4.7

10

10.1

10

25.4/17.5

17.8/15.3

22/14

11.3 × 10 × 10

13.5 × 12.9 × 5

13.5 × 12.6 × 5

Coilcraft

Vishay

Sumida

(1) See the Third-Party Products Disclaimer.

8.2.2.5 Input Capacitor

In buck mode, the input capacitor supplies high ripple current. The RMS current in the input capacitors is given

by Equation 14.

:

V_OUT× V_IN-V_OUT

;

¨

I_{CIN RMS}_;= I

:

×

OUT

V_IN×V_IN

(14)

where

•

I_CIN(RMS)is the RMS current through the input capacitor

I_OUTis the output current

The maximum RMS current occurs at the output voltage is half of the input voltage, which gives I_CIN(RMS)= I_OUT

/

2. Ceramic capacitors are recommended for their low ESR and high ripple current capability. A total of 20 µF

effective capacitance is a good starting point for this application.

8.2.2.6 Output Capacitor

In boost mode, the output capacitor conducts high ripple current. The output capacitor RMS ripple current is

given by Equation 15, where the minimum input voltage and the maximum output voltage correspond to the

maximum capacitor current.

V_OUT

¨

I_{COUT RMS}_;= I

:

×

-1

OUT

V_IN

(15)

where

•

I_COUT(RMS)is the RMS current through the output capacitor

I_OUTis the output current

In this example, the maximum output ripple RMS current is 5.5 A.

The ESR of the output capacitor causes an output voltage ripple given by Equation 16 in boost mode.

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I_OUT×V_OUT

V_RIPPLE(ESR)

=

×R_COUT

V_IN

(16)

where

R_COUTis the ESR of the output capacitance

•

The capacitance also causes a capacitive output voltage ripple given by Equation 17 in boost mode. When input

voltage reaches the minimum value and the output voltage reaches the maximum value, there is the largest

output voltage ripple caused by the capacitance.

V_IN

V_OUT

l

I_OUT× 1-

p

V_RIPPLE(CAP)

=

C_OUT×f_SW

(17)

Typically, a combination of ceramic capacitors and bulk electrolytic capacitors is needed to provide low ESR,

high ripple current, and small output voltage ripple. From the required output voltage ripple, use Equation 16 and

Equation 17 to calculate the minimum required effective capacitance of the C_OUT

.

8.2.2.7 Output Current Limit Sense Resistor

The output current limit is implemented by putting a current sense resistor between the ISP and ISN pins. The

value of the limit voltage between the ISP and ISN pins is 50 mV. The current sense resistor between the ISP

and ISN pins should be selected to ensure that the output current limit is set high enough for output. The output

current limit setting resistor is given by Equation 18.

V_SNS

R_SNS

=

I_{OUT_LIMIT}

(18)

where

•

V_SNSis the current limit setting voltage between the ISP and ISN pin

I_{OUT_LIMIT}is the desired output current limit

Because the power dissipation is large, make sure the current sense resistor has enough power dissipation

capability with large package.

8.2.2.8 Loop Stability

The TPS55288 uses average current control scheme. The inner current loop uses internal compensation

and requires the inductor value must be larger than 1.2/f_SW. The outer voltage loop requires an external

compensation. The COMP pin is the output of the internal voltage error amplifier. An external compensation

network comprised of resistor and ceramic capacitors is connected to the COMP pin.

The TPS55288 operates in buck mode or boost mode. Therefore, both buck and boost operating modes require

loop compensations. The restrictive one of both compensations is selected as the overall compensation from a

loop stability point of view. Typically for a converter designed either work in buck mode or boost mode, the boost

mode compensation design is more restrictive due to the presence of a right half plane zero (RHPZ).

The power stage in boost mode can be modeled by Equation 19.

s

l

p l

× 1-

p

1+

:

R_LOAD× 1-D

;

2N×f_ESRZ

2N×f_RHPZ

G_PS(s) =

×

s

2×R_SENSE

1+

2N×f_P

(19)

where

•

R_LOADis the output load resistance

D is the switching duty cycle in boost mode

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•

R_SENSEis the equivalent internal current sense resistor, which is 0.055 Ω

The power stage has two zeros and one pole generated by the output capacitor and load resistance. Use

Equation 20 to Equation 22 to calculate them.

2

f_P=

2N×R_LOAD×C_OUT

(20)

(21)

(22)

1

f_ESRZ

=

2N×R_COUT×C_OUT

2

:

R_LOAD× 1-D

;

f_RHPZ

=

2N×L

The internal transconductance amplifier together with the compensation network at the COMP pin constitutes the

control portion of the loop. The transfer function of the control portion is shown by Equation 23.

s

l

p

1+

G_EA×R_EA×V_REF

V_OUT

2N×f_COMZ

G_C(s) =

×

s

l

p

l

× 1 +

p

1+

2N×f_COMP1

2N×f_COMP2

(23)

where

•

G_EAis the transconductance of the error amplifier

R_EAis the output resistance of the error amplifier

V_REFis the reference voltage input to the error amplifier

V_OUTis the output voltage

f_COMP1and f_COMP2are the pole’s frequency of the compensation network

f_COMZis the zero’s frequency of the compensation network

The total open-loop gain is the product of G_PS(s) and G_C(s). The next step is to choose the loop crossover

frequency, f_C, at which the total open-loop gain is 1, namely 0 dB. The higher in frequency that the loop gain

stays above 0 dB before crossing over, the faster the loop response. It is generally accepted that the loop gain

cross over 0 dB at the frequency no higher than the lower of either 1/10 of the switching frequency, f_SWor 1/5 of

the RHPZ frequency, f_RHPZ

.

Then, set the value of R_C, C_Cand C_Pby Equation 24 to Equation 26.

2N×V_OUT×R

×C_OUT×f_C

SENSE

R_C=

: ;

1-D ×V_REF×G_EA

(24)

where

•

f_Cis the selected crossover frequency

R_LOAD×C_OUT

C_C=

2×R_C

(25)

(26)

R_COUT×C_OUT

C_P=

R_C

If the calculated C_Pis less than 10 pF, it can be left open.

Designing the loop for greater than 45° of phase margin and greater than 10-dB gain margin eliminates output

voltage ringing during the line and load transient.

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8.2.3 Application Curves

Figure 8-2. Switching Waveforms in V_IN= 12 V,

V_OUT= 5 V, I_O= 5 A, FPWM

Figure 8-3. Switching Waveforms in V_IN= 12 V,

V_OUT= 5 V, I_O= 0 A, PFM

Figure 8-4. Switching Waveforms in V_IN= 12 V,

V_OUT= 12 V, I_O= 5 A, FPWM

Figure 8-5. Switching Waveforms in V_IN= 12 V,

V_OUT= 12 V, I_O= 0 A, PFM

Figure 8-7. Switching Waveforms in V_IN= 12 V,

V_OUT= 20 V, I_O= 0 A, PFM

Figure 8-6. Switching Waveforms in V_IN= 12 V,

V_OUT= 20 V, I_O= 5 A, FPWM

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Figure 8-8. Start-up Waveforms in V_IN= 12 V, V_OUT

= 5 V, I_O= 5 A, FPWM

Figure 8-9. Shutdown Waveforms in V_IN= 12 V,

V_OUT= 5 V, I_O= 5 A, FPWM

Figure 8-10. Line Transient Waveforms in V_IN= 9 V

to 20 V, V_OUT= 12 V, I_O= 5 A with 200-μs Slew Rate,

FPWM

Figure 8-11. Load Transient Waveforms in V_IN= 12

V, V_OUT= 5 V, I_O= 2.5 A to 5 A with 20-μs Slew

Rate, FPWM

Figure 8-12. Output Current Limit Waveforms in V_IN= 12 V, V_OUT= 5 V, R_LOAD= 0.9 Ω, R_SNS= 10 mΩ,

FPWM

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9 Power Supply Recommendations

The device is designed to operate from an input voltage supply range between 2.7 V to 36 V. This input supply

must be well regulated. If the input supply is located more than a few inches from the converter, additional

bulk capacitance can be required in addition to the ceramic bypass capacitors. A typical choice is an aluminum

electrolytic capacitor with a value of 100 μF.

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10 Layout

10.1 Layout Guidelines

As for all switching power supplies, especially those running at high switching frequency and high currents,

layout is an important design step. If layout is not carefully done, the regulator can suffer from instability and

noise problems. To maximize efficiency, switching rise time and fall time are very fast. To prevent radiation

of high-frequency noise (for example, EMI), proper layout of the high-frequency switching path is essential.

Minimize the length and area of all traces connected to the SW1 and SW2 pins, and always use a ground plane

under the switching regulator to minimize interplane coupling. The input capacitor needs to be close to the VIN

pin and the PGND to reduce the input supply current ripple.

The most critical current path for buck converter portion is from the switching FET at the buck side, through the

rectifier FET at the buck side to the PGND, then the input capacitors, and back to the input of the switching FET.

This high current path contains nanosecond rise time and fall time, and should be kept as short as possible.

Therefore, the input capacitor for power stage must be close to the input of the switching FET and the PGND

terminal of the rectifier FET.

The most critical current path for boost converter portion is from the switching FET at the boost side, through the

rectifier FET at boost side, then the output capacitors, and back to ground of the switching FET. This high current

path contains nanosecond rise time and fall time, and should be kept as short as possible. Therefore, the output

capacitor needs not only to be close to the VOUT pin, but also to the PGND pin to reduce the overshoot at the

SW2 pin and the VOUT pin.

The traces from the output current sensing resistor to the ISP pin and the ISN pin must be in parallel and close

to each other to avoid noise coupling.

The PGND plane and the AGND plane are connected at the terminal of the capacitor at the VCC pin. Thus the

noise caused by the MOSFET driver and parasitic inductance does not interfere with the AGND and internal

control circuit.

To get good thermal performance, it is recommended to use thermal vias beneath the TPS552882-Q1

connecting the PGND pin to the PGND plane, and the VOUT pin to a large VOUT area separately.

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10.2 Layout Example

trace on bottom layer

AGND plane on an inner layer

The first inner layer is the PGND plane

VOUT

AGND plane connects to PGND plane at the terminal of the capacitor at the VCC pin

AGND

PGND

18 17 16 15 14 13

19

12

11

20

26

25

24

21

22

10

9

23

1

8

VIN

2

3

4

5

6

7

NMOSFET

PGND

AGND

Figure 10-1. Example Layout

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11 Device and Documentation Support

11.1 Device Support

11.1.1 Third-Party Products Disclaimer

TI'S PUBLICATION OF INFORMATION REGARDING THIRD-PARTY PRODUCTS OR SERVICES DOES NOT

CONSTITUTE AN ENDORSEMENT REGARDING THE SUITABILITY OF SUCH PRODUCTS OR SERVICES

OR A WARRANTY, REPRESENTATION OR ENDORSEMENT OF SUCH PRODUCTS OR SERVICES, EITHER

ALONE OR IN COMBINATION WITH ANY TI PRODUCT OR SERVICE.

11.1.2 Development Support

11.1.2.1 Custom Design With WEBENCH® Tools

Click here to create a custom design using the TPS552882-Q1 device with the WEBENCH® Power Designer.

1. Start by entering the input voltage (V_IN), output voltage (V_OUT), and output current (I_OUT) requirements.

2. Optimize the design for key parameters such as efficiency, footprint, and cost using the optimizer dial.

3. Compare the generated design with other possible solutions from Texas Instruments.

The WEBENCH Power Designer provides a customized schematic along with a list of materials with real-time

pricing and component availability.

In most cases, these actions are available:

•

Run electrical simulations to see important waveforms and circuit performance

Run thermal simulations to understand board thermal performance

Export customized schematic and layout into popular CAD formats

Print PDF reports for the design, and share the design with colleagues

Get more information about WEBENCH tools at www.ti.com/WEBENCH.

11.2 Receiving Notification of Documentation Updates

To receive notification of documentation updates, navigate to the device product folder on ti.com. Click on

Subscribe to updates to register and receive a weekly digest of any product information that has changed. For

change details, review the revision history included in any revised document.

11.3 Support Resources

TI E2E^™support forums are an engineer's go-to source for fast, verified answers and design help — straight

from the experts. Search existing answers or ask your own question to get the quick design help you need.

Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do

not necessarily reflect TI's views; see TI's Terms of Use.

11.4 Trademarks

HotRod^™and TI E2E^™are trademarks of Texas Instruments.

WEBENCH^®is a registered trademark of Texas Instruments.

All trademarks are the property of their respective owners.

11.5 Glossary

TI Glossary

This glossary lists and explains terms, acronyms, and definitions.

11.6 Electrostatic Discharge Caution

This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled

with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.

ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may

be more susceptible to damage because very small parametric changes could cause the device not to meet its published

specifications.

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12 Mechanical, Packaging, and Orderable Information

The following pages include mechanical, packaging, and orderable information. This information is the most

current data available for the designated devices. This data is subject to change without notice and revision of

this document. For browser-based versions of this data sheet, refer to the left-hand navigation.

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PACKAGE MATERIALS INFORMATION

www.ti.com

23-Dec-2021

TAPE AND REEL INFORMATION

*All dimensions are nominal

Device

Package Package Pins

Type Drawing

SPQ

Reel

A0

B0

K0

P1

W

Pin1

Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant

(mm) W1 (mm)

TPS552882QRPMRQ1

VQFN-

HR

RPM

26

3000

330.0

12.4

3.8

4.3

1.5

8.0

12.0

Q2

TPS552882QWRPMRQ1 VQFN-

HR

330.0

12.4

3.8

4.3

1.5

8.0

12.0

Q2

Pack Materials-Page 1

PACKAGE MATERIALS INFORMATION

www.ti.com

23-Dec-2021

*All dimensions are nominal

Device

Package Type Package Drawing Pins

SPQ

Length (mm) Width (mm) Height (mm)

TPS552882QRPMRQ1

TPS552882QWRPMRQ1

VQFN-HR

RPM

26

3000

367.0

35.0

Pack Materials-Page 2

GENERIC PACKAGE VIEW

RPM 26

3.5 x 4, 0.5 mm pitch

VQFN-HR - 1 mm max height

VERY THIN QUAD FLATPACK-HotRod

This image is a representation of the package family, actual package may vary.

Refer to the product data sheet for package details.

4226451/A

www.ti.com

PACKAGE OUTLINE

VQFN-HR - 1 mm max height

PLASTIC QUAD FLATPACK-NO LEAD

RPM0026A

A

4.1

3.9

B

3.6

3.4

PIN 1 INDEX AREA

1.0

0.8

C

SEATING PLANE

0.08 C

0.05

0.00

5X 0.25±0.05

2X 0.35±0.05

0.1

C A B

0.1

C A B

0.05

C

0.05

C

5X

6X 0.4±0.1

0.425±0.1

2X (0.150 X 0.150)

TYP

(0.1) TYP

6X 0.525±0.1

7

2X 1.4875

13

6X 0.25±0.05

0.1

C A B

2X 0.225±0.05

2X 1

0.05

C

2X 0.5

PKG

6X 0.25±0.05

3X

0.1

C A B

1.425±0.1

24

25

26

0.05

C

2X 0.225±0.05

2X 1.4875

19

1

2X (0.175 X 0.150)

TYP

2X 0.475±0.1

PKG

2X 0.25±0.05

2X 0.4±0.05

0.1

C

A

B

3X 0.375±0.05

0.05

C

0.1

C A B

0.05

C

4224618/A 10/2018

NOTES:

1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing

per ASME Y14.5M.

2. This drawing is subject to change without notice.

www.ti.com

EXAMPLE BOARD LAYOUT

VQFN-HR - 1 mm max height

PLASTIC QUAD FLATPACK-NO LEAD

RPM0026A

3X (0.375)

PKG

2X (0.4)

1

2X (0.25)

2X (0.675)

19

2X (1.4875)

2X (0.225)

(R0.05) TYP

(1.6125)

(1.65)

3X (1.425)

PKG

24

25

26

2X (0.5)

2X (1)

(1.6375)

6X (0.25)

13

2X (1.4875)

2X (0.225)

7

6X (0.725)

6X (0.6)

5X (0.625)

5X (0.25)

2X (0.35)

(3.675)

(3.8)

LAND PATTERN EXAMPLE

EXPOSED METAL SHOWN

SCALE: 20X

0.05 MAX

ALL AROUND

METAL EDGE

EXPOSED METAL

SOLDER MASK

OPENING

NON SOLDER MASK

DEFINED

SOLDER MASK DETAIL

4224618/A 10/2018

NOTES: (continued)

3. For more information, see Texas Instruments literature number SLUA271 (www.ti.com/lit/slua271) .

www.ti.com

EXAMPLE STENCIL DESIGN

VQFN-HR - 1 mm max height

PLASTIC QUAD FLATPACK-NO LEAD

RPM0026A

3X (0.375)

PKG

2X (0.4)

1

2X (0.25)

2X (0.675)

19

2X (1.4875)

2X (0.225)

(R0.05) TYP

(1.6125)

(1.65)

3X (1.425)

PKG

24

25

26

2X (0.5)

2X (1)

(1.6375)

6X (0.25)

13

2X (1.4875)

2X (0.225)

7

6X (0.725)

6X (0.6)

5X (0.625)

5X (0.25)

2X (0.35)

(3.675)

(3.8)

SOLDER PASTE EXAMPLE

BASED ON 0.1 mm THICK STENCIL

SCALE: 20X

4224618/A 10/2018

NOTES: (continued)

4. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate

design recommendations.

www.ti.com

PACKAGE OUTLINE

VQFN-HR - 1 mm max height

PLASTIC QUAD FLATPACK-NO LEAD

RPM0026B

A

4.1

3.9

B

0.100 MIN

3.6

3.4

PIN 1 INDEX AREA

(0.130)

SECTION A-A

TYPICAL

1.0

0.8

C

SEATING PLANE

0.08

C

0.05

0.00

0.525

0.325

5X

3X 0.375±0.05

0.5

0.3

10X

0.1

C A B

(0.2) TYP

0.05

C

7

13

(0.16)

6

14

2X 1

2X 0.5

3X

1.425±0.1

PKG

0

2X 0.5

2X 1

26

25

24

0.3

23X

0.2

0.1

0.05

C

A B

18

2

C

PIN 1 ID

(OPTIONAL)

1

19

23

0.575

0.375

2X

0.625

0.425

6X

4226413/A 11/2020

NOTES:

1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing

per ASME Y14.5M.

2. This drawing is subject to change without notice.

www.ti.com

EXAMPLE BOARD LAYOUT

VQFN-HR - 1 mm max height

PLASTIC QUAD FLATPACK-NO LEAD

RPM0026B

3X 0.375

10X (0.6)

19

23

1

(1.65)

2X (0.675)

(1.6125)

2

18

2X (1)

2X (0.5)

(0)

PKG

3X

1.425

25

26

24

2X (0.5)

2X (1)

14

6

(1.65)

(1.6375)

13

7

5X (0.625)

(R 0.05) TYP

6X (0.725)

23X (0.25)

LAND PATTERN EXAMPLE

EXPOSED METAL SHOWN

SCALE: 20X

0.05 MAX

ALL AROUND

METAL EDGE

EXPOSED METAL

SOLDER MASK

OPENING

NON SOLDER MASK

DEFINED

SOLDER MASK DETAIL

4226413/A 11/2020

NOTES: (continued)

3. For more information, see Texas Instruments literature number SLUA271 (www.ti.com/lit/slua271) .

4. Solder mask tolerances between and around signal pads can vary based on board fabrication site.

www.ti.com

EXAMPLE STENCIL DESIGN

VQFN-HR - 1 mm max height

PLASTIC QUAD FLATPACK-NO LEAD

RPM0026B

3X 0.375

10X (0.6)

19

23

1

(1.65)

2X (0.675)

(1.6125)

2

18

2X (1)

2X (0.5)

(0)

PKG

3X

1.425

25

26

24

2X (0.5)

2X (1)

14

6

(1.65)

(1.6375)

13

7

5X (0.625)

(R 0.05) TYP

6X (0.725)

23X (0.25)

SOLDER PASTE EXAMPLE

BASED ON 0.1 mm THICK STENCIL

SCALE: 20X

4226413/A 11/2020

NOTES: (continued)

5.

Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate

design recommendations.

www.ti.com

IMPORTANT NOTICE AND DISCLAIMER

TI PROVIDES TECHNICAL AND RELIABILITY DATA (INCLUDING DATA SHEETS), DESIGN RESOURCES (INCLUDING REFERENCE

DESIGNS), APPLICATION OR OTHER DESIGN ADVICE, WEB TOOLS, SAFETY INFORMATION, AND OTHER RESOURCES “AS IS”

AND WITH ALL FAULTS, AND DISCLAIMS ALL WARRANTIES, EXPRESS AND IMPLIED, INCLUDING WITHOUT LIMITATION ANY

IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NON-INFRINGEMENT OF THIRD

PARTY INTELLECTUAL PROPERTY RIGHTS.

These resources are intended for skilled developers designing with TI products. You are solely responsible for (1) selecting the appropriate

TI products for your application, (2) designing, validating and testing your application, and (3) ensuring your application meets applicable

standards, and any other safety, security, regulatory or other requirements.

These resources are subject to change without notice. TI grants you permission to use these resources only for development of an

application that uses the TI products described in the resource. Other reproduction and display of these resources is prohibited. No license

is granted to any other TI intellectual property right or to any third party intellectual property right. TI disclaims responsibility for, and you

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TI objects to and rejects any additional or different terms you may have proposed. IMPORTANT NOTICE

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型号：	TPS552882QWRPMRQ1
厂家：	TEXAS INSTRUMENTS
描述：	TPS552882-Q1 36-V, 16-A Buck-boost Converter
文件：	总44页 (文件大小：3626K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

TPS552882QWRPMRQ1 [TI]

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