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TPS549B22

ZHCSGO0 –JUNE 2017

TPS549B22 1.5V 至 18V V_IN，4.5V 至 22V V_DD，具有全差动传感功能和

PMBus™ 的 25A SWIFT™

同步降压转换器

1 特性

2 应用

1

•

输入电压 (PV_IN)：1.5V 至 18V

•

企业级存储、SSD、NAS

输入偏置电压 (V_DD) 范围：4.5V 至 22V

输出电压范围：0.6V 至 5.5V

无线和有线通信基础设施

工业 PC、自动化、ATE、PLC、视频监控

企业服务器、交换机、路由器

集成型 4.1mΩ 和 1.9mΩ 功率 MOSFET，持续输

出电流为 25A

ASIC、SoC、FPGA、DSP 内核和 I/O 电源轨

•

基准电压范围：0.6V 至 1.2V（步长为 50mV），

采用 VSEL 引脚

3 说明

±0.5%，0.9V_REF公差范围：–40°C 至 +125°C 结

温

TPS549B22 器件是一款紧凑型单通道降压转换器，具

有自适应导通时间 D-CAP3 模式控制。该器件专为高

精度、高效率、快速瞬态响应、易于使用、外部组件较

少且空间受限的电源系统而设计。

•

真正的差分遥感放大器

D-CAP3™控制环路

自适应导通时间控制，具有 8 种 PMBus^TM

频

该器件采用全差动传感和 TI 的集成 FET，高侧导通

电阻为 4.1mΩ，低侧导通电阻为 1.9mΩ。此外，该器

件还具有 0.5% 的精度和 0.9V 基准电压，环境温度范

围介于 –40°C 和 +125°C 之间。其竞争优势包括：超

低的外部组件数、精准的负载和线路调节、自动跳频或

FCCM 工作模式以及内部软启动控制。

率：315kHz、425kHz、550kHz、650kHz、

825kHz、900kHz、1.025MHz 和 1.125MHz

•

温度补偿和可编程电流限值，具有 R_ILIM和 OC 钳

位

•

可选断续或闭锁 OVP 或 UVP

通过精确的 EN 实现的 V_DDUVLO 外部调整

预偏置启动支持

TPS549B22 器件采用 7mm × 5mm、40 引脚、

LQFN-CLIP (RVF) 封装（RoHs 豁免）。

Eco-mode™和 FCCM 可供选择

全套故障保护和 PGOOD

器件信息⁽¹⁾

标准 VOUT_COMMAND 和 VOUT_MARGIN（高

电平和低电平）

器件型号

TPS549B22

封装

封装尺寸（标称值）

LQFN-CLIP (40)

7.00mm × 5.00mm

•

引脚捆绑和实时编程

故障报告和警告

(1) 如需了解所有可用封装，请参阅数据表末尾的可订购产品附

录。

针对所选命令的 NVM 备份

1MHz PMBus，支持 PEC 和 SMB_ALRT#

结合使用 TPS549B22 和 WEBENCH^®电源设计器

创建定制设计

简化应用

PVIN

VSEL

PGND

MODE

PGOOD

ILIM

TPS549B22

RESV_TRK

RSN

Load

+

œ

RSP

VOSNS

ALERT#

DATA

CLOCK

ENABLE

Copyright

1

An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,

intellectual property matters and other important disclaimers. PRODUCTION DATA.

English Data Sheet: SNVSAU8

TPS549B22

ZHCSGO0 –JUNE 2017

www.ti.com.cn

7.6 Register Maps......................................................... 29

Application and Implementation ........................ 43

8.1 Application Information............................................ 43

8.2 Typical Applications ................................................ 44

Power Supply Recommendations...................... 54

1

2

3

4

5

6

特性.......................................................................... 1

8

9

应用.......................................................................... 1

说明.......................................................................... 1

修订历史记录 ........................................................... 2

Pin Configuration and Functions......................... 3

Specifications......................................................... 4

6.1 Absolute Maximum Ratings ...................................... 4

6.2 ESD Ratings.............................................................. 4

6.3 Recommended Operating Conditions....................... 5

6.4 Thermal Information.................................................. 5

6.5 Electrical Characteristics........................................... 5

6.6 Typical Characteristics............................................ 10

Detailed Description ............................................ 14

7.1 Overview ................................................................. 14

7.2 Functional Block Diagram ....................................... 15

7.3 Feature Description................................................. 15

7.4 Device Functional Modes........................................ 19

7.5 Programming........................................................... 19

10 Layout................................................................... 54

10.1 Layout Guidelines ................................................. 54

10.2 Layout Examples................................................... 55

10.3 Mounting and Thermal Profile Recommendation.. 57

11 器件和文档支持 ..................................................... 58

11.1 器件支持................................................................ 58

11.2 文档支持................................................................ 58

11.3 接收文档更新通知 ................................................. 58

11.4 社区资源................................................................ 58

11.5 商标....................................................................... 58

11.6 静电放电警告......................................................... 58

11.7 Glossary................................................................ 58

12 机械、封装和可订购信息....................................... 59

7

4 修订历史记录

注：之前版本的页码可能与当前版本有所不同。

日期

修订版本

说明

2017 年 6 月

*

初始发行版

2

TPS549B22

www.ti.com.cn

ZHCSGO0 –JUNE 2017

5 Pin Configuration and Functions

RVF Package

40-Pin LQFN-CLIP With Thermal Pad

Top View

32

26

27

21

31 30 29 28

25 24 23 22

PGND

20

VSEL 33

19 PGND

MODE

34

35

18

17

16

15

PGND

PGOOD

ILIM 36

37

38

RESV_TRK

RSN

Thermal Pad

14 PGND

PGND

RSP 39

VOSNS

13

40

6

7

8

9

10 11 12

1

2

3

4

5

Pin Functions

I/O/P⁽¹⁾

DESCRIPTION

NAME

ADDR

NO.

32

I

Program device address and SKIP or FCCM mode.

Ground pin for internal analog circuits.

AGND

30

G

Supply rail for high-side gate driver (boot terminal). Connect boot capacitor from this pin to SW

node. Internally connected to BP via bootstrap PMOS switch.

BOOT

5

P

BP

31

29

O

P

LDO output

DRGND

Internal gate driver return.

Enable pin that can turn on the DC/DC switching converter. Use also to program the required

PVIN UVLO when PVIN and VDD are connected together.

EN_UVLO

4

I

ILIM

36

34

I/O

I

Program overcurrent limit by connecting a resistor to ground.

MODE

Mode selection pin. Select the control mode (DCAP3 or DCAP), and soft-start timing selection.

6, 7, 26,

27

NC

No connect.

13, 14, 15,

16, 17, 18,

19, 20

PGND

P

Power ground of internal FETs.

PGOOD

35

3

O

I

Open drain power-good status signal.

Clock input for the PMBus interface.

Data I/O for the PMBus interface.

PMB_CLK

PMB_DATA

2

I/O

21, 22, 23,

24, 25

PVIN

P

Power supply input for integrated power MOSFET pair.

RSN

38

39

37

1

I

Inverting input of the differential remote sense amplifier.

Non-inverting input of the differential remote sense amplifier.

Do not connect.

RSP

RESV_TRK

SMB_ALRT#

I

O

Alert output for the PMBus interface.

(1) I = input, O = output, G = GND

3

TPS549B22

ZHCSGO0 –JUNE 2017

www.ti.com.cn

Pin Functions (continued)

I/O/P⁽¹⁾

DESCRIPTION

NAME

NO.

8, 9, 10,

11, 12

SW

I/O

Output switching terminal of power converter. Connect the pins to the output inductor.

VDD

28

40

P

I

Controller power supply input.

Output voltage monitor input pin.

VOSNS

Program the initial start-up and or reference voltage without feedback resistor dividers (from

0.6 V to 1.2 V in 50-mV increments).

VSEL

33

I

6 Specifications

6.1 Absolute Maximum Ratings

over operating free-air temperature range (unless otherwise noted)

(1)(2)

MIN

–0.3

–5

MAX

25

UNIT

PVIN

VDD

25

BOOT

34

DC

BOOT to SW

7.7

9

< 10 ns

PMB_CLK, PMB_DATA

Input voltage

6

V

EN_UVLO, VOSNS, MODE, ADDR, ILIM

7.7

3.6

0.3

25

RSP, RESV_TRK, VSEL

RSN

PGND, AGND, DRGND

DC

SW

< 10 ns

27

Output voltage

PGOOD, BP

–0.3

–55

7.7

6

V

Output voltage

SMB_ALRT#, PMB_DATA

Junction temperature, T_J

Storage temperature, T_stg

150

°C

–55

(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings

only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended

Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

(2) All voltage values are with respect to the network ground terminal unless otherwise noted.

6.2 ESD Ratings

VALUE

±2000

±500

UNIT

Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001⁽¹⁾

Charged-device model (CDM), per JEDEC specification JESD22-C101⁽²⁾

Electrostatic

discharge

V_(ESD)

V

(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.

(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

4

TPS549B22

www.ti.com.cn

ZHCSGO0 –JUNE 2017

6.3 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted)

MIN

MAX

UNIT

PVIN with no snubber circuit:

SW ringing peak voltage equals 23 V at 25-A output

1.5

14

PVIN with snubber circuit:

SW ringing peak voltage equals 23 V at 25-A output

1.5

18

VDD

4.5

–0.1

–5

22

24.5

6.5

7

BOOT

DC

BOOT to SW

< 10 ns

Input voltage

V

PMB_CLK, PMB_DATA

EN_UVLO, VOSNS, MODE, ADDR, ILIM

RSP, RESV_TRK, VSEL

RSN

5.5

3.3

0.1

18

PGND, AGND, DRGND

DC

SW

< 10 ns

27

Output voltage

PGOOD, BP

–0.1

–40

7

V

Output voltage

SMB_ALRT#, PMB_DATA

5.5

125

Junction temperature, T_J

°C

6.4 Thermal Information

TPS549B22

THERMAL METRIC⁽¹⁾

RVF (LQFN-CLIP)

UNIT

40 PINS

28.5

18.3

3.6

R_θJA

Junction-to-ambient thermal resistance

Junction-to-case (top) thermal resistance

Junction-to-board thermal resistance

°C/W

R_θJC(top)

R_θJB

ψ_JT

Junction-to-top characterization parameter

Junction-to-board characterization parameter

Junction-to-case (bottom) thermal resistance

0.96

3.6

ψ_JB

R_θJC(bot)

0.6

(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application

report.

6.5 Electrical Characteristics

over operating free-air temperature range, V_VDD= 12 V, V_{EN_UVLO}= 5 V (unless otherwise noted)

PARAMETER

TEST CONDITION

MIN

TYP

MAX

UNIT

MOSFET ON-RESISTANCE (R_DS(on)

)

High-side FET

R_DS(on)

(V_BOOT– V_SW) = 5 V, I_D= 25 A, T_J= 25°C

V_VDD= 5 V, I_D= 25 A, T_J= 25°C

4.1

1.9

mΩ

Low-side FET

INPUT SUPPLY AND CURRENT

V_VDD

VDD supply voltage

Nominal VDD voltage range

4.5

22

V

No load, power conversion enabled (no switching),

T_A= 25°C,

I_VDD

VDD bias current

2

mA

µA

I_VDDSTBY

VDD standby current

No load, power conversion disabled, T_A= 25°C

700

5

TPS549B22

ZHCSGO0 –JUNE 2017

www.ti.com.cn

Electrical Characteristics (continued)

over operating free-air temperature range, V_VDD= 12 V, V_{EN_UVLO}= 5 V (unless otherwise noted)

PARAMETER

TEST CONDITION

MIN

TYP

MAX

UNIT

UNDERVOLTAGE LOCKOUT

V_{VDD_UVLO}

VDD UVLO rising threshold

4.23

4.25

0.2

4.34

V

V_{VDD_UVLO(HYS)}VDD UVLO hysteresis

V_{EN_ON_TH}

V_{EN_HYS}

EN_UVLO on threshold

EN_UVLO hysteresis

1.45

270

1.6

1.75

340

V

300

mV

EN_UVLO input leakage

current

I_{EN_LKG}

V_{EN_UVLO}= 5 V

–1

0

1

µA

INTERNAL REFERENCE VOLTAGE RANGE

V_INTREF

Internal REF voltage

900.4

mV

Internal REF voltage

tolerance

V_INTREFTOL

V_INTREF

–40°C ≤ T_J≤ 125°C

–0.5%

0.6

0.5%

1.2

Internal REF voltage range

V

OUTPUT VOLTAGE

Loop comparator input offset

V_{IOS_LPCMP}

–2.5

2.5

1

mV

voltage⁽¹⁾

I_RSP

RSP input current

VO discharge current

V_RSP= 600 mV

–1

8

µA

I_VO(dis)

V_VO= 0.5 V, power conversion disabled

12

7

mA

DIFFERENTIAL REMOTE SENSE AMPLIFIER

f_UGBW

A₀

Unity gain bandwidth⁽¹⁾

Open loop gain⁽¹⁾

Slew rate⁽¹⁾

Input range⁽¹⁾

Input offset voltage⁽¹⁾

5

MHz

dB

75

SR

±4.7

V/µsec

V

V_IRNG

V_OFFSET

–0.2

–3.5

1.8

3.5

mV

INTERNAL BOOT STRAP SWITCH

V_F

Forward voltage

V_BP-BOOT, I_F= 10 mA, T_A= 25°C

0.1

0.2

1.5

V

I_BOOT

VBST leakage current

V_BOOT= 30 V, V_SW= 25 V, T_A= 25°C

0.01

µA

SWITCHING FREQUENCY

275

380

490

585

740

790

920

950

315

425

550

650

825

900

1025

1125

60

350

475

615

740

f_SW

VO switching frequency⁽²⁾

V_IN= 12 V, V_VO= 1 V, T_A= 25°C

kHz

930

995

1160

1250

t_ON(min)

Minimum on-time⁽¹⁾

Minimum off-time⁽¹⁾

ns

t_OFF(min)

DRVH falling to rising

300

(1) Specified by design. Not production tested.

(2) Correlated with close-loop EVM measurement at load current of 30 A.

6

TPS549B22

www.ti.com.cn

ZHCSGO0 –JUNE 2017

Electrical Characteristics (continued)

over operating free-air temperature range, V_VDD= 12 V, V_{EN_UVLO}= 5 V (unless otherwise noted)

PARAMETER

TEST CONDITION

MIN

TYP

MAX

UNIT

MODE, VSEL, ADDR DETECTION

Open

V_BP

1.9091

1.8243

1.7438

1.6725

1.6042

1.5348

1.465

R_LOW= 187 kΩ

R_LOW= 165 kΩ

R_LOW= 147 kΩ

R_LOW= 133 kΩ

R_LOW= 121 kΩ

R_LOW= 110 kΩ

R_LOW= 100 kΩ

R_LOW= 90.9 kΩ

R_LOW= 82.5 kΩ

R_LOW= 75 kΩ

1.3952

1.3245

1.2557

1.187

R_LOW= 68.1 kΩ

R_LOW= 60.4 kΩ

R_LOW= 53.6 kΩ

R_LOW= 47.5 kΩ

R_LOW= 42.2 kΩ

R_LOW= 37.4 kΩ

R_LOW= 33.2 kΩ

R_LOW= 29.4 kΩ

R_LOW= 25.5 kΩ

R_LOW = 22.1 kΩ

R_LOW= 19.1 kΩ

R_LOW= 16.5 kΩ

R_LOW= 14.3 kΩ

R_LOW= 12.1 kΩ

R_LOW= 10 kΩ

1.1033

1.0224

0.9436

0.8695

0.7975

0.7303

0.6657

0.5953

0.5303

0.4699

0.415

V_BP= 2.93 V,

R_HIGH= 100 kΩ

MODE, VSEL, and ADDR

detection voltage

V_{DETECT_TH}

V

0.3666

0.3163

0.2664

0.2138

0.1708

0.1299

0.0898

0.0512

GND

R_LOW= 7.87 kΩ

R_LOW= 6.19 kΩ

R_LOW= 4.64 kΩ

R_LOW= 3.16 kΩ

R_LOW= 1.78 kΩ

R_LOW= 0 Ω

7

TPS549B22

ZHCSGO0 –JUNE 2017

www.ti.com.cn

Electrical Characteristics (continued)

over operating free-air temperature range, V_VDD= 12 V, V_{EN_UVLO}= 5 V (unless otherwise noted)

PARAMETER

TEST CONDITION

MIN

TYP

MAX

UNIT

SOFT-START

R_{MODE_LOW}= 60.4 kΩ

7

3.6

1.6

0.8

8⁽³⁾

4⁽⁴⁾

2

10

5.2

2.8

1.6

V_OUTrising from 0 V to

95% of final set point,

R_{MODE_HIGH}= 100 kΩ

R_{MODE_LOW}= 53.6 kΩ

R_{MODE_LOW}= 47.5 kΩ

R_{MODE_LOW}= 42.2 kΩ

t_SS

Soft-start time

ms

1

POWER-ON DELAY

Delay from enable to switching POD[2:0] = 000

Delay from enable to switching POD[2:0] = 001

Delay from enable to switching POD[2:0] = 010

Delay from enable to switching POD[2:0] = 011

Delay from enable to switching POD[2:0] = 100

Delay from enable to switching POD[2:0] = 101

Delay from enable to switching POD[2:0] = 110

Delay from enable to switching POD[2:0] = 111

256

512

µs

1.024

2.048

4.096

8.192

16.384

32.768

t_PODLY

Power-on delay time

ms

PGOOD COMPARATOR

PGOOD in from higher

105

89

108

92

111

95

PGOOD in from lower

V_PGTH

PGOOD threshold

%V_REF

PGOOD out to higher

120

PGOOD out to lower

68

I_PG

PGOOD sink current

PGOOD delay time

V_PGOOD= 0.5 V

6.9

mA

µs

Delay for PGOOD going in, PGD[2:0] = 000

Delay for PGOOD going in, PGD[2:0] = 001

Delay for PGOOD going in, PGD[2:0] = 010

Delay for PGOOD going in, PGD[2:0] = 011

Delay for PGOOD going in, PGD[2:0] = 100

Delay for PGOOD going in, PGD[2:0] = 101

Delay for PGOOD going in, PGD[2:0] = 110

Delay for PGOOD going in, PGD[2:0] = 111

Delay for PGOOD coming out

256

512

1.024

2.048

4.096

8.192

16.384

131

t_PGDLY

ms

2

1

µs

I_PGLK

PGOOD leakage current

V_PGOOD= 5 V

–1

0

μA

CURRENT DETECTION

R_LIM= 61.9 kΩ

OC tolerance

R_LIM= 51.1 kΩ

OC tolerance

R_LIM= 40.2 kΩ

R_LIM= 61.9 kΩ

R_LIM= 51.1 kΩ

R_LIM= 40.2 kΩ

30

±15%⁽⁵⁾

25

A

I_{OCL_VA}

Valley current limit threshold

±15%⁽⁵⁾

17

20

23

A

–30

Negative valley current limit

threshold

I_{OCL_VA_N}

–25

–20

Clamp current at V_LIMclamp

at lowest

I_{CLMP_LO}

I_{CLMP_HI}

V_{ILIM_CLMP}= 0.1 V, T_A= 25°C

V_{ILIM_CLMP}= 1.2 V, T_A= 25°C

5

A

Clamp current at V_LIMclamp

at highest

50

(3) In order to use the 8-ms SS setting, follow the steps outlined in Application Workaround to Support 4-ms and 8-ms SS Settings.

(4) In order to use the 4-ms SS setting, follow the steps outlined in Application Workaround to Support 4-ms and 8-ms SS Settings.

(5) Calculated from 20-A test data. Not production tested.

8

TPS549B22

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ZHCSGO0 –JUNE 2017

Electrical Characteristics (continued)

over operating free-air temperature range, V_VDD= 12 V, V_{EN_UVLO}= 5 V (unless otherwise noted)

PARAMETER

TEST CONDITION

MIN

TYP

MAX

UNIT

PROTECTIONS AND OOB

Wake-up

3.32

3.11

V

V_BPUVLO

BP UVLO threshold voltage

Shutdown

V_OVP

OVP threshold voltage

OVP response time

OVP detect voltage

100-mV over drive

UVP detect voltage

117%

65%

120%

123%

1

V_REF

µs

t_OVPDLY

V_UVP

t_UVPDLY

V_OOB

UVP threshold voltage

UVP delay filter delay time

OOB threshold voltage

68%

1

71%

V_REF

ms

8%

16

24

38

67

V_REF

ms

t_SS= 1 ms

t_SS= 2 ms

t_SS= 4 ms

t_SS= 8 ms

ms

t_HICDLY

Hiccup blanking time

ms

BP VOLTAGE

V_BP

BP LDO output voltage

BP LDO dropout voltage

BP LDO overcurrent limit

V_IN= 12 V, 0 A ≤ I_LOAD≤ 10 mA,

V_IN= 4.5 V, I_LOAD= 30 mA, T_A= 25°C

V_IN= 12 V, T_A= 25°C

5.07

100

V

V_BPDO

365

0.8

mV

mA

I_BPMAX

PMB_CLK and PMB_DATA INPUT BUFFER LOGIC THRESHOLDS

PMB_CLK and PMB_DATA

V_IL-PMBUS

V

low-level input voltage⁽¹⁾

PMB_CLK and PMB_DATA

V_IH-PMBUS

1.35

high-level input voltage⁽¹⁾

PMB_CLK and PMB_DATA

V_HY-PMBUS

150

165

mV

hysteresis voltage⁽¹⁾

PMB_CLK and SMB_ALRT OUTPUT PULLDOWN

PMB_DATA and SMB_ALRT

V_OL-PMBUS

I_SINK= 20 mA

0.4

30

V

low-level output voltage⁽¹⁾

THERMAL SHUTDOWN

Shutdown temperature

Hysteresis

155

Built-In thermal shutdown

T_SDN

°C

threshold⁽¹⁾

9

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ZHCSGO0 –JUNE 2017

www.ti.com.cn

6.6 Typical Characteristics

100%

95%

90%

85%

80%

75%

70%

65%

60%

100%

95%

90%

85%

80%

75%

70%

65%

60%

V_IN= 5 V

V_IN= 12 V

V_IN= 14 V

V_IN= 18 V

V_IN= 12 V

V_IN= 14 V

V_IN= 18 V

0

5

10

15

20

25

0

5

10

15

20

25

Output Current (A)

D001

D002

V_OUT= 1 V

V_DD= V_IN

SKIP Mode

V_OUT= 1 V

V_DD= V_IN

FCCM Mode

f_SW= 650 kHz

Figure 1. Efficiency vs Output Current

Figure 2. Efficiency vs Output Current

4.5

4

1.01

1.005

1

3.5

3

2.5

2

1.5

1

0.995

0.99

V_IN= 5 V

V_IN= 12 V

V_IN= 14 V

V_IN= 18 V

V_IN= 12 V

V_IN= 14 V

V_IN= 18 V

0.5

0

5

10

15

20

25

0

5

10

15

20

25

Output Current (A)

D003

D004

V_OUT= 1 V

V_DD= V_IN

SKIP Mode

V_OUT= 1 V

V_DD= V_IN

FCCM Mode

f_SW= 650 kHz

Figure 3. Converter Power Loss vs Output Current

Figure 4. Output Voltage Regulation vs Output Current

2.525

100%

95%

90%

85%

80%

2.52

2.515

2.51

2.505

2.5

2.495

2.49

V_IN= 5 V

2.485

2.48

V_IN= 12 V

V_IN= 14 V

V_IN= 18 V

V_IN= 12 V

V_IN= 14 V

V_IN= 18 V

2.475

0

5

10

15

20

25

0

5

10

15

20

SKIP Mode

25

Output Current (A)

D005

D006

V_DD= V_IN

f_SW= 650 kHz

L= 820 nH, 0.9 mΩ

SKIP Mode

V_DD= V_IN

f_SW= 650 kHz

L= 820 nH, 0.9 mΩ

V_OUT= 2.5 V

Figure 5. Efficiency vs Output Current

Figure 6. Output Voltage Regulation vs Output Current

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Typical Characteristics (continued)

100%

6

5

4

3

2

1

0

95%

90%

85%

80%

V_IN= 9 V

V_IN= 12 V

V_IN= 14 V

V_IN= 18 V

V_IN= 12 V

V_IN= 14 V

V_IN= 18 V

0

5

10

15

20

FCCM Mode

25

0

5

10

15

20

25

Output Current (A)

D007

D008

V_DD= V_IN

f_SW= 650 kHz

L= 820 nH, 0.9 mΩ

V_DD= V_IN

f_SW= 650 kHz

FCCM Mode

V_OUT= 5 V

L= 820 nH, 0.9 mΩ

Figure 7. Efficiency vs Output Current

Figure 8. Power Loss vs Output Current

I_OUT= 25 A

V_DD= V_IN= 12 V

V_OUT= 1 V

f_SW= 650 kHz

V_DD= V_IN= 12 V

V_OUT= 1 V

f_SW= 650 kHz

Natural convection at room temperature

Figure 9. Thermal Image

Figure 10. Thermal Image

I_OUT= 25 A

V_DD= V_IN= 12 V

V_OUT= 2.5 V

f_SW= 650 kHz

I_OUT= 25 A

V_DD= V_IN= 12 V

V_OUT= 5 V

f_SW= 650 kHz

Natural convection at room temperature

Figure 11. Thermal Image

Figure 12. Thermal Image

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Typical Characteristics (continued)

1 – Operation only

2 – Turnoff

4 – V_OUTCommand up to 1.2 V

5 – V_OUTCommand down to 0.6 V

6 – Turnoff

3 – Turnon without Margin

Figure 13. PMBus 1-MHz Bus Speed with 1.8-V Pullup

Figure 14. 6 Sequenced Events – I2C Write

1 – Operation only

2 – Turnoff

4 – V_OUTCommand up to 1.2 V

5 – V_OUTCommand down to 0.6 V

6 – Turnoff

1 – Operation only

4 – V_OUTCommand up to 1.2 V

5 – V_OUTCommand down to 0.6 V

6 – Turnoff

2 – Turnoff

3 – Turnon without Margin

Figure 15. 6 Sequenced Events – I2C Write/Read

Figure 16. 6 Sequenced Events – I2C Write/Read with PEC

1 – Operation only

4 – 16 V_OUTCommand up to 1.2 V,

50 mV per step down to 0.6 V

17 – Turnoff

1 – Operation only

4 – 16 V_OUTCommand up to 1.2 V,

50 mV per step down to 0.6 V

17 – Turnoff

2 – Turnoff

3 – Turnon without Margin

Figure 17. 17 Sequenced Events – I2C Write

Figure 18. 17 Sequenced Events – I2C Write/Read

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Typical Characteristics (continued)

1 – Operation only

2 – Turnoff

4 – 16 V_OUTCommand up to 1.2 V,

1 – Operation only

4 – 16 V_OUTCommand up to 1.2

V,

50 mV per step down to 0.6 V

17 – Turnoff

2 – Turnoff

3 – Turnon without Margin

17 – 28 V_OUTCommand from 0.6

V

to 1.2 V, 50 mV per step

29 – Turnoff

Figure 19. 17 Sequenced Events – I2C Write/Read with PEC

Figure 20. 29 Sequenced Events – I2C Write

1 – Operation only

2 – Turnoff

4 – 16 V_OUTCommand up to 1.2 V,

50 mV per step down to 0.6 V

17 – 28 Vout Command from 0.6 V

to 1.2 V, 50 mV per step

29 – Turnoff

1 – Operation only

4 – 16 Vout Command up to 1.2 V,

50 mV per step down to 0.6 V

2 – Turnoff

3 – Turnon without Margin

17 – 28 Vout Command from 0.6 V

to 1.2 V, 50 mV per step

29 – Turnoff

3 – Turnon without Margin

Figure 21. 29 Sequenced Events – I2C Write/Read

Figure 22. 29 Sequenced Events – I2C Write/Read with PEC

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7 Detailed Description

7.1 Overview

TPS549B22 device is a high-efficiency, single-channel, FET-integrated, synchronous buck converter. It is

suitable for point-of-load applications with 25 A or lower output current in storage, telecom and similar digital

applications. The device features proprietary D-CAP3 mode control combined with adaptive on-time architecture.

This combination is ideal for building modern high/low duty ratio, ultra-fast load step response DC-DC converters.

TPS549B22 device has integrated MOSFETs rated at 25-A TDC.

The converter input voltage range is from 1.5 V up to 18 V, and the V_DDinput voltage range is from 4.5 V to

22 V. The output voltage ranges from 0.6 V to 5.5 V.

Stable operation with all ceramic output capacitors is supported as the D-CAP3 mode uses emulated current

information to control the modulation. An advantage of this control scheme is that it does not require phase

compensation network outside which makes it easy to use and also enables low external component count. .

Adaptive on-time control tracks the preset switching frequency over a wide range of input and output voltage

while increasing switching frequency as needed during load step transient.

The default preset switching frequency for this device is 650 kHz. Switching frequency is also programmable

from 8 preset values via PMBus interface. supports digital communication via PMBus using standard interfacing

pins, PMB_CLK, PMB_DATA and SMB_ALRT#. The detailed PMBus features, capabilities and command sets of

the TPS549B22 can be found in PMBus Programming.

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7.2 Functional Block Diagram

External Soft

RESV_TRK

Start

MUX

Internal

Soft Start

V_REF-32%

EN_UVLO

RSN

PGOOD

+

-

V_REF+8/16%

+

-

UV

Delay

Control

+

-

OV

+

-

V_REF-8/16%

PVIN

RSP

V_REF+20%

BOOT

+

-

PWM

+

D-CAP3^TM

Ramp Generator

v_out

V_REF

VOSNS

VSEL

Reference

Generator

XCON

PMB_CLK

Adjustment/

Margining

SW

PMBus

Interface

PMB_DATA

t_ON

One-

Shot

SMB_ALRT#

ADDR

Control Logic

Address

Detector

BP

+

ZC

x(1/16)

ILIM

-

PGND

AGND

+

x(-1/16)

LS

OCP

-

LDO

VDD

Regulator

MODE Logic

MODE

DRGND

7.3 Feature Description

7.3.1 25-A FET

The TPS549B22 device is a high-performance, integrated FET converter supporting current rating up to 25 A

thermally. It integrates two N-channel NexFET™ power MOSFETs, enabling high power density and small PCB

layout area. The drain-to-source breakdown voltage for these FETs is 25-V DC and 27-V transient for 10 ns.

Avalanche breakdown occurs if the absolute maximum voltage rating exceeds 27 V. In order to limit the switch

node ringing of the device, TI recommends adding an R-C snubber from the SW node to the PGND pins. Refer

to Layout Guidelines for the detailed recommendations.

7.3.2 On-Resistance

The typical on-resistance (R_DS(on)) for the high-side MOSFET is 4.1 mΩ, and typical on-resistance for the low-

side MOSFET is 1.9 mΩ with a nominal gate voltage (V_GS) of 5 V.

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Feature Description (continued)

7.3.3 Package Size, Efficiency and Thermal Performance

The TPS549B22 device is available in a 7 mm × 5 mm QFN package with 40 power and I/O pins. The device

employs TI proprietary MCM packaging technology with thermal pad. With a properly designed system layout,

applications achieve optimized safe operating area (SOA) performance. The curves shown in Figure 23 and

Figure 24 are based on the orderable evaluation module design. (See www.ti.com to order the EVM.)

110

100

90

110

100

90

80

70

60

50

Nat Conv

100 LFM

200 LFM

400 LFM

Nat Conv

100 LFM

200 LFM

400 LFM

40

30

0

5

10

15

20

25

0

5

10

15

20

25

Output Current (A)

D012

D011

V_IN= 12 V

V_OUT= 5.5 V

f_SW= 650 kHz

V_IN= 12 V

V_OUT= 1 V

f_SW= 650 kHz

Figure 24. Safe Operating Area

Figure 23. Safe Operating Area

7.3.4 Soft-Start Operation

In the TPS549B22 device the soft-start time controls the inrush current required to charge the output capacitor

bank during start-up. The device offers selectable soft-start options of 1 ms, 2 ms, 4 ms and 8 ms. When the

device is enabled (either by EN or V_DDUVLO), the reference voltage ramps from 0 V to the final level defined by

VSEL pin-strap configuration, in a given soft-start time. The TPS549B22 device supports several soft-start times

between 1 ms and 8 ms selected by MODE pin configuration. Refer to MODE definition table for details.

7.3.5 V_DDSupply Undervoltage Lockout (UVLO) Protection

The TPS549B22 device provides fixed V_DDundervoltage lockout threshold and hysteresis. The typical V_DDturnon

threshold is 4.25 V, and hysteresis is 0.2 V. The V_DDUVLO can be used in conjunction with the EN_UVLO signal

to provide proper power sequence to the converter design. UVLO is a non-latched protection.

7.3.6 EN_UVLO Pin Functionality

The EN_UVLO pin drives an input buffer with accurate threshold and can be used to program the exact required

turnon and turnoff thresholds for switcher enable, V_DDUVLO or VIN UVLO (if VIN and VDD are tied together). If

desired, an external resistor divider can be used to set and program the turnon threshold for V_DDor VIN UVLO.

Figure 25 shows how to program the input voltage UVLO using the EN_UVLO pin.

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Feature Description (continued)

PVIN

29

28

26 25 24 23 22 21

PGND 20

PGND 19

PGND 18

PGND 17

PGND 16

PGND 15

PGND 14

PGND 13

TPS549B22

4

PVIN

Figure 25. Programming the UVLO Voltage

7.3.7 Fault Protections

This section describes positive and negative overcurrent limits, overvoltage protections, out-of-bounds limits,

undervoltage protections, and overtemperature protections.

7.3.7.1 Current Limit (ILIM) Functionality

90

80

70

60

50

40

30

20

10

0

5

10

15

20

25

30

35

40

Output Current (A)

D010

Figure 26. Current Limit Resistance vs OCP Valley Overcurrent Limit

The ILIM pin sets the OCP level. Connect the ILIM pin to GND through the voltage setting resistor, R_ILIM. In order

to provide both good accuracy and a cost-effective solution, the TPS549B22 device supports temperature

compensated internal MOSFET R_DS(on)sensing.

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Feature Description (continued)

Also, the TPS549B22 device performs both positive and negative inductor current limiting with the same

magnitudes. The positive current limit normally protects the inductor from saturation that causes damage to the

high-side FET and low-side FET. The negative current limit protects the low-side FET during OVP discharge.

The voltage between GND pin and SW pin during the OFF time monitors the inductor current. The current limit

has 1200 ppm/°C temperature slope to compensate the temperature dependency of the on-resistance (R_DS(on)).

The GND pin is used as the positive current sensing node.

The TPS549B22 device uses cycle-by-cycle over-current limiting control. The inductor current is monitored

during the OFF-state and the controller maintains the OFF-state during the period that the inductor current is

larger than the overcurrent I_LIMlevel. V_ILIMsets the valley level of the inductor current.

7.3.7.2 V_DDUndervoltage Lockout (UVLO)

The TPS549B22 device has an UVLO protection function for the V_DDsupply input. The on-threshold voltage is

4.25 V with 200 mV of hysteresis. During a UVLO condition, the device is disabled regardless of the EN_UVLO

pin voltage. The supply voltage (V_VDD) must be above the on-threshold to begin the pin strap detection.

7.3.7.3 Overvoltage Protection (OVP) and Undervoltage Protection (UVP)

The device monitors a feedback voltage to detect overvoltage and undervoltage. When the feedback voltage

becomes lower than 68% of the target voltage, the UVP comparator output goes high and an internal UVP delay

counter begins counting. After 1 ms, the device latches OFF both high-side and low-side MOSFETs drivers. The

UVP function enables after soft-start is complete.

When the feedback voltage becomes higher than 120% of the target voltage, the OVP comparator output goes

high and the circuit latches OFF the high-side MOSFET driver and turns on the low-side MOSFET until reaching

a negative current limit. Upon reaching the negative current limit, the low-side FET is turned off and the high-side

FET is turned on again for a minimum on-time. The TPS549B22 device operates in this cycle until the output

voltage is pulled down under the UVP threshold voltage for 1 ms. The fault is cleared with a reset of VDD or by

retoggling the EN pin.

Table 1. Overvoltage Protection Details

REFERENCE

VOLTAGE

START-UP

OVP

THRESHOLD

OPERATING

OVP

THRESHOLD

OVP DELAY

100 mV OD

(µs)

SOFT-START

RAMP

OVP RESET

(V_REF

)

1.2 × Internal

V_REF

1.2 × Internal

V_REF

Internal

1

UVP

7.3.7.4 Out-of-Bounds Operation

The device has an out-of-bounds (OOB) overvoltage protection that protects the output load at a much lower

overvoltage threshold of 8% above the target voltage. OOB protection does not trigger an overvoltage fault, so

the device is not latched off after an OOB event. OOB protection operates as an early no-fault overvoltage-

protection mechanism. During the OOB operation, the controller operates in forced PWM mode only by turning

on the low-side FET. Turning on the low-side FET beyond the zero inductor current quickly discharges the output

capacitor thus causing the output voltage to fall quickly toward the setpoint. During the operation, the cycle-by-

cycle negative current limit is also activated to ensure the safe operation of the internal FETs.

7.3.7.5 Overtemperature Protection

TPS549B22 device has overtemperature protection (OTP) by monitoring the die temperature. If the temperature

exceeds the threshold value (default value 165°C), TPS549B22 device is shut off. When the temperature falls

about 25°C below the threshold value, the device turns on again. The OTP is a non-latch protection.

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7.4 Device Functional Modes

7.4.1 DCAP3 Control Topology

The TPS549B22 employs an artificial ramp generator that stabilizes the loop. The ramp amplitude is

automatically adjusted as a function of selected switching frequency (f_SW) The ramp amplitude is a function of

duty cycle (V_OUT-to-V_INratio). Consequently, two additional pin-strap bits are provided for fine tuning the internal

ramp amplitude. The device uses an improved DCAP3 control loop architecture that incorporates a steady-state

error integrator. The slow integrator improves the output voltage DC accuracy greatly and presents minimal

impact to small signal transient response. To further enhance the small signal stability of the control loop, the

device uses a modified ramp generator that supports a wider range of output LC stage.

7.4.2 DCAP Control Topology

For advanced users of this device, the internal DCAP3 ramp can be disabled using the MODE[4] pin-strap bit.

This situation requires an external RCC network to ensure control loop stability. Place this RCC network across

the output inductor. Use a range between 10 mV and 15 mV of injected RSP pin ripple. If no feedback resistor

divider network is used, insert a 10-kΩ resistor between the VOUT pin and the RSP pin.

7.5 Programming

7.5.1 Programmable Pin-Strap Settings

ADDR, VSEL and MODE. Description: a 1% or better 100-kΩ resistor is needed from BP to each of the three

pins. The bottom resistor from each pin to ground (see MODE, VSEL, ADDR DETECTION section of the

Electrical Characteristics table) in conjunction with the top resistor defines each pin strap selection. The pin

detection checks for external resistor divider ratio during initial power up (VDD is brought down below

approximately 3 V) when BP LDO output is at approximately 2.9 V.

7.5.1.1 Address Selection (ADDR) Pin

The TPS549B22 allows up to 16 different chip addresses for PMBus communication with the first 3 bits fixed as

001. The address selection process is defined by resistor divider ratio from BP pin to ADDR pin, and the address

detection circuit starts to work only after the initial power up when V_DDhas risen above its UVLO threshold.

Table 4 lists all combinations of the address selections. The 1% or better tolerance resistors with typical

temperature coefficient of ±100ppm/°C are recommended.

ADDR pin-strap configuration also programs the light load conduction mode.

7.5.1.2 VSEL Pin

VSEL pin strap configuration is used to program initial boot voltage value, hiccup mode and latch off mode. The

initial boot voltage is used to program the main loop voltage reference point. VSEL voltage settings provide TI

designated discrete internal reference voltages. Table 2 lists internal reference voltage selections.

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Table 2. Internal Reference Voltage Selections

(1)

VSEL[4]

VSEL[3]

VSEL[2]

VSEL[1]

VSEL[0]

1: Latch-Off

0: Hiccup

R_VSEL(kΩ)

Open

187

1111: 0.975 V

1: Latch-Off

0: Hiccup

165

1110: 1.1992 V

1101: 1.1504 V

1100: 1.0996 V

1011: 1.0508 V

1010: 1.0000 V

1001: 0.9492 V

1000: 0.9023 V

0111: 0.9004 V

0110: 0.8496 V

0101: 0.8008 V

0100: 0.7500 V

0011: 0.6992 V

0010: 0.6504 V

0001: 0.5996 V

0000: 0.975 V

147

1: Latch-Off

0: Hiccup

133

121

1: Latch-Off

0: Hiccup

110

100

1: Latch-Off

0: Hiccup

90.9

82.5

75

1: Latch-Off

0: Hiccup

68.1

60.4

53.6

47.5

42.2

37.4

33.2

29.4

25.5

22.1

19.1

16.5

14.3

12.1

10

1: Latch-Off

0: Hiccup

1: Latch-Off

0: Hiccup

1: Latch-Off

0: Hiccup

1: Latch-Off

0: Hiccup

1: Latch-Off

0: Hiccup

1: Latch-Off

0: Hiccup

1: Latch-Off

0: Hiccup

1: Latch-Off

0: Hiccup

7.87

6.19

4.64

3.16

1.78

0

1: Latch-Off

0: Hiccup

1: Latch-Off

0: Hiccup

(1) 1% or better and connect to ground

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7.5.1.3 DCAP3 Control and Mode Selection

The MODE pinstrap configuration programs the control topology and internal soft-start timing selections. The

TPS549B22 device supports both DCAP3 and DCAP operation

MODE[4] selection bit is used to set the control topology. If MODE[4] bit is 0, it selects DCAP operation. If

MODE[4] bit is 1, it selects DCAP3 operation.

MODE[1] and MODE[0] selection bits are used to set the internal soft-start timing.

Table 3. Allowable MODE Pin Selections

(1)

MODE[4]

MODE[3]

MODE[2]

MODE[1]

MODE[0]

R_MODE(kΩ)

60.4

11: 8 ms⁽²⁾

10: 4 ms⁽²⁾

01: 2 ms

53.6

0: Internal

Reference

1: DCAP3

0: Internal SS

47.5

00: 1 ms

42.2

11: 8 ms⁽²⁾

10: 4 ms⁽²⁾

01: 2 ms

4.64

3.16

0: Internal

Reference

0: DCAP

0: Internal SS

1.78

00: 1 ms

0

(1) 1% or better and connect to ground

(2) See Application Workaround to Support 4-ms and 8-ms SS Settings.

7.5.1.4 Application Workaround to Support 4-ms and 8-ms SS Settings

In order to properly design for 4-ms and 8-ms SS settings, additional application consideration is needed. The

recommended application workaround to support the 4-ms and 8-ms soft-start settings is to ensure sufficient time

delay between the V_DDand EN_UVLO signals. The minimum delay between the rising maximum V_DDUVLO level

and the minimum turn on threshold of EN_UVLO is at least T_{DELAY_MIN}

.

T_{DELAY _MIN}= K ì V_REF

where

•

K = 9 ms/V for SS setting of 4 ms

K = 18 ms/V for SS setting of 8 ms

V_REFis the internal reference voltage programmed by VSEL pin strap

(1)

For example, if SS setting is 4 ms and V_REF= 1 V, program the minimum delay at least 9 ms; if SS setting is 8

ms, the minimum delay should be programmed at least 18 ms. See Figure 27 and Figure 28 for detailed timing

requirement. Because TPS549B22 is a PMBus device, the end user has the option of programming power-on

delay (POD) as another workaround. Be sure to follow the same calculation to determine the needed POD (see

MFR_SPECIFIC_01 (address = D1h) and Table 25 for detailed information).

Figure 27. Proper Sequencing of V_DDand EN_UVLO to Support the use of 4-ms SS Setting

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V_DD

V_DD_UVLO

Maximum Threshold

4.34 V

EN_UVLO

Minimum ON Threshold 1.45 V

Minimum

T_{DELAY_MIN}

Figure 28. Minimum Delay Between V_DDand EN_UVLO to Support the use of 4-ms and 8-ms SS settings

The workaround/consideration described previously is not required for SS settings of 1 ms and 2 ms.

7.5.2 Programmable Analog Configurations

7.5.2.1 RSP/RSN Remote Sensing Functionality

RSP and RSN pins are used for remote sensing purpose. In the case where feedback resistors are required for

output voltage programming, connect the RSP pin to the mid-point of the resistor divider, and connect the RSN

pin to the load return. In the case where feedback resistors are not required as when the VSEL programs the

output-voltage setpoint, connect the RSP pin to the positive sensing point of the load, and the RSN pin must

always be connected to the load return.

RSP and RSN pins are extremely high-impedance input terminals of the true differential remote sense amplifier.

The feedback resistor divider must use resistor values much less than 100 kΩ.

7.5.2.1.1 Output Differential Remote Sensing Amplifier

The examples in this section show simplified remote sensing circuitry where each example uses an internal

reference of 1 V. Figure 29 shows remote sensing without feedback resistors, with an output voltage setpoint of 1

V. Figure 30 shows remote sensing using feedback resistors, with an output voltage setpoint of 5 V.

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TPS549B22

38 RSN

39 RSP

40 VOSNS

BOOT

5

Load

+

œ

+

œ

Figure 29. Remote Sensing Without Feedback

Resistors

Figure 30. Remote Sensing With Feedback

Resistors

7.5.2.2 Power Good (PGOOD Pin) Functionality

The TPS549B22 device has power-good output that registers high when switcher output is within the target. The

power-good function is activated after soft start has finished. When the soft-start ramp reaches 300 mV above

the internal reference voltage, SS end signal goes high to enable the PGOOD detection function. If the output

voltage becomes within ±8% of the target value, internal comparators detect power-good state and the power-

good signal becomes high after a 1-ms programmable delay. If the output voltage goes outside of ±16% of the

target value, the power-good signal becomes low after two microsecond (2-µs) internal delay. The open-drain

power-good output must be pulled up externally. The internal N-channel MOSFET does not pull down until the

V_DDsupply is above 1.2 V.

7.5.3 PMBus Programming

TPS549B22 has seven internal custom user-accessible 8-bit registers. The PMBus interface has been designed

for program flexibility, supporting direct format for write operation. Read operations are supported for both

combined format and stop separated format. While there is no auto increment/decrement capability in the

TPS549B22 PMBus logic, a tight software loop can be designed to randomly access the next register

independent of which register was accessed first. The start and stop commands frame the data packet and the

repeat start condition is allowed when necessary.

7.5.3.1 TPS549B22 Limitations to the PMBUS Specifications

TPS549B22 only recognizes seven bit addressing. This means TPS549B22 is not compatible with ten bit

addressing and CBUS communication. The device can operate in standard mode (100 kbit/s), fast mode (400

kbit/s) or faster mode (1000 kbit/s).

7.5.3.2 Slave Address Assignment

The seven bit slave address is 001A₃A₂A₁A₀x, where A₃A₂A₁A₀is set by the ADDR pin on the device. Bit 0 is the

data direction bit, i.e. 001A₃A₂A₁A₀0 is used for write operation and 001A₃A₂A₁A₀1 is used for read operation.

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7.5.3.3 PMBUS Address Selection

TPS549B22 allows up to 16 different chip addresses for PMBus communication, with the first three bits fixed as

001. The address selection process is defined by the resistor divider ratio from BP pin to ADDR pin, and the

address detection circuit will start to work only after V_DDinput supply has risen above its UVLO threshold.

Table 4 lists the divider ratio and some example resistor values. The 1% tolerance resistors with typical

temperature coefficient of ±100 ppm/ºC are recommended. Higher performance resistors can be used if tighter

noise margin is required for more reliable address detection.

7.5.3.4 Supported Formats

The supported formats are described in the following subsections.

7.5.3.4.1 Direct Format — Write

The simplest format for a PMBus write is direct format. After the start condition [S], the slave chip address is

sent, followed by an eighth bit indicating a write. TPS549B22 then acknowledges that it is being addressed, and

the master responds with an 8 bit register address byte. The slave acknowledges and the master sends the

appropriate 8-bit data byte. Once again the slave acknowledges and the master terminates the transfer with the

stop condition [P].

7.5.3.4.2 Combined Format — Read

After the start condition [S], the slave chip address is sent, followed by an eighth bit indicating a write.

TPS549B22 then acknowledges that it is being addressed, and the master responds with an 8-bit register

address byte. The slave acknowledges and the master sends the repeated start condition [Sr]. Once again, the

slave chip address is sent, followed by an eighth bit indicating a read. The slave responds with an acknowledge

followed by previously addressed 8-bit data byte. The master then sends a non-acknowledge (NACK) and finally

terminates the transfer with the stop condition [P].

7.5.3.5 Stop Separated Reads

Stop-separated reads can also be used. This format allows a master to set up the register address pointer for a

read and return to that slave at a later time to read the data. In this format the slave chip address followed by a

write bit are sent after a start [S] condition. TPS549B22 then acknowledges it is being addressed, and the master

responds with the 8-bit register address byte. The master then sends a stop or restart condition and may then

address another slave. After performing other tasks, the master can send a start or restart condition to the

TPS549B22 with a read command. The device acknowledges this request and returns the data from the register

location that had been set up previously.

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Table 4. ADDR Pin Selection Table

RADDR (kΩ)

PMBus_Address<3:0>

CM

(1% or better and

connect to ground)

1: FCCM

0: SKIP

1: FCCM

0: SKIP

1: FCCM

0: SKIP

1: FCCM

0: SKIP

1: FCCM

0: SKIP

1: FCCM

0: SKIP

1: FCCM

0: SKIP

1: FCCM

0: SKIP

1: FCCM

0: SKIP

1: FCCM

0: SKIP

1: FCCM

0: SKIP

1: FCCM

0: SKIP

1: FCCM

0: SKIP

1: FCCM

0: SKIP

1: FCCM

0: SKIP

1: FCCM

0: SKIP

Open

187

165

147

133

121

110

100

90.9

82.5

75

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

68.1

60.4

53.6

47.5

42.2

37.4

33.2

29.4

25.5

22.1

19.1

16.5

14.3

12.1

10

7.87

6.19

4.64

3.16

1.78

0

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7.5.3.6 Supported PMBUS Commands and Registers

Only the following PMBus commands are supported by TPS549B22, and not all parts of each command are

supported.

Table 5. PMBUS Command and Register Table

No. of DATA

BYTES

CMD CODE

COMMAND NAME

DESCRIPTION

NVM?

TYPE

BIT PATTERN

00XX XX00 = Turn Off

1000 XX00 = Turn on (VOUT Margin off)

1001 0100 = Turn on (VOUT Margin Low, Ignore

Fault)

1001 1000 = Turn on (VOUT Margin Low, Act on

Fault)

1010 0100 = Turn on (VOUT Margin High,

Ignore Fault)

1010 1000 = Turn on (VOUT Margin High, Act

on Fault)

The OPERATION command is

used to turn the unit on and off

in conjunction with the input

from the EN pin. It is also used

to cause the device to set the

output voltage to the upper or

lower margin voltages.

1h

OPERATION

no

R/W Byte

1

0001 0011 = Act on neither OPERATION nor EN

Configures the combination of

EN pin input and serial bus

commands needed to turn the

unit on and off. This includes

how the unit responds when

power is applied.

0001 0111 = Act on EN pin and ignore

OPERATION

0001 1011 = Act on OPERATION and ignore EN

0001 1111 = Act on OPERATION and Act on EN

pin (requires both)

2h

ON_OFF_CONFIG

yes

R/W Byte

1

Clears all fault status registers

to 0x00 and deasserts

SMBAlert. The "Unit is Off" bit

in the status byte and

"PGOOD# de-assertion" bit in

the status word are not cleared

when this command is issued.

3h

CLEAR_FAULTS

no

Send Byte

R/W Byte

0

1

No data. Write only.

1000 0000 Only allow WRITE_PROTECT

0100 0000 Only allow WRITE_PROTECT and

OPERATION

0010 0000 Only allow WRITE_PROTECT,

OPERATION, ON_OFF_CONFIG and

VOUT_COMMAND

Prevents unwanted writes to

the device. This register can be

over-written. This is not a

permanent lock.

10h

WRITE_PROTECT

yes

0000 0000 Allow all writes

Copies Operating Memory to

matching non-volatile Default

Store Memory.

11h

12h

STORE_DEFAULT_ALL

no

Send Byte

0

No data. Write only.

Restores all parameters from

non-volatile Default Store

RESTORE_DEFAULT_ALL

Memory to Operating Memory

This command provides a way

for a host system to determine

some key capabilities of a

PMBus device, including PEC,

Alert and Speed.

19h

CAPABILITY

no

Read Byte

1

1101 0000 = PEC, 1-MHz bus speed, ALERT

000x xxxx = Linear format.

0001 0111 = Exponent value of –9 (1.953 mV

resolution)

Hard coded to linear mode with

exponent of –9.

20h

21h

VOUT_MODE

no

Read Byte

R/W Word

1

2

Output voltage setpoint. DAC

resolution is 1.9531 mV and

range is ~0.6 V to ~1.200 V

0000 0001 0011 0011 = 0.5996 V

0000 0010 0110 0110 = 1.1992 V

VOUT_COMMAND

yes

Sets the voltage to which the

output is to be changed when

the OPERATION command is

set to "MARGIN HIGH".

0000 0001 0011 0011 = 0.5996 V

0000 0010 0110 0110 = 1.1992 V

25h

26h

VOUT_MARGIN_HIGH

VOUT_MARGIN_LOW

no

R/W Word

2

Sets the voltage to which the

output is to be changed when

the OPERATION command is

set to "MARGIN LOW".

0000 0001 0011 0011 = 0.5996 V

0000 0010 0110 0110 = 1.1992 V

Status of all fault conditions in a

data byte.

78h

79h

STATUS_BYTE

STATUS_WORD

no

Read Byte

Read Word

1

2

See Table 6

Status of all fault conditions in

two data bytes.

Returns one byte of information

relating to the status of the

output voltage related faults.

7Ah

7Bh

STATUS_VOUT

STATUS_OUT

no

Read Byte

1

See Table 8

Returns one byte of information

relating to the status of the

output current related faults.

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Table 5. PMBUS Command and Register Table (continued)

No. of DATA

COMMAND NAME

DESCRIPTION

NVM?

TYPE

BIT PATTERN

BYTES

XXX0 0000

0XX0 0000 = A valid or supported command has

been received

1XX0 0000 = An invalid or unsupported

command has been received

X0X0 0000 = A valid or supported data has been

received

Status of communications, logic

and memory in a data byte

7Eh

STATUS_CML

no

Read Byte

1

X1X0 0000 = An invalid or unsupported data has

been received

XX00 0000 = Packet error check has failed

XX10 0000 = Packet error check has succeeded

Customer programmable byte

that does not affect chip

functionality

D0h

D1h

D2h

D3h

MFR_SPECIFIC_00

MFR_SPECIFIC_01

MFR_SPECIFIC_02

MFR_SPECIFIC_03

yes

R/W Byte

1

Program PGOOD delay and

Power-On delay

Read SST, CM, HICLOFF, TRK

and SEQ. Program Forced

SKIP Soft Start.

Program Fsw and control

mode, Read RC ramp

Free format

D4h

D6h

MFR_SPECIFIC_04

MFR_SPECIFIC_06

Program the DCAP3 offset

Program the V_DDUVLO level

yes

R/W Byte

1

Program the final tracking set

point and select

pseudo/external tracking

D7h

FCh

MFR_SPECIFIC_07

MFR_SPECIFIC_44

yes

no

R/W Byte

1

2

Read TI PMBUS GUI Devcie ID

and IC revision code

Read Word

spacer

Figure 31. Start-up and VOUT_COMMAND Timing Diagram

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Table 6. Status Word Summary Table

BITS

Low 7

Low 6

Low 5

Low 4

Low 3

NAME

MEANING

not used

OFF

Unit is not providing power to the output

Output overvoltage

VOUT_OV_FAULT

IOUT_OC_FAULT

VDD_UV_FAULT

Output overcurremt

Input V_DDundervoltage

Internal die temperature.

Overtemperature fault

Low 2

TEMP

Low 1

Low 0

High 7

High 6

High 5

High 4

High 3

High 2

High 1

High 0

CML

OTHER

Communications, logic or memory fault

None of the above in the PMBUS spec

Any output voltage fault or warning

Any output current fault or warning

Input V_DDundervoltage

Not used

VOUT

IOUT

VDD_UV_FAULT

not used

PGOOD#

not used

Power good de-asserted

not used

Table 7. Status V_OUTSummary Table

BITS

NAME

MEANING

7

6

5

4

3

2

1

OVF

Overvoltage fault

OVW

UVW

Overvoltage warning

Undervoltage warning

Undervoltage fault

not used

UVF

not used

Table 8. Status I_OUTSummary Table

BITS

NAME

MEANING

7

OCF

Overcurrent fault

Overcurrent and output undervoltage

fault

6

OCUVF

5

4

3

2

1

0

not used

UCF

not used

Negative overcurrent limit

not used

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7.6 Register Maps

7.6.1 OPERATION Register (address = 1h)

Figure 32. OPERATION

7

6

0

5

4

3

2

1

0

On_OFF

R/W

OPMARGIN<3:0>

R/W

R

RLEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 9. OPERATION

Bit

7

Field

Type

R/W

R

Reset

Description

0: Turn off switching converter (if CMD=1)

1: Turn on switching converter (if CMD=1), and also enable

VOUT Margin function

ON_OFF

0

6

00xx: Turn off VOUT Margin function

0101: Turn on VOUT Margin Low and Ignore Fault

0110: Turn on VOUT Margin Low and Act On Fault

1001: Turn on VOUT Margin High and Ignore Fault

1010: Turn on VOUT Margin High and Act On Fault

5:2

OPMARGIN<3:0>

R/W

0

1

0

R

0

7.6.2 ON_OFF_CONFIG Register (address = 2h)

Figure 33. ON_OFF_CONFIG

7

0

6

0

5

0

4

3

2

1

0

1

CMD

R/W

CP

R/W

R

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 10. ON_OFF_CONFIG

Bit

7

Field

Type

R

Reset

Description

0

1

6

R

5

R

4

R

0: Ignore ON_OFF bit

1: Act on ON_OFF bit

3

2

CMD

CP

R/W

0

1

0: Ignore ON_OFF bit

1: Act on ON_OFF bit

1

0

R

1

7.6.3 CLEAR FAULTS (address = 3h)

The CLEAR_FAULTS command is used to clear any fault bits that have been set. This command simultaneously

clears all bits in all status registers. At the same time, the device clears its SMB_ALERT# signal output if the

device is asserting the SMB_ALERT# signal.

The CLEAR_FAULTS command does not cause a unit that has latched off for a fault condition to restart. If the

fault is still present when the bit is cleared, the fault bit shall immediately be set again and the host notified by the

usual means.

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7.6.4 WRITE PROTECT (address = 10h)

Figure 34. WRITE PROTECT

7

0

6

0

5

0

4

0

3

0

2

0

1

0

R/W

R

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 11. WRITE PROTECT

Bit

Field

Type

Reset

Description

00000000: Enable writes to ALL commands

00100000: Enable writes to only WRITE_PROTECT,

OPERATION and ON_OFF_CONFIG and VOUT_COMMAND

commands

7:0

WRITE_PROTECT

R/W

0

01000000: Enable writes to only WRITE_PROTECT and

OPERATION

10000000: Enable writes to only WRITE_PROTECT

7.6.5 STORE_DEFAULT_ALL (address = 11h)

Store all of the current storable register settings in the EEPROM memory as the new defaults on power up.

It is permitted to use the STORE_DEFAULT_ALL command while the device is operating. However, the device

may be unresponsive during the write operation with unpredictable memory storage results. TI recommends to

turn the device output off before issuing this command.

EEPROM programming faults will set the ‘CML’ bit in the STATUS_BYTE and the ‘MEM’ bit in the STATUS_CML

registers.

7.6.6 RESTORE_DEFAULT_ALL (address = 12h)

Write EEPROM data to those CSRs that: (1) have EEPROM support, and; (2) are unprotected according to

current setting of WRITE_PROTECT.

It is permitted to use the RESTORE_DEFAULT_ALL command while the device is operating. However, the

device may be unresponsive during the copy operation with unpredictable, undesirable or even catastrophic

results. TI recommends turning the device output off before issuing this command.

No data bytes are sent, just the command code is sent.

7.6.7 CAPABILITY (address = 19h)

This command provides a way for a host system to determine some key capabilities of this PMBus device.

Figure 35. CAPABILITY

7

PEC=1

R

6

5

4

ALRT=1

R

3

0

2

0

1

0

SPEED <1:0>

R

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 12. CAPABILITY

Bit

7

Field

Type

R

Reset

1

Description

1: Packet Error Checking is supported

10: Maximum supported bus speed is 1 MHz

PEC=1

6:5

SPEED <1:0>

R

10b

TPS549B22 has an ALERT# pin and it supports SMBus Alert Response

protocol

4

ALRT=1

R

1

3

2

1

0

R

0

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7.6.8 VOUT_MODE (address = 20h)

Figure 36. VOUT_MODE

7

6

MODE = 000

R

5

4

3

2

1

0

Exponent = 10111

R

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 13. VOUT_MODE

Bit

7:5

4:0

Field

Type

R

Reset

0

Description

000: Linear Format

10111: Exponent = −9 (equivalent of 1.9531 mV/LSB)

MODE = 000

Exponent

R

17h

7.6.9 VOUT_COMMAND (address = 21h)

The VOUT_COMMAND command sets the output voltage in volts. The exponent is set be VOUT_MODE at –9

(equivalent of 1.9531 mV/LSB). The programmed V_OUTis computed as:

V_OUT= VOUT_COMMAND × VOUT_MODE volts = VOUT_COMMAND × 2^–9

V

(2)

The support range for TPS549B22 is: 0.5996 V to 1.1992 V. It is effectively 9 bits limited to 307 to 614 decimal.

Slew-rate control is provided through MODE pin.

V_OUTchanges 1 step per t_slew, where t_slewis programmable by MODE pin: 4, 8, 16, or 32 µs.

Figure 37. VOUT_COMMAND

7

6

5

4

3

2

1

0

7

6

5

4

3

2

1

0

Mantissa

R/W

R

R/W

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 14. VOUT_COMMAND

Bit

7:4

3:0

7:0

Field

Type

R

Reset

0000

Description

Mantissa

R/W

00xx

x = pin strap

xxxx xxxx

7.6.10 VOUT_MARGIN_HIGH (address = 25h) ®

The VOUT_MARGIN_HIGH command loads the TPS549B22 with the voltage to which the output is to be

changed when the OPERATION command is set to “Margin High”.

The data bytes are two bytes formatted according to the setting of the VOUT_MODE command.

The support margin range for TPS549B22 is: 0.5996 V to 1.1992 V. It is effectively 9 bits limited to 307 to 614

decimal. Slew-rate control is provided through MODE pin.

Figure 38. VOUT_MARGIN_HIGH

7

6

5

4

3

2

1

0

7

6

5

4

3

2

1

0

Mantissa

R/W

R

R/W

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 15. VOUT_MARGIN_HIGH

Bit

7:4

3:0

7:0

Field

Type

R

Reset

0000

Description

Mantissa

R/W

00xx

x = pin strap

xxxx xxxx

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7.6.11 VOUT_MARGIN_LOW (address = 26h)

The VOUT_MARGIN_LOW command loads the TPS549B22 with the voltage to which the output is to be

changed when the OPERATION command is set to “Margin Low”.

The data bytes are two bytes formatted according to the setting of the VOUT_MODE command.

The support margin range for TPS549B22 is: 0.5996 V to 1.1992 V. It is effectively 9-bits limited to 307 to 614

decimal. Slew-rate control is provided through MODE pin.

Figure 39. VOUT_MARGIN_LOW:

7

6

5

4

3

2

1

0

7

6

5

4

3

2

1

0

Mantissa

R/W

R

R/W

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 16. VOUT_MARGIN_LOW:

Bit

7:4

3:0

7:0

Field

Type

R

Reset

0000

Description

Mantissa

R/W

00xx

x = pin strap

xxxx xxxx

7.6.12 STATUS_BYTE (address = 78h)

Figure 40. STATUS_BYTE

7

Not used

R

6

OFF

R

5

VOUT_OV

R

4

IOUT_OC

R

3

VDD_UV

R

2

TEMP

R

1

0

CML

R

OTHER

R

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 17. STATUS_BYTE

Bit

Field

Type

Reset

Description

7

Not Used

R

N/A

Not used

0: IC is on. This includes the following fault response conditions

where the output is still being actively driven, such as OVP and

OCF.

1: IC is off. This includes two conditions. One is unit is

commanded off via OPERATION/ON_OFF _CONFIG and the

other is unit is commanded on via

6

OFF

R

N/A

OPERATION/ON_OFF_CONFIG; but, due to fault response the

output has been tri-stated by UVF, OT and UVLO.

0: An output overvoltage fault has not occurred

1: An output overvoltage fault has occurred

5

4

3

2

1

0

VOUT_OV

IOUT_OC

VDD_UV

TEMP

R

N/A

0: An output overcurrent fault has not occurred

1: An output overcurrent fault has occurred

0: An input undervoltage fault has not occurred

1: An input undervoltage fault has occurred

0: A temperature fault or warning has not occurred

1: A temperature fault or warning has occurred

0: A communications, memory or logic fault has not occurred

1: A communications, memory or logic fault has occurred

CML

0: A fault or warning not listed above has not occurred

1: A fault of warning not listed above has occurred

OTHER

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7.6.13 STATUS_WORD (High Byte) (address = 79h)

Figure 41. STATUS_WORD (High Byte)

7

VOUT

R

6

IOUT

R

5

VDD

R

4

Not Used

R

3

PGOOD#

R

2

1

Not Used

R

0

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 18. STATUS_WORD (High Byte)

Bit

Field

Type

Reset

Description

0: An output voltage fault or warning has not occurred

1: An output voltage fault or warning has occurred

7

VOUT

R

N/A

0: An output current fault has not occurred

1:An output current fault has occurred

6

IOUT

R

N/A

A VDD voltage fault has not occurred

1: A VDD voltage fault has occurred

5

4

VDD

R

N/A

Not Used

0: PGOOD pin is at logic high

1: PGOOD pin is at logic high

3

PGOOD#

Not Used

R

N/A

2:0

Not used

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7.6.14 STATUS_VOUT (address = 7Ah)

Figure 42. STATUS_VOUT

7

OVF

R

6

OVW

R

5

UVW

R

4

UVF

R

3

2

1

0

Not Used

R

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 19. STATUS_VOUT

Bit

Field

Type

Reset

Description

0: An output overvoltage fault has not occurred

1: An output overvoltage fault has occurred

7

OVF

R

N/A

0: An output overvoltage warning has not occurred

1: An output overvoltage warning has occurred

6

5

OVW

UVW

R

N/A

0: An output undervoltage warning has not occurred

1: An output undervoltage warning has occurred

0: An output undervoltage fault has not occurred

1: An output undervoltage fault has occurred

4

UVF

R

N/A

3:0

Not Used

7.6.15 STATUS_IOUT (address = 7Bh)

Figure 43. STATUS_IOUT

7

OCF

R

6

OCUVF

R

5

Not Used

R

4

UCF

R

3

2

1

0

Not Used

R

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 20. STATUS_IOUT

Bit

Field

Type

Reset

Description

0: An output positive overcurrent fault has not occurred

1: An output positive overcurrent fault has occurred

7

OCF

R

N/A

0: A simultaneous output positive overcurrent and undervoltage

fault has not occurred

1: A simultaneous output positive overcurrent and undervoltage

fault has occurred

6

OCUVF

R

N/A

5

4

Not Used

UCF

R

N/A

Not Used

0: An output negative overcurrent fault has not occurred

1: An output negative overcurrent fault has occurred

3:0

Not Used

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7.6.16 STATUS_CML (address = 7Eh)

Figure 44. STATUS_CML

7

COMM

R

6

DATA

R

5

PEC

R

4

3

Not Used

R

2

1

OTH

R

0

Not Used

R

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 21. STATUS_CML

Bit

Field

Type

Reset

Description

0: A valid or supported command has been received

1: An invalid or unsupported command has been received

7

COMM

R

N/A

0: A valid or supported data has been received

1: An invalid or unsupported data has been received

6

DATA

R

N/A

0: Packet Error Check has failed

1: Packet Error Check has succeeded

5

PEC

R

N/A

4:2

Not Used

0: A communication fault other than the ones listed in this table

has not occurred

1: A communication fault other than the ones listed in this table

has occurred. Currently, this bit is only set for too many data

bytes

1

0

OTH

R

N/A

Not Used

7.6.17 MFR_SPECIFIC_00 (address = D0h)

Figure 45. MFR_SPECIFIC_00

7

6

5

4

3

2

1

0

USER SCRATCH PAD

R/W

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 22. MFR_SPECIFIC_00

Bit

Field

Type

Reset

Description

The MFR_SPECIFIC_00 is a user-accessible register dedicated

as a user scratch pad.

7:0

USER SCRATCH PAD

R/W

0

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7.6.18 MFR_SPECIFIC_01 (address = D1h)

Figure 46. MFR_SPECIFIC_01

7

0

6

0

5

4

3

2

1

0

PGD

R/W

POD

R/W

R

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 23. MFR_SPECIFIC_01

Bit

7:6

5:3

2:0

Field

Type

R

Reset

00b

Description

The MFR_SPECIFIC_01 is a user-accessible register dedicated

for configuring the PGOOD delay and Power-On Delay

functions. (Refer to Table 24 and Table 25)

PGD

POD

R/W

010b

Table 24. PGD[2:0]

PGD[2]

PGD[1]

PGD[0]

PGood Delay

256 µs

0

1

0

1

0

1

0

1

0

1

0

1

0

1

512 µs

1.024 ms

2.048 ms

4.096 ms

8.192 ms

16.384 ms

131.072 ms

Table 25. POD[2:0]

POD[2]

POD[1]

POD[0]

Power-On Delay

256 µs

0

1

0

1

0

1

0

1

0

1

0

1

0

1

512 µs

1.024 ms

2.048 ms

4.096 ms

8.192 ms

16.384 ms

32.768 ms

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7.6.19 MFR_SPECIFIC_02 (address = D2h)

The MFR_SPECIFIC_02 register allows the user to read the configuration of various pin-strap features and/or

overwrite them. Note that any overwritten values here are only good until the next power-on-reset, when all

parameters revert back to their pin-strap configurations.

Figure 47. MFR_SPECIFIC_02

7

6

5

0

4

3

2

1

0

TRK

R/W

SEQ

R/W

FORCESKIPSS

R/W

SST

R/W

HICLOFF

R/W

CM

R/W

R

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 26. MFR_SPECIFIC_02

Bit

Field

Type

Reset

Description

This bit indicates whether the device is using internal or external

reference voltage tracking. It will initially be loaded and reflect

the value of the pin strap; but, can also be overwritten by

PMBus.

7

TRK

R/W

P

0: No tracking. The device will use internal reference voltage.

1: External tracking.

This bit indicates whether the device is using internal or external

soft-start ramp. It will initially be loaded and reflect the value of

the pin strap; but, can also be overwritten by PMBus.

0: No sequencing. The device will use the internal soft start

ramp.

6

5

4

SEQ

R/W

R

P

0

1

1: Sequencing

This bit (when set) allows the user to force Soft-start to always

use SKIP mode; regardless of the CM pin strap.

0: CM bit controls whether to operate in SKIP or FCCM mode

during and after soft start.

FORCESKIPSS

R/W

1: Soft start is forced to operate in SKIP mode, then CM bit

controls the mode after soft start.

These bits indicate the time the device takes to ramp the output

voltage up to regulation (that is, soft-start). The field will initially

be loaded and reflect the value of the pin strap; but, can also be

overwritten by PMBus. (Refer to Table 27)

3:2

SST

R/W

P

This bit indicates the response the device will take upon an

output undervoltage fault. There are two fault response options

which are enforced by the analog circuits: Hiccup or Latch-off.

The bit value will initially be loaded and reflect the value of the

pin strap; but, can also be overwritten by PMBus.

0: Hiccup after UVP fault.

1

HICLOFF

1: Latch off after UVP fault.

This bit indicates the conduction mode for the device. The bit

value will initially be loaded and reflect the value of the pin strap;

0

CM

R/W

P

but,

can

also

be

overwritten

by

PMBus.

0: SKIP

1: FCCM

Table 27. SST

SST[1]

SST[0]

Soft-start time

1 ms

0

1

0

1

0

1

2 ms

4 ms

8 ms

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7.6.20 MFR_SPECIFIC_03 (address = D3h)

The MFR_SPECIFIC_03 register allows the user to read the configuration of the DCAP pin-strap feature (and/or

overwrite it), as well configure the Ramp Generator and the PWM switching frequency.

Figure 48. MFR_SPECIFIC_03

7

6

0

5

4

3

0

2

1

0

DCAP3

R/W

RCSP

R/W

FS

R

R/W

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 28. MFR_SPECIFIC_03 Field Descriptions

Bit

Field

Type

Reset

Description

This bit allows the user to read/configure the device’s internal

DCAP-3 mode. It is initially loaded and reflects the value of the

pin strap, but can also be overwritten by PMBus.

7

DCAP3

R/W

P

0: Internal DCAP3 is disabled (ramp injection is off).

1: Internal DCAP3 is enabled (ramp injection is on)

6

R

0

These bits allow the user to read/configure the D-CAP3 ramp

generator’s resistor value selection. (Refer to Table 29.)

5:4

3

RCSP

FS

R/W

R

P

0

These bits allow the user to read/configure the device’s PWM

switching frequency. (Refer to Table 30)

2:0

R/W

011b

Table 29. RCSP

RCSP[1]

RCSP[0]

Resistor Selection

Resistor ÷ 2

0

1

0

1

0

1

Resistor ÷ 1

Resistor × 2

Resistor × 3

Table 30. FS

FS[2]

FS[1]

FS[0]

Switching Frequency

315 kHz

0

1

0

1

0

1

0

1

0

1

0

1

0

1

425 kHz

550 kHz

650 KHz

825 KHz

900 KHz

1.025 MHz

1.125 MHz

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7.6.21 MFR_SPECIFIC_04 (address = D4h)

The MFR_SPECIFIC_04 register allows the user to configure the D-CAP offset reduction and fixed offset

correction.

Figure 49. MFR_SPECIFIC_04

7

6

5

4

0

3

0

2

0

1

0

DCAP3OffsetSel

R/W

DCAP3Offset[1:0]

R/W

R

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 31. MFR_SPECIFIC_04

Bit

Field

Type

Reset

Description

This bit allows the user to read/configure the D-CAP loop’s offset

reduction scheme.

0: Select DCAP loop manual offset reduction circuit.

1: Select DCAP loop automatic offset reduction circuit.

7

DCAP3OffsetSel

R/W

1

These bits allow the user to read/configure the D-CAP3 offset

correction if and only if DCAP3OffsetSel = 0 (refer to Table 32).

6:5

4:0

DCAP3Offset

R/W

R

0

Table 32. DCAP3OFFSET

Additional Offset Correction

Voltage Added

DCAP3Offset[1]

DCAP3Offset[0]

0

1

0

1

0

1

0 mV

+ 2 mV

+ 4 mV

+ 6 mV

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7.6.22 MFR_SPECIFIC_06 (address = D6h)

The MFR_SPECIFIC_06 is a user-accessible register dedicated for configuring the V_DDUVLO threshold.

Figure 50. MFR_SPECIFIC_06

7

0

6

0

5

0

4

0

3

0

2

1

0

VDDUVLO[2:0]

R/W

R

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 33. MFR_SPECIFIC_06

Bit

Field

Type

Reset

Description

7:3

R

0

These bits allow the user to read/configure the device V_DD

ULVO threshold (refer to Table 34).

2:0

VDDUVLO

R/W

101b

Table 34. VDDUVLO

VDDUVLO[2]

VDDUVLO[1]

VDDUVLO[0]

VDD UVLO threshold

10.2 volts

0

1

X

0

1

X

0

1

0

1

2.8 volts

4.25 volts

6 volts

8.1 volts

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7.6.23 MFR_SPECIFIC_07 (address = D7h)

The MFR_SPECIFIC_07 is a user-accessible register dedicated for configuring the device’s PGOOD threshold

and external tracking options.

Figure 51. MFR_SPECIFIC_07

7

6

5

0

4

3

2

1

0

VPBAD

R/W

SPARE

R/W

TRKOPTION

R/W

VTRKIN[3:0]

R/W

R

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 35. MFR_SPECIFIC_07

Bit

Field

Type

Reset

Description

This bit allows the user to read/configure the PGOOD high and

low thresholds.

0: PGOOD high and low thresholds are +16% and -16%,

respectively

7

VPBAD

R/W

1

1: PGOOD high and low thresholds are +20% and -32%,

respectively

This bit allows the user to read/configure an EEPROM backed

SPARE bit and corresponding digital block output.

0: pSPARE = 0

6

5

SPARE

R/W

R

0

1: pSPARE = 1

This bit allows the user to read/control whether the external

TRKIN is enabled by a 425 mV threshold, or not.

0: TRKIN voltage must be above 425mV (that is, TRKINOK = 1)

before switcher can be enabled.

1: TRKIN voltage does not need to be above 425mV before

switcher can be enabled.

4

TRKOPTION

VTRKIN

R/W

0

These bits allow the user to read/configure the device’s final

TRKIN target voltage for external tracking operation. (Refer to

Table 36)

3:0

1111b

Table 36. VTRKIN

Final TRKIN target

voltage for

external tracking

operation

VTRKIN[3]

VTRKIN[2]

VTRKIN[1]

VTRKIN[0]

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

500 mV

550 mV

600 mV

650 mV

700 mV

750 mV

800 mV

850 mV

900 mV

950 mV

1.00 V

1.05 V

1.10 V

1.15 V

1.20 V

1.25 V

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7.6.24 MFR_SPECIFIC_44 (address = FCh)

The DEVICE_CODE command returns a 12-bit unique identifier code for the device and a 4 bit device revision

code.

Figure 52. MFR_SPECIFIC_44

7

6

5

4

3

2

1

0

7

6

5

4

3

2

1

0

Identifier Code

Revision Code

R

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 37. MFR_SPECIFIC_44

Bit

7:0

7:4

3:0

Field

Type

R

Reset

Description

02h

0

Identifier Code

Revision Code

0000 0010 0000b – Device ID Code Identifier for TPS549B22.

1000b - Revision Code (first silicon starts at 0)

R

0

Can

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8 Application and Implementation

NOTE

Information in the following applications sections is not part of the TI component

specification, and TI does not warrant its accuracy or completeness. TI’s customers are

responsible for determining suitability of components for their purposes. Customers should

validate and test their design implementation to confirm system functionality.

8.1 Application Information

The TPS549B22 device is a highly-integrated synchronous step-down DC-DC converter with PMBus features

and capabilities. This devices is used to convert a higher DC input voltage to a lower DC output voltage, with a

maximum output current of 25 A. Use the following design procedure to select key component values for this

family of devices.

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8.2.2 Design Requirements

For this design example, use the input parameters shown in Table 38.

Table 38. Design Example Specifications

PARAMETER

Input voltage

V_IN(ripple)Input ripple voltage

TEST CONDITION

MIN

TYP

MAX

18

UNIT

V_IN

5

12

V

I_OUT= 25 A

0.4

V_OUT

Output voltage

1

Line regulation

5 V ≤ V_IN≤ 18 V

0 V ≤ I_OUT≤ 25 A

I_OUT= 25 A

0.5%

Load regulation

V_PP

V_OVER

V_UNDER

I_OUT

t_SS

Output ripple voltage

Transient response overshoot

Transient response undershoot

Output current

10

30

mV

A

I_STEP= 15 A

5 V ≤ V_IN≤ 18 V

25

Soft-start time

1

32

ms

A

I_OC

Overcurrent trip point

Peak efficiency

η

I_OUT= 7 A,

90%

650

f_SW

Switching frequency

kHz

8.2.3 Detailed Design Procedure

8.2.3.1 Custom Design With WEBENCH® Tools

Click here to create a custom design using the TPS549B22 device with the WEBENCH® Power Designer.

1. Start by entering the input voltage (V_IN), output voltage (V_OUT), and output current (I_OUT) requirements.

2. Optimize the design for key parameters such as efficiency, footprint, and cost using the optimizer dial.

3. Compare the generated design with other possible solutions from Texas Instruments.

The WEBENCH Power Designer provides a customized schematic along with a list of materials with real-time

pricing and component availability.

In most cases, these actions are available:

•

Run electrical simulations to see important waveforms and circuit performance

Run thermal simulations to understand board thermal performance

Export customized schematic and layout into popular CAD formats

Print PDF reports for the design, and share the design with colleagues

Get more information about WEBENCH tools at www.ti.com/WEBENCH.

8.2.3.2 Switching Frequency Selection

The default switching frequency of the TPS549B22 device is 650 kHz. There are a total of 8 switching frequency

settings that can be programmed via PMBus interface. For each switching frequency setting, there are 4 internal

ramp compensations (DCAP3) to choose from, also via PMBus. When DCAP3 mode is selected (preferred), the

internal ramp compensation is used for stabilizing the converter design. The ramp is a function of the switching

frequency and duty cycle range (the output voltage to input voltage ratio). Table 39 summarizes the ramp

choices using these functions.

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Table 39. Switching Frequency Selection

V_OUTRANGE

(FIXED V_IN= 12 V)

DUTY CYCLE RANGE

SWITCHING FREQUENCY

SETTING

RAMP

SELECT

OPTION

TIME

CONSTANT

t (µs)

(V_OUT/V_IN) (%)

(f_SW) (kHz)

MIN

0.6

0.9

1.5

2.5

0.6

0.9

1.5

2.5

0.6

0.9

1.5

2.5

0.6

0.9

1.5

2.5

MAX

0.9

1.5

2.5

5.5

0.9

1.5

2.5

5.5

0.9

1.5

2.5

5.5

0.9

1.5

2.5

5.5

MIN

5

MAX

7.5

R/2

9

R × 1

R × 2

R × 3

R/2

16.8

32.3

55.6

7

7.5

12.5

>21

5

12.5

21

315,

425

7.5

12.5

21

R × 1

R × 2

R × 3

R/2

13.5

25.9

44.5

5.6

7.5

12.5

>21

5

550,

650

7.5

12.5

21

R × 1

R × 2

R × 3

R/2

10.4

20

7.5

12.5

>21

5

825,

900

34.4

3.8

7.5

12.5

21

R × 1

R × 2

R × 3

7.1

7.5

12.5

>21

1.025,

1.225 MHz

13.6

23.3

8.2.3.3 Inductor Selection

To calculate the value of the output inductor, use Equation 3. The coefficient K_INDrepresents the amount of

inductor ripple current relative to the maximum output current. The output capacitor filters the inductor ripple

current. Therefore, choosing a high inductor ripple current impacts the selection of the output capacitor since the

output capacitor must have a ripple current rating equal to or greater than the inductor ripple current. In general,

maintain a K_INDcoefficient between 0 and 40 for balanced performance. Using this target ripple current, the

required inductor size can be calculated as shown in Equation 3

1V ì 18 V -1V

V_OUT

ìf_SW

V - V_OUT

(

)

IN

ìK_IND

OUT max

L1=

ì

=

= 0.29 mH

18 V ì650 kHzì25 A ì0.2

(

)

V

I

(

)

IN max

(

)

(

)

(3)

Selecting a K_INDof 0.2, the target inductance L₁= 290 nH. Using the next standard value, the 330 nH is chosen

in this application for its high current rating, low DCR, and small size. The inductor ripple current, RMS current,

and peak current can be calculated using Equation 4, Equation 5 and Equation 6. Use these values to select an

inductor with approximately the target inductance value, and current ratings that allow normal operation with

some margin.

V

- V_OUT

1V ì 18 V -1V

V_OUT

ì f_SW

(

)

IN max

(

)

I_RIPPLE

=

ì

=

= 4.4 A

L1

18 V ì 650 kHzì330 nH

V

(

)

IN max

(

)

(4)

1

2

I_{L rms}

=

I

+

ì I

= 25 A

(

)

(

)

OUT

RIPPLE

(

)

12

(5)

(6)

1

2

I_{L peak}= I

+

ì I

(

= 27.2 A

(

)

OUT

RIPPLE

(

)

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8.2.3.4 Output Capacitor Selection

There are three primary considerations for selecting the value of the output capacitor. The output capacitor

affects three criteria:

•

Stability

Regulator response to a change in load current or load transient

Output voltage ripple

These three considerations are important when designing regulators that must operate where the electrical

conditions are unpredictable. The output capacitance needs to be selected based on the most stringent of these

three criteria.

8.2.3.4.1 Minimum Output Capacitance to Ensure Stability

To prevent sub-harmonic multiple pulsing behavior, TPS549B22 application designs must strictly follow the small

signal stability considerations described in Equation 7.

t

V_REF

8t

C_{OUT min}

>

^ONì

ì

(

)

2

L_OUTV_OUT

where

•

C_OUT(min)is the minimum output capacitance needed to meet the stability requirement of the design

t_ONis the on-time information based on the switching frequency and duty cycle (in this design, 128 ns)

τ is the ramp compensation time constant of the design based on the switching frequency and duty cycle, (in

this design, 25.9 µs, refer to Table 39)

•

L_OUTis the output inductance (in the design, 0.33 µH)

V_REFis the user-selected reference voltage level (in this design, 1 V)

V_OUTis the output voltage (in this design, 1 V)

(7)

The minimum output capacitance calculated from Equation 7 is 40 µF. The stability is ensured when the amount

of the output capacitance is 40 µF or greater. And when all MLCCs (multi-layer ceramic capacitors) are used,

both DC- and AC-derating effects must be considered to ensure that the minimum output capacitance

requirement is met with sufficient margin.

8.2.3.4.2 Response to a Load Transient

The output capacitance must supply the load with the required current when current is not immediately provided

by the regulator. When the output capacitor supplies load current, the impedance of the capacitor greatly affects

the magnitude of voltage deviation (such as undershoot and overshoot) during the transient.

Use Equation 8 and Equation 9 to estimate the amount of capacitance needed for a given dynamic load step and

release.

NOTE

There are other factors that can impact the amount of output capacitance for a specific

design, such as ripple and stability.

≈

∆

«

’

÷

◊

2

V_OUTì t_SW

L_OUTì DI

ì

+ t_{OFF min}

(

)

LOAD max

(

)

(

)

∆

÷

V

IN min

(

)

C_{OUT min_under}

=

(

)

≈

∆

’

≈

∆

’

V

- V_OUT

IN min

(

)

÷

ì t_SW- t_{OFF min}ì V_OUT

÷

2ì DV_{LOAD insert}₎ì

(

)

∆

«

÷

◊

∆

«

V

÷

IN min

(

)

◊

(8)

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2

L_OUTì DI

(

)

LOAD max

(

)

C_{OUT min_ over}

=

(

)

2ì DV_{LOAD release}ì V_OUT

(

)

where

•

C_{OUT(min_under)}is the minimum output capacitance to meet the undershoot requirement

C_{OUT(min_over)}is the minimum output capacitance to meet the overshoot requirement

L is the output inductance value (0.33 µH)

∆I_LOAD(max)is the maximum transient step (15 A)

V_OUTis the output voltage value (1 V)

t_SWis the switching period (1.54 µs)

V_IN(min)is the minimum input voltage for the design (10.8 V)

t_OFF(min)is the minimum off time of the device (300 ns)

∆V_LOAD(insert)is the undershoot requirement (30 mV)

∆V_{LOAD(release)}is the overshoot requirement (30 mV)

(9)

Most of the above parameters can be found in Table 38.

The minimum output capacitance to meet the undershoot requirement is 516 µF. The minimum output

capacitance to meet the overshoot requirement is 1238 µF. This example uses a combination of POSCAP and

MLCC capacitors to meet the overshoot requirement.

•

POSCAP bank 1: 2 x 470 µF, 2.5 V, 6 mΩ per capacitor

MLCC bank 2: 7 × 100 µF, 2.5 V, 1 mΩ per capacitor with DC+AC derating factor of 60%

Recalculating the worst case overshoot using the described capacitor bank design, the overshoot is 29.0 mV

which meets the 30-mV overshoot specification requirement.

8.2.3.4.3 Output Voltage Ripple

The output voltage ripple is another important design consideration. Equation 10 calculates the minimum output

capacitance required to meet the output voltage ripple specification. This criterion is the requirement when the

impedance of the output capacitance is dominated by ESR.

I_RIPPLE

C_{OUT min RIPPLE}

=

= 82 mF

(

)

8ì f_SWì V_{OUT ripple}

(

)

(10)

In this case, the maximum output voltage ripple is 10 mV. For this requirement, the minimum capacitance for

ripple requirement yields 82 µF. Because this capacitance value is significantly lower compared to that of

transient requirement, determine the capacitance bank from steps in the previous section Response to a Load

Transient. Because the output capacitor bank consists of both POSCAP and MLCC type capacitors, it is

important to consider the ripple effect at the switching frequency due to effective ESR. Use Equation 11 to

determine the maximum ESR of the output capacitor bank for the switching frequency.

I_RIPPLE

V_{OUT ripple}

-

(

)

8ì f_SWìC_OUT

ESR_MAX

=

= 2.2 mW

I_RIPPLE

(11)

Estimate the effective ESR at the switching frequency by obtaining the impedance vs frequency characteristics of

the output capacitors. The parallel impedance of capacitor bank 1 and capacitor bank 2 at the switching

frequency of the design example is estimated to be 1.2 mΩ, which is less than that of the maximum ESR value.

Therefore, the output voltage ripple requirement (10 mV) can be met. For detailed calculation on the effective

ESR please contact the factory to obtain a user-friendly Excel based design tool.

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8.2.3.5 Input Capacitor Selection

The TPS549B22 devices require a high-quality, ceramic, type X5R or X7R, input decoupling capacitor with a

value of at least 1 μF of effective capacitance on the VDD pin, relative to AGND. The power stage input

decoupling capacitance (effective capacitance at the PVIN and PGND pins) must be sufficient to supply the high

switching currents demanded when the high-side MOSFET switches on, while providing minimal input voltage

ripple as a result. This effective capacitance includes any DC bias effects. The voltage rating of the input

capacitor must be greater than the maximum input voltage. The capacitor must also have a ripple current rating

greater than the maximum input current ripple to the device during full load. The input ripple current can be

calculated using Equation 12.

V

- V_OUT

(

)

IN min

V_OUT

(

)

I_{CIN rms}= I_{OUT max}₎ì

ì

= 10 Arms

(

)

(

V

IN min

(

)

(

)

(12)

The minimum input capacitance and ESR values for a given input voltage ripple specification, V_IN(ripple), are

shown in Equation 13 and Equation 14. The input ripple is composed of a capacitive portion, V_RIPPLE(cap), and a

resistive portion, V_RIPPLE(esr)

.

I_{OUT max}ì V_OUT

(

)

C_{IN min}

=

= 21.4 mF

(

)

V_{RIPPLE cap}ì V

₎ì f_SW

IN max

(

)

(13)

V_{RIPPLE ESR}

(

)

ESR_{CIN max}

=

= 3.4 mW

(

)

I

≈

’

RIPPLE

I_{OUT max}

+

∆

«

÷

◊

(

)

2

(14)

The value of a ceramic capacitor varies significantly over temperature and the amount of DC bias applied to the

capacitor. The capacitance variations due to temperature can be minimized by selecting a dielectric material that

is stable over temperature. X5R and X7R ceramic dielectrics are usually selected for power regulator capacitors

because they have a high capacitance to volume ratio and are fairly stable over temperature. The input capacitor

must also be selected with the DC bias taken into account. For this example design, a ceramic capacitor with at

least a 25-V voltage rating is required to support the maximum input voltage. For this design, allow 0.1-V input

ripple for V_RIPPLE(cap), and 0.1-V input ripple for V_RIPPLE(esr). Using Equation 13 and Equation 14, the minimum

input capacitance for this design is 21.4 µF, and the maximum ESR is 3.4 mΩ. For this example, four 22-μF, 25-

V ceramic capacitors and one additional 100-μF, 25-V low-ESR polymer capacitors in parallel were selected for

the power stage.

8.2.3.6 Bootstrap Capacitor Selection

A ceramic capacitor with a value of 0.1 μF must be connected between the BOOT and SW pins for proper

operation. TI recommends using a ceramic capacitor with X5R or better grade dielectric. Use a capacitor with a

voltage rating of 25 V or higher.

8.2.3.7 BP Pin

Bypass the BP pin to DRGND with 4.7 µF of capacitance. In order for the regulator to function properly, it is

important that these capacitors be localized to the TPS549B22 , with low-impedance return paths. See Layout

Guidelines for more information.

8.2.3.8 R-C Snubber and VIN Pin High-Frequency Bypass

Though it is possible to operate the TPS549B22 within absolute maximum ratings without ringing reduction

techniques, some designs may require external components to further reduce ringing levels. This example uses

two approaches: a high frequency power stage bypass capacitor on the VIN pins, and an R-C snubber between

the SW area and GND.

The high-frequency VIN bypass capacitor is a lossless ringing reduction technique which helps minimizes the

outboard parasitic inductances in the power stage, which store energy during the low-side MOSFET on-time, and

discharge once the high-side MOSFET is turned on. For this example two 2.2-nF, 25-V, 0603-sized high-

frequency capacitors are used. The placement of these capacitors is critical to its effectiveness. Their ideal

placement is shown in Figure 53.

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Additionally, an R-C snubber circuit is added to this example. To balance efficiency and spike levels, a 1-nF

capacitor and a 1-Ω resistor are chosen. In this example a 0805-sized resistor is chosen, which is rated for 0.125

W, nearly twice the estimated power dissipation. See Snubber Circuits: Theory, Design and Application for more

information about snubber circuits.

8.2.3.9 Optimize Reference Voltage (VSEL)

Optimize the reference voltage by choosing a value for R_VSEL. The TPS549B22 device is designed with a wide

range of precision reference voltage support from 0.6 V to 1.2 V with an available step change of 50 mV.

Program these reference voltages using the VSEL pin-strap configurations. See Table 2 for internal reference

voltage selections. In addition to providing initial boot voltage value, use the VSEL pin to program hiccup and

latch-off mode.

There are two ways to program the output voltage set point. If the output voltage set point is one of the 16

available reference and boot voltage options, no feedback resistors are required for output voltage programming.

In the case where feedback resistors are not needed, connect the RSP pin to the positive sensing point of the

load. Always connect the RSN pin to the load return sensing point.

In this design example, since the output voltage set point is 1 V, select R_VSEL(LS)of either 75 kΩ (latch off) or 68.1

kΩ (hiccup) as shown in Table 3. If the output voltage set point is NOT one of the 16 available reference or boot

voltage options, feedback resistors are required for output voltage programming. Connect the RSP pin to the

mid-point of the resistor divider. Always connect the RSN pin to the load return sensing point as shown in Figure

23 and Figure 24.

The general guideline to select boot and internal reference voltage is to select the reference voltage closest to

the output voltage set point. In addition, because the RSP and RSN pins are extremely high-impedance input

terminals of the true differential remote sense amplifier, use a feedback resistor divider with values much less

than 100 kΩ.

8.2.3.10 MODE Pin Selection

MODE pin strap configuration is used to program control topology and internal soft-start timing selections.

TPS549B22 supports both DCAP3 and DCAP operation. For general POL applications, TI strongly recommends

configuring the control topology to be DCAP3 due to its simple to use and no external compensation features. In

the rare instance where DCAP is needed, an RCC network across the output inductor is needed to generate

sufficient ripple voltage on the RSP pin. In this design example, R_MODE(LS)of 42.2 kΩ is selected for DCAP3 and

soft start time of 1 ms.

8.2.3.11 ADDR Pin Selection

ADDR pin strap configuration is used to program device address and light load conduction mode selection. The

TPS549B22 allows up to 16 different chip addresses for PMBus communication with the first 3 bits fixed as 001.

The address selection process is defined by resistor divider ratio from BP pin to ADDR pin, and the address

detection circuit will start to work only after the initial power up when V_DDhas risen above its UVLO threshold.

For this application example, a device address of 16d is desired. We select the low side RADDR to be 0 Ω

considering the SKIP operation and device address of 16d. Table 4 lists all combinations of the address

selections. The 1% or better tolerance resistors with typical temperature coefficient of ±100 ppm/°C are

recommended

8.2.3.12 Overcurrent Limit Design

The TPS549B22 device uses the ILIM pin to set the OCP level. Connect the ILIM pin to GND through the voltage

setting resistor, R_ILIM. In order to provide both good accuracy and cost effective solution, this device supports

temperature compensated MOSFET on-resistance (R_DS(on)) sensing. Also, this device performs both positive and

negative inductor current limiting with the same magnitudes. Positive current limit is normally used to protect the

inductor from saturation therefore causing damage to the high-side and low-side FETs. Negative current limit is

used to protect the low-side FET during OVP discharge.

The inductor current is monitored by the voltage between PGND pin and SW pin during the OFF time. The ILIM

pin has 1200 ppm/°C temperature slope to compensate the temperature dependency of the on-resistance. The

PGND pin is used as the positive current sensing node.

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TPS549B22 has cycle-by-cycle over-current limiting control. The inductor current is monitored during the OFF

state and the controller maintains the OFF state during the period that the inductor current is larger than the

overcurrent ILIM level. The voltage on the ILIM pin (V_ILIM) sets the valley level of the inductor current. The range

of value of the R_ILIMresistor is between 9.53 kΩ and 105 kΩ. The range of valley OCL is between 5 A and 50 A

(typical). If the R_ILIMresistance is outside of the recommended range, OCL accuracy and function cannot be

ensured. (see Table 40)

Table 40. Closed Loop EVM Measurement of OCP Settings

1% R_ILIM

(kΩ)

OVERCURRENT PROTECTION VALLEY (A)

82.1

71.5

61.9

51.1

40.2

30.1

20.5

40

35

30

25

20

15

10

Use Equation 15 to relate the valley OCL to the R_ILIMresistance.

R_ILIM= 2.0664 × OCL_VALLEY– 0.6036

where

•

R_ILIMis in kΩ

OCL_VALLEYis in A

(15)

In this design example, the desired valley OCL is 43 A, the calculated R_ILIMis 61.9 kΩ. Use Equation 16 to

calculate the DC OCL to be 32.1 A.

OCL_DC= OCL_VALLEY+ 0.5ìI_RIPPLE

where

•

R_ILIMis in kΩ

OCL_DCis in A

(16)

In an overcurrent condition, the current to the load exceeds the inductor current and the output voltage falls.

When the output voltage crosses the under-voltage fault threshold for at least 1 ms, the behavior of the device

depends on the VSEL pin strap setting. If hiccup mode is selected, the device restarts after a 16-ms delay (1-ms

soft-start option). If the overcurrent condition persists, the OC hiccup behavior repeats. During latch-off mode

operation the device shuts down until the EN pin is toggled or VDD pin is power cycled.

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Figure 54. VOUT Command Graphic User Interface

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8.2.4 Application Curves

1.01

1.005

1

0.995

0.99

V_IN= 5 V

V_IN= 12 V

V_IN= 14 V

V_IN= 18 V

0

5

10

15

20

SKIP Mode

25

Output Current (A)

D009

f_SW= 650 kHz

FCCM mode

V_DD= V_IN= 5 V

V_OUT= 1 V

V_DD= V_IN

f_SW= 650 kHz

5-A DC with 15-A

step at 40A/µs

V_OUT= 1 V

Figure 55. Output Voltage Regulation vs. Output Current

Figure 56. Transient Response Peak-to-Peak

V_IN= 12 V

I_OUT= 0 A

V_OUT= 0.6 V to 1.2 V

V_IN= 12 V

I_OUT= 0 A

V_OUT= 1.2 V to 0.6 V

Figure 57. VOUT Command

Figure 58. VOUT Command

V_IN= 12 V

I_OUT= 40 A

V_OUT= 0.6 V to 1.2 V

V_IN= 12 V

I_OUT= 40 A

V_OUT= 1.2 V to 0.6 V

Figure 59. VOUT Command

Figure 60. VOUT Command

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9 Power Supply Recommendations

This device is designed to operate from an input voltage supply between 1.5 V and 18 V. Ensure the supply is

well regulated. Proper bypassing of input supplies and internal regulators is also critical for noise performance,

as is the quality of the PCB layout and grounding scheme. See the recommendations in the Layout section.

10 Layout

10.1 Layout Guidelines

Consider these layout guidelines before starting a layout work using TPS549B22.

•

It is absolutely critical that all GND pins, including AGND (pin 30), DRGND (pin 29), and PGND (pins 13, 14,

15, 16, 17, 18, 19, and 20) are connected directly to the thermal pad underneath the device via traces or

plane.

Include as many thermal vias as possible to support a 25-A thermal operation. For example, a total of 35

thermal vias are used (outer diameter of 20 mil) in the TPS49B22EVM-847, which is available for purchase at

www.ti.com.

Placed the power components (including input/output capacitors, output inductor and TPS549B22 device) on

one side of the PCB (solder side). Insert at least two inner layers (or planes) connected to the power ground,

in order to shield and isolate the small signal traces from noisy power lines.

Place the VIN pin decoupling capacitors as close as possible to the PVIN and PGND pins to minimize the

input AC current loop. Place a high-frequency decoupling capacitor (with a value between 1 nF and 0.1 µF)

as close to the PVIN pin and PGND pin as the spacing rule allows. This placement helps suppress the switch

node ringing.

•

Place VDD and BP decoupling capacitors as close as possible to the device pins. Do not use PVIN plane

connection for the VDD pin. Separate the VDD signal from the PVIN signal by using separate trace

connections. Provide GND vias for each decoupling capacitor and make the loop as small as possible.

Ensure that the PCB trace defined as switch node (which connects the SW pins and up-stream of the output

inductor) are as short and wide as possible. In the TPS49B22EVM-847 design, the SW trace width is 200 mil.

Use a separate via or trace to connect SW node to snubber and bootstrap capacitor. Do not combine these

connections.

•

Place all sensitive analog traces and components (including VOSNS, RSP, RSN, ILIM, MODE, VSEL and

ADDR) far away from any high voltage switch node (itself and others), such as SW and BOOT to avoid noise

coupling. In addition, place MODE, VSEL and ADDR programming resistors near the device pins.

The RSP and RSN pins operate as inputs to a differential remote sense amplifier that operates with very high

impedance. It is essential to route the RSP and RSN pins as a pair of diff-traces in Kelvin-sense fashion.

Route them directly to either the load sense points (+ and –) or the output bulk capacitors. The internal circuit

uses the VOSNS pin for on-time adjustment. It is critical to tie the VOSNS pin directly tied to VOUT (load

sense point) for accurate output voltage result.

•

Pins 6, 7, and 26 are not connected in the 25-A TPS549B22 device, while pins 6, and 7 connect to SW and

pins 26 connects to PVIN in the 40-A TPS549D22 device.

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10.2 Layout Examples

图 61. EVM Top View

图 62. EVM Top Layer

图 63. EVM Inner Layer 1

图 64. EVM Inner Layer 2

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Layout Examples (接下页)

图 65. EVM Inner Layer 3

图 66. EVM Inner Layer 4

图 67. EVM Bottom Layer

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10.3 Mounting and Thermal Profile Recommendation

Proper mounting technique adequately covers the exposed thermal tab with solder. Excessive heat during the

reflow process can affect electrical performance. 图 68 shows the recommended reflow oven thermal profile.

Proper post-assembly cleaning is also critical to device performance. See

QFN/SON PCB Attachment for more information.

t_P

T_P

T_L

T_S(max)

T_S(min)

t_L

r_RAMP(up)

r_RAMP(down)

t_S

t_25P

Time (s)

25

图 68. Recommended Reflow Oven Thermal Profile

表 41. Recommended Thermal Profile Parameters

PARAMETER

MIN

TYP

MAX

UNIT

RAMP UP AND RAMP DOWN

r_RAMP(up)

Average ramp-up rate, T_S(max)to T_P

Average ramp-down rate, T_Pto T_S(max)

3

6

°C/s

r_RAMP(down)

PRE-HEAT

T_S

Pre-heat temperature

150

60

200

180

°C

s

t_S

Pre-heat time, T_S(min)to T_S(max)

REFLOW

T_L

T_P

t_L

Liquids temperature

217

°C

s

Peak temperature

260

150

40

Time maintained above liquidus temperature, T_L

Time maintained within 5°C of peak temperature, T_P

Total time from 25°C to peak temperature, T_P

60

20

t_P

s

t_25P

480

s

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11 器件和文档支持

11.1 器件支持

11.1.1 开发支持

11.1.1.1 使用 WEBENCH® 工具创建定制设计

单击此处，使用 TPS549B22 器件并借助 WEBENCH® 电源设计器创建定制设计方案。

1. 在开始阶段键入输出电压 (V_IN)、输出电压 (V_OUT) 和输出电流 (I_OUT) 要求。

2. 使用优化器拨盘优化关键设计参数，如效率、封装和成本。

3. 将生成的设计与德州仪器 (TI) 的其他解决方案进行比较。

WEBENCH Power Designer 提供一份定制原理图以及罗列实时价格和组件可用性的物料清单。

在多数情况下，可执行以下操作：

•

运行电气仿真，观察重要波形以及电路性能

运行热性能仿真，了解电路板热性能

将定制原理图和布局方案导出至常用 CAD 格式

打印设计方案的 PDF 报告并与同事共享

有关 WEBENCH 工具的详细信息，请访问 www.ti.com/WEBENCH。

11.2 文档支持

11.2.1 相关文档

请参阅如下相关文档：

《阻尼器电路：理论、设计和应用》

11.3 接收文档更新通知

要接收文档更新通知，请导航至 TI.com 上的器件产品文件夹。请单击右上角的通知我进行注册，即可收到所有的

产品更改信息每周摘要。有关更改的详细信息，请查看任何已修订文档中包含的修订历史记录。

11.4 社区资源

下列链接提供到 TI 社区资源的连接。链接的内容由各个分销商“按照原样”提供。这些内容并不构成 TI 技术规范，

并且不一定反映 TI 的观点；请参阅 TI 的《使用条款》。

TI E2E™ 在线社区 TI 的工程师对工程师 (E2E) 社区。此社区的创建目的在于促进工程师之间的协作。在

e2e.ti.com 中，您可以咨询问题、分享知识、拓展思路并与同行工程师一道帮助解决问题。

设计支持

TI 参考设计支持可帮助您快速查找有帮助的 E2E 论坛、设计支持工具以及技术支持的联系信息。

11.5 商标

D-CAP3, Eco-mode, NexFET, E2E are trademarks of Texas Instruments.

WEBENCH is a registered trademark of Texas Instruments.

PMBus is a trademark of SMIF, Inc..

All other trademarks are the property of their respective owners.

11.6 静电放电警告

ESD 可能会损坏该集成电路。德州仪器 (TI) 建议通过适当的预防措施处理所有集成电路。如果不遵守正确的处理措施和安装程序 , 可

能会损坏集成电路。

ESD 的损坏小至导致微小的性能降级 , 大至整个器件故障。精密的集成电路可能更容易受到损坏 , 这是因为非常细微的参数更改都可

能会导致器件与其发布的规格不相符。

11.7 Glossary

SLYZ022 — TI Glossary.

This glossary lists and explains terms, acronyms, and definitions.

58

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12 机械、封装和可订购信息

以下页面包含机械、封装和可订购信息。这些信息是指定器件的最新可用数据。这些数据如有变更，恕不另行通知

和修订此文档。如欲获取此数据表的浏览器版本，请参阅左侧的导航。

59

PACKAGE OUTLINE

RVF0040A

LQFN-CLIP - 1.52 mm max height

S

C

A

L

E

2

.

0

PLASTIC QUAD FLATPACK - NO LEAD

5.1

4.9

A

B

PIN 1 INDEX AREA

7.1

6.9

C

1.52

1.32

SEATING PLANE

0.08 C

0.05

0.00

2X 3.5

(0.2) TYP

3.3 0.1

EXPOSED

THERMAL PAD

36X 0.5

13

20

12

21

41

SYMM

2X

5.3 0.1

5.5

32

1

0.3

40X

0.2

40

33

PIN 1 ID

(OPTIONAL)

0.1

C A B

SYMM

0.05

0.5

0.3

40X

4222989/B 10/2017

NOTES:

1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing

per ASME Y14.5M.

2. This drawing is subject to change without notice.

3. The package thermal pad must be soldered to the printed circuit board for thermal and mechanical performance.

4. Reference JEDEC registration MO-220.

www.ti.com

EXAMPLE BOARD LAYOUT

RVF0040A

LQFN-CLIP - 1.52 mm max height

PLASTIC QUAD FLATPACK - NO LEAD

(3.3)

6X (1.4)

40

33

40X (0.6)

1

32

40X (0.25)

2X

(1.12)

36X (0.5)

6X

(1.28)

(6.8)

(5.3)

41

SYMM

(R0.05) TYP

(

0.2) TYP

VIA

12

21

13

20

SYMM

(4.8)

LAND PATTERN EXAMPLE

SCALE:12X

0.07 MAX

ALL AROUND

0.07 MIN

ALL AROUND

SOLDER MASK

OPENING

METAL

SOLDER MASK

OPENING

METAL UNDER

SOLDER MASK

NON SOLDER MASK

DEFINED

SOLDER MASK

DEFINED

(PREFERRED)

SOLDER MASK DETAILS

4222989/B 10/2017

NOTES: (continued)

5. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature

number SLUA271 (www.ti.com/lit/slua271).

www.ti.com

EXAMPLE STENCIL DESIGN

RVF0040A

LQFN-CLIP - 1.52 mm max height

PLASTIC QUAD FLATPACK - NO LEAD

SYMM

(0.815) TYP

40

33

40X (0.6)

1

41

32

40X (0.25)

(1.28)

TYP

36X (0.5)

(0.64)

TYP

SYMM

(6.8)

(R0.05) TYP

8X

(1.08)

12

21

METAL

TYP

20

13

8X (1.43)

(4.8)

SOLDER PASTE EXAMPLE

BASED ON 0.125 mm THICK STENCIL

EXPOSED PAD

71% PRINTED SOLDER COVERAGE BY AREA

SCALE:18X

4222989/B 10/2017

NOTES: (continued)

6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate

design recommendations.

www.ti.com

重要声明和免责声明

TI“按原样”提供技术和可靠性数据（包括数据表）、设计资源（包括参考设计）、应用或其他设计建议、网络工具、安全信息和其他资源，

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本、损失和债务，TI 对此概不负责。

TI 提供的产品受 TI 的销售条款或 ti.com 上其他适用条款/TI 产品随附的其他适用条款的约束。TI 提供这些资源并不会扩展或以其他方式更改

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TI 反对并拒绝您可能提出的任何其他或不同的条款。IMPORTANT NOTICE

邮寄地址：Texas Instruments, Post Office Box 655303, Dallas, Texas 75265


型号：	TPS549B22RVFR
厂家：	TEXAS INSTRUMENTS
描述：	具有差分遥感功能和 PMBus 的 1.5V 至 18V、25A 同步 SWIFT™ 降压转换器 \| RVF \| 40 \| -40 to 125 转换器
文件：	总68页 (文件大小：5571K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

TPS549B22RVFR [TI]

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