TPS54614QPWPRQ1_技术文档

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Typical Size

6,6 mm X 9,8 mm

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SGLS266D − OCTOBER 2004 − REVISED DECEMBER 2004

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

FEATURES

DESCRIPTION

(1)

D

Qualification in Accordance With AEC-Q100

Qualified for Automotive Applications

Customer-Specific Configuration Control Can

Be Supported Along With Major-Change

Approval

The SWIFT family of dc/dc regulators, the TPS54611,

TPS54612, TPS54613, TPS54614, TPS54615, and

TPS54616 low-input voltage high-output current

synchronous-buck PWM converters integrate all required

active components. Included on the substrate are true,

high-performance, voltage error amplifiers that provide

high performance under transient conditions; an

under-voltage-lockout circuit to prevent start-up until the

input voltage reaches 3 V; an internally and externally set

slow-start circuit to limit in-rush currents; and a power good

output useful for processor/logic reset, fault signaling, and

supply sequencing.

D

30-mΩ, 12-A Peak MOSFET Switches for High

Efficiency at 6-A Continuous Output Source

and Sink

0.9-V, 1.2-V, 1.5-V, 1.8-V, 2.5-V, and 3.3-V Fixed

Output Voltage Devices With 1% Initial

Accuracy

Internally Compensated for Easy Use and

Minimal Component Count

The TPS54611−6 devices are available in a thermally

enhanced 28-pin TSSOP (PWP) PowerPAD package,

which eliminates bulky heatsinks. Texas Instruments

provides evaluation modules and the SWIFT designer

software tool to aid in quickly achieving high-performance

power supply designs to meet aggressive equipment

development cycles.

D

Fast Transient Response

Wide PWM Frequency − Fixed 350 kHz,

550 kHz or Adjustable 280 kHz to 700 kHz

D

Load Protected by Peak Current Limit and

Thermal Shutdown

D

Integrated Solution Reduces Board Area and

Total Cost

Contact Texas Instruments for details. Q100 qualification data

availableon request.

(1)

APPLICATIONS

D

Low-Voltage, High-Density Systems With

Power Distributed at 5 V or 3.3 V

Point of Load Regulation for High

Performance DSPs, FPGAs, ASICs and

Microprocessors

D

Broadband, Networking and Optical

Communications Infrastructure

Portable Computing/Notebook PCs

These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during

storage or handling to prevent electrostatic damage to the MOS gates.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments

semiconductor products and disclaimers thereto appears at the end of this data sheet.

PowerPAD and SWIFT are trademarks of Texas Instruments.

ꢁꢕ ꢍ ꢜꢐ ꢓ ꢀꢎ ꢍꢏ ꢜ ꢑꢀꢑ ꢡꢢ ꢣꢤ ꢥ ꢦꢧ ꢨꢡꢤꢢ ꢡꢞ ꢩꢪ ꢥ ꢥ ꢫꢢꢨ ꢧꢞ ꢤꢣ ꢬꢪꢭ ꢮꢡꢩ ꢧꢨꢡ ꢤꢢ ꢯꢧ ꢨꢫꢰ ꢁꢥ ꢤꢯꢪ ꢩꢨꢞ

ꢩ ꢤꢢ ꢣꢤꢥ ꢦ ꢨꢤ ꢞ ꢬꢫ ꢩ ꢡ ꢣꢡ ꢩ ꢧ ꢨꢡ ꢤꢢꢞ ꢬ ꢫꢥ ꢨꢱꢫ ꢨꢫ ꢥ ꢦꢞ ꢤꢣ ꢀꢫꢲ ꢧꢞ ꢎꢢꢞ ꢨꢥ ꢪꢦ ꢫꢢꢨ ꢞ ꢞꢨ ꢧꢢꢯ ꢧꢥ ꢯ ꢳ ꢧꢥ ꢥ ꢧ ꢢꢨꢴꢰ

ꢁꢥ ꢤ ꢯꢪꢩ ꢨ ꢡꢤ ꢢ ꢬꢥ ꢤ ꢩ ꢫ ꢞ ꢞ ꢡꢢ ꢵ ꢯꢤ ꢫ ꢞ ꢢꢤꢨ ꢢꢫ ꢩꢫ ꢞꢞ ꢧꢥ ꢡꢮ ꢴ ꢡꢢꢩ ꢮꢪꢯ ꢫ ꢨꢫ ꢞꢨꢡ ꢢꢵ ꢤꢣ ꢧꢮ ꢮ ꢬꢧ ꢥ ꢧꢦ ꢫꢨꢫ ꢥ ꢞꢰ

Copyright  2001−2004, Texas Instruments Incorporated

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SGLS266D − OCTOBER 2004 − REVISED DECEMBER 2004

EFFICIENCY AT 350 kHz

100

95

90

85

80

SIMPLIFIED SCHEMATIC

Input

Output

VIN

PH

TPS54614

BOOT

75

70

65

PGND

VSENSE

VBIAS

AGND

60

55

50

0

1

2

3

4

5

6

Load Current − A

PWP PACKAGE

(TOP VIEW)

1

28

AGND

VSENSE

NC

PWRGD

BOOT

PH

RT

FSEL

SS/ENA

VBIAS

VIN

PGND

2

27

26

25

24

23

22

21

20

19

18

17

16

15

3

4

5

6

7

PH

THERMAL

PAD

8

9

10

11

12

13

14

AVAILABLE OPTIONS

PACKAGED DEVICES

PLASTIC HTSSOP

PACKAGED DEVICES

PLASTIC HTSSOP

OUTPUT

VOLTAGE

OUTPUT

VOLTAGE

T

J

T

J

)(1)

(PWP

0.9 V

1.2 V

1.5 V

TPS54611QPWPRQ1

1.8 V

2.5 V

3.3 V

TPS54614QPWPRQ1

TPS54615QPWPRQ1

TPS54616QPWPRQ1

(2)

TPS54612QPWPRQ1

−40°C to 125°C

TPS54613QPWPRQ1

(1)

(2)

The PWP package is taped and reeled as denoted by the R suffix on the device type (i.e., TPS54616QPWPRQ1).

See application section of data sheet for PowerPAD drawing and layout information.

Product Preview

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TERMINAL

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SGLS266D − OCTOBER 2004 − REVISED DECEMBER 2004

Terminal Functions

DESCRIPTION

NAME

AGND

NO.

1

5

Analog ground. Return for slow-start capacitor, VBIAS capacitor, RT resistor FSEL. Make PowerPAD connection to AGND.

BOOT

Bootstrap input. A 0.022-µF to 0.1-µF low-ESR capacitor connected from BOOT to PH generates a floating drive for the

high-set FET driver.

NC

3

No connection

PGND

15−19 Power ground. High current return for the low-side driver and power MOSFET. Connect PGND with large copper areas to

the input and output supply returns and negative terminals of the input and output capacitors.

PH

6−14 Phase input/output. Junction of the internal high-side and low-side power MOSFETs, and output inductor.

PWRGD

4

Power good open drain output. High-Z when VSENSE ≥ 90% V , otherwise PWRGD is low. Note that output is low when

SS/ENA is low or internal shutdown signal active.

ref

RT

28

26

Frequency setting resistor input. Connect a resistor from RT to AGND to set the switching frequency.

SS/ENA

Slow-start/enable input/output. Dual function pin which provides logic input to enable/disable device operation and

capacitor input to externally set the start-up time.

FSEL

27

25

Frequency select input. Provides logic input to select between two internally set switching frequencies.

VBIAS

Internal bias regulator output. Supplies regulated voltage to internal circuitry. Bypass VBIAS pin to AGND pin with a high

quality, low-ESR 0.1-µF to 1-µF ceramic capacitor.

20−24 Input supply for the power MOSFET switches and internal bias regulator. Bypass VIN pins to PGND pins close to device

VIN

package with a high quality, low-ESR 1-µF to 10-µF ceramic capacitor.

VSENSE

2

Error amplifier inverting input. Connect directly to output voltage sense point.

ABSOLUTE MAXIMUM RATINGS

over operating free-air temperature range unless otherwise noted

(1)

VIN, SS/ENA, FSEL

RT

−0.3 V to 7 V

−0.3 V to 6 V

−0.3 V to 4 V

−0.3 V to 17 V

−0.3 V to 7 V

−0.6 V to 10 V

Internally Limited

6 mA

V

Input voltage range

I

VSENSE

BOOT

VBIAS, PWRGD

PH

V

O

Output voltage range

Source current

Sink current

PH

I

O

VBIAS

PH

12 A

S

SS/ENA, PWRGD

AGND to PGND

10 mA

Voltage differential

0.3 V

Continuous power dissipation

See Power Dissipation Rating Table

−40°C to 150°C

−65°C to 150°C

300°C

T

Operating virtual junction temperature range

Storage temperature

J

T

stg

Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds

(1)

Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and

functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not

implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

3

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SGLS266D − OCTOBER 2004 − REVISED DECEMBER 2004

DISSIPATION RATINGS⁽¹⁾⁽²⁾

THERMAL IMPEDANCE

JUNCTION-TO-AMBIENT

T

= 25°C

T

= 70°C

T = 85°C

A

PACKAGE

POWER RATING POWER RATING POWER RATING

(3)

28 Pin PWP with solder

18.2°C/W

5.49 W

3.02 W

1.36 W

2.2 W

28 Pin PWP without solder

40.5°C/W

2.48 W

0.99 W

(1)

(2)

For more information on the PWP package, see the Texas Instruments technical brief, literature number SLMA002.

Test board conditions:

1. 3” x 3”, 4 layers, thickness: 0.062”

2. 1.5 oz. copper traces located on the top of the PCB

3. 1.5 oz. copper ground plane on the bottom of the PCB

4. 0.5 oz. copper ground planes on the 2 internal layers

5. 12 thermal vias (see “Recommended Land Pattern” in applications section of this data sheet)

Maximum power dissipation may be limited by overcurrent protection.

(3)

ADDITIONAL 6A SWIFT DEVICES

DEVICE

TPS54610

TPS54672

TPS54680

TPS54673

OUTPUT VOLTAGE

0.9 V to 3.3 V

DDR memory adjustable

Sequencing adjustable

Prebias adjustable

RELATED DC/DC PRODUCTS

D

TPS40000—Low-input, voltage-mode synchronous buck controller

TPS759xx—7.5-A low dropout regulator

PT6440 series—6 A plugin modules

4

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SGLS266D − OCTOBER 2004 − REVISED DECEMBER 2004

ELECTRICAL CHARACTERISTICS

T

J

= –40°C to 125°C, V = 3 V to 6 V (unless otherwise noted)

I

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

V

SUPPLY VOLTAGE, VIN

Input voltage range, VIN

3

6

f

= 350 kHz, FSEL ≤ 0.8 V, RT open, phase pin open

= 550 kHz, FSEL ≥ 2.5 V, RT open, phase pin open

9.8

15

23

s

14

1

I

Quiescent current

mA

s

(Q)

Shutdown, SS/ENA = 0 V

1.4

UNDER VOLTAGE LOCK OUT

Start threshold voltage, UVLO

Stop threshold voltage, UVLO

Hysteresis voltage, UVLO

2.95

2.8

3

V

2.7

0.16

Rising and falling edge deglitch,

2.5

µs

(1)

UVLO

BIAS VOLTAGE

Output voltage, VBIAS

(2)

I

= 0

2.8

2.95

100

V

(VBIAS)

Output current, VBIAS

OUTPUT VOLTAGE

µA

T

= 25°C, VIN = 5 V

0.9

1.2

1.5

1.8

2.5

3.3

V

J

TPS54611

TPS54612

TPS54613

TPS54614

TPS54615

TPS54616

3 V ≤ VIN ≤ 6 V, 0 ≤ I ≤ 6 A, −40° ≤ T ≤ 125°C

−2%

−3%

2%

3%

L

J

T

J

= 25°C, VIN = 5 V

3 V ≤ VIN ≤ 6 V, 0 ≤ I ≤ 6 A, −40° ≤ T ≤ 125°C

L

J

T

J

= 25°C, VIN = 5 V

3 V ≤ VIN ≤ 6 V, 0 ≤ I ≤ 6 A, −40° ≤ T ≤ 125°C

L

J

V

O

Output voltage

T

J

= 25°C, VIN = 5 V

3 V ≤ VIN ≤ 6 V, 0 ≤ I ≤ 6 A, −40° ≤ T ≤ 125°C

L

J

T

J

= 25°C, VIN = 5 V

3 V ≤ VIN ≤ 6 V, 0 ≤ I ≤ 6 A, −40° ≤ T ≤ 125°C

L

J

T

J

= 25°C, VIN = 5 V

4 V ≤ VIN ≤ 6 V, 0 ≤ I ≤ 6 A, −40° ≤ T ≤ 125°C

L

J

REGULATION

Line regulation

(1) (3)

I

= 3 A, 350 ≤ f ≤ 550 kHz, T = 85°C

0.088

%/V

%/A

L

s

J

Load regulation

= 0 A to 6 A, 350 ≤ f ≤ 550 kHz, T = 85°C

0.0917

L

s

J

5

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SGLS266D − OCTOBER 2004 − REVISED DECEMBER 2004

ELECTRICAL CHARACTERISTICS (CONTINUED)

T

J

= –40°C to 125°C, V = 3 V to 6 V (unless otherwise noted)

I

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

OSCILLATOR

FSEL ≤ 0.8 V, RT open

265

350

440

680

308

350

762

Internally set—free running frequency

kHz

FSEL ≥ 2.5 V, RT open

415

252

290

663

2.5

550

280

312

700

(1)

RT = 180 kΩ (1% resistor to AGND)

Externally set—free running

frequency range

RT = 160 kΩ (1% resistor to AGND)

(1)

RT = 68 kΩ (1% resistor to AGND)

High level threshold, FSEL

Low level threshold, FSEL

V

0.8

(1)

Pulse duration, FSEL

50

ns

kHz

V

(1) (4)

Frequency range, FSEL

(1)

330

700

Ramp valley

Ramp amplitude (peak-to-peak)

(1)

0.75

1

(1)

V

Minimum controllable on time

(1)

200

ns

Maximum duty cycle

Specified by design

Static resistive loads only

Tested using circuit in Figure 10.

90%

(1)

(2)

(3)

(4)

To ensure proper operation when RC filter is used between external clock and FSEL pin, the recommended values are R ≤ 1kΩ and

C ≤ 120 pF.

6

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SGLS266D − OCTOBER 2004 − REVISED DECEMBER 2004

ELECTRICAL CHARACTERISTICS (CONTINUED)

T

J

= –40°C to 125°C, V = 3 V to 6 V (unless otherwise noted)

I

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

ERROR AMPLIFIER

Error amplifier open loop voltage gain

(1)

26

dB

MHz

V

Error amplifier unity gain bandwidth

Error amplifier common mode input voltage range

PWM COMPARATOR

3

0

5

(1)

Powered by internal LDO

VBIAS

85

PWM comparator propagation delay time, PWM

comparator input to PH pin (excluding deadtime)

(1)

10-mV overdrive

70

ns

SLOW-START/ENABLE

Enable threshold voltage, SS/ENA

Enable hysteresis voltage, SS/ENA

0.82

1.20

0.03

2.5

3.3

4.5

5.6

3.3

4.7

6.1

5

1.40

V

(1)

Falling edge deglitch, SS/ENA

µs

TPS54611

TPS54612

TPS54613

TPS54614

TPS54615

TPS54616

2.6

3.5

4.4

2.6

3.6

4.7

2.5

1.2

4.1

5.4

6.7

4.1

5.6

7.6

8

(1)

Internal slow-start time

ms

Charge current, SS/ENA

SS/ENA = 0 V

µA

Discharge current, SS/ENA

SS/ENA = 0.2 V, V = 2.7 V

I

2.3

4.0

mA

POWER GOOD

Power good threshold voltage

Power good hysteresis voltage

Power good falling edge deglitch

Output saturation voltage, PWRGD

Leakage current, PWRGD

VSENSE falling

90

3

%V

O

(1)

See

O

35

µs

V

I

= 2.5 mA

0.18

0.3

1

(sink)

V = 5.5 V

µA

I

CURRENT LIMIT

V = 3 V

7.2

10

12

I

Current limit

A

V = 6 V

I

(1)

Current limit leading edge blanking time

(1)

100

200

ns

Current limit total response time

THERMAL SHUTDOWN

Thermal shutdown trip point

(1)

135

150

10

165

_

C

Thermal shutdown hysteresis

OUTPUT POWER MOSFETS

(2)

I

= 3 A, V = 6 V

26

36

47

65

O

I

r

Power MOSFET switches

mΩ

DS(on)

= 3 A, V = 3 V

O

I

(1)

(2)

Specified by design

Matched MOSFETs, low side r

production tested, high side r

DS(on)

specified by design.

DS(on)

7

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SGLS266D − OCTOBER 2004 − REVISED DECEMBER 2004

INTERNAL BLOCK DIAGRAM

VBIAS

AGND

VBIAS

VIN

Enable

Comparator

5 µA

SS/ENA

REG

Falling

Edge

Deglitch

SHUTDOWN

VIN

ILIM

Comparator

1.8 V

VIN

Thermal

Shutdown

145°C

Hysteresis: 0.03

V

Leading

Edge

Blanking

2.5 µs

VIN UVLO

Comparator

Falling

and

Rising

Edge

100 ns

VIN

BOOT

2.94 V

Sensefet

Deglitch

Hysteresis: 0.16

V

30 mΩ

2.5 µs

SS_DIS

SHUTDOWN

L

OUT

V

O

PH

Internal/External

Slow-Start

(Internal Slow-Start Time

=

+

−

C

O

Adaptive Dead-Time

and

Control Logic

R

S

Q

2 kΩ

3.3 ms to 6.6 ms)

PWM

Comparator

40 kΩ

Error

Amplifier

VIN

25 ns Adaptive

Deadtime

V

I

30 mΩ

Feed-Forward

V

I

OSC

PGND

Compensation

Power good

Comparator

Reference/

DAC

Falling

Edge

PWRGD

VSENSE

0.90 V

ref

Deglitch

TPS5461x

Hysteresis: 0.03 Vref

SHUTDOWN

35 µs

FSEL

VSENSE

RT

8

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SGLS266D − OCTOBER 2004 − REVISED DECEMBER 2004

TYPICAL CHARACTERISTICS

DRAIN-SOURCE ON-STATE

RESISTANCE

DRAIN-SOURCE ON-STATE

INTERNALLY SET OSCILLATOR

FREQUENCY

RESISTANCE

vs

JUNCTION TEMPERATURE

vs

JUNCTION TEMPERATURE

100

80

60

40

20

0

120

100

80

750

650

550

450

V

= 5 V

V

= 3.3 V

I

= 3 A

O

I

= 3 A

O

FSEL ≥ 2.5 V

60

FSEL ≤ 0.8 V

40

350

250

20

0

−40

0

25

85

125

−40

0

25

85

125

−40

0

25

85

125

T

J

− Junction Temperature − °C

T

J

− Junction Temperature − °C

T

J

− Junction Temperature − °C

Figure 1

Figure 2

Figure 3

EXTERNALLY SET OSCILLATOR

FREQUENCY

OUTPUT VOLTAGE REGULATION

VOLTAGE REFERENCE

vs

JUNCTION TEMPERATURE

vs

INPUT VOLTAGE

JUNCTION TEMPERATURE

0.8950

0.8930

0.8910

0.8890

0.895

800

T

A

= 85°C

RT = 68 k

700

600

500

400

0.893

0.891

RT = 100 k

f = 350 kHz

0.889

RT = 180 k

0.8870

0.8850

0.887

0.885

300

200

−40

0

25

85

125

3

4

5

6

−40

0

25

85

125

V − Input Voltage − V

I

T

J

− Junction Temperature − °C

T

J

− Junction Temperature − °C

Figure 4

Figure 5

Figure 6

DEVICE POWER LOSSES

vs

INTERNAL SLOW-START TIME

vs

JUNCTION TEMPERATURE

ERROR AMPLIFIER

OPEN LOOP RESPONSE

LOAD CURRENT

0

−20

5

140

3.80

3.65

3.50

3.35

3.20

3.05

R = 10 kΩ,

L

T

F

= 125°C

= 700 kHz

J

S

4.5

C

L

= 160 pF,

120

100

80

T

A

= 25°C

−40

−60

−80

4

V

= 3.3 V

3.5

3

I

Phase

−100

−120

60

2.5

2

1.5

1

40

20

Gain

−140

−160

V

= 5.0 V

I

0

2.90

2.75

−180

−200

0.5

0

−20

0

1

2

3

4

5

6

7

8

0

10

100 1 k 10 k 100 k 1 M 10 M

−40

0

25

85

125

I

− Load Current − A

f − Frequency − Hz

T

J

− Junction Temperature − °C

L

Figure 7

Figure 8

Figure 9

9

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SGLS266D − OCTOBER 2004 − REVISED DECEMBER 2004

APPLICATION INFORMATION

Figure 10 shows the schematic diagram for a typical

TPS54614 application. The TPS54614 (U1) can provide

greater than 6 A of output current at a nominal output

voltage of 1.8 V. For proper operation, the exposed thermal

PowerPAD underneath the integrated circuit package

needs to be soldered to the printed-circuit board.

V

20

21

5

I

VIN

BOOT

3 V − 6 V

220 µF

6

10 µF

0.047 µF

PH

22

23

24

7

PH

7.2 µH

680 µF

8

PH

V

1.8 V

O

9

10

11

10 kΩ

27

28

26

FSEL

RT

PwrGood

Enable

12

13

SS/ENA

VBIAS

PWRGD

NC

25

4

14

15

PH

PGND

16

17

18

3

2

0.1 µF

VSENSE

PGND

C

SS

1

19

AGND

PwrPad

Figure 10. Application Circuit

COMPONENT SELECTION

OPERATING FREQUENCY

In the application circuit, 350 kHz operation is selected by

leaving FSEL open. Different operating frequencies can

be selected by connecting a resistor between RT pin and

AGND. Choose the value of R using Equation 1 for the

desired operating frequency:

The values for the components used in this design

example were selected using the SWIFT designer

software tool. SWIFT designer provides a complete design

environment for developing dc-dc converters using the

TPS54614, or other devices in the SWIFT product family.

Additional design information is available at www.ti.com.

500 kHz

SwitchingFrequency

R +

100 kW

(1)

INPUT FILTER

Alternately, a preset operating frequency of 550 kHz can

be selected by leaving RT open and connecting the FSEL

The input to the circuit is a nominal 3.3 VDC or 5 VDC. The

input filter is a 220-µF POSCAP capacitor, with a

maximum allowable ripple current of 3 A. A 10-µF ceramic

capacitor for the TPS54614 is required, and must be

located as close as possible to the device.

pin to V .

I

OUTPUT FILTER

The output filter is composed of a 5.2-µH inductor and a

470-µF capacitor. The inductor is low dc resistance

(16-mΩ) type, Sumida CDRH104R−5R2. The capacitor

used is a 4-V POSCAP with a maximum ESR of 40 mΩ.

The output filter components work with the internal

compensation network to provide a stable closed loop

response for the converter.

FEEDBACK CIRCUIT

The output voltage of the converter is fed directly into the

VSENSE pin of the TPS54614. The TPS54614 is

internally compensated to provide stability of the output

under varying line and load conditions.

10

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SGLS266D − OCTOBER 2004 − REVISED DECEMBER 2004

GROUNDING AND POWERPAD LAYOUT

LAYOUT CONSIDERATIONS FOR THERMAL

PERFORMANCE

The TPS54611−16 have two internal grounds (analog and

power). Inside the TPS54611−16, the analog ground ties

to all of the noise sensitive signals, while the power ground

ties to the noisier power signals. The PowerPAD is tied

internally to the analog ground. Noise injected between the

two grounds can degrade the performance of the

TPS54611−16, particularly at higher output currents.

However, ground noise on an analog ground plane can

also cause problems with some of the control and bias

signals. For these reasons, separate analog and power

ground planes are recommended. These two planes

should tie together directly at the IC to reduce noise

between the two grounds. The only components that

should tie directly to the power ground plane are the input

capacitor, the output capacitor, the input voltage

decoupling capacitor, and the PGND pins of the

TPS54611−16. The layout of the TPS54614 evaluation

module is representative of a recommended layout for a

4-layer board. Documentation for the TPS54614

evaluation module can be found on the Texas Instruments

web site (www.ti.com) under the TPS54614 product folder.

See the TPS54614−185 User’s Guide, Texas Instruments

(SLVU053) and the application note, Texas Instruments

(SLVA105).

For operation at full rated load current, the analog ground

plane must provide adequate heat dissipating area. A 3

inch by 3 inch plane of 1 ounce copper is recommended,

though not mandatory, depending on ambient temperature

and airflow. Most applications have larger areas of internal

ground plane available, and the PowerPAD should be

connected to the largest area available. Additional areas

on the top or bottom layers also help dissipate heat, and

any area available should be used when 3 A or greater

operation is desired. Connection from the exposes area of

the PowerPAD to the analog ground plane layer should be

made using 0.013 inch diameter vias to avoid solder

wicking through the vias. Six vias should be in the

PowerPAD area with four additional vias located under the

device package. The size of the vias under the package,

but not in the exposed thermal pad area, can be increased

to 0.018. Additional vias beyond the 10 recommended that

enhance thermal performance should be included in areas

not under the device package.

Minimum Recommended Thermal Vias: 8 x 0.013 Diameter Inside

Powerpad Area 4 x 0.018 Diameter Under Device as Shown.

Additional 0.018 Diameter Vias May Be Used if Top Side Analog Ground

Area Is Extended.

Ø0.0130

8 PL

4 PL Ø0.0180

Connect Pin 1 to Analog Ground Plane

in This Area for Optimum Performance

0.0150

0.06

0.0339

0.0650

0.0500

0.3820 0.3478

0.2090

0.0256

0.0500

0.0650

0.0339

Minimum Recommended Exposed

Copper Area for Powerpad. 5mm

Stencils May Require 10 Percent

0.1700

Larger Area

0.1340

0.0630

Minimum Recommended Top

Side Analog Ground Area

0.0400

Figure 11. Recommended Land Pattern for 28-Pin PWP PowerPAD

11

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SGLS266D − OCTOBER 2004 − REVISED DECEMBER 2004

PERFORMANCE GRAPHS

EFFICIENCY

vs

OUTPUT VOLTAGE

vs

LOAD CURRENT

LOOP RESPONSE

100

1.03

1.02

1.01

1

180

60

50

90

80

135

90

40

30

Phase

V

= 5 V

I

V

= 5 V

I

V

= 3.3V

I

20

10

V

= 3.3V

I

70

Gain

0.99

45

0

60

50

0.98

0.97

−10

−20

0

10

100

1 k

10 k

100 k

0

1

2

3

4

5

6

7

8

9

10

0

1

2

3

4

5

I − Load Current − A

L

6

7

8

9

10

I

− Load Current − A

f − Frequency − Hz

L

Figure 12

TRANSIENT RESPONSE

Figure 13

START-UP WAVEFORMS

Figure 14

OUTPUT RIPPLE VOLTAGE

16

80

70

60

400

8

7

6

14

12

10

350

300

50

40

30

20

250

200

150

100

5

4

3

2

8

6

4

10

0

2

0

50

0

1

0

20 40 60 80 100 120 140 160 180 200

0

20 40 60 80 100 120 140 160 180 200

0

2

4

6

8

10 12 14 16 18 20

t − Time − µs

Figure 15

Figure 16

Figure 17

AMBIENT TEMPERATURE

vs

LOAD CURRENT

125

T

F

= 125°C

= 700 kHz

J

S

115

105

V

= 5 V

I

95

85

75

65

55

45

V

= 3.3 V

I

Safe Operating Area

35

25

0

1

2

3

4

5

6

7

8

I

− Load Current − A

L

Figure 18

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SGLS266D − OCTOBER 2004 − REVISED DECEMBER 2004

Second, as the output becomes active, a brief ramp up at

the internal slow-start rate may be observed before the

externally set slow-start rate takes control and the output

rises at a rate proportional to the slow-start capacitor. The

slow-start time set by the capacitor is approximately:

DETAILED DESCRIPTION

Under Voltage Lock Out (UVLO)

The TPS5461x incorporates an under voltage lockout

circuit to keep the device disabled when the input voltage

(VIN) is insufficient. During power up, internal circuits are

held inactive until VIN exceeds the nominal UVLO

threshold voltage of 2.95 V. Once the UVLO start threshold

is reached, device start-up begins. The device operates

until VIN falls below the nominal UVLO stop threshold of

2.8 V. Hysteresis in the UVLO comparator and a 2.5-µs

rising and falling edge deglitch circuit reduces the

likelihood of shutting the device down due to noise on VIN.

0.7 V

(3)

t

+ C

(SS)

5 mA

The actual slow-start time is likely to be less than the above

approximation due to the brief ramp up at the internal rate.

VBIAS Regulator

The VBIAS regulator provides internal analog and digital

blocks with a stable supply voltage over variations in

junction temperature and input voltage. A high quality,

low-ESR, ceramic bypass capacitor is required on the

VBIAS pin. X7R or X5R grade dielectrics are

recommended because their values are more stable over

temperature. The bypass capacitor should be placed close

to the VBIAS pin and returned to AGND.

Slow-Start/Enable (SS/ENA)

The slow-start/enable pin provides two functions. First, the

pin acts as an enable (shutdown) control by keeping the

device turned off until the voltage exceeds the start

threshold voltage of approximately 1.2 V. When SS/ENA

exceeds the enable threshold, device start up begins. The

reference voltage fed to the error amplifier is linearly

ramped up from 0 V to 0.891 V in 3.35 ms. Similarly, the

converter output voltage reaches regulation in

approximately 3.35 ms. Voltage hysteresis and a 2.5-µs

falling edge deglitch circuit reduce the likelihood of

triggering the enable due to noise. See the following table

for start up times for each device

External loading on VBIAS is allowed, with the caution that

internal circuits require a minimum VBIAS of 2.7 V, and

external loads on VBIAS with ac or digital switching noise

may degrade performance. The VBIAS pin may be useful

as a reference voltage for external circuits.

Voltage Reference

The voltage reference system produces a precise,

temperature-stable voltage from a bandgap circuit. A

scaling amplifier and DAC are then used to produce the

reference voltages for each of the fixed output devices.

DEVICE

OUTPUT VOLTAGE

SLOW-START

3.3 ms

TPS54611

TPS54612

TPS54613

TPS54614

TPS54615

TPS54616

0.9 V

1.2 V

1.5 V

1.8 V

2.5 V

3.3 V

Oscillator and PWM Ramp

4.5 ms

The oscillator frequency can be set to internally fixed

values of 350 kHz or 550 kHz using the FSEL pin as a static

digital input. If a different frequency of operation is required

for the application, the oscillator frequency can be

externally adjusted from 280 kHz to 700 kHz by connecting

a resistor from the RT pin to AGND and floating the FSEL

pin. The switching frequency is approximated by the

following equation, where R is the resistance from RT to

AGND:

5.6 ms

3.3 ms

4.7 ms

6.1 ms

The second function of the SS/ENA pin provides an

external means for extending the slow-start time with a

ceramic capacitor connected between SS/ENA and

AGND. Adding a capacitor to the SS/ENA pin has two

effects on start-up. First, a delay occurs between release

of the SS/ENA pin and start-up of the output. The delay is

proportional to the slow-start capacitor value and lasts until

the SS/ENA pin reaches the enable threshold. The

start-up delay is approximately:

100 kW

Switching Frequency +

500 [kHz]

(4)

R

External synchronization of the PWM ramp is possible

over the frequency range of 330 kHz to 700 kHz by driving

a synchronization signal into FSEL and connecting a

resistor from RT to AGND. Choose an RT resistor that sets

the free-running frequency to 80% of the synchronization

signal. Table 1 summarizes the frequency selection

configurations.

1.2 V

(2)

t + C

d

(SS)

5 mA

13

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SGLS266D − OCTOBER 2004 − REVISED DECEMBER 2004

rises to the regulation set-point, setting VSENSE to

Table 1. Summary of the Frequency

Selection Configurations

approximately the same voltage as V . If the error

ref

amplifier output is low, the PWM latch is continually reset

and the high-side FET does not turn on. The low-side FET

remains on until the VSENSE voltage decreases to a

range that allows the PWM comparator to change states.

The TPS54611−TPS54616 devices are capable of sinking

current continuously until the output reaches the

regulation set-point.

SWITCHING

FREQUENCY

FSEL PIN

RT PIN

350 kHz, internally

set

Float or AGND

Float

550 kHz, internally

set

≥ 2.5 V

Externally set 280

kHz to 700 kHz

Float

R = 68 k to 180 k

If the current limit comparator trips for longer than 100 ns,

the PWM latch resets before the PWM ramp exceeds the

error amplifier output. The high-side FET turns off and the

low-side FET turns on to decrease the energy in the output

inductor and consequently decrease the output current.

This process is repeated each cycle in which the current

limit comparator is tripped.

Externally

Synchronization R = RT value for 80% of

signal

synchronized

external synchronization

frequency

(1)

frequency

(1)

To ensure proper operation when RC filter is used between external

clock and FSEL pin, the recommended values are R ≤ 1kΩ and

C ≤ 120 pF.

Dead-Time Control and MOSFET Drivers

Error Amplifier

Adaptive dead-time control prevents shoot-through

current from flowing in both N-channel power MOSFETs

during the switching transitions by actively controlling the

turnon times of the MOSFET drivers. The high-side driver

does not turn on until the voltage at the gate of the low-side

FET is below 2 V. The high-side and low-side drivers are

designed with 300 mA source and sink capability to quickly

drive the power MOSFETs gates. The low-side driver is

supplied from VIN, while the high-side drive is supplied

from the BOOT pin. A bootstrap circuit uses an external

BOOT capacitor and internal 2.5-Ω bootstrap switch

connected between the VIN and BOOT pins. The

integrated bootstrap switch improves drive efficiency and

reduces external component count.

The high performance, wide bandwidth, voltage error

amplifier is gain-limited to provide internal compensation

of the control loop. The user is given limited flexibility in

choosing output L and C filter components. Inductance

values of 4.7 µH to 10 µH are typical and available from

several vendors. The resulting designs exhibit good noise

and ripple characteristics, but with exceptional transient

response. Transient recovery times are typically in the

range of 10 µs to 20 µs.

PWM Control

Signals from the error amplifier output, oscillator, and

current limit circuit are processed by the PWM control

logic. Referring to the internal block diagram, the control

logic includes the PWM comparator, OR gate, PWM latch,

and portions of the adaptive dead-time and control logic

block. During steady-state operation below the current

limit threshold, the PWM comparator output and oscillator

pulse train alternately set and reset the PWM latch. Once

the PWM latch is set, the low-side FET remains on for a

minimum duration set by the oscillator pulse width. During

this period, the PWM ramp discharges rapidly to its valley

voltage. When the ramp begins to charge back up, the

low-side FET turns off and high-side FET turns on. As the

PWM ramp voltage exceeds the error amplifier output

voltage, the PWM comparator resets the latch, thus

turning off the high-side FET and turning on the low-side

FET. The low-side FET remains on until the next oscillator

pulse discharges the PWM ramp.

Overcurrent Protection

Cycle-by-cycle current limiting is achieved by sensing the

current flow through the high-side MOSFET and a

differential amplifier with preset overcurrent threshold. The

high-side MOSFET is turned off within 200 ns of reaching

the current limit threshold. A 100-ns leading edge blanking

circuit prevents false tripping of current limit. Current limit

detection occurs only when current flows from VIN to PH

when sourcing current to the output filter. Load protection

during current sink operation is provided by thermal

shutdown.

Thermal Shutdown

The device uses the thermal shutdown to turn off the power

MOSFETs and disable the controller if the junction

temperature exceeds 150°C. The device is released from

shutdown when the junction temperature decreases to

10°C below the thermal shutdown trip point, and starts up

under control of the slow-start circuit. Thermal shutdown

provides protection when an overload condition is

sustained for several milliseconds. With a persistent fault

condition, the device cycles continuously: starting up by

During transient conditions, the error amplifier output

could be below the PWM ramp valley voltage or above the

PWM peak voltage. If the error amplifier is high, the PWM

latch is never reset, and the high-side FET remains on until

the oscillator pulse signals the control logic to turn the

high-side FET off and the low-side FET on. The device

operates at its maximum duty cycle until the output voltage

14

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SGLS266D − OCTOBER 2004 − REVISED DECEMBER 2004

control of the slow-start circuit, heating up due to the fault,

and then shutting down upon reaching the thermal

shutdown trip point.

output is pulled low. PWRGD is also pulled low if VIN is

less than the UVLO threshold, or SS/ENA is low, or

thermal shutdown is asserted. When VIN = UVLO

threshold, SS/ENA = enable threshold, and VSENSE >

Power Good (PWRGD)

90% of V , the open drain output of the PWRGD pin is

ref

The power good circuit monitors for under voltage

conditions on VSENSE. If the voltage on VSENSE falls

10% below the reference voltage, the open-drain PWRGD

high. A hysteresis voltage equal to 3% of V and a 35-µs

falling edge deglitch circuit prevent tripping of the power

good comparator due to high-frequency noise.

ref

15

PACKAGE OPTION ADDENDUM

www.ti.com

25-Feb-2005

PACKAGING INFORMATION

Orderable Device

TPS54613QPWPRQ1

TPS54614QPWPRQ1

TPS54615QPWPRQ1

Status ⁽¹⁾

ACTIVE

Package Package

Pins Package Eco Plan ⁽²⁾Lead/Ball Finish MSL Peak Temp ⁽³⁾

Qty

Type

Drawing

HTSSOP

PWP

28

2000 Green (RoHS &

no Sb/Br)

Call TI

Level-2-260C-1 YEAR

HTSSOP

PWP

2000 Green (RoHS &

no Sb/Br)

2000 Green (RoHS &

no Sb/Br)

⁽¹⁾The marketing status values are defined as follows:

ACTIVE: Product device recommended for new designs.

LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.

NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in

a new design.

PREVIEW: Device has been announced but is not in production. Samples may or may not be available.

OBSOLETE: TI has discontinued the production of the device.

(2)

Eco Plan - May not be currently available - please check http://www.ti.com/productcontent for the latest availability information and additional

product content details.

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(3)

MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDECindustry standard classifications, and peak solder

temperature.

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Addendum-Page 1

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型号：	TPS54614QPWPRQ1
厂家：	TEXAS INSTRUMENTS
描述：	3-V TO 6-V INPUT, 6-A OUTPUT SYNCHRONOUS BUCK PWM SWITCHER WITH INTEGRATED FETs(SWIFT) 3 V至6 V的输入， 6 -A输出同步降压PWM具有集成FET SWITCHER （ SWIFT ）稳压器开关式稳压器或控制器电源电路开关式控制器光电二极管输出元件输入元件
文件：	总18页 (文件大小：245K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

TPS54614QPWPRQ1 [TI]

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