TPS54616 [TI]
3-V TO 6-V INPUT, 6-A OUTPUT SYNCHRONOUS BUCK PWM SWITCHER WITH INTEGRATED FETs; 3 V至6 V的输入， 6 -A输出，带集成FET的同步降压型PWM SWITCHER
| 型号： | TPS54616 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 3-V TO 6-V INPUT, 6-A OUTPUT SYNCHRONOUS BUCK PWM SWITCHER WITH INTEGRATED FETs |
| 文件： | 总16页 (文件大小：290K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Typical Size
6,4 mm X 9,7 mm
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SLVS398D − JUNE 2001 − REVISED JULY 2003
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FEATURES
DESCRIPTION
D
30-mΩ, 12-A Peak MOSFET Switches for High
Efficiency at 6-A Continuous Output Source
or Sink Current
Adjustable Output Voltage Down To 0.9 V
With 1.0% Accuracy
As a member of the SWIFT family of dc/dc regulators,
the TPS54610 low-input voltage high-output current
synchronous buck PWM converter integrates all
required active components. Included on the substrate
with the listed features are a true, high performance,
voltage error amplifier that enables maximum
performance and flexibility in choosing the output filter
L and C components; an under-voltage-lockout circuit
to prevent start-up until the input voltage reaches 3 V;
an internally or externally set slow-start circuit to limit
inrush currents; and a power good output useful for
processor/logic reset, fault signaling, and supply
sequencing.
D
D
Wide PWM Frequency:
Fixed 350 kHz, 550 kHz or
Adjustable 280 kHz to 700 kHz
Synchronizable to 700 kHz
Load Protected by Peak Current Limit and
Thermal Shutdown
Integrated Solution Reduces Board Area and
Component Count
D
D
D
The TPS54610 is available in a thermally enhanced
28-pin TSSOP (PWP) PowerPAD package, which
eliminates bulky heatsinks. TI provides evaluation
modules and the SWIFT designer software tool to aid
in quickly achieving high-performance power supply
designs to meet aggressive equipment development
cycles.
APPLICATIONS
D
D
Low-Voltage, High-Density Distributed Power
Systems
Point of Load Regulation for High
Performance DSPs, FPGAs, ASICs and
Microprocessors
D
D
Broadband, Networking and Optical
Communications Infrastructure
Portable Computing/Notebook PCs
SIMPLIFIED SCHEMATIC
EFFICIENCY AT 350 kHz
100
Input
Output
95
90
85
80
VIN
PH
TPS54610
BOOT
PGND
75
70
65
VSENSE
AGND COMP
VBIAS
V
V
= 5 V,
I
60
55
= 3.3 V
O
50
0
1
2
3
4
5
6
Load Current − A
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments
semiconductor products and disclaimers thereto appears at the end of this data sheet.
PowerPAD and SWIFT are trademarks of Texas Instruments.
ꢁꢔ ꢋ ꢛꢎ ꢒ ꢀꢌ ꢋꢍ ꢛ ꢐꢀꢐ ꢠꢡ ꢢꢣ ꢤ ꢥꢦ ꢧꢠꢣꢡ ꢠꢝ ꢨꢩ ꢤ ꢤ ꢪꢡꢧ ꢦꢝ ꢣꢢ ꢫꢩꢬ ꢭꢠꢨ ꢦꢧꢠ ꢣꢡ ꢮꢦ ꢧꢪꢯ ꢁꢤ ꢣꢮꢩ ꢨꢧꢝ
ꢨ ꢣꢡ ꢢꢣꢤ ꢥ ꢧꢣ ꢝ ꢫꢪ ꢨ ꢠ ꢢꢠ ꢨ ꢦ ꢧꢠ ꢣꢡꢝ ꢫ ꢪꢤ ꢧꢰꢪ ꢧꢪ ꢤ ꢥꢝ ꢣꢢ ꢀꢪꢱ ꢦꢝ ꢌꢡꢝ ꢧꢤ ꢩꢥ ꢪꢡꢧ ꢝ ꢝꢧ ꢦꢡꢮ ꢦꢤ ꢮ ꢲ ꢦꢤ ꢤ ꢦ ꢡꢧꢳꢯ
ꢁꢤ ꢣ ꢮꢩꢨ ꢧ ꢠꢣ ꢡ ꢫꢤ ꢣ ꢨ ꢪ ꢝ ꢝ ꢠꢡ ꢴ ꢮꢣ ꢪ ꢝ ꢡꢣꢧ ꢡꢪ ꢨꢪ ꢝꢝ ꢦꢤ ꢠꢭ ꢳ ꢠꢡꢨ ꢭꢩꢮ ꢪ ꢧꢪ ꢝꢧꢠ ꢡꢴ ꢣꢢ ꢦꢭ ꢭ ꢫꢦ ꢤ ꢦꢥ ꢪꢧꢪ ꢤ ꢝꢯ
Copyright 2002, Texas Instruments Incorporated
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SLVS398D − JUNE 2001 − REVISED JULY 2003
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during
storage or handling to prevent electrostatic damage to the MOS gates.
ORDERING INFORMATION
T
A
OUTPUT VOLTAGE
PACKAGE
PART NUMBER
(1)
−40°C to 85°C
Adjustable down to 0.9 V
Plastic HTSSOP (PWP)
TPS54610PWP
(1)
The PWP package is also available taped and reeled. Add an R suffix to the device type (i.e., TPS54610PWPR). See the application section of
the data sheet for PowerPAD drawing and layout information.
ABSOLUTE MAXIMUM RATINGS
over operating free-air temperature range unless otherwise noted
(1)
TPS54610
−0.3 V to 7 V
−0.3 V to 6 V
−0.3 V to 4V
−0.3 V to 17 V
−0.3 V to 7 V
−0.6 V to 10 V
UNIT
VIN, SS/ENA, SYNC
RT
Input voltage range, V
V
I
VSENSE
BOOT
VBIAS, COMP, PWRGD
Output voltage range, V
V
O
PH
PH
Internally Limited
Source current, I
O
COMP, VBIAS
PH
6
mA
A
12
6
COMP
Sink current, I
S
mA
SS/ENA, PWRGD
AGND to PGND
10
Voltage differential
Operating virtual junction temperature range, T
0.3
V
−40 to 125
−65 to 150
300
°C
°C
°C
J
Storage temperature, T
stg
Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds
(1)
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
RECOMMENDED OPERATING CONDITIONS
MIN NOM MAX UNIT
Input voltage, V
3
6
V
I
Operating junction temperature, T
−40
125
°C
J
DISSIPATION RATINGS(1)(2)
THERMAL IMPEDANCE
JUNCTION-TO-AMBIENT
T
= 25°C
T
= 70°C
T = 85°C
A
A
A
PACKAGE
POWER RATING POWER RATING POWER RATING
(3)
28 Pin PWP with solder
18.2 °C/W
40.5 °C/W
5.49 W
3.02 W
1.36 W
2.20 W
0.99 W
28 Pin PWP without solder
2.48 W
(1)
(2)
For more information on the PWP package, refer to TI technical brief, literature number SLMA002.
Test board conditions:
1. 3” x 3”, 4 layers, thickness: 0.062”
2. 1.5 oz. copper traces located on the top of the PCB
3. 1.5 oz. copper ground plane on the bottom of the PCB
4. 0.5 oz. copper ground planes on the 2 internal layers
5. 12 thermal vias (see “Recommended Land Pattern” in applications section of this data sheet)
Maximum power dissipation may be limited by over current protection.
(3)
2
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SLVS398D − JUNE 2001 − REVISED JULY 2003
ELECTRICAL CHARACTERISTICS
over operating free-air temperature range unless otherwise noted
PARAMETER
SUPPLY VOLTAGE, VIN
TEST CONDITIONS
MIN
TYP
MAX
UNIT
Input voltage range, VIN
3.0
11
6.0
V
f = 350 kHz, SYNC ≤ 0.8 V, RT open,
PH pin open
s
15.8
f = 550 kHz, SYNC ≥ 2.5 V, RT open,
PH pin open
I
Quiescent current
mA
s
(Q)
16
23.5
1.4
Shutdown, SS/ENA = 0 V
1
UNDER VOLTAGE LOCK OUT
Start threshold voltage, UVLO
2.95
2.80
0.16
2.5
3.0
V
V
Stop threshold voltage, UVLO
Hysteresis voltage, UVLO
2.70
0.14
V
(1)
Rising and falling edge deglitch, UVLO
µs
BIAS VOLTAGE
Output voltage, VBIAS
Output current, VBIAS
I
= 0
2.70
2.80
2.90
100
V
(VBIAS)
(2)
µA
CUMULATIVE REFERENCE
V
ref
Accuracy
0.882 0.891
0.900
V
REGULATION
I
L
I
L
I
L
I
L
= 3 A, f = 350 kHz, T = 85°C
0.04
0.04
0.03
0.03
s
J
(1)(3)
Line regulation
%/V
%/A
= 3 A, f = 550 kHz, T = 85°C
s
J
= 0 A to 6 A, f = 350 kHz, T = 85°C
s
J
(1)(3)
Load regulation
= 0 A to 6 A, f = 550 kHz, T = 85°C
s
J
OSCILLATOR
Internally set—free running frequency
SYNC ≤ 0.8 V,
SYNC ≥ 2.5 V,
RT open
RT open
280
440
252
460
663
2.5
350
550
280
500
700
420
660
308
540
762
kHz
kHz
(1)
RT = 180 kΩ (1% resistor to AGND)
RT = 100 kΩ (1% resistor to AGND)
(1)
RT = 68 kΩ (1% resistor to AGND)
Externally set—free running frequency range
High level threshold, SYNC
V
V
Low level threshold, SYNC
0.8
Pulse duration, external synchronization,
SYNC
50
ns
(1)
(1)
Frequency range, SYNC
(1)
330
700
kHz
V
Ramp valley
Ramp amplitude (peak-to-peak)
0.75
1
(1)
(1)
V
Minimum controllable on time
Maximum duty cycle
200
ns
90%
(1)
(2)
(3)
Specified by design
Static resistive loads only
Specified by the circuit used in Figure 10
3
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SLVS398D − JUNE 2001 − REVISED JULY 2003
ELECTRICAL CHARACTERISTICS (continued)
over operating free-air temperature range unless otherwise noted
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
ERROR AMPLIFIER
(1)
Error amplifier open loop voltage gain
Error amplifier unity gain bandwidth
1 kΩ COMP to AGND
90
3
110
5
dB
(1)
Parallel 10 kΩ, 160 pF COMP to AGND
MHz
Error amplifier common mode input voltage
range
(1)
Powered by internal LDO
0
VBIAS
250
V
Input bias current, VSENSE
VSENSE = V
ref
60
nA
Output voltage slew rate (symmetric), COMP
1.0
1.4
V/µs
PWM COMPARATOR
PWM comparator propagation delay time,
PWM comparator input to PH pin (excluding
deadtime)
(1)
10-mV overdrive
70
85
ns
SLOW-START/ENABLE
Enable threshold voltage, SS/ENA
Enable hysteresis voltage, SS/ENA
0.82
1.20
0.03
2.5
3.35
5
1.40
V
V
(1)
Falling edge deglitch, SS/ENA
µs
ms
µA
mA
Internal slow-start time
2.6
3
4.1
8
Charge current, SS/ENA
Discharge current, SS/ENA
SS/ENA = 0 V
SS/ENA = 0.2 V, V = 2.7 V
I
2.0
2.3
4.0
POWER GOOD
Power good threshold voltage
Power good hysteresis voltage
VSENSE falling
90
3
%V
%V
ref
(1)
(1)
ref
Power good falling edge deglitch
35
µs
Output saturation voltage, PWRGD
Leakage current, PWRGD
I
= 2.5 mA
0.18
0.3
1
V
(sink)
V = 5.5 V
µA
I
CURRENT LIMIT
(1)
(1)
V = 3 V Output shorted
7.2
10
10
12
I
Current limit trip point
A
V = 6 V Output shorted
I
(1)
Current limit leading edge blanking time
100
200
ns
ns
(1)
Current limit total response time
THERMAL SHUTDOWN
Thermal shutdown trip point
(1)
(1)
135
150
10
165
°C
°C
Thermal shutdown hysteresis
OUTPUT POWER MOSFETS
(4)
(4)
V = 6 V
26
36
47
65
I
r
Power MOSFET switches
mΩ
DS(on)
V = 3 V
I
(1)
(2)
(3)
(4)
Specified by design
Static resistive loads only
Specified by the circuit used in Figure 10
Matched MOSFETs low-side r production tested, high-side r
specified by design
DS(on) DS(on)
4
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SLVS398D − JUNE 2001 − REVISED JULY 2003
PWP PACKAGE
(TOP VIEW)
1
28
AGND
VSENSE
COMP
PWRGD
BOOT
PH
RT
2
27
26
25
24
23
22
21
20
19
18
17
16
15
SYNC
SS/ENA
VBIAS
VIN
VIN
VIN
3
4
5
6
7
PH
PH
PH
PH
PH
PH
PH
PH
THERMAL
PAD
8
VIN
VIN
9
10
11
12
13
14
PGND
PGND
PGND
PGND
PGND
TERMINAL FUNCTIONS
TERMINAL
DESCRIPTION
NAME
AGND
NO.
1
Analog ground. Return for compensation network/output divider, slow-start capacitor, VBIAS capacitor, RT resistor and
SYNC pin. Connect PowerPAD to AGND.
BOOT
5
3
Bootstrap output. 0.022-µF to 0.1-µF low-ESR capacitor connected from BOOT to PH generates floating drive for the
high-side FET driver.
COMP
PGND
Error amplifier output. Connect frequency compensation network from COMP to VSENSE
15−19 Power ground. High current return for the low-side driver and power MOSFET. Connect PGND with large copper areas
to the input and output supply returns, and negative terminals of the input and output capacitors. A single point connection
to AGND is recommended.
PH
6−14 Phase output. Junction of the internal high-side and low-side power MOSFETs, and output inductor.
PWRGD
4
Power good open drain output. High when VSENSE ≥ 90% V , otherwise PWRGD is low. Note that output is low when
SS/ENA is low or the internal shutdown signal is active.
ref
RT
28
26
27
Frequency setting resistor input. Connect a resistor from RT to AGND to set the switching frequency. When using the
SYNC pin, set the RT value for a frequency at or slightly lower than the external oscillator frequency.
SS/ENA
SYNC
Slow-start/enable input/output. Dual function pin which provides logic input to enable/disable device operation and
capacitor input to externally set the start-up time.
Synchronization input. Dual function pin which provides logic input to synchronize to an external oscillator or pin select
between two internally set switching frequencies. When used to synchronize to an external signal, a resistor must be
connected to the RT pin.
VBIAS
25
Internal bias regulator output. Supplies regulated voltage to internal circuitry. Bypass VBIAS pin to AGND pin with a high
quality, low-ESR 0.1-µF to 1.0-µF ceramic capacitor.
20−24 Input supply for the power MOSFET switches and internal bias regulator. Bypass VIN pins to PGND pins close to device
VIN
package with a high quality, low-ESR 10-µF ceramic capacitor.
VSENSE
2
Error amplifier inverting input. Connect to output voltage through compensation network/output divider.
5
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SLVS398D − JUNE 2001 − REVISED JULY 2003
INTERNAL BLOCK DIAGRAM
VBIAS
AGND
VBIAS
VIN
Enable
Comparator
SS/ENA
REG
Falling
Edge
SHUTDOWN
VIN
ILIM
Comparator
1.2 V
3 − 6 V
Deglitch
Thermal
Shutdown
150°C
Hysteresis: 0.03
Leading
Edge
Blanking
2.5 µs
V
VIN UVLO
Comparator
Falling
and
100 ns
VIN
BOOT
Rising
Edge
2.95 V
Deglitch
Hysteresis: 0.16
V
30 mΩ
2.5 µs
SS_DIS
SHUTDOWN
L
OUT
V
O
PH
Internal/External
Slow-start
(Internal Slow-start Time = 3.35 ms
+
−
C
O
Adaptive Dead-Time
and
Control Logic
R
S
Q
Error
Amplifier
PWM
Comparator
Reference
VIN
VREF = 0.891 V
30 mΩ
OSC
PGND
Powergood
Comparator
PWRGD
VSENSE
0.90 V
Falling
Edge
Deglitch
ref
TPS54610
Hysteresis: 0.03 Vref
SHUTDOWN
35 µs
SYNC
VSENSE
COMP
RT
ADDITIONAL 6A SWIFT DEVICES, (REFER TO SLVS397 AND SLVS400)
DEVICE
TPS54611
TPS54612
TPS54613
OUTPUT VOLTAGE
DEVICE
TPS54614
TPS54615
TPS54616
OUTPUT VOLTAGE
DEVICE
TPS54672
TPS54673
TPS54680
OUTPUT VOLTAGE
DDR memory/Adjustable
Prebias/adjustable
0.9 V
1.2 V
1.5 V
1.8 V
2.5 V
3.3 V
Sequencing/adjustable
RELATED DC/DC PRODUCTS
D
D
D
TPS40000—Low-input, voltage-mode synchronous buck controller
TPS759xx—7.5 A low dropout regulator
PT6440 series—6 A plugin modules
6
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SLVS398D − JUNE 2001 − REVISED JULY 2003
TYPICAL CHARACTERISTICS
INTERNALLY SET
DRAIN-SOURCE
DRAIN-SOURCE
OSCILLATOR FREQUENCY
ON-STATE RESISTANCE
vs
JUNCTION TEMPERATURE
ON-STATE RESISTANCE
vs
JUNCTION TEMPERATURE
750
vs
JUNCTION TEMPERATURE
60
50
40
60
VIN = 3.3 V
VIN = 5 V
I
= 6 A
O
50
650
I
= 6 A
O
SYNC ≥ 2.5 V
40
550
30
20
30
20
450
SYNC ≤ 0.8 V
350
250
10
0
10
0
−40
0
25
85
125
−40
0
25
85
125
−40
0
25
85
125
T
J
− Junction Temperature − °C
T
J
− Junction Temperature − °C
T
J
− Junction Temperature − °C
Figure 1
Figure 2
Figure 3
EXTERNALLY SET
OSCILLATOR FREQUENCY
vs
DEVICE POWER LOSSES AT T = 125°C
J
VOLTAGE REFERENCE
vs
JUNCTION TEMPERATURE
vs
LOAD CURRENT
JUNCTION TEMPERATURE
5
0.895
0.893
0.891
0.889
800
700
600
T
= 125°C
= 700 kHz
J
4.5
4
f
s
RT = 68 k
RT = 100 k
RT = 180 k
V
= 3.3 V
I
3.5
3
2.5
2
500
400
300
200
1.5
1
V
I
= 5 V
0.887
0.885
0.5
0
0
1
2
3
4
5
6
7
8
−40
0
25
85
125
−40
0
25
85
125
I
− Load Current − A
L
T
J
− Junction Temperature − °C
T
J
− Junction Temperature − °C
Figure 6
Figure 4
Figure 5
INTERNAL SLOW-START TIME
vs
JUNCTION TEMPERATURE
OUTPUT VOLTAGE REGULATION
ERROR AMPLIFIER
OPEN LOOP RESPONSE
vs
INPUT VOLTAGE
0
140
3.80
0.895
0.893
0.891
0.889
R
C
T
= 10 kΩ,
= 160 pF,
= 25°C
L
L
A
T
= 85°C,
= 3 A
A
−20
120
100
80
I
O
3.65
3.50
−40
−60
−80
Phase
Gain
f
= 550 kHz
3.35
s
−100
−120
−140
−160
−180
−200
60
3.20
3.05
40
20
0.887
0.885
2.90
2.75
0
−20
1
10 100 1 k 10 k 100 k 1 M 10 M
−40
0
25
85
125
3
3.5
4
4.5
5
5.5
6
f − Frequency − Hz
T
J
− Junction Temperature − °C
V − Input Voltage − V
I
Figure 7
Figure 8
Figure 9
7
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SLVS398D − JUNE 2001 − REVISED JULY 2003
APPLICATION INFORMATION
Figure 10 shows the schematic diagram for a typical
TPS54610 application. The TPS54610 (U1) can provide
greater than 6 A of output current at a nominal output
voltage of 3.3 V. For proper thermal performance, the
exposed thermal PowerPAD underneath the integrated
circuit package must be soldered to the printed-circuit
board.
V
I
C2
220 µF
10 V
U1
+
C8
TPS54610PWP
10 µF
28
24
RT
VIN
R2
23
22
21
VIN
VIN
VIN
VIN
PH
PH
PH
PH
PH
PH
PH
PH
10 kΩ
27
26
SYNC
SS/ENA
L1
4.7 µH
20
14
13
V
O
25
C9
470 µF
4 V
C10
470 µF
4 V
C11
100 pF
+
+
VBIAS
PWRGD
COMP
C1
0.047 µF
12
11
PWRGD
4
3
10
9
C4
0.1 µF
8
7
6
C7
PH
BOOT
PGND
PGND
2
1
5
VSENSE
AGND
19
18
17
16
15
0.047 µF
PGND
PGND
PGND
C5
5600 pF
C3
120 pF
POWERPAD
R1
9.09 kΩ
C6
R5
1.74 kΩ
8200 pF
R3
3.74 kΩ
R4
10 kΩ
Figure 10. Application Circuit
current is carried in both C2 and C8, and the return path to
PGND must avoid the current circulating in the output
capacitors C9 and C10.
COMPONENT SELECTION
The values for the components used in this design
example were selected using the SWIFT designer
software tool. SWIFT designer provides a complete design
environment for developing dc-dc converters using the
TPS54610.
FEEDBACK CIRCUIT
The resistor divider network of R3 and R4 sets the output
voltage for the circuit at 3.3 V. R4, along with R1, R5, C3,
C5, and C6 form the loop compensation network for the
circuit. For this design, a Type 3 topology is used.
INPUT FILTER
The input to the circuit is a nominal 5 VDC. The input filter
C2 is a 220-µF POSCAP capacitor, with a maximum
allowable ripple current of 3 A. C8 provides high frequency
decoupling of the TPS54610 from the input supply and
must be located as close as possible to the device. Ripple
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The only components that must tie directly to the power
ground plane are the input capacitor, the output capacitor,
the input voltage decoupling capacitor, and the PGND pins
of the TPS54610. The layout of the TPS54610 evaluation
module is representative of a recommended layout for a
4-layer board. Documentation for the TPS54610
evaluation module can be found on the Texas Instruments
web site under the TPS54610 product folder. See the
TPS54610 EVM user’s guide, TI literature number
SLVU054, and the application note, TI literature number
SLVA104.
OPERATING FREQUENCY
In the application circuit, the 350 kHz operation is selected
by leaving RT and SYNC open. Connecting a 180 kΩ to 68
kΩ resistor between RT (pin 28) and analog ground can be
used to set the switching frequency to 280 kHz to 700 kHz.
To calculate the RT resistor, use the equation below:
500 kHz
Switching Frequency
R +
100 [kW]
(1)
OUTPUT FILTER
LAYOUT CONSIDERATIONS FOR THERMAL
PERFORMANCE
The output filter is composed of a 4.7-µH inductor and two
470-µF capacitors. The inductor is a low dc resistance (12
mΩ) type, Coiltronics UP3B−4R7. The capacitors used
are 4 V POSCAP types with a maximum ESR of 0.040 Ω.
The feedback loop is compensated so that the unity gain
frequency is approximately 25 kHz.
For operation at full rated load current, the analog ground
plane must provide an adequate heat dissipating area. A
3-inch by 3-inch plane of 1 ounce copper is recommended,
though not mandatory, depending on ambient temperature
and airflow. Most applications have larger areas of internal
ground plane available, and the PowerPAD must be
connected to the largest area available. Additional areas
on the top or bottom layers also help dissipate heat, and
any area available must be used when 6 A or greater
operation is desired. Connection from the exposed area of
the PowerPAD to the analog ground plane layer must be
made using 0.013 inch diameter vias to avoid solder
wicking through the vias. Eight vias must be in the
PowerPAD area with four additional vias located under the
device package. The size of the vias under the package,
but not in the exposed thermal pad area, can be increased
to 0.018. Additional vias beyond the twelve recommended
that enhance thermal performance must be included in
areas not under the device package.
GROUNDING AND POWERPAD LAYOUT
The TPS54610 has two internal grounds (analog and
power). Inside the TPS54610, the analog ground ties to all
of the noise sensitive signals, while the power ground ties
to the noisier power signals. The PowerPAD must be tied
directly to AGND. Noise injected between the two grounds
can degrade the performance of the TPS54610,
particularly at higher output currents. However, ground
noise on an analog ground plane can also cause problems
with some of the control and bias signals. Therefore,
separate analog and power ground planes are
recommended. These two planes must tie together
directly at the IC to reduce noise between the two grounds.
Minimum Recommended Thermal Vias: 8 x 0.013 Diameter Inside
Powerpad Area 4 x 0.018 Diameter Under Device as Shown.
Additional 0.018 Diameter Vias May Be Used if Top Side Analog Ground
Area Is Extended.
Ø0.0130
8 PL
4 PL Ø0.0180
Connect Pin 1 to Analog Ground Plane
in This Area for Optimum Performance
0.0150
0.06
0.0339
0.0650
0.0500
0.3820 0.3478
0.2090
0.0256
0.0500
0.0500
0.0650
0.0339
Minimum Recommended Exposed
Copper Area for Powerpad. 5mm
Stencils May Require 10 Percent
0.1700
Larger Area
0.1340
0.0630
Minimum Recommended Top
Side Analog Ground Area
0.0400
Figure 11. Recommended Land Pattern for 28-Pin PWP PowerPAD
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SLVS398D − JUNE 2001 − REVISED JULY 2003
PERFORMANCE GRAPHS
EFFICIENCY
vs
LOAD REGULATION
EFFICIENCY
vs
vs
OUTPUT CURRENT
OUTPUT CURRENT
OUTPUT CURRENT
1.004
1.003
100
95
90
85
80
75
70
65
60
55
50
100
V
V
T
= 5 V,
= 3.3 V,
= 25°C,
= 550 kHz
I
O
A
95
90
85
1.002
1.001
f
s
V
= 3.3 V
O
V
= 2.5 V
O
80
75
70
65
60
55
50
V
= 1.8 V
V
= 1.8 V
O
O
1
V
= 1.2 V
O
V
= 1.2 V
0.999
O
V
= 5 V,
V
= 3.3 V,
0.998
I
I
f = 550 kHz,
L = 4.7 µH,
f = 550 kHz,
L = 4.7 µH,
0.997
0.996
T
A
= 25°C
T
A
= 25°C
0
1
2
3
4
5
6
7
0
1
2
3
4
5
6
0
1
2
3
4
5
6
7
I
− Output Current − A
I
− Output Current − A
I
− Output Current − A
O
O
O
Figure 12
Figure 13
Figure 14
LINE REGULATION
vs
AMBIENT TEMPERATURE
vs
INPUT VOLTAGE
LOAD CURRENT
LOOP RESPONSE
1.002
125
115
105
95
60
180
135
V
V
T
= 5 V,
V
V
I
= 5 V,
I
I
T
J
= 125°C
= 3.3 V,
= 3.3 V,
1.0015
O
O
f
= 700 kHz
s
= 25°C,
= 550 kHz
= 6 A,
A
O
I
= 6 A
O
f
T
A
= 25°C,
1.001
1.0005
1
s
40
20
V
= 5 V
I
f
= 550 kHz
s
I
= 3 A
85
O
(1)
Safe Operating Area
75
90
65
Phase
V
= 3.3 V
0.9995
I
55
No Load
Gain
0
0.999
45
0
45
0.9985
0.998
35
−20
25
4
4.5
5
5.5
6
0
1
2
3
4
5
6
7
8
100
1 k
10 k
100 k
1 M
I
− Output Current − A
V − Input Voltage − V
I
O
f − Frequency − Hz
Figure 15
Figure 16
Figure 17
LOAD TRANSIENT RESPONSE
SLOW-START TIMING
OUTPUT RIPPLE VOLTAGE
V
= 5 V,
I
V
V
= 5 V,
I
0.047 µF
Slow-start Cap
= 3.3 V,
O
6A, 350 kHz
V
= 5 V,
I
1A to 5A,
4.0 ms/div
Time − 1 µs/div
100 µs/div
Figure 18
Figure 19
Figure 20
(1)
Safe operating area is applicable to the test board conditions in the Dissipation Ratings
10
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Figure 21 shows the schematic diagram for a reduced
size, high frequency application using the TPS54610. The
TPS54610 (U1) can provide up to 6 A of output current at
a nominal output voltage of 1.8 V. A small size 0.56 uH
inductor is used and the switching frequency is set to 680
kHz by R1. The compensation network is optimized for fast
transient response as shown in Figure 21. For good
thermal performance, the PowerPAD underneath the
integrated circuit TPS54610 needs to be soldered well to
the printed-circuit board. Application information is
available in TI literature number SLVA107, Designing for
Small-Size, High-Frequency Applications With Swift
Family of Synchronous Buck Regulators.
V
I
U1
C1
10 µF
C2
10 µF
TPS54610PWP
R1
28
24
23
22
21
RT
VIN
71.5 kΩ
VIN
VIN
VIN
VIN
PH
PH
PH
PH
PH
PH
PH
PH
27
26
SYNC
SS/ENA
C3
20
14
13
0.047 µF
C4
25
VBIAS
PWRGD
COMP
1 µF
12
11
4
3
10
9
C5
R2
8
7
6
10 kΩ
L1
0.56 µH
470 pF
C6
V
O
PH
BOOT
PGND
PGND
470 pF
2
1
5
C7
C8
150 µF
C9
150 µF
C10
1 pF
+
+
VSENSE
19
18
17
16
15
0.047 µF
R5
1.47 kΩ
R4
2.4 Ω
PGND
PGND
PGND
R3
AGND
39 Ω
C11
3300 pF
R6
1.5 kΩ
POWERPAD
C12
0.012 µF
Figure 21. Small Size, High Frequency Design
TRANSIENT RESPONSE, 1.5-A to 4.5-A STEP
10 µs/div
Figure 22
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DETAILED DESCRIPTION
VBIAS REGULATOR (VBIAS)
The VBIAS regulator provides internal analog and digital
blocks with a stable supply voltage over variations in
junction temperature and input voltage. A high quality,
low-ESR, ceramic bypass capacitor is required on the
VBIAS pin. X7R or X5R grade dielectrics are
recommended because their values are more stable over
temperature. The bypass capacitor must be placed close
to the VBIAS pin and returned to AGND.
UNDERVOLTAGE LOCK OUT (UVLO)
The TPS54610 incorporates an under voltage lockout
circuit to keep the device disabled when the input voltage
(VIN) is insufficient. During power up, internal circuits are
held inactive until VIN exceeds the nominal UVLO
threshold voltage of 2.95 V. Once the UVLO start threshold
is reached, device start-up begins. The device operates
until VIN falls below the nominal UVLO stop threshold of
2.8 V. Hysteresis in the UVLO comparator, and a 2.5-µs
rising and falling edge deglitch circuit reduce the likelihood
of shutting the device down due to noise on VIN.
External loading on VBIAS is allowed, with the caution that
internal circuits require a minimum VBIAS of 2.70 V, and
external loads on VBIAS with ac or digital switching noise
may degrade performance. The VBIAS pin may be useful
as a reference voltage for external circuits.
VOLTAGE REFERENCE
The voltage reference system produces a precise V
SLOW-START/ENABLE (SS/ENA)
ref
signal by scaling the output of a temperature stable
bandgap circuit. During manufacture, the bandgap and
scaling circuits are trimmed to produce 0.891 V at the
output of the error amplifier, with the amplifier connected
as a voltage follower. The trim procedure adds to the high
precision regulation of the TPS54610, since it cancels
offset errors in the scale and error amplifier circuits.
The slow-start/enable pin provides two functions. First, the
pin acts as an enable (shutdown) control by keeping the
device turned off until the voltage exceeds the start
threshold voltage of approximately 1.2 V. When SS/ENA
exceeds the enable threshold, device start-up begins. The
reference voltage fed to the error amplifier is linearly
ramped up from 0 V to 0.891 V in 3.35 ms. Similarly, the
converter output voltage reaches regulation in
approximately 3.35 ms. Voltage hysteresis and a 2.5-µs
falling edge deglitch circuit reduce the likelihood of
triggering the enable due to noise.
OSCILLATOR AND PWM RAMP
The oscillator frequency can be set to internally fixed
values of 350 kHz or 550 kHz using the SYNC pin as a
static digital input. If a different frequency of operation is
required for the application, the oscillator frequency can be
externally adjusted from 280 to 700 kHz by connecting a
resistor between the RT pin and AGND and floating the
SYNC pin. The switching frequency is approximated by
the following equation, where R is the resistance from RT
to AGND:
The second function of the SS/ENA pin provides an
external means of extending the slow-start time with a
low-value capacitor connected between SS/ENA and
AGND.
Adding a capacitor to the SS/ENA pin has two effects on
start-up. First, a delay occurs between release of the
SS/ENA pin and start-up of the output. The delay is
proportional to the slow-start capacitor value and lasts
until the SS/ENA pin reaches the enable threshold. The
start-up delay is approximately:
(4)
100 kW
Switching Frequency +
500 [kHz]
R
External synchronization of the PWM ramp is possible
over the frequency range of 330 kHz to 700 kHz by driving
a synchronization signal into SYNC and connecting a
resistor from RT to AGND. Choose a resistor between the
RT and AGND which sets the free running frequency to
80% of the synchronization signal. The following table
summarizes the frequency selection configurations:
(2)
1.2 V
t + C
d
(SS)
5 mA
Second, as the output becomes active, a brief ramp-up at
the internal slow-start rate may be observed before the
externally set slow-start rate takes control and the output
rises at a rate proportional to the slow-start capacitor. The
slow-start time set by the capacitor is approximately:
SWITCHING
FREQUENCY
SYNC PIN
Float or AGND
≥ 2.5 V
RT PIN
350 kHz, internally
set
Float
Float
550 kHz, internally
set
(3)
0.7 V
t
+ C
Externally set 280
kHz to 700 kHz
Float
R = 180 kΩ to 68 kΩ
(SS)
(SS)
5 mA
Externally
synchronized
frequency
Synchronization
signal
R = RT value for 80%
of external synchro-
nization frequency
The actual slow-start time is likely to be less than the above
approximation due to the brief ramp-up at the internal rate.
12
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current from flowing in both N-channel power MOSFETs
during the switching transitions by actively controlling the
turnon times of the MOSFET drivers. The high-side driver
does not turn on until the voltage at the gate of the low-side
FET is below 2 V. While the low-side driver does not turn
on until the voltage at the gate of the high-side MOSFET
is below 2 V.
ERROR AMPLIFIER
The high performance, wide bandwidth, voltage error
amplifier sets the TPS54610 apart from most dc/dc
converters. The user is given the flexibility to use a wide
range of output L and C filter components to suit the
particular application needs. Type
compensation can be employed using external
compensation components.
2 or type 3
The high-side and low-side drivers are designed with
300-mA source and sink capability to quickly drive the
power MOSFETs gates. The low-side driver is supplied
from VIN, while the high-side drive is supplied from the
BOOT pin. A bootstrap circuit uses an external BOOT
capacitor and an internal 2.5-Ω bootstrap switch
connected between the VIN and BOOT pins. The
integrated bootstrap switch improves drive efficiency and
reduces external component count.
PWM CONTROL
Signals from the error amplifier output, oscillator, and
current limit circuit are processed by the PWM control
logic. Referring to the internal block diagram, the control
logic includes the PWM comparator, OR gate, PWM latch,
and portions of the adaptive dead-time and control logic
block. During steady-state operation below the current
limit threshold, the PWM comparator output and oscillator
pulse train alternately reset and set the PWM latch. Once
the PWM latch is reset, the low-side FET remains on for a
minimum duration set by the oscillator pulse width. During
this period, the PWM ramp discharges rapidly to its valley
voltage. When the ramp begins to charge back up, the
low-side FET turns off and high-side FET turns on. As the
PWM ramp voltage exceeds the error amplifier output
voltage, the PWM comparator resets the latch, thus
turning off the high-side FET and turning on the low-side
FET. The low-side FET remains on until the next oscillator
pulse discharges the PWM ramp.
OVERCURRENT PROTECTION
The cycle-by-cycle current limiting is achieved by sensing
the current flowing through the high-side MOSFET and
comparing this signal to a preset overcurrent threshold.
The high side MOSFET is turned off within 200 ns of
reaching the current limit threshold. A 100-ns leading edge
blanking circuit prevents current limit false tripping.
Current limit detection occurs only when current flows from
VIN to PH when sourcing current to the output filter. Load
protection during current sink operation is provided by
thermal shutdown.
THERMAL SHUTDOWN
During transient conditions, the error amplifier output
could be below the PWM ramp valley voltage or above the
PWM peak voltage. If the error amplifier is high, the PWM
latch is never reset, and the high-side FET remains on until
the oscillator pulse signals the control logic to turn the
high-side FET off and the low-side FET on. The device
operates at its maximum duty cycle until the output voltage
rises to the regulation set-point, setting VSENSE to
approximately the same voltage as VREF. If the error
amplifier output is low, the PWM latch is continually reset
and the high-side FET does not turn on. The low-side FET
remains on until the VSENSE voltage decreases to a
range that allows the PWM comparator to change states.
The TPS54610 is capable of sinking current continuously
until the output reaches the regulation set-point.
The device uses the thermal shutdown to turn off the power
MOSFETs and disable the controller if the junction
temperature exceeds 150°C. The device is released from
shutdown automatically when the junction temperature
decreases to 10°C below the thermal shutdown trip point,
and starts up under control of the slow-start circuit.
Thermal shutdown provides protection when an overload
condition is sustained for several milliseconds. With a
persistent fault condition, the device cycles continuously;
starting up by control of the soft-start circuit, heating up due
to the fault condition, and then shutting down upon
reaching the thermal shutdown trip point. This sequence
repeats until the fault condition is removed.
POWER-GOOD (PWRGD)
If the current limit comparator trips for longer than 100 ns,
the PWM latch resets before the PWM ramp exceeds the
error amplifier output. The high-side FET turns off and
low-side FET turns on to decrease the energy in the output
inductor and consequently the output current. This
process is repeated each cycle in which the current limit
comparator is tripped.
The power good circuit monitors for under voltage
conditions on VSENSE. If the voltage on VSENSE is 10%
below the reference voltage, the open-drain PWRGD
output is pulled low. PWRGD is also pulled low if VIN is
less than the UVLO threshold or SS/ENA is low, or a
thermal shutdown occurs. When VIN ≥ UVLO threshold,
SS/ENA ≥ enable threshold, and VSENSE > 90% of V
the open drain output of the PWRGD pin is high. A
hysteresis voltage equal to 3% of V and a 35 µs falling
edge deglitch circuit prevent tripping of the power good
comparator due to high frequency noise.
,
ref
DEAD-TIME CONTROL AND MOSFET
DRIVERS
ref
Adaptive dead-time control prevents shoot-through
13
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PowerPADt PLASTIC SMALL−OUTLINE
PWP (R−PDSO−G28)
14
IMPORTANT NOTICE
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