TPS2HB50BQPWPRQ1 [TI]
具有可调节电流限制的 40V、50mΩ、2 通道汽车类智能高侧开关 | PWP | 16 | -40 to 125;
| 型号： | TPS2HB50BQPWPRQ1 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 具有可调节电流限制的 40V、50mΩ、2 通道汽车类智能高侧开关 | PWP | 16 | -40 to 125 开关 |
| 文件： | 总42页 (文件大小：1462K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
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TPS2HB50-Q1
ZHCSJN5A –FEBRUARY 2018–REVISED APRIL 2019
TPS2HB50-Q1 40V、50mΩ 双通道智能高侧开关
1 特性
3 说明
1
•
•
符合汽车类 应用要求
具有符合 AEC-Q100 标准的下列特性：
TPS2HB50-Q1 器件是一款适用于 12V 汽车系统的双
通道智能高侧开关。该器件集成了强大的保护和诊断
功能 ，以确保即使在汽车系统中发生短路等有害事件
时也能提供输出端口保护。该器件通过可靠的电流限制
来防止故障，根据器件型号不同，电流限制可调范围为
1.6A 至 18A。凭借较高的电流限制范围，该器件可用
于需要大瞬态电流的负载，而低电流限制范围可为不需
要高峰值电流的负载提供更好的保护。该器件能够可靠
地驱动各种负载分布。
–
器件温度等级 1：环境工作温度范围 TA =
–40°C 至
125°C
–
–
–
器件 HBM ESD 分类等级 2
器件 CDM ESD 分类等级 C4B
可承受 40V 负载突降
•
•
具有 50mΩ RON (TJ = 25°C) 的双通道智能高侧开
关
TPS2HB50-Q1 还能够提供可改进负载诊断的高精度模
拟电流检测。通过向系统 MCU 报告负载电流和器件温
度，该器件可实现预测性维护和负载诊断，从而延长系
统寿命。
通过可调电流限制提高系统级可靠性
–
电流限制可调范围为 1.6A 至 18A
•
强大的集成输出保护：
–
–
–
–
–
–
集成热保护
接地短路或电池短路保护
反向电池事件保护包括电压反向时自动启动
发生失电或接地失效时自动关闭
集成输出钳位对电感负载进行消磁
可配置故障处理
TPS2HB50-Q1 采用 HTSSOP 封装，可减小 PCB 尺
寸。
器件信息(1)
器件型号
封装
封装尺寸（标称值）
TPS2HB50-Q1
HTSSOP (16)
5.00mm × 4.40mm
•
•
可对模拟检测输出进行配置，以精确测量：
(1) 如需了解所有可用封装，请参阅数据表末尾的可订购产品附
录。
–
–
负载电流
器件温度
简化原理图
通过 SNS 引脚提供故障指示
开路负载和电池短路检测
VBAT /
Supply Voltage
–
DIA_EN
VBB
Bulbs
2 应用
SEL1
SEL2
•
•
•
信息娱乐显示屏
VOUT1
SNS
Relays/Motors
µC
ILIM1
ILIM2
LATCH
EN1
ADAS 模块
加热元件：
Power Module:
Cameras, Sensors
–
–
–
座椅加热器
VOUT2
EN2
General Resistive,
Capacitive, Inductive Loads
火花塞
GND
油箱加热器
•
•
•
•
变速器控制单元
HVAC 空调
车身控制模块
白炽灯和 LED 照明
1
本文档旨在为方便起见，提供有关 TI 产品中文版本的信息，以确认产品的概要。 有关适用的官方英文版本的最新信息，请访问 www.ti.com，其内容始终优先。 TI 不保证翻译的准确
性和有效性。 在实际设计之前，请务必参考最新版本的英文版本。
English Data Sheet: SLVSDZ5
TPS2HB50-Q1
ZHCSJN5A –FEBRUARY 2018–REVISED APRIL 2019
www.ti.com.cn
目录
9.2 Functional Block Diagram ....................................... 15
9.3 Feature Description................................................. 16
9.4 Device Functional Modes........................................ 27
10 Application and Implementation........................ 29
10.1 Application Information.......................................... 29
10.2 Typical Application ............................................... 32
11 Power Supply Recommendations ..................... 34
12 Layout................................................................... 34
12.1 Layout Guidelines ................................................. 34
12.2 Layout Example .................................................... 35
13 器件和文档支持 ..................................................... 36
13.1 文档支持 ............................................................... 36
13.2 接收文档更新通知 ................................................. 36
13.3 社区资源................................................................ 36
13.4 商标....................................................................... 36
13.5 静电放电警告......................................................... 36
13.6 术语表 ................................................................... 36
14 机械、封装和可订购信息....................................... 36
1
2
3
4
5
6
特性.......................................................................... 1
应用.......................................................................... 1
说明.......................................................................... 1
修订历史记录 ........................................................... 2
Device Comparison Table..................................... 3
Pin Configuration and Functions......................... 4
6.1 Recommended Connections for Unused Pins.......... 5
Specifications......................................................... 6
7.1 Absolute Maximum Ratings ...................................... 6
7.2 ESD Ratings.............................................................. 6
7.3 Recommended Operating Conditions....................... 6
7.4 Thermal Information.................................................. 7
7.5 Electrical Characteristics........................................... 7
7.6 SNS Timing Characteristics ...................................... 9
7.7 Switching Characteristics........................................ 10
Parameter Measurement Information ................ 13
Detailed Description ............................................ 14
9.1 Overview ................................................................. 14
7
8
9
4 修订历史记录
Changes from Original (February 2018) to Revision A
Page
•
对整篇数据表进行了更改 ........................................................................................................................................................ 1
2
Copyright © 2018–2019, Texas Instruments Incorporated
TPS2HB50-Q1
www.ti.com.cn
ZHCSJN5A –FEBRUARY 2018–REVISED APRIL 2019
5 Device Comparison Table
Table 1. TPS2HB50-Q1 Device Options
Device
Part Number
Current Limit
Current Limit Range
Overcurrent Behavior
Version
A
B
TPS2HB50A-Q1
TPS2HB50B-Q1
Resistor Programmable
Resistor Programmable
1.6 A - 8 A
Disable switch immediately
Disable switch immediately
3.6 A - 18 A
Copyright © 2018–2019, Texas Instruments Incorporated
3
TPS2HB50-Q1
ZHCSJN5A –FEBRUARY 2018–REVISED APRIL 2019
www.ti.com.cn
6 Pin Configuration and Functions
PWP Package
16-Pin HTSSOP
Top View
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
GND
SNS
DIA_EN
SEL2
LATCH
EN1
SEL1
EN2
VBB
ILIM1
ILIM2
VOUT1
VOUT1
VOUT1
VOUT2
VOUT2
VOUT2
Pin Functions
PIN
I/O
DESCRIPTION
NO.
NAME
GND
1
—
O
I
Device ground
Sense output
2
SNS
3
LATCH
EN1
Sets fault handling behavior (latched or auto-retry)
Channel 1 control input, active high
Connect pull-up resistor to VBB to set current-limit threshold on CH1
Channel 1 output
4
I
5
ILIM1
VOUT1
VOUT2
ILIM2
EN2
O
O
O
O
I
6-8
9-11
Channel 2 output
12
Connect pull-up resistor to VBB to set current-limit threshold on CH2
Channel 2 control input, active high
Diagnostics select 1
13
14
SEL1
SEL2
DIA_EN
VBB
I
15
I
Diagnostics select 2
16
I
Diagnostic enable, active high
Exposed pad
I
Power supply input
4
Copyright © 2018–2019, Texas Instruments Incorporated
TPS2HB50-Q1
www.ti.com.cn
ZHCSJN5A –FEBRUARY 2018–REVISED APRIL 2019
6.1 Recommended Connections for Unused Pins
The TPS2HB50-Q1 device is designed to provide an enhanced set of diagnostic and protection features.
However, if the system design only allows for a limited number of I/O connections, some pins may be considered
optional.
Table 2. Connections for Optional Pins
PIN NAME
CONNECTION IF NOT USED
Ground through 1-kΩ resistor Analog sense is not available.
With LATCH unused, the device will auto-retry after a fault. If latched
IMPACT IF NOT USED
SNS
Float or ground through
RPROT resistor
behavior is desired, but the system describes limited I/O, it is possible to
use one microcontroller output to control the latch function of several high-
side channels.
LATCH
If the ILIMx pin is left floating, the device will be set to the default internal
current-limit threshold.
ILIM1, ILIM2
SEL1
Float
Float or ground through
RPROT resistor
SEL1 selects the TJ sensing feature. With SEL1 unused, only CH1 and
CH2 current sensing and open load detection are available.
Ground through RPROT
resistor
With SEL2 = 0 V, CH2 current sensing and CH2 open load detection are
not available.
SEL2
Float or ground through
RPROT resistor
With DIA_EN unused, the analog sense, open-load, and short-to-battery
diagnostics are not available.
DIA_EN
RPROT is used to protect the pins from excess current flow during reverse battery conditions, for more information
please see the section on Reverse Battery protection.
Copyright © 2018–2019, Texas Instruments Incorporated
5
TPS2HB50-Q1
ZHCSJN5A –FEBRUARY 2018–REVISED APRIL 2019
www.ti.com.cn
7 Specifications
7.1 Absolute Maximum Ratings
Over operating free-air temperature range (unless otherwise noted)(1)
MIN
MAX
UNIT
V
Maximum continuous supply voltage, VBB
36
40
Load dump voltage, VLD
ISO16750-2:2010(E)
V
Reverse battery voltage, VRev, t ≤ 3 minutes
Enable pin voltage, VEN1 and VEN2
LATCH pin voltage, VLATCH
–18
–1
–1
–1
–1
–1
V
7
7
V
V
Diagnostic Enable pin voltage, VDIA_EN
Sense pin voltage, VSNS
7
V
18
7
V
Select pin voltage, VSEL1 and VSEL2
Reverse ground current, IGND
V
VBB < 0 V
–50
mA
Single pulse, one channel, LOUT = 5 mH,
TJ,start = 125°C
Energy dissipation during turnoff, ETOFF
Energy dissipation during turnoff, ETOFF
TBD(2)
TBD(2)
mJ
mJ
Repetitive pulse, one channel, LOUT = 5 mH,
TJ,start = 125°C
Maximum junction temperature, TJ
Maximum junction temperature - limited duration, TJ
Storage temperature, Tstg
150
170
150
°C
°C
°C
t < 100 hours
–65
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute maximum rated conditions for extended periods may affect device reliability.
(2) For further details, see the section regarding switch-off of an inductive load.
7.2 ESD Ratings
VALUE
UNIT
All pins except VBB and
VOUTx
±2000
Human-body model (HBM), per AEC Q100-002(1)
Charged-device model (CDM), per AEC Q100-011
Electrostatic
discharge
V(ESD)
V
VBB and VOUTx
All pins
±4000
±750
(1) AEC-Q100-002 indicates that HBM stressing shall be in accordance with the ANSI/ESDA/JEDEC JS-001 specifications.
7.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
(1)
MIN
6
MAX
18
UNIT
(1)
VBB
VBB
Nominal supply voltage
V
V
Extended supply voltage(2)
3
28
VEN1
VEN2
,
Enable voltage
–1
5.5
V
VLATCH
VDIA_EN
LATCH voltage
–1
–1
5.5
5.5
V
V
Diagnostic Enable voltage
VSEL1
VSEL2
,
Select voltage
–1
5.5
V
VSNS
TA
Sense voltage
–1
7
V
Operating free-air temperature
–40
125
°C
(1) All operating voltage conditions are measured with respect to device GND
(2) Device will function within extended operating range, however some parametric values might not apply
6
Copyright © 2018–2019, Texas Instruments Incorporated
TPS2HB50-Q1
www.ti.com.cn
ZHCSJN5A –FEBRUARY 2018–REVISED APRIL 2019
7.4 Thermal Information
TPS2HB50-Q1
THERMAL METRIC(1)(2)
PWP (HTSSOP)
UNIT
16 PINS
32.9
30.8
9.0
RθJA
Junction-to-ambient thermal resistance
Junction-to-case (top) thermal resistance
Junction-to-board thermal resistance
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
RθJC(top)
RθJB
ψJT
Junction-to-top characterization parameter
Junction-to-board characterization parameter
Junction-to-case (bottom) thermal resistance
1.8
ψJB
9.2
RθJC(bot)
2.0
(1) For more information about traditional and new thermal metrics, see TI's SPRA953 application report.
(2) The thermal parameters are based on a 4-layer PCB according to the JESD51-5 and JESD51-7 standards.
7.5 Electrical Characteristics
VBB = 6 V to 18 V, TJ = -40°C to 150°C (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
INPUT VOLTAGE AND CURRENT
VDSCLAMP VDS clamp voltage
38
58
46
76
V
V
VBBCLAMP
VUVLOF
VUVLOR
VBB clamp voltage
VBB undervoltage lockout
falling
Measured with respect to the GND pin of the device
Measured with respect to the GND pin of the device
2.0
2.2
3
3
V
V
VBB undervoltage lockout
rising
VBB = 13.5 V, TJ = 25°C
VENx = VDIA_EN = 0 V, VOUT = 0 V
0.5
4
µA
µA
Standby current (total
device leakage including
both MOSFET channels)
ISB
VBB = 13.5 V, TJ = 125°C,
VENx = VDIA_EN = 0 V, VOUT = 0 V
Two channels enabled, TAMB = 70°C
One channel enabled, TAMB = 70°C
3
A
A
Continuous load current,
per channel
ILNOM
4.5
VBB = 13.5 V, TJ = 25°C
VENx = VDIA_EN = 0 V, VOUT = 0 V
0.01
0.5
1.5
6
µA
µA
Output leakage current
(per channel)
IOUT(standby)
VBB = 13.5 V, TJ = 125°C
VENx = VDIA_EN = 0 V, VOUT = 0 V
VBB = 13.5 V, ISNS = 0 mA
VENx = 0 V, VDIA_EN = 5 V, VOUT = 0V
Current consumption in
diagnostic mode
IDIA
3
mA
VBB = 13.5 V
VENx = VDIA_EN = 5 V, IOUTx = 0 A
IQ
Quiescent current
3
6
mA
ms
tSTBY
Standby mode delay time VENx = VDIA_EN = 0 V to standby
12
17
22
RON CHARACTERISTICS
TJ = 25°C, 6 V ≤ VBB ≤ 28 V, IOUT1 = IOUT2 > 1 A
TJ = 150°C, 6 V ≤ VBB ≤ 28 V, IOUT1 = IOUT2 > 1 A
TJ = 25°C, 3 V ≤ VBB ≤ 6 V, IOUT1 = IOUT2 > 1 A
TJ = 25°C, -18 V ≤ VBB ≤ -7 V
50
50
mΩ
mΩ
mΩ
mΩ
mΩ
On-resistance
(Includes MOSFET and
package)
RON
100
75
On-resistance during
reverse polarity
RON(REV)
TJ = 105°C, -18 V ≤ VBB ≤ -7 V
100
CURRENT SENSE CHARACTERISTICS
Current sense ratio
IOUTx / ISNS
KSNS
IOUTX = 1 A
1500
Copyright © 2018–2019, Texas Instruments Incorporated
7
TPS2HB50-Q1
ZHCSJN5A –FEBRUARY 2018–REVISED APRIL 2019
www.ti.com.cn
Electrical Characteristics (continued)
VBB = 6 V to 18 V, TJ = -40°C to 150°C (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
–4%
TYP
MAX
UNIT
mA
%
4.000
IOUT = 6 A
4%
4%
2.000
0.667
0.2
mA
%
IOUT = 3 A
–4%
mA
%
IOUT = 1 A
–4%
4%
Current sense current
and accuracy
VEN = VDIA_EN = 5 V,
VSEL1 = 0 V, VSEL2 = X
ISNSI
mA
%
IOUT = 300 mA
IOUT = 100 mA
IOUT = 50 mA
–10%
–25%
–35%
10%
25%
35%
0.067
0.033
mA
%
mA
%
TJ SENSE CHARACTERISTICS
TJ = -40°C
TJ = 25°C
TJ = 85°C
TJ = 125°C
TJ = 150°C
0.00
0.68
1.25
1.61
1.80
0.12
0.85
1.52
1.96
2.25
0.011
0.29
1.02
1.79
2.31
2.70
mA
mA
Temperature sense
current
VDIA_EN = 5 V, VSEL1 = 5
V, VSEL2 = 0 V
ISNST
mA
mA
mA
dISNST/dT
Coefficient
mA/°C
SNS CHARACTERISTICS
ISNSFH
ISNS fault high-level
ISNS leakage
VDIA_EN = 5 V, VSEL1 = 0 V, VSEL2 = X
VDIA_EN = 0 V
4
4.5
5.3
1
mA
µA
ISNSleak
CURRENT LIMIT CHARACTERISTICS
RILIM = GND, open, or
11.8
A
out of range
RILIM = 5 kΩ
RILIM = 25 kΩ
Device Version A, TJ =
-40°C to 150°C
6.2
1.4
8
9.36
2.28
A
A
1.6
ICL
Current Limit Threshold
Current Limit Ratio
RILIM = GND, open, or
out of range
27
A
Device Version B, TJ =
-40°C to 150°C
RILIM = 5 kΩ
13.68
2.96
31
18
3.6
40
21.6
4.44
A
A
RILIM = 25 kΩ
Version A
Version B
57 A * kΩ
KCL
68.4
90
111 A * kΩ
FAULT CHARACTERISTICS
Open-load (OL) detection
voltage
VOL
tOL1
tOL2
VENx = 0 V, VDIA_EN = 5 V
2
3
4
700
50
V
VENx = 5 V to 0 V, VDIA_EN = 5 V, VSEL1 = 0 V(1)
IOUT = 0 mA, VOUTx = 4 V
VENx = 0 V, VDIA_EN = 0 V to 5 V, VSEL1 = 0 V(1)
IOUT = 0 mA, VOUTx = 4 V
OL and STB indication-
time from ENx falling
300
500
µs
µs
OL and STB indication-
time from DIA_EN rising
VENx = 0 V, VDIA_EN = 5 V, VSEL1 = 0 V(1)
IOUT = 0 mA, VOUTx = 0 V to 4 V
OL and STB indication-
time from VOUT rising
tOL3
50
µs
°C
°C
TABS
TREL
Thermal shutdown
150
Relative thermal
shutdown
50
28
Thermal shutdown
hysteresis
THYS
°C
(1) SELx must be set to select the relevant channel. Diagnostics are performed on Channel 1 when SELx = 00 and diagnostics are
performed on channel 2 when SELx =01
8
Copyright © 2018–2019, Texas Instruments Incorporated
TPS2HB50-Q1
www.ti.com.cn
ZHCSJN5A –FEBRUARY 2018–REVISED APRIL 2019
Electrical Characteristics (continued)
VBB = 6 V to 18 V, TJ = -40°C to 150°C (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
VDIA_EN = 5 V
Time between switch shutdown and ISNS settling at
ISNSFH
Fault shutdown
indication-time
tFAULT
50
µs
Time from fault shutdown until switch re-enable
(thermal shutdown or current limit).
tRETRY
Retry time
1
2
3
ms
EN1 AND EN2 PIN CHARACTERISTICS(2)
VIL, ENx
VIH, ENx
Input voltage low-level
Input voltage high-level
No GND network diode
No GND network diode
0.8
V
V
2
VIHYS, ENx Input voltage hysteresis
350
1
mV
MΩ
µA
µA
RENx
Internal pulldown resistor
Input current low-level
Input current high-level
0.5
2
IIL, EN
IIH, EN
VEN = 0.8 V
VEN = 5 V
0.8
5
DIA_EN PIN CHARACTERISTICS(2)
VIL, DIA_EN Input voltage low-level
VIH, DIA_EN Input voltage high-level
No GND network diode
No GND network diode
0.8
V
V
2.0
200
0.5
VIHYS,
DIA_EN
Input voltage hysteresis
350
530
2
mV
RDIA_EN
Internal pulldown resistor
Input current low-level
Input current high-level
1
0.8
5
MΩ
µA
µA
IIL, DIA_EN
IIH, DIA_EN
VDIA_EN = 0.8 V
VDIA_EN = 5 V
SEL1 AND SEL2 PIN Characteristics
VIL, SELx
VIH, SELx
Input voltage low-level
Input voltage high-level
No GND network diode
No GND network diode
0.8
2
V
V
2
VIHYS, SELx Input voltage hysteresis
350
1
mV
MΩ
µA
µA
RSELx
Internal pulldown resistor
Input current low-level
Input current high-level
0.5
IIL, SELX
IIH, SELX
VSELX = 0.8 V
VSELX = 5 V
0.8
5
LATCH PIN CHARACTERISTICS(2)
VIL, LATCH Input voltage low-level
No GND network diode
No GND network diode
0.8
V
V
VIH, LATCH Input voltage high-level
2
200
0.5
VIHYS,
LATCH
Input voltage hysteresis
350
530
2
mV
RLATCH
Internal pulldown resistor
Input current low-level
Input current high-level
1
0.8
5
MΩ
µA
µA
IIL, LATCH
IIH, LATCH
VLATCH = 0.8 V
VLATCH = 5 V
(2) VBB = 3 V to 28 V
7.6 SNS Timing Characteristics
VBB = 6 V to 18 V, TJ = -40°C to +150°C (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
SNS TIMING - CURRENT SENSE
VENx = 5 V, VDIA_EN = 0 V to 5 V
RSNS = 1 kΩ, RL ≤ 6 Ω
tSNSION1
tSNSION2
tSNSION3
Settling time from rising edge of DIA_EN
40
165
165
µs
µs
µs
VENx = VDIA_EN = 0 V to 5 V
RSNS = 1 kΩ, RL ≤ 6 Ω
Settling time from rising edge of ENx and
DIA_EN
VENx = 0 V to 5 V, VDIA_EN = 5 V
RSNS = 1 kΩ, RL ≤ 6 Ω
Settling time from rising edge of ENx
Copyright © 2018–2019, Texas Instruments Incorporated
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TPS2HB50-Q1
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SNS Timing Characteristics (continued)
VBB = 6 V to 18 V, TJ = -40°C to +150°C (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
VENx = 5 V, VDIA_EN = 5 V to 0 V
RSNS = 1 kΩ, RL ≤ 6 Ω
tSNSIOFF1
tSETTLEH
tSETTLEL
Settling time from falling edge of DIA_EN
20
20
20
µs
VEN1 = 5 V, VDIA_EN = 5 V
RSNS = 1 kΩ, IOUT = 5 A to 1 A
Settling time from rising edge of load step
Settling time from falling edge of load step
µs
µs
VENx = 5 V, VDIA_EN = 5 V
RSNS = 1 kΩ, IOUT = 5 A to 1 A
SNS TIMING - TEMPERATURE SENSE
VENx = 5 V, VDIA_EN = 0 V to 5 V
RSNS = 1 kΩ
tSNSTON1
tSNSTON2
tSNSTOFF
Settling time from rising edge of DIA_EN
40
70
20
µs
µs
µs
VENx = 0 V, VDIA_EN = 0 V to 5 V
RSNS = 1 kΩ
Settling time from rising edge of DIA_EN
Settling time from falling edge of DIA_EN
VENx = X, VDIA_EN = 5 V to 0 V
RSNS = 1 kΩ
SNS TIMING - MULTIPLEXER
VENx = X, VDIA_EN = 5 V
VSEL1 = 5 V to 0 V, VSEL2 = X
RSNS = 1 kΩ, RL ≤ 6 Ω
Settling time from temperature sense to
current sense
60
20
60
µs
µs
µs
VENx = X, VDIA_EN = 5 V
VSEL1 = 0 V, VSEL2 = 0 V to 5 V
RSNS = 1 kΩ, IOUT1 = 2 A, IOUT2 = 4 A
Settling time from current sense on CHx to
CHy
tMUX
VENx = X, VDIA_EN = 5 V
VSEL1 = 0 V to 5 V, VSEL2 = X
RSNS = 1 kΩ, RL ≤ 6 Ω
Settling time from current sense to
temperature sense
7.7 Switching Characteristics
VBB = 13.5 V, TJ = -40°C to +150°C (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
VBB = 13.5 V, RL ≤ 6 Ω, 50% EN
rising to 10% VOUT rising
tDR
Turnon delay time
20
60
60
100
100
0.7
µs
VBB = 13.5 V, RL ≤ 6 Ω, 50% EN
falling to 90% VOUT Falling
tDF
Turnoff delay time
VOUTx rising slew rate
VOUTx falling slew rate
Turnon time
20
0.1
0.1
39
µs
V/µs
V/µs
µs
VBB = 13.5 V, 20% to 80% of VOUT
,
SRR
SRF
tON
0.4
0.4
87
R
L ≤ 6 Ω
VBB = 13.5 V, 80% to 20% of VOUT
L ≤ 6 Ω
,
0.7
R
VBB = 13.5 V, RL ≤ 6 Ω, 50% EN
rising to 80% VOUT rising
145
VBB = 13.5 V, RL ≤ 6 Ω, 50% EN
rising to 80% VOUT rising
tOFF
Turnoff time
39
87
0
147
50
µs
µs
tON - tOFF
EON
Turnon and turnoff matching
200-µs enable pulse
–50
Switching energy losses during
turnon
VBB = 13.5 V, RL ≤ 6 Ω
0.4
mJ
Switching energy losses during
turnoff
EOFF
VBB = 13.5 V, RL ≤ 6 Ω
0.4
mJ
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(1)
VEN
50%
50%
90%
90%
tDR
tDF
VOUT
10%
10%
tON
tOFF
(1) Rise and fall time of VENx is 100 ns.
图 1. Switching Characteristics Definitions
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VEN1
VDIA_EN
IOUT1
ISNS
tSNSION1
tSNSION2
tSNSION3
tSNSIOFF1
VEN1
VDIA_EN
IOUT1
ISNS
tSETTLEH
tSETTLEL
VEN1
VDIA_EN
TJ
ISNS
tSNSTON1
tSNSTON2
tSNSTOFF
NOTE1: Rise and fall times of control signals are 100 ns. Control signals include: EN1, EN2, DIA_EN, SEL1, SEL2.
NOTE2: SEL1 and SEL2 must be set to the appropriate values.
图 2. SNS Timing Characteristics Definitions
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8 Parameter Measurement Information
图 3. Parameter Definitions
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9 Detailed Description
9.1 Overview
The TPS2HB50-Q1 device is a dual-channel smart high-side switch intended for use with 12-V automotive
batteries. Many protection and diagnostic features are integrated in the device.
Diagnostics features include the analog SNS output that is capable of providing a signal that is proportional to
load current or device temperature. The high-accuracy load current sense allows for diagnostics of complex
loads.
This device includes protection through thermal shutdown, current limiting, transient withstand, and reverse
battery operation. For more details on the protection features, refer to the Feature Description and Application
Information sections of the document.
The TPS2HB50-Q1 is one device in a family of TI high side switches. For each device, the part number indicates
elements of the device behavior. 图 4 gives an example of the device nomenclature.
图 4. Naming Convention
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9.2 Functional Block Diagram
VBB
VBB to GND
Clamp
Internal Power
Supply
VBB to VOUT
Clamp
GND
VOUT1
Gate Driver
EN1
EN2
Power FET
Channel 1/2
VOUT2
LATCH
ILIM1
Current Limit
Thermal
Shutdown
ILIM2
Open-load /
Short-to-Bat
Detection
DIA_EN
SEL1
SEL2
Fault Indication
SNS
SNS Mux
Current Sense
Temperature
Sense
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9.3 Feature Description
9.3.1 Protection Mechanisms
The TPS2HB50-Q1 is designed to operate in the automotive environment. The protection mechanisms allow the
device to be robust against many system-level events such as load dump, reverse battery, short-to-ground, and
more.
There are two protection features which, if triggered, will cause the switch to automatically disable:
•
•
Thermal Shutdown
Current Limit
When any of these protections are triggered, the device will enter the FAULT state. In the FAULT state, the fault
indication will be available on the SNS pin (see the Diagnostic Mechanisms section of the data sheet for more
details).
The switch is no longer held off and the fault indication is reset when all of the below conditions are met:
•
•
•
LATCH pin is low
tRETRY has expired
All faults are cleared (thermal shutdown, current limit)
注
CH1 and CH2 operate independently. If there is a fault on one channel, the other channel
is not affected.
9.3.1.1 Thermal Shutdown
The device includes a temperature sensor on each power FET and also within the controller portion of the
device. There are two cases that the device will consider to be a thermal shutdown fault:
•
•
TJ,FET > TABS
(TJ,FET – TJ,controller) > TREL
After the fault is detected, the relevant switch will turn off. Each channel is turned off based on the measurement
of temperature sensor for that channel. Therefore, if the thermal fault is detected on only one channel, the other
channel continues operation. If TJ,FET passes TABS, the fault is cleared when the switch temperature decreases
by the hysteresis value, THYS. If instead the TREL threshold is exceeded, the fault is cleared after TRETRY passes.
9.3.1.2 Current Limit
When IOUT reaches the current limit threshold, ICL, the channel will switch off immediately. The ICL value will vary
with slew rate and a fast current increase that occurs during a powered-on short circuit can temporarily go above
the specified ICL value. When the switch is in the FAULT state it will output an output current ISNSFH on the SNS
pin.
During a short circuit event, the device will hit the ICL value that is listed in the Electrical Characteristics table (for
the given device version and RILIM) and then turn the output off to protect the device. The device will register a
short circuit event when the output current exceeds ICL, however the measured maximum current may exceed
the ICL value due to the TPS2HB50-Q1 deglitch filter and turn-off time. The device is guaranteed to protect itself
during a short circuit event up to 24 V at 125°C.
9.3.1.2.1 Current Limit Foldback
Version B of the TPS2HB50-Q1 implements a current limit foldback feature that is designed to protect the device
in the case of a long-term fault condition. If the device undergoes fault shutdown events (either of thermal
shutdown or current limit) seven consecutive times, the current limit will be reduced to half of the original value.
The device will revert back to the original current limit threshold if either of the following occurs:
•
•
The device goes to standby mode.
The switch turns on and turns off without any fault occurring.
Version A does not implement the current limit foldback due to the lower current limit causing less harm during
repetitive long-term faults.
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Feature Description (接下页)
9.3.1.2.2 Programmable Current Limit
The TPS2HB50-Q1 includes an adjustable current limit. Some applications (for example, incandescent bulbs) will
require a high current limit. Other applications can benefit from a lower current limit threshold. In general,
wherever possible a lower current limit is recommended due to allowing system advantages through:
•
•
•
Reduced size and cost in current carrying components such as PCB traces and module connectors
Less disturbance at the power supply (VBB pin) during a short circuit event
Improved protection of the downstream load
To set the current limit threshold, connect a resistor from ILIM to VBB. The current limit threshold is determined by
Equation 1 (RILIM in kΩ):
ICL = KCL / RILIM
(1)
The RILIM range is between 5 kΩ and 25 kΩ. An RILIM resistor is required, however in the fault case where the pin
is floating, grounded, or outside of this range the current limit will default to an internal level that is defined in the
Specifications section of this document.
注
Capacitance on the ILIM pin can cause ILIM to go out of range during short circuit events.
For accurate current limiting, place RILIM near to the device with short traces to ensure <5
pF capacitance to GND on the ILIM pin.
9.3.1.2.3 Undervoltage Lockout (UVLO)
The device monitors the supply voltage VBB to prevent unpredicted behaviors in the event that the supply voltage
is too low. When the supply voltage falls down to VUVLOF, the output stage is shut down automatically. When the
supply rises up to VUVLOR, the device turns back on.
During an initial ramp of VBB from 0 V at a ramp rate slower than 1 V/ms, VEN pin will have to beBB held low until
VBB is above UVLO threshold (with respect to board ground) and the supply voltage to the device has reliably
reached above the UVLO condition. For best operation, ensure that V has risen above UVLO before setting the
VEN pin to high.
9.3.1.2.4 VBB During Short-to-Ground
When VOUT is shorted to ground, the module power supply (VBB) can have a transient decrease. This is caused
by the sudden increase in current flowing through the wiring harness cables. To achieve ideal system behavior, it
is recommended that the module maintain VBB > 3 V (above the maximum VUVLOF) during VOUT short-to-ground.
This is typically accomplished by placing bulk capacitance on the power supply node.
9.3.1.3 Voltage Transients
The TPS2HB50-Q1 device describes two types of voltage clamps which protect the FET against system-level
voltage transients. The two different clamps are shown in 图 5.
The clamp from VBB to GND is primarily used to protect the controller from positive transients on the supply line
(for example, ISO7637-2). The clamp from VBB to VOUT is primarily used to limit the voltage across the FET when
switching off an inductive load. If the voltage potential from VBB to GND exceeds the VBB clamp level, the clamp
will allow current to flow through the device from VBB to GND (Path 2). If the voltage potential from VBB to VOUT
exceeds the clamping voltage, the power FET will allow current to flow from VBB to VOUT (Path 3). Additional
capacitance from VBB to GND can increase the reliability of the system during ISO 7637 pulse 2A testing.
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Feature Description (接下页)
Ri
Positive Supply Transient
(e.g. ISO7637 pulse 2a/3b)
(1)
VBB
VDS
Clamp
(3)
(2)
Controller
VBB
Clamp
VOUT
Load
GND
图 5. Current Path During Supply Voltage Transient
9.3.1.3.1 Load Dump
The TPS2HB50-Q1 device is tested according to ISO 16750-2:2010(E) suppressed load dump pulse. The device
supports up to 40-V load dump transient and will maintain normal operation during the load dump pulse. If the
switch is enabled, it will stay enabled and if the switch is disabled, it will stay disabled.
9.3.1.4 Driving Inductive Loads
When switching off an inductive load, the inductor may impose a negative voltage on the output of the switch.
The TPS2HB50-Q1 includes a voltage clamp to limit voltage across the FET. The maximum acceptable load
inductance is a function of the device robustness.
For more information on driving inductive loads, refer to TI's How To Drive Inductive, Capacitive, and Lighting
Loads with Smart High Side Switches application report.
9.3.1.5 Reverse Battery
In the reverse battery condition, the switch will automatically be enabled regardless of the state of EN1/EN2 to
prevent excess power dissipation inside the MOSFET body diode. In many applications (for example, resistive
loads), the full load current may be present during reverse battery. In order to activate the automatic switch on
feature, the SEL2 pin must have a path to module ground. This may be path 1 as shown in 图 6, or if the SEL2
pin is unused, the path may be through RPROT to module ground.
Protection features like thermal shutdown are not available during a reverse battery event. Care must be taken to
ensure that excessive power is not dissipated in the switch during the reverse battery condition.
There are two options for blocking reverse current in the system. The first option is to place a blocking device
(FET or diode) in series with the battery supply, blocking all current paths. The second option is to place a
blocking diode in series with the GND node of the high-side switch. This method will protect the controller portion
of the switch (path 2), but it will not prevent current from flowing through the load (path 3). The diode used for the
second option may be shared amongst multiple high-side switches.
Path 1 shown in 图 6 is blocked inside of the device.
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Feature Description (接下页)
Reverse blocking
FET or diode
Option 1
BAT
VBB
0V
µC
VDD
(3)
(2)
Controller
VOUT
GPIO
GPIO
VBB
Clamp
Load
RPROT
(1)
GND
Option 2
图 6. Current Path During Reverse Battery
9.3.1.6 Fault Event – Timing Diagrams
注
All timing diagrams assume that the SELx pins are set to select the relevant channel.
The LATCH, DIA_EN, and ENx pins are controlled by the user. The timing diagrams
represent a possible use-case.
图 7 shows the immediate current limit switch off and the retry behavior of versions A and B of the device. As
shown, the switch will remain latched off until the LATCH pin is low.
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Feature Description (接下页)
µC
resets
the latch
LATCH
DIA_EN
ISNSFH
Current
Sense
Current
Sense
High-z
High-z
High-z
High-z
SNS
VOUTx
ENx
ICL
tRETRY
IOUTx
t
Switch follows ENx.
Normal operation.
Load reaches limit.
Switch is Disabled.
图 7. Current Limit – Version A and B - Latched Behavior
图 8 shows the immediate current limit switch off behavior of versions A and B. In this example, LATCH is tied to
GND; hence, the switch will retry after the fault is cleared and tRETRY has expired.
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Feature Description (接下页)
DIA_EN
ISNSFH
Current
Sense
Current
Sense
High-z
High-z
High-z
High-z
SNS
VOUTx
ENx
ICL
tRETRY
IOUTx
t
Switch follows ENx.
Normal operation.
Load reaches limit.
Switch is Disabled.
图 8. Current Limit – Version A and B - LATCH = 0
图 9 illustrates auto-retry behavior and provides a zoomed-in view of the fault indication during retry. When the
switch retries after a shutdown event, the SNS fault indication will remain at the fault state until VOUT has risen to
VBB – 1.8 V. Once VOUT has risen, the SNS fault indication is reset and current sensing is available. If there is a
short-to-ground and VOUT cannot rise, the SNS fault indication will remain indefinitely.
注
图 9 assumes that tRETRY has expired by the time that TJ reaches the hysteresis threshold.
LATCH = 0 V and DIA_EN = 5 V
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Feature Description (接下页)
ISNSFH
ISNSFH
ISNSFH
ISNSFH
SNS
VOUTx
ENx
TABS
THYS
TJ
t
ISNSFH
ISNSI
SNS
VBB t 1.8 V
VOUTx
ENx
TABS
THYS
TJ
t
图 9. Fault Indication During Retry
9.3.2 Diagnostic Mechanisms
9.3.2.1 VOUTx Short-to-Battery and Open-Load
The TPS2HB50-Q1 is capable of detecting short-to-battery and open-load events regardless of whether the
switch is turned on or off, however the two conditions use different methods.
9.3.2.1.1 Detection With Switch Enabled
When the switch is enabled, the VOUTx short-to-battery and open-load conditions can be detected by the current
sense feature. In both cases, the load current will be measured through the SNS pin as below the expected
value.
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Feature Description (接下页)
9.3.2.1.2 Detection With Switch Disabled
While the switch is disabled, if DIA_EN is high, an internal comparator will detect the condition of VOUT. If the
load is disconnected (open load condition) or there is a short to battery the VOUT voltage will be higher than the
open load threshold (VOL,off) and a fault is indicated on the SNS pin . An internal pull-up of 1 MΩ is in series with
an internal MOSFET switch, so no external component is required if only a completely open load must be
detected. However, if there is significant leakage or other current draw even when the load is disconnected, a
lower value pull-up resistor and switch can be added externally to set the VOUT voltage above the VOL,off during
open load conditions.
(1) This figure assumes that the device ground and the load ground are at the same potential. In a real system, there
may be a ground shift voltage of 1 V to 2 V.
图 10. Short to Battery and Open Load Detection
The detection circuitry is only enabled when DIA_EN = HIGH and EN = LOW. If VOUT > VOL, the SNS pin will go
to the fault level, but if VOUT < VOL there will be no fault indication. The fault indication will only occur if the SEL1
pin is set to diagnose the respective channel.
While the switch is disabled and DIA_EN is high, the fault indication mechanisms will continuously represent the
present status. For example, if VOUT decreases from greater than VOL to less than VOL, the fault indication is
reset. Additionally, the fault indication is reset upon the falling edge of DIA_EN or the rising edge of EN.
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Feature Description (接下页)
DIA_EN
ISNSFH
High-z
High-z
SNS
tOL2
Enabled
VOUT depends on external conditions
VOL
VOUT
EN
t
Switch is disabled and DIA_EN goes
high.
The condition is determined by the
internal comparator.
The open-load fault is
indicated.
Device standby
图 11. Open Load
9.3.2.2 SNS Output
The SNS output may be used to sense the load current or device temperature. The SELx pins will select the
desired sense signal. The sense circuit will provide a current that is proportional to the selected parameter. This
current will be sourced into an external resistor to create a voltage that is proportional to the selected parameter.
This voltage may be measured by an ADC or comparator.
To ensure accurate sensing measurement, the sensing resistor should be connected to the same ground
potential as the μC ADC.
表 3. Analog Sense Transfer Function
PARAMETER
Load current
TRANSFER FUNCTION
ISNSI = IOUT / KSNS (1500)
Device temperature
ISNST = (TJ – 25°C) × dISNST / dT + 0.85
The SNS output will also be used to indicate system faults. ISNS will go to the predefined level, ISNSFH, when there
is a fault. ISNSFH, dISNST/dT, and KSNS are defined in the Specifications section.
9.3.2.2.1 RSNS Value
The following factors should be considered when selecting the RSNS value:
•
Current sense ratio (KSNS)
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•
•
•
Largest and smallest diagnosable load current required for application operation
Full-scale voltage of the ADC
Resolution of the ADC
For an example of selecting RSNS value, reference Selecting the RSNS Value in the applications section of this
datasheet.
9.3.2.2.1.1 High Accuracy Load Current Sense
In many automotive modules, it is required that the high-side switch provide diagnostic information about the
downstream load. With more complex loads, high accuracy sensing is required. A few examples follow:
•
LED lighting: In many architectures, the body control module (BCM) must be compatible with both
incandescent bulbs and also LED modules. The bulb may be relatively simple to diagnose. However, the LED
module will consume less current and also can include multiple LED strings in parallel. The same BCM is
used in both cases, so the high-side switch can accurately diagnose both load types.
•
Solenoid protection: Often solenoids are precisely controlled by low-side switches. However, in a fault
event, the low-side switch cannot disconnect the solenoid from the power supply. A high-side switch can be
used to continuously monitor several solenoids. If the system current becomes higher than expected, the
high-side switch can disable the module.
9.3.2.2.1.2 SNS Output Filter
To achieve the most accurate current sense value, it is recommended to filter the SNS output. There are two
methods of filtering:
•
Low-Pass RC filter between the SNS pin and the ADC input. This filter is illustrated in 图 15 with typical
values for the resistor and capacitor. The designer should select a CSNS capacitor value based on system
requirements. A larger value will provide improved filtering but a smaller value will allow for faster transient
response.
•
The ADC and microcontroller can also be used for filtering. It is recommended that the ADC collects several
measurements of the SNS output. The median value of this data set should be considered as the most
accurate result. By performing this median calculation, the microcontroller can filter out any noise or outlier
data.
9.3.2.3 Fault Indication and SNS Mux
The following faults will be communicated through the SNS output:
•
Switch shutdown, due to:
–
–
Thermal Shutdown
Current limit
•
Open-Load / VOUT shorted-to-battery
Open-load / Short-to-battery are not indicated while the switch is enabled, although these conditions can still be
detected through the sense current. Hence, if there is a fault indication corresponding to an enabled channel,
then it must be either due to an over-current or over-temperature event.
The SNS pin will only indicate the fault if the SELx pins are selecting the relevant channel. When the device is
set to measure temperature, the pin will be measuring the temperature of whichever channel is at a higher
temperature.
表 4. Version A/B SNS Mux
INPUTS
OUTPUTS
SNS
DIA_EN
SEL1
SEL2
FAULT DETECT(1)
0
1
1
1
X
0
0
1
X
0
1
0
X
0
0
0
High-Z
CH1 current
CH2 current
Device temperature
(1) Fault Detect encompasses multiple conditions:
(a) Switch shutdown and waiting for retry
(b) Open Load / Short To Battery
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表 4. Version A/B SNS Mux (接下页)
INPUTS
OUTPUTS
DIA_EN
SEL1
SEL2
FAULT DETECT(1)
SNS
1
1
1
1
1
1
0
0
1
1
1
0
1
0
1
0
1
1
1
1
N/A
ISNSFH
ISNSFH
Device temperature
N/A
9.3.2.4 Resistor Sharing
Multiple high-side channels may use the same SNS resistor as shown in the figure below. This reduces the total
number of passive components in the system and the number of ADC terminals that are required of the
microcontroller.
Microcontroller
GPIO
GPIO
GPIO
DIA_EN
DIA_EN
DIA_EN
DIA_EN
Switch 1
Switch 2
Switch 3
Switch 4
SNS
SNS
SNS
SNS
GPIO
ADC
RPROT
CSNS
RSNS
图 12. Sharing RSNS Among Multiple Devices
9.3.2.5 High-Frequency, Low Duty-Cycle Current Sensing
Some applications will operate with a high-frequency, low duty-cycle PWM or require fast settling of the SNS
output. For example, a 250 Hz, 5% duty cycle PWM will have an on-time of only 200 µs that must be
accommodated. The micro-controller ADC may sample the SNS signal after the defined settling time tSNSION3
.
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DIA_EN
ENx
IOUT
SNS
t
t
SNSION3
图 13. Current Sensing in Low-Duty Cycle Applications
9.4 Device Functional Modes
During typical operation, the TPS2HB50-Q1 can operate in a number of states that are described below and
shown as a state diagram in 图 14.
9.4.1 Off
Off state occurs when the device is not powered.
9.4.2 Standby
Standby state is a low-power mode used to reduce power consumption to the lowest level. Diagnostic
capabilities are not available in Standby mode.
9.4.3 Diagnostic
Diagnostic state may be used to perform diagnostics while the switches are disabled.
9.4.4 Standby Delay
The Standby Delay state is entered when EN1, EN2, and DIA_EN are low. After tSTBY, if the ENx and DIA_EN
pins are still low, the device will go to Standby State.
9.4.5 Active
In Active state, one or more of the switches are enabled. The diagnostic functions may be turned on or off during
Active state.
9.4.6 Fault
The Fault state is entered if a fault shutdown occurs (thermal shutdown or current limit). After all faults are
cleared, the LATCH pin is low, and the retry timer has expired, the device will transition out of Fault state. If the
relevant ENx pin is high, the switch will re-enable. If the relevant ENx pin is low, the switch will remain off.
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Device Functional Modes (接下页)
VBB < UVLO
OFF
ANY STATE
VBB > UVLO
EN1 & EN2 = Low
DIA_EN = Low
t > tSTBY
STANDBY
EN1 & EN2 = Low
DIA_EN = High
EN1 & EN2 = Low
DIA_EN = Low
STANDBY
DELAY
EN1 || EN2 = High
DIA_EN = X
DIAGNOSTIC
EN1 & EN2 = Low
DIA_EN = High
EN1 & EN2 = Low
DIA_EN = High
EN1 || EN2 = High
DIA_EN = X
ACTIVE(1)
EN1 & EN2 = Low
DIA_EN = Low
EN1 || EN2 = High
DIA_EN = X
!OT_ABS & !OT_REL & !ILIM
& LATCH = Low & tRETRY
expired
OT_ABS || OT_REL
|| ILIM
FAULT(1)
(1) CH1 and CH2 operate independently. Each channel is enabled/disabled independently. Also, if there is a fault on one
channel, the other channel is not affected.
图 14. State Diagram
28
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10 Application and Implementation
注
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
10.1 Application Information
图 15 shows the schematic of a typical application for the TPS2HB50-Q1. It includes all standard external
components. This section of the datasheet discusses the considerations in implementing commonly required
application functionality.
VBB
DIA_EN
SEL1
RPROT
RPROT
RPROT
RPROT
RPROT
CVBB
BAT
GND
SEL2
EN1
RGND
DGND
(1)
(1)
EN2
Load
VOUT1
VOUT2
Microcontroller
LATCH
COUT
COUT
RPROT
VBB
RILIM1
Load
ILIM1
VBB
RILIM2
ILIM2
SNS
Legend
ADC
Chassis GND
Module GND
Device GND
RPROT
RSNS
CSNS
(1) With the ground protection network, the device ground will be offset relative to the microcontroller ground.
图 15. System Diagram
表 5. Recommended External Components
COMPONENT
RPROT
TYPICAL VALUE
15 kΩ
PURPOSE
Protect microcontroller and device I/O pins
RSNS
1 kΩ
Translate the sense current into sense voltage
Low-pass filter for the ADC input
CSNS
100 pF - 10 nF
4.7 kΩ
RGND
Stabilize GND potential during turn-off of inductive load
Protects device during reverse battery
DGND
BAS21 Diode
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Application Information (接下页)
表 5. Recommended External Components (接下页)
COMPONENT
TYPICAL VALUE
PURPOSE
RILIM
5 kΩ - 25 kΩ
Set current limit threshold
Filtering of voltage transients (for example, ESD, ISO7637-2) and improved
emissions
220 nF to Device GND
CVBB
100 nF to Module GND Stabilize the input supply and filter out low frequency noise.
COUT
CGND
22 nF
Filtering of voltage transients (for example, ESD, ISO7637-2)
1 µF from Device GND to
Module GND
Optional capacitance to help with RF immunity.
10.1.1 Ground Protection Network
As discussed in the Reverse Battery section, DGND may be used to prevent excessive reverse current from
flowing into the device during a reverse battery event. Additionally, RGND is placed in parallel with DGND if the
switch is used to drive an inductive load. The ground protection network (DGND and RGND) may be shared
amongst multiple high-side switches.
A minimum value for RGND may be calculated by using the absolute maximum rating for IGND. During the reverse
battery condition, IGND = VBB / RGND
:
RGND ≥ VBB / IGND
•
•
Set VBB = –13.5 V
Set IGND = –50 mA (absolute maximum rating)
RGND ≥ –13.5 V / –50 mA = 270 Ω
(2)
In this example, it is found that RGND must be at least 270 Ω. It is also necessary to consider the power
dissipation in RGND during the reverse battery event:
PRGND = VBB2 / RGND
(3)
PRGND = (13.5 V)2 / 270 Ω = 0.675 W
In practice, RGND may not be rated for such a high power. In this case, a larger resistor value should be selected.
10.1.2 Interface With Microcontroller
The ground protection network will cause the device ground to be at a higher potential than the module ground
(and microcontroller ground). This offset will impact the interface between the device and the microcontroller.
Logic pin voltage will be offset by the forward voltage of the diode. For input pins (for example, EN1), the
designer must consider the VIH specification of the switch and the VOH specification of the microcontroller. For a
system that does not include DGND, it is required that VOH > VIH. For a system that does include DGND, it is
required that VOH > (VIH + VF). VF is the forward voltage of DGND
.
The sense resistor, RSNS, should be terminated to the microcontroller ground. In this case, the ADC can
accurately measure the SNS signal even if there is an offset between the microcontroller ground and the device
ground.
10.1.3 I/O Protection
RPROT is used to protect the microcontroller I/O pins during system-level voltage transients such as ISO pulses or
reverse battery. The SNS pin voltage can exceed the ADC input pin maximum voltage if the fault or saturation
current causes a high enough voltage drop across the sense resistor. If that can occur in the design (for
example, by switching to a high value RSNS to improve ADC input level), then an appropriate external clamp has
to be designed to prevent a high voltage at the SNS output and the ADC input.
10.1.4 Inverse Current
Inverse current occurs when 0 V < VBB < VOUTx. In this case, current may flow from VOUTx to VBB. Inverse current
cannot be caused by a purely resistive load. However, a capacitive or inductive load can cause inverse current.
For example, if there is a significant amount of load capacitance and the VBB node has a transient droop, VOUTx
may be greater than VBB
.
30
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The TPS2HB50-Q1 will not detect inverse current. When the switch is enabled, inverse current will pass through
the switch. When the switch is disabled, inverse current may pass through the MOSFET body diode. The device
will continue operating in the normal manner during an inverse current event.
10.1.5 Loss of GND
The ground connection may be lost either on the device level or on the module level. If the ground connection is
lost, both switches will be disabled. If the switch was already disabled when the ground connection was lost, the
switch will remain disabled. When the ground is reconnected, normal operation will resume.
10.1.6 Automotive Standards
The TPS2HB50-Q1 is designed to be protected against all relevant automotive standards to ensure reliable
operations when connected to a 12-V automotive battery.
10.1.6.1 ISO7637-2
The TPS2HB50-Q1 is tested according to the ISO7637-2:2011 (E) standard. The test pulses are applied both
with the switches enabled and disabled. The test setup includes only the DUT and minimal external components:
CVBB, COUT, DGND, and RGND
.
Status II is defined in ISO 7637-1 Function Performance Status Classification (FPSC) as: “The function does not
perform as designed during the test but returns automatically to normal operation after the test”. See 表 6 for
ISO7637-2:2011 (E) expected results.
表 6. ISO7637-2:2011 (E) Results
TEST PULSE SEVERITY LEVEL WITH
STATUS II FUNCTIONAL PERFORMANCE
MINIMUM NUMBER
OF PULSES OR TEST
TIME
BURST CYCLE / PULSE REPETITION TIME
TEST
PULSE
LEVEL
US
MIN
0.5 s
0.20
MAX
--
1
2a(1)
2b
III
III
IV
IV
IV
–112 V
+55 V
+10 V
–220 V
+150 V
500 pulses
500 pulses
10 pulses
1 hour
5 s
0.5 s
90 ms
90 ms
5 s
3a
100 ms
100 ms
3b
1 hour
(1) 1 µF capacitance on CVBB is required for passing level 3 ISO7637 pulse 2A.
10.1.6.2 AEC – Q100-012 Short Circuit Reliability
The TPS2HB50-Q1 is tested according to the AEC-Q100-012 Short Circuit Reliability standard. This test is
performed to demonstrate the robustness of the device against VOUT short-to-ground events. Test conditions and
test procedures are summarized in 表 7. For further details, refer to the AEC - Q100-012 standard document.
Test conditions:
•
•
•
•
•
LATCH = 0 V
ILIM = 5 kΩ
10 units from 3 separate lots for a total of 30 units.
Lsupply = 5 μH, Rsupply = 10 mΩ
VBB = 14 V
Test procedure:
•
•
•
Parametric data is collected on each unit pre-stress
Each unit is enabled into a short-circuit with the required short circuit cycles or duration as specified
Functional testing is performed on each unit post-stress to verify that the part still operates as expected
The cold repetitive test is run at 85ºC which is the worst case condition for the device to sustain a short circuit.
The cold repetitive test refers to the device being given time to cool down between pulses, rather than being run
at a cold temperature. The load short circuit is the worst case situation, since the energy stored in the cable
inductance can cause additional harm. The fast response of the device ensures current limiting occurs quickly
and at a current close to the load short condition. In addition, the hot repetitive test is performed as well.
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表 7. AEC - Q100-012 Test Results
DEVICE
VERSION
NO. OF CYCLES /
NO. OF
UNITS
NO. OF
FAILS
TEST
LOCATION OF SHORT
DURATION
Cold Repetitive - Long
Pulse
Load Short Circuit, Lshort = 5 μH, Rshort
100 mΩ, TA = 85ºC
=
=
B
100 k cycles
30
0
Load Short Circuit, Lshort = 5 μH, Rshort
100 mΩ, TA = 25ºC
B
100 hours
30
0
Hot Repetitive - Long Pulse
10.2 Typical Application
This application example demonstrates how the TPS2HB50-Q1 device can be used to power resistive heater
loads in automotive seats. In this example, we consider dual heater loads that are powered independently by the
two channels of the device. A dual-channel device is the ideal solution as it will yield a smaller solution size
relative to two single-channel devices.
+12 V Battery
DIA_EN
VBB
SEL1
SEL2
SNS
µC
ILIM1
ILIM2
LATCH
EN1
EN2
GND
VOUT1
VOUT2
HEATER LOAD
R1
HEATER LOAD
R2
图 16. Block Diagram for Powering Dual Heater Loads
10.2.1 Design Requirements
For this design example, use the input parameters shown in 表 8.
表 8. Design Parameters
DESIGN PARAMETER
VBB
EXAMPLE VALUE
13.5 V
Load Ch1 - Heater 1
Load Ch2 - Heater 2
32 W max
32 W max
32
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表 8. Design Parameters (接下页)
DESIGN PARAMETER
EXAMPLE VALUE
Load Current Sense
ILIM
30 mA to 6 A
4 A
Ambient temperature
RθJA
70°C
32.5°C/W (depending on PCB)
A
Device Version
10.2.2 Detailed Design Procedure
10.2.2.1 Thermal Considerations
The DC current in each channel under maximum load power condition will be around 2.4 A. Both heater loads
can be ON at the same time, so the case where both channels are enabled simultaneously is considered to
assume worst case heating.
Power dissipation in the switch is calculated in 公式 4. RON is assumed to be 100 mΩ because this is the
maximum specification at high temperature. In practice, RON will almost always be lower.
PFET = I2 × RON
PFET = (2.4 A)2 × 100 mΩ = 0.58 W
(4)
(5)
If both channels are enabled, then the total power dissipation is 1.15 W. The junction temperature of the device
can be calculated using 公式 6 and the RθJA value from the Specifications section.
TJ = TA + RθJA × PFET
(6)
TJ = 70°C + 32.5°C/W × 1.15 W = 107.5°C
The maximum junction temperature rating for the TPS2HB50-Q1 device is TJ = 150°C. Based on the above
example calculation, the device temperature will stay below the maximum rating.
10.2.2.2 RILIM Calculation
In this application, the TPS2HB50-Q1 must allow for the maximum 2.4 A current with margin but minimize the
energy in the switch during a fault condition by minimizing the current limit. For this application, the best ILIM set
point is approximately 4 A. 公式 7 allows you to calculate the RILIM value that is placed from the ILIMX pins to VBB
.
RILIM is calculated in kΩ.
RILIM = KCL / ICL
(7)
(8)
Because this device is version A, the KCL value in the Specifications section is 40 A × kΩ.
RILIM = 40 A × kΩ / 4 A = 10 kΩ
For a ILIM of 4 A, the RILIM value should be set at approximately 10 kΩ.
10.2.2.3 Diagnostics
If the resistive heating load is disconnected (heater malfunction), an alert is desired. Open-load detection can be
performed in the switch-enabled state with the current sense feature of the TPS2HB50-Q1 device. Under open
load condition, the current in the SNS pin will be the fault current and the can be detected from the sense voltage
measurement.
10.2.2.3.1 Selecting the RSNS Value
表 9 shows the requirements for the load current sense in this application. The KSNS value is specified for the
device and can be found in the Specifications section.
表 9. RSNS Calculation Parameters
PARAMETER
EXAMPLE VALUE
Current Sense Ratio (KSNS
)
1500
6 A
Largest diagnosable load current
Smallest diagnosable load current
Full-scale ADC voltage
30 mA
5-V
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表 9. RSNS Calculation Parameters (接下页)
PARAMETER
EXAMPLE VALUE
ADC resolution
10-bit
The load current measurement requirements of 6 A ensures that even in the event of a overcurrent surpassing
the device internal 4 A limit, the MCU can register and react by shutting down the TPS2HB50-Q1, while the low
level of 30 mA allows for accurate measurement of low load currents.
The RSNS resistor value should be selected such that the largest diagnosable load current puts VSNS at about
95% of the ADC full-scale. With this design, any ADC value above 95% can be considered a fault. Additionally,
the RSNS resistor value should ensure that the smallest diagnosable load current does not cause VSNS to fall
below 1 LSB of the ADC. With the given example values, a 1.2 kΩ sense resistor satisfies both requirements
shown in 表 10.
表 10. VSNS Calculation
LOAD (A)
0.030
6
SENSE RATIO
1500
ISNS (mA)
RSNS (Ω)
1200
VSNS (V)
0.024
% of 5-V ADC
0.5%
0.02
4
1500
1200
4.800
96.0%
11 Power Supply Recommendations
The TPS2HB50-Q1 device is designed to operate in a 12-V automotive system. The nominal supply voltage
range is 6 V to 18 V as measured at the VBB pin with respect to the GND pin of the device. In this range the
device meets full parametric specifications as listed in the Electrical Characteristics table. The device is also
designed to withstand voltage transients beyond this range. When operating outside of the nominal voltage range
but within the operating voltage range, the device will exhibit normal functional behavior. However, parametric
specifications may not be specified outside the nominal supply voltage range.
表 11. Operating Voltage Range
VBB Voltage Range
Note
Transients such as cold crank and start-stop, functional operation
are specified but some parametric specifications may not apply. The
device is completely short-circuit protected up to 125°C
3 V to 6 V
Nominal supply voltage, all parametric specifications apply. The
device is completely short-circuit protected up to 125°C
6 V to 18 V
18 V to 24 V
18 V to 40 V
Transients such as jump-start and load-dump, functional operation
specified but some parametric specifications may not apply. The
device is completely short-circuit protected up to 125°C
Transients such as jump-start and load-dump, functional operation
specified but some parametric specifications may not apply.
12 Layout
12.1 Layout Guidelines
To achieve optimal thermal performance, connect the exposed pad to a large copper pour. On the top PCB layer,
the pour may extend beyond the package dimensions as shown in the example below. In addition to this, it is
recommended to also have a VBB plane either on one of the internal PCB layers or on the bottom layer.
Vias should connect this plane to the top VBB pour.
Ensure that all external components are placed close to the pins. Device current limiting performance can be
harmed if the RILIM is far from the pins and extra parasitics are introduced.
34
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TPS2HB50-Q1
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ZHCSJN5A –FEBRUARY 2018–REVISED APRIL 2019
12.2 Layout Example
GND
SNS
DIA_EN
SEL2
SEL1
NC
To µC
LATCH
EN
To µC
VBB
ST
NC
VOUT
VOUT
VOUT
VOUT
VOUT
VOUT
图 17. PWP Layout Example
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13 器件和文档支持
13.1 文档支持
13.1.1 相关文档
请参阅如下相关文档：
•
•
•
•
•
TI《如何利用智能高侧开关驱动电感、电容和照明负载》
TI《智能电源开关的短路可靠性测试》
TI《智能电源开关的可调电流限制》
TI《TPS2HB35-Q1 40V、35mΩ 双通道智能高侧开关》
TI《使用可调电流限制提高汽车短路可靠性》
13.2 接收文档更新通知
要接收文档更新通知，请导航至 TI.com.cn 上的器件产品文件夹。单击右上角的通知我 进行注册，即可每周接收产
品信息更改摘要。有关更改的详细信息，请查看任何已修订文档中包含的修订历史记录。
13.3 社区资源
下列链接提供到 TI 社区资源的连接。链接的内容由各个分销商“按照原样”提供。这些内容并不构成 TI 技术规范，
并且不一定反映 TI 的观点；请参阅 TI 的 《使用条款》。
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.
13.4 商标
E2E is a trademark of Texas Instruments.
13.5 静电放电警告
ESD 可能会损坏该集成电路。德州仪器 (TI) 建议通过适当的预防措施处理所有集成电路。如果不遵守正确的处理措施和安装程序 , 可
能会损坏集成电路。
ESD 的损坏小至导致微小的性能降级 , 大至整个器件故障。 精密的集成电路可能更容易受到损坏 , 这是因为非常细微的参数更改都可
能会导致器件与其发布的规格不相符。
13.6 术语表
SLYZ022 — TI 术语表。
这份术语表列出并解释术语、缩写和定义。
14 机械、封装和可订购信息
以下页面包含机械、封装和可订购信息。这些信息是指定器件的最新可用数据。数据如有变更，恕不另行通知，且
不会对此文档进行修订。如需获取此数据表的浏览器版本，请查阅左侧的导航栏。
36
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PACKAGE OPTION ADDENDUM
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23-Feb-2023
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
PTPS2HB50BQPWPRQ1
TPS2HB50AQPWPRQ1
OBSOLETE HTSSOP
PWP
PWP
16
16
TBD
Call TI
NIPDAU
Call TI
ACTIVE
HTSSOP
3000
3000
RoHS-Exempt
& Green
Level-3-260C-168HRS
-40 to 125
-40 to 125
2HB50AQ
2HB50BQ
Samples
Samples
TPS2HB50BQPWPRQ1
ACTIVE
HTSSOP
PWP
16
RoHS-Exempt
& Green
NIPDAU
Level-3-260C-168HRS
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
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In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
29-Jan-2020
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
TPS2HB50AQPWPRQ1 HTSSOP PWP
TPS2HB50BQPWPRQ1 HTSSOP PWP
16
16
3000
3000
330.0
330.0
12.4
12.4
6.9
6.9
5.6
5.6
1.6
1.6
8.0
8.0
12.0
12.0
Q1
Q1
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
29-Jan-2020
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SPQ
Length (mm) Width (mm) Height (mm)
TPS2HB50AQPWPRQ1
TPS2HB50BQPWPRQ1
HTSSOP
HTSSOP
PWP
PWP
16
16
3000
3000
350.0
350.0
350.0
350.0
43.0
43.0
Pack Materials-Page 2
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