TPS259827ONRGER [TI]
具有精确负载电流监测和可调节瞬态故障管理功能的 2.7V 至 24V、2.7mΩ、15A 电子保险丝 | RGE | 24 | -40 to 125;
| 型号： | TPS259827ONRGER |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 具有精确负载电流监测和可调节瞬态故障管理功能的 2.7V 至 24V、2.7mΩ、15A 电子保险丝 | RGE | 24 | -40 to 125 电子 |
| 文件： | 总55页 (文件大小：5979K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
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TPS25982
ZHCSIW7B –OCTOBER 2018–REVISED JANUARY 2020
具有 1.5% 精确负载电流监测和可调节瞬态故障管理功能的 TPS25982
2.7V 至 24V、15A、2.7mΩ 智能电子保险丝
1 特性
3 说明
1
•
宽输入电压范围：2.7V 至 24V
绝对最大值为 30V
TPS25982 系列电子保险丝是采用小型封装的高度集
成电路保护和电源管理解决方案。这些器件可在宽输入
电压范围内工作。单个器件适用于需要最小 I*R 压降的
低电压系统以及需要低功率耗散的高电压、高电流系
统。它们能够非常有效地抵御过载、短路、电压浪涌和
过多浪涌电流。
–
•
•
低导通电阻：RON = 2.7mΩ（典型值）
可调节电流限制阈值
–
–
范围：2A 至 15A
精度：± 8%（ILIM > 5A 时的典型值）
•
•
断路器和限流器选项
过压事件受内部截止电路的限制，可通过多个器件选项
来选择过压阈值。
可调节过流消隐计时器
–
处理负载瞬态而不跳变
精确的电流监视器输出
± 1.5%（25°C 且 IOUT > 3A 时的典型值）
用户可配置的故障响应
存在多种器件选项，可在过流情况响应、断路器或有源
限流器之间进行选择。可以使用单个外部电阻器来设置
过流限值和快速跳变（短路）阈值。这些器件通过区分
瞬态事件和实际故障来智能地管理过流响应，从而允许
系统在线路和负载瞬变期间不间断运行，而不会影响故
障保护的稳健性。可将该器件配置为在故障关闭后保持
闭锁或自动重试。可使用电容器来配置自动重试次数和
重试延迟。这使远程系统能够自动从临时故障中恢复，
同时确保电源不会因持续的故障而无限期地承受应力。
•
•
–
–
–
–
闭锁或自动重试
重试次数（有限或无限）
重试之间的延迟
•
强大的短路保护
–
–
–
快速跳变响应时间 < 400ns（典型值）
完成 100 万次电源短路事件测试
不受线路瞬变影响 - 无干扰性跳变
TPS25982 器件采用 4mm × 4mm 小型 QFN 封装。这
些器件的额定工作结温范围为 –40˚C 至 125˚C。
•
•
•
可调节的输出压摆率控制 (dVdt) 控制
可调节的欠压锁定
器件信息(1)
过压锁定（固定 3.7V、7.6V 和 16.9V 且无 OVLO
选项）
器件型号
TPS25982
封装
QFN (24)
封装尺寸（标称值）
4.0mm × 4.0mm
•
•
•
•
集成式过热保护
(1) 如需了解所有可用封装，请参阅数据表末尾的可订购产品附
录。
电源正常状态指示
可调节的负载检测和握手计时器
UL 2367 认证
简化电路原理图
TPS25982
Power
Supply
–
–
文件编号E339631
ILIM ≥ 182Ω
IN
OUT
VPG
RPG
LDSTRT
RVL1
R
EN/UVLO
NRETRY
PG
IMON
•
•
经 IEC 62368 CB 认证
CL
RL
CIN
RETRY_DLY
dVdt
小尺寸：4mm × 4mm QFN 封装
*
*
CNRETRY
CLDSTRT
RVL2
GND ITIMER
ILIM
RILIM
CdVdt
*
CRETRY_DLY
RIMON
*
CITIMER
2 应用
* Optional components for extended functionality
•
•
热插拔
服务器待机电源轨、PCIe 转接卡、附加卡和风扇
模块保护
•
•
•
路由器和开关光学模块保护
工业 PC
数字电视
1
本文档旨在为方便起见，提供有关 TI 产品中文版本的信息，以确认产品的概要。 有关适用的官方英文版本的最新信息，请访问 www.ti.com，其内容始终优先。 TI 不保证翻译的准确
性和有效性。 在实际设计之前，请务必参考最新版本的英文版本。
English Data Sheet: SLVSEI3
TPS25982
ZHCSIW7B –OCTOBER 2018–REVISED JANUARY 2020
www.ti.com.cn
目录
8.5 Device Functional Modes........................................ 29
Application and Implementation ........................ 31
9.1 Application Information............................................ 31
1
2
3
4
5
6
7
特性.......................................................................... 1
应用.......................................................................... 1
说明.......................................................................... 1
修订历史记录 ........................................................... 2
器件比较表............................................................... 3
Pin Configuration and Functions......................... 4
Specifications......................................................... 5
7.1 Absolute Maximum Ratings ...................................... 5
7.2 ESD Ratings.............................................................. 5
7.3 Recommended Operating Conditions....................... 6
7.4 Thermal Information.................................................. 6
7.5 Electrical Characteristics........................................... 7
7.6 Timing Requirements................................................ 8
7.7 Switching Characteristics.......................................... 9
7.8 Typical Characteristics............................................ 10
Detailed Description ............................................ 17
8.1 Overview ................................................................. 17
8.2 Functional Block Diagram ....................................... 17
8.3 Feature Description................................................. 18
8.4 Fault Response ...................................................... 27
9
9.2 Typical Application: Standby Power Rail Protection in
Datacenter Servers ................................................. 31
9.3 System Examples ................................................... 38
10 Power Supply Recommendations ..................... 42
10.1 Transient Protection.............................................. 42
10.2 Output Short-Circuit Measurements ..................... 43
11 Layout................................................................... 44
11.1 Layout Guidelines ................................................. 44
11.2 Layout Example .................................................... 45
12 器件和文档支持 ..................................................... 46
12.1 文档支持 ............................................................... 46
12.2 接收文档更新通知 ................................................. 46
12.3 社区资源................................................................ 46
12.4 商标....................................................................... 46
12.5 静电放电警告......................................................... 46
12.6 Glossary................................................................ 46
13 机械、封装和可订购信息....................................... 46
8
4 修订历史记录
注：之前版本的页码可能与当前版本有所不同。
Changes from Revision A (June 2019) to Revision B
Page
•
Change Overtemperature Protection IdVdt min from 3.55 µA to 2 µA in the Electrical Characteristics table.......................... 5
Changes from Original (October 2018) to Revision A
Page
•
已更改 将“高级信息”更改为“生产数据” ................................................................................................................................... 1
2
版权 © 2018–2020, Texas Instruments Incorporated
TPS25982
www.ti.com.cn
ZHCSIW7B –OCTOBER 2018–REVISED JANUARY 2020
5 器件比较表
过压锁定阈值
典型值 (V)
3.7
器件型号
过流响应
TPS259822LNRGE
TPS259823LNRGE
TPS259824LNRGE
TPS259827LNRGE
TPS259822ONRGE
TPS259823ONRGE
TPS259824ONRGE
TPS259827ONRGE
有源限流器
有源限流器
有源限流器
有源限流器
断路器
7.6
16.9
无 OVLO
3.7
7.6
断路器
16.9
断路器
无 OVLO
断路器
Copyright © 2018–2020, Texas Instruments Incorporated
3
TPS25982
ZHCSIW7B –OCTOBER 2018–REVISED JANUARY 2020
www.ti.com.cn
6 Pin Configuration and Functions
RGE
24-Pin QFN
Top View
18
17
OUT
OUT
IN
IN
1
2
IN
IN
IN
Thermal Pad 1
16
15
14
13
3
4
5
6
dVdt
GND
GND
GND
GND
Thermal Pad 2
EN/UVLO
PG
Pin Functions
PIN
TYPE
DESCRIPTION
NAME
NO.
17, 18, 19,
20, 21, 22,
23, 24
OUT
Power
Power Output
1, 2, 3, 16,
Pad 1
Thermal /
Power
Power Input. The exposed pad must be soldered to input power plane uniformly to ensure
proper heat dissipation and to maintain optimal current distribution through the device.
IN
4, 5, 14,
Pad 2
GND
Ground
Connect to System Ground
Active High Enable for the device. A resistor divider on this pin from input supply to GND can
be used to adjust the Undervoltage Lockout threshold. Do not leave floating.
EN/UVLO
6
Analog Input
A capacitor from this pin to GND sets the overcurrent blanking interval during which the
output current can temporarily exceed set current limit (but lower than fast-trip threshold)
before the device overcurrent response takes action. Leave this pin open for fastest
response to overcurrent events. Refer to ITIMER Functional Mode Summary for more
details.
Analog
Output
ITIMER
7
Analog
Output
An external resistor from this pin to GND sets the output current limit threshold and fast trip
threshold. Do not leave floating.
ILIM
8
9
Analog output load current monitor. This pin sources a current proportional to the load
current. This can be converted to a voltage signal by connecting an appropriate resistor from
this pin to GND.
Analog
Output
IMON
A capacitor from this pin to GND sets the time period that has to elapse after a fault
shutdown before the device attempts to restart automatically. Connect this pin to GND for
latch-off operation (no auto-retries) after a fault. Refer to Fault Response section for more
details.
Analog
Output
RETRY_DLY
NRETRY
10
11
A capacitor from this pin to GND sets the number of times the part attempts to restart
automatically after shutdown due to fault. Connect this pin to GND if the part should retry
indefinitely. Refer to Fault Response section for more details.
Analog
Output
4
Copyright © 2018–2020, Texas Instruments Incorporated
TPS25982
www.ti.com.cn
ZHCSIW7B –OCTOBER 2018–REVISED JANUARY 2020
Pin Functions (continued)
PIN
TYPE
DESCRIPTION
NAME
NO.
Load Detect/Handshake Signal. A capacitor from this pin to GND sets the time period after
PG assertion within which the pin has to be pulled low for the device to remain ON. Connect
to GND if the load detect/handshake feature is not used. Refer to Load Detect/Handshake
(LDSTRT) section for more details. Do not leave floating.
LDSTRT
12
Analog Input
Active High Power Good Indication. This pin is asserted when the FET is fully enhanced and
PG
13
15
Digital Output output has reached maximum voltage. It is an open drain output that requires an external
pull-up resistor to an external supply. This pin remains logic low when VIN < VUVP
.
Analog
Output
A capacitor from this pin to GND sets the output turn on slew rate. Leave this pin floating for
the fastest slew rate during start up.
dVdt
7 Specifications
7.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)(1)
Parameter
Pin
MIN
–0.3
–0.8
–0.3
MAX UNIT
VIN
Maximum Input Voltage Range
Maximum Output Voltage Range
Maximum Enable Pin Voltage Range
Maximum LDSTRT Pin Voltage Range
Maximum dVdt Pin Voltage Range
Maximum PG Pin Voltage Range
Maximum ITIMER Pin Voltage Range
Maximum NRETRY Pin Voltage Range
Maximum RETRY_DLY Pin Voltage Range
Maximum Continuous Switch Current
Junction temperature
IN
30
V
V
V
V
V
V
V
V
V
A
°C
VOUT
OUT
min (30V, VIN + 0.3)
VEN/UVLO
VLDSTRT
VdVdt
EN/UVLO
LDSTRT
dVdt
7
7
Internally Limited
–0.3
VPG
PG
7
VITIMER
VNRETRY
VRETRY_DLY
IMAX
ITIMER
NRETRY
RETRY_DLY
IN to OUT
Internally Limited
Internally Limited
Internally Limited
Internally Limited
Internally Limited
TJ
TLEAD
Tstg
Maximum Soldering Temperature
Storage temperature
300 °C
150 °C
–65
(1) Stresses beyond those listed under Absolute Maximum Rating may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
7.2 ESD Ratings
VALUE
UNIT
Human body model (HBM), per
± 2000
ANSI/ESDA/JEDEC JS-001, all pins(1)
V(ESD)
Electrostatic discharge
V
Charged device model (CDM), per JEDEC
specificationJESD22-C101, all pins(2)
± 1000
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
Copyright © 2018–2020, Texas Instruments Incorporated
5
TPS25982
ZHCSIW7B –OCTOBER 2018–REVISED JANUARY 2020
www.ti.com.cn
7.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
Parameter
Pin
MIN
MAX
UNIT
V
VIN
Input Voltage Range
IN
2.7
24
VIN + 0.3
6(1)
VOUT
Output Voltage Range
OUT
V
VEN/UVLO
VLDSTRT
VdVdT
Enable Pin Voltage Range
EN/UVLO
LDSTRT
dVdt
V
LDSTRT Pin Capacitor Voltage Rating
dVdT Pin Capacitor Voltage Rating
PG Pin Voltage Range
4
V
VIN + 4
V
VPG
PG
6(2)
V
VITIMER
VNRETRY
VRETRY_DLY
RILIM
ITIMER Pin Capacitor Voltage Rating
NRETRY Pin Capacitor Voltage Rating
RETRY_DLY Pin Capacitor Voltage Rating
ILIM Pin Resistor
ITIMER
NRETRY
4
4
V
V
RETRY_DLY
ILIM
4
V
82
1650
15
Ω
A
IMAX
Continuous Switch Current
Junction temperature
IN to OUT
TJ
–40
125
°C
(1) For supply voltages below 6V, it is okay to pull up the EN pin to IN directly. For supply voltages greater than 6V, it is recommended
to use an appropriate resistor divider between IN, EN and GND to ensure the voltage at the EN pin is within the specified limits.
(2) For supply voltages below 6V, it is okay to pull up the PG pin to IN/OUT through a resistor. For supply voltages greater than 6V, it is
recommended to use a stepped down power supply to ensure the voltage at the PG pin is within the specified limits.
7.4 Thermal Information
TPS25982X
THERMAL METRIC(1) (2)
RGE (QFN)
24 PINS
34.6
UNIT
RθJA
Junction-to-ambient thermal resistance
Junction-to-case (top) thermal resistance
Junction-to-board thermal resistance
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
RθJC(top)
RθJB
36.7
11.2
ΨJT
Junction-to-top characterization parameter
Junction-to-board characterization parameter
Junction-to-case (bottom) thermal resistance
3
ΨJB
11.2
RθJC(bot)
1.6
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
(2) Based on simulations conducted with the device mounted on a JEDEC 4-layer PCB (2s2p) with minimum recommended pad size (2 oz
Cu) and 3x2 via array.
6
Copyright © 2018–2020, Texas Instruments Incorporated
TPS25982
www.ti.com.cn
ZHCSIW7B –OCTOBER 2018–REVISED JANUARY 2020
7.5 Electrical Characteristics
(Test conditions unless otherwise noted) –40°C ≤ TJ ≤ 125°C, VIN = 12 V for TPS259824x/7x, 5 V for TPS259823x, 3.3 V for
TPS259822x, VEN/UVLO = 2 V, RILIM = 1650 Ω , CdVdT = Open, OUT = Open. All voltages referenced to GND.
PARAMETER
INPUT SUPPLY (IN)
TEST CONDITIONS
MIN
TYP
MAX
UNIT
VIN
IQ
Input Voltage Range
IN Quiescent Current
2.7
24
1200
300
20
V
µA
µA
µA
V
V
EN ≥ VUVLO(R)
800
204
VSD < VEN < VUVLO
VEN < VSD
ISD
IN Shutdown Current
3.67
2.53
2.42
VIN Rising
2.46
2.35
2.6
IN Undervoltage Protection
Threshold
VUVP
VIN Falling
2.49
V
OVERVOLTAGE PROTECTION (IN)
TPS259822x, VIN Rising
TPS259823x, VIN Rising
TPS259824x, VIN Rising
TPS259822x, VIN Falling
TPS259823x, VIN Falling
TPS259824x, VIN Falling
3.62
7.39
3.7
7.6
3.76
7.76
V
V
V
V
V
V
VOVP(R)
16.32
3.52
16.9
3.6
17.31
3.66
Overvoltage Protection Threshold
VOVP(F)
7.22
7.4
7.55
15.80
16.4
16.81
OUTPUT CURRENT MONITOR (IMON)
3 A ≤ IOUT ≤ min(15 A, ILIM), –40 °C ≤
GIMON
Current Monitor Gain (IIMON:IOUT
)
238.6
246
253.4
µA/A
TA ≤ 75 °C
OUTPUT CURRENT LIMIT (ILIM)
RILIM = 773 Ω, TJ = 25 ℃
RILIM = 773 Ω, TJ = -40 to 125 ℃
RILIM = 300 Ω, TJ = 25 ℃
RILIM = 300 Ω, TJ = -40 to 125 ℃
RILIM = 182 Ω, TJ = 25 ℃
RILIM = 182 Ω, TJ = -40 to 125 ℃
RILIM = 100 Ω, TJ = 25 ℃
RILIM = 100 Ω, TJ = -40 to 125 ℃
RILIM = Open
1.76
1.53
2
2
2.17
2.43
A
A
A
A
A
A
A
A
A
4.75
4.98
4.98
8.13
8.13
14.71
14.71
0
5.23
4.36
5.66
ILIM
IOUT Current Limit Threshold
7.77
8.54
7.23
9.07
13.56
12.85
15.66
15.99
IOUT Circuit Breaker Threshold
During ILIM pin Short to GND
Condition (Single point failure)
ICB
ISC
RILIM = Short to GND, TJ = 25 ℃
20
A
Short-circuit Fast Trip Threshold
210
2.7
% ILIM
ON-RESISTANCE (IN - OUT)
TJ = 25 ℃, IOUT = 2 A
3.2
4.5
mΩ
mΩ
RON ON State Resistance
TJ = -40 to 125 ℃, IOUT = 2 A
ENABLE / UNDERVOLTAGE LOCKOUT (EN/UVLO)
VUVLO(R)
VEN Rising
VEN Falling
1.18
1.08
1.2
1.1
1.23
1.13
V
V
EN/UVLO Pin Voltage Threshold
VUVLO(F)
EN/UVLO Pin Voltage Threshold for
Lowest Shutdown Current
VSD
VEN Falling
0.59
0.8
V
IENLKG
EN/UVLO Pin Leakage Current
0.1
µA
POWER GOOD INDICATION (PG)
VIN < VUVP, VEN < VSD, IPG = 26 µA
VIN = 3.3V, IPG ≤ 5 mA
651
320
100
786
mV
mV
mV
PG Pin Low Voltage (PG de-
asserted)
VPGD
VIN ≥ 5V, IPG ≤ 5 mA
PG Pin Leakage Current (PG
asserted)
IPGLKG
PG pulled up to 5 V through 10 kΩ
1.7
µA
RON(PGA)
RON When PG is asserted
4.2
mΩ
Copyright © 2018–2020, Texas Instruments Incorporated
7
TPS25982
ZHCSIW7B –OCTOBER 2018–REVISED JANUARY 2020
www.ti.com.cn
Electrical Characteristics (continued)
(Test conditions unless otherwise noted) –40°C ≤ TJ ≤ 125°C, VIN = 12 V for TPS259824x/7x, 5 V for TPS259823x, 3.3 V for
TPS259822x, VEN/UVLO = 2 V, RILIM = 1650 Ω , CdVdT = Open, OUT = Open. All voltages referenced to GND.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
VIN - VOUT Threshold when PG is
de-asserted
VPGTHD
0.224
0.326
0.450
V
AUTO-RETRY DELAY INTERVAL (RETRY_DLY)
VRETRY_DLY(R)
VRETRY_DLY(F)
VRETRY_DLY_HY
1.1
V
V
RETRY_DLY Oscillator Comparator
Threshold
0.35
RETRY_DLY Oscillator Hysteresis
RETRY_DLY Pin Bias Current
0.65
1.7
0.75
2.05
0.85
2.5
V
S
IRETRY_DLY
µA
NUMBER OF AUTO-RETRIES (NRETRY)
VNRETRY(R)
VNRETRY(F)
VNRETRY_HYS
INRETRY
1.1
0.35
0.75
2.05
V
V
NRETRY Oscillator Comparator
Threshold
NRETRY Oscillator Hysteresis
NRETRY Pin Bias Current
0.65
1.7
0.85
2.5
V
µA
CURRENT FAULT TIMER (ITIMER)
IITIMER
RITIMER
VINT
ITIMER Discharge Current
ISC > IOUT > ILIM
1.4
2.1
23
2.8
µA
kΩ
V
ITIMER Internal Pull-up Resistance IOUT < ILIM
ITIMER Pin Default Voltage
IOUT < ILIM
2.5
ITIMER Comparator Falling
Threshold
VITIMER
ISC > IOUT > ILIM, ITIMER Voltage Rising
1.53
0.98
V
V
ITIMER Comparator Voltage
Threshold Delta
ΔVITIMER
ISC > IOUT > ILIM, ITIMER Voltage Falling
0.7
1.3
LDSTRT
VLDSTRT
ILDSTRT
LDSTRT Rising Threshold
LDSTRT Charging Current
LDSTRT voltage rising
PG asserted
1.1
1.7
1.21
2.05
1.3
2.4
V
µA
LDSTRT Internal Pull-down
Resistance
RLDSTRT
31
Ω
OVERTEMPERATURE PROTECTION
TSD
Thermal Shutdown Threshold
TJ Rising
TJ Falling
150
10
°C
°C
TSDHys
dVdt
IdVdt
Thermal Shutdown Hysteresis
dVdt Pin Charging Current
2
4.6
6.33
µA
7.6 Timing Requirements
PARAMETER
TEST CONDITIONS
MIN TYP MAX
UNIT
VIN > VOVLO(R) to VOUT↓, TPS259822x
VIN > VOVLO(R) to VOUT↓, TPS259823x
VIN > VOVLO(R) to VOUT↓, TPS259824x
IOUT > ILIM + 30% and ITIMER expired to
1.5
5
µs
µs
µs
(1)
tOVP
Overvoltage Protection Response Time
5
(2)
tLIM
tSC
Current Limit Response Time
Short Circuit Response Time
270
400
120
µs
ns
µs
IOUT ≤ ILIM
IOUT > 3 x ILIM to VOUT turned OFF
VG > (VIN + 3.6V) to PG↑ or (VIN - VOUT)>
VPGTHD to PG↓
(3)
tPGD
PG Assertion/De-assertion De-glitch
(1) Please refer to Fig. 43
(2) Please refer to Fig. 45
(3) Please refer to Fig. 47
8
Copyright © 2018–2020, Texas Instruments Incorporated
TPS25982
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ZHCSIW7B –OCTOBER 2018–REVISED JANUARY 2020
7.7 Switching Characteristics
The output rising slew rate is internally controlled and constant across the entire operating voltage range to ensure the turn
on timing is not affected by the load conditions. The rising slew rate can be adjusted by adding capacitance from the dVdt pin
to ground. As CdVdt is increased it will slow the rising slew rate (SR). See Slew Rate and Inrush Current Control (dVdt) section
for more details. The Turn-Off Delay and Fall Time, however, are dependent on the RC time constant of the load capacitance
(COUT) and Load Resistance (RL). The Switching Characteristics are only valid for the power-up sequence where the supply is
available in steady state condition and the load voltage is completely discharged before the device is enabled.Typical Values
are taken at TJ = 25°C unless specifically noted otherwise. RL = 3.6 Ω, COUT = 1 mF
CdVdt
6800pF
=
PARAMETER
VIN
CdVdt = Open CdVdt = 3300pF
UNIT
2.7 V
12 V
24 V
2.7 V
12 V
24 V
2.7 V
12 V
24 V
2.7 V
12 V
24 V
2.7 V
12 V
24 V
6.26
7.35
7.4
1.39
1.4
0.68
SRON
tD,ON
tR
Output Rising slew rate
0.68
0.68
1.7
V/ms
1.4
1.3
1.49
2.1
Turn on delay
Rise time
1.24
1.2
3.01
4.74
3.35
14.41
28.41
5.05
17.42
33.15
152
ms
ms
ms
µs
2.91
1.63
6.99
13.77
3.12
9.09
16.68
152
0.67
1.35
2.66
1.97
2.59
3.86
151
212
262
tON
Turn on time
Turn off delay
tD,OFF
212
212
262
262
VEN/UVLO
EN/UVLO
VUVLO(R)
VUVLO(F)
0
tON
SRON
tD,OFF
90%
VIN
OUT
10%
0V
tR
tD,ON
tF
Time
图 1. TPS25982 Switching Times
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www.ti.com.cn
7.8 Typical Characteristics
4
2.56
2.54
2.52
2.5
VIN
2.7 V
3.3 V
5 V
12 V
24 V
3.8
3.6
3.4
3.2
3
2.48
2.46
2.44
2.42
2.4
Rising
Falling
2.8
2.6
2.4
2.2
2
-40
-20
0
20
40
60
80
100 120 140
-40
-20
0
20
40
60
80
100 120 140
TJ (èC)
TJ (èC)
D006
D007
图 2. ON Resistance vs Temperature
图 3. Supply UVP Threshold vs Temperature
7.625
3.7
3.68
3.66
3.64
3.62
3.6
7.6
7.575
Rising
Falling
Rising
Falling
7.55
7.525
7.5
7.475
7.45
7.425
7.4
3.58
7.375
-40
-20
0
20
40
60
80
100 120 140
-40
-20
0
20
40
60
80
100 120 140
TJ (èC)
TJ (èC)
D001
D003
TPS259822x Variants
TPS259823x Variants
图 4. Supply OVP Threshold vs Temperature
图 5. Supply OVP Threshold vs Temperature
16.9
16.85
16.8
1.21
1.2
1.19
1.18
1.17
16.75
16.7
Rising
Falling
16.65
16.6
1.16
1.15
1.14
1.13
1.12
1.11
1.1
Rising
Falling
16.55
16.5
16.45
16.4
16.35
16.3
-40
-20
0
20
40
60
80
100 120 140
-40
-20
0
20
40
60
80
100 120 140
TJ (èC)
TJ (èC)
D009
D008
TPS259824x Variants
图 6. Supply OVP Threshold vs Temperature
图 7. EN/UVLO Threshold vs Temperature
0.875
0.85
900
VIN
2.7 V
12 V
875
850
0.825
24 V
825
VIN
0.8
3.3 V
12 V
24 V
800
775
750
725
700
675
650
0.775
0.75
0.725
0.7
0.675
0.65
0.625
-40
-20
0
20
40
60
80
100 120 140
-40
-20
0
20
40
60
80
100 120 140
TJ (èC)
TJ (èC)
D002
D014
VENUVLO = 2 V, OUT = Open
图 8. Quiescent Current vs Temperature
图 9. EN/UVLO Falling Threshold for Lowest Current
Consumption
10
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ZHCSIW7B –OCTOBER 2018–REVISED JANUARY 2020
Typical Characteristics (接下页)
240
12
10
8
VIN
2.7 V
VIN
235
230
225
220
215
210
205
200
195
190
185
180
175
170
165
160
2.7 V
12 V
24 V
12 V
24 V
6
4
2
0
-40
-20
0
20
40
60
80
100 120 140
-40
-20
0
20
40
60
80
100 120 140
TJ(èC)
TJ (èC)
D004
D005
VENUVLO = 1 V, OUT = Open
VENUVLO = 0 V, OUT = Open
图 10. Shut-Down Current vs Temperature
图 11. Deep Shut-Down Current vs Temperature
25
20
18
16
14
12
10
8
MIN
MAX
20
15
10
5
0
-5
6
-10
-15
-20
-25
4
2
0
0
200 400 600 800 1000 1200 1400 1600 1800
RILIM (W)
0
2
4
6
8
ILIM (A)
10
12
14
16
D010
D011
Across Process, Voltage, Temperature Corners
图 12. Output Current Limit (ILIM) vs RILIM
图 13. Output Current Limit (ILIM) Accuracy
3
2.5
2
900
IPG
26uA
242uA
850
800
750
700
650
600
550
500
1.5
1
0.5
0
MIN
MAX
-0.5
-1
-1.5
-2
-2.5
-3
-3.5
-4
0
2
4
6
8
IOUT (A)
10
12
14
16
-40
-20
0
20
40
TJ (èC)
60
80
100 120 140
D012
D015
Across Process, Voltage, Temperature Corners, Normalized to
VIN = 0 V
mean value of 246 μA/A
图 15. Power Good Output Voltage (De-asserted State) vs
图 14. Output Current Monitor Gain (GIMON) Accuracy
Temperature
2.2
2.18
2.16
2.14
2.12
2.1
1.0025
1
0.9975
0.995
0.9925
0.99
0.9875
0.985
2.08
2.06
0.9825
2.04
VIN
VIN
0.98
0.9775
0.975
2.02
2
2.7 V
12 V
24 V
2.7 V
12 V
24 V
1.98
-40
-20
0
20
40
60
80
100 120 140
-40
-20
0
20
40
60
80
100 120 140
TJ (èC)
TJ (èC)
D016
D019
图 16. ITIMER Voltage Threshold Delta vs Temperature
图 17. ITIMER Discharge Current vs Temperature
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Typical Characteristics (接下页)
1.215
1.213
1.211
1.209
1.207
1.205
2.16
2.14
2.12
2.1
VIN
2.7 V
12 V
24 V
2.08
2.06
2.04
VIN
2.02
2.7 V
12 V
24 V
2
1.98
-40
-20
0
20
40
60
80
100 120 140
-40
-20
0
20
40
60
80
100 120 140
TJ (èC)
TJ (èC)
D020
D021
图 18. LDSTRT Charging Current vs Temperature
图 19. LDSTRT Threshold Voltage vs Temperature
5
2.16
VIN
2.14
2.12
2.1
2.7 V
12 V
24 V
4.8
4.6
2.08
2.06
2.04
2.02
2
4.4
VIN
4.2
2.7 V
12 V
24 V
4
-40
1.98
-40
-20
0
20
40
60
80
100 120 140
-20
0
20
40
60
80
100 120 140
TJ (èC)
TJ (èC)
D022
D024
图 20. DVDT Charging Current vs Temperature
0.76
图 21. RETRY_DLY Bias Current vs Temperature
2.14
2.12
2.1
VIN
2.7 V
12 V
0.758
0.756
24 V
0.754
2.08
2.06
2.04
2.02
0.752
0.75
0.748
0.746
0.744
0.742
0.74
VIN
2
2.7 V
12 V
24 V
1.98
1.96
-40
-20
0
20
40
60
80
100 120 140
-40
-20
0
20
40
60
80
100 120 140
TJ (èC)
TJ (èC)
D025
D027
图 22. RETRY_DLY Oscillator Hysteresis vs Temperature
图 23. NRETRY Bias Current vs Temperature
0.76
0.755
0.75
1000
VIN
3.3 V
12 V
TA
-40 èC
500
300
200
27 èC
24 V
85 èC
125 èC
100
0.745
0.74
50
30
20
0.735
0.73
10
5
3
2
0.725
0.72
1
-40
-20
0
20
40
TJ (èC)
60
80
100 120 140
0
4
8
12
16
Power Dissipation (W)
20
24
28
32
36
40
D026
D023
图 24. NRETRY Oscillator Hysteresis vs Temperature
图 25. Thermal Shutdown Plot - Steady State
12
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ZHCSIW7B –OCTOBER 2018–REVISED JANUARY 2020
Typical Characteristics (接下页)
200
100
50
TPS259827x
TPS259822x/23x/24x
30
20
10
5
3
2
1
0.5
2
3
4
5
6
7 8 10
Power Dissipation (W)
20
30 40 50 70 100
D002
图 26. Thermal Shutdown Plot - Inrush/Overload
CIN = 1 μF
COUT = 220 μF
图 27. Hotplug
CdVdt = 3.3 nF
COUT = 220 μF
CdVdt = 10 nF
ROUT = Open
图 28. Startup With EN - dVdt Limited
COUT = 220 μF
CdVdt = 3.3 nF
ROUT = 6 Ω
TPS259824x (16.7-V OVP variant)
图 30. Overvoltage Protection
图 29. Startup With EN Into Resistive Load - dVdt Limited
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Typical Characteristics (接下页)
RILIM = 100 Ω
CITIMER = Open
RILIM = 100 Ω
CITIMER = 4.7 nF
图 31. Current Limit Without Transient Overcurrent Blanking
图 32. Current Limit With Transient Overcurrent Blanking
RILIM = 100 Ω CITIMER = 4.7 nF RETRY_DLY =
RILIM = 100 Ω
CITIMER = 4.7 nF CRETRY_DLY = 1 nF,
CNRETRY = Open
Short to GND
图 33. Current Limit Followed By Thermal Shutdown - Latch-
图 34. Current Limit Followed By Thermal Shutdown - Auto-
off
Retry
14
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ZHCSIW7B –OCTOBER 2018–REVISED JANUARY 2020
Typical Characteristics (接下页)
RILIM = 100 Ω
CITIMER = 4.7 nF
RILIM = 100 Ω
CITIMER = 4.7 nF CRETRY_DLY = Open,
CNRETRY = Open
图 36. Circuit Breaker - Auto-Retry
图 35. Circuit Breaker With Transient Overcurrent Blanking
RILIM = 100 Ω
RILIM = 100 Ω
图 37. Power Up Into Output Short-Circuit
图 38. Output Hard Short-Circuit While ON
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Typical Characteristics (接下页)
RILIM = 100 Ω
RILIM = 332 Ω
图 40. Supply Line Transient Immunity - Input Voltage Step
图 39. Output Hard Short-Circuit While ON (Zoomed In)
RILIM = 511 Ω
图 41. Supply Line Transient Immunity - Adjacent Load Hot Unplug
16
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ZHCSIW7B –OCTOBER 2018–REVISED JANUARY 2020
8 Detailed Description
8.1 Overview
The TPS25982 device is a smart eFuse with integrated power switch that is used to manage load voltage and
load current. The device starts its operation by monitoring the IN bus. When VIN is above the Undervoltage
Protection threshold (VUVP) and below the Overvoltage Protection threshold (VOVP), the device samples the
EN/UVLO pin. A high level on this pin enables the internal MOSFET to start conducting and allow current to flow
from IN to OUT. When EN/UVLO is held low, the internal MOSFET is turned off. After a successful start-up
sequence, the device now actively monitors its load current, input voltage and protects the load from harmful
overcurrent and overvoltage conditions. The device also relies on a built-in thermal sense circuit to shut down
and protect itself in case the device internal temperature (Tj) exceeds the safe operating conditions.
8.2 Functional Block Diagram
TPS25982
PG
120 µs
120 µs
/Q
Q
R
S
GHI
GND
PG_int
FET Temperature Sense &
Overtemperature Protection
TSD
326 mV
OUT
IN
x 246
µA/A
UVPb
Charge
Pump
GHI
GHI
2.53 V
2.42 V
IMON
4.6 µA
dVdt
ILIM
OVPb#
UVLOb
3.6 V
3.7 V/7.6 V/16.9 V
3.6 V/7.4 V/16.4 V
SWEN
Gate control
OC
GHI
CL*
Short
detect
Current Limit Amplifier*
EN/UVLO
1.2 V
1.1 V
VIN transient
detect
ILIM pin fault
SCPb
LDSTRT_FLT
CL* or CB**
SD
0.6 V
2.5V
SD
UVPb
RETRY
RETRY
R
Q
1.5 V
FLTb
FLT
ITIMER
PG_int
CB**
TSD
ITIMER pin fault
ILIM pin fault
Short
detect
1.2 V
S
OC
2.1 µA
R
Retry Logic
S
Q
Q
Q
2.5V
2 µA
ITIMER pin fault
* TPS25982xL (CL variants) only
RETRY_DLY
NRETRY
LDSTRT
** TPS25982xO (CB variants) only
#
Not applicable for TPS259827x (no-OVLO variant)
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8.3 Feature Description
The TPS25982 eFuse is a compact, feature rich power management device that provides detection, protection
and indication in the event of system faults.
8.3.1 Undervoltage Protection (UVLO and UVP)
The TPS25982 implements Undervoltage Protection on IN to turn off the output in case the applied voltage
becomes too low for the downstream load or the device to operate correctly. The Undervoltage Protection has a
default internal threshold of VUVP. If needed, it is also possible to set a user defined Undervoltage Protection
threshold higher than VUVP using the UVLO comparator on the EN/UVLO pin. 图 42 and 公式 1 show how a
resistor divider from supply to GND can be used to set the UVLO set point for a given voltage supply level.
Power
Supply
IN
RVL1
EN/UVLO
RVL2
GND
图 42. Adjustable Supply UVLO Threshold
VUVLO(R) x (RVL1+ RVL2)
RVL2
VINUVLO =
(1)
The resistors must be sized large enough to minimize the constant leakage from supply to ground through the
resistor divider network. At the same time, keep the current through the resistor network sufficiently larger (20x)
than the leakage current on the EN/UVLO pin to minimize the error in the resistor divider ratio.
8.3.2 Overvoltage Protection (OVP)
The TPS25982 implements Overvoltage Lock-Out (OVLO) on IN to protect the output load in the event of input
overvoltage. When the input exceeds the Overvoltage Protection threshold (VOVP(R)) the device turns off the
output within tOVP. As long as an overvoltage condition is present on the input, the device stays disabled and the
output will be turned off. Once the input voltage returns to the normal operating range, the device attempts to
start up normally.
18
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ZHCSIW7B –OCTOBER 2018–REVISED JANUARY 2020
Feature Description (接下页)
Input Overvoltage Event
Input Overvoltage Removed
VOVP(R)
VOVP(F)
IN
0
tOVP
OUT
dVdt Limited
0
VPG
PG
0
Time
图 43. Overvoltage Response
There are multiple device options with different fixed overvoltage thresholds to choose from, including one
without internal overvoltage protection. See the Device Comparison Table for a list of available options.
8.3.3 Inrush Current, Overcurrent, and Short-Circuit Protection
TPS25982 devices incorporate three levels of protection against overcurrent:
•
•
Adjustable slew rate (dVdt) for inrush current control
Adjustable overcurrent protection (with adjustable blanking timer) - Circuit Breaker or Active Current Limiter to
protect against soft overload conditions
•
Adjustable fast-trip response to quickly protect against severe overcurrent (short-circuit) faults
8.3.3.1 Slew Rate and Inrush Current Control (dVdt)
During hot-plug events or while trying to charge a large output capacitance, there can be a large inrush current. If
the inrush current is not controlled, it can damage the input connectors and/or cause the system power supply to
droop leading to unexpected restarts elsewhere in the system. The TPS25982 provides integrated output slew
rate (dVdt) control to manage the inrush current during start-up. The inrush current is directly proportional to the
load capacitance and rising slew rate. The following equation can be used to calculate the slew rate (SR)
required to limit the inrush current (IINRUSH) for a given load capacitance (COUT):
IINRUSH
(
mA
)
SR V / ms =
(
)
COUT
(
mF
)
(2)
An external capacitance can be connected to the dVdt pin to control the rising slew rate and lower the inrush
current during turn on. The required CdVdt capacitance to produce a given slew rate can be calculated using the
following formula:
4600
CdVdt pF =
(
)
SR V / ms
(
)
(3)
19
The fastest output slew rate is achieved by leaving the dVdt pin open.
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Feature Description (接下页)
8.3.3.2 Circuit Breaker
The TPS25982xO (Circuit Breaker) variants respond to output overcurrent conditions by turning off the output
after a user adjustable transient fault blanking interval. When the load current exceeds the programmed current
limit threshold (ILIM set by the ILIM pin resistor RILIM), but lower than the fast-trip threshold (2.1 x ILIM), the device
starts discharging the ITIMER pin capacitor using an internal pull-down current (IITIMER). If the load current drops
below the current limit threshold before the ITIMER capacitor drops by ΔVITIMER, the circuit breaker action is not
engaged and the ITIMER is reset by pulling it up to VINT internally. This allows short transient overcurrent pulses
to pass through the device without tripping the circuit. If the overcurrent condition persists, the ITIMER capacitor
continues to discharge and once it falls by ΔVITIMER, the circuit breaker action turns off the FET immediately. The
following equation can be used to calculate the RILIM value for a desired current limit threshold.
1460
RILIM W =
(
)
ILIM
( )
A - 0.11
(4)
注
Leaving the ILIM pin Open sets the current limit to zero and causes the FET to shut off as
soon as any load current is detected. Shorting the ILIM pin to ground at any point during
normal operation is detected as a fault and the part shuts down. The ILIM pin Short to
GND fault detection circuit requires a minimum amount of load current (ICB) to flow through
the device. This ensures robust eFuse behavior even under single point failure conditions.
Refer to the Fault Response section for details on the device behavior after a fault.
Transient Output Overload
Overload Removed
Persistent Output Overload
ITIMER expired
2.1 x ILIM
IOUT
ILIM
Circuit Breaker
operation
0
VINT
tITIMER
4VITIMER
ITIMER
OUT
0
VIN
0
VPG
PG
TJ
0
TSD
TSDHYS
TJ
Time
图 44. Circuit Breaker Response
20
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Feature Description (接下页)
The duration for which load transients are allowed can be adjusted using an appropriate capacitor value from
ITIMER pin to ground. The transient overcurrent blanking interval can be calculated using 公式 5.
CITIMER (nF) ì DVITIMER (V)
tITIMER (ms) =
IITIMER (mA)
(5)
Leave the ITIMER pin open to allow the part to break the circuit with the minimum possible delay.
表 1. Device ITIMER Functional Mode Summary
ITIMER Pin Connection
OPEN
Timer Delay before Overcurrent response
0 s
Capacitor to ground
Short to GND
As per 公式 5
ITIMER Pin Fault - Part Shuts Off
注
1. Shorting the ITIMER pin to ground is detected as a fault and the part shuts down. This
ensures robust eFuse behavior even in case of single point failure conditions. Refer to the
Fault Response section for details on the device behavior after a fault.
2. Larger ITIMER capacitors take longer to charge during start-up and may lead to
incorrect fault assertion if the ITIMER voltage is still below the pin short detection
threshold after the device has reached steady state. To avoid this, it is recommended to
limit the maximum ITIMER capacitor to the value suggested by the equation below.
tGHI
CITIMER <
53000
VIN + 3.6V
≈
’
tGHI = tD,ON + Cdvdt ì
∆
«
÷
◊
Idvdt
Where
•
•
•
•
tGHI is the time taken by the device to reach steady state
tD,ON is the device turn-on delay
Cdvdt is the dVdt capacitance
Idvdt is the dVdt charging current
It is possible to avoid incorrect ITIMER pin fault assertion and achieve higher ITIMER
intervals if needed by increasing the dVdt capacitor value accordingly, but at the expense
of higher start-up time.
Once the part shuts down due to a Circuit Breaker fault, it can be configured to either stay latched off or restart
automatically. Refer to the Fault Response section for details.
8.3.3.3 Active Current Limiting
The TPS25982xL (Current Limiter) variants respond to output overcurrent conditions by actively regulating the
current to a set limit after a user adjustable fault blanking interval. When the load current exceeds the
programmed current limit threshold (ILIM set by the ILIM pin resistor RILIM), but lower than the fast-trip threshold
(2.1 x ILIM), the device starts discharging the ITIMER pin capacitor using an internal pull-down current (IITIMER). If
the load current drops below the current limit threshold before the ITIMER capacitor voltage drops by ΔVITIMER
,
the current limit action is not engaged and the ITIMER is reset by pulling it up to VINT internally. This allows short
transient overcurrent pulses to pass through the device without limiting the current. If the overcurrent condition
persists, the ITIMER capacitor continues to discharge and once it falls by ΔVITIMER, the device regulates the FET
gate voltage to actively limit the output current to the set ILIM level. The device will exit current limiting when the
load current falls below ILIM. 公式 6 can be used to calculate the RILIM value for a desired current limit.
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1460
RILIM W =
(
)
ILIM
( )
A - 0.11
(6)
注
Leaving the ILIM pin Open sets the current limit to zero and causes the FET to shut off as
soon as any load current is detected. Shorting the ILIM pin to ground at any point during
normal operation is detected as a fault and the part shuts down. The ILIM pin Short to
GND fault detection circuit requires a minimum amount of load current (ICB) to flow through
the device. This ensures robust eFuse behavior even under single point failure conditions.
Refer to the Fault Response section for details on the device behavior after a fault.
ITIMER expired
tLIM
Transient Output Overload
Overload Removed
Persistent Output Overload
2.1 x ILIM
Thermal shutdown
IOUT
ILIM
Current limiting
operation
0
tITIMER
VINT
4VITIMER
ITIMER
0
VIN
VIN - VPGTHD
OUT
0
VPG
PG
TJ
0
TSD
TSDHYS
TJ
Time
图 45. Active Current Limiter Response
The duration for which load transients are allowed can be adjusted using an appropriate capacitor value from
ITIMER pin to ground. The transient overcurrent blanking interval can be calculated using 公式 7.
CITIMER (nF) ì DVITIMER (V)
tITIMER (ms) =
IITIMER (mA)
(7)
Leave the ITIMER pin open to allow the part to activate the current limit with the minimum possible delay. Refer
to ITIMER Functional Mode Summary for more details.
22
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注
1. Current limiting based on RILIM is active during startup for both Current Limit and Circuit
Breaker variants. In case the startup current exceeds ILIM, the device regulates the current
to the set limit. However, during startup the current limit is engaged without waiting for the
ITIMER delay.
2. Shorting the ITIMER pin to ground is detected as a fault and the part shuts down. This
ensures robust eFuse behavior even in case of single point failure conditions. Refer to the
Fault Response section for details on the device behavior after a fault.
3. Larger ITIMER capacitors take longer to charge during start-up and may lead to
incorrect fault assertion if the ITIMER voltage is still below the pin short detection
threshold after the device has reached steady state. To avoid this, it is recommended to
limit the maximum ITIMER capacitor to the value suggested by the equation below.
tGHI
CITIMER <
53000
VIN + 3.6V
≈
’
tGHI = tD,ON + Cdvdt ì
∆
«
÷
◊
Idvdt
Where
•
tGHI is the time taken by the device to reach steady state
tD,ON is the device turn-on delay
Cdvdt is the dVdt capacitance
•
•
•
Idvdt is the dVdt charging current
It is possible to avoid incorrect ITIMER pin fault assertion and achieve higher ITIMER
intervals if needed by increasing the dVdt capacitor value accordingly, but at the expense
of higher start-up time.
During current regulation, the output voltage will drop resulting in increased device power dissipation across the
FET. If the device internal temperature (TJ) exceeds the thermal shutdown threshold (TSD), the FET is turned
off. See Overtemperature Protection (OTP) for more details on device response to overtemperature.
8.3.3.4 Short-Circuit Protection
During an output short-circuit event, the current through the device increases very rapidly. When an output short-
circuit is detected, the internal fast-trip comparator turns off the output within the tSC. The comparator employs a
scalable threshold which is equal to 2.1 × ILIM. This enables the user to adjust the fast-trip threshold as per
system needs rather than using a fixed threshold which may not be suitable for all systems. After a fast trip
event, the device restarts in a current limited mode to try and restore power to the load quickly in case the fast
trip was triggered by a transient event. However, if the fault is persistent, the device will stay in current limit
causing the junction temperature to rise and eventually enter thermal shutdown. See Overtemperature Protection
(OTP) section for details on the device response to overtemperature.
In some of the systems, for example servers or telecom equipment which house multiple hot-pluggable cards
connected to a common supply backplane, there can be transients on the supply due to switching of large
currents through the inductive backplane. This can result in current spikes on adjacent cards which could be
potentially large enough to inadvertently trigger the fast-trip comparator of the eFuse. The TPS25982 uses a
proprietary algorithm to avoid nuisance tripping in such cases thereby facilitating un-interrupted system
operation.
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Input Line
Transient
Persistent Output Short-Circuit
Thermal Shutdown
Output Short-Circuit Removed
Temporary Output
Short-Circuit
Retry Timer Elapsed
IN
0
tSC
tSC
2.1 x ILIM
IOUT
ILIM
0
No Fast-trip
Fast-trip
Fast-trip
VIN
OUT
dVdt Limited
Start-up
Current Limited
Start-up
0
VPG
PG
tRETRY_DLY
0
TSD
TSDHYS
TJ
Time
图 46. Input Line Transient and Output Short-Circuit Response
注
To prevent the current limit/circuit breaker loop from interfering with the input line transient
detection logic, TI recommends to set the ITIMER interval higher than 100 μs. Refer to 表
1 for more details on ITIMER.
8.3.4 Overtemperature Protection (OTP)
The device monitors the internal die temperature (TJ) at all times and shuts down the part as soon as the
temperature exceeds a safe operating level (TSD) thereby protecting the device from damage. The device will
not turn back on until the die cools down sufficiently, that is the die temperature falls below (TSD - TSDHys).
Thereafter, the part can be configured to either remain latched off or restart automatically. Refer to the Fault
Response section for details.
8.3.5 Analog Load Current Monitor (IMON)
The device allows the system to monitor the output load current accurately by providing an analog current on the
IMON pin which is proportional to the current through the FET. The user can connect a resistor from IMON to
ground to convert this signal to a voltage which can be fed to the input of an Analog-to-Digital Converter. The
internal amplifier on the IMON employs chopper based offset cancellation techniques to provide accurate
measurement even at lower currents over time and temperature.
VIMON V = G
mA / A ìI
A ìR
W
IMON
OUT
IMON
(8)
24
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It is recommended to limit the maximum IMON voltage to the values mentioned in VIMON(Max) Recommended
Values . This is to ensure the IMON pin internal amplifier has sufficient headroom to operate linearly.
表 2. VIMON(MAX) Recommended Values
VIN
Recommended VIMON(MAX)
2.7 V
3.3 V
> 5 V
1 V
1.8 V
3.3 V
It is recommended to add a RC low pass filter on the IMON output to filter out any glitches and get a smooth
average current measurement. TI recommends a series resistance of 10 kΩ or higher.
8.3.6 Power Good (PG)
PG is an active high open drain output which indicates whether the FET is fully turned ON and the output voltage
has reached the maximum value. After power-up, PG is pulled low initially. The gate driver circuit starts charging
the gate capacitance from the internal charge pump. When the FET gate voltage reaches (VIN + 3.6V), PG is
asserted after a de-glitch time (tPGD). During normal operation, if at any time VOUT falls below (VIN - VPGTHD), PG
is de-asserted after a de-glitch time (tPGD).
Overcurrent Removed
Device Enabled
Overcurrent Event
VUVLO(R)
0
EN/UVLO
IN
Slew rate (dVdt) controlled
startup/Inrush current limiting
0
VIN
Current limiting
operation
VPGTHD
OUT
PG
0
VPG
0
120 µs
120 µs
120 µs
VIN
dVdT
0
VIN + 3.6V
VGate
tITIMER
0
ILIM
IINRUSH
0
IOUT
Time
图 47. Power Good Assertion and De-assertion
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注
1. When there is no supply to the device, the PG pin is expected to stay low. However,
there is no active pull-down in this condition to drive this pin all the way down to 0 V. If the
PG pin is pulled up to an independent supply which is present even if the TPS25982 is
unpowered, there can be a small voltage seen on this pin depending on the pin sink
current, which in turn is a function of the pull-up supply voltage and resistor. Minimize the
sink current to keep this pin voltage low enough not to be detected as a logic HIGH by
associated external circuits in this condition.
2. The PG pin provides a mechanism to detect a possible failed MOSFET condition during
start-up. If the PG does not get asserted for an extended period of time after the device is
powered up and enabled, it might be an indication of internal MOSFET failure.
8.3.7 Load Detect/Handshake (LDSTRT)
The LDSTRT pin provides a mechanism for the downstream load circuit to indicate to the TPS25982 that the
load is present and has powered up successfully. This allows the system to have additional control over the
conditions in which power is presented to the load and disconnect the power when the load is not present or
unable to provide a valid handshake signal after an expected boot-up time.
Once the TPS25982 completes the startup sequence and the output reaches the full voltage, it asserts the PG
signal. At the same time, it also starts charging the capacitor on the LDSTRT pin (CLDSTRT) with an internal
current source (ILDSTRT). If the LDSTRT pin voltage rises above VLDSTRT before the load circuit pulls it low, the
TPS25982 detects the condition as a LDSTRT fault and turns off the FET to power down the load. The time to
trigger the LDSTRT fault can be calculated from the following equation:
CLDSTRT (nF) ì VLDSTRT (V)
tLDSTRT (ms) =
ILDSTRT (mA)
(9)
During normal operation, if at any time the load circuit releases the active pull-down on the LDSTRT pin, the
capacitor CLDSTRT would start charging up again and eventually trigger a shutdown due to LDSTRT fault once the
capacitor charges up to VLDSTRT
.
Once the TPS25982 turns off due to LDSTRT fault, it can be turned ON again in 3 ways:
•
•
•
LDSTRT pin is driven low
Input supply voltage is driven low (< VUVP(F)) and then driven high (> VUVP(R)
EN/UVLO voltage is driven low (< VSD) and then driven high (> VUVLO(R)
)
)
Tie the LDSTRT pin to ground if this functionality is not needed.
IN
IN
0
0
EN/UVLO
EN/UVLO
OUT
0
0
VIN
VIN
OUT
0
0
VPG
VPG
PG
PG
0
0
tLDSTRT
tLDSTRT
1.2 V
2.5 V
LDSTRT
LDSTRT
1.2 V
LDSTRT pulled low by MCU
No Handshake Signal from System MCU
0
0
Time
Time
图 48. Successful LDSTRT Handshake
图 49. Unsuccessful LDSTRT Handshake
26
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The LDSTRT pin can also be used to implement a load or module detect function wherein the output power is
presented only when the load or module is plugged in. A typical use case for this function is on optical module
power supply rails in Switches/Routers or similar networking end equipment. The LDSTRT pin should be tied to a
corresponding pin on the module connector which gets pulled low by the module when it is plugged in. An
example of such a signal is ModPrsL on QSFP-DD modules.
In this scheme, initially when the TPS25982 is powered up or enabled, the output charges up and PG is
asserted. If the module is not plugged in, there is no external pull-down on the LDSTRT pin and the pin voltage
starts rising due to internal pull-up . Once the LDSTRT pin voltage exceeds VLDSTRT, the TPS25982 turns off the
output power. If the module is plugged in later, the LDSTRT pin is pulled low by the module and the TPS25982
turns on the output power.
IN
0
EN/UVLO
0
VIN
OUT
dVdt limited
0
VPG
PG
0
2.5 V
LDSTRT
1.2 V
Optical module not present
Optical module plugged in
0
Time
图 50. Optical Module Plug-In Detection Using LDSTRT
8.4 Fault Response
The following events trigger an internal fault which causes the device to shut down:
•
•
•
•
Overtemperature Protection
Circuit Breaker Operation
ITIMER pin Short to GND
ILIM pin Short to GND
Once the device shuts down due to a fault, even if the associated external fault is subsequently cleared, the fault
stays latched internally and the output cannot turn on again until the latch is reset. The fault latch can be
externally reset by one of the following methods:
•
•
Input supply voltage is driven low (< VUVP(F)
)
EN/UVLO voltage is driven low (< VSD
)
The fault latch can also be reset by an internal auto-retry logic. The user can either disable the auto-retry
behavior completely (latch-off behavior) or configure the device to auto-retry indefinitely or for a limited number of
times before latching off. The auto-retry behavior is controlled by the connections on the RETRY_DLY and
NRETRY pins.
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Fault Response (接下页)
表 3. Pin Configurable Fault Response
EN/UVLO
RETRY_DLY
X
NRETRY
DEVICE STATE
Disabled
L
X
X
H
Short to GND
No auto-retry (Latch-off)
Auto-retry 4 times with minimum delay between retries and
then latch-off
H
Open
Open
H
H
Open
Short to GND
Auto-retry indefinitely with minimum delay between retries
Capacitor to GND
Capacitor to GND
Auto-retry delay and count as per 公式 10 and 公式 11
Auto-retry 4 times with finite delay between retries as per 公
式 10 and then latch-off
H
H
Capacitor to GND
Capacitor to GND
Open
Auto-retry indefinitely with finite delay between retries as per
Short to GND
公式 10
To configure the part for a finite number of auto-retries with a finite auto-retry delay, first choose the capacitor
value on RETRY_DLY pin using the following equation.
128ì CRETRY_DLY (pF) + 4 pF ì VRETRY_DLY_HYS (V)
(
)
tRETRY_DLY (ms) =
IRETRY_DLY (mA)
(10)
(11)
Next, choose the capacitor value on the NRETRY pin using the following equation.
4ìIRETRY_DLY (mA)ìCNRETRY (pF)
NRETRY =
INRETRY (mA)ì CRETRY_DLY (pF) + 4 pF
(
)
The number of auto-retries is quantized to certain discrete levels as shown in 表 4 .
表 4. NRETRY Quantization Levels
NRETRY Calculated From 公式 11
0 < N < 4
NRETRY Actual
4
16
4 < N < 16
16 < N < 64
64
64 < N < 256
256
1024
256 < N < 1024
表 5. NRETRY and RETRY_DLY Combination Examples
Auto Retry Delay
915 ms
416 ms
91.7 ms
2.2 nF
9.3 ms
3 ms
RETRY_DLY Capacitor
22 nF
10 nF
220 pF
68 pF
No. of Auto Retries
NRETRY Capacitor
Open
4
16
47 nF
0.22 μF
1 μF
22 nF
0.1 μF
0.47 μF
1.5 μF
4.7 nF
1 nF
2.2 nF
10 nF
33 nF
220 pF
1 nF
64
22 nF
256
0.1 μF
4.7 nF
10 nF
1024
Infinite
3.3 μF
0.47 μF
Short to GND
28
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A spreadsheet design tool TPS25982xx Design Calculator is also available for simplified calculations.
Output overload followed by Thermal Shutdown
Retry Timer starts once device cools down
1st Retry
Nth Retry
IN
0
tRETRY_DLY
Thermal Shutdown
Thermal Shutdown
IOUT
ILIM
0
VIN
OUT
Programmed number of retries over,
Device Latches Off
0
TSD
TSDHYS
TJ
TJ
Time
图 51. Auto-Retry After Fault
The auto-retry logic has a mechanism to reset the count to zero if two consecutive faults occur far apart in time.
This ensures that the auto-retry response to any later fault is handled as a fresh sequence and not as a
continuation of the previous fault. If the fault which triggered the shutdown and subsequent auto-retry cycle is
cleared eventually and does not occur again for a duration equal to 7 retry delay timer periods starting from the
last fault, the auto-retry logic resets the internal auto-retry count to zero.
8.5 Device Functional Modes
The TPS25982 can be pin strapped to support various configurable functional modes.
表 6. LDSTRT Handshake Functional Modes
EN/UVLO
LDSTRT
DEVICE STATE
Disabled
ON
L
H
H
X
L
H
OFF
Refer to Load Detect/Handshake (LDSTRT) section for more details.
表 7. Fault Response Functional Modes
EN/UVLO
RETRY_DLY
X
NRETRY
DEVICE STATE
L
X
X
Disabled
H
Short to GND
No auto-retry (Latch-off)
Auto-retry 4 times with minimum delay between retries and
then latch-off
H
Open
Open
H
H
Open
Short to GND
Auto-retry indefinitely with minimum delay between retries
Capacitor to GND
Capacitor to GND
Auto-retry delay and count as per 公式 10 and 公式 11
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表 7. Fault Response Functional Modes (接下页)
EN/UVLO
RETRY_DLY
NRETRY
DEVICE STATE
Auto-retry 4 times with finite delay between retries as per 公
式 10 and then latch-off
H
Capacitor to GND
Open
Auto-retry indefinitely with finite delay between retries as per
H
Capacitor to GND
Short to GND
公式 10
Refer to Fault Response section for more details.
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9 Application and Implementation
注
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
9.1 Application Information
The TPS25982 device is an integrated 15-A eFuse that is typically used for hot-swap and power rail protection
applications. It operates from 2.7 V to 24 V with adjustable overcurrent and undervoltage protection. It also
provides optional overvoltage with various fixed internal thresholds. The device aids in controlling the inrush
current and has the flexibility to configure the number of auto-retries and retry delay. The adjustable overcurrent
blanking timer provides the functionality to allow transient overcurrent pulses without limiting or tripping. These
devices protect source, load and internal MOSFET from potentially damaging events in systems such as Server
standby rails, PCIe cards, SSDs, HDDs, Optical Modules, Routers and Switches.
The following design procedure can be used to select the supporting component values based on the application
requirement. Additionally, a spreadsheet design tool TPS25982xx Design Calculator is available in the web
product folder.
9.2 Typical Application: Standby Power Rail Protection in Datacenter Servers
VIN
TPS259824O
VOUT
12 V
IN
OUT
3.3V
LDSTRT
RVL1
1MΩ
RPG
100KΩ
EN/UVLO
NRETRY
PG
IMON
CIN
CNRETRY
2.2nF
CL
1.4mF
RL
0.1µF
RETRY_DLY
dVdt
SMCJ12A
CLDSTRT
0.1µF
RVL2
B520C-13-F
GND ITIMER
ILIM
125KΩ
RIMON
CdVdt
887Ω
CRETRY_DLY
2.2nF
10nF
RILIM
100Ω
CITIMER
4.7nF
图 52. Typical Application Schematic - Protection for Server Standby Rail
9.2.1 Design Requirements
表 8 shows the design parameters for this application example.
表 8. Design Parameters
DESIGN PARAMETER
Input voltage, VIN
EXAMPLE VALUE
12 V
Undervoltage lockout set point, VINUVLO
Maximum load current, IOUT
Current limit, ILIM
10.8 V
12 A
15 A
Transient overcurrent blanking interval (tITIMER
)
2 ms
Load capacitance, COUT
1.4 mF
10 Ω
Load at start-up, RL(SU)
Output voltage ramp time, TdVdt
Maximum ambient temperature, TA
20 ms
70 °C
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Typical Application: Standby Power Rail Protection in Datacenter Servers (接下页)
表 8. Design Parameters (接下页)
LDSTRT handshake delay, tLDSTRT
Retry delay, tRETRY_DLY
60 ms
100 ms
4
No. of retries, NRETRY
9.2.2 Detailed Design Procedure
9.2.2.1 Device Selection
This design example considers a 12-V system operating voltage with a tolerance of ±10 %. The rated load
current is 12 A. If the current exceeds 15 A, then the device must allow overload current for 2-ms interval before
breaking the circuit and then restart. Accordingly, the TPS259824O variant is chosen. (Refer to Device
Comparison Table for device options.) Ambient temperatures may range from 20 °C to 70 °C. The load has a
minimum input capacitance of 1.4 mF and start-up resistive load of 10 Ω. The downstream load is turned on only
after the PG signal is asserted.
9.2.2.2 Setting the Current Limit Threshold: RILIM Selection
The RILIM resistor at the ILIM pin sets the overload current limit, whose value can be calculated using 公式 12.
1460
RILIM W =
(
)
ILIM
( )
A - 0.11
(12)
For ILIM = 15 A, RILIM value is calculated to be 98.05 Ω. Choose the closest available standard value: 100 Ω, 1%.
Refering to the Electrical Characteristics table, it can be verified that the minimum current limit across
temperature for RILIM value of 100 Ω is 12.85 A, which is higher than the nominal rated load current (12 A),
thereby ensuring stable operation under normal conditions.
9.2.2.3 Setting the Undervoltage Lockout Set Point
The undervoltage lockout (UVLO) trip point is adjusted using the external voltage divider network of RVL1 and
RVL2 connected between IN, EN/UVLO and GND pins of the device. The resistor values required for setting the
undervoltage are calculated using 公式 13.
VUVLO(R) x (RVL1+ RVL2)
RVL2
VINUVLO =
(13)
For minimizing the input current drawn from the power supply, TI recommends to use higher values of resistance
for RVL1 and RVL2. However, leakage currents due to external active components connected to the resistor string
can add error to these calculations. So, the resistor string current, IRVL12 must be 20 times greater than the
leakage current (IENLKG).
From the device electrical specifications, UVLO rising threshold VUVLO(R) = 1.2 V. From design requirements,
VINUVLO = 10.8 V. First choose the value of RVL1 = 1 MΩ and use 公式 13 to calculate RVL2 = 125 kΩ.
Use the closest standard 1% resistor values: RVL1 = 1 MΩ, and RVL2 = 125 kΩ
9.2.2.4 Choosing the Current Monitoring Resistor: RIMON
Voltage at IMON pin VIMON is proportional to the output load current. This can be connected to an ADC of the
downstream system for monitoring the operating condition and health of the system. The RIMON must be selected
based on the maximum load current and the maximum IMON pin voltage at full-scale load current. The maximum
IMON pin voltage must be selected based on the input voltage range of the ADC used or the value suggested in
VIMON(Max) Recommended Values, whichever is lower. RIMON is set using 公式 14.
VIMONmax(V)
RIMON(W) =
-6
IOUTmax(A)ì 246 ì10
(14)
For ILIM = 15 A and considering the operating range of ADC to be 0 V to 3.3 V, RIMON can be calculated as
32
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3.3
15ì 246 ì10
RIMON =
= 894 ꢀ
-6
(15)
Selecting RIMON value less than shown in 公式 15 ensures that ADC limits are not exceeded for maximum value
of load current. Choose closest available standard value: 887 Ω, 1 %.
9.2.2.5 Setting the Output Voltage Ramp Time (TdVdt
)
For a successful design, the junction temperature of device must be kept below the absolute maximum rating
during both dynamic (start-up) and steady state conditions. Dynamic power stresses often are an order of
magnitude greater than the static stresses, so it is important to determine the right start-up time and in-rush
current limit required with system capacitance to avoid thermal shutdown during start-up with and without load.
The required ramp-up capacitor CdVdt is calculated considering the two possible cases (see Case 1: Start-Up
Without Load: Only Output Capacitance COUT Draws Current and Case 2: Start-Up With Load: Output
Capacitance COUT and Load Draw Current)
9.2.2.5.1 Case 1: Start-Up Without Load: Only Output Capacitance COUT Draws Current
During start-up, as the output capacitor charges, the voltage drop as well as the power dissipated across the
internal FET decreases. The average power dissipated in the device during start-up is calculated using 公式 16
P
D(INRUSH) = 0.5 x VIN x IINRUSH
(16)
Where IINRUSH is the inrush current and is determined by 公式 17
V
IN
I
INRUSH = COUT
ì
T
dVdt
(17)
公式 16 assumes that the load does not draw any current (apart from the capacitor charging current) until the
output voltage has reached its final value.
9.2.2.5.2 Case 2: Start-Up With Load: Output Capacitance COUT and Load Draw Current
When the load draws current during the turn-on sequence, there is additional power dissipated. Considering a
resistive load during start-up RL(SU), load current ramps up proportionally with increase in output voltage during
TdVdt time. 公式 18 shows the average power dissipation in the internal FET during charging time due to resistive
load.
2
1
V
IN
≈ ’
PD(LOAD)
=
×
∆ ÷
6
R
L(SU)
« ◊
(18)
公式 19 gives the total power dissipated in the device during start-up
PD(STARTUP) = PD(INRUSH) + PD(LOAD)
(19)
The power dissipation, with and without load, for selected start-up time must not exceed the start-up thermal
shutdown limits as shown in Thermal Shutdown Plot During Start-up
版权 © 2018–2020, Texas Instruments Incorporated
33
TPS25982
ZHCSIW7B –OCTOBER 2018–REVISED JANUARY 2020
www.ti.com.cn
200
100
50
TPS259827x
TPS259822x/23x/24x
30
20
10
5
3
2
1
0.5
2
3
4
5
6 7 8 10 20
Power Dissipation (W)
30 40 50 70 100
D002
图 53. Thermal Shutdown Plot During Start-up
For the design example under discussion, the output voltage has to be ramped up in 20 ms, which mandates a
slew-rate of 0.6 V/ms for a 12 V rail.
The required CdVdt capacitance on dVdt pin to set 0.6 V/ms slew rate can be calculated using 公式 20
4600
CdVdt pF =
= 7666 pF
(
)
SR V / ms
(
)
(20)
The dVdt capacitor is subjected to typically VIN+ 4 V during startup. The high voltage bias leads to a drop in the
effective capacitor value. So, it is suggested to choose 20% higher than the calculated value, which gives 9.2 nF.
Choose closest 10% standard value: 10 nF
The 10 nF CdVdt capacitance sets a slew-rate of 0.46 V/ms and output ramp time TdVdt of 26 ms.
The inrush current drawn by the load capacitance COUT during ramp-up can be calculated using 公式 21
12 V
I
INRUSH = 1.4 mFì
= 0.65 A
26 ms
(21)
(22)
The inrush power dissipation can be calculated using 公式 22
PD(INRUSH) = 0.5 x 12 x 0.65 = 3.9 W
For 3.9 W of power loss, the thermal shutdown time of the device must be greater than the ramp-up time TdVdt to
ensure a successful start-up. 图 53 shows the start-up thermal shutdown limit. For 3.9 W of power, the shutdown
time is approximately 100 ms. So it is safe to use 26 ms as the start-up time without any load on the output.
The additional power dissipation when a 10-Ω load is present during start-up is calculated using 公式 23
1
122
10
≈ ’
PD(LOAD)
=
ì
= 2.4W
∆ ÷
6
« ◊
(23)
(24)
The total device power dissipation during start-up can be calculated using 公式 24
PD(STARTUP) = 3.9 + 2.4 = 6.3 W
From Thermal Shutdown Plot During Start-up, the thermal shutdown time for 6.3 W is approximately 40 ms. It is
safe to have 30% margin to allow for variation of system parameters such as load, component tolerance, and
input voltage. So it is well within acceptable limits to use the 10 nF for CdVdt capacitor with start-up load of 10 Ω.
When COUT is large, there is a need to decrease the power dissipation during start-up. This can be done by
increasing the value of the CdVdt capacitor. A spreadsheet tool TPS25982xx Design Calculator available on the
web can be used for iterative calculations.
34
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TPS25982
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ZHCSIW7B –OCTOBER 2018–REVISED JANUARY 2020
9.2.2.6 Setting the Load Handshake (LDSTRT) Delay
To indicate a successful start-up, the load circuit must provide a handshake signal to TPS25982 by pulling down
the LDSTRT pin within the time set by the capacitor CLDSTRT on the LDSTRT pin. Once the PG asserts, the
device sources 2-μA current into CLDSTRT. For a successful handshake, the load circuit must pull-down the
LDSTRT pin before CLDSTRT charges up to 1.2 V.
For the design requirement of 60-ms handshake delay, use 公式 25 to calculate CLDSTRT
tLDSTRT
60ms
1.2V
CLDSTRT = ILDSTRT ì
= 2mA ì
= 0.1mF
VLDSTRT
(25)
Choose closest available standard value: 0.1 µF, 10 %.
9.2.2.7 Setting the Transient Overcurrent Blanking Interval (tITIMER
)
For the design example under discussion, overcurrent transients are allowed for 2-ms duration. This blanking
interval can be set by selecting appropriate capacitor CITIMER from ITIMER pin to ground. The value of CITIMER to
set 2 ms for tITIMER can be calculated using 公式 26.
tITIMER (ms)
CITIMER (nF) =
= 4.255 nF
0.47
(26)
Choose closest available standard value: 4.7 nF, 10 %.
9.2.2.8 Setting the Auto-Retry Delay and Number of Retries
The time delay between retries can be programmed by selecting capacitor CRETRY_DLY on RETRY_DLY pin. The
value of CRETRY_DLY to set a 100-ms auto-retry delay can be calculated using 公式 27.
tRETRY_DLY (ms)
46.83
CRETRY_DLY (pF) =
- 4 pF = 2131.38 pF
(27)
Choose closest available standard value: 2.2 nF, 10 %.
The number of auto-retry attempts can be set by a capacitor CNRETRY on the NRETRY pin using 公式 28
4ìCNRETRY (pF)
CRETRY_DLY (pF) + 4 pF
NRETRY =
(28)
For this design example, the requirement is to retry 4 times after the device shuts down due to a fault. Since, the
number of auto-retries can be adjusted in discrete steps as explained in Fault Response , choose CNRETRY such
that NRETRY is less than 4. Use 公式 29 to calculate CNRETRY
.
NRETRY ì CRETRY_DLY (pF) + 4 pF
(
)
< 2204 pF
CNRETRY (pF) <
4
(29)
Choose closest available standard value: 2.2 nF, 10 %.
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35
TPS25982
ZHCSIW7B –OCTOBER 2018–REVISED JANUARY 2020
www.ti.com.cn
9.2.3 Application Curves
COUT = 1.4 mF
CdVdt = 10 nF
RL(SU) = Open
COUT = 1.4 mF
CdVdt = 10 nF
RL(SU) = 10 Ω
图 54. Hot-Plug Start-Up Without Load on Output - dVdt
图 55. Hot-Plug Start-Up With Load on Output - dVdt
Limited
Limited
RILIM = 100 Ω
CITIMER = 4.7 nF
RILIM = 100 Ω
CITIMER = 4.7 nF CRETRY_DLY = 2.2 nF,
CNRETRY = 2.2 nF
图 57. Circuit Breaker - Auto-Retry 4 Times With Retry
图 56. Circuit Breaker With Transient Overcurrent Blanking
Delay of 100 ms
Interval of 2 ms
36
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TPS25982
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ZHCSIW7B –OCTOBER 2018–REVISED JANUARY 2020
RILIM = 100 Ω
图 58. Output Hard Short-Circuit While ON
RILIM = 100 Ω
图 59. Output Hard Short-Circuit While ON (Zoomed In)
图 60. Power-Up With Short-Circuit on Output
图 61. Power-Up With Short-Circuit on Output - Auto-Retry
4 Times With Retry Delay of 100 ms
CLDSTRT = 0.1 μF
图 62. Successful Load Handshake (LDSTRT)
CLDSTRT = 0.1 μF
图 63. Unsuccessful Load Handshake (LDSTRT)
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37
TPS25982
ZHCSIW7B –OCTOBER 2018–REVISED JANUARY 2020
www.ti.com.cn
9.3 System Examples
9.3.1 Optical Module Power Rail Path Protection
Optical modules are commonly used in high-bandwidth data communication systems such as Optical Networking
equipment, Enterprise/Data-Center Switches and Routers. Several variants of optical modules are available in
the market, which differ in the form-factor and the data speed support (Gbit/s). Of these, the popular variant
Double Dense Quad Small Form-factor Pluggable (QSFP-DD) module supports speeds up to 400 Gbit/s. In
addition to the system protection during hot-plug events, the other key requirement for optical module is the tight
voltage regulation. The optical module uses 3.3 V supply and requires voltage regulation within ±5 % for proper
operation.
A typical power tree of such system is shown in 图 64. The optical line card consists of DC-DC converter,
protection device (eFuse) and power supply filters. The DC-DC converter steps-down the 12 V to 3.3 V and
maintains the 3.3 V rail within ±2 %. The power supply filtering network uses ‘LC’ components to reduce high
frequency noise injection into the optical module. The DC resistance of the inductor ‘L’ causes voltage drop of
around 1.5 % which leaves us with a voltage drop budget of just 1.5 % (3.3 V * 1.5% = 50 mV) across the
protection device. Considering a maximum load current of 5.5 A per module, the maximum ON-resistance of the
protection device should be less than 9 mΩ. TPS25982 eFuse offers ultra-low ON-resistance of 2.7 mΩ (typical)
and 4.5 mΩ (maximum, across temperature), thereby meeting the target specification with additional margin to
spare and simplifying the overall system design.
VIN
12V
3.3V
VOUT
IN
OUT
VccTx
VccRx
DC-DC
eFuse
LDSTRT
QSFP
Module
Hot Plug / Unplug
Vcc
GND
ModPrsL
Optical Line Card
图 64. Power Tree Block Diagram of a Typical Optical Line Card
As shown in 图 64, ModPrsL signal acts as a handshake signal between the line card and the optical module.
ModPrsL is always pulled to ground inside the module. When the module is hot-plugged into the host “Optical
Line Card” connector, the ModPrsL signal pulls down the LDSTRT pin and enables the TPS25982 eFuse to
power the module. This ensures that power is applied on the port only when a module is plugged in and
disconnected when there is no module present.
38
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TPS25982
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ZHCSIW7B –OCTOBER 2018–REVISED JANUARY 2020
System Examples (接下页)
TPS259822O
VOUT
VIN
IN
OUT
3.3V
LDSTRT
RPG
100KΩ
EN/UVLO
NRETRY
PG
IMON
CL
CIN
CNRETRY
0.1µF
OPEN
RL
RETRY_DLY
dVdt
10µF
B520C-13-F
CLDSTRT
0.1µF
GND ITIMER
ILIM
RIMON
CdVdt
1910Ω
CRETRY_DLY
OPEN
3.3nF
RILIM
210Ω
CITIMER
15nF
图 65. TPS259822O Configured for a 3.3-V Power Rail Path Protection in Optical Module
9.3.1.1 Design Requirements
表 9 shows the design parameters for this example.
表 9. Design Parameters
DESIGN PARAMETER
Input voltage, VIN
EXAMPLE VALUE
3.3 V
3.7 V
± 5 %
5.5 A
7 A
Overvoltage lockout, VOVP
Maximum voltage drop in the path
Maximum load current, IOUT
Current limit, ILIM
Transient overcurrent blanking interval (tITIMER
)
6 ms
10 µF
85 °C
Yes
Load capacitance, COUT
Maximum ambient temperature, TA
Module present detection, ModPrsL
Retry delay, tRETRY_DLY
200 µs
4
No. of retries, NRETRY
9.3.1.2 Device Selection
Optical modules are very sensitive to supply voltage variations and thus require input overvoltage protection.
TPS259822O variant from TPS25982 family is selected to set overvoltage protection at 3.7 V. TPS259822O
allows overcurrents for a user specified blanking interval tITIMER before breaking the circuit path. In this use case,
tITIMER is set for 6 ms interval.
9.3.1.3 External Component Settings
By following similar design procedure as outlined in Detailed Design Procedure, the external component values
are calculated as below
•
•
•
•
•
RILIM = 210 Ω to set 7-A current limit
CITIMER = 15 nF to set fault blanking time of 6 ms
RIMON = 1910 Ω to set maximum IMON pin voltage VIMON within ADC range of 3.3 V
CdVdt capacitance is chosen as 3.3 nF
Leave RETRY_DLY and NRETRY pins OPEN to set minimum auto-retry delay of 200 μs and number of
retries to 4
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ZHCSIW7B –OCTOBER 2018–REVISED JANUARY 2020
www.ti.com.cn
9.3.1.4 Voltage Drop
表 10 shows the power path voltage drop (%) due to the eFuse in QSFP modules of different power classes.
表 10. Voltage Drop across TPS25982 on QSFP Module Power Rail
POWER CLASS
MAXIMUM POWER
CONSUMPTION PER MODULE
(W)
MAXIMUM LOAD CURRENT (A) TYPICAL VOLTAGE DROP (%)
1
2
3
4
5
6
7
8
1.5
3.5
7
0.454
1.06
2.12
2.42
3.03
3.63
4.24
5.45
0.037
0.087
0.174
0.2
8
10
12
14
18
0.248
0.3
0.347
0.446
9.3.1.5 Application Curves
图 66. Output Voltage Profile When Optical Module is
图 67. Output Voltage Profile When Optical Module is
Inserted
Plugged Out
40
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TPS25982
www.ti.com.cn
ZHCSIW7B –OCTOBER 2018–REVISED JANUARY 2020
图 68. Circuit Breaker With Transient Overcurrent Blanking
图 69. Overload Response and Recovery
Interval of 6 ms; Device Restarts in Current Limit Mode
图 70. Overvoltage Cut-off at 3.7 V with TPS259822O
图 71. Overvoltage Protection Response and Recovery
Device
with TPS259822O Device
9.3.2 Input Protection for 12-V Rail Applications: PCIe Cards, Storage Interfaces and DC Fans
TPS25982 eFuse provides inrush current management and also protects the system from most common faults
such as undervoltage, overvoltage and overcurrents. The combination of high current support along with low ON-
resistance makes TPS25982 eFuse an ideal protection solution for PCIe cards, Storage Interfaces and DC Fan
loads. The external component values can be calculated by following the design procedure outlined in Detailed
Design Procedure. Alternatively, a spreadsheet design tool TPS25982xx Design Calculator is available for
simplified design efforts.
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ZHCSIW7B –OCTOBER 2018–REVISED JANUARY 2020
www.ti.com.cn
10 Power Supply Recommendations
The TPS25982 devices are designed for a supply voltage range of 2.7 V ≤ VIN ≤ 24 V. TI recommends an input
ceramic bypass capacitor higher than 0.1 μF if the input supply is located more than a few inches from the
device. The power supply must be rated higher than the set current limit to avoid voltage droops during
overcurrent and short-circuit conditions.
10.1 Transient Protection
In the case of a short circuit and overload current limit when the device interrupts current flow, the input
inductance generates a positive voltage spike on the input, and the output inductance generates a negative
voltage spike on the output. The peak amplitude of voltage spikes (transients) is dependent on the value of
inductance in series to the input or output of the device. Such transients can exceed the absolute maximum
ratings of the device if steps are not taken to address the issue. Typical methods for addressing transients
include:
•
•
•
•
Minimize lead length and inductance into and out of the device.
Use a large PCB GND plane.
Use a Schottky diode across the output to absorb negative spikes.
Use a low value ceramic capacitor CIN = 0.001 μF to 0.1 μF to absorb the energy and dampen the transients.
The approximate value of input capacitance can be estimated using 公式 30.
LIN
VSPIKE(Absolute) = VIN + ILOAD x
CIN
where
•
•
•
•
VIN is the nominal supply voltage
ILOAD is the load current
LIN equals the effective inductance seen looking into the source
CIN is the capacitance present at the input
(30)
Some of the applications may require the addition of a Transient Voltage Suppressor (TVS) to prevent transients
from exceeding the absolute maximum ratings of the device. A typical circuit implementation with optional
protection components (a ceramic capacitor, TVS and Schottky diode) is shown in 图 72.
TPS25982
IN
OUT
12V
3.3V
LDSTRT
1MO
100kO
100O
EN/UVLO
NRETRY
PG
IMON
220uF
0.1uF
RETRY_DLY
dVdt
1uF
56pF
56pF
137kO
GND ITIMER
ILIM
511O
3.3nF
4.7nF
100O
图 72. Typical Circuit Implementation With Optional Protection Components
42
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TPS25982
www.ti.com.cn
ZHCSIW7B –OCTOBER 2018–REVISED JANUARY 2020
10.2 Output Short-Circuit Measurements
It is difficult to obtain repeatable and similar short-circuit testing results. The following contribute to variation in
results:
•
•
•
•
•
•
•
Source bypassing
Input leads
Board layout
Component selection
Output shorting method
Relative location of the short
Instrumentation
The actual short exhibits a certain degree of randomness because it microscopically bounces and arcs. Ensure
that configuration and methods are used to obtain realistic results.
注
Do not expect to see waveforms exactly like the waveforms in this data sheet because
every setup is different.
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ZHCSIW7B –OCTOBER 2018–REVISED JANUARY 2020
www.ti.com.cn
11 Layout
11.1 Layout Guidelines
•
The IN Exposed Thermal Pad is used for Heat Dissipation. Connect to as much copper area as possible
using an array of thermal vias. The via array also helps to minimize the voltage gradient across the VIN pad
and facilitates uniform current distribution through the internal FET, which improves the current sensing and
monitoring accuracy.
•
•
•
•
•
For all applications, TI recommends a ceramic decoupling capacitor of 0.01 μF or greater between IN and
GND terminals. For hot-plug applications, where input power-path inductance is negligible, this capacitor can
be eliminated or minimized.
The optimal placement of the decoupling capacitor is closest to the IN and GND terminals of the device. Care
must be taken to minimize the loop area formed by the bypass-capacitor connection, the IN terminal, and the
GND terminal of the IC.
High current carrying power path connections must be as short as possible and must be sized to carry at
least twice the full-load current. It is recommended to use a minimum trace width of 50 mil for the OUT power
connection.
The GND terminal is the reference for all internal signals and must be isolated from any bounce due to large
switching currents in the system power ground plane. It is recommended to connect the device GND to a
signal ground island on the board, which in turn is connected to the system power GND plane at one point.
Locate the support components for the following signals close to their respective connection pins - ILIM,
IMON, ITIMER, RETRY_DLY, NRETRY and dVdT with the shortest possible trace routing to reduce parasitic
effects on the respective associated functions. These traces must not have any coupling to switching signals
on the board.
•
•
•
The ILIM pin is highly sensitive to capacitance and TI recommends to pay special attention to the layout to
maintain the parasitic capacitance below 30 pF for stable operation.
Use short traces on the RETRY_DLY and NRETRY pins to ensure the auto-retry timer delay and number of
auto-retries is not altered by the additional parasitic capacitance on these pins.
Protection devices such as TVS, snubbers, capacitors, or diodes must be placed physically close to the
device they are intended to protect. These protection devices must be routed with short traces to reduce
inductance. For example, TI recommends a protection Schottky diode to address negative transients due to
switching of inductive loads, and it must be physically close to the OUT pins.
•
•
Use proper layout and thermal management techniques to ensure there is no significant steady state thermal
gradient between the two thermal pads on the IC. This is necessary for proper functioning of the device
overtemperature protection mechanism and successful startup under all conditions.
Obtaining acceptable performance with alternate layout schemes is possible; the Layout Example is intended
as a guideline and shown to produce good results from electrical and thermal standpoint.
44
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TPS25982
www.ti.com.cn
ZHCSIW7B –OCTOBER 2018–REVISED JANUARY 2020
11.2 Layout Example
PCB via to Bottom Layer
VIN Plane (Top Layer)
Blind PCB via to Inner Layer
VOUT Plane (Top Layer)
> 50 mils
*
*
*
*
Signal GND (Top Layer)
Power GND Plane (Top Layer)
* Optional components for suppressing transients induced while
switching current through inductive elements at input/output
图 73. TPS25982 Example PCB Layout
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ZHCSIW7B –OCTOBER 2018–REVISED JANUARY 2020
www.ti.com.cn
12 器件和文档支持
12.1 文档支持
12.1.1 相关文档
请参阅如下相关文档：
•
•
•
《TPS259824OEVM 电子保险丝评估板》
《TPS259827LEVM 电子保险丝评估板》
《TPS25982xx 设计计算器》
12.1.1.1 相关链接
下表列出了快速访问链接。类别包括技术文档、支持和社区资源、工具和软件，以及立即订购快速访问。
表 11. 相关链接
器件
产品文件夹
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立即订购
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技术文档
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工具和软件
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支持和社区
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单击此处
TPS259822L
TPS259823L
TPS259824L
TPS259827L
TPS259822O
TPS259823O
TPS259824O
TPS259827O
12.2 接收文档更新通知
要接收文档更新通知，请导航至 ti.com.cn 上的器件产品文件夹。单击右上角的通知我进行注册，即可每周接收产
品信息更改摘要。有关更改的详细信息，请查看任何已修订文档中包含的修订历史记录。
12.3 社区资源
TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help — straight
from the experts. Search existing answers or ask your own question to get the quick design help you need.
Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do
not necessarily reflect TI's views; see TI's Terms of Use.
12.4 商标
E2E is a trademark of Texas Instruments.
12.5 静电放电警告
ESD 可能会损坏该集成电路。德州仪器 (TI) 建议通过适当的预防措施处理所有集成电路。如果不遵守正确的处理措施和安装程序 , 可
能会损坏集成电路。
ESD 的损坏小至导致微小的性能降级 , 大至整个器件故障。 精密的集成电路可能更容易受到损坏 , 这是因为非常细微的参数更改都可
能会导致器件与其发布的规格不相符。
12.6 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
13 机械、封装和可订购信息
以下页面包含机械、封装和可订购信息。这些信息是指定器件的最新可用数据。数据如有变更，恕不另行通知，且
不会对此文档进行修订。如需获取此数据表的浏览器版本，请查阅左侧的导航栏。
46
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PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
RGE
RGE
RGE
RGE
RGE
RGE
RGE
RGE
RGE
RGE
RGE
RGE
RGE
RGE
RGE
RGE
Qty
(1)
(2)
(3)
(4/5)
(6)
TPS259822LNRGER
TPS259822LNRGET
TPS259822ONRGER
TPS259822ONRGET
TPS259823LNRGER
TPS259823LNRGET
TPS259823ONRGER
TPS259823ONRGET
TPS259824LNRGER
TPS259824LNRGET
TPS259824ONRGER
TPS259824ONRGET
TPS259827LNRGER
TPS259827LNRGET
TPS259827ONRGER
TPS259827ONRGET
ACTIVE
VQFN
VQFN
VQFN
VQFN
VQFN
VQFN
VQFN
VQFN
VQFN
VQFN
VQFN
VQFN
VQFN
VQFN
VQFN
VQFN
24
24
24
24
24
24
24
24
24
24
24
24
24
24
24
24
3000 RoHS & Green
250 RoHS & Green
3000 RoHS & Green
250 RoHS & Green
3000 RoHS & Green
250 RoHS & Green
3000 RoHS & Green
250 RoHS & Green
3000 RoHS & Green
250 RoHS & Green
3000 RoHS & Green
250 RoHS & Green
3000 RoHS & Green
250 RoHS & Green
3000 RoHS & Green
NIPDAUAG
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
TP2598
22LN
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
NIPDAUAG
NIPDAUAG
NIPDAUAG
NIPDAUAG
NIPDAUAG
NIPDAUAG
NIPDAUAG
NIPDAUAG
NIPDAUAG
NIPDAUAG
NIPDAUAG
NIPDAUAG
NIPDAUAG
NIPDAUAG
NIPDAUAG
TP2598
22LN
TP2598
22ON
TP2598
22ON
TP2598
23LN
TP2598
23LN
TP2598
23ON
TP2598
23ON
TP2598
24LN
TP2598
24LN
TP2598
24ON
TP2598
24ON
TP2598
27LN
TP2598
27LN
TP2598
27ON
250
RoHS & Green
TP2598
27ON
(1) The marketing status values are defined as follows:
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
17-Apr-2023
TAPE AND REEL INFORMATION
REEL DIMENSIONS
TAPE DIMENSIONS
K0
P1
W
B0
Reel
Diameter
Cavity
A0
A0 Dimension designed to accommodate the component width
B0 Dimension designed to accommodate the component length
K0 Dimension designed to accommodate the component thickness
Overall width of the carrier tape
W
P1 Pitch between successive cavity centers
Reel Width (W1)
QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE
Sprocket Holes
Q1 Q2
Q3 Q4
Q1 Q2
Q3 Q4
User Direction of Feed
Pocket Quadrants
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
TPS259822LNRGER
TPS259822LNRGET
TPS259822ONRGER
TPS259822ONRGET
TPS259823LNRGER
TPS259823LNRGET
TPS259823ONRGER
TPS259823ONRGET
TPS259824LNRGER
TPS259824LNRGET
TPS259824ONRGER
TPS259824ONRGET
TPS259827LNRGER
TPS259827LNRGET
TPS259827ONRGER
TPS259827ONRGET
VQFN
VQFN
VQFN
VQFN
VQFN
VQFN
VQFN
VQFN
VQFN
VQFN
VQFN
VQFN
VQFN
VQFN
VQFN
VQFN
RGE
RGE
RGE
RGE
RGE
RGE
RGE
RGE
RGE
RGE
RGE
RGE
RGE
RGE
RGE
RGE
24
24
24
24
24
24
24
24
24
24
24
24
24
24
24
24
3000
250
330.0
180.0
330.0
180.0
330.0
180.0
330.0
180.0
330.0
180.0
330.0
180.0
330.0
180.0
330.0
180.0
12.4
12.5
12.4
12.5
12.4
12.5
12.4
12.5
12.4
12.5
12.4
12.5
12.4
12.5
12.4
12.5
4.35
4.35
4.35
4.35
4.35
4.35
4.35
4.35
4.35
4.35
4.35
4.35
4.35
4.35
4.35
4.35
4.35
4.35
4.35
4.35
4.35
4.35
4.35
4.35
4.35
4.35
4.35
4.35
4.35
4.35
4.35
4.35
1.1
1.1
1.1
1.1
1.1
1.1
1.1
1.1
1.1
1.1
1.1
1.1
1.1
1.1
1.1
1.1
8.0
8.0
8.0
8.0
8.0
8.0
8.0
8.0
8.0
8.0
8.0
8.0
8.0
8.0
8.0
8.0
12.0
12.0
12.0
12.0
12.0
12.0
12.0
12.0
12.0
12.0
12.0
12.0
12.0
12.0
12.0
12.0
Q2
Q2
Q2
Q2
Q2
Q2
Q2
Q2
Q2
Q2
Q2
Q2
Q2
Q2
Q2
Q2
3000
250
3000
250
3000
250
3000
250
3000
250
3000
250
3000
250
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
17-Apr-2023
TAPE AND REEL BOX DIMENSIONS
Width (mm)
H
W
L
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SPQ
Length (mm) Width (mm) Height (mm)
TPS259822LNRGER
TPS259822LNRGET
TPS259822ONRGER
TPS259822ONRGET
TPS259823LNRGER
TPS259823LNRGET
TPS259823ONRGER
TPS259823ONRGET
TPS259824LNRGER
TPS259824LNRGET
TPS259824ONRGER
TPS259824ONRGET
TPS259827LNRGER
TPS259827LNRGET
TPS259827ONRGER
TPS259827ONRGET
VQFN
VQFN
VQFN
VQFN
VQFN
VQFN
VQFN
VQFN
VQFN
VQFN
VQFN
VQFN
VQFN
VQFN
VQFN
VQFN
RGE
RGE
RGE
RGE
RGE
RGE
RGE
RGE
RGE
RGE
RGE
RGE
RGE
RGE
RGE
RGE
24
24
24
24
24
24
24
24
24
24
24
24
24
24
24
24
3000
250
338.0
205.0
338.0
205.0
338.0
205.0
338.0
205.0
338.0
205.0
338.0
205.0
338.0
205.0
338.0
205.0
355.0
200.0
355.0
200.0
355.0
200.0
355.0
200.0
355.0
200.0
355.0
200.0
355.0
200.0
355.0
200.0
50.0
33.0
50.0
33.0
50.0
33.0
50.0
33.0
50.0
33.0
50.0
33.0
50.0
33.0
50.0
33.0
3000
250
3000
250
3000
250
3000
250
3000
250
3000
250
3000
250
Pack Materials-Page 2
GENERIC PACKAGE VIEW
RGE 24
VQFN - 1 mm max height
PLASTIC QUAD FLATPACK - NO LEAD
Images above are just a representation of the package family, actual package may vary.
Refer to the product data sheet for package details.
4204104/H
PACKAGE OUTLINE
RGE0024M
VQFN - 1 mm max height
S
C
A
L
E
3
.
0
0
0
PLASTIC QUAD FLATPACK - NO LEAD
4.1
3.9
B
A
0.475
0.275
PIN 1 INDEX AREA
4.1
3.9
0.29
0.19
DETAIL
OPTIONAL TERMINAL
TYPICAL
1.0
0.8
C
SEATING PLANE
0.08 C
0.05
0.00
2X 2.7 0.1
4X 2.5
(0.2) TYP
7
12
SEE TERMINAL
DETAIL
EXPOSED
THERMAL PAD
6
13
26
25
0.85 0.1
(0.925)
SYMM
(0.625)
1.45 0.1
1
18
0.29
0.19
24X
24
19
0.1
0.05
C A B
SYMM
PIN 1 ID
(OPTIONAL)
0.475
0.275
24X
2X 0.5
4223975/B 03/2018
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. The package thermal pad must be soldered to the printed circuit board for thermal and mechanical performance.
www.ti.com
EXAMPLE BOARD LAYOUT
RGE0024M
VQFN - 1 mm max height
PLASTIC QUAD FLATPACK - NO LEAD
(2.7)
SYMM
24
19
24X (0.575)
24X (0.24)
1
18
(0.625)
(1.45)
25
26
(1.1)
TYP
(R0.05)
TYP
SYMM
(3.825)
(0.925)
TYP
(0.15)
TYP
20X (0.5)
(0.85)
13
6
(
0.2) TYP
VIA
7
12
6X (1.1)
(3.825)
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE:15X
0.07 MIN
ALL AROUND
0.07 MAX
ALL AROUND
SOLDER MASK
OPENING
METAL
EXPOSED
METAL
EXPOSED
METAL
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
NON SOLDER MASK
DEFINED
SOLDER MASK
DEFINED
(PREFERRED)
SOLDER MASK DETAILS
4223975/B 03/2018
NOTES: (continued)
4. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature
number SLUA271 (www.ti.com/lit/slua271).
5. Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to their locations shown
on this view. It is recommended that vias under paste be filled, plugged or tented.
www.ti.com
EXAMPLE STENCIL DESIGN
RGE0024M
VQFN - 1 mm max height
PLASTIC QUAD FLATPACK - NO LEAD
4X (1.188)
4X (0.694)
19
24
24X (0.575)
1
25
18
24X (0.24)
2X
(1.3)
(R0.05) TYP
2X
(0.625)
SYMM
(3.825)
26
2X
(0.925)
2X
(0.76)
20X (0.5)
13
6
METAL
TYP
7
12
SYMM
(3.825)
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
EXPOSED PAD 25
78% PRINTED SOLDER COVERAGE BY AREA UNDER PACKAGE
SCALE:20X
4223975/B 03/2018
NOTES: (continued)
6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
www.ti.com
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Copyright © 2023，德州仪器 (TI) 公司
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