TPS259850RQPR [TI]
具有准确、快速电流监测器的 4.5V 至 16V、0.59mΩ、80A 可堆叠紧凑型电子保险丝 | RQP | 26 | -40 to 125;
| 型号： | TPS259850RQPR |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 具有准确、快速电流监测器的 4.5V 至 16V、0.59mΩ、80A 可堆叠紧凑型电子保险丝 | RQP | 26 | -40 to 125 电子 |
| 文件： | 总67页 (文件大小：6861K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
TPS25985
ZHCSOF5A –MAY 2022 –REVISED SEPTEMBER 2022
具有准确、快速电流监测器的TPS25985x 4.5V 至16V、0.59mΩ、80A 可堆叠电
子保险丝
1 特性
2 应用
• 输入工作电压范围：4.5 V 至16 V
• 输入热插拔
• 服务器和高性能计算
• 网络接口卡
• 显卡和硬件加速器卡
• 数据中心交换机和路由器
• 风扇托盘
– 绝对最大值为20V
– 输出端可耐受高达-1V 的负电压
• 具有低导通电阻的集成FET：0.59mΩ（典型值）
• 额定电流为60A RMS，峰值电流为80A
• 支持多个电子保险丝并行连接，从而支持更高的电
流
3 说明
– 启动和稳态期间的主动器件状态同步和负载共
享，可实现巨大的可扩展性
• 强大的过流保护
TPS25985x 是采用小型封装的集成式高电流电路保护
和电源管理解决方案。该器件只需很少的外部元件即可
提供多种保护模式，能够非常有效地抵御过载、短路和
过多浪涌电流。
– 可调过流阈值(IOCP)：10A 至60A，精度为
±6%（最大）
– 在稳态运行期间，断路器通过可调瞬态消隐计时
器(ITIMER) 进行响应，可支持高达2 × IOCP 的
峰值电流
浪涌电流有特别要求的应用可以通过单个外部电容器设
定输出转换率。用户可根据系统需求设置输出电流限制
电平。借助用户可调节的过流消隐计时器，系统可在电
子保险丝不出现跳变的情况下支持负载电流的瞬态峰
值。
– 启动期间运行模式下的可调电流限制(ILIM
)
• 强大的短路保护
器件信息
封装(1)
– 针对输出短路事件进行快速跳变响应(< 200ns)
– 可调节(2 × IOCP) 和固定阈值
器件型号
封装尺寸（标称值）
TPS25985xRQP
QFN (26)
4.50 mm × 5.00 mm
– 不受电源线路瞬变影响- 无干扰性跳变
• 精确的模拟负载电流监控
(1) 如需了解所有可用封装，请参阅数据表末尾的可订购产品附
录。
– ±1.4% 精度
– 带宽大于500kHz
TPS25985x
IN
SUPPLY
LOAD
OUT
IREF
• 快速过压保护（16.6V 固定阈值）
• 可调节输出压摆率控制(dVdt)，用于提供浪涌电流
保护
VDD
TEMP
IMON
EN
EN/UVLO
MODE
SWEN
PG
PG
FLT
FLT
ITIMER GND
ILIM
DVDT
• 带有可调节欠压锁定(UVLO) 的高电平有效使能输
入
TPS25985x
IN
OUT
• 过热保护(OTP) 以确保实现FET SOA 保护
IREF
TEMP
IMON
VDD
IMON
– 确保FET SOA：12W√s
• 集成式FET 运行状况监测和报告
• 模拟芯片温度监测器输出(TEMP)
• 故障指示专用引脚(FLT)
EN/UVLO
PG
ITIMER
SWEN
FLT
MODE GND
ILIM
DVDT
TPS25985x
IN
OUT
IREF
TEMP
IMON
• 电源正常状态指示引脚(PG)
• 非限定通用快速比较器
VDD
TEMP
EN/UVLO
PG
ITIMER
SWEN
FLT
• 小尺寸：QFN 封装（4.5mm × 5mm，间距为
0.6mm）
MODE GND
ILIM
DVDT
– 电源引脚和GND 引脚之间的间隙为29mil
• 100% 无铅
简化版原理图
本文档旨在为方便起见，提供有关TI 产品中文版本的信息，以确认产品的概要。有关适用的官方英文版本的最新信息，请访问
www.ti.com，其内容始终优先。TI 不保证翻译的准确性和有效性。在实际设计之前，请务必参考最新版本的英文版本。
English Data Sheet: SLVSGG3
TPS25985
www.ti.com.cn
ZHCSOF5A –MAY 2022 –REVISED SEPTEMBER 2022
Table of Contents
9.1 Application Information............................................. 39
9.2 Typical Application: 12-V, 3.6-kW Power Path
Protection in Datacenter Servers................................ 43
9.3 Multiple eFuses, Parallel Connection with
1 特性................................................................................... 1
2 应用................................................................................... 1
3 说明................................................................................... 1
4 Revision History.............................................................. 2
5 说明（续）.........................................................................2
6 Pin Configuration and Functions...................................3
7 Specifications.................................................................. 5
7.1 Absolute Maximum Ratings........................................ 5
7.2 ESD Ratings............................................................... 5
7.3 Recommended Operating Conditions.........................5
7.4 Thermal Information....................................................6
7.5 Electrical Characteristics.............................................6
7.6 Logic Interface............................................................ 9
7.7 Timing Requirements..................................................9
7.8 Switching Characteristics..........................................10
7.9 Typical Characteristics.............................................. 11
8 Detailed Description......................................................17
8.1 Overview...................................................................17
8.2 Functional Block Diagram.........................................18
8.3 Feature Description...................................................19
8.4 Device Functional Modes..........................................38
9 Application and Implementation..................................39
PMBus® ......................................................................52
9.4 Digital Telemetry Using External Microcontroller...... 56
9.5 What to Do and What Not to Do............................... 57
10 Power Supply Recommendations..............................58
10.1 Transient Protection................................................58
10.2 Output Short-Circuit Measurements....................... 59
11 Layout...........................................................................60
11.1 Layout Guidelines................................................... 60
11.2 Layout Example...................................................... 61
12 Device and Documentation Support..........................62
12.1 Documentation Support.......................................... 62
12.2 接收文档更新通知................................................... 62
12.3 支持资源..................................................................62
12.4 Trademarks.............................................................62
12.5 Electrostatic Discharge Caution..............................62
12.6 术语表..................................................................... 62
13 Mechanical, Packaging, and Orderable
Information.................................................................... 62
4 Revision History
注：以前版本的页码可能与当前版本的页码不同
Changes from Revision * (May 2022) to Revision A (September 2022)
Page
• 将状态从“预告信息”更改为“量产数据”....................................................................................................... 1
5 说明（续）
可以并行连接多个TPS25985x 器件，以增加高功率系统的总电流容量。所有器件在启动和稳态期间均主动同步其
运行状态并共享电流，以避免某些器件上出现过载情况而导致并行链过早关闭或部分关闭。
集成的快速、准确检测模拟负载电流监测器有助于进行预测性维护，并且先进的动态平台电源管理技术（如Intel®
PSYS 和PROCHOT#）可更大限度地提高系统吞吐量和电源利用率。
此类器件的额定工作结温范围为–40°C 至+125°C。
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6 Pin Configuration and Functions
14
22
VIN
VIN
VIN
VIN
23
13
VOUT
VOUT
VOUT
VOUT
26
10
9
1
图6-1. TPS25985x RQP Package 26-pin QFN Top View
表6-1. Pin Functions
PIN
TYPE
DESCRIPTION
NAME
CMPOUT
NO.
1
O
I
General purpose comparator open-drain output
General purpose comparator negative input
General purpose comparator positive input
CMPM
CMPP
2
3
I
Start-up output slew rate control pin. Leave this pin open to allow fastest start-
up. Connect capacitor to ground to slow down the slew rate to manage inrush
current.
DVDT
TEMP
4
5
I/O
O
Die junction temperature monitor analog voltage output. Can be tied together
with TEMP outputs of multiple devices in a parallel configuration to indicate the
peak temperature of the chain.
A capacitor from this pin to GND sets the overcurrent blanking interval during
which the output current can temporarily exceed the overcurrent threshold (but
lower than fast-trip threshold) during steady-state operation before the device
overcurrent response takes action.
ITIMER
6
I/O
An external resistor from this pin to GND sets the overcurrent protection
threshold and fast-trip threshold during steady-state. This pin also acts as a fast
and accurate analog output load current monitor signal during steady-state. Do
not leave floating.
IMON
ILIM
7
8
O
O
An external resistor from this pin to GND sets the current limit threshold and
fast-trip threshold during start-up. This also sets the active current sharing
threshold during steady-state. Do not leave floating.
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表6-1. Pin Functions (continued)
PIN
TYPE
DESCRIPTION
NAME
NO.
Reference voltage for overcurrent, short-circuit protection and active current
sharing blocks. Can be generated using internal current source and resistor on
this pin, or can be driven from external voltage source. Do not leave floating.
IREF
OUT
9
I/O
Power output. Must be soldered to output power plane uniformly to ensure
proper heat dissipation and to maintain optimal current distribution through the
device.
10, 11, 12, 13
P
GND
DNC
DNC
14
15
16
G
X
X
Device ground reference pin. Connect to system ground.
Do not connect anything to this pin.
Do not connect anything to this pin.
MODE selection pin. Leave the pin floating for standalone and primary mode of
operation. Connect the pin to GND to configure device as a secondary device in
a parallel chain.
MODE
17
18
I
I
Active high enable input. Connect resistor divider from input supply to set the
EN/UVLO
undervoltage threshold. Do not leave floating.
PG
19
20
I/O
O
Open-drain active high Power Good indication
Open-drain active low fault indication
FLT
Open-drain signal to indicate and control power switch ON/OFF status. This pin
facilitates active synchronization between multiple devices in a parallel chain.
SWEN
VDD
IN
21
I/O
Controller power input pin. Can be used to power the internal control circuitry
with a filtered and stable supply which is not affected by system transients.
Connect this pin to VIN through a series resistor and add a decoupling capacitor
to GND.
22
P
Power input. Must be soldered to input power plane uniformly to ensure proper
heat dissipation and to maintain optimal current distribution through the device.
23, 24, 25, 26
P
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7 Specifications
7.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)(1)
Parameter
Pin
MIN
–0.3
–0.3
MAX
20
UNIT
V
VINMAX
Maximum Input Voltage Range
Maximum Supply Voltage Range
IN
VDDMAX
VDD
20
V
Min(20 V,
VIN + 0.3)
VOUTMAX
Maximum Output Voltage Range
OUT
–1
VIREFMAX
VDVDTMAX
VMODEMAX
VSWENMAX
ISWENMAX
VENMAX
Maximum IREF Pin Voltage Range
Maximum DVDT Pin Voltage Range
Maximum MODE Pin Voltage Range
Maximum SWEN Pin Voltage Range
Maximum SWEN Pin Sink Current
Maximum Enable Pin Voltage Range
Maximum FLT Pin Voltage Range
Maximum FLT Pin Sink Current
IREF
5.5
5.5
V
V
DVDT
MODE
SWEN
SWEN
EN/UVLO
FLT
Internally Limited
V
5.5
10
V
mA
V
20
VFLTBMAX
IFLTBMAX
VPGMAX
5.5
10
V
FLT
mA
V
Maximum PG Pin Voltage Range
Maximum PG Pin Sink Current
PG
5.5
10
IPGMAX
PG
mA
V
VCMPPMAX
VCMPMMAX
Maximum CMPP Pin Voltage Range
Maximum CMPM Pin Voltage Range
CMPP
CMPM
CMPOUT
CMPOUT
TEMP
ILIM
5.5
5.5
5.5
10
V
VCMPOUTMAX Maximum CMPOUT Pin Voltage Range
ICMPOUTMAX Maximum CMPOUT Pin Sink Current
V
mA
V
VTEMPMAX
VILIMMAX
VIMONMAX
Maximum TEMP Pin Voltage Range
Maximum ILIM pin voltage
5.5
Internally Limited
Internally Limited
Internally Limited
Internally Limited
Internally Limited
V
Maximum IMON pin voltage
IMON
ITIMER
IN to OUT
V
VITIMERMAX Maximum ITIMER pin voltage
V
IMAX
Maximum Continuous Switch Current
Junction temperature
A
TJMAX
TLEAD
TSTG
°C
°C
°C
Maximum Soldering Temperature
Storage temperature
300
150
–65
(1) Operation outside the Absolute Maximum Ratings may cause permanent device damage. Absolute Maximum Ratings do not imply
functional operation of the device at these or any other conditions beyond those listed under Recommended Operating Conditions. If
used outside the Recommended Operating Conditions but within the Absolute Maximum Ratings, the device may not be fully
functional, and this may affect device reliability, functionality, performance, and shorten the device lifetime.
7.2 ESD Ratings
VALUE
UNIT
Human body model (HBM), per ANSI/ESDA/
JEDEC JS-001(1)
±2000
V(ESD)
Electrostatic discharge
V
Charged device model (CDM), per ANSI/ESDA/
JEDEC JS-002(2)
±500
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
7.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
Parameter
Pin
MIN
MAX
UNIT
VIN
Input Voltage Range
IN
4.5
16
V
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over operating free-air temperature range (unless otherwise noted)
Parameter
Pin
MIN
MAX
UNIT
V
VDD
Supply Voltage Range
Output Voltage Range
VDD
OUT
4.5
16
VOUT
VIN
V
Min(VDD
1 V, VIN
+
+
VEN/UVLO Enable Pin Voltage Range
EN/UVLO
V
1 V)
VDVDT
VPG
DVDT Pin Cap Voltage Rating
PG Pin Pull-up Voltage Range
FLT Pin Pull-up Voltage Range
SWEN Pin Pull-up Voltage Range
ITIMER Pin Cap Voltage Rating
IREF Pin Voltage Range
DVDT
4
V
V
V
V
V
V
V
V
V
V
A
A
°C
PG
5
5
5
VFLTB
VSWEN
VITIMER
VIREF
VILIM
FLT
SWEN
ITIMER
IREF
2.5
4
0.3
1.2
0.4
1.2
1.5
5
ILIM Pin Voltage Range
ILIM
VIMON
VCMPx
IMON Pin Voltage Range
IMON
CMPP, CMPM Common Mode Voltage Range
CMPP, CMPM
CMPOUT
IN to OUT
IN to OUT
0.3
VCMPOUT CMPOUT Pin Pull-up Voltage Range
IMAX
60
RMS Switch Current, TJ ≤125℃
Peak Output Current, TJ ≤125℃
Junction temperature
IMAX, PLS
TJ
80
125
–40
7.4 Thermal Information
TPS25985X
RQP (QFN)
26 PINS
19.9
THERMAL METRIC(1) (2)
UNIT
RθJA(eff)
ΨJT
Junction-to-ambient thermal resistance (effective)
Junction-to-top characterization parameter
Junction-to-board characterization parameter
°C/W
°C/W
°C/W
0.2
4.2
ΨJB
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
(2) Based on simulations conducted with the device mounted on a custom 8-layer PCB (4s4p)
7.5 Electrical Characteristics
(Test conditions unless otherwise noted) –40°C ≤TJ ≤125°C, VIN = 12 V, VDD = 12 V, OUT = Open, VEN/UVLO = 2 V,
SWEN = 10 kΩ pull-up to 5 V, RILIM = 550 Ω, RIMON = 1100 Ω, VIREF = 1 V, DVDT = Open, ITIMER = Open, FLT = 10 kΩ
pull-up to 5 V, PG = 10 kΩ pull-up to 5 V, TEMP = Open, MODE = Open, CMPM = Open, CMPP = Open, CMPOUT = Open.
All voltages referenced to GND.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX UNIT
INPUT SUPPLY (VDD)
VDD
VDD input operating voltage range
VDD ON state quiescent current
VDD OFF state current
4.5
16
0.55
240
V
mA
µA
V
IQON(VDD)
IQOFF(VDD)
VUVP(R)
VUVP(F)
0.45
82
VVDD > VUVP(R), VEN ≥VUVLO(R)
VEN < VUVLO(F)
VDD undervoltage protection threshold VDD Rising
VDD undervoltage protection threshold VDD Falling
4.03
3.8
4.21
4.05
4.38
4.24
V
INPUT SUPPLY (IN)
VIN
VIN input operating voltage range
4.5
4
16
4.5
4.4
V
V
V
VUVPIN(R)
VUVPIN(F)
VIN undervoltage protection threshold
VIN undervoltage protection threshold
VIN Rising
VIN Falling
4.23
4.08
3.9
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7.5 Electrical Characteristics (continued)
(Test conditions unless otherwise noted) –40°C ≤TJ ≤125°C, VIN = 12 V, VDD = 12 V, OUT = Open, VEN/UVLO = 2 V,
SWEN = 10 kΩ pull-up to 5 V, RILIM = 550 Ω, RIMON = 1100 Ω, VIREF = 1 V, DVDT = Open, ITIMER = Open, FLT = 10 kΩ
pull-up to 5 V, PG = 10 kΩ pull-up to 5 V, TEMP = Open, MODE = Open, CMPM = Open, CMPP = Open, CMPOUT = Open.
All voltages referenced to GND.
PARAMETER
TEST CONDITIONS
MIN
TYP
2.83
2.9
MAX UNIT
IQON(IN)
IN ON state quiescent current
IN OFF state current
4.7
mA
µA
VEN ≥VUVLO(R)
IQOFF(IN)
VEN < VUVLO(F)
400
ENABLE / UNDERVOLTAGE LOCKOUT (EN/UVLO)
EN/UVLO pin voltage rising threshold for
turning on
VUVLO(R)
EN/UVLO Rising
1.12
1.02
1.2
1.28
1.18
V
V
EN/UVLO pin voltage falling threshold
for turning off and engaging output
EN/UVLO Falling, MODE = Open
1.09
discharge (primary device)
VUVLO(F)
EN/UVLO pin voltage threshold for
turning off and engaging QOD
(secondary device)
EN/UVLO Falling, MODE = GND
0.92
0.99
0.8
1.08
0.1
V
EN/UVLO pin voltage threshold for
entering full shutdown
VSD(F)
EN/UVLO Falling
0.5
V
IENLKG
OVERVOLTAGE PROTECTION (IN)
Input overvoltage protection threshold
EN/UVLO pin leakage current
VEN < Min(VIN + 1 V, VDD + 1 V)
µA
–0.1
VOVP(R)
VIN rising
VIN falling
15.7
15.4
16.6
17.9
17.8
V
V
(rising)
Input overvoltage protection threshold
(falling)
VOVP(F)
16.44
ON-RESISTANCE (IN - OUT)
0.582
24.98
0.737
1
IOUT = 8 A, TJ = 25℃
mΩ
mΩ
RON ON resistance
IOUT = 8 A, TJ = -40 to 125℃
OVERCURRENT PROTECTION REFERENCE (IREF)
IIREF IREF pin internal sourcing current
CURRENT LIMIT (ILIM)
GILIM(LIN) ILIM current monitor gain (ILIM:IOUT)
Ratio of start-up current limit threshold
24.3
25.7
µA
17.62
17
18.18
22
18.74
29
µA/A
%
CLREF(SAT)% (ILIM) to steady-state overcurrent
protection threshold reference (IREF)
VOUT > VFB, PG not asserted
28.4
26.5
39.51
34.66
52.8
45
A
A
RILIM = 138 Ω, VIREF = 1.2 V, VOUT > VFB
RILIM = 160 Ω, VIREF = 1..2 V, VOUT
VFB
>
Start-up current limit regulation
threshold
ILIM
8
5.7
1.5
13.65
9.73
1.99
18.2
13
A
A
V
RILIM = 400 Ω, VIREF = 1.2 V, VOUT > VFB
RILIM = 800 Ω, VIREF = 1.2 V, VOUT > VFB
VFB
Foldback voltage
2.5
OUTPUT CURRENT MONITOR AND OVERCURRENT PROTECTION (IMON)
GIMON
IMON current monitor gain (IMON:IOUT) Device in steady state (PG asserted)
17.808
58.04
48.3
18.19
60.11
50.1
18.57
61.96
51.7
µA/A
A
RIMON = 1100 Ω, VIREF = 1.2 V
A
RIMON = 1100 Ω, VIREF = 1V
RIMON = 1100 Ω, VIREF = 0.5 V
RIMON = 1100 Ω, VIREF = 0.24 V
Steady-state overcurrent protection
(Circuit-Breaker) threshold
IOCP
24.1
25.09
12.05
25.9
A
11.35
12.65
A
TRANSIENT OVERCURRENT BLANKING TIMER (ITIMER)
IITIMER
ITIMER pin internal discharge current
ITIMER pin internal pull-up resistance
1.29
10
2.07
2.98
19
µA
IOUT > IOCP, ITIMER ↓
RITIMER
13.87
kΩ
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7.5 Electrical Characteristics (continued)
(Test conditions unless otherwise noted) –40°C ≤TJ ≤125°C, VIN = 12 V, VDD = 12 V, OUT = Open, VEN/UVLO = 2 V,
SWEN = 10 kΩ pull-up to 5 V, RILIM = 550 Ω, RIMON = 1100 Ω, VIREF = 1 V, DVDT = Open, ITIMER = Open, FLT = 10 kΩ
pull-up to 5 V, PG = 10 kΩ pull-up to 5 V, TEMP = Open, MODE = Open, CMPM = Open, CMPP = Open, CMPOUT = Open.
All voltages referenced to GND.
PARAMETER
TEST CONDITIONS
MIN
TYP
3.65
2.16
1.50
MAX UNIT
VINT
ITIMER pin internal pull-up voltage
ITIMER comparator falling threshold
ITIMER discharge voltage threshold
IOUT < IOCP
3
4.1
V
V
V
VITIMERTHR
ΔVITIMER
IOUT > IOCP, ITIMER ↓
IOUT > IOCP, ITIMER ↓
1.24
1.76
SHORT-CIRCUIT PROTECTION
PG asserted High, Standalone/Primary
mode, MODE = Open
99
148
222
210
290
A
A
IFFT
Fixed fast-trip threshold in steady-state
PG asserted High, Secondary mode,
MODE = GND
130
Scalable fast-trip threshold (IMON) to
overcurrent protection threshold
reference (IREF) ratio during steady-
state
Standalone/Primary mode, MODE =
Open
186
210
200
225
214
240
%
%
SFTREF(LIN)%
Secondary mode, MODE = GND
Standalone/Primary mode, MODE =
Open
Scalable fast trip threshold to start-up
SFTREF(SAT)% current limit threshold ratio (ILIM)
(Inrush)
34
34
50
50
66
66
%
%
Secondary mode, MODE = GND
VILIM > CLREF(ACS)% × VIREF
Maximum RON during steady-state
RON(ACS)
0.778
1.31
mΩ
active current sharing
IMON:IOUT ratio during active current
PG asserted High, VILIM > CLREF(ACS)%
× VIREF
GIMON(ACS)
sharing
18.02
34.67
18.39
36.67
18.87
38.67
µA/A
%
Ratio of active current sharing trigger
CLREF(ACS)% threshold to steady state overcurrent
protection threshold
PG asserted High
INRUSH CURRENT PROTECTION (DVDT)
Primary/Standalone mode, MODE =
Open
IDVDT
DVDT pin charging current
1.4
2.03
2.9
µA
GDVDT
RDVDT
DVDT gain
18
20.5
529.6
0.749
22
670
V/V
Ω
dVdt pin to GND discharge resistance
RON when PG is asserted
350
RON(GHI)
1.31
mΩ
COMPARATOR INPUTS (CMPP, CMPM)
VCM(CMP) CMPx common mode voltage range
ICMPx CMPx pin leakage current
QUICK OUTPUT DISCHARGE (QOD)
Quick output discharge internal pull-
down current
TEMPERATURE SENSOR OUTPUT (TEMP)
0.3
1.5
0.1
0.3 V < VCMPx < 1.5 V
µA
–0.1
VSD(F) < VEN < VUVLO(F), –40 < TJ <
125℃
IQOD
11.6
20.65
26.5
mA
GTMP
TEMP sensor gain
2.58
672
75
2.65
678.5
93.4
2.72
685
170
14
mV/℃
mV
VTMP
TEMP pin output voltage
TEMP pin sourcing current
TEMP pin sinking current
TJ = 25℃
ITMPSRC
ITMPSNK
µA
8
10.1
µA
OVERTEMPERATURE PROTECTION (OTP)
TSD
Thermal shutdown threshold
Thermal shutdown hysteresis
TJ Rising
TJ Falling
150
°C
°C
TSDHYS
12.5
FET HEALTH MONITOR
VDSFLT
FET D-S fault threshold
SWEN = L
0.38
0.49
0.59
V
SINGLE POINT FAILURE (ILIM, IMON, IREF, ITIMER)
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7.5 Electrical Characteristics (continued)
(Test conditions unless otherwise noted) –40°C ≤TJ ≤125°C, VIN = 12 V, VDD = 12 V, OUT = Open, VEN/UVLO = 2 V,
SWEN = 10 kΩ pull-up to 5 V, RILIM = 550 Ω, RIMON = 1100 Ω, VIREF = 1 V, DVDT = Open, ITIMER = Open, FLT = 10 kΩ
pull-up to 5 V, PG = 10 kΩ pull-up to 5 V, TEMP = Open, MODE = Open, CMPM = Open, CMPP = Open, CMPOUT = Open.
All voltages referenced to GND.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX UNIT
Back-up overcurrent protection
threshold (steady -state)
IOC_BKP(LIN)
IOC_BKP(SAT)
70
94.2
140
160
A
A
Back-up overcurrent protection
threshold (start-up)
50
102.2
7.6 Logic Interface
over operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
SWEN
RSWEN
SWEN pin pull-down resistance
SWEN pin leakage current
SWEN de-asserted Low
SWEN asserted High
4.4
8.1
13
2
Ω
µA
V
ISWENLKG
–2
VIH_SWEN(min) SWEN input logic high
VIL_SWEN(max) SWEN input logic low
FAULT INDICATION (FLTB)
1.44
0.4
V
RFLTB
FLT pin pull-down resistance
FLT pin leakage current
FLT asserted Low
4.4
8.09
7.14
8.1
13
2
Ω
IFLTBLKG
FLT de-asserted High
µA
–2
POWER GOOD INDICATION (PG)
RPG
PG pin pull-down resistance
PG pin leakage current
PG de-asserted Low
PG asserted High
4.3
13
2
Ω
IPGKG
µA
–2
COMPARATOR OUTPUT (CMPOUT)
RCMPOUT CMPOUT pin pull-down resistance
ICMPOUT CMPOUT pin leakage current
CMPOUT de-asserted Low
CMPOUT asserted High
5
40
2
Ω
µA
–2
7.7 Timing Requirements
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX UNIT
tOVP
tINSDLY
tFFT
Overvoltage protection response time
Insertion delay
1.57
13.7
192
364
µs
ms
ns
VIN > VOVP(R) to SWEN↓
VDD > VUVP(R) to SWEN↑
Fixed Fast-Trip response time
Scalable Fast-Trip response time
IOUT > 1.5 × IFFT to IOUT
IOUT > 3 × IOCP to IOUT
↓
tSFT
ns
↓
VCMPP > 1.3 × VCMPM to CMPOUT
↑
tCMP
General purpose comparator response time
Overcurrent blanking interval
Auto-Retry Interval
366
ns
IOUT = 1.5 × IOCP, CITIMER = Open
0
ms
ms
tITIMER
IOUT = 1.5 × IOCP, CITIMER = 4.7 nF
3.79
Auto-retry variant, Primary mode
(MODE = Open)
tRST
107.5
ms
tEN(DG)
EN/UVLO de-glitch time
Start-up timeout interval
6
µs
tSU_TMR
215
ms
SWEN↑to FLT↓
VSD(F) < VEN/UVLO < VUVLO(F), VIN
12 V, COUT = 1 mF
=
tDischarge QOD discharge time (90% to 10% of VOUT
)
588
ms
tQOD
tPGA
QOD enable timer
PG assertion delay
VSD(F) < VEN/UVLO < VUVLO(F)
4.66
20
ms
us
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7.8 Switching Characteristics
The output rising slew rate is internally controlled and constant across the entire operating voltage range to ensure the turn
on timing is not affected by the load conditions. The rising slew rate can be adjusted by adding capacitance from the dVdt pin
to ground. As CdVdt is increased it will slow the rising slew rate (SR). See Slew Rate and Inrush Current Control (dVdt)
section for more details. The Turn-Off Delay and Fall Time, however, are dependent on the RC time constant of the load
capacitance (COUT) and Load Resistance (RL). The Switching Characteristics are only valid for the power-up
sequence where the supply is available in steady state condition and the load voltage is completely discharged before the
device is enabled. Typical values are taken at TJ = 25°C unless specifically noted otherwise. VIN = 12 V, ROUT = 500 Ω, COUT
= 1 mF
PARAMETER
CdVdt = 3.3 nF
CdVdt = 33 nF
UNITS
V/ms
ms
SRON
tD,ON
tR
Output rising slew rate
9.79
1.20
Turn on delay
Rise time
0.34
1.00
1.38
1081
1.54
8.13
ms
tON
Turn on time
Turn off delay
Fall time
10.35
1060
ms
tD,OFF
tF
µs
Depends on ROUT and COUT
µs
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7.9 Typical Characteristics
850
800
750
700
650
600
550
500
450
4.22
4.2
Rising
Falling
4.18
4.16
4.14
4.12
4.1
4.08
4.06
4.04
-40
-20
0
20
40
TA (C)
60
80
100 120 140
-40
-20
0
20
40
TA (C)
60
80
100 120 140
图7-2. VDD Undervoltage Thresholds Across Temperature
图7-1. ON Resistance Across Temperature
4.26
16.66
16.64
16.62
16.6
4.24
4.22
4.2
16.58
4.18
4.16
4.14
4.12
4.1
16.56
16.54
16.52
16.5
Rising
Falling
16.48
16.46
16.44
Rising
Falling
4.08
-40
-20
0
20
40
TA (C)
60
80
100 120 140
-40
-20
0
20
40
TA (C)
60
80
100 120 140
图7-4. Overvoltage Protection Threshold Across Temperature
图7-3. VIN Undervoltage Thresholds Across Temperature
1.22
0.91
0.9
1.2
0.89
0.88
0.87
1.18
1.16
0.86
0.85
0.84
0.83
0.82
0.81
0.8
Rising
Falling
Rising
Falling
1.14
1.12
1.1
1.08
-40
-20
0
20
40
60
80
100 120 140
-40
-20
0
20
40
60
80
100 120 140
TA (C)
TA (C)
图7-5. EN/UVLO Thresholds Across Temperature
图7-6. EN/UVLO Based Shutdown Falling Threshold Across
Temperature
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7.9 Typical Characteristics (continued)
18.3
18.25
18.2
25.3
25.25
25.2
TA (C)
-40
0
85
125
25.15
25.1
25.05
25
27
18.15
18.1
24.95
24.9
24.85
24.8
18.05
18
24.75
24.7
24.65
24.6
10
15
20
25
30
35
40
45
50
IOUT (A)
-40
-20
0
20
40
60
80
100 120 140
TA (C)
图7-8. IMON Gain Across Load and Temperature
图7-7. IREF Charging Current Across Temperature
1
4
3
TA (C)
-40
0
Max
Typ
Min
85
125
0.75
0.5
27
2
0.25
0
1
0
-0.25
-0.5
-0.75
-1
-1
-2
-3
-4
10
15
20
25
30
IOUT (A)
35
40
45
50
图7-9. IMON Gain Accuracy Across Load and Temperature
15
18
21
24
27
30
33
36
IOUT (A)
图7-10. IMON Gain Accuracy Across Process and Temperature
Corners
10
50
Max
Typ
Min
Max
Typ
Min
40
7.5
5
30
20
10
2.5
0
0
-10
-20
-30
-40
-50
-2.5
-5
-7.5
-10
10
15
20
25
30
IOCP (A)
35
40
45
50
10
15
20
25
30
35
40
45
ILIM (A)
图7-11. Steady-State Overcurrent Protection Threshold (Circuit-
图7-12. Start-up Overcurrent Protection Threshold (Current
Breaker) Accuracy
Limit) Accuracy
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7.9 Typical Characteristics (continued)
91.4
91.2
91
96
95.5
95
90.8
90.6
90.4
90.2
90
94.5
94
93.5
93
89.8
89.6
89.4
89.2
92.5
92
91.5
-40
-20
0
20
40
60
80
100 120 140
-40
-20
0
20
40
60
80
100 120 140
TA (C)
TA (C)
图7-13. Backup Overcurrent Protection Threshold (Start-up)
图7-14. Backup Overcurrent Protection Threshold (Steady-
Accuracy
State) Accuracy
3.76
3.74
3.72
3.7
2.079
2.076
2.073
2.07
2.067
2.064
2.061
2.058
2.055
2.052
3.68
3.66
3.64
3.62
3.6
3.58
-40
-20
0
20
40
60
80
100 120 140
-40
-20
0
20
40
60
80
100 120 140
TA (C)
TA (C)
图7-16. ITIMER Pin Discharge Current Across Temperature
图7-15. ITIMER Pin Internal Pullup Voltage Across Temperature
1.503
1.502
1.501
1.5
1.2
1.15
1.1
1.05
1
1.499
1.498
1.497
1.496
1.495
1.494
1.493
0.95
0.9
0.85
0.8
0.75
0.7
0.65
VIL
VIH
0.6
-40
-40
-20
0
20
40
TA (C)
60
80
100 120 140
-20
0
20
40
TA (C)
60
80
100 120 140
图7-17. ITIMER Pin Discharge Differential Voltage Threshold
图7-18. SWEN Pin Logic Thresholds Across Temperature
Across Temperature
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7.9 Typical Characteristics (continued)
2.06
2.055
2.05
20.58
20.56
20.54
20.52
20.5
2.045
2.04
2.035
2.03
2.025
2.02
2.015
2.01
20.48
20.46
2.005
2
1.995
-40
-20
0
20
40
60
80
100 120 140
-40
-20
0
20
40
60
80
100 120 140
TA (C)
TA (C)
图7-19. DVDT Charging Current Across Temperature
图7-20. DVDT Gain Across Temperature
110
105
100
95
23
22.5
22
TA (C)
70
55
21.5
21
90
20.5
20
85
80
19.5
19
75
18.5
18
70
65
40
42
44
46
48
50
IOUT (A)
52
54
56
58
60
17.5
-40
-20
0
20
40
60
80
100 120 140
TA (C)
图7-22. Junction Temperature vs Load Current (No Air-Flow)
图7-21. QOD Sink Current Across Temperature
80
75
70
65
60
55
50
45
40
35
Airflow (LFM)
No Airflow
100
200
400
EN held high, input supply ramped up and down
40
42
44
46
48
50
IOUT (A)
52
54
56
58
60
图7-24. Power Up and Down Sequencing Using Input Supply
图7-23. Junction Temperature vs Load Current (TA = 25°C, With
Air-Flow)
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7.9 Typical Characteristics (continued)
Input supply held steady, EN/UVLO pin toggled high and low
Input supply held steady, EN/UVLO pin held high, SWEN pin
toggled high and low
图7-25. Power Up and Down Sequencing Using EN/UVLO Pin
图7-26. Power Up and Down Sequencing Using SWEN Pin
COUT = 6.8 mF, CdVdt = 33 nF
COUT = 6.8 mF, ROUT = 1.2 Ω, CdVdt = 33 nF
图7-27. Inrush Current Control with Capacitive Load
图7-28. Inrush Current Control with Capacitive and Resistive
Load
IOCP = 50 A, tITIMER = 14 ms, IOUT pulsed above the IOCP
threshold for short duration without triggering circuit-breaker
response
Input supply ramped up above 16.6 V
图7-29. Input Overvoltage Protection Response
图7-30. Peak Current Support Using Transient Overcurrent
Blanking
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7.9 Typical Characteristics (continued)
IOCP = 50 A, tITIMER = 14 ms, IOUT stays above the IOCP
threshold persistently to trigger circuit-breaker response
IOCP = 50 A, Output hard-short to GND while in steady. IOUT
rises above 2 × IOCP triggers fast-trip response
图7-31. Overcurrent Protection Response (Circuit-Breaker)
图7-32. Short-Circuit Protection Response
Device turned on using SWEN with output hard-short to GND. Device limits the current with foldback.
图7-33. Power Up into Short-Circuit
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8 Detailed Description
8.1 Overview
The TPS25985x is an eFuse with integrated power switch that is used to manage load voltage and load current.
The device starts its operation by monitoring the VDD and IN bus. When VDD and VIN exceed the respective
Undervoltage Protection (UVP) thresholds, the device waits for the insertion delay timer duration to allow the
supply to stabilize before starting up. Next the device samples the EN/UVLO pin and SWEN pins. A high level on
both these pins enables the internal MOSFET to start conducting and allow current to flow from IN to OUT. When
either EN/UVLO or SWEN is held low, the internal MOSFET is turned off.
After a successful start-up sequence, the TPS25985x device now actively monitors its load current and input
voltage, and controls the internal FET to ensure that the programmed overcurrent threshold is not exceeded and
input overvoltage spikes are cut off. This action keeps the system safe from harmful levels of voltage and
current. At the same time, a user-adjustable overcurrent blanking timer allows the system to pass transient
peaks in the load current profile without tripping the eFuse. Similarly, voltage transients on the supply line are
intelligently masked to prevent nuisance trips. This feature ensures a robust protection solution against real
faults which is also immune to transients, thereby ensuring maximum system uptime.
The device has integrated high accuracy and high bandwidth analog load current monitor, which allows the
system to precisely monitor the load current in steady state as well as during transients. This feature facilitates
the implementation of advanced dynamic platform power management techniques such as Intel PSYS or
PROCHOT# to maximize system power usage and throughput without sacrificing safety and reliability.
For systems needing higher load current support, multiple TPS25985x eFuses can be connected in parallel. All
devices share current during start-up as well as steady-state to avoid over-stressing some of the devices more
than others which can result in premature or partial shutdown of the parallel chain. The devices synchronize their
operating states to ensure graceful startup, shutdown and response to faults. This makes the whole chain
function as a single very high current eFuse rather than a bunch of independent eFuses operating
asynchronously.
The device has integrated protection circuits to ensure device safety and reliability under recommended
operating conditions. The internal FET SOA is protected at all times using the thermal shutdown mechanism,
which turns off the FET whenever the junction temperature (TJ) becomes too high for the FET to operate safely.
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8.2 Functional Block Diagram
TSD
TPS25985
Temp Sense and
Overtemperature
protection
TEMP
OUT
5
23, 24,
IN
25, 26
10, 11,
12, 13
tQOD
UV
SD
FB
Back-up
OC
detector
TSD
VDD
22
LDO
VINT
CP
20.65 mA
OC_BKP
2.03 µA
MODE
18.18
µA/A
18.19
µA/A
SPFLT
Driver/Controller
SWEN_SNS
GHI
FFT
FB
4
×20
OV
DVDT
GHI
+
-
+
16.60 V9
16.44 V;
OC_IMON
-
OC_BKP
-
+
7
8
IMON
ILIM
VIN
Transient
Masking
UVP
14
18
GND
SFT
4.21 V9
4.05 V;
SFTREF
+
-
GHI MODE
OC_ILIM
+
-
EN/UVLO
VINT
UV
SD
1.20 V9
1.09 V;
-
+
25 µA
MODE
CLREF(SAT)
-
FB
GHI
MODE
REF
GEN
9
IREF
+
0.5 V;
19
21
20
PG
SWEN
FLT
SWEN_SNS
3.65V
UV
OV
EXTFLT
+
-
2.16V
SWEN_INT
13.87 kΩ
CB
6
ITIMER
OC_IMON
MODE
OV
UV
TSD
CB
2.07 µA
VDS_OK
SFT
FFT
SPFLT
EXTFLT
Q
S
FLT
MODE
VDS_OK
RETRY
TIMER#
1
CMPOUT
DNC
DNC
15
16
+
-
/Q
R
VINT
SWEN_SNS
SD
10 µs
17
MODE
3
2
CMPP CMPM
# Only for TPS259851 (auto-retry variant)
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8.3 Feature Description
The TPS25985x eFuse is a compact, feature rich power management device that provides detection, protection
and indication in the event of system faults.
8.3.1 Undervoltage Protection
The TPS25985x implements undervoltage lockout on VDD and VIN in case the applied voltage becomes too low
for the system or device to properly operate. The undervoltage lockout has a default internal threshold of VUVP
on VDD and VUVPIN on VIN. Alternatively, the UVLO comparator on the EN/UVLO pin allows the undervoltage
protection threshold to be externally adjusted to a user defined value. 图 8-1 and 方程式 1 show how a resistor
divider can be used to set the UVLO set point for a given voltage supply.
Power
Supply
IN
R1
EN/UVLO
R2
GND
图8-1. Adjustable Undervoltage Protection
R
+ R
2
1
V
= V
(1)
IN UV
UVLO R
R
2
The EN/UVLO pin implements a bi-level threshold.
1. VEN > VUVLO(R): Device is fully ON.
2. VSD(F) < VEN < VUVLO(F): The FET along with most of the controller circuitry is turned OFF, except for some
critical bias and digital circuitry. Holding the EN/UVLO pin in this state for > tQOD activates the Output
Discharge function.
3. VEN < VSD(F): All active circuitry inside the part is turned OFF and it retains no digital state memory. It also
resets any latched faults. In this condition, the device quiescent current consumption is minimal.
8.3.2 Insertion Delay
The TPS25985x implements insertion delay at start-up to ensure the supply has stabilized before the device tries
to turn on the power to the load. The device initially waits for the VDD supply to rise above the UVP threshold
and all the internal bias voltages to settle. After that, the device remains off for an additional delay of tINSDLY
irrespective of the EN/UVLO pin condition. This action helps to prevent any unexpected behavior in the system if
the device tries to turn on before the card has made firm contact with the backplane or if there is any supply
ringing or noise during start-up.
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Input supply stepped up from 0 V to 12 V. Device waits for tINSDLY for input supply to stabilize before it turns on the output.
图8-2. Insertion Delay
8.3.3 Overvoltage Protection
The TPS25985x implements overvoltage lockout to protect the load from input overvoltage conditions. The OVP
comparator on the IN pin uses a fixed internal overvoltage protection threshold. If the input voltage on IN
exceeds the OVP rising threshold (VOVP(R)), the power FET is turned OFF within tOVP. After the voltage on IN
falls below the OVP falling threshold (VOVP(F)), the FET is turned ON in a dVdt controlled manner.
Input Overvoltage Event
Input Overvoltage Removed
VOVP(R)
VOVP(F)
IN
0
tOVP
VIN
OUT
dVdt limited Start-up
0
VL
0
SWEN
VL
0
PG
VL
0
FLT
Time
图8-3. Input Overvoltage Protection Response
8.3.4 Inrush Current, Overcurrent, and Short-Circuit Protection
TPS25985x incorporates four levels of protection against overcurrent:
1. Adjustable slew rate (dVdt) for inrush current control
2. Active current limit with an adjustable threshold (ILIM) for overcurrent protection during start-up
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3. Circuit-breaker with an adjustable threshold (IOCP) and blanking timer (tITIMER) for overcurrent protection
during steady-state
4. Fast-trip response to severe overcurrent faults with an adjustable threshold (ISFT = 2 × IOCP) to quickly
protect against severe short-circuits under all conditions, as well as a fixed threshold (IFFT) during steady
state
8.3.4.1 Slew rate (dVdt) and Inrush Current Control
During hot plug events or while trying to charge a large output capacitance, there can be a large inrush current.
If the inrush current is not managed properly, the inrush current can damage the input connectors and cause the
system power supply to droop. This action can lead to unexpected restarts elsewhere in the system. The inrush
current during turn-on is directly proportional to the load capacitance and rising slew rate. 方程式 2 can be used
to find the slew rate (SR) required to limit the inrush current (IINRUSH) for a given load capacitance (CLOAD):
I
A
INRUSH
SR V/ms =
(2)
C
mF
LOAD
A capacitor can be added to the DVDT pin to control the rising slew rate and lower the inrush current during turn-
on. The required CdVdt capacitance to produce a given slew rate can be calculated using 方程式3.
42000
SR V/ms
C
pF =
(3)
DVDT
The fastest output slew rate is achieved by leaving the dVdt pin open.
备注
1. High input slew rates in combination with high input power path inductance can result in
oscillations during start-up. This can be mitigated using one or more of the following steps:
a. Reduce the input inductance.
b. Increase the capacitance on VIN pin.
c. Increase the dVdt pin capacitance to reduce the slew rate or increase the start-up time. TI
recommends using a minimum start-up time of 5 ms.
8.3.4.1.1 Start-Up Time Out
If the start-up is not completed, that is, the FET is not fully turned on within a certain timeout interval (tSU_TMR
)
after SWEN is asserted, the device registers it as a fault. FLT is asserted low and the device goes into latch-off
or auto-retry mode depending on the device configuration.
8.3.4.2 Steady-State Overcurrent Protection (Circuit-Breaker)
The TPS25985x responds to output overcurrent conditions during steady-state by performing a circuit-breaker
action after a user-adjustable transient fault blanking interval. This action allows the device to support a higher
peak current for a short user-defined interval but also ensures robust protection in case of persistent output
faults.
The device constantly senses the output load current and provides an analog current output (IIMON) on the IMON
pin which is proportional to the load current, which in turn produces a proportional voltage (VIMON) across the
IMON pin resistor (RIMON) as per 方程式4.
V
= I
× G
× R
IMON
(4)
IMON
OUT
IMON
Where GIMON is the current monitor gain (IIMON : IOUT
)
The overcurrent condition is detected by comparing this voltage against the voltage on the IREF pin as a
reference. The reference voltage (VIREF) can be controlled in two ways, which sets the overcurrent protection
threshold (IOCP) accordingly.
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• In the standalone or primary mode of operation, the internal current source interacts with the external IREF
pin resistor (RIREF) to generate the reference voltage. It is also possible to drive the IREF pin from an external
low impedance reference voltage source as shown in 方程式5.
V
= I
× R
IREF
(5)
IREF
IREF
• In a primary and secondary parallel configuration, the primary eFuse or controller drives the voltage on the
IREF pin to provide an external reference (VIREF) for all the secondary devices in the chain.
The overcurrent protection threshold during steady-state (IOCP) can be calculated using 方程式6.
V
IREF
I
=
(6)
OCP
G
× R
IMON
IMON
备注
Maintain VIREF within the recommended voltage range to ensure proper operation of the overcurrent
detection circuit.
TI recommends to add a 150-pF capacitor from IREF pin to GND for improved noise immunity.
After an overcurrent condition is detected, that is the load current exceeds the programmed current limit
threshold (IOCP), but stays lower than the short-circuit threshold (2 × IOCP), the device starts discharging the
ITIMER pin capacitor using an internal 2.07-μA pulldown current. If the load current drops below the current
limit threshold before the ITIMER capacitor discharges by ΔVITIMER, the ITIMER is reset by pulling it up to VINT
internally and the circuit-breaker action is not engaged. This action allows short overload transient pulses to pass
through the device without tripping the circuit. If the overcurrent condition persists, the ITIMER capacitor
continues to discharge and after it falls by ΔVITIMER, the circuit-breaker action turns off the FET immediately. At
the same time, the ITIMER cap is charged up to VINT again so that it is at its default state before the next
overcurrent event. This action ensures the full blanking timer interval is provided for every overcurrent event. 方
程式7 can be used to calculate the RIMON value for the desired overcurrent threshold.
V
IREF
× I
R
=
(7)
IMON
G
IMON
OCP
The duration for which transients are allowed can be adjusted using an appropriate capacitor value from ITIMER
pin to ground. The transient overcurrent blanking interval can be calculated using 方程式8.
C
nF × ∆ V V
ITIMER
ITIMER
t
ms =
(8)
ITIMER
I
μA
ITIMER
备注
1. Leave the ITIMER pin open to allow the part to break the circuit with the minimum possible delay.
However, this makes the circuit-breaker response extremely sensitive to noise and can cause
false tripping during load transients.
2. Shorting the ITIMER pin to ground results in minimum overcurrent response delay (similar to
ITIMER pin open condition), but increases the quiescent current –not a recommended mode of
operation.
3. Increasing the ITIMER cap value extends the overcurrent blanking interval. However, it also
extends the time needed for the ITIMER cap to recharge up to VINT before the next overcurrent
event. If the next overcurrent event occurs before the ITIMER cap is recharged fully, it takes less
time to discharge to the VITIMER threshold, thereby it provides a shorter blanking interval than
intended.
图 8-4 illustrates the overcurrent response for TPS25985x eFuse. After the part shuts down due to a circuit-
breaker fault, it either stays latched off (TPS259850 variant) or restarts automatically after a fixed delay
(TPS259851 variant).
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Load Transient
Persistent Output Overload
ITIMER expired
2 × IOCP
Circuit-Breaker
operation
IOUT
IOCP
0
IMON
VIREF
0
tITIMER
VINT
∆VITIMER
ITIMER
0
VIN
OUT
0
VL
FLT
0
VL
PG
0
VL
SWEN
0
TSD
TSDHYS
TJ
TJ
Time
图8-4. Steady-State Overcurrent (Circuit-Breaker) Response
8.3.4.3 Active Current Limiting During Start-Up
The TPS25985x responds to output overcurrent conditions during start-up by actively limiting the current. The
device constantly senses the current flowing through each one (IDEVICE) and provides an analog current output
(IILIM) on the ILIM pin, which in turn produces a proportional voltage (VILIM) across the ILIM pin resistor (RILIM) as
per 方程式9.
V
= I
× G
× R
ILIM
(9)
ILIM
DEVICE
ILIM
Where GILIM is the current monitor gain (IILIM : IDEVICE
)
The overcurrent condition is detected by comparing this voltage against a threshold which is a scaled voltage
(CLREFSAT) derived from the reference voltage (VIREF) on the IREF pin as presented in 方程式10.
0.7 × V
IREF
CLREF
=
(10)
SAT
3
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The reference voltage (VIREF) can be controlled in two ways, which sets the start-up current limit threshold (ILIM
accordingly.
)
1. In the standalone mode of operation, the internal current source interacts with the external IREF pin resistor
(RIREF) to generate the reference voltage as shown in 方程式11.
V
= I
× R
IREF
(11)
IREF
IREF
2. In a primary and secondary configuration, the primary eFuse or controller drives the voltage on the IREF pin
to provide an external reference (VIREF).
The active current limit (ILIM) threshold during start-up can be calculated using 方程式12.
CLREF
SAT
I
=
(12)
ILIM
G
× R
ILIM
ILIM
When the load current during start-up exceeds ILIM, the device tries to regulate and hold the load current at ILIM
.
During current regulation, the output voltage drops, resulting in increased device power dissipation across the
FET. If the device internal temperature (TJ) exceeds the thermal shutdown threshold (TSD), the FET is turned
off. After the part shuts down due to a TSD fault, it either stays latched off (TPS259850 variants) or restarts
automatically after a fixed delay (TPS259851 variants). See Overtemperature protection section for more details
on device response to overtemperature.
备注
The active current limit block employs a foldback mechanism during start-up based on the output
voltage (VOUT). When VOUT is below the foldback threshold (VFB), the current limit threshold is further
lowered.
8.3.4.4 Short-Circuit Protection
During an output short-circuit event, the current through the device increases very rapidly. When an output short-
circuit is detected, the internal fast-trip comparator triggers a fast protection sequence to prevent the current from
building up further and causing any damage or excessive input supply droop. The fast-trip comparator employs a
scalable threshold (ISFT) which is equal to 2 × IOCP (primary device) or 2.25 × IOCP (secondary device) during
steady-state and 1.5 × ILIM during inrush. This action enables the user to adjust the fast-trip threshold as per
system rating, rather than using a high fixed threshold which can not be suitable for all systems. After the current
exceeds the fast-trip threshold, the TPS25985x turns off the FET within tSFT. The device also employs a higher
fixed fast-trip threshold (IFFT) to provide fast protection against hard short-circuits during steady-state (FET in
linear region). After the current exceeds IFFT, the FET is turned off completely within tFFT. 图 8-5 illustrates the
short-circuit response for TPS25985x eFuse.
In some of the systems, for example blade servers and telecom equipment which house multiple hot-pluggable
blades or line cards connected to a common supply backplane, there can be transients on the supply due to
switching of large currents through the inductive backplane. This can result in current spikes on adjacent cards
which can potentially be large enough to trigger the fast-trip comparator of the eFuse. The TPS25985x uses a
proprietary algorithm to avoid nuisance tripping in such cases thereby facilitating uninterrupted system operation.
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Retry Timer Elapsed (1)
Or
Power/Enable Cycled
Transient Severe Overcurrent
Retry Timer Elapsed (1)
Or
Persistent Severe Overcurrent Fault
Retry Timer Elapsed (1)
Or
Power/Enable Cycled
Power/Enable Cycled
Thermal Shutdown
VIN
Fault Removed
IN
0
tSC
tSC
IFT
2 × IOCP
IOUT
IOCP
ILIM
0
2 × VIREF
IMON
VIREF
0
0.5 × VIREF
ILIM
0.23 × VIREF
0
Current limited
Start-up
VIN
OUT
dVdt limited
Start-up
dVdt limited
Start-up
0
tPGD
VL
PG
0
VL
FLT
0
VL
SWEN
0
TSD
TSDHYS
TJ
Time
(1) Applicable only to TPS259851 variants
图8-5. Short-Circuit Response
8.3.5 Analog Load Current Monitor (IMON)
The TPS25985x allows the system to monitor the output load current accurately by providing an analog current
on the IMON pin which is proportional to the current through the FET. The benefit of having a current output is
that the signal can be routed across a board without adding significant errors due to voltage drop or noise
coupling from adjacent traces. The current output also allows the IMON pins of multiple TPS25985x devices to
be tied together to get the total current in a parallel configuration. The IMON signal can be converted to a voltage
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by dropping it across a resistor at the point of monitoring. The user can sense the voltage (VIMON) across the
RIMON to get a measure of the output load current using 方程式13.
V
IMON
I
=
(13)
OUT
G
× R
IMON
IMON
The TPS25985x IMON circuit is designed to provide high bandwidth and high accuracy across load and
temperature conditions, irrespective of board layout and other system operating conditions. This design allows
the IMON signal to be used for advanced dynamic platform power management techniques such as Intel PSYS
or PROCHOT# to maximize system power usage and platform throughput without sacrificing safety or reliability.
图8-6. Analog Load Current Monitor Response
备注
1. The IMON pin provides load current monitoring information only during steady-state. During
inrush, the IMON pin reports zero load current.
2. The ILIM pin reports the individual device load current at all times and can also be used as an
analog load current monitor for each individual device.
3. Care must be taken to minimize parasitic capacitance on the IMON and ILIM pins to avoid any
impact on the overcurrent and short-circuit protection timing.
8.3.6 Mode Selection (MODE)
This pin can be used to configure the TPS25985x as a primary device in a chain along with other TPS25985x
eFuses, designated as secondary devices. This feature allows some of the TPS25985x pin functions to be
changed to aid the primary + secondary parallel connection.
This pin is sampled at power up. Leaving the pin open configures it as a primary or standalone device.
Connecting this pin to GND configures it as a secondary device.
The following functions are disabled in secondary mode and the device relies on the primary device to provide
this functionality:
1. IREF internal current source
2. DVDT internal current source
3. Overcurrent detection in steady-state for circuit-breaker response
4. PG de-assertion (pulldown) after reaching steady-state
5. Latch-off after fault
In secondary mode, the following functions are still active:
1. Overtemperature protection
2. Start-up current limit based on ILIM
3. Active current sharing during inrush as well as steady-state
4. Analog current monitor (IMON) in steady state
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5. Steady-state overcurrent detection based on IMON. This is indicated by pulling ITIMER pin low internally, but
does not trigger circuit-breaker action on ITIMER expiry. Rather, it relies on the primary device to start its
own ITIMER and then trigger the circuit-breaker action for the whole chain by pulling SWEN low after the
ITIMER expiry. However, the secondary devices use an internal overcurrent timer as a backup in case the
primary device fails to initiate circuit-breaker action for an extended period of time. Refer to Single Point
Failure Mitigation section for details.
6. Each device still has individual scalable and fixed fast-trip thresholds to protect itself. The individual short-
circuit protection threshold is set to maximum, that is 2.25 × IOCP (steady-state) or 2 × ILIM (start-up) in
secondary mode so that the primary device can lower it further for the whole system.
7. Individual OVP is set to maximum in secondary device so that the primary can lower it further for the whole
system.
8. FLT assertion based on individual device fault detection (except circuit-breaker).
9. PG de-assertion control during inrush and assertion control after device reaches steady state. However, after
that in steady state, the secondary device no longer controls the de-assertion of the PG in case of faults.
10. SWEN assertion or de-assertion based on internal events as well as FET ON and OFF control based on
SWEN pin status.
In secondary mode, the device behavior during short-circuit and fast-trip is also altered. More details are
available in the Short-Circuit Protection section.
8.3.7 Parallel Device Synchronization (SWEN)
The SWEN pin is a signal which is driven high when the FET must be turned ON. When the SWEN pin is driven
low (internally or externally), it signals the driver circuit to turn OFF the FET. This pin serves both as a control
and handshake signal and allows multiple devices in a parallel configuration to synchronize their FET ON and
OFF transitions.
表8-1. SWEN Summary
Device State
FET Driver Status
SWEN
Steady-state
Inrush
ON
ON
H
H
L
L
L
L
L
L
L
H
L
Overtemperature shutdown
Auto-retry timer running
Undervoltage (EN/UVLO)
Undervoltage (VDD UVP)
Undervoltage (VIN UVP)
Insertion delay
OFF
OFF
OFF
OFF
OFF
OFF
OFF
ON
Overvoltage lockout (VIN OVP)
Transient overcurrent
Circuit-breaker (persistent overcurrent
followed by ITIMER expiry)
OFF
Fast-trip
OFF
OFF
L
L
Fault response mono-shot running (MODE =
GND)
Fault response mono-shot expired (MODE =
GND)
ON
H
ILM pin open (start-up)
OFF
OFF
OFF
OFF
L
L
L
L
ILM pin short (start-up)
ILM pin open (steady-state)
ILM pin short (steady-state)
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表8-1. SWEN Summary (continued)
Device State
FET Driver Status
SWEN
FET health fault
OFF
L
The SWEN is an open-drain pin and must be pulled up to an external supply.
备注
1. The SWEN pullup supply must be powered up before the eFuse can be turned on. TI
recommends to use a system standby rail which is derived from the input of the eFuse.
2. In some cases, it can be possible to use the ITIMER pin as a pullup rail for SWEN pin. Usse a
weak pullup to ensure that the loading on the ITIMER is not high enough to affect the ITIMER
charging and discharging time.
In a primary + secondary parallel configuration, the SWEN pin is used by the primary device to control the on
and off transitions of the secondary devices. At the same time, it allows the secondary devices to communicate
any faults or other condition which can prevent it from turning on to the primary device. Refer to Fault Response
and Indication (FLT) for more details.
To maintain state machine synchronization, the devices rely on SWEN level transitions as well as timing for
handshakes. This ensures all the devices turn ON and OFF synchronously and in the same manner (for
example, DVDT controlled or current limited start-up). There are also fail-safe mechanisms in the SWEN control
and handshake logic to ensure the entire chain is turned off safely even if the primary device is unable to take
control in case of a fault.
备注
TI recommends to keep the parasitic loading on the SWEN pin to a minimum to avoid synchronization
timing issues.
8.3.8 Stacking Multiple eFuses for Unlimited Scalability
For systems needing higher current than supported by a single TPS25985x, multiple TPS25985x devices can be
connected in parallel to deliver the total system current. Conventional eFuses can not share current equally
between themselves during steady-state due to mismatches in their path resistances (which includes the
individual device RDSON variation from part to part, as well as the parasitic PCB trace resistance). This fact can
lead to multiple problems in the system:
1. Some devices always carry higher current as compared to other devices, which can result in accelerated
failures in those devices and an overall reduction in system operational lifetime.
2. As a result, thermal hotspots form on the board, devices, traces, and vias carrying higher current, leading to
reliability concerns for the PCB. In addition, this problem makes thermal modeling and board thermal
management more challenging for designers.
3. The devices carrying higher current can hit their individual circuit-breaker threshold prematurely even while
the total system load current is lower than the overall circuit-breaker threshold. This action can lead to false
tripping of the eFuse during normal operation. This has the effect of lowering the current-carrying capability
of the parallel chain. In other words, the current rating of the parallel eFuse chain must be de-rated as
compared to the sum of the current ratings of the individual eFuses. This de-rating factor is a function of the
path resistance mismatch, the number of devices in parallel, and the individual eFuse circuit-breaker
accuracy.
The need for de-rating has an adverse impact on the system design. The designer is forced to make one of
these trade-offs:
1. Limit the operating load current of the system to below the derated current threshold of the eFuse chain.
Essentially, it means lower platform capabilities than are supported by the power supply (PSU).
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2. Increase the overall circuit-breaker threshold to allow the desired system load current to pass through
without tripping. As a consequence, the power supply (PSU) must be oversized to deliver higher currents
during faults to account for the de-grading of the overall circuit-breaker accuracy.
In either case, the system suffers from poor power supply utilization, which can mean sub-optimal system
throughput or increased installation and operating costs, or both.
The TPS25985x uses a proprietary technique to address these problems and provide unlimited scalability of the
solution by paralleling as many eFuses as needed. This is incorporated without unequal current sharing or any
degradation in accuracy.
For this scheme to work correctly, the devices must be connected in the following manner:
• The SWEN pins of all the devices are connected together.
• The IMON pins of all the devices must be connected together. The RIMON resistor value on the combined
IMON pin can be calculated using 方程式14.
V
IREF
R
=
(14)
IMON
G
× I
IMON
OCP TOTAL
• The RILIM for each individual eFuse must be selected based on 方程式15.
1.1 × N × R
IMON
R
=
(15)
ILIM
3
Where N = number of devices in parallel chain. 图8-7 illustrates the response of the active current sharing
block in TPS25985 eFuse during steady-state.
Intentional skew is introduced between the power path resistances for six devices and the load current is ramped up slowly. Equal
current distribution is seen between all devices after the current through each device exceeds the active current sharing threshold.
图8-7. Active Current Sharing During Steady-State with Six TPS25985x eFuses in Parallel
备注
The active current sharing scheme is engaged when the current through any eFuse while in steady-
state exceeds the individual current sharing threshold set by the RILIM based on 方程式16.
1.1 × V
IREF
R
=
(16)
ILIM
3 × G
ILIM
× I
LIM ACS
The active current sharing scheme is disengaged when the total system current exceeds the system
overcurrent (circuit-breaker) threshold (IOCP(TOTAL)).
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8.3.8.1 Current Balancing During Start-Up
The TPS25985x implements a proprietary current balancing mechanism during start-up, which allows multiple
TPS25985x devices connected in parallel to share the inrush current and distribute the thermal stress across all
the devices. This feature helps to complete a successful start-up with all the devices and avoid a scenario where
some of the eFuses hit thermal shutdown prematurely. This in effect increases the inrush current capability of the
parallel chain. The improved inrush performance makes it possible to support very large load capacitors on high
current platforms without compromising the inrush time or system reliability.
8.3.9 Analog Junction Temperature Monitor (TEMP)
The device allows the system to monitor the junction temperature (TJ) accurately by providing an analog voltage
on the TEMP pin which is proportional to the temperature of the die. This voltage can be connected to the ADC
input of a host controller or eFuse with digital telemetry. In a multi-device parallel configuration, the TEMP
outputs of all devices can be tied together. In this configuration, the TEMP signal reports the temperature of the
hottest device in the chain.
备注
1. The TEMP pin voltage is used only for external monitoring and does not interfere with the
overtemperature protection scheme of each individual device which is based purely on the internal
temperature monitor.
2. TI recommends to add a capacitance of 22 pF on the TEMP pin to filter out glitches during system
transients.
3. The current source on the TEMP pin of TPS25985x is internally clamped to a safe value to protect
against overload, short circuit on this pin. This can lead to incorrect temperature reporting on the
TEMP when the number of devices connected in parallel is higher than 6. This limitation can be
overcome by connecting an external pull-resistance on the TEMP pin.
8.3.10 Overtemperature Protection
The TPS25985x employs an internal thermal shutdown mechanism to protect itself when the internal FET
becomes too hot to operate safely. When the TPS259850 detects thermal overload, it shuts down and remains
latched-off until the device is power cycled or re-enabled. When the TPS259851 detects thermal overload, it
remains off until it has cooled down sufficiently. Thereafter, the device remains off for an additional delay of tRST
after which it automatically retries to turn on if it is still enabled.
表8-2. Overtemperature Protection Summary
Device
Enter TSD
Exit TSD
TJ < TSD –TSDHYS
TPS259850 (Latch-Off)
TJ ≥TSD
TJ ≥TSD
VDD cycled to 0 V and then above VUVP(R) or
EN/UVLO toggled below VSD(F)
TJ < TSD –TSDHYS
tRST timer expired or VDD cycled to 0 V and
then above VUVP(R) or EN/UVLO toggled
below VSD(F)
TPS259851 (Auto-Retry)
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8.3.11 Fault Response and Indication (FLT)
表8-3 summarizes the device response to various fault conditions.
表8-3. Fault Summary
Event or Condition
Device Response
Fault Latched Internally
FLT Pin Status
Delay
Steady-state
None
N/A
N/A
Y
H
H
L
Inrush
None
Overtemperature
Shutdown
Undervoltage (EN/UVLO) Shutdown
Undervoltage (VDD UVP) Shutdown
N
H
H
H
H
H
N
Undervoltage (VIN UVP)
Overvoltage (VIN OVP)
Transient overcurrent
Shutdown
Shutdown
None
N
N
N
Persistent overcurrent
(steady-state)
Circuit-Breaker
Current Limit
Fast-trip
Y
N
Y
L
L
L
tITIMER
Persistent overcurrent
(start-up)
Short-circuit (primary
mode)
tFT
Short-circuit (secondary
mode)
Fast-trip followed by
current limited Start-up
N
Y
H
L
ILIM pin open (start-up)
Shutdown
Shutdown (if IOUT
IOC_BKP
>
ILIM pin short (start-up)
)
Y
N
N
Y
Y
Y
Y
L
H
H
L
ILIM pin open (steady-
state)
Active current sharing loop
always active
ILIM pin short (steady-
state)
Active current sharing loop
disabled
IMON pin open (steady-
state)
Shutdown
IMON pin short (steady-
state)
Shutdown (If IOUT
IOC_BKP
>
>
>
)
L
45 μs
Shutdown (If IOUT
IOC_BKP
IREF pin open (start-up)
)
L
IREF pin open (steady-
state)
Shutdown (if IOUT
IOC_BKP
)
L
tITIMER
IREF pin short (steady-
state)
Shutdown
Shutdown
Y
Y
L
L
IREF pin short (start-up)
ITIMER pin forced to high Shutdown (if IOUT > IOCP or
voltage
IOUT > IOC_BKP
)
Y
Y
Y
Y
L
L
L
L
tSPFAIL_TMR
tSU_TMR
Start-up timeout
FET health fault (G-S)
FET health fault (G-D)
Shutdown
Shutdown
10 μs
Shutdown
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表8-3. Fault Summary (continued)
Event or Condition
Device Response
Fault Latched Internally
FLT Pin Status
Delay
FET health fault (D-S)
Shutdown
N
L
tSU_TMR
External fault (SWEN
pulled low externally while
device is not in UV or OV) Shutdown
Y
L
FLT is an open-drain pin and must be pulled up to an external supply.
The device response after a fault varies based on the mode of operation:
1. During standalone or primary mode of operation (MODE = OPEN), the device latches a fault and follows the
auto-retry or latch-off response as per the device selection. When the device turns on again, it follows the
usual DVDT limited start-up sequence.
2. During the secondary mode of operation (MODE = GND), if the device detects any fault, it pulls the SWEN
pin low momentarily to signal the event to the primary device and thereafter relies on the primary to take
control of the fault response. However, if the primary device fails to register the fault, there i a failsafe
mechanism in the secondary device to turn off the entire chain and enter a latch-off condition. Thereafter, the
device can be turned on again only by power cycling VDD below VUVP(F) or by cycling EN/UVLO pin below
VSD(F)
.
For faults that are latched internally, power cycling the part or pulling the EN/UVLO pin voltage below VSD(F)
clears the fault and the pin is de-asserted. This action also clears the tRST timer (auto-retry variants only). Pulling
the EN/UVLO just below the UVLO threshold has no impact on the device in this condition. This is true for both
latch-off and auto-retry variants.
8.3.12 Power Good Indication (PG)
Power Good indication is an active high output which is asserted high to indicate when the device is in steady-
state and capable of delivering maximum power.
表8-4. PG Indication Summary
Event or Condition
Undervoltage ( VEN < VUVLO
VIN < VUVP
FET Status
PG Pin Status
PG Delay
)
OFF
OFF
OFF
OFF
ON
L
L
L
L
H
L
H
tPGD
VDD < VUVP
Overvoltage (VIN > VOVP
Steady-state
)
tPGD
tPGA
tPGA
N/A
Inrush
ON
Transient overcurrent
ON
Circuit-breaker (persistent
L (MODE = H)
H (MODE = L)
tPGD
N/A
overcurrent followed by ITIMER
expiry)
OFF
L (MODE = H)
H (MODE = L)
tPGD
N/A
Fast-trip
OFF
L (MODE = H)
H (MODE = L)
tITIMER + tPGD
N/A
ILM pin open
ILM pin short
Overtemperature
OFF
L (MODE = H)
H(MODE = L)
tPGD
N/A
OFF
L (MODE = H)
H (MODE = L)
tPGD
N/A
Shutdown
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After power up, PG is pulled low initially. The device initiates an inrush sequence in which the gate driver circuit
starts charging the gate capacitance from the internal charge pump. When the FET gate voltage reaches the full
overdrive indicating that the inrush sequence is complete and the device is capable of delivering full power, the
PG pin is asserted HIGH after a de-glitch time (tPGA).
The PG is de-asserted if the FET is turned off at any time during normal operation. The PG de-assertion de-
glitch time is tPGD
.
Overload Event
Overcurrent blanking timer expired
Device Enabled
VUVLO(R)
0
EN/UVLO
SWEN
0
IN
Slew rate (dVdt) controlled
startup/Inrush current limiting
0
VIN
Circuit-breaker action
OUT
0
VPG
PG
tPGA
0
dVdt
0
VOUT + 2.8 V
VHGate
0
tITIMER
IOCP
IINRUSH
IOUT
0
Time
图8-8. TPS25985x PG Timing Diagram
The PG is an open-drain pin and must be pulled up to an external supply.
When there is no supply to the device, the PG pin is expected to stay low. However, there is no active pulldown
in this condition to drive this pin all the way down to 0 V. If the PG pin is pulled up to an independent supply
which is present even if the device is unpowered, there can be a small voltage seen on this pin depending on the
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pin sink current, which is a function of the pullup supply voltage and resistor. Minimize the sink current to keep
this pin voltage low enough not to be detected as a logic HIGH by associated external circuits in this condition.
When the device is used in secondary mode (MODE = GND) in conjunction with another TPS25985 device as a
primary device in a parallel chain, it controls the PG assertion during start-up, but after the device reaches
steady-state, it no longer has control over the PG de-assertion. Refer to the Mode Selection (MODE) for more
details.
8.3.13 Output Discharge
The device has an integrated output discharge function which discharges the capacitors on the OUT pin using
an internal constant current (IQOD) to GND. The output discharge function is activated when the EN/UVLO is held
low (VSD(F) < VEN < VUVLO(F)) for a minimum interval (tQOD). The output discharge function helps to rapidly
remove the residual charge left on large output capacitors and prevents the bus from staying at some undefined
voltage for extended periods of time. The output discharge is disengaged when VOUT < VFB or if the device
detects a fault.
The output discharge function can result in excessive power dissipation inside the device leading to an increase
in junction temperature (TJ). The output discharge is disabled if the junction temperature (TJ) crosses TSD to
avoid long-term degradation of the part.
备注
In a primary+secondary parallel configuration, TI recommends to hold EN/UVLO voltage below the
VUVLO(F) threshold of the secondary device to activate output discharge for all the devices in the chain.
8.3.14 General Purpose Comparator
The device has a spare general purpose comparator whose inputs (CMPP, CMPM) and output (CMPOUT) are
not connected to any internal logic, thereby allowing the user complete flexibility to use this comparator as per
the system needs.
The comparator can be used for various purposes. Here are a few examples:
• Adjustable fast overcurrent detect (PROCHOT#): IMON pin is connected to CMPM input and an
appropriate reference voltage is connected to CMPP input. CMPOUT is connected to the PROCHOT# pin of
the processor. When the load current crosses the set threshold, the CMPOUT goes low and signals the
processor to throttle down immediately.
PROCHOTREF
CMPOUT
CMPP
PROCHOT#
+
CMPM
-
IMON
图8-9. Adjustable Fast Overcurrent (PROCHOT#) Detect Using Internal Comparator
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图8-10. PROCHOT# Response Using Internal Comparator
• Fast overvoltage protection with adjustable threshold: Input supply is connected to CMPM input through
a resistor divider and an appropriate reference voltage is connected to CMPP input. CMPOUT is connected
to the EN/UVLO pin. When the input supply crosses the set threshold, the CMPOUT goes low and turns off
the part.
VIN
OVREF
VIN
CMPOUT
CMPP
CMPM
+
-
SWEN
图8-11. Fast Overvoltage Protection with Adjustable Threshold Using Internal Comparator
• Load handshake or detect timer: An R-C network from VOUT supply is connected to CMPM input through
a resistor divider and an appropriate reference voltage is connected to the CMPP input. CMPOUT is
connected to the EN/UVLO pin. After the device turns on, the R-C on VOUT starts charging and after it
crosses the threshold, CMPOUT goes low to pull down the EN/UVLO and turn off the device, unless the
downstream circuit indicates it has powered up successfully by driving the CMPM input low within the
expected amount of time determined by the R-C time constant.
LDREF
VL
VIN
PG
CMPOUT
SWEN
VL
CMPP
+
-
CMPM
FROM
DOWNSTREAM
图8-12. Load Handshake or Detect Timer Using Internal Comparator
8.3.15 FET Health Monitoring
The TPS25985x can detect and report certain conditions which are indicative of a failure of the power path FET.
If undetected or unreported, these conditions can compromise system performance by not providing power to
the load correctly or by not providing the necessary level of protection. After a FET failure is detected, the
TPS25985x tries to turn off the internal FET by pulling the gate low and asserts the FLT pin.
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• D-S short: D-S short can result in a constant uncontrolled power delivery path formed from source to load,
either due to a board assembly defect or due to internal FET failure. This condition is detected at start-up by
checking if VIN-OUT < VDSFLT before the FET is turned ON. If yes, the device engages the internal output
discharge to try and discharge the output. If the VOUT does not discharge below VFB within a certain allowed
interval, the device asserts the FLT pin.
• G-D short: The TPS25985x detects this kind of FET failure at all times by checking if the gate voltage is
close to VIN even when the internal control logic is trying to hold the FET in OFF condition.
• G-S short: The TPS25985x detects this kind of FET failure during start-up by checking if the FET G-S
voltage fails to reach the necessary overdrive voltage within a certain timeout period (tSU_TMR) after the gate
driver is turned ON. While in steady-state, if the G-S voltage becomes low before the controller logic has
signaled to the gate driver to turn off the FET, it is latched as a fault.
8.3.16 Single Point Failure Mitigation
The TPS25985x relies on the proper component connections and biasing on the IMON, ILIM, IREF, and ITIMER
pins to provide overcurrent and short-circuit protection under all circumstances. As an added safety measure,
the device uses the following mechanisms to ensure that the device provides some form of overcurrent
protection even if any of these pins are not connected correctly in the system or the associated components
have a failure in the field.
8.3.16.1 IMON Pin Single Point Failure
• IMON pin open: In this case, the IMON pin voltage is internally pulled up to a higher voltage and exceeds the
threshold (VIREF), causing the part to perform a circuit-breaker action even if there is no significant current
flowing through the device.
• IMON pin shorted to GND directly or through a very low resistance: In this case, the IMON pin voltage is
held at a low voltage and is not allowed to exceed the threshold (VIREF) even if there is significant current
flowing through the device, thereby rendering the primary overcurrent protection mechanism ineffective. The
device relies on an internal overcurrent sense mechanism to provide some protection as a backup. If the
device detects that the backup current sense threshold (IOC_BKP) is exceeded but at the same time the
primary overcurrent detection on IMON pin fails, it triggers single point failure detection and latches a fault.
The FET is turned off and the FLT pin is asserted.
8.3.16.2 ILIM Pin Single Point Failure
• ILIM pin open: In this case, the ILIM pin voltage is internally pulled up to a higher voltage and exceeds the
VIREF threshold, causing the part to engage the current limit even if there is no significant current flowing
through the device.
• ILIM pin shorted to GND directly or through a very low resistance: In this case, the ILIM pin voltage is
held at a low voltage and is not allowed to exceed the start-up current limit threshold even if there is
significant current flowing through the device, thereby rendering the primary current limit mechanism
ineffective during start-up. The device relies on an internal overcurrent detection mechanism to provide some
protection as a backup. If the device detects that the backup overcurrent threshold (IOC_BKP) is exceeded
but at the same time the primary overcurrent detection on ILIM pin fails, it triggers single point failure
detection and latches a fault. The FET is turned off and the FLT pin is asserted.
8.3.16.3 IREF Pin Single Point Failure
• IREF pin open or forced to higher voltage: In this case, the IREF pin (VIREF) is pulled up internally or
externally to a voltage which is higher than the target value as per the recommended IOCP or ILIM calculations,
preventing the primary circuit-breaker, active current limit, and short-circuit protection from getting triggered
even if there is significant current flowing through the device. The device relies on an internal overcurrent
detection mechanism to provide some protection as a backup. If the device detects that the backup
overcurrent threshold is exceeded but at the same the primary overcurrent or short-circuit detection on ILIM
or IMON pin fails, it triggers single point failure detection and latches a fault. The FET is turned off and the
FLT pin is asserted.
• IREF pin shorted to GND: In this case, the VIREF threshold is set to 0 V, causing the part to perform active
current limit or circuit-breaker action even if there is no significant current flowing through the device.
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8.3.16.4 ITIMER Pin Single Point Failure
• ITIMER pin open or short to GND: In this case, the ITIMER pin is already discharged below VITIMERTHR and
hence indicates overcurrent blanking timer expiry instantaneously after an overcurrent event and triggers a
circuit-breaker action without any delay.
• ITIMER pin forced to some voltage higher than VITIMERTHR: In this case, the ITIMER pin is unable to
discharge below VITIMERTHR and hence fails to indicate overcurrent blanking timer expiry, thereby rendering
the primary circuit-breaker mechanism ineffective. The device relies on a backup overcurrent timer
mechanism to provide some protection as a backup. If the device detects an overcurrent event on either the
IMON pin or the backup overcurrent detection circuit, the device engages the internal backup time and after
the timer expires (tSPFLTMR), it latches a fault. The FET is turned off and the FLT pin is asserted.
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8.4 Device Functional Modes
The features of the device depend on the operating mode. 表 8-5 and 表 8-6 summarize the device functional
modes.
表8-5. Device Functional Modes Based on EN/UVLO Pin
Pin: EN/UVLO
Device State
Output Discharge
> VUVLO(R)
> VSD(F) , < VUVLO(F) (< tQOD
> VSD(F) , < VUVLO(F) (> tQOD
< VSD(F)
Fully ON
Disabled
)
)
FET OFF
FET OFF
Shutdown
Disabled
Enabled
Disabled
表8-6. Device Functional Modes Based on MODE Pin
Pin: MODE
Device Configuration
Open
GND
Primary or standalone
Secondary
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9 Application and Implementation
备注
Information in the following applications sections is not part of the TI component specification, and TI
does not warrant its accuracy or completeness. TI’s customers are responsible for determining
suitability of components for their purposes, as well as validating and testing their design
implementation to confirm system functionality.
9.1 Application Information
The TPS25985x is a high-current eFuse that is typically used for power rail protection applications. The device
operates from 4.5 V to 16 V with input overvoltage and adjustable undervoltage protection. The device provides
ability to control inrush current and offers protection against overcurrent and short-circuit conditions. The device
can be used in a variety of systems such as server motherboards, add-on cards, graphics cards, accelerator
cards, enterprise switches, routers, and so forth. The design procedure explained in the subsequent sections
can be used to select the supporting component values based on the application requirements. Additionally, a
spreadsheet design tool, TPS25985x Design Calculator is available in the web product folder.
9.1.1 Single Device, Standalone Operation
TPS25985x
IN
VIN
VOUT
OUT
IREF
VDD
IMON
IMON
TEMP
EN
EN/UVLO
MODE
VL
VL
VLSTBY
PG
PG
SWEN
FLT
ITIMER GND
ILIM DVDT
FLT
图9-1. Single Device, Standalone Operation
备注
The MODE pin is left OPEN to configure for standalone operation.
Other variations:
1. The IREF pin can be driven from an external reference voltage source.
2. In a host MCU controlled system, EN/UVLO can be connected to a GPIO pin to control the device. IMON pin
voltage can be monitored using an ADC. The host MCU can use a DAC to drive IREF to change the current
limit threshold dynamically.
3. The device can be used as a simple high current load switch without adjustable overcurrent or fast-trip
protection by tying the ILIM and IMON pins to GND and leaving the IREF pin open. The inrush current
protection, fixed fast-trip and internal fixed overcurrent protection are still active in this condition.
4. The CMPP, CMPM, and CMPOUT pins can be used to implement adjustable OVP or PG thresholds or
PROCHOT# or Load Handshake timer functionality as described in the General Purpose Comparator
section.
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9.1.2 Multiple Devices, Parallel Connection
Applications which need higher current capability can use two or more TPS25985x devices connected in parallel
as shown in 图9-2.
TPS25985x
IN
VIN
VOUT
OUT
IREF
VDD
TEMP
IMON
EN
EN/UVLO
MODE
VL
VL
VLSTBY
PG
PG
SWEN
FLT
FLT
ITIMER GND
ILIM
DVDT
TPS25985x
IN
OUT
IREF
TEMP
IMON
VDD
IMON
EN/UVLO
PG
ITIMER
SWEN
FLT
MODE
ILIM
DVDT
GND
TPS25985x
IN
OUT
IREF
TEMP
IMON
VDD
TEMP
EN/UVLO
PG
ITIMER
SWEN
FLT
MODE GND
ILIM
DVDT
图9-2. Devices Connected in Parallel for Higher Current Capability
In this configuration, one TPS25985x device is designated as the primary device and controls the other
TPS25985x devices in the chain which are designated as secondary devices. This configuration is achieved by
connecting the primary device as follows:
1. VDD is connected to IN through an R-C filter.
2. MODE pin is left OPEN.
3. ITIMER is connected through capacitor to GND.
4. DVDT is connected through capacitor to GND.
5. IREF is connected through resistor to GND.
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6. IMON is connected through resistor to GND.
7. ILIM is connected through resistor to GND.
8. SWEN is pulled up to a 3.3-V to 5-V standby rail. This rail must be powered up independent of the eFuse.
The secondary devices must be connected in the following manner:
1. VDD is connected to IN through a R-C filter.
2. MODE pin is connected to GND.
3. ITIMER pin is left OPEN.
4. ILIM is connected through resistor to GND.
The following pins of all devices must be connected together:
1. IN
2. OUT
3. EN/UVLO
4. DVDT
5. SWEN
6. PG
7. IMON
8. IREF
In this configuration, all the devices are powered up and enabled simultaneously.
Power up: After power up or enable, all devices initially hold their SWEN low till the internal blocks are biased
and initialized correctly. After that, each device releases its own SWEN. After all devices have released their
SWEN, the combined SWEN goes high and the devices are ready to turn on their respective FETs at the same
time.
Inrush: During inrush, because the DVDT pins are tied together to a single DVDT capacitor all the devices turn
on the output with the same slew rate (SR). Choose the common DVDT capacitor (CDVDT) as per the following
方程式17 and 方程式18.
I
A
INRUSH
SR V/ms =
(17)
C
mF
LOAD
42000
SR V/ms
C
pF =
(18)
DVDT
In this condition, the internal balancing circuit ensures that the load current is shared among all devices during
start-up. This action prevents a situation where some devices turn on faster than others and experience more
thermal stress as compared to other devices. This can potentially result in premature or partial shutdown of the
parallel chain, or even SOA damage to the devices. The current balancing scheme ensures the inrush capability
of the chain scales according to the number of devices connected in parallel, thereby ensuring successful start-
up with larger output capacitances or higher loading during start-up.
All devices hold their respective PG signals low during start-up. After the output ramps up fully and reaches
steady-state, each device releases its own PG pulldown. Because the DVDT pins of all devices are tied together,
the internal gate high detection of all devices is synchronized. There can be some threshold or timing
mismatches between devices leading to PG assertion in a staggered manner. However, since the PG pins of all
devices are tied together, the combined PG signal becomes high only after all devices have released their PG
pulldown. This signal is sent to the downstream loads to allow power to be drawn.
Steady-state: During steady-state, all devices share current equally using the active current sharing mechanism
which actively regulates the respective device RDSON to evenly distribute current across all the devices in the
parallel chain.
Overcurrent during steady-state: The circuit-breaker threshold for the parallel chain is based on the total
system current rather than the current flowing through individual devices. This is done by connecting the IMON
pins of all the devices together. Similarly, the IREF pins of all devices are tied together and connected to a single
RIREF (or an external VIREF source) to generate a common reference for the overcurrent protection block in all
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the devices. This action helps minimize the contribution of IIREF variation and RIREF tolerance to the overall
mismatch in overcurrent threshold between devices. In this case, choose the combined RIMON as per the
following 方程式19:
I
× R
IREF
IREF
R
=
(19)
IMON
G
× I
IMON
OCP TOTAL
The RILIM value for each individual eFuse must be selected based on the following 方程式20.
1.1 × N × R
IMON
R
=
(20)
ILIM
3
Where N = number of devices in parallel chain.
Other variations:
The IREF pin can be driven from an external voltage reference (VIREF).
V
IREF
R
=
(21)
IMON
G
× I
IMON
OCP TOTAL
During an overcurrent event, the overcurrent detection of all the devices is triggered simultaneously. This in turn
triggers the overcurrent blanking timer (ITIMER) on each device. However, only the primary device uses the
ITIMER expiry event as a trigger to pull the SWEN low for all the devices, thereby initiating the circuit-breaker
action for the whole chain. This mechanism ensures that mismatches in the current distribution, overcurrent
thresholds and ITIMER intervals among the devices do not degrade the accuracy of the circuit-breaker threshold
of the complete parallel chain or the overcurrent blanking interval.
However, the secondary devices also start their backup overcurrent timer and can trigger the shutdown of the
whole chain if the primary device fails to do so within a certain interval.
Severe overcurrent (short-circuit): If there is a severe fault at the output (for example, output shorted to
ground with a low impedance path) during steady-state operation, the current builds up rapidly to a high value
and triggers the fast-trip response in each device. The devices use two thresholds for fast-trip protection – a
user-adjustable threshold (ISFT = 2 × IOCP in steady-state or ISFT = 2 × ILIM during inrush) as well as a fixed
threshold (IFFT only during steady-state). After the fast-trip, the devices enter into a latch-off fault condition till the
device is power cycled or re-enabled or expires the auto-retry timer (only for auto-retry variants).
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9.2 Typical Application: 12-V, 3.6-kW Power Path Protection in Datacenter Servers
9.2.1 Application
This design example considers a 12-V system operating voltage with a tolerance of ±10%. The maximum
steady-state load current is 300 A. If the load current exceeds 330 A, the eFuse circuit must allow transient
overload currents up to a 16-ms interval. For persistent overloads lasting longer than that, the eFuse circuit must
break the circuit and then latch-off. The eFuse circuit must charge a bulk capacitance of 55 mF and support
approximately 12% of the steady-state load during start-up. 图 9-3 shows the application schematic for this
design example.
TPS25985x
OUT
IN
VOUT
VIN
1 nF
R1
10
0.1 µF
R2
IREF
TEMP
IMON
VDD
2.2 µF
RIREF
2.2 µF
IMON
PG
EN
EN/UVLO
PG
MODE
SWEN
1 nF
FLT
FLT1
*Power supply input (VIN)
to the eFuse(s) must be
used to derive VSWEN
ITIMER GND ILIM
DVDT
10 k
100 k
*
22 pF
RIMON
.
CDVDT
VDD-PULLUP
VSWEN
(2.5 V
to 5 V)
10 k
TPS25985x
VDD-PULLUP
The non-repetitive peak
forward surge current (IFSM
IN
OUT
)
of the selected diode must
be more than the fast-trip
threshold (2 × IOCP(TOTAL)).
Two or more Schottky
diodes in parallel must be
used if a single Schottky
diode is unable to meet the
required IFSM rating.
10
Maximum Clamping Voltage VC
specification of the selected TVS
diode at Ipp (10/1000 s) (V) must
be lower than the absolute
maximum rating of the power
input (IN) pin for safe operation of
the eFuse.
0.1 µF
IREF
TEMP
IMON
VDD
2.2 µF
2.2 µF
eFuse - 2
EN/UVLO
VDD-PULLUP
PG
ITIMER
SWEN
N = 5
R1 = 1 M
FLT2
FLT
R2 = 124 k
RIREF = 40.2 k
RIMON = 167
RILIM1 = 300
RILIM2 = 300
RILIM3 = 300
RILIM4 = 300
RILIM5 = 300
CITIMER = 22 nF
CDVDT = 33 nF
MODE GND
ILIM DVDT
RILIM2
TPS25985x
IN
OUT
VDD-PULLUP
**
**Required only if the number
of devices connected in
parallel is more than six (6).
10
0.1 µF
IREF
TEMP
IMON
VDD
10 k
2.2 µF
eFuse - N
TEMP
22 pF
VDD-PULLUP
10 k
EN/UVLO
PG
ITIMER
SWEN
MODE
FLT
FLTN
DVDT
GND
ILIM
ꢀꢁVDD-PULLUP should be less than 5V.
ꢀꢁVDD-PULLUP and VSWEN can be the same
RILIMN
pullup supply if both are generated
0
from the input (VIN) of the eFuse(s).
图9-3. Application Schematic for a 12-V, 3.6-kW Power Path Protection Circuit
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9.2.2 Design Requirements
表9-1 shows the design parameters for this application example.
表9-1. Design Parameters
PARAMETER
VALUE
Input voltage range (VIN)
10.8 V –13.2 V
Maximum DC load current (IOUT(max)
Maximum output capacitance (CLOAD
Are all the loads off until the PG is asserted?
Load at start-up (RLOAD(Startup)
)
300 A
)
55 mF
No
0.33 Ω(equivalent to approximately 12% of the maximum steady-
)
state load)
Maximum ambient temperature
Transient overload blanking timer
55°C
16 ms
1.2 V/ms
Yes
Output voltage slew rate
Need to survive a “hot-short”on output condition ?
Yes
Need to survive a “power up into short”condition?
Can a board be hotplugged in or power cycled?
Yes
Load current monitoring needed?
Fault response
Yes
Latch-off
9.2.3 Detailed Design Procedure
• Determining the number of eFuse devices to be used in parallel
By factoring in a small variation in the junction to ambient thermal resistance (RθJA), a single TPS25985x
eFuse is rated at a maximum steady state DC current of 60 A with a maximum junction temperature of less
than 125°C. Therefore, 方程式22 can be used to calculate the number of devices (N) to be in parallel to
support the maximum steady state DC load current (ILOAD(max)), for which the solution must be designed.
I
A
OUT max
N ≥
(22)
60 A
According to 表9-1, IOUT(max) is 300 A. Therefore, five (5) TPS25985 eFuses are connected in parallel.
• Setting up the primary and secondary devices in a parallel configuration
The MODE pin is used to configure one TPS25985x eFuse as the primary device in a parallel chain along
with the other TPS25985x eFuses as the secondary devices. As a result, some of the TPS25985 pin
functionalities can be changed to facilitate primary and secondary configuration as described in Multiple
Devices, Parallel Connection.
Leaving the pin open configures the corresponding device as the primary one. For the secondary devices,
this pin must be connected to GND.
• Selecting the CDVDT capacitor to control the output slew rate and start-up time
For a robust design, the junction temperature of the device must be kept below the absolute maximum rating
during both dynamic (start-up) and steady-state conditions. Typically, dynamic power stresses are orders of
magnitude greater than static stresses, so it is crucial to establish the right start-up time and inrush current
limit for the capacitance in the system and the associated loads to avoid thermal shutdown during start-up.
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表9-2 summarizes the formulas for calculating the average inrush power loss on the eFuses in the presence
of different loads during start-up if the power-good (PG) signal is not used to turn on all the downstream
loads.
表9-2. Calculation of Average Power Loss During Inrush
Type of Loads During Start-Up
Expressions to Calculate the Average Inrush Power Loss
2
V
V
V
V
C
IN LOAD
Only output capacitor of CLOAD (µF)
(23)
(24)
(25)
(26)
2T
ss
2
2
Output capacitor of CLOAD (µF) and constant resistance
2
3
C
V
V
V
V
RTH
IN LOAD
IN
LOAD Startup
1
6
1
2
RTH
1
3
+
−
+
2T
R
V
V
of RLOAD(Startup) (Ω) with turn-ON threshold of VRTH (V)
ss
IN
IN
2
2
Output capacitor of CLOAD (µF) and constant current of
ILOAD(Startup) (A) with turn-ON threshold of VCTH (V)
C
V
CTH
IN LOAD
1
2
CTH
1
+ V
I
−
+
2
IN LOAD Startup
2T
V
V
ss
IN
IN
2
Output capacitor of CLOAD (µF) and constant power of
PLOAD(Startup) (W) with turn-ON threshold of VPTH (V)
C
V
V
PTH
IN LOAD
PTH
+ P
ln
+
− 1
LOAD Startup
2T
V
V
ss
IN
IN
Where VIN is the input voltage and Tss is the start-up time.
With the different combinations of loads during start-up, the total average inrush power loss (PINRUSH) can be
calculated using the formulas described in 表9-2. For a successful start-up, the system must satisfy the
condition stated in 方程式27.
P
W
T
s < 12 × N
(27)
INRUSH
ss
Where N denotes the number of eFuses in parallel and 12 W√s is the SOA limit of a single TPS25985x
eFuse. This equation can be used to obtain the maximum allowed Tss.
备注
TI recommends to use a Tss in the range of 5 ms to 120 ms to prevent start-up issues.
A capacitor (CDVDT) must be added at the DVDT pin to GND to set the required value of Tss as calculated
above. 方程式28 is used to compute the value of CDVDT. The DVDT pins of all the eFuses in a parallel chain
must be connected together.
42000
C
pF =
(28)
DVDT
V
V /T ms
IN
ss
In this design example, CLOAD = 55 mF, RLOAD(Startup) = 0.33 Ω, VRTH = 0 V, VIN = 12 V, and Tss = 10 ms.
INRUSH is calculated to be 469 W using the equations provided in the 表9-2. It is verified that the system
P
satisfies condition state in 方程式27 and therefore capable of having a successful start-up. If 方程式27 does
not hold true, start-up loads or Tss must be tuned to prevent chances of thermal shutdown during start-up.
Using VIN = 12 V, Tss = 10 ms and 方程式28, the required CDVDT value can be calculated to be 35 nF. The
closest standard value of CDVDT is 33 nF with 10% tolerance and DC voltage rating of 25 V.
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备注
In some systems, there can be active load circuits (for example, DC-DC converters) with low turn-
on threshold voltages which can start drawing power before the eFuse has completed the inrush
sequence. This action can cause additional power dissipation inside the eFuse during start-up and
can lead to thermal shutdown. TI recommends using the Power Good (PG) pin of the eFuse to
enable and disable the load circuit. This action ensures that the load is turned on only when the
eFuse has completed its start-up and is ready to deliver full power without the risk of hitting thermal
shutdown.
• Selecting the RIREF resistor to set the reference voltage for overcurrent protection and active current
sharing
In this parallel configuration, the IREF internal current source (IIREF) of the primary eFuse interacts with the
external IREF pin resistor (RIREF) to generate the reference voltage (VIREF) for the overcurrent protection and
active current sharing blocks. When the voltage at the IMON pin (VIMON) is used as an input to an ADC to
monitor the system current or to implement the Platform Power Control (Intel PSYS) functionality inside the
VR controller, VIREF must be set to half of the maximum voltage range of the ISYS_IN input of the controller.
This action provides the necessary headroom and dynamic range for the system to accurately monitor the
load current up to the fast-trip threshold (2 × IOCP). 方程式29 is used to calculate the value of RIREF
.
V
= I
× R
IREF
(29)
IREF
IREF
In this design example, VIREF is set at 1 V. With IIREF = 25 µA (typical), we can calculate the target RIREF to be
40 kΩ. The closest standard value of RIREF is 40.2 kΩwith 0.1% tolerance and power rating of 100 mW. For
improved noise immunity, place a 1-nF ceramic capacitor from the IREF pin to GND.
备注
Maintain VIREF within the recommended voltage to ensure proper operation of overcurrent
detection circuit.
• Selecting the RIMON resistor to set the overcurrent (circuit-breaker) and fast-trip thresholds during
steady-state
TPS25985x eFuse responds to the output overcurrent conditions during steady-state by turning off the output
after a user-adjustable transient fault blanking interval. This eFuse continuously senses the total system
current (IOUT) and produces a proportional analog current output (IIMON) on the IMON pin. This generates a
voltage (VIMON) across the IMON pin resistor (RIMON) in response to the load current, which is defined as 方程
式30.
V
= I
× G
× R
IMON
(30)
IMON
OUT
IMON
GIMON is the current monitor gain (IIMON : IOUT), whose typical value is 18.18 µA/A. The overcurrent condition
is detected by comparing the VIMON against the VIREF as a threshold. The circuit-breaker threshold during
steady-state (IOCP) can be calculated using 方程式31.
V
IREF
I
=
(31)
OCP(TOTAL)
G
× R
IMON
IMON
In this design example, IOCP(TOTAL) is considered to be 1.1 times IOUT(max). Hence, IOCP(TOTAL) is set at 330 A,
and RIMON can be calculated to be 166.67 Ωwith GIMON as 18.19 µA/A and VIREF as 1 V. The nearest value
of RIMON is 167 Ωwith 0.1% tolerance and power rating of 100 mW. For noise reduction, place a 22-pF
ceramic capacitor across the IMON pin and GND.
备注
A system output current (IOUT) must be considered when selecting RIMON, not the current carried
by each device.
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• Selecting the RILIM resistor to set the current limit and fast-trip thresholds during start-up and the
active sharing threshold during steady-state
RILIM is used in setting up the active current sharing threshold during steady-state and the overcurrent limit
during startup among the devices in a parallel chain. Each device continuously monitors the current flowing
through it (IDEVICE) and outputs a proportional analog output current on its own ILIM pin. This in turn produces
a proportional voltage (VILIM) across the respective ILIM pin resistor (RILIM), which is expressed as 方程式32.
V
= I
× G
× R
ILIM
(32)
ILIM
DEVICE
ILIM
GILIM is the current monitor gain (IILIM : IDEVICE), whose typical value is 18.18 μA/A.
– Active current sharing during steady-state: This mechanism operates only after the device reaches
steady-state and acts independently by comparing its own load current information (VILIM) with the Active
Current Sharing reference (CLREFLIN) threshold, defined as 方程式33.
1.1 × V
IREF
CLREF
=
(33)
LIN
3
Therefore, RILIM must be calculated using 方程式34 to define the active current sharing threshold as
IOCP(TOTAL)/N, where N is the number of devices in parallel. Using N = 5, RIMON = 167 Ω, and 方程式34,
RILIM can be calculated to be 306.2 Ω. The closest standard value of 300 Ωwith 0.1% tolerance and
power rating of 100 mW resistances are selected as RILIM for each device.
1.1 × N × R
IMON
R
=
(34)
ILIM
3
备注
To determine the value of RILIM, 方程式35 must be used if a different threshold for active
current sharing (ILIM(ACS)) than IOCP/N is desired.
1.1 × V
IREF
R
=
(35)
ILIM
3 × G
ILIM
× I
LIM ACS
When computing the current limit threshold during start-up in the next sub-section, ensure to
use this RILIM value.
– Overcurrent limit during start-up: During inrush, the overcurrent condition for each device is detected
by comparing its own load current information (VILIM) with a scaled reference voltage as depicted in 方程
式36.
0.7 × V
IREF
CLREF
=
(36)
SAT
3
The current limit threshold during start-up can be calculated using 方程式37.
CLREF
SAT
I
=
G
(37)
ILIM Startup
× R
ILIM
ILIM
By using a RILIM value of 300 Ωfor each device, the start-up current is limited to ~43 A for each device
and the ILIM(ACS) is set at ~67 A.
备注
The active current limit block employs a foldback mechanism during start-up based on VOUT
.
When VOUT is below the foldback threshold (VFB) of 1.99 V, the current limit threshold is further
lowered.
• Selecting the CITIMER capacitor to set the overcurrent blanking timer
An appropriate capacitor must be connected at the ITIMER pin to ground of the primary or standalone device
to adjust the duration for which the load transients above the circuit-breaker threshold are allowed. The
transient overcurrent blanking interval can be calculated using 方程式38.
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C
nF × ∆ V V
ITIMER
ITIMER
t
ms =
(38)
ITIMER
I
μA
ITIMER
Where tITIMER is the transient overcurrent blanking timer and CITIMER is the capacitor connected between
ITIMER pin of the primary device and GND. IITIMER = 2.07 µA (typical) and ΔVITIMER = 1.5 V (typical). A 22-
nF capacitor with 10% tolerance and DC voltage rating of 25 V is used as the CITIMER for the primary device
in this design, which results in 16.5 ms of tITIMER. The ITIMER pin for all the secondary devices should be left
open.
• Selecting the resistors to set the undervoltage lockout threshold
The undervoltage lockout (UVLO) threshold is adjusted by employing the external voltage divider network of
R1 and R2 connected between IN, EN/UVLO, and GND pins of the device as described in Undervoltage
protection section. The resistor values required for setting up the UVLO threshold are calculated using 方程式
39.
R
+ R
2
1
V
= V
(39)
IN UV
UVLO R
R
2
To minimize the input current drawn from the power supply, TI recommends using higher resistance values
for R1 and R2. The current drawn by R1 and R2 from the power supply is IR12 = VIN / (R1 + R2). However, the
leakage currents due to external active components connected to the resistor string can add errors to these
calculations. So, the resistor string current, IR12 must be 20 times greater than the leakage current at the EN/
UVLO pin (IENLKG). From the device electrical specifications, IENLKG is 0.1 µA (maximum) and UVLO rising
threshold VUVLO(R) = 1.2 V. From the design requirements, VINUVLO = 10.8 V. First choose the value of R1 = 1
MΩ and use 方程式39 to calculate R2 = 125 kΩ. Use the closest standard 1 % resistor values: R1 = 1 MΩ
and R2 = 124 kΩ. For noise reduction, place a 1-nF ceramic capacitor across the EN/UVLO pin and GND.
• Selecting the R-C filter between VIN and VDD
VDD pin is intended to power the internal control circuitry of the eFuse with a filtered and stable supply, not
affected by system transients. Therefore, use an R (10 Ω) –C (2.2 µF) filter from the input supply (IN pin) to
the VDD pin. This helps to filter out the supply noises and to hold up the controller supply during severe faults
such as short-circuit at the output. In a parallel chain, this R-C filter must be employed for each device.
• Selecting the pullup resistors and power supplies for SWEN, PG, FLT, and CMPOUT pins
FLT, PG, and CMPOUT are the open drain outputs. If these logic signals are used, the corresponding pins
must be pulled up to an appropriate supply rail voltage through 10-kΩpullup resistances.
SWEN pin must be pulled up to a voltage in the range of 2.5 V to 5 V through a 100-kΩresistance.
This pullup power supply must be generated from the input (VIN) to the eFuse and available before
the eFuse is enabled, without which the eFuse cannot start up.
• Selection of TVS diode at input and Schottky diode at output
In the case of a short circuit and overload current limit when the device interrupts a large amount of current
instantaneously, the input inductance generates a positive voltage spike on the input, whereas the output
inductance creates a negative voltage spike on the output. The peak amplitudes of these voltage spikes
(transients) are dependent on the value of inductance in series with the input or output of the device. Such
transients can exceed the absolute maximum ratings of the device and eventually lead to failures due to
electrical overstress (EOS) if appropriate steps are not taken to address this issue. Typical methods for
addressing this issue include:
1. Minimize lead length and inductance into and out of the device.
2. Use a large PCB GND plane.
3. Addition of the Transient Voltage Suppressor (TVS) diodes to clamp the positive transient spike at the
input.
4. Using Schottky diodes across the output to absorb negative spikes.
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Refer to TVS Clamping in Hot-Swap Circuits and Selecting TVS Diodes in Hot-Swap and ORing Applications
for details on selecting an appropriate TVS diode and the number of TVS diodes to be in parallel to effectively
clamp the positive transients at the input below the absolute maximum ratings of the IN pin (20 V). These
TVS diodes also help to limit the transient voltage at the IN pin during the Hot Plug event. Four (4) SMDJ12A
are used in parallel in this design example.
备注
Maximum Clamping Voltage VC specification of the selected TVS diode at Ipp (10/1000 μs) (V)
must be lower than the absolute maximum rating of the power input (IN) pin for safe operation of
the eFuse.
Selection of the Schottky diodes must be based on the following criteria:
– The non-repetitive peak forward surge current (IFSM) of the selected diode must be more than the fast-trip
threshold (2 × IOCP(TOTAL)). Two or more Schottky diodes in parallel must be used if a single Schottky
diode is unable to meet the required IFSM rating. 方程式40 calculates the number of Schottky diodes
(NSchottky) that must be in parallel.
2 × I
OCP TOTAL
N
>
(40)
Scℎottky
I
FSM
– Forward Voltage Drop (VF) at near to IFSM must be as small as possible. Ideally, the negative transient
voltage at the OUT pin must be clamped within the absolute maximum rating of the OUT pin (–1 V).
– DC Blocking Voltage (VRM) must be more than the maximum input operating voltage.
– Leakage current (IR) must be as small as possible.
Three (3) SBR10U45SP5 are used in parallel in this design example.
• Selecting CIN and COUT
TI recommends to add ceramic bypass capacitors to help stabilize the voltages on the input and output. The
value of CIN must be kept small to minimize the current spike during hot-plug events. For each device, 0.1 µF
of CIN is a reasonable target. Because COUT does not get charged during hot-plug, a larger value such as 2.2
µF can be used at the OUT pin of each device.
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9.2.4 Application Performance Plots
All the waveforms below are captured on an evaluation setup with five (5) TPS25985 eFuses in parallel. All the
pullup supplies are derived from a separate standby rail.
VIN
VIN
EN/UVLO
SWEN
EN/UVLO
SWEN
DVDT
VOUT
DVDT
VOUT
PG
PG
FLTb
FLTb
Input
Input
Current
Current
图9-4. Input Hot Plug: VIN Stepped Up from 0 V to
12 V, CLOAD = 55 mF, CDVDT = 33 nF, RIREF = 40.2
kΩ, and RILIM on Each Device = 300 Ω
图9-5. Start-up with EN/UVLO: VIN = 12 V, EN/UVLO
Stepped Up From 0 V to 3 V, CLOAD = 55 mF,
RLOAD(Start-up) = 0.33 Ω, CDVDT = 33 nF, RIREF = 40.2
kΩ, and RILIM on Each Device = 300 Ω
VIN
EN/UVLO
SWEN
DVDT
VOUT
PG
FLTb
Input
Current
图9-6. Start-up with EN/UVLO (Current distribution
among five devices in parallel): VIN = 12 V, EN/
UVLO Stepped Up From 0 V to 3 V, CLOAD = 55 mF,
图9-7. Power Up into Short: VIN = 12 V, EN/UVLO
Stepped Up From 0 V to 3 V, RIREF = 40.2 kΩ, RILIM
on Each Device = 300 Ω, and OUT Shorted to GND
CDVDT = 33 nF, RIREF = 40.2 kΩ, and RILIM on Each
Device = 300 Ω
VIN
VOUT
SWEN
TIMER
IMON
PG
FLTb
Load Current
(Derived from IMON)
图9-8. Power Up into Short (Current distribution
among five devices in parallel): VIN = 12 V, EN/
UVLO Stepped Up From 0 V to 3 V, RIREF = 40.2 kΩ,
RILIM on Each Device = 300 Ω, and OUT Shorted to
GND
图9-9. Transient Overload: VIN = 12 V, CITIMER = 22
nF, CLOAD = 55 mF, RIMON = 167 Ω, RIREF = 40.2 kΩ,
and Load Current Stepped from 300 A to 400 A
then 300 A within 10 ms
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VIN
VOUT
SWEN
TIMER
IMON
PG
FLTb
Load Current
(Derived from IMON)
图9-10. Transient Overload (Current distribution
among five devices in parallel): VIN = 12 V, CITIMER
= 22 nF, CLOAD = 55 mF, RIMON = 167 Ω, RIREF = 40.2
kΩ, and Load Current Stepped from 300 A to 450 A
then 300 A within 8.5 ms
图9-11. Circuit-Breaker Response: VIN = 12 V,
ITIMER = 22 nF, CLOAD = 55 mF, RIMON = 167 Ω,
RIREF = 40.2 kΩ, and Load Current Stepped up
C
From 300 A to 500 A for > 20 ms
图9-13. Output Hot-Short Response: VIN = 12 V,
图9-12. Circuit-Breaker Response (Current
distribution among five devices in parallel): VIN
12 V, CITIMER = 22 nF, CLOAD = 55 mF, RIMON = 167
Ω, RIREF = 40.2 kΩ, and Load Current Stepped up
From 300 A to 475 A for > 20 ms
RIMON = 167 Ω, RIREF = 40.2 kΩ, and OUT Shorted
=
to GND
图9-14. Two (2) TPS25985x eFuses in Parallel: Temperature Rise with 100-A DC Current at Room
Temperature (No Air-Flow)
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9.3 Multiple eFuses, Parallel Connection with PMBus®
Applications which need higher current input protection along with digital interface for telemetry, control,
configurability can use one or more TPS25985x device(s) in parallel with TPS25990x as shown in 图9-15
VL
VL
VL
TPS25990x
ADDR0
ADDR1
AUX
SCL
SCL
SDA
SDA
SMBA#
SMBA#
VOUT
IN
OUT
IREF/DAC2
TEMP/CMP
VIN
VDD
IMON
IMON
VL VL
EN/UVLO
EN
VLSTBY
PG
PG
SWEN
FLT
FLT
GND
ILIM
DVDT
TPS25985x
IN
OUT
IREF
TEMP
IMON
VDD
EN/UVLO
PG
ITIMER
SWEN
FLT
MODE GND
ILIM
DVDT
TPS25985x
IN
OUT
IREF
TEMP
IMON
VDD
EN/UVLO
PG
ITIMER
SWEN
FLT
GND ILIM DVDT
MODE
图9-15. TPS25990x Connected in Parallel with TPS25985x For Higher Current Support With PMBus®
TPS25990x is a 60-A integrated eFuse with PMBus Telemetry interface.
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In this configuration, the TPS25990x acts as the primary device and controls the other TPS25985x devices in the
chain which are designated as secondary devices. This configuration is achieved by connecting the primary
device as follows:
1. VDD is connected to IN through an R-C filter.
2. DVDT is connected through capacitor to GND.
3. IREF is connected through capacitor to GND.
4. IMON is connected through resistor to GND.
5. ILIM is connected through resistor to GND.
SWEN is pulled up to a 3.3-V to 5-V standby rail. This rail must be powered up independent of the eFuse
ON/OFF status.
The secondary devices must be connected in the following manner:
1. VDD is connected to IN through a R-C filter.
2. MODE pin is connected to GND.
3. ITIMER pin is left OPEN.
4. ILIM is connected through resistor to GND.
The following pins of all devices must be connected together:
1. IN
2. OUT
3. EN/UVLO
4. DVDT
5. SWEN
6. PG
7. IMON
8. IREF
9. TEMP
In this configuration, all the devices are powered up and enabled simultaneously.
• The TPS25990x monitors the combined VIN, VOUT, IMON, TEMP and reports it over the PMBus telemetry
interface.
• THE OVLO threshold is set to max value in all devices by default. For TPS25985x devices, the OV threshold
is fixed in hardware and cannot be changed. The TPS25990x OV threshold can be lowered through PMBus
writes to the VIN_OV_FAULT register. In this case, the TPS25990x uses the SWEN pin to turn off the
TPS25985x devices during OV conditions.
• The UVLO threshold for all devices is set by the external resistor divider from IN to GND on the EN/UVLO
pin. The TPS25990x UV threshold can be changed through PMBus writes to the VIN_UV_FAULT register. In
this case, the TPS25990x uses the SWEN pin to turn off the TPS25985x devices during UV conditions.
• During inrush, the output of all the devices are ramped together based on the DVDT cap. However, the
TPS25990x DVDT sourcing current can be configured through the PMBus to change the inrush behavior of
the whole chain. The TPS25990x controls the DVDT ramp rate for the whole chain and secondary devices
simply follow the ramp rate.
• Due to the inherent difference in Rdson, the current carried by the TPS25990x is lower than the TPS25985x
devices. Accordingly, the start-up current limit threshold and active current sharing threshold for the
TPS25990x has to be set to a relatively lower value as compared to all the TPS25985x devices by
connecting a proportionately higher ILIM resistor.
• The TPS25990x controls the overall overcurrent threshold of the parallel chain by setting the VIREF threshold
voltage using its internal DAC. The VIREF voltage can be programmed through PMBus to change the
overcurrent threshold.
• The TPS25990x controls the transient overcurrent blanking interval (tOC_TIMER) for the whole system through
PMBus writes to the OC_TIMER register. After the digital timer expires, the TPS25990x pulls the SWEN pin
low to signal all devices to break the circuit simultaneously.
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• The system Power Good (PG) indication is a combination of all the individual device PG indications. All the
devices hold their respective PG pins low till their power FET is fully turned on. After all devices have reached
steady-state, they release their respective PG pin pulldown and the PG signal for the whole chain is asserted
high. The TPS25985x secondary devices have control over the system PG assertion only during startup.
After in steady state, only the TPS25990x controls the de-assertion of the PG based on the VOUT_PGTH
register setting.
• The fault indication (FLT) for the whole system is provided by TPS25990x. However, each secondary device
also asserts its own FLT independently.
Power up: After power up or enable, all the eFuse devices initially hold their SWEN low till the internal blocks
are biased and initialized correctly. After that, each device releases its own SWEN. After all devices have
released their SWEN, the combined SWEN goes high and the devices are ready to turn on their respective FETs
at the same time.
Inrush: During inrush, because the DVDT pins are tied together to a single DVDT capacitor all the devices turn
on the output with the same slew rate (SR). Choose the common DVDT capacitor (CDVDT) as per 方程式 41 and
方程式42.
I
mA
V
ms
INRUSH
SR
=
(41)
(42)
C
µF
OUT
42000 × k
C
pF =
dVdt
V
SR
ms
Refer to TPS25990x for more details.
The internal balancing circuits ensure that the load current is shared among all devices during start-up. This
action prevents a situation where some devices turn on faster than others and experience more thermal stress
as compared to other devices. This can potentially result in premature or partial shutdown of the parallel chain,
or even SOA damage to the devices. The current balancing scheme ensures the inrush capability of the chain
scales according to the number of devices connected in parallel, thereby ensuring successful start-up with larger
output capacitances or higher loading during start-up. All devices hold their respective PG signals low during
start-up. After the output ramps up fully and reaches steady-state, each device releases its own PG pulldown.
Because the DVDT pins of all devices are tied together, the internal gate high detection of all devices is
synchronized. There can be some threshold or timing mismatches between devices leading to PG assertion in a
staggered manner. However, because the PG pins of all devices are tied together, the combined PG signal
becomes high only after all devices have released their PG pulldown. This signals the downstream load that it is
okay to draw power.
Steady-state: During steady-state, all devices share current nearly equally using the active current sharing
mechanism which actively regulates the respective device RDSON to evenly distribute current across all the
devices in the parallel chain. After PG is asserted, de-assertion is controlled only by TPS25990x and based on
VOUT_PGTH register setting.
备注
The TPS25990x current can be slightly higher as compared to TPS25985x higher owing to its higher
on-resistance. This current is fine as long as the steady-state current does not exceed the
recommended maximum continuous rating for the device.
Overcurrent during steady-state: The circuit-breaker threshold for the parallel chain is based on the total
system current rather than the current flowing through individual devices. This is done by connecting the IMON
pins of all the devices together to a single resistor (RIMON) to GND. Similarly, the IREF pins of all devices are tied
together and TPS25990x uses internal programmable DAC (VIREF) to generate a common reference for the
overcurrent protection block in all the devices. This action helps minimize the contribution of VIREF variation to
the overall mismatch in overcurrent threshold between devices.
In this case, choose the RIMON as per the following Equation 16:
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V
IREF
× I
R
=
(43)
IMON
G
IMON
OCP(TOTAL)
The start-up current limit and active current sharing threshold for each device is set independently using the ILIM
pin. The RILIM value for the TPS25990x should be selected based on the following equation:
1.1 × 4N − 1 × R
IMON
R
=
(44)
ILIM 25990
9
The RILIM value for each TPS25985x must be selected based on the following equation:
1.1 × 4N − 1 × R
IMON
R
=
(45)
ILIM 25985
12
Where N = number of devices in parallel chain (1 × TPS25990x + (N - 1) × TPS25985x)
Other variations: The IREF pin can be driven from an external precision voltage reference.
During an overcurrent event, the overcurrent detection of all the devices is triggered simultaneously. This in turn
triggers the overcurrent blanking timer (OC_TIMER) in TPS25990x. The TPS25990x uses the OC_TIMER expiry
event as a trigger to pull the SWEN low for all the devices, thereby initiating the circuit-breaker action for the
whole chain at the same time. This mechanism ensures that mismatches in the current distribution, overcurrent
thresholds and OC_TIMER intervals among the devices do not degrade the accuracy of the circuit-breaker
threshold of the complete parallel chain or the overcurrent blanking interval. However, the secondary devices
also maintain their backup overcurrent timer and can trigger the shutdown of the whole chain if the primary
device fails to do so within a certain interval.
Severe overcurrent (short-circuit): If there is a severe fault at the output (for example, output shorted to
ground with a low impedance path), the current builds up rapidly to a high value and triggers the fast-trip
response in each device. The devices use two thresholds for fast-trip protection – a user-adjustable threshold
(ISFT = 2 × IOCP in steady-state or ISFT = 1.5 × ILIM during inrush) as well as a fixed threshold (IFFT only during
steady-state). After the fast-trip, the TPS25990x relies on the SC_RETRY config bit in the DEVICE_CONFIG
register to determine if the whole chain enters a latched fault or performs a fast recovery by restarting in current
limit manner. If it enters a latched fault, the devices remain latched off till the device is power cycled or re-
enabled, or auto-retry with a delay based on the RETRY_CONFIG register setting.
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9.4 Digital Telemetry Using External Microcontroller
Systems which need digital telemetry, control, and configurability along with high current eFuse functionality can
use one or more TPS25985x devices in conjunction with a general purpose microcontroller as shown in 图9-16.
MCU
ADC
SCL
SDA
SCL
SDA
DAC
ADC
GPIO
ADC
SMBA#
ADC
VL
VL
GPIO
GPIO
GPIO
GND
TPS25985
IN
OUT
IREF
TEMP
PG
VOUT
VIN
VDD
VLSTBY
EN/UVLO
MODE
FLT
IMON
SWEN
ITIMER GND
ILIM
DVDT
TPS25985
IN
OUT
IREF
TEMP
IMON
PG
VDD
EN/UVLO
ITIMER
SWEN
FLT
DVDT
MODE GND
ILIM
图9-16. Digital Telemetry Using External Microcontroller
The basic circuit connections for the eFuses are the same for the single or multiple parallel device configuration.
In addition, the following connections can be made to the microcontroller:
• IMON is connected to an ADC input of microcontroller for monitoring the load current.
• EN/UVLO is connected to GPIO of microcontroller to allow digital ON and OFF control of the eFuse.
• PG and FLT pins are connected to GPIO of microcontroller to allow digital monitoring of the eFuse status.
• VIN and VOUT rails are connected to the ADC inputs of microcontroller (through resistor ladder to
appropriately step down the voltage) for monitoring the bus voltages.
• TEMP is connected to an ADC input of microcontroller for monitoring the eFuse die temperature.
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• IREF can be optionally connected to a DAC output of the microcontroller to dynamically change the reference
voltage for overcurrent and short-circuit current thresholds.
9.5 What to Do and What Not to Do
TPS25985x needs the SWEN pin to be pulled up to a supply rail which is powered up before the device is
enabled. Failing this, the device is not able to turn on the output. The SWEN pullup supply must not be derived
from the output of the eFuse. Use one of the following options to derive the pullup supply rail for SWEN.
1. Use an existing standby rail in the system, which is derived from the main power input and comes up before
the eFuse is turned on.
2. Use an LDO (3.3 V or 5 V) powered from the main power input.
LDO
100 k
VSWEN
eFuse Input
Supply
IN
OUT
GND
SWEN
0.1 µF
0.1 µF
图9-17. LDO Used as Pullup Supply for SWEN
3. Use a Zener regular powered from the main power input.
100 k
100 k
eFuse Input
Supply
SWEN
4.7 V Zener
Diode
0.1 µF
图9-18. Zener Regulator Used as Pullup Supply for SWEN
4. Use the ITIMER pin of the primary eFuse. Ensure the ITIMER pin does not have excess loading which can
interfere with the normal overcurrent blanking timer functionality.
ITIMER of
primary eFuse
100 k
SWEN
图9-19. ITIMER Pin Used as Pullup Supply for SWEN
The ground connections for the various components around the TPS25985 eFuses must be wired directly to
each other and the GND pins of respective eFuses. This must be followed by connecting them to the system
ground at one point. For more details, refer to TPS25985EVM eFuse Evaluation Board. Do not connect the
various component grounds through the high current system ground line.
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10 Power Supply Recommendations
The TPS25985x devices are designed for a supply voltage in the range of 4.5 V to 16 V on the IN and VDD pins.
TI recommends using a minimum capacitance of 0.1 μF on the IN pin of each device in parallel chain to avoid
coupling of high slew rates during hot plug events. TI also recommends using an R-C filter from the input supply
to the VDD pin on each device in parallel chain to filter out supply noise and to hold up the controller supply
during severe faults such as short-circuit.
10.1 Transient Protection
In the case of a short-circuit or circuit-breaker event when the device interrupts current flow, the input inductance
generates a positive voltage spike on the input, and the output inductance generates a negative voltage spike on
the output. The peak amplitude of voltage spikes (transients) is dependent on the value of inductance in series
to the input or output of the device. Such transients can exceed the absolute maximum ratings of the device if
steps are not taken to address the issue. Typical methods for addressing transients include:
• Minimize lead length and inductance into and out of the device.
• Use a large PCB GND plane.
• Connect a Schottky diode from the OUT pin ground to absorb negative spikes.
• Connect a low ESR capacitor of 2.2 μF or higher at the OUT pin very close to the device.
• Connect a ceramic capacitor CIN = 0.1 μF or higher at the IN pin very close to the device to dampen the rise
time of input transients. The capacitor voltage rating must be at least twice the input supply voltage to be able
to withstand the positive voltage excursion during inductive ringing.
The approximate value of input capacitance can be estimated with 方程式46.
L
IN
V
= V + I ×
LOAD
(46)
SPIKE Absolute
IN
C
IN
where
VIN is the nominal supply voltage.
ILOAD is the load current.
LIN equals the effective inductance seen looking into the source.
CIN is the capacitance present at the input.
• Some applications can require the addition of a Transient Voltage Suppressor (TVS) to prevent transients
from exceeding the absolute maximum ratings of the device. In some cases, even if the maximum amplitude
of the transients is below the absolute maximum rating of the device, a TVS can help to absorb the excessive
energy dump and prevent it from creating very fast transient voltages on the input supply pin of the IC, which
can couple to the internal control circuits and cause unexpected behavior.
The circuit implementation with optional protection components is shown in 图10-1.
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TPS25985x
IN
VOUT
VIN
OUT
IREF
VDD
IMON
TEMP
EN
EN/UVLO
MODE
VLSTBY
PG
SWEN
ITIMER GND
ILIM
FLT
DVDT
图10-1. Circuit Implementation with Optional Protection Components
10.2 Output Short-Circuit Measurements
It is difficult to obtain repeatable and similar short-circuit testing results. The following contribute to variation in
results:
• Source bypassing
• Input leads
• Circuit layout
• Component selection
• Output shorting method
• Relative location of the short
• Instrumentation
The actual short exhibits a certain degree of randomness because it microscopically bounces and arcs. Ensure
that configuration and methods are used to obtain realistic results. Do not expect to see waveforms exactly like
those in this data sheet because every setup is different.
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11 Layout
11.1 Layout Guidelines
• For all applications, TI recommends a ceramic decoupling capacitor of 0.1 μF or greater between the IN
terminal and GND terminal.
• For all applications, TI recommends a ceramic decoupling capacitor of 2.2 μF or greater between the OUT
terminal and GND terminal.
• The optimal placement of the decoupling capacitor is closest to the IN and GND terminals of the device. Care
must be taken to minimize the loop area formed by the bypass-capacitor connection, the IN terminal, and the
GND terminal of the IC. See Figure below for a PCB layout example.
• High current-carrying power-path connections must be as short as possible and must be sized to carry at
least twice the full-load current.
• The GND terminal must be tied to the PCB ground plane at the terminal of the IC. The PCB ground must be a
copper plane or island on the board.
• The IN and OUT pins are used for Heat Dissipation. Connect to as much copper area as possible with
thermal vias.
• Locate the following support components close to their connection pins:
– RILIM
– RIMON
– CIMON
– RIREF
– CIREF
– CdVdT
– CITIMER
– CIN
– COUT
– CVDD
– Resistors for the EN/UVLO pin
• Connect the other end of the component to the GND pin of the device with shortest trace length. The trace
routing for the CIN, COUT, CVDD, RIREF, CIREF, RILIM, RIMON, CIMON, CITIMER and CdVdt components to the
device must be as short as possible to reduce parasitic effects on the current limit, overcurrent blanking
interval and soft-start timing. These traces must not have any coupling to switching signals on the board.
• Because the IMON, ILIM, IREF and ITIMER pins directly control the overcurrent protection behavior of the
device, the PCB routing of these nodes must be kept away from any noisy (switching) signals.
• TI recommends to keep the parasitic loading on SWEN pin to a minimum to avoid synchronization issues.
• Protection devices such as TVS, snubbers, capacitors, or diodes must be placed physically close to the
device they are intended to protect. These protection devices must be routed with short traces to reduce
inductance. For example, TI recommends a protection Schottky diode to address negative transients due to
switching of inductive loads, and it must be physically close to the OUT pins.
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11.2 Layout Example
Top Power layer
Top Power GND layer
Top Signal GND layer
Bottom Power layer
+
-
VOUT
VIN
图11-1. TPS25985x Two Parallel Devices Layout Example
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12 Device and Documentation Support
TI offers an extensive line of development tools. Tools and software to evaluate the performance of the device,
generate code, and develop solutions are listed below.
12.1 Documentation Support
12.1.1 Related Documentation
For related documentation see the following:
• Texas Instruments, TPS25985EVM eFuse Evaluation Board
• Texas Instruments, TPS25985x Design Calculator
• Texas Instruments, TPS25990 Datasheet
12.2 接收文档更新通知
要接收文档更新通知，请导航至 ti.com 上的器件产品文件夹。点击订阅更新 进行注册，即可每周接收产品信息更
改摘要。有关更改的详细信息，请查看任何已修订文档中包含的修订历史记录。
12.3 支持资源
TI E2E™ 支持论坛是工程师的重要参考资料，可直接从专家获得快速、经过验证的解答和设计帮助。搜索现有解
答或提出自己的问题可获得所需的快速设计帮助。
链接的内容由各个贡献者“按原样”提供。这些内容并不构成 TI 技术规范，并且不一定反映 TI 的观点；请参阅
TI 的《使用条款》。
12.4 Trademarks
TI E2E™ is a trademark of Texas Instruments.
Intel® is a registered trademark of Intel.
PMBus® is a registered trademark of SMIF.
所有商标均为其各自所有者的财产。
12.5 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled
with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may
be more susceptible to damage because very small parametric changes could cause the device not to meet its published
specifications.
12.6 术语表
TI 术语表
本术语表列出并解释了术语、首字母缩略词和定义。
13 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
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PACKAGE OPTION ADDENDUM
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13-Jul-2023
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
TPS259850RQPR
ACTIVE
VQFN-HR
RQP
26
3000 RoHS & Green
SN
Level-2-260C-1 YEAR
-40 to 125
TP9850
Z2
Samples
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
PACKAGE OUTLINE
VQFN-HR - 1 mm max height
PLASTIC QUAD FLATPACK-NO LEAD
A
RQP0026A
5.1
4.9
B
PIN 1 IDENTIFICATION
4.6
4.4
C
1.0
0.8
SEATING PLANE
0.08 C
0.05
0.00
4X TYP (0.15)
0.3
0.2
8X
9
2.55
2.35
4X TYP (0.35)
TYP (0.1)
8X
10
13
0.25
0.15
0.1
4X 1.7
14
14X
4X 1.2
4X 0.8
4X 0.4
C A B
0.05
C
0.0 PKG
0.45
0.35
4X
0.85
0.65
4X
0.1
C A B
22
1
0.05
C
26
23
PIN1 ID
0.4
0.3
4X
(OPTIONAL)
0.6
0.4
0.1
0.05
C A B
18X
C
4225325/B 10/2020
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
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EXAMPLE BOARD LAYOUT
VQFN-HR - 1 mm max height
PLASTIC QUAD FLATPACK-NO LEAD
RQP0026A
26
23
(1.975)
1
22
4X (1.7)
4X (1.2)
(1.125)
8X
(2.65)
4X (0.8)
4X (0.4)
(0.0)
PKG
14X (0.2)
(R0.05) TYP
(1.125)
9
14
(1.975)
4X (0.4)
13
10
4X (0.95)
18X (0.7)
4X (0.35)
8X (0.25)
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE: 15X
0.05 MIN
ALL AROUND
METAL
0.05 MAX
ALL AROUND
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
SOLDER MASK
OPENING
EXPOSED METAL
EXPOSED METAL
NON- SOLDER MASK
DEFINED
SOLDER MASK
DEFINED
(PREFERRED)
SOLDER MASK DETAILS
NOT TO SCALE
4225325/B 10/2020
NOTES: (continued)
3. For more information, see Texas Instruments literature number SLUA271 (www.ti.com/lit/slua271).
4. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
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EXAMPLE STENCIL DESIGN
VQFN-HR - 1 mm max height
PLASTIC QUAD FLATPACK-NO LEAD
RQP0026A
26
23
METAL TYP
(1.975)
1
22
4X (1.675)
4X (1.2)
4X (0.8)
4X (0.4)
(0.0)
PKG
16X
(1.225)
14X (0.2)
2X (0.4)
(0.2)
(R0.05) TYP
2X (1.8)
(1.975)
9
14
4X (0.35)
13
10
4X (0.95)
4X (0.35)
18X (0.7)
16X (0.21)
SOLDER PASTE EXAMPLE
BASED ON 0.1mm THICK STENCIL
PIN 1,9,14 & 22: 96%; PIN 10-13 & 23-26: 77%
SCALE: 15X
4225325/B 10/2020
NOTES: (continued)
5.
Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
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