TPS25200 [TI]
关断时可实现反向电流阻断的 2.5V 至 6.5V、60mΩ、0.085A 至 2.9A 电子保险丝;
| 型号： | TPS25200 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 关断时可实现反向电流阻断的 2.5V 至 6.5V、60mΩ、0.085A 至 2.9A 电子保险丝 电子 |
| 文件： | 总32页 (文件大小：4838K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
TPS25200
ZHCSC71E –MARCH 2014 –REVISED JUNE 2021
具有高精度可调电流限值和过压钳位的TPS25200 5V 电子保险丝
1 特性
3 说明
• 2.5V 至6.5V 工作电压
• 输入可耐受高达20V 的电压
• 7.6V 输入过压关断
TPS25200 是一款具有高精度电流限值和过压钳位的
5V 电子保险丝。此器件可在过压和过流事件发生期间
为负载和电源提供可靠保护。
• 5.25V 至5.55V 固定过压钳位
• 0.6μs 过压锁定响应
• 3.5μs 短路响应
• 集成式60mΩ高侧MOSFET
• 高达2.5A 的持续负载电流
• 2.9 A 电流下的限流精度为±6%
• 禁用时反向电流阻断
• 内置软启动
• 与TPS2553 引脚到引脚兼容
• 通过UL 2367 认证
TPS25200 是一款用于保护负载的智能开关，可耐受
20V 的输入电压。如果在输入端施加了错误电压，输
出端可将电压限制在 5.4V，以保护负载。如果输入端
的电压超过 7.6V，此器件将断开负载，以防止对器件
和/或负载造成损坏。
TPS25200 具有 60mΩ 的内部电源开关，可用于在多
种异常情况下保护电源、器件和负载。此器件提供高达
2.5A 的持续负载电流。通过一个连接到地的电阻，可
对限流值在85mA 到2.9A 范围内进行设置。当发生过
载时，输出电流被限制在由 RILIM 设定的电流值上如果
出现持续过载，TPS25200 将最终进入热关断模式，从
而避免自身发生损坏。
– 文件编号169910
– RILIM ≥33kΩ（最大电流为3.12A）
2 应用
器件信息
封装
• USB 电源开关
订货编号
封装尺寸
• USB 从设备
TPS25200
WSON (6)
2.00mm × 2.00mm
• 手机/智能电话
• 3G、4G 无线数据卡
• 固态硬盘(SSD)
• 3V 或5V 适配器供电设备
V
IO
VOUT (V)
300kΩ
Over Voltage Clamp
(OVC)
Fault signal
TPS25200DRV
V
IN
V
OUT
5.4 V
6
5
4
1
2
3
IN
OUT
ILIM
C
IN
300 kΩ
GND
EN
Turn Off
MOSFET
C
OUT
FAULT
PowerPAD
R
ILIM
VIN (V)
UVLO(2.35V)
OVLO(7.6V)
20 V
V
OUT 与VIN 之间的关系
简化版原理图
本文档旨在为方便起见，提供有关TI 产品中文版本的信息，以确认产品的概要。有关适用的官方英文版本的最新信息，请访问
www.ti.com，其内容始终优先。TI 不保证翻译的准确性和有效性。在实际设计之前，请务必参考最新版本的英文版本。
English Data Sheet: SLVSCJ0
TPS25200
ZHCSC71E –MARCH 2014 –REVISED JUNE 2021
www.ti.com.cn
Table of Contents
8.4 Device Functional Modes..........................................13
9 Application and Implementation..................................14
9.1 Application Information............................................. 14
9.2 Typical Application.................................................... 14
10 Power Supply Recommendations..............................21
11 Layout...........................................................................21
11.1 Layout Guidelines................................................... 21
11.2 Layout Example...................................................... 21
12 Device and Documentation Support..........................22
12.1 Documentation Support.......................................... 22
12.2 接收文档更新通知................................................... 22
12.3 支持资源..................................................................22
12.4 Trademarks.............................................................22
12.5 Electrostatic Discharge Caution..............................22
12.6 术语表..................................................................... 22
13 Mechanical, Packaging, and Orderable
1 特性................................................................................... 1
2 应用................................................................................... 1
3 说明................................................................................... 1
4 Revision History.............................................................. 2
5 Pin Configuration and Functions...................................3
6 Specifications.................................................................. 4
6.1 Absolute Maximum Ratings........................................ 4
6.2 ESD Ratings............................................................... 4
6.3 Recommended Operating Conditions.........................4
6.4 Thermal Information....................................................4
6.5 Electrical Characteristics.............................................5
6.6 Timing Requirements..................................................6
6.7 Typical Characteristics................................................7
7 Parameter Measurement Information............................9
8 Detailed Description......................................................10
8.1 Overview...................................................................10
8.2 Functional Block Diagram......................................... 11
8.3 Feature Description...................................................11
Information.................................................................... 22
4 Revision History
注：以前版本的页码可能与当前版本的页码不同
Changes from Revision D (February 2020) to Revision E (June 2021)
Page
• 更新了整个文档中的表格、图和交叉参考的编号格式.........................................................................................1
• Corrected package type......................................................................................................................................3
• Corrected package type......................................................................................................................................4
Changes from Revision C (September 2017) to Revision D (February 2020)
Page
• Updated Figure 9-5 ..........................................................................................................................................15
Changes from Revision B (February 2017) to Revision C (September 2017)
Page
• 在器件信息表中将封装从SON 更改为WSON.................................................................................................. 1
Changes from Revision A (March 2014) to Revision B (February 2017)
Page
• 向特性部分添加了UL 认证状态.........................................................................................................................1
Changes from Revision * (March 2014) to Revision A (March 2014)
Page
• Changed the toff TYP value From: 0.24 ms To: 0.22 ms ....................................................................................6
• Added condition: VEN = VIN = 0 V to Figure 6-3 .................................................................................................7
• Changed Figure 6-8 graph title From: Discharge Resistance To: VIN ................................................................7
• Changed 方程式4 From = 2470 mA to = 2479 mA..........................................................................................16
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5 Pin Configuration and Functions
IN
6
5
4
1
2
3
OUT
ILIM
Power
PAD
GND
EN
FAULT
图5-1. DRV Package 6-Pin WSON Top View
表5-1. Pin Functions
PIN
I/O
DESCRIPTION
NAME
NO.
Logic-level control input. When is driven high, the power switch is enabled. When it is driven low,
turn power switch off. This pin cannot be left floating and it must be limited below the absolute
maximum rating if tied to VIN
EN
4
I
Active-low open-drain output, asserted during overcurrent, overvoltage or overtemperature.
Connect a pull up resistor to the logic I/O voltage
FAULT
3
O
GND
ILIM
5
2
Ground connection; connect externally to PowerPAD
—
O
External resistor used to set current-limit threshold; Recommended 33 kΩ≤RILIM ≤1100 kΩ
Input voltage; connect a 0.1-μF or greater ceramic capacitor from IN to GND as close to the IC as
possible
IN
6
1
I
OUT
O
—
Protected power switch VOUT
Internally connected to GND; used to heat-sink the part to the circuit board traces. Connect
PowerPAD to GND terminal externally
PowerPAD™
PAD
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6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range, voltage are referenced to GND (unless otherwise noted) (1)
MIN
MAX
20
UNIT
Voltage on IN
V
V
V
–0.3
–0.3
–7
Voltage on OUT, EN, ILIM, FAULT
Voltage from IN to OUT
7
20
IO
Continuous output current
Continuous FAULT output sink current
Continuous ILIM output source current
Operating junction temperature
Storage temperature
Thermally Limited
25
150
mA
µA
TJ
Internally limited
Tstg
150
°C
–65
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under
Recommended Operating Conditions. Exposure to absolutemaximum- rated conditions for extended periods may affect device
reliability.
6.2 ESD Ratings
VALUE
UNIT
Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1)
±2000
V(ESD)
Electrostatic discharge
V
Charged-device model (CDM), per JEDEC specification JESD22-
C101(2)
±500
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
6.3 Recommended Operating Conditions
over operating free-air temperature range, voltage are referenced to GND (unless otherwise noted)
MIN
MAX
6.5
UNIT
V
VIN
Input voltage of IN
2.5
0
VEN
IFAULT
IOUT
RILIM
TJ
Enable terminal voltage
6.5
V
Continuous FAULT sink current
Continuous output current of OUT
Current-limit set resistors
Operating junction temperature
0
10
mA
A
2.5
33
1100
125
kΩ
°C
–40
6.4 Thermal Information
TPS25200
THERMAL METRIC(1)
DRV (WSON)
6 PINS
66.5
UNIT
Junction-to-ambient thermal resistance
Junction-to-case (top) thermal resistance
Junction-to-board thermal resistance
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
θJA
83.4
θJCtop
θJB
36.1
Junction-to-top characterization parameter
Junction-to-board characterization parameter
Junction-to-case (bottom) thermal resistance
1.6
ψJT
36.5
ψJB
7.6
θJCbot
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
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6.5 Electrical Characteristics
Conditions are –40°C ≤TJ ≤+125°C and 2.5 V ≤VIN ≤6.5 V. VEN = VIN, RILIM = 33 kΩ. Positive current into terminals.
Typical value is at 25°C. All voltages are with respect to GND (unless otherwise noted).
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
POWER SWITCH
TJ = 25°C
60
60
70
90
–40°C ≤TJ ≤+85°C
2.5 V ≤VIN ≤5 V,
IOUT = 2.5 A
IN–OUT resistance(1)
mΩ
rDS(on)
–40°C ≤TJ ≤
+125°C
60
99
ENABLE INPUT EN
EN terminal turnon threshold
Input rising
Input falling
1.9
V
V
EN terminal turnoff threshold
Hyesteresis
0.6
330(2)
480
mV
µA
IEN
Leakage current
VEN = 0 V or 5.5 V
2
–2
DISCHARGE
RDCHG OUT discharge resistance
CURRENT LIMIT
VOUT = 5 V, VEN = 0 V
625
Ω
2773
2270
1620
1110
590
2952
2423
1740
1206
647
3127
2570
1860
1300
710
RILIM = 33 kΩ
RILIM = 40.2 kΩ
RILIM = 56 kΩ
RILIM = 80.6 kΩ
RILIM = 150 kΩ
RILIM = 1100 kΩ
IOS
mA
Current - limit, See 图7-4
40
83
130
OVERVOLTAGE LOCKOUT, IN
V(OVLO) IN rising OVLO threshold voltage
Hysteresis
IN rising
6.8
7.6
8.45
5.55
V
70(2)
mV
VOLTAGE CLAMP, OUT
V(OVC)
OUT clamp voltage threshold
5.25
5.4
V
CL = 1 µF, RL = 100 Ω, VIN = 6.5 V
SUPPLY CURRENT
VEN = 0 V, VIN = 5 V
0.8
1000
143
5
1700
200
IIN(off)
Supply current, low-level output
µA
VEN = 0 or 5 V, VIN = 20 V
RILIM = 33 kΩ
RILIM = 150 kΩ
VIN = 5 V,
No load on OUT
IIN(on)
Supply current, high-level output
Reverse leakage current
µA
µA
134
190
VOUT = 6.5V, VIN = VEN = 0 V, TJ = 25°C,
measure IOUT
IREV
3
5
UNDERVOLTAGE LOCKOUT, IN
VUVLO IN rising UVLO threshold voltage
Hysteresis
FAULT FLAG
VOL Output low voltage, FAULT
Off-state leakage
IN rising
2.35
30(2)
2.45
V
mV
IFAULT = 1 mA
VFAULT = 6.5 V
50
180
1
mV
µA
THERMAL SHUTDOWN
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Conditions are –40°C ≤TJ ≤+125°C and 2.5 V ≤VIN ≤6.5 V. VEN = VIN, RILIM = 33 kΩ. Positive current into terminals.
Typical value is at 25°C. All voltages are with respect to GND (unless otherwise noted).
PARAMETER
TEST CONDITIONS
MIN
155
135
TYP
MAX
UNIT
Thermal shutdown threshold, OTSD2
Thermal shutdown threshold only in
current-limit, OTSD1
°C
Hysteresis
20(2)
(1) Pulse-testing techniques maintain junction temperature close to ambient temperature. Thermal effects must be taken into account
separately.
(2) These parameters are provided for reference only and does not constitute part of TI's published device specifications for purposes of
TI's product warranty.
6.6 Timing Requirements
Conditions are –40°C ≤TJ ≤+125°C and 2.5 V ≤VIN ≤6.5 V. VEN = VIN, RILIM = 33 kΩ. Positive current are into
terminals. Typical value is at 25°C. All voltages are with respect to GND (unless otherwise noted)
TEST CONDITIONS
MIN
TYP
MAX UNIT
POWER SWITCH
tr
tf
OUT voltage rise time
OUT voltage fall time
2.05
0.18
3.2
ms
0.2
CL = 1 µF, RL = 100 Ω, (see 图7-2)
ENABLE INPUT EN
ton Turnon time
toff Turnoff time
CURRENT LIMIT
5.12
0.22
7.3
0.3
ms
ms
2.5 V ≤VIN ≤5 V, CL = 1 µF, RL = 100 Ω,
(see 图7-2)
t(IOS)
Short-circuit response time
3.5(1)
0.6(1)
µs
µs
VIN = 5 V (see 图7-4)
OVERVOLTAGE LOCKOUT, IN
VIN 5 V to 10 V with 1-V/µs ramp up rate,
VOUT with 100-Ωload
t(OVLO_off_delay) Turnoff delay for OVLO
FAULT FLAG
FAULT assertion or de-assertion due to
overcurrent condition
FAULT deglitch
5
8
12
ms
(1) This parameter is provided for reference only and does not constitute part of TI's published device specifications for purposes of TI's
product warranty.
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6.7 Typical Characteristics
200
180
160
140
120
100
80
3.0
2.5
2.0
1.5
1.0
0.5
0.0
VIN = 2.5
V = 5 V
IN
60
40
V=2.5V
IN
20
V
= 5 V
IN
0
œ50
0
50
100
150
œ50
0
50
100
150
Junction Temperature (°C)
Junction Temperature (°C)
C001
C002
RILIM = 33 KΩ
RILIM = 33 KΩ
图6-1. IIN(on) vs Junction Temperature
图6-2. IIN(off) vs Junction Temperature
6
5
4
3
2
1
0
100
90
80
70
60
50
40
30
20
10
0
VIN = 5 V
VOUT = 6.5 V
0
50
100
150
0
50
100
150
œ50
œ50
Junction Temperature (°C)
Junction Temperature (°C)
C003
C004
图6-4. rDS(ON) vs Junction Temperature
VEN = VIN = 0 V
图6-3. IREV vs Junction Temperature
7.8
7.8
7.7
7.7
7.6
7.6
7.5
7.5
7.4
5.50
5.45
5.40
5.35
5.30
0
50
100
150
0
50
100
150
C005
œ50
œ50
Junction Temperature (°C)
Junction Temperature (°C)
RL = 100 Ω
C005
VEN = VIN = 0 V
图6-5. V(OVLO) vs Junction Temperature
CL = 1 µF
VIN = 6.5 V
图6-6. VO(VC) vs Junction Temperature
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6.7 Typical Characteristics (continued)
3500
3000
2500
2000
540
530
520
510
500
490
480
470
460
RILIM = 33 K
RILIM = 40.2 K
RILIM = 150 K
R
= 80.6 K
ILIM
1500
1000
500
0
œ50
0
50
100
150
2
3
4
5
6
7
Junction Temperature (°C)
VIN
C007
C001
图6-7. IOS vs Junction Temperature
图6-8. Discharge Resistance vs VIN
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7 Parameter Measurement Information
OUT
90%
tr
tf
VOUT
RL
10%
CL
图7-2. Power-On and Off Timing
图7-1. Output Rise-Fall Test Load
IOS
50%
ton
50%
VEN
IOUT
toff
90%
VOUT
tIOS
10%
图7-4. Output Short Circuit Parameters
图7-3. Enable Timing, Active High Enable
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8 Detailed Description
8.1 Overview
The TPS25200 is an intelligent low voltage switch or e-Fuse with robust overcurrent and overvoltage protection
which are suitable for a variety of applications.
The TPS25200 current limited power switch uses N-channel MOSFETs in applications requiring up to 2.5 A of
continuous load current. The device allows the user to program the current-limit threshold between 85 mA and
2.9 A (typical) via an external resistor. The device enters constant-current mode when the load exceeds the
current-limit threshold.
The TPS25200 Input can withstand 20-V DC voltage, but clamps VOUT to a precision regulated 5.4 V and shuts
down in the event VIN exceeds 7.6 V. The device also integrates overcurrent and short circuit protection. The
precision overcurrent limit helps to minimize over design of the input power supply while the fast response short
circuit protection isolates the load when a short circuit is detected.
The additional features include:
• Enable the device can be put into a sleep mode for portable applications.
• Overtemperature protection to safely shutdown in the event of an overcurrent event or a slight overvoltage
event where the VOUT clamp is engaged over and extended period of time.
• Deglitched fault reporting to filter the Fault signal to ensure the TPS25200 do not provide false fault alerts.
• Output discharge pull-down to help ensue a load is in fact off and not in some undefined operational state.
• Reverse blocking when disabled to prevent back-drive from an active load inadvertently causing
undetermined behavior in the application.
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8.2 Functional Block Diagram
Current
Sense
CS
IN
OUT
UVLO
Charge
Pump
Current
Limit
Driver
OVLO
See Note A
EN
GND
Zener Diode
OTSD
Thermal
Sense
OVC
8-ms
Deglitch
FAULT
ILIM
A. 6.4-V Typical Clamp Voltage
8.3 Feature Description
8.3.1 Enable
This logic enable input controls the power switch and device supply current. A logic high input on EN enables the
driver, control circuits, and power switch. The enable input is compatible with both TTL and CMOS logic levels.
EN can be tied to VIN with a pull up resistor, and is protected with an integrated zener diode. Use a sufficiently
large (300-kΩ) pull up resistor to ensure that the V(EN) is limited below the absolute maximum rating.
8.3.2 Thermal Sense
The TPS25200 self protects by using two independent thermal sensing circuits that monitor the operating
temperature of the power switch and disable operation if the temperature exceeds recommended operating
conditions. The TPS25200 device operates in constant-current mode during an overcurrent condition, which
increases the voltage drop across power switch. The power dissipation in the package is proportional to the
voltage drop across the power switch, which increases the junction temperature during an overcurrent condition.
The first thermal sensor (OTSD1) turns off the power switch when the die temperature exceeds 135°C
(minimum) and the part is in current limit. Hysteresis is built into the thermal sensor, and the switch turns on after
the device has cooled approximately 20°C.
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The TPS25200 also has a second ambient thermal sensor (OTSD2). The ambient thermal sensor turns off the
power switch when the die temperature exceeds 155°C (minimum) regardless of whether the power switch is in
current limit and turns on the power switch after the device has cooled approximately 20°C. The TPS25200
continues to cycle off and on until the fault is removed.
8.3.3 Overcurrent Protection
The TPS25200 thermally protects itself by thermal cycling during an extended overcurrent condition. The device
turns off when the junction temperature exceeds 135°C (typical) while in current limit. The device remains off
until the junction temperature cools 20°C (typical) and then restarts. The TPS25200 cycles on/off until the
overload is removed (see Figure 9-13 and 图9-16).
The TPS25200 responds to an overcurrent condition by limiting their output current to the IOS levels shown in 图
7-4. When an overcurrent condition is detected, the device maintains a constant output current and the output
voltage is reduced accordingly. During an over current event, two possible overload conditions can occur.
The first condition is when a short circuit or partial short circuit is present when the device is powered-up or
enabled. The output voltage is held near zero potential with respect to ground and the TPS25200 ramps the
output current to IOS. The TPS25200 devices limit the current to IOS until the overload condition is removed or
the device begins to thermal cycle.
The second condition is when a short circuit, partial short circuit, or transient overload occurs while the device is
enabled and powered on. The device responds to the overcurrent condition within time tIOS (see 图 7-4). The
current-sense amplifier is overdriven during this time and momentarily disables the internal current-limit
MOSFET. The current-sense amplifier recovers and limits the output current to IOS. Similar to the previous case,
the TPS25200 limits the current to IOS until the overload condition is removed or the device begins to thermal
cycle.
8.3.4 FAULT Response
The FAULT open-drain output is asserted (active low) during an overcurrent, overtemperature or overvoltage
condition. The TPS25200 asserts the FAULT signal until the fault condition is removed and the device resumes
normal operation. The TPS25200 is designed to eliminate false FAULT reporting by using an internal delay
"deglitch" circuit for overcurrent (8-ms typical) conditions without the need for external circuitry. This ensures that
FAULT is not accidentally asserted due to normal operation such as starting into a heavy capacitive load. The
deglitch circuitry delays entering and leaving current-limit induced fault conditions.
The FAULT signal is not deglitched when the MOSFET is disabled due to an overtemperature condition but is
deglitched after the device has cooled and begins to turnon. This unidirectional deglitch prevents FAULT
oscillation during an overtemperature event.
The FAULT signal is not deglitched when the MOSFET is disabled into OVLO or out of OVLO. The TPS25200
does not assert the FAULT during output voltage clamp mode.
Connect FAULT with a pull up resistor to a low voltage I/O rail.
8.3.5 Output Discharge
A 480-Ω(typical) output discharge dissipates stored charge and leakage current on OUT when the TPS25200 is
in UVLO, disabled or OVLO. The pull down capability decreases as VIN decreases (Figure 6-8).
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8.4 Device Functional Modes
The TPS25200 VIN can withstand up to 20 V. Within 0 V to 20 V range, it can be divided to four modes as shown
in 图8-1.
VOUT (V)
Over Voltage Clamp
(OVC)
5.4 V
Turn Off
MOSFET
VIN (V)
UVLO(2.35V)
OVLO(7.6V)
20 V
图8-1. Output vs Input Voltage
8.4.1 Undervoltage Lockout (UVLO)
The undervoltage lockout (UVLO) circuit disables the power switch until the input voltage reaches the UVLO
turnon threshold. Built-in hysteresis prevents unwanted on and off cycling due to input voltage droop during
turnon.
8.4.2 Overcurrent Protection (OCP)
When 2.35 V < VIN < 5.4 V, the TPS25200 is a traditional power switch, providing overcurrent protection.
8.4.3 Overvoltage Clamp (OVC)
When 5.4 V < VIN < 7.6 V, the overvoltage clamp (OVC) circuit clamps the output voltage to 5.4 V. Within this VIN
range, the overcurrent protection remains active.
8.4.4 Overvoltage Lockout (OVLO)
When VIN exceeds 7.6 V, the overvoltage lockout (OVLO) circuit turns off the protected power switch.
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9 Application and Implementation
备注
以下应用部分中的信息不属于TI 器件规格的范围，TI 不担保其准确性和完整性。TI 的客 户应负责确定
器件是否适用于其应用。客户应验证并测试其设计，以确保系统功能。
9.1 Application Information
The TPS25200 is a 5-V eFuse with precision current limit and over-voltage clamp. When a slave device such as
a mobile data-card device is hot plugged into a USB port as shown in 图 9-1, an input transient voltage could
damage the slave device due to the cable inductance. Placing the TPS25200 at the input of mobile device as
over-voltage and overcurrent protector can safeguard these slave devices. Input transients also occur when the
current through the cable parasitic inductance changes abruptly. This can occur when the TPS25200 turns off
the internal MOSFET in response to an overvoltage or overcurrent event. The TPS25200 can withstand the
transient without a bypass bulk capacitor, or other external overvoltage protection components at input side. The
TPS25200 also can be used at host side as a traditional power switch pin-to-pin compatible with the TPS2553.
Mobile Device
Rcable
Lcable
OUT
IN
TPS25200
GND
5 V
USB Port
Load
图9-1. Hot Plug Into 5V USB port with Parasitic Cable Resistance and Inductance
9.2 Typical Application
VIO
300 kΩ
Fault signal
TPS25200DRV
0.1µF
VOUT
VIN
6
5
4
1
IN
OUT
ILIM
300 kΩ
GND
EN
2
3
FAULT
22mF
PowerPAD
R
ILIM
图9-2. Overvoltage and Overcurrent Protector—Typical Application Schematic
Use the IOS in the Electrical Characteristics table or IOS in 方程式1 to select the RILIM
.
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9.2.1 Design Requirements
For this design example, use the desgin parameters in 表9-1 as the input parameters.
表9-1. Design Parameters
DESIGN PARAMETERS
Normal input operation voltage
Output transient voltage
Minimum current limit
EXAMPLE VALUE
5 V
6.5 V
2.1 A
2.9 A
Maximum currnt limit
9.2.2 Detailed Design Procedure
9.2.2.1 Step by Step Design Produce
To begin the design process a few parameters must be decided upon. The designer needs to know the following:
• Normal Input Operation Voltage
• Output transient voltage
• Minimum Current Limit
• Maximum Current Limit
9.2.2.2 Input and Output Capacitance
Input and output capacitance improves the performance of the device; the actual capacitance must be optimized
for the particular application. For all applications, a 0.1-µF or greater ceramic bypass capacitor between IN and
GND is recommended as close to the device as possible for local noise decoupling.
When VIN ramp up exceed 7.6 V, VOUT follows VIN until the TPS25200 turns off the internal MOSFET after
t(OVLO_off_delay). Since t(OVLO_off_delay) largely depends on the VIN ramp rate, VOUT sees some peak voltage.
Increasing the output capacitance can lower the output peak voltage as shown in 图9-3.
10
8
6
4
2
0
0
10
20
30
40
50
Output Cap (ꢀF)
C008
图9-3. VOUT Peak Voltage vs COUT (VIN Step From 5 V to 15 V with 1-V/µs Ramp Up Rate)
9.2.2.3 Programming the Current-Limit Threshold
The overcurrent threshold is user programmable via an external resistor. The TPS25200 uses an internal
regulation loop to provide a regulated voltage on the ILIM terminal. The current-limit threshold is proportional to
the current sourced out of ILIM. The recommended 1% resistor range for RILIM is 33 kΩ ≤ RILIM ≤ 1100 kΩ to
ensure stability of the internal regulation loop. Many applications require that the minimum current limit is above
a certain current level or that the maximum current limit is below a certain current level, so it is important to
consider the tolerance of the overcurrent threshold when selecting a value for RILIM. The current-limit threshold
equations (IOS) in 方程式 1 approximate the resulting overcurrent threshold for a given external resistor value
RILIM. See the Electrical Characteristics table for specific current limit settings. The traces routing the RILIM
resistor to the TPS25200 must be as short as possible to reduce parasitic effects on the current-limit accuracy.
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RILIM can be selected to provide a current-limit threshold that occurs 1) above a minimum load current or 2)
below a maximum load current.
To design above a minimum current-limit threshold, find the intersection of RILIM and the maximum desired load
current on the IOS(min) curve and choose a value of RILIM below this value. Programming the current limit above a
minimum threshold is important to ensure start up into full load or heavy capacitive loads. The resulting
maximum current-limit threshold is the intersection of the selected value of RILIM and the IOS(max) curve.
To design below a maximum current-limit threshold, find the intersection of RILIM and the maximum desired load
current on the IOS(max) curve and choose a value of RILIM above this value. Programming the current limit below
a maximum threshold is important to avoid current limiting upstream power supplies causing the input voltage
bus to droop. The resulting minimum current-limit threshold is the intersection of the selected value of RILIM and
the IOS(min) curve. See Figure 9-4 and Figure 9-5 .
96754V
IOSmax (mA) =
IOSnom(mA) =
IOSmin(mA) =
+ 30
0.985
RILIM
kW
98322V
1.003kW
RILIM
97399
1.015
- 30
RILIM
kW
(1)
Where 33 kΩ ≤RILIM ≤1100 kΩ.
750
700
650
600
550
500
450
400
350
300
250
200
150
100
50
3500
3000
2500
IOS (max)
IOS (typ)
IOS (min)
IOS(typ)
2000
1500
1000
500
0
IOS(max)
IOS(min)
0
30 40 50 60 70 80 90 100 110 120 130 140 150
100 200 300 400 500 600 700 800 900 1000 1100
Current Limit Resistor (kW
Current Limit Resistor (kW)
C001
C002
33 kΩ ≤RILIM ≤150 kΩ
150 kΩ ≤RILIM ≤1100 kΩ
图9-4. Current-Limit Threshold vs RILIM
I
图9-5. Current-Limit Threshold vs RILIM II
9.2.2.4 Design Above a Minimum Current Limit
Some applications require that current limiting cannot occur below a certain threshold. For this example, assume
that 2.1 A must be delivered to the load so that the minimum desired current-limit threshold is 2100 mA. Use the
IOS equations (方程式1) and Figure 9-4 to select RILIM as shown in 方程式2.
IOSmin(mA) = 2100 mA
97399V
RILIM1.015kW
IOSmin(mA) =
- 30
1
1
1.015
æ
ö
÷
÷
ø
97399
97399
1.015
æ
ö
RILIM(kW) = ç
=
= 43.22 kW
ç
÷
ç
è
IOS(min) + 30
2100 + 30
è
ø
(2)
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Select the closest 1% resistor less than the calculated value: RILIM = 42.2 kΩ. This sets the minimum current-
limit threshold at 2130 mA as shown in 方程式3.
97399V
RILIM1.015kW
97399
42.2 x 1.01 1.015
IOSmin(mA) =
- 30 =
- 30 = 2130mA
(
)
(3)
Use the IOS equations (方程式 1), Figure 9-4, and the previously calculated value for RILIM to calculate the
maximum resulting current-limit threshold as shown in 方程式4.
96754
IOSmax (mA) =
IOSmax (mA) =
+ 30
0.985
RILIM
96754
(42.2´0.99)0.985
+ 30 = 2479 mA
(4)
The resulting current-limit threshold minimum is 2130 mA and maximum is 2479 mA with RILIM = 42.2kΩ ± 1%.
9.2.2.5 Design Below a Maximum Current Limit
Some applications require that current limiting must occur below a certain threshold. For this example, assume
that 2.9 A must be delivered to the load so that the minimum desired current-limit threshold is 2900 mA. Use the
IOS equations (方程式1) and Figure 9-5 to select RILIM as shown in 方程式5.
IOSmax (mA) = 2900mA
96754
RILIM0.985kW
IOSmax (mA) =
+ 30
1
1
0.985
æ
ö
÷
÷
ø
96754
96754
0.985
æ
ö
R
(kW) = ç
=
= 35.57 kW
ç
÷
ILIM
ç
IOS(max) - 30
2900 - 30
è
ø
è
(5)
Select the closest 1% resistor greater than the calculated value: RILIM = 36 kΩ. This sets the maximum current-
limit threshold at 2894 mA as shown in 方程式6.
96754V
RILIM0.985kW
96754
IOSmax (mA) =
+ 30 =
+ 30 = 2894mA
0.985
36 x 0.99
(
)
(6)
Use the IOS equations, Figure 9-5, and the previously calculated value for RILIM to calculate the minimum
resulting current-limit threshold as shown in 方程式7.
97399
IOSmin(mA) =
IOSmin(mA) =
- 30
1.015
RILIM
97399
36´1.01 1.015
- 30 = 2508mA
(
)
(7)
The resulting minimum current-limit threshold minimum is 2592 mA and maximum is 2894 mA with RILIM = 36 kΩ
± 1%.
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9.2.2.6 Power Dissipation and Junction Temperature
The low on-resistance of the internal N-channel MOSFET allows small surface-mount packages to pass large
currents. It is good design practice to estimate power dissipation and junction temperature. The below analysis
gives an approximation for calculating junction temperature based on the power dissipation in the package.
However, it is important to note that thermal analysis is strongly dependent on additional system level factors.
Such factors include air flow, board layout, copper thickness and surface area, and proximity to other devices
dissipating power. Good thermal design practice must include all system level factors in addition to individual
component analysis. Begin by determining the rDS(on) of the N-channel MOSFET relative to the input voltage and
operating temperature. As an initial estimate, use the highest operating ambient temperature of interest and read
rDS(on) from the typical characteristics graph. When VIN is lower than V(OVC), the TPS2500 is an traditional power
switch. Using this value, the power dissipation can be calculated by usnig 方程式8.
2
PD = rDS(on) × IOUT
(8)
When VIN exceed V(OVC), but lower than V(OVLO), the TPS25200 clamp output to fixed V(OVC), the power
dissipation can be calculated by using 方程式9.
PD = (VIN –V(OVC)) × IOUT
(9)
where
• PD = Total power dissipation (W)
• rDS(on) = Power switch on-resistance (Ω)
• V(OVC) = Overvoltage clamp voltage (V)
• IOUT = Maximum current-limit threshold (A)
This step calculates the total power dissipation of the N-channel MOSFET.
Finally, calculate the junction temperature using 方程式10.
TJ = PD × θJA + TA
(10)
where
• TA = Ambient temperature (°C)
• θJA = Thermal resistance (°C /W)
• PD = Total power dissipation (W)
Compare the calculated junction temperature with the initial estimate. If they are not within a few degrees, repeat
the calculation using the "refined" rDS(on) from the previous calculation as the new estimate. Two or three
iterations are generally sufficient to achieve the desired result. The final junction temperature is highly dependent
on thermal resistance θJA, and thermal resistance is highly dependent on the individual package and board
layout.
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9.2.3 Application Curves
9
8
0.32
0.28
0.24
0.2
12
11
10
9
VOUT
V
IN
7
6
8
5
7
0.16
0.12
0.08
0.04
6
4
5
3
4
2
V
V
IN
3
OUT
1
2
/FAULT
0
0
1
I
OUT
0
œ1
-0.04
œ80
œ40
0
40
80
120
160
œ1
œ2.0 œ1.5 œ1.0 œ0.5
0.0
0.5
1.0
1.5
2.0
C009
Time (ms)
Time (s)
C001
图9-7. VIN Step 5 V to 8 V with 4.7 μF // 100 Ω
图9-6. VOUT vs VIN (0 V to 10 V)
12
11
10
9
11
VIN
V
V
IN
10
9
VOUT
OUT
/FAULT
8
8
7
7
6
6
5
5
4
4
3
3
2
2
1
1
0
0
œ1
-1
-2
0
2
4
6
8
-6
-4
-2
0
2
4
Time (s)
Time (us)
C010
C012
图9-8. Pulse Overvoltage with 100 Ω
图9-9. 5-V to 10-V OVLO Response Time
5
5
4
3
2
1
0
-1
5
5
4
3
2
1
0
-1
EN
V
IN
4
3
4
V
OUT
3
2
2
1
1
EN
0
0
V
IN
V
OUT
œ1
œ1
œ4
1
6
11
16
-1.2
-0.2
0.8
1.8
2.8
Time (ms)
Time (ms)
C013
C013
图9-10. Turnon Delay and Rise Time 150 µF || 2.5 Ω 图9-11. Turnoff Delay and Fall Time 150 µF || 2.5 Ω
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6
5
4
3
2
6
5
4
3
2
1
0
-1
6
5
6
V
I
OUT
OUT
/FAULT
5
4
3
2
1
0
-1
4
3
2
1
1
EN
0
0
/FAULT
I
OUT
œ1
œ1
œ2
2
6
10
Time (ms)
14
18
œ20
0
20
40
60
80
Time (ms)
C015
C016
图9-12. Enable into Output Short
图9-13. 2.5 Ω to Output Short Transient Response
6
5
6
5
4
3
2
1
0
-1
6
6
5
4
3
2
1
0
-1
V
I
V
I
OUT
OUT
/FAULT
OUT
OUT
/FAULT
5
4
4
3
3
2
2
1
1
0
0
œ1
œ1
œ70
œ50
œ30
œ10
10
30
œ20
0
20
40
60
80
Time (ms)
Time (ms)
C016
C016
图9-14. Output Short to 2.5-Ω Load Recovery
图9-15. No Load to Output Short Transient
Response
Response
6
5
6
5
4
3
2
1
0
-1
6
5
6
VOUT
V
IN
V
V
OUT
I
OUT
/FAULT
5
4
4
4
3
3
3
2
2
2
1
1
1
0
0
0
œ1
œ1
-1
-0.8
0
0.8
1.6
2.4
3.2
œ70
œ50
œ30
œ10
10
30
Time (ms)
Time (ms)
C020
C016
图9-17. Hot-Short With 50 mΩ
图9-16. Output Short to No Load Recovery
Response
6
5
60
V
VOUT
I
IOUT
50
40
30
20
10
0
4
3
2
1
0
œ1
œ2
-10
-20
œ4
œ2
œ0
2
4
6
Time (ms)
C021
图9-18. 50-mΩ Hot-Short Response Time
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10 Power Supply Recommendations
The TPS25200 is designed for 2.7 V < VIN < 5 V (typical) voltage rails. While there is a VOUT clamp, it is not
intended to be used to regulate VOUT at approximately 5.4 V with 6 V < VIN < 7 V. This is a protection feature
only.
11 Layout
11.1 Layout Guidelines
• For all applications, a 0.1-µF or greater ceramic bypass capacitor between IN and GND is recommended as
close to the device as possible for local noise decoupling.
• For output capacitance, refer to 图9-3, low ESR ceramic cap is recommended.
• The traces routing the RILIM resistor to the device must be as short as possible to reduce parasitic effects on
the current limit accuracy.
• The PowerPAD must be directly connected to PCB ground plane using wide and short copper trace.
11.2 Layout Example
VIA to Power Ground Plane
FAULT
4
5
6
3
EN
ILIM
2
1
IN
High Frequency
Bypass Capacitor
OUT
Power Ground
VI/O
图11-1. TPS25200 Board Layout
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12 Device and Documentation Support
12.1 Documentation Support
12.1.1 Related Documentation
For related documentation, see the following:
TPS25200 EVM User's Guide
12.2 接收文档更新通知
要接收文档更新通知，请导航至 ti.com 上的器件产品文件夹。点击订阅更新 进行注册，即可每周接收产品信息更
改摘要。有关更改的详细信息，请查看任何已修订文档中包含的修订历史记录。
12.3 支持资源
TI E2E™ 支持论坛是工程师的重要参考资料，可直接从专家获得快速、经过验证的解答和设计帮助。搜索现有解
答或提出自己的问题可获得所需的快速设计帮助。
链接的内容由各个贡献者“按原样”提供。这些内容并不构成 TI 技术规范，并且不一定反映 TI 的观点；请参阅
TI 的《使用条款》。
12.4 Trademarks
PowerPAD™ and TI E2E™ are trademarks of Texas Instruments.
所有商标均为其各自所有者的财产。
12.5 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled
with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may
be more susceptible to damage because very small parametric changes could cause the device not to meet its published
specifications.
12.6 术语表
TI 术语表
本术语表列出并解释了术语、首字母缩略词和定义。
13 Mechanical, Packaging, and Orderable Information
The following pages include mechanical packaging and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
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重要声明和免责声明
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有瑕疵且不做出任何明示或暗示的担保，包括但不限于对适销性、某特定用途方面的适用性或不侵犯任何第三方知识产权的暗示担保。
这些资源可供使用TI 产品进行设计的熟练开发人员使用。您将自行承担以下全部责任：(1) 针对您的应用选择合适的TI 产品，(2) 设计、验
证并测试您的应用，(3) 确保您的应用满足相应标准以及任何其他安全、安保或其他要求。这些资源如有变更，恕不另行通知。TI 授权您仅可
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提供这些资源并不会扩展或以其他方式更改TI 针对TI 产品发布的适用的担保或担保免责声明。重要声明
邮寄地址：Texas Instruments, Post Office Box 655303, Dallas, Texas 75265
Copyright © 2021，德州仪器(TI) 公司
PACKAGE OPTION ADDENDUM
www.ti.com
17-Jun-2021
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
TPS25200DRVR
TPS25200DRVT
ACTIVE
ACTIVE
WSON
WSON
DRV
DRV
6
6
3000 RoHS & Green
250 RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
-40 to 125
-40 to 125
SKB
SKB
NIPDAU
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
17-Jun-2021
OTHER QUALIFIED VERSIONS OF TPS25200 :
Automotive : TPS25200-Q1
•
NOTE: Qualified Version Definitions:
Automotive - Q100 devices qualified for high-reliability automotive applications targeting zero defects
•
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
1-Jul-2023
TAPE AND REEL INFORMATION
REEL DIMENSIONS
TAPE DIMENSIONS
K0
P1
W
B0
Reel
Diameter
Cavity
A0
A0 Dimension designed to accommodate the component width
B0 Dimension designed to accommodate the component length
K0 Dimension designed to accommodate the component thickness
Overall width of the carrier tape
W
P1 Pitch between successive cavity centers
Reel Width (W1)
QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE
Sprocket Holes
Q1 Q2
Q3 Q4
Q1 Q2
Q3 Q4
User Direction of Feed
Pocket Quadrants
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
TPS25200DRVR
TPS25200DRVT
TPS25200DRVT
WSON
WSON
WSON
DRV
DRV
DRV
6
6
6
3000
250
180.0
180.0
178.0
8.4
8.4
8.4
2.3
2.3
2.3
2.3
1.15
1.15
1.0
4.0
4.0
4.0
8.0
8.0
8.0
Q2
Q2
Q2
250
2.25
2.25
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
1-Jul-2023
TAPE AND REEL BOX DIMENSIONS
Width (mm)
H
W
L
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SPQ
Length (mm) Width (mm) Height (mm)
TPS25200DRVR
TPS25200DRVT
TPS25200DRVT
WSON
WSON
WSON
DRV
DRV
DRV
6
6
6
3000
250
210.0
210.0
205.0
185.0
185.0
200.0
35.0
35.0
33.0
250
Pack Materials-Page 2
GENERIC PACKAGE VIEW
DRV 6
WSON - 0.8 mm max height
PLASTIC SMALL OUTLINE - NO LEAD
Images above are just a representation of the package family, actual package may vary.
Refer to the product data sheet for package details.
4206925/F
PACKAGE OUTLINE
DRV0006A
WSON - 0.8 mm max height
SCALE 5.500
PLASTIC SMALL OUTLINE - NO LEAD
2.1
1.9
A
B
PIN 1 INDEX AREA
2.1
1.9
0.8
0.7
C
SEATING PLANE
0.08 C
(0.2) TYP
0.05
0.00
1
0.1
EXPOSED
THERMAL PAD
3
4
6
2X
7
1.3
1.6 0.1
1
4X 0.65
0.35
0.25
6X
PIN 1 ID
(OPTIONAL)
0.3
0.2
6X
0.1
C A
C
B
0.05
4222173/B 04/2018
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. The package thermal pad must be soldered to the printed circuit board for thermal and mechanical performance.
www.ti.com
EXAMPLE BOARD LAYOUT
DRV0006A
WSON - 0.8 mm max height
PLASTIC SMALL OUTLINE - NO LEAD
6X (0.45)
6X (0.3)
(1)
1
7
6
SYMM
(1.6)
(1.1)
4X (0.65)
4
3
SYMM
(1.95)
(R0.05) TYP
(
0.2) VIA
TYP
LAND PATTERN EXAMPLE
SCALE:25X
0.07 MIN
ALL AROUND
0.07 MAX
ALL AROUND
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
METAL
SOLDER MASK
OPENING
NON SOLDER MASK
DEFINED
SOLDER MASK
DEFINED
(PREFERRED)
SOLDER MASK DETAILS
4222173/B 04/2018
NOTES: (continued)
4. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature
number SLUA271 (www.ti.com/lit/slua271).
5. Vias are optional depending on application, refer to device data sheet. If some or all are implemented, recommended via locations are shown.
www.ti.com
EXAMPLE STENCIL DESIGN
DRV0006A
WSON - 0.8 mm max height
PLASTIC SMALL OUTLINE - NO LEAD
SYMM
7
6X (0.45)
METAL
1
6
6X (0.3)
(0.45)
SYMM
4X (0.65)
(0.7)
4
3
(R0.05) TYP
(1)
(1.95)
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
EXPOSED PAD #7
88% PRINTED SOLDER COVERAGE BY AREA UNDER PACKAGE
SCALE:30X
4222173/B 04/2018
NOTES: (continued)
6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
www.ti.com
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