TPS2521XX [TI]
TPS2521xx, 2.7 - 5.7 V, 4 A, 31-mΩ True Reverse Current Blocking eFuse with Input Reverse Polarity Protection;型号: | TPS2521XX |
厂家: | TEXAS INSTRUMENTS |
描述: | TPS2521xx, 2.7 - 5.7 V, 4 A, 31-mΩ True Reverse Current Blocking eFuse with Input Reverse Polarity Protection |
文件: | 总47页 (文件大小:4299K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
TPS2521
SLVSFX8 – MARCH 2021
TPS2521xx, 2.7 - 5.7 V, 4 A, 31-mΩ True Reverse Current Blocking eFuse with Input
Reverse Polarity Protection
blocked at all times, making the device well suited for
systems which need load side energy hold up storage
1 Features
•
•
•
•
Wide operating input voltage range: 2.7 V to 5.7 V
28-V absolute maximum
Withstands negative voltages up to – 15 V
Integrated back-to-back FETs with low On-
Resistance: RON = 31 mΩ (typ)
Ideal diode operation with true reverse current
blocking
Fast overvoltage clamp (OVC) with pin-selectable
threshold (3.8 V, 5.7 V) with 5-μs (typ) response
time
Overcurrent protection with load current monitor
output (ILM)
– Active current limit response
– Adjustable threshold (ILIM) 0.5 A - 4.44 A
in case input power supply fails.
Output current limit level can be set with a single
external resistor. It is also possible to get an accurate
sense of the output load current by measuring the
voltage drop across the current limit resistor.
•
•
Applications
with
particular
inrush
current
requirements can set the output slew rate with a
single external capacitor. Loads are protected from
input overvoltage conditions by clamping the output to
a safe fixed maximum voltage (pin selectable).
•
The devices are available in a 2-mm × 2-mm,
10-pin HotRod QFN package for improved thermal
performance and reduced system footprint.
•
±10% accuracy for ILIM > 1 A
The devices are characterized for operation over a
junction temperature range of –40°C to +125°C.
– Adjustable transient blanking timer (ITIMER) to
allow peak currents up to 2 x ILIM
– Output load current monitor accuracy: ±6%
(IOUT ≥ 1 A)
Device Information
PART NUMBER
PACKAGE(1)
BODY SIZE (NOM)
•
•
Fast-trip response for short-circuit protection
– 500-ns (typ) response time
– Adjustable (2 x ILIM) and fixed thresholds
Active High Enable input with adjustable
undervoltage lockout threshold (UVLO)
Adjustable output slew rate control (dVdt)
Overtemperature protection
Power Good indication (PG) with adjustable
threshold (PGTH)
IEC 62368 CB certification (pending)
UL 2367 recognition (pending)
TPS2521xxRPW
QFN (10)
2 mm × 2 mm
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
VOUT
•
•
•
VIN = 2.7 to 5.7 V
IN
OUT
COUT
PGTH
EN/UVLO
OVCSEL
VLOGIC
TPS25210x
•
•
•
PG
ITIMER dVdt
GND
ILM
Small footprint: QFN 2 mm × 2 mm, 0.45-mm pitch
2 Applications
RILM
CITIMER
CDVDT
•
•
•
•
•
Adapter input protection
Enterprise storage - RAID/HBA/SAN/eSSD
USB PD port protection
Server/PC motherboard/add-on cards
Monitors/docks
Simplified Schematic
3 Description
The TPS2521x family of eFuses is a highly integrated
circuit protection and power management solution
in a small package. The devices provide multiple
protection modes using very few external components
and are
a
robust defense against overloads,
short-circuits, voltage surges, reverse polarity and
excessive inrush current. With integrated back-to-
back FETs, reverse current flow from output to input is
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
TPS2521
SLVSFX8 – MARCH 2021
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Table of Contents
1 Features............................................................................1
2 Applications.....................................................................1
3 Description.......................................................................1
4 Revision History.............................................................. 2
5 Device Comparison Table...............................................3
6 Pin Configuration and Functions...................................4
7 Specifications.................................................................. 5
7.1 Absolute Maximum Ratings ....................................... 5
7.2 ESD Ratings .............................................................. 5
7.3 Recommended Operating Conditions ........................6
7.4 Thermal Information ...................................................6
7.5 Electrical Characteristics ............................................7
7.6 Timing Requirements .................................................9
7.7 Switching Characteristics ...........................................9
7.8 Typical Characteristics..............................................10
8 Detailed Description......................................................16
8.1 Overview...................................................................16
8.2 Functional Block Diagram.........................................17
8.3 Feature Description...................................................18
8.4 Device Functional Modes..........................................27
9 Application and Implementation..................................28
9.1 Application Information............................................. 28
9.2 Single Device, Self-Controlled.................................. 28
9.3 Typical Application.................................................... 29
10 Power Supply Recommendations..............................35
10.1 Transient Protection................................................35
10.2 Output Short-Circuit Measurements....................... 36
11 Layout...........................................................................37
11.1 Layout Guidelines................................................... 37
11.2 Layout Example...................................................... 38
12 Device and Documentation Support..........................39
12.1 Documentation Support.......................................... 39
12.2 Receiving Notification of Documentation Updates..39
12.3 Support Resources................................................. 39
12.4 Trademarks.............................................................39
12.5 Electrostatic Discharge Caution..............................39
12.6 Glossary..................................................................39
13 Mechanical, Packaging, and Orderable
Information.................................................................... 40
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
DATE
REVISION
NOTES
March 2021
*
Initial Release
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5 Device Comparison Table
Part Number
Overvoltage Response
Overcurrent Response
Response to Fault
TPS25210A
Auto-Retry
Latch-Off
Pin Selectable OVC (3.8 V/5.7 V)
Active Current Limit
TPS25210L
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6 Pin Configuration and Functions
IN
OUT
1
EN/UVLO
10
ITIMER
ILM
OVCSEL
9
8
2
3
5
6
PG
GND
DVDT
PGTH
7
4
Figure 6-1. TPS2521x RPW Package 10-Pin QFN Top View
Table 6-1. Pin Functions
PIN
TYPE
DESCRIPTION
NAME
NO.
Active High Enable for the device. A Resistor Divider on this pin from input supply to GND
can be used to adjust the Undervoltage Lockout threshold. Do not leave floating. Refer to
Section 8.3.2 for details.
Analog
Input
EN/UVLO
1
Analog
Input
OVCSEL
PG
2
3
4
Overvoltage Clamp Threshold Select Pin. Refer to Section 8.3.3 for details.
Power Good indication. This is an Open Drain signal which is asserted High when the
internal powerpath is fully turned ON and PGTH input exceeds a certain threshold. Refer
to Section 8.3.9 for more details.
Digital
Output
Analog
Input
PGTH
Power Good Threshold. Refer to Section 8.3.9 for more details.
IN
5
6
Power Power Input.
Power Power Output.
OUT
Analog A capacitor from this pin to GND sets the output turn on slew rate. Leave this pin floating
Output for the fastest turn on slew rate. Refer to Section 8.3.4.1 for details.
DVDT
GND
7
8
Ground This is the ground reference for all internal circuits and must be connected to system GND.
This is a dual function pin used to limit and monitor the output current. An external resistor
Analog from this pin to GND sets the output current limit threshold during start-up as well as
Output steady state. The pin voltage can also be used as analog output load current monitor
signal. Do not leave floating. Refer to Section 8.3.4.2 for more details.
ILM
9
A capacitor from this pin to GND sets the overcurrent blanking interval during which the
Analog output current can temporarily exceed set current limit (but lower than fast-trip threshold)
Output before the device overcurrent response takes action. Leave this pin open for fastest
response to overcurrent events. Refer to Section 8.3.4.2 for more details.
ITIMER
10
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7 Specifications
7.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)(1)
Parameter
Pin
MIN
MAX UNIT
Maximum Input Voltage Range, -40 ℃ ≤ TJ ≤ 125 ℃
max(-15, VOUT - 21)
28
28
V
V
VIN
IN
Maximum Input Voltage Range, -10 ℃ ≤ TJ ≤ 125 ℃
Maximum Output Voltage Range, -40 ℃ ≤ TJ ≤ 125 ℃
Maximum Output Voltage Range, -10 ℃ ≤ TJ ≤ 125 ℃
Minimum Output Voltage Pulse (< 1 µs)
max(-15, VOUT - 22)
–0.3
–0.3
–0.8
–0.3
min (28, VIN + 21)
min (28, VIN + 22)
VOUT
OUT
OUT
VOUT,PLS
VEN/UVLO Maximum Enable Pin Voltage Range (2)
EN/UVLO
OVCSEL
dVdt
6.5
V
V
VOVCSEL
VdVdT
VITIMER
VPGTH
VPG
Maximum OVCSEL Pin Voltage Range
Maximum dVdT Pin Voltage Range
Maximum ITIMER Pin Voltage Range
Maximum PGTH Pin Voltage Range (2)
Maximum PG Pin Voltage Range
Maximum ILM Pin Voltage Range
Maximum Continuous Switch Current
Junction temperature
Internally Limited
Internally Limited
Internally Limited
–0.3
V
ITIMER
PGTH
PG
V
6.5
6.5
V
–0.3
V
VILM
ILM
Internally Limited
Internally Limited
Internally Limited
V
IMAX
IN to OUT
A
TJ
°C
°C
°C
TLEAD
TSTG
Maximum Lead Temperature
300
150
Storage temperature
–65
(1) Operation outside the Absolute Maximum Ratings may cause permanent device damage. Absolute Maximum Ratings do not imply
functional operation of the device at these or any other conditions beyond those listed under Recommended Operating Conditions.
If used outside the Recommended Operating Conditions but within the Absolute Maximum Ratings, the device may not be fully
functional, and this may affect device reliability, functionality, performance, and shorten the device lifetime.
(2) If this pin has a pull-up up to VIN, it is recommended to use a resistance of 350 kΩ or higher to limit the current under conditions where
IN can be exposed to reverse polarity.
7.2 ESD Ratings
VALUE
UNIT
Human body model (HBM), per ANSI/ESDA/JEDEC JS-001,
all pins(1)
±2000
V(ESD)
Electrostatic discharge
V
Charged device model (CDM), per JEDEC specification
JESD22-C101, all pins(2)
±500
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process precautions.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
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MAX UNIT
SLVSFX8 – MARCH 2021
7.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
Parameter
Pin
MIN
VIN
Input Voltage Range
Output Voltage Range
IN
2.7
5.7 (1)
min (23, VIN + 20)
5 (2)
V
V
VOUT
OUT
VEN/UVLO Enable Pin Voltage Range
EN/UVLO
dVdt
V
VdVdT
VPGTH
VPG
dVdT Capacitor Voltage Rating
PGTH Pin Voltage Range
PG Pin Voltage Range
VIN + 5 V
V
PGTH
PG
5 (3)
5 (3)
V
V
VITIMER
RILM
IMAX
ITIMER Pin Capacitor Voltage Rating
ILM Pin Resistance
ITIMER
ILM
4
V
750
6650
4
Ω
A
Continuous Switch Current, TJ ≤ 125 ℃
Junction temperature
IN to OUT
TJ
–40
125
°C
(1) The input operating voltage should be limited to the selected Output Voltage Clamp threshold as listed in the Electrical Characteristics
section
(2) For supply voltages below 5V, it is okay to pull up the EN pin to IN directly. For supply voltages greater than 5V or systems which can
be exposed to reverse polarity on input supply, it is recommended to use a pull-up resistor with a minimum value of 350 kΩ.
(3) For systems which can be exposed to reverse polarity on input supply, if this pin is referred to input supply, it is recommended to use a
pull-up resistor with a minimum value of 350 kΩ to limit the current through the pin.
7.4 Thermal Information
TPS2521xx
THERMAL METRIC (1)
RPW (QFN)
10 PINS
41.7 (2)
74.5 (3)
1
UNIT
°C/W
°C/W
°C/W
°C/W
°C/W
RθJA
ΨJT
ΨJB
Junction-to-ambient thermal resistance
Junction-to-top characterization parameter
Junction-to-board characterization parameter
20 (2)
27.6 (3)
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
(2) Based on simulations conducted with the device mounted on a custom 4-layer PCB (2s2p) with 8 thermal vias under device
(3) Based on simulations conducted with the device mounted on a JEDEC 4-layer PCB (2s2p) with no thermal vias under device
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7.5 Electrical Characteristics
(Test conditions unless otherwise noted) –40°C ≤ TJ ≤ 125°C, VIN = 5 V, OUT = Open, VEN/UVLO = 2 V, OVCSEL = Open, RILM
= 750 Ω , dVdT = Open, ITIMER = Open, PGTH = Open, PG = Open. All voltages referenced to GND.
Test
Parameter
Description
MIN
TYP
MAX
UNITS
INPUT SUPPLY (IN)
VUVP(R)
VUVP(F)
IQ(ON)
IN Supply UVP Rising Threshold
IN Supply UVP Falling Threshold
2.44
2.35
2.53
2.42
411
426
186
67
2.64
2.55
593
620
V
V
IN Supply Quiescent Current
µA
µA
µA
µA
µA
µA
IQ(ON)
IN Supply Current during OVC
IQ(ON)
IN Supply Quiescent Current during RCB, VOUT = VIN + 1 V
IQ(OFF)
ISD
IN Supply OFF State Current (VSD(F) < VEN < VUVLO(F)
IN Supply Shutdown Current (VEN < VSD(F)
IN Supply Leakage Current (VIN = -14 V, VOUT = 0 V)
)
130
)
1.62
-3.7
28.7
IINLKG(IRPP)
ON RESISTANCE (IN - OUT)
VIN = 5 V, IOUT = 3 A, TJ = 25 ℃
2.7 ≤ VIN ≤ 5.7 V, –40 ℃ ≤ TJ ≤ 125 ℃
ENABLE/UNDERVOLTAGE LOCKOUT (EN/UVLO)
31
mΩ
mΩ
RON
50.2
VUVLO(R)
VUVLO(F)
VSD(F)
EN/UVLO Rising Threshold
EN/UVLO Falling Threshold
1.183
1.076
0.45
1.2
1.1
1.223
1.116
V
V
EN/UVLO Falling Threshold for lowest shutdown current
EN/UVLO Leakage Current
0.73
V
IENLKG
-0.1
0.1
µA
OUTPUT VOLTAGE CLAMP (OUT)
Overvoltage Clamp Threshold, OVCSEL = Shorted to GND
3.65
5.25
3.88
5.74
4.1
6.2
V
V
VOVC
Overvoltage Clamp Threshold, OVCSEL = Open
Output Voltage During Clamping, OVCSEL = Shorted to
GND, IOUT = 10 mA
3.2
5
3.82
5.58
4.2
6.1
V
V
VCLAMP
Output Voltage During Clamping, OVCSEL = Open, IOUT
10 mA
=
OVERCURRENT PROTECTION (OUT)
Current Limit Threshold, RILM = 6.65 kΩ
0.425
0.85
1.8
0.5
1.0
0.575
1.15
2.2
A
A
A
A
Current Limit Threshold, RILM = 3.32 kΩ
Current Limit Threshold, RILM = 1.65 kΩ
Current Limit Threshold, RILM = 750 Ω
ILIM
2.02
4.44
3.96
4.84
Circuit Breaker Threshold, ILM Pin Open (Single point
failure)
0.1
1.1
A
A
IFLT
Circuit Breaker Threshold, ILM Pin Short to GND (Single
point failure)
2.1
ISCGain
IFT
Scalable Fast Trip Threshold (ISC) : ILIM Ratio
Fixed Fast-trip Current Threshold
201
22
%
A
V
V
VFB
VOUT threshold to exit Current Limit Foldback
ITIMER pin internal pull-up voltage
1.9
VINT
2.3
1.2
2.52
2.72
2.5
OVERCURRENT FAULT TIMER (ITIMER)
IITIMER
ITIMER pin internal discharge current, IOUT > ILIM
1.81
15
µA
kΩ
V
RITIMER
ΔVITIMER
ITIMER pin internal pull-up resistance
ITIMER discharge voltage
1.28
1.51
1.74
OUTPUT LOAD CURRENT MONITOR (ILM)
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7.5 Electrical Characteristics (continued)
(Test conditions unless otherwise noted) –40°C ≤ TJ ≤ 125°C, VIN = 5 V, OUT = Open, VEN/UVLO = 2 V, OVCSEL = Open, RILM
= 750 Ω , dVdT = Open, ITIMER = Open, PGTH = Open, PG = Open. All voltages referenced to GND.
Test
Parameter
Description
MIN
165
165
TYP
182
182
MAX
UNITS
Analog Load Current Monitor Gain (IMON : IOUT), IOUT = 0.5 A
to 1 A, IOUT < ILIM
200
µA/A
GIMON
Analog Load Current Monitor Gain (IMON : IOUT), IOUT = 1 A to
4 A, IOUT < ILIM
200
µA/A
REVERSE CURRENT BLOCKING (IN - OUT)
VFWD
VIN - VOUT Forward regulation voltage, IOUT = 10 mA
5
17.4
mV
mV
VIN - VOUT threshold for fast BFET turn off (enter reverse
current blocking)
VREVTH
-36.5
-29.1
-22.3
125
VIN - VOUT threshold for fast BFET turn on (exit reverse
current blocking)
VFWDTH
83
102.2
270
mV
µA
µA
OUT Leakage Current during ON state with RCB, VOUT
VIN + 1 V
=
IOUTLKG(RCB)
IREVLKG(OFF)
Reverse Leakage Current during unpowered condition, VOUT
= 12 V, VIN = 0 V
4.8
POWER GOOD INDICATION (PG)
PG pin voltage while de-asserted, VIN < VUVP(F), VEN
<
<
0.67
0.78
1
1
V
V
VSD(F), Weak pull-up (IPG = 26 µA)
VPGD
PG pin voltage while de-asserted, VIN < VUVP(F), VEN
VSD(F), Strong pull-up (IPG = 242 µA)
PG pin voltage while de-asserted, VIN > VUVP(R)
PG Pin Leakage Current, PG asserted
0
V
IPGLKG
0.9
3
µA
POWERGOOD THRESHOLD (PGTH)
VPGTH(R)
VPGTH(F)
IPGTHLKG
PGTH Rising Threshold
PGTH Falling Threshold
PGTH Leakage Current
1.183
1.076
-0.1
1.2
1.223
1.116
0.3
V
V
1.09
µA
OVERTEMPERATURE PROTECTION (OTP)
TSD
Thermal Shutdown Rising Threshold, TJ↑
154
10
°C
°C
TSDHYS
DVDT
IdVdt
Thermal Shutdown Hysteresis, TJ↓
dVdt Pin Charging Current
0.78
1.97
3.3
µA
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7.6 Timing Requirements
PARAMETER
TEST CONDITIONS
MIN TYP MAX
UNIT
tOVC
tLIM
Overvoltage clamp response time
VIN > VOVC to VOUT
↓
5
µs
IOUT > 1.2 x ILIM & ITIMER expired to IOUT
settling to within 5 % of ILIM
Current limit response time
400
µs
tSC
Scalable fast-trip response time
IOUT > 3 x ILIM to IOUT
IOUT > IFT to IOUT
↓
500
500
110
50
ns
ns
tFT
Fixed fast-trip response time
↓
tRST
tSWRCB
Auto-Retry Interval after fault (TPS25210A)
Reverse Current Blocking recovery time
ms
µs
(VIN - VOUT) > VFWDTH to VOUT
↑
Reverse Current Blocking comparator
response time
tRCB
(VOUT - VIN) > 1.3 x VREVTH to BFET OFF
1
µs
tPGA
tPGD
PG Assertion de-glitch
12
12
µs
µs
PG De-assertion de-glitch
7.7 Switching Characteristics
The output rising slew rate is internally controlled and constant across the entire operating voltage range to ensure the
turn on timing is not affected by the load conditions. The rising slew rate can be adjusted by adding capacitance from
the dVdt pin to ground. As CdVdt is increased it will slow the rising slew rate (SR). See Slew Rate and Inrush Current
Control (dVdt) section for more details. The Turn-Off Delay and Fall Time, however, are dependent on the RC time constant
of the load capacitance (COUT) and Load Resistance (RL). The Switching Characteristics are only valid for the power-up
sequence where the supply is available in steady state condition and the load voltage is completely discharged before the
device is enabled.Typical Values are taken at TJ = 25°C unless specifically noted otherwise. VIN = 2.7 V, RL = 100 Ω, COUT
1 µF
=
CdVdt = 3300
PARAMETER
CdVdt = Open
12.14
CdVdt = 1800 pF
0.87
UNIT
pF
SRON
tD,ON
tR
Output Rising slew rate
Turn on delay
Rise time
0.5
V/ms
ms
0.09
0.17
0.27
64.44
0.6
0.97
4.33
5.31
2.51
3.11
64.44
ms
tON
Turn on time
ms
tD,OFF
Turn off delay
64.44
µs
VEN/UVLO
VUVLO(R)
VUVLO(F)
EN/UVLO
0
tON
tD,OFF
90%
VIN
SRON
OUT
10%
0V
tR
tD,ON
tF
Time
Figure 7-1. TPS2521xx Switching Times
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7.8 Typical Characteristics
31
30.5
30
0.16
0.14
0.12
0.1
-40
25
125
IOUT (A)
1
3
4
29.5
29
0.08
0.06
0.04
0.02
0
28.5
28
2.7
3.2
3.7
VIN (V)
4.2
4.7
5
0
0.5
1
1.5
2
2.5
3
3.5
4
IOUT (A)
Figure 7-2. ON-Resistance vs Supply Voltage
Figure 7-3. Forward Voltage Drop vs Load Current
435
80
VIN (V)
3.3
5
VIN (V)
2.7
5
430
425
420
415
410
405
400
395
390
385
77.5
75
72.5
70
67.5
65
62.5
60
57.5
55
-40
-20
0
20
40
T
60
A°(C)
80
100 120 140
-40
-20
0
20
40
T
60
A°(C)
80
100 120 140
Figure 7-4. IN Quiescent Current vs Temperature
Figure 7-5. IN OFF state (UVLO) Current vs Temperature
5
2.54
T
A°(C)
4.5
4
-40
2.52
25
85
2.5
105
125
3.5
3
Rising
Falling
2.48
2.46
2.44
2.42
2.4
2.5
2
1.5
1
0.5
2.7
3.2
3.7
VIN (V)
4.2
4.7
5
-40
-20
0
20
40
T
60
A°(C)
80
100 120 140
Figure 7-6. IN Shutdown Current vs Supply Voltage
Figure 7-7. IN Undervoltage Threshold vs Temperature
1.206
1.099
VIN (V)
2.7
5
VIN (V)
2.7
5
1.205
1.204
1.203
1.202
1.201
1.2
1.098
1.097
1.096
1.095
1.094
1.093
-40
-20
0
20
40
T
60
A°(C)
80
100 120 140
-40
-20
0
20
40
T
60
A°(C)
80
100 120 140
Figure 7-8. EN/UVLO Rising Threshold vs Temperature
Figure 7-9. EN/UVLO Falling Threshold vs Temperature
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7.8 Typical Characteristics (continued)
0.8
4500
4200
3900
3600
3300
3000
2700
2400
2100
1800
1500
1200
900
VIN (V)
2.7
5
0.775
0.75
0.725
0.7
0.675
0.65
0.625
0.6
0.575
0.55
600
300
-40
-20
0
20
40
T
60
A°(C)
80
100 120 140
0.5
1
1.5
2
2.5
3
3.5
4
4.5
5
5.5
6
6.5
7
RILMΩ)(k
Figure 7-10. EN/UVLO Shutdown Falling Threshold vs
Temperature
Figure 7-11. Overcurrent Protection Threshold vs ILM resistor
18
10
Min
Max
12
Min
Max
7.5
5
6
0
2.5
0
-2.5
-5
-6
-12
-18
-7.5
-10
0
500 1000 1500 2000 2500 3000 3500 4000 4500
ILIM (mA)
0.5
1
1.5
2
2.5
3
3.5
4
IOUT (A)
Figure 7-12. Overcurrent Protection Threshold Accuracy
(Across Process, Voltage & Temperature)
Figure 7-13. Analog Current Monitor Gain Accuracy
206
24
VIN (V)
2.7
5
VIN (V)
2.7
205
204
203
202
201
200
199
198
23
5
22
21
20
19
18
17
-40
-20
0
20
40
T
60
A°(C)
80
100 120 140
-40
-20
0
20
40
T
60
A°(C)
80
100 120 140
Figure 7-14. Scalable Fast-Trip Threshold:Current Limit
Threshold (ILIM) Ratio vs Temperature
Figure 7-15. Steady State Fixed Fast-Trip Current Threshold vs
Temperature
19.8
-29
VIN (V)
2.7
5
VIN (V)
19.5
19.2
18.9
18.6
18.3
18
2.7
-29.05
5
-29.1
-29.15
-29.2
17.7
17.4
17.1
16.8
-29.25
-29.3
-29.35
-40
-20
0
20
40
T
60
A°(C)
80
100 120 140
-40
-20
0
20
40
T
60
A°(C)
80
100 120 140
Figure 7-16. RCB - Forward Regulation Voltage vs Temperature
Figure 7-17. RCB - Reverse Comparator Threshold vs
Temperature
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7.8 Typical Characteristics (continued)
107
VIN (V)
106.5
2.7
106
5
105.5
105
104.5
104
103.5
103
102.5
102
101.5
101
100.5
-40
-20
0
20
40
T
60
A°(C)
80
100 120 140
Figure 7-19. Reverse Leakage Current During OFF-State
Figure 7-18. RCB - Forward Comparator Threshold vs
Temperature
5.8
5.6
5.4
4
3.95
3.9
T
A°(C)
-40
25
85
105
125
5.2
OVCSEL
GND
OPEN
3.85
3.8
5
4.8
4.6
4.4
4.2
4
3.75
3.7
3.65
3.6
3.8
-40
-20
0
20
40
T
60
A°(C)
80
100 120 140
0
100 200 300 400 500 600 700 800 900 1000
IOUT (mA)
Figure 7-20. OVC Threshold vs Temperature
Figure 7-21. OVC Clamping Voltage (OVCSEL = GND) vs Load
current
5.85
1.518
T
A°(C)
VIN (V)
2.7
5
-40
5.8
5.75
5.7
1.516
1.514
1.512
1.51
25
85
105
125
5.65
5.6
1.508
1.506
1.504
1.502
5.55
5.5
5.45
0
100 200 300 400 500 600 700 800 900 1000
IOUT (mA)
-40
-20
0
20
40
T
60
A°(C)
80
100 120 140
Figure 7-22. OVC Clamping Voltage (OVCSEL = Open) vs Load
current
Figure 7-23. ITIMER discharge differential voltage threshold vs
Temperature
1.83
2.7
18.5
VIN (V)
18
5
2.7
1.825
5
17.5
17
1.82
16.5
16
1.815
1.81
15.5
15
1.805
1.8
14.5
14
1.795
1.79
13.5
13
-40
-20
0
20
40
T
60
A°(C)
80
100 120 140
-40
-20
0
20
40
T
60
A°(C)
80
100 120 140
Figure 7-24. ITIMER discharge current vs Temperature
Figure 7-25. ITIMER internal pull-up resistance vs Temperature
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7.8 Typical Characteristics (continued)
2.6
2.1
2.08
2.06
2.04
2.02
2
VIN (V)
VIN (V)
2.7
5
2.575
2.7
5
2.55
2.525
2.5
2.475
2.45
2.425
2.4
1.98
1.96
1.94
2.375
2.35
2.325
-40
-20
0
20
40
T
60
A°(C)
80
100 120 140
-40
-20
0
20
40
T
60
A°(C)
80
100 120 140
Figure 7-26. ITIMER internal pull-up voltage vs Temperature
Figure 7-27. DVDT Charging Current vs Temperature
0.9
IPGA()
26
242
0.85
0.8
μ
0.75
0.7
0.65
0.6
0.55
0.5
-40
-20
0
20
40
T
60
A°(C)
80
100 120 140
Figure 7-29. PG low voltage without input supply vs
Temperature
Figure 7-28. PGTH Threshold vs Temperature
Figure 7-30. Time to Thermal Shut-Down During Inrush State
Figure 7-31. Time to thermal Shut-Down During Steady State
VIN
VIN
VOUT
EN
VOUT
EN
IIN
IIN
VIN = 5 V, COUT = 220 μF, CdVdt = Open, VEN/UVLO stepped up
to 1.4 V
VEN/UVLO = 1.5 V, COUT = 220 μF, CdVdt = Open, VIN ramped
up to 5 V
Figure 7-32. Start Up with Enable
Figure 7-33. Start Up with Supply
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7.8 Typical Characteristics (continued)
VIN
VIN
VOUT
PG
VOUT
EN
IIN
IIN
VIN = 5 V, COUT = 690 μF, CdVdt = 3300 pF, VEN/UVLO stepped
up to 1.4 V
VIN = 5 V, COUT = 690 μF, ROUT = 4 Ω, CdVdt = 3300 pF, VEN/
UVLO stepped up to 1.4 V
Figure 7-34. Inrush Current with Capacitive Load
Figure 7-35. Inrush Current with Resistive and Capacitive Load
VIN
VIN
VOUT
VOUT
PG
PG
COUT = 220 μF, PG pulled up to 3 V, - 15 V hot-plugged to IN
COUT = 220 μF, PG pulled up to 3 V, VIN ramped down from 0
V to - 15 V and then ramped up to 0 V
Figure 7-36. Input Reverse Polarity Protection - Fast Ramp
Figure 7-37. Input Reverse Polarity Protection - Slow Ramp
VIN
VOUT
VIN
VOUT
PG
PG
ROVCSEL = GND, COUT = 220 μF, IOUT = 120 mA, VIN ramped
up from 3.3 V to 6 V
ROVCSEL = Open, COUT = 220 μF, IOUT = 150 mA, VIN ramped
up from 5 V to 8 V
Figure 7-38. Overvoltage Clamp Response
Figure 7-39. Overvoltage Clamp Response
VIN
VIN
VOUT
VOUT
VITIMER
VITIMER
IIN
IIN
A.
VIN = 5 V, CITIMER = 2.2 nF, COUT = 220 μF, RILM = 750 Ω, IOUT
A.
VIN = 5 V, CITIMER = 2.2 nF, COUT = 220 μF, RILM = 750 Ω, IOUT
stepped from 0 A → 6.7 A
stepped from 2 A → 6 A → 2 A within 1 ms
Figure 7-40. Transient Overcurrent Blanking Timer Response
Figure 7-41. Active Current Limit Response
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7.8 Typical Characteristics (continued)
VIN
VIN
VOUT
VOUT
IOUT
IOUT
VIN = 5 V, RILM = 750 Ω, VEN/UVLO = 1.4 V, OUT stepped from
Open → Short-circuit to GND
VIN = 5 V, RILM = 750 Ω, VEN/UVLO = 1.4 V, OUT stepped from
Open → Short-circuit to GND
Figure 7-42. Output Short-Circuit During Steady State
Figure 7-43. Output Short-Circuit During Steady State (zoomed
in)
VIN
VOUT
PG
IIN
VIN = 5 V, COUT = Open, OUT short-circuit to GND, RILM = 750 Ω, VEN/UVLO stepped from 0 V to 1.4 V
Figure 7-44. Power Up into Short-Circuit
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8 Detailed Description
8.1 Overview
The TPS2521xx is an eFuse with integrated power path that is used to ensure safe power delivery in a system.
The device starts its operation by monitoring the IN bus. When the input supply voltage (VIN) exceeds the
Undervoltage Protection threshold (VUVP), the device samples the EN/UVLO pin. A high level (> VUVLO) on
this pin enables the internal power path (BFET+HFET) to start conducting and allow current to flow from IN to
OUT. When EN/UVLO is held low (< VUVLO), the internal power path is turned off. In case of reverse voltages
appearing at the input, the power path remains OFF thereby protecting the output load.
After a successful start-up sequence, the device now actively monitors its load current and input voltage, and
controls the internal HFET to ensure that the user adjustable overcurrent limit threshold (ILIM) is not exceeded
and overvoltage spikes are either safely clamped to the selected threshold voltage (VOVC). The device also
provides fast protection against severe overcurrent during short-circuit events. This keeps the system safe from
harmful levels of voltage and current. At the same time, a user adjustable overcurrent blanking timer allows the
system to pass moderate transient peaks in the load current profile without tripping the eFuse. This ensures
a robust protection solution against real faults which is also immune to transients, thereby ensuring maximum
system uptime.
The device has integrated reverse current blocking FET (BFET) which operates like an ideal diode. The BFET
is linearly regulated to maintain a small constant forward drop (VFWD) in forward conduction mode and turned off
completely to block reverse current if output voltage exceeds the input voltage.
The device also has a built-in thermal sensor based shutdown mechanism to protect itself in case the device
temperature (TJ) exceeds the recommended operating conditions.
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8.2 Functional Block Diagram
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8.3 Feature Description
The TPS2521xx eFuse is a compact, feature rich power management device that provides detection, protection
and indication in the event of system faults.
8.3.1 Input Reverse Polarity Protection
The TPS2521xx device is internally protected against steady state negative voltages applied at the input supply
pin. The device blocks the negative voltage from appearing at the output, thereby protecting the load circuits.
There’s no reverse current flowing from output to the input in this condition. The lowest negative voltage the
device can handle at the input is limited to -15 V or VOUT – 21 V, whichever is higher. It’s also recommended
that all signal pins (e.g. EN/UVLO, PGTH) which are connected to input supply should have a sufficiently large
pull-up resistor to limit the current flowing out of these pins during reverse polarity conditions.
8.3.2 Undervoltage Lockout (UVLO & UVP)
The TPS2521x implements Undervoltage Protection on IN in case the applied voltage becomes too low for the
system or device to properly operate. The Undervoltage Protection has a default lockout threshold of VUVP which
is fixed internally. Also, the UVLO comparator on the EN/UVLO pin allows the Undervoltage Protection threshold
to be externally adjusted to a user defined value. The Figure 8-1 and Equation 1 show how a resistor divider can
be used to set the UVLO set point for a given voltage supply.
Power
Supply
IN
R1
EN/UVLO
R2
GND
Figure 8-1. Adjustable Undervoltage Protection
V
UVLO(R) x (R1 + R2 )
VIN(UV)
=
(1)
8.3.3 Overvoltage Clamp (OVC)
The TPS2521xx implements a voltage clamp on the output to protect the system in the event of input
overvoltage. When the device detects the input has exceeded the Overvoltage Clamp Threshold (VOVC), it
quickly responds within tOVC and stops the output from rising further and then regulates the HFET linearly to
clamp the output voltage below VCLAMP as long as an overvoltage condition is present on the input.
If the part stays in clamping state for an extended period of time, there will be higher power dissipation inside the
part which may eventually lead to thermal shut-down (TSD). Once the part shuts down due to TSD fault, it would
either stay latched off (TPS2521xL variant) or restart automatically after a fixed delay (TPS2521xA variant). See
Overtemperature Protection (OTP) for more details on device response to overtemperature.
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Input Overvoltage Event
Input Overvoltage Removed
VOVC
IN
Thermal
Shutdown
Retry Timer Expired (1)
0
tOVC
tRST
VCLAMP
OUT
PG
TJ
dVdt Limited Start-up
tPGA
0
tPGD
VPG
0
TSD
TSDHYS
Time
(1) Applicable only for TPS25210A (Auto-retry variant)
Figure 8-2. TPS2521xA Overvoltage Response (Auto-Retry)
There are 2 available overvoltage clamp threshold options which can be configured using the OVCSEL pin.
Table 8-1. TPS2521xx Overvoltage Clamp Threshold Selection
OVCSEL Pin Connection
Shorted to GND
Open
Overvoltage Clamp Threshold
3.8 V
5.7 V
8.3.4 Inrush Current, Overcurrent, and Short Circuit Protection
TPS2521xx incorporates four levels of protection against overcurrent:
1. Adjustable slew rate (dVdt) for inrush current control
2. Adjustable threshold (ILIM) for overcurrent protection during start-up or steady-state
3. Adjustable threshold (ISC) for fast-trip response to severe overcurrent during start-up or steady-state
4. Fixed threshold (IFT) for fast-trip response to quickly protect against hard output short-circuits during steady-
state
8.3.4.1 Slew Rate (dVdt) and Inrush Current Control
During hot-plug events or while trying to charge a large output capacitance at start-up, there can be a large
inrush current. If the inrush current is not managed properly, it can damage the input connectors and/or cause
the system power supply to droop leading to unexpected restarts elsewhere in the system. The inrush current
during turn on is directly proportional to the load capacitance and rising slew rate. Equation 2 can be used to find
the slew rate (SR) required to limit the inrush current (IINRUSH) for a given load capacitance (COUT):
IINRUSH (mA)
SR (V/ms) =
C
OUT (µF)
(2)
A capacitor can be connected to the dVdt pin to control the rising slew rate and lower the inrush current during
turn on. The required CdVdt capacitance to produce a given slew rate can be calculated using Equation 3.
2000
CdVdt (pF) =
SR (V/ms)
(3)
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The fastest output slew rate is achieved by leaving the dVdt pin open.
Note
For CdVdt > 10 nF, it's recommended to add a 100-Ω resistor in series with the capacitor on the dVdt
pin.
8.3.4.2 Active Current Limiting
The TPS2521xx responds to output overcurrent conditions by actively limiting the current after a user adjustable
transient fault blanking interval. When the load current exceeds the set overcurrent threshold (ILIM) set by the
ILM pin resistor (RILM), but stays lower than the short-circuit threshold (2 x ILIM), the device starts discharging the
ITIMER pin capacitor using an internal 1.8-μA pull-down current. If the load current drops below the overcurrent
threshold before the ITIMER capacitor (CITIMER) discharges by ΔVITIMER, the ITIMER is reset by pulling it up to
VINT internally and the current limit action is not engaged. This allows short load transient pulses to pass through
the device without getting current limited. If the overcurrent condition persists, the CITIMER continues to discharge
and once it discharges by ΔVITIMER, the current limit starts regulating the HFET to actively limit the current to
the set overcurrent threshold (ILIM). At the same time, the CITIMER is charged up to VINT again so that it is at its
default state before the next overcurrent event. This ensures the full blanking timer interval is provided for every
overcurrent event. Equation 4 can be used to calculate the RILM value for a desired overcurrent threshold.
3334
: ;
RILM À =
: ;
A
ILIM
(4)
Note
1. Leaving the ILM pin Open sets the current limit to nearly zero and results in the part entering
current limit with the slightest amount of loading at the output.
2. The current limit circuit employs a foldback mechanism. The current limit threshold in the foldback
region (0 V < VOUT < VFB) is lower than the steady state current limit threshold (ILIM).
3. Shorting the ILM pin to ground at any point during normal operation is detected as a fault and the
part shuts down. There’s a minimum current (IFLT) which the part allows in this condition before
the pin short condition is detected.
The duration for which transients are allowed can be adjusted using an appropriate capacitor value from ITIMER
pin to ground. The CITIMER value needed to set the desired transient overcurrent blanking interval can be
calculated using Equation 5 below.
¿VITIMER (V) x CITIMER (nF)
tITIMER (ms) =
IITIMER (µA)
(5)
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Overload Removed
Persistent Output Overload
Transient Overcurrent
Persistent Output Overload
ITIMER expired
ITIMER expired
Thermal shutdown
2 x ILIM
tLIM
tLIM
IOUT
ILIM
Current limiting
operation
Current limiting
operation
0
tITIMER
tITIMER
VINT
∆VITIMER
ITIMER
0
VIN
OUT
0
1.2 V
0
PGTH
tPGD
tPGD
tPGA
VPG
PG
0
TSD
TSDHYS
TJ
TJ
Time
Figure 8-3. TPS2521xx Active Current Limit Response
Note
1. Leave the ITIMER pin open to allow the part to limit the current with the minimum possible delay.
2. Shorting the ITIMER pin to ground results in minimum overcurrent response delay (similar
to ITIMER pin open condition), but increases the device current consumption. This is not a
recommended mode of operation.
3. Active current limiting based on RILM is active during startup. In case the startup current exceeds
ILIM, the device regulates the current to the set limit. However, during startup the current limit is
engaged without waiting for the ITIMER delay.
4. During overvoltage clamp condition, if an overcurrent event occurs, the current limit is engaged
without waiting for the ITIMER delay.
5. Increasing the CITIMER value extends the overcurrent blanking interval, but it also extends the
time needed for the CITIMER to recharge up to VINT. If the next overcurrent event occurs before
the CITIMER is recharged fully, it will take lesser time to discharge to the ITIMER expiry threshold,
thereby providing a shorter blanking interval than intended.
During active current limit, the output voltage will drop resulting in increased device power dissipation across the
HFET. If the device internal temperature (TJ) exceeds the thermal shutdown threshold (TSD), the HFET is turned
off. Once the part shuts down due to TSD fault, it would either stay latched off (TPS252x1L variant) or restart
automatically after a fixed delay (TPS2521xA variant). See Overtemperature Protection (OTP) for more details
on device response to overtemperature.
8.3.4.3 Short-Circuit Protection
During an output short-circuit event, the current through the device increases very rapidly. When a severe
overcurrent condition is detected, the device triggers a fast-trip response to limit the current to a safe level.
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The internal fast-trip comparator employs a scalable threshold (ISC) which is equal to 2 × ILIM. This enables the
user to adjust the fast-trip threshold rather than using a fixed threshold which can be too high for some low
current systems. The device also employs a fixed fast-trip threshold (IFT) to protect fast protection against hard
short-circuits during steady state. The fixed fast-trip threshold is higher than the maximum recommended user
adjustable scalable fast-trip threshold. Once the current exceeds ISC or IFT, the HFET is turned off completely
within tFT. Thereafter, the devices tries to turn the HFET back ON after a short de-glitch interval (30 μs) in a
current limited manner instead of a dVdt limited manner. This ensures that the HFET has a faster recovery after
a transient overcurrent event and minimizes the output voltage droop. However, if the fault is persistent, the
device will stay in current limit causing the junction temperature to rise and eventually enter thermal shutdown.
See Overtemperature Protection (OTP) section for details on the device response to overtemperature.
Persistent Severe Overcurrent
Thermal Shutdown
Overcurrent Removed
Retry Timer Elapsed (1)
Transient Severe Overcurrent
Output Hard Short-circuit to ground
Thermal Shutdown
Short-circuit Removed
Retry Timer Elapsed (1)
VIN
IN
0
tFT
tSC
tSC
IFT
2 x ILIM
IOUT
ILIM
0
VIN
OUT
PG
TJ
dVdt Limited
Start-up
dVdt Limited
Start-up
Current Limited
Start-up
0
tPGD
tPGD
tPGD
VPG
0
tRST
tRST
TSD
TSDHYS
(1) Applicable only for TPS25210A variant
Time
Figure 8-4. TPS2521xx Short-Circuit Response
8.3.5 Analog Load Current Monitor
The device allows the system to accurately monitor the output load current by providing an analog current sense
output on the ILM pin which is proportional to the current through the FET. The user can sense the voltage (VILM
)
across the RILM to get a measure of the output load current.
VILM (µV)
IOUT (A) =
RILM :À; x GIMON (µA/A)
(6)
The waveform below shows the ILM signal response to a load step at the output.
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VIN
VOUT
VILM
IIN
VIN = 5 V, COUT = 220 μF, RILM = 750 Ω, IOUT stepped up from 0 A to 4 A
Figure 8-5. Analog Load Current Monitor Response
Note
The ILM pin is sensitive to capacitive loading. Careful design and layout is needed to ensure the
parasitic capacitive loading on the ILM pin is < 50 pF for stable operation.
8.3.6 Reverse Current Protection
The device functions like an ideal diode and blocks reverse current flow from OUT to IN under all conditions.
The device has integrated back-to-back MOSFETs connected in a common drain configuration. The voltage
drop between the IN and OUT pins is constantly monitored and the gate drive of the blocking FET (BFET) is
adjusted as needed to regulate the forward voltage drop at VFWD. This closed loop regulation scheme (linear
ORing control) enables graceful turn off of the MOSFET during a reverse current event and ensures there's no
DC reverse current flow.
The device also uses a conventional comparator (VREVTH) based reverse blocking mechanism to provide fast
response (tRCB) to transient reverse currents.Once the device enters reverse current blocking condition, it waits
for the (VIN - VOUT) forward drop to exceed the VFWDTH before it performs a fast recovery to reach full forward
conduction state. This provides sufficient hysterisis to prevent supply noise or ripple from affecting the reverse
current blocking response. The recovery from reverse current blocking is very fast (tSWRCB). This ensures
minimum supply droop which is helpful in applications such as supply MUXing/ORing and USB Fast Role Swap
(FRS).
VFWD
IN
OUT
OUT
IN
BFET operating state
BFET turned OFF BFET regulation
BFET fast disable
Linear ORing loop response
BFET full conduction
BFET fast enable
(RCB exit)
RCB fast comparator response
(RCB entry)
VIN - VOUT
IIN
0 V
0 A
VFWD
VREVTH
Reverse
VFWTH
Forward
Figure 8-6. Reverse Current Blocking Response
The waveforms below illustrate the reverse current blocking performance in various scenarios.
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During fast voltage step at output (e.g. hot-plug), the fast comparator based reverse blocking mechanism
ensures minimum jump/glitch on the input rail.
VIN
VBUS
IIN
Figure 8-7. Reverse Current Blocking Performance During Fast Voltage Step at Output
During slow voltage ramp at output, the linear ORing based reverse blocking mechanism ensures there's no DC
current flow from OUT to IN, thereby avoiding input rail from getting slowly charged up to output voltage.
VIN
VBUS
IIN
Figure 8-8. Reverse Current Blocking Performance During Slow Voltage Ramp at Output
When the input supply droops or gets disconnected while the output storage element (capacitor bank or super
capacitor) is charged to the full voltage, the linear ORing scheme minimizes the self-discharge from OUT to IN.
This ensures maximum hold-up time for the output storage element in critical power back-up applications.
It also prevents incorrect supply presence indication in applications which sense the input voltage to detect if the
supply is connected.
VIN
VOUT
PG
Figure 8-9. Reverse Current Blocking Performance During Input Supply Failure
8.3.7 Overtemperature Protection (OTP)
The device monitors the internal die temperature (TJ) at all times and shuts down the part as soon as the
temperature exceeds a safe operating level (TSD) thereby protecting the device from damage. The device will
not turn back on until the junction cools down sufficiently, that is the die temperature falls below (TSD - TSDHYS).
When the TPS2521xL (latch-off variant) detects thermal overload, it will be shut down and remain latched-off
until the device is power cycled or re-enabled. When the TPS2521xA (auto-retry variant) detects thermal
overload, it will remain off until it has cooled down by TSDHYS. Thereafter, it will remain off for an additional
delay of tRST after which it will automatically retry to turn on if it is still enabled.
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Table 8-2. Thermal Shutdown
Device
Enter TSD
Exit TSD
TJ < TSD - TSDHYS
VIN cycled to 0 V and then above VUVP(R) OR
EN/UVLO toggled below VSD(F)
TPS2521xL (Latch-Off)
TJ ≥ TSD
TJ ≥ TSD
TJ < TSD - TSDHYS
VIN cycled to 0 V and then above VUVP(R) OR
TPS2521xA (Auto-Retry)
EN/UVLO toggled below VSD(F) OR tRST timer
expired
8.3.8 Fault Response
The following table summarizes the device response to various fault conditions.
Table 8-3. Fault Summary
Event
Protection Response
Fault Latched Internally
Overtemperature
Shutdown
Y
N
N
N
N
N
N
Undervoltage (UVP or UVLO)
Input Reverse Polarity
Input Overvoltage
Shutdown
Shutdown
Voltage Clamp
None
Transient Overcurrent (ILIM < IOUT < 2 x ILIM
Persistent Overcurrent
Output Short-Circuit to GND
)
Current Limit
Fast trip followed by Current Limit
ILM Pin Open
(During Steady State)
Shutdown
N
ILM Pin Shorted to GND
Shutdown
Y
N
Reverse Current ((VOUT - VIN) > VREVTH
)
Reverse Current Blocking
Faults which are latched internally can be cleared either by power cycling the part (pulling VIN to 0 V) or by
pulling the EN/UVLO pin voltage below VSD. This also resets the tRST timer for the TPS2521xA (auto-retry)
variants.
During a latched fault, pulling the EN/UVLO just below the UVLO threshold has no impact on the device. This is
true for both TPS2521xL (latch-off) & TPS2521xA (auto-retry) variants.
For TPS2521xA (auto-retry) variant, on expiry of the tRSTtimer after a fault, the device restarts automatically.
8.3.9 Power Good Indication (PG)
The TPS2521xx provides an active high digital output (PG) which serves as a power good indication signal and
is asserted high depending on the voltage at the PGTH pin along with the device state information. The PG is an
open-drain pin and needs to be pulled up to an external supply.
After power up, PG is pulled low initially. The device initiates a inrush sequence in which the HFET is turned
on in a controlled manner. When the HFET gate voltage reaches the full overdrive indicating that the inrush
sequence is complete and the voltage at PGTH is above VPGTH(R), the PG is asserted after a de-glitch time
(tPGA).
PG is de-asserted if at any time during normal operation, the voltage at PGTH falls below VPGTH(F), or the device
detects a fault (except overcurrent). The PG de-assertion de-glitch time is tPGD
.
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Overload Event
Overcurrent blanking timer expired
Overload Removed
Device Enabled
VUVLO(R)
EN/UVLO
0
VIN
IN
Slew rate (dVdt) controlled
startup/Inrush current limiting
0
Active Current
limiting
VIN
OUT
0
VPGTH(R)
VPGTH(F)
PGTH
PG
0
VPG
tPGA
tPGD
tPGA
0
VIN
dVdt
0
VOUT + 2.8V
VHGate
0
tITIMER
ILIM
IINRUSH
IOUT
0
Time
Figure 8-10. TPS2521xx PG Timing Diagram
Table 8-4. TPS2521xx PG Indication Summary
Event
Protection Response
PG Pin
PG Delay
Undervoltage (UVP or UVLO)
Input Reverse Polarity
Shutdown
L
Shutdown
L
H (If PGTH pin voltage >
VPGTH(R)
L (If PGTH pin voltage <
VPGTH(F)
)
tPGA
tPGD
Overvoltage (OVC)
Clamp
)
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Event
Table 8-4. TPS2521xx PG Indication Summary (continued)
Protection Response
PG Pin
PG Delay
H (If PGTH pin voltage >
VPGTH(R)
L (If PGTH pin voltage <
VPGTH(F)
)
tPGA
tPGD
Steady State
NA
)
H (If PGTH pin voltage >
VPGTH(R)
L (If PGTH pin voltage <
VPGTH(F)
)
tPGA
tPGD
Transient overcurrent
Persistent overload
NA
)
H (If PGTH pin voltage >
VPGTH(R)
L (If PGTH pin voltage <
VPGTH(F)
)
tPGA
tPGD
Current Limiting
)
H (If PGTH pin voltage >
Fast trip followed by Current Limit VPGTH(R)
L (If PGTH < VPGTH(F)
tPGA
tPGD
Output Short-Circuit to GND
ILM Pin Open
)
)
L (If PGTH pin voltage <
VPGTH(F)
Shutdown
tPGD
tPGD
tPGD
)
ILM Pin Shorted to GND
Shutdown
L (If PGTH < VPGTH(F)
)
Reverse current ((VOUT - VIN) >
Reverse current blocking
L
VREVTH
)
L (If PGTH pin voltage <
VPGTH(F)
Overtemperature
Shutdown
tPGD
)
When there is no supply to the device, the PG pin is expected to stay low. However, there is no active pull-down
in this condition to drive this pin all the way down to 0 V. If the PG pin is pulled up to an independent supply
which is present even if the device is unpowered, there can be a small voltage seen on this pin depending on the
pin sink current, which is a function of the pull-up supply voltage and resistor. Minimize the sink current to keep
this pin voltage low enough not to be detected as a logic HIGH by associated external circuits in this condition.
8.4 Device Functional Modes
Table 8-5. TPS2521xx Overvoltage Clamp Threshold Selection
OVCSEL Pin Connection
Shorted to GND
Open
Overvoltage Clamp Threshold
3.8 V
5.7 V
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9 Application and Implementation
Note
Information in the following applications sections is not part of the TI component specification,
and TI does not warrant its accuracy or completeness. TI’s customers are responsible for
determining suitability of components for their purposes, as well as validating and testing their design
implementation to confirm system functionality.
9.1 Application Information
The TPS2521xx is a 2.7 V to 5.7 V, 4-A eFuse that is typically used for power rail protection applications. It
can withstand maximum input voltage of 28 V with adjustable undervoltage lockout and fast overvoltage clamp
protection. It provides ability to control inrush current and protection against input reverse polarity as well as
reverse current conditions. It can be used in a variety of systems such as Adapter Input Protection, Storage
– eSSD/cSSD, e-Meters, Smart Speakers, Headphones, USB power accessories. The design procedure
explained in the subsequent sections can be used to select the supporting component values based on the
application requirement. Additionally, a spreadsheet design tool TPS2521x Design Calculator is available in the
web product folder.
9.2 Single Device, Self-Controlled
VIN = 2.7 to 5.7 V
VOUT
IN
OUT
COUT
VLOGIC
PGTH
EN/UVLO
OVCSEL
TPS25210x
PG
ITIMER dVdt
ILM
GND
Figure 9-1. Single Device, Self-Controlled
Other variations:
In a Host MCU controlled system, EN/UVLO or OVCSEL can also be driven from the host GPIO to control/
configure the device operation.
ILM pin can be connected to the MCU ADC input for current monitoring purpose.
Note
It's recommended to keep parasitic capacitance on ILM pin below 50 pF to ensure stable operation.
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Either VIN or VOUT can be used to drive the PGTH resistor divider depending on which supply needs to be
monitored for power good indication.
9.3 Typical Application
End equipments like PC, Notebooks, Docking Stations, Monitors etc.. have USB PD ports which can be
configured as DFP (Source), UFP (Sink) or DRP (Source+Sink). TPS2521xx can be used independently or
in conjunction with LM73100 to handle the power path protection requirements of USB PD ports as shown in
Figure 9-2 below.
TPS2521xx provides Overcurrent & Short-Circuit protection in the source path, while blocking any reverse
current from the port to the internal source power rail. The fast recovery (tSWRCB) from reverse current blocking
ensures minimum supply droop during Fast Role Swap (FRS) events.
The LM73100 provides overvoltage protection on the sink path, while blocking reverse current from internal sink
rail to the port.
The linear ORing mechanism in TPS2521xx & LM73100 ensures that there's no reverse current flowing from
one power source to the other during fast or slow ramp of either supply.
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VOUT = 5 V to 20 V
IN
OUT
OVLO
IMON
LM73100
PGTH
dVdt
PG
EN/UVLO
GND
VBUS = 5 V to 20V
CDVDT
PD Controller
EN/UVLO
PG
IN
OUT
VIN = 5 V
TPS25210L
PGTH
OVCSEL
ITIMER dVdt
ILM
GND
RILM
CDVDT
CITIMER
Figure 9-2. USB PD Port Protection
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9.3.1 Application
USB DATA
VIN = 5V
IN
OUT
VBUS
COUT
10uF
R3
100 kO
R1
470 kO
PGTH
EN/UVLO
OVCSEL
TPS25210L
R4
36.5 kO
3.3V
47 kO
R2
205 kO
PG
ITIMER dVdt
GND ILM
CDVDT
1 nF
RILM
953 O
CITIMER
2.2 nF
Figure 9-3. TPS2521xx Application Circuit for USB PD Source Path Protection
9.3.2 Design Requirements
Table 9-1. Design Parameters
PARAMETER
VALUE
5 V
Input supply voltage (VIN)
Undervoltage threshold (VIN(UV)
)
4 V
Overvoltage Clamp (VIN(OVC)
Output power good threshold (VPG
Output capacitance (COUT
)
5.7 V
4.5 V
10 μF
2 V/ms
)
)
Output Slew Rate (SR)
Max continuous current
3 A
Overcurrent response
Current Limit
3.5 A
Current Limit Threshold (ILIM
)
Load transient blanking interval (tITIMER
)
2 ms
Fault response
Latch-off
9.3.3 Detailed Design Procedure
9.3.3.1 Device Selection
Since the application requires current limit response to overcurrent with latch-off response after a fault, the
TPS25210L variant is selected after refering to the Device Comparison Table.
9.3.3.2 Setting Undervoltage and Overvoltage Thresholds
The supply undervoltage threshold is set using the resistors R1 , R2 and can be calculated using Equation 7:
V
UVLO(R) x (R1 + R2 )
VIN(UV)
=
(7)
VUVLO(R) is the UVLO rising threshold. Because R1 & R2 leak the current from input supply VIN, these resistors
must be selected based on the acceptable leakage current from input power supply VIN. The current drawn by
R1 and R2 from the power supply is IR12 = VIN / (R1 + R2 ). However, leakage currents due to external active
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components connected to the resistor string can add error to these calculations. So, the resistor string current,
IR12 must be chosen to be 20 times greater than the leakage current expected on the EN/UVLO pin.
From the device electrical specifications, the EN/UVLO leakage current is 0.1 μA (max), and VUVLO(R) = 1.2 V.
From design requirements,VIN(UV) = 4 V. To solve the equation, first choose the value of R1 = 470 kΩ and use
the above equation to solve for R2 = 201.4 kΩ.
Using the closest standard 1% resistor values, we get R1 = 470 kΩ and R2 = 205 kΩ.
Refer to Table 8-5 to set overvoltage clamp. OVCSEL pin is left open to select overvoltage clamp as 5.7 V.
9.3.3.3 Setting Output Voltage Rise Time (tR)
The slew rate (SR) needed to meet the target specification is:
SR (V/ms) = 2 V/ms
(8)
(9)
The CdVdt needed to achieve this slew rate can be calculated as:
2000
2000
2
:
;
CdVdt pF =
=
;
= 1000 pF
:
SR V/ms
Choose the nearest standard capacitor value as 1 nF.
For this slew rate, the inrush current can be calculated as:
:
;
:
IINRUSH mA = SR (V/ms) x COUT µF = 2 x 10 = 20 mA
;
(10)
(11)
The average power dissipation inside the part during inrush can be calculated as:
: ;
IINRUSH A x VIN
: ;
V
0.02 x 5
2
: ;
PDINRUSH W =
=
= 0.05 W
2
The power dissipation is below the allowed limit for a successful start-up without hitting thermal shut-down within
the target rise time as shown in Figure 9-4.
Figure 9-4. Thermal Shut-Down Plot During Inrush
9.3.3.4 Setting Power Good Assertion Threshold
The Power Good assertion threshold can be set using the resistors R3 & R4 connected to the PGTH pin whose
values can be calculated as:
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VPGTH(R) x (R3 + R4)
R4
VPG =
(12)
Because R3 and R4 leak the current from the output rail VOUT, these resistors must be selected to minimize the
leakage current. The current drawn by R3and R4 from the power supply is IR34 = VOUT / (R3+ R4). However,
leakage currents due to external active components connected to the resistor string can add error to these
calculations. So, the resistor string current, IR34 must be chosen to be 20 times greater than the PGTH leakage
current expected.
From the device electrical specifications, PGTH leakage current is 1 μA (max), VPGTH(R) = 1.2 V and from design
requirements, VPG = 4.5 V. To solve the equation, first choose the value of R3 = 100 kΩ and calculate R4 = 36.4
kΩ. Choose nearest 1% standard resistor value as R4 = 36.5 kΩ.
9.3.3.5 Setting Overcurrent Threshold (ILIM
)
The overcurrent protection (Current limit) threshold can be set using the RILM resistor whose value can be
calculated as:
3334
3334
3.5 A
: ;
RILM À =
=
= 952.57 À
: ;
A
ILIM
(13)
Choose nearest 1% standard resistor value as 953 Ω.
9.3.3.6 Setting Overcurrent Blanking Interval (tITIMER
)
The overcurrent blanking timer interval can be set using the CITIMER capacitor whose value can be calculated as:
tITIMER (ms) x IITIMER (µA) 2 x 1.8
=
CITIMER (nF) =
= 2.4 nF
¿VITIMER (V)
1.5
(14)
Choose nearest standard capacitor value as 2.2 nF.
9.3.4 Application Curves
VIN
VIN
VBUS
VBUS
IIN
IIN
Figure 9-5. VBUS 20-V Hot-Plug
Figure 9-6. VBUS 20-V Slow Ramp Up
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VIN
VBUS
IIN
VIN = 5 V, COUT = 10 μF, ROUT = 8 Ω, VBUS = 20 V initially and then disconnected
Figure 9-7. Fast Role Swap
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10 Power Supply Recommendations
The TPS2521xx devices are designed for a supply voltage range of 2.7 V ≤ VIN ≤ 5.7 V. An input ceramic
bypass capacitor higher than 0.1 μF is recommended if the input supply is located more than a few inches from
the device. The power supply must be rated higher than the set current limit to avoid voltage droops during
overcurrent and short-circuit conditions.
The lowest negative voltage the device can handle at the input is limited to -15 V or VOUT – 21 V, whichever is
higher. Any low voltage signals (e.g. EN/UVLO, PGTH) derived from the input supply must have a sufficiently
large pull-up resistor to limit the current through those pins to < 10 μA during reverse polarity conditions. Please
refer to Absolute Maximum Ratings table for more details.
10.1 Transient Protection
In the case of a short-circuit and overload current limit when the device interrupts current flow, the input
inductance generates a positive voltage spike on the input, and the output inductance generates a negative
voltage spike on the output. The peak amplitude of voltage spikes (transients) is dependent on the value of
inductance in series to the input or output of the device. Such transients can exceed the absolute maximum
ratings of the device if steps are not taken to address the issue. Typical methods for addressing transients
include:
• Minimize lead length and inductance into and out of the device.
• Use a large PCB GND plane.
• Use a Schottky diode across the output to absorb negative spikes.
• Connect a low ESR capacitor of value greater than 1 μF at the OUT pin very close to the device.
• Use a low-value ceramic capacitor CIN = 1 μF to absorb the energy and dampen the transients. The capacitor
voltage rating should be atleast twice the input supply voltage to be able to withstand the positive voltage
excursion during inductive ringing.
The approximate value of input capacitance can be estimated with Equation 15:
LIN
VSPIKE(Absolute) = VIN + ILOAD x
CIN
(15)
where
• VIN is the nominal supply voltage.
• ILOAD is the load current.
• LIN equals the effective inductance seen looking into the source.
• CIN is the capacitance present at the input.
Some applications may require the addition of a Transient Voltage Suppressor (TVS) to prevent transients from
exceeding the absolute maximum ratings of the device. In some cases, even if the maximum amplitude of the
transients is below the absolute maximum rating of the device, a TVS can help to absorb the excessive energy
dump and prevent it from creating very fast transient voltages on the input supply pin of the IC, which can couple
to the internal control circuits and cause unexpected behavior.
Note
If there's a likelihood of input reverse polarity in the system, it's recommended to use a bi-directional
TVS, or a reverse blocking diode in series with the TVS.
For applications such as USB-C ports where a powered cable can be plugged to the output of the device, there
could be excess voltage stress from OUT to IN which exceeds the absolute maximum rating of the device. It's
recommended to add a TVS diode from OUT to IN to clamp the voltage to a safe level.
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The circuit implementation with optional protection components is shown in Figure 10-1.
D3
D4
VOUT
VIN = 2.7 to 5.7 V
IN
OUT
R1
R2
COUT
D2
PGTH
EN/UVLO
OVCSEL
VLOGIC
TPS25210x
CIN
D1
PG
ITIMER
dVdt
GND
ILM
RILM
CITIMER
CDVDT
Figure 10-1. Circuit Implementation with Optional Protection Components
10.2 Output Short-Circuit Measurements
It is difficult to obtain repeatable and similar short-circuit testing results. The following contribute to variation in
results:
• Source bypassing
• Input leads
• Circuit layout
• Component selection
• Output shorting method
• Relative location of the short
• Instrumentation
The actual short exhibits a certain degree of randomness because it microscopically bounces and arcs. Ensure
that configuration and methods are used to obtain realistic results. Do not expect to see waveforms exactly like
those in this data sheet because every setup is different.
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11 Layout
11.1 Layout Guidelines
•
•
For all applications, a ceramic decoupling capacitor of 0.1 μF or greater is recommended between the IN
terminal and GND terminal.
The optimal placement of the decoupling capacitor is closest to the IN and GND terminals of the device. Care
must be taken to minimize the loop area formed by the bypass-capacitor connection, the IN terminal, and the
GND terminal of the IC.
•
•
High current-carrying power-path connections must be as short as possible and must be sized to carry at
least twice the full-load current.
The GND terminal must be tied to the PCB ground plane at the terminal of the IC with the shortest possible
trace. The PCB ground must be a copper plane or island on the board. It's recommended to have a separate
ground plane island for the eFuse. This plane doesn't carry any high currents and serves as a quiet ground
reference for all the critical analog signals of the eFuse. The device ground plane should be connected to the
system power ground plane using a star connection.
•
•
The IN and OUT pins are used for heat dissipation. Connect to as much copper area on top and bottom PCB
layers using as possible. Adding thermal vias on the under the device further helps to minimize the voltage
gradient accross the IN and OUT pads and distribute current unformly through the device, which improves
the on-resistance and current sense accuracy.
Locate the following support components close to their connection pins:
– RILM
– CdVdT
– CITIMER
– Resistors for the EN/UVLO, OVCSEL and PGTH pins
•
Connect the other end of the component to the GND pin of the device with shortest trace length. The trace
routing for the RILM, CITIMER and CdVdt components to the device must be as short as possible to reduce
parasitic effects on the current limit , overcurrent blanking interval and soft start timing. It's recommended to
keep parasitic capacitance on ILM pin below 50 pF to ensure stable operation. These traces must not have
any coupling to switching signals on the board.
•
•
Since the bias current on ILM pin directly controls the overcurrent protection behavior of the device, the PCB
routing of this node must be kept away from any noisy (switching) signals.
Protection devices such as TVS, snubbers, capacitors, or diodes must be placed physically close to the
device they are intended to protect. These protection devices must be routed with short traces to reduce
inductance. For example, a protection Schottky diode is recommended to address negative transients due to
switching of inductive loads. It's also recommended to add a ceramic decoupling capacitor of 1 μF or greater
between OUT and GND. These components must be physically close to the OUT pins. Care must be taken to
minimize the loop area formed by the Schottky diode/bypass-capacitor connection, the OUT pin and the GND
terminal of the IC.
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11.2 Layout Example
Bottom Signal/GND layer
Top Power layer
6
5
OUT
IN
OUT
IN
Figure 11-1. Layout Example
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12 Device and Documentation Support
TI offers an extensive line of development tools. Tools and software to evaluate the performance of the device,
generate code, and develop solutions are listed below.
12.1 Documentation Support
12.1.1 Related Documentation
For related documentation see the following:
•
•
•
•
TPS25210EVM eFuse Evaluation Board
TPS2521x Design Calculator
Application brief - eFuses for USB Type-C protection
Application brief - eFuses in smart e-meters
12.2 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. Click on
Subscribe to updates to register and receive a weekly digest of any product information that has changed. For
change details, review the revision history included in any revised document.
12.3 Support Resources
TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help — straight
from the experts. Search existing answers or ask your own question to get the quick design help you need.
Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do
not necessarily reflect TI's views; see TI's Terms of Use.
12.4 Trademarks
TI E2E™ is a trademark of Texas Instruments.
All trademarks are the property of their respective owners.
12.5 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled
with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may
be more susceptible to damage because very small parametric changes could cause the device not to meet its published
specifications.
12.6 Glossary
TI Glossary
This glossary lists and explains terms, acronyms, and definitions.
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13 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
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PACKAGE OPTION ADDENDUM
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7-Apr-2021
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
TPS25210ARPWR
ACTIVE
VQFN-HR
RPW
10
3000 RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 125
2AJH
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
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In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
8-Apr-2021
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
TPS25210ARPWR
VQFN-
HR
RPW
10
3000
180.0
8.4
2.3
2.3
1.15
4.0
8.0
Q2
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
8-Apr-2021
*All dimensions are nominal
Device
Package Type Package Drawing Pins
VQFN-HR RPW 10
SPQ
Length (mm) Width (mm) Height (mm)
210.0 185.0 35.0
TPS25210ARPWR
3000
Pack Materials-Page 2
PACKAGE OUTLINE
VQFN-HR - 1 mm max height
PLASTIC QUAD FLATPACK - NO LEAD
RPW0010A
2.1
1.9
A
B
2.1
1.9
PIN 1 IDENTIFICATION
(0.1) TYP
1 MAX
C
SEATING PLANE
0.08 C
0.05
0.00
2X 1.45
PKG
4X
SQ (0.15) TYP
4X 0.475
4
2X 0.25
6
5
7
0.35
4X
4X 0.475
0.25
0.1
C A B
C
0.05
2.1
1.9
2X
2X 0.45
PKG
4X
0.3
0.2
0.1
0.05
C A B
C
1
10
0.3
0.2
PIN 1 ID
(OPTIONAL)
4X
0.5
0.3
0.35
0.25
8X
2X
0.1
C A B
C
0.1
C A B
0.05
0.05
C
4225183/A 08/2019
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
www.ti.com
EXAMPLE BOARD LAYOUT
VQFN-HR - 1 mm max height
PLASTIC QUAD FLATPACK - NO LEAD
RPW0010A
(1.8)
(1.45)
4X (0.475)
2X (0.25)
1
10
4X (0.25)
4X
(0.225)
PKG
2X
2X
(1.75)
(2.4)
4X (0.3)
4X (0.475)
7
4
4X
(0.65)
(R0.05) TYP
6
5
2X (0.3)
4X (0.25)
PKG
8X (0.6)
LAND PATTERN EXAMPLE
SCALE: 30X
SOLDER MASK
OPENING
0.05 MAX
ALL AROUND
0.05 MIN
ALL AROUND
METAL
METAL UNDER
SOLDER MASK
SOLDER MASK
OPENING
EXPOSED METAL
EXPOSED METAL
SOLDER MASK
DEFINED
NON- SOLDER MASK
DEFINED
(PREFERRED)
SOLDER MASK DETAILS
NOT TO SCALE
4225183/A 08/2019
NOTES: (continued)
3. For more information, see Texas Instruments literature number SLUA271 (www.ti.com/lit/slua271).
4. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
www.ti.com
EXAMPLE STENCIL DESIGN
VQFN-HR - 1 mm max height
PLASTIC QUAD FLATPACK - NO LEAD
RPW0010A
(1.8)
(1.425)
4X (0.4625)
2X (0.25)
METAL TYP
1
10
4X (0.25)
4X
(0.63)
PKG
2X
(1.75)
4X (0.225)
4X (0.275)
4X
4X (0.4625)
(1.06)
7
4
4X
(0.65)
(R0.05)
TYP
6
5
4X (0.28)
4X (0.225)
PKG
8X (0.6)
SOLDER PASTE EXAMPLE
BASED ON 0.100 mm THICK STENCIL
PADS 1, 4,7 & 10: 93%; PADS 5 & 6: 82%
SCALE: 30X
4225183/A 08/2019
NOTES: (continued)
5.
Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
www.ti.com
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