TPS22953-Q1 [TI]
TPS2295x-Q1 5.7-V, 5-A, 14-mΩ On-Resistance, Automotive Load Switch;
| 型号： | TPS22953-Q1 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | TPS2295x-Q1 5.7-V, 5-A, 14-mΩ On-Resistance, Automotive Load Switch |
| 文件： | 总47页 (文件大小：3273K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
TPS22953-Q1, TPS22954-Q1
SLVSGK4 – NOVEMBER 2021
TPS2295x-Q1 5.7-V, 5-A, 14-mΩ On-Resistance, Automotive Load Switch
1 Features
3 Description
•
•
Qualified for automotive applications
AEC-Q100 qualified:
The TPS2295x-Q1 are small, single channel load
switches with controlled turn on. The devices contain
a N-channel MOSFET that can operate over an input
voltage range of 0.7 V to 5.7 V and can support a
maximum continuous current of 5 A.
– Device temperature grade 1: –40°C to 125°C
ambient operating temperature range
Integrated single channel load switch
Input voltage range: 0.7 V to 5.7 V
RON resistance
– RON = 14 mΩ at VIN = 5 V (VBIAS = 5 V)
5-A maximum continuous switch current
Adjustable Undervoltage Lockout Threshold
(UVLO)
•
•
•
The integrated adjustable Undervoltage Lockout
(UVLO) and adjustable Power Good (PG) threshold
provides voltage monitoring as well as robust power
sequencing. The adjustable rise time control of the
device greatly reduces inrush current for a wide
variety of bulk load capacitances, thereby reducing
or eliminating power supply droop. The switch is
independently controlled by an on and off input
(EN), which is capable of interfacing directly with
low-voltage control signals. A 15-Ω on-chip load is
integrated into the device for a quick discharge of the
output when the switch is disabled. The enhanced
Quick Output Discharge (QOD) remains active for a
short time after power is removed from the device to
finish discharging the output.
•
•
•
Adjustable voltage supervisor with
Power Good (PG) indicator
•
•
Adjustable output slew rate control
Enhanced quick output discharge remains active
after power is removed (TPS22954-Q1 only)
– 15 Ω (typ.) discharges 100 µF within 10 ms
Reverse current blocking when disabled
(TPS22953-Q1 only)
Automatic restart after supervisor fault detection
when enabled
Thermal shutdown
•
•
The TPS2295x-Q1 are available in small, space-
saving 10-SON packages with integrated thermal
pad, allowing for high power dissipation. The device
is characterized for operation over the free-air
temperature range of –40°C to +125°C.
•
•
•
•
Low quiescent current ≤ 50 µA
SON 10-pin package with thermal pad
ESD performance tested per JESD 22
– 2-kV HBM and 750-V CDM
Device Information(1)
2 Applications
PART NUMBER
PACKAGE (PIN)
BODY SIZE (NOM)
•
•
•
•
Infotainment and cluster head unit
Automotive cluster display
ADAS surround view system ECU
Body control module and gateway
TPS2295x-Q1
WSON (10)
2.00 mm × 3.00 mm
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
Simplified Schematic
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. ADVANCE INFORMATION for preproduction products; subject to change
without notice.
TPS22953-Q1, TPS22954-Q1
SLVSGK4 – NOVEMBER 2021
www.ti.com
Table of Contents
1 Features............................................................................1
2 Applications.....................................................................1
3 Description.......................................................................1
4 Revision History.............................................................. 2
5 Device Comparison Table...............................................3
6 Pin Configuration and Functions...................................3
7 Specifications.................................................................. 4
7.1 Absolute Maximum Ratings........................................ 4
7.2 ESD Ratings .............................................................. 4
Recommended Operating Conditions...............................4
7.3 Thermal Information....................................................4
7.4 Electrical Characteristics.............................................5
7.5 Electrical Characteristics – VBIAS = 5 V.................... 5
7.6 Electrical Characteristics – VBIAS = 3.3 V................. 6
7.7 Electrical Characteristics – VBIAS = 2.5 V................. 7
7.8 Switching Characteristics – CT = 1000 pF..................9
7.9 Switching Characteristics – CT = 0 pF......................10
7.10 Typical DC Characteristics......................................11
7.11 Typical Switching Characteristics............................14
8 Parameter Measurement Information..........................20
9 Detailed Description......................................................21
9.1 Overview...................................................................21
9.2 Functional Block Diagram.........................................21
9.3 Feature Description...................................................22
9.4 Device Functional Modes..........................................28
10 Application and Implementation................................29
10.1 Application Information........................................... 29
10.2 Typical Application.................................................. 34
11 Power Supply Recommendations..............................37
12 Layout...........................................................................37
12.1 Layout Guidelines................................................... 37
12.2 Layout Example...................................................... 37
13 Device and Documentation Support..........................38
13.1 Documentation Support.......................................... 38
13.2 Related Links.......................................................... 38
13.3 Receiving Notification of Documentation Updates..38
13.4 Support Resources................................................. 38
13.5 Trademarks.............................................................38
13.6 Electrostatic Discharge Caution..............................38
13.7 Glossary..................................................................38
14 Mechanical, Packaging, and Orderable
Information.................................................................... 38
14.1 Tape and Reel Information......................................39
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
DATE
REVISION
NOTES
November 2021
*
Initial release
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SLVSGK4 – NOVEMBER 2021
5 Device Comparison Table
Quick Output
Discharge
Reverse Current
Blocking
Device
Package (Pin)
Body Size
Pin Pitch
TPS22954-Q1
TPS22953-Q1
Yes
No
No
DQC (10)
DQC (10)
2.00 mm × 3.00 mm
2.00 mm × 3.00 mm
0.5 mm
0.5 mm
Yes
6 Pin Configuration and Functions
IN
IN
1
2
3
4
5
10 OUT
OUT 10
1
IN
IN
9
8
7
6
OUT
OUT
9
8
7
6
2
GND
(Exposed
thermal pad)
GND
(Exposed
thermal pad)
3
4
5
BIAS
EN
SNS
PG
SNS
PG
BIAS
EN
GND
CT
CT
GND
Figure 6-1. DQC/DSQ Package 10-Pin WSON Top
View
Figure 6-2. DQC/DSQ Package 10-Pin WSON
Bottom View
Table 6-1. Pin Functions
PIN(1)
NAME
I/O
DESCRIPTION
NO.
1
IN
I
Switch input. Bypass this input with a ceramic capacitor to GND.
2
3
BIAS
EN
I
I
Bias pin and power supply to the device
Active high switch to enable and disable the output. Also acts as the input UVLO pin. Use external resistor
divider to adjust the UVLO level. Do not leave floating.
4
5
6
GND
CT
—
O
Device ground
VOUT slew rate control. Place ceramic cap from CT to GND to change the VOUT slew rate of the device
and limit the inrush current. Rate the CT Capacitor to 25 V or higher.
Power Good. This pin is open drain which pulls low when the voltage on EN or SNS is below their
respective VIL levels.
7
PG
O
I
8
9
SNS
Sense pin. Use external resistor divider to adjust the power good level. Do not leave floating.
OUT
O
Switch output
10
—
Thermal Pad
—
Exposed thermal pad. Tie to GND.
(1) Pinout applies to all package versions.
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7 Specifications
7.1 Absolute Maximum Ratings
Over operating free-air temperature range (unless otherwise noted)(1)
MIN
–0.3
–0.3
–0.3
–0.3
MAX
UNIT
V
VIN
Input voltage
6
6
6
6
5
7
VBIAS
Bias voltage
V
VOUT
Output voltage
V
VEN, VSNS, VPG
EN, SNS, and PG voltage
V
IMAX
IPLS
TJ
Maximum continuous switch current, TA = 70°C
Maximum pulsed switch current, pulse < 300-µs, 2% duty cycle
Maximum junction temperature
Storage temperature
A
A
Internally Limited
–65
Tstg
150
°C
(1) Operation outside the Absolute Maximum Ratings may cause permanent device damage. Absolute Maximum Ratings do not imply
functional operation of the device at these or any other conditions beyond those listed under Recommended Operating Conditions.
If used outside the Recommended Operating Conditions but within the Absolute Maximum Ratings, the device may not be fully
functional, and this may affect device reliability, functionality, performance, and shorten the device lifetime.
7.2 ESD Ratings
VALUE
UNIT
Human body model (HBM), per AEC Q100- 002(1)
HBM ESD classification level 2
±2000
V(ESD)
Electrostatic discharge
V
Charged device model (CDM), per AEC Q100- 011
CDM ESD classification level C5
±750
(1) AEC Q100-002 indicates that HBM stressing shall be in accordance with the ANSI/ESDA/JEDEC JS-001 specification.
Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
MIN
0.7
2.5
0.9
0
MAX
VBIAS
5.7
UNIT
VIN
Input voltage
V
V
VBIAS
Bias voltage
VOUT
Output voltage
5.7
V
VEN, VSNS, VPG
EN, SNS, and PG voltage
Operating free-air temperature
Operating junction temperature
5.7
V
TA
TJ
–40
–40
125
150
°C
°C
7.3 Thermal Information
TPS2295x-Q1
THERMAL METRIC (1)
DQC (WSON)
UNIT
10 PINS
65.2
73.9
25.5
2
RθJA
RθJC(top)
RθJB
ψJT
Junction-to-ambient thermal resistance
Junction-to-case (top) thermal resistance
Junction-to-board thermal resistance
°C/W
°C/W
°C/W
°C/W
°C/W
Junction-to-top characterization parameter
Junction-to-board characterization parameter
ψJB
25.4
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
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SLVSGK4 – NOVEMBER 2021
7.4 Electrical Characteristics
Unless otherwise noted, the specification in the following table applies over the operating ambient temperature –40 °C ≤ TA ≤
+125 °C and the recommended VBIAS voltage range of 2.5 V to 5.7 V. Typical values are for TA = 25°C.
PARAMETER
TEST CONDITIONS
VIN = 0.7V to VBIAS
TA
MIN
650
560
465
410
TYP
700
600
515
455
MAX UNIT
VIH, Rising threshold
VIL, Falling threshold
VIH, Rising threshold
VIL, Falling threshold
–40°C to +125°C
–40°C to +125°C
–40°C to +125°C
–40°C to +125°C
750
640
565
500
mV
mV
mV
mV
VEN
VIN = 0.7V to VBIAS
VIN = 0.7V to VBIAS
VIN = 0.7V to VBIAS
VSNS
Blanking time for EN and
SNS
tBLANK
EN or SNS rising
EN or SNS falling
–40°C to +125°C
–40°C to +125°C
100
5
µs
µs
Deglitch time for EN and
SNS
tDEGLITCH
Output discharge time
(TPS22954 only)
tDIS
CL = 100µF
SNS falling
–40°C to +125°C
–40°C to +125°C
10
ms
ms
tRESTART
Output restart time
2
Response time for
reverse current blocking
(TPS22953 only)
VOUT = VBIAS
EN falling
tRCB
–40°C to +125°C
10
µs
TSD
Thermal shutdown
Junction temperature rising
Junction temperature falling
-
-
130
150
20
170
°C
°C
Thermal shutdown
hysteresis
TSDHYS
25°C
0.01
2
5
mΩ
mΩ
mΩ
Input reverse blocking
current (TPS22953 only)
VOUT = 5V, VIN = VEN = 0V,
VBIAS = 0V to 5.7V
IRCB,IN
–40°C to +85°C
–40°C to +125°C
11
7.5 Electrical Characteristics – VBIAS = 5 V
Unless otherwise noted, the specification in the following table applies over the operating ambient temperature –40 °C ≤ TA ≤
+125 °C and VBIAS = 5 V. Typical values are for TA = 25°C.
PARAMETER
TEST CONDITIONS
TA
MIN
TYP
MAX UNIT
–40°C to +85°C
–40°C to +125°C
–40°C to +85°C
–40°C to +125°C
–40°C to +85°C
–40°C to +125°C
–40°C to +85°C
–40°C to +125°C
–40°C to +85°C
–40°C to +125°C
–40°C to +85°C
–40°C to +125°C
–40°C to +85°C
–40°C to +125°C
–40°C to +125°C
–40°C to +125°C
34
45
µA
50
IQ, BIAS
BIAS quiescent current
IOUT = 0, VIN = 0.7 V to VBIAS, VEN = 5 V
5
0.02
0.01
0.01
0.01
0.01
7
ISD,BIAS
BIAS shutdown current
VOUT = 0 V, VIN = 0.7 V to VBIAS, VEN = 0 V to VIL
µA
8
4
13
3
VIN = 5 V
VIN = 3.3 V
10
3
µA
10
VEN = 0 V to VIL, VOUT
VIN = 1.8 V
ISD, IN
Input shutdown current
= 0 V
2
8
2
8
VIN = 1.2 V
VIN = 0.7 V
IEN
EN pin leakage current
SNS pin leakage current
VEN = 0 V to 5.7 V
VSNS ≤ VBIAS
0.1
0.1
µA
µA
ISNS
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7.5 Electrical Characteristics – VBIAS = 5 V (continued)
Unless otherwise noted, the specification in the following table applies over the operating ambient temperature –40 °C ≤ TA ≤
+125 °C and VBIAS = 5 V. Typical values are for TA = 25°C.
PARAMETER
TEST CONDITIONS
TA
MIN
TYP
MAX UNIT
25°C
14
20
23
24
20
23
24
20
23
VIN = 5 V
–40°C to +85°C
–40°C to +125°C
25°C
14
14
14
14
14
15
VIN = 3.3 V
VIN = 1.8 V
–40°C to +85°C
–40°C to +125°C
25°C
–40°C to +85°C
–40°C to +125°C
25°C
24
RON
ON-resistance
IOUT = –200 mA
mΩ
20
VIN = 1.5 V
VIN = 1.2 V
VIN = 0.7 V
–40°C to +85°C
–40°C to +125°C
25°C
23
24
20
23
24
20
23
24
–40°C to +85°C
–40°C to +125°C
25°C
–40°C to +85°C
–40°C to +125°C
25°C
Output pull down
resistance (TPS22954
only)
28
30
Ω
Ω
RPD
VIN = VOUT = VBIAS, VEN = 0 V
–40°C to +125°C
7.6 Electrical Characteristics – VBIAS = 3.3 V
Unless otherwise noted, the specification in the following table applies over the operating ambient temperature –40 °C ≤ TA ≤
+125 °C and VBIAS = 3.3 V. Typical values are for TA = 25°C.
PARAMETER
TEST CONDITIONS
TA
MIN
TYP
MAX UNIT
–40°C to +85°C
–40°C to +125°C
–40°C to +85°C
–40°C to +125°C
–40°C to +85°C
–40°C to +125°C
–40°C to +85°C
–40°C to +125°C
–40°C to +85°C
–40°C to +125°C
–40°C to +85°C
–40°C to +125°C
–40°C to +125°C
–40°C to +125°C
19
35
µA
37
IQ, BIAS
BIAS quiescent current
IOUT = 0, VIN = 0.7 V to VBIAS, VEN = 3.3 V
4
0.01
0.01
0.01
0.01
6
ISD,BIAS
BIAS shutdown current
Input shutdown current
VOUT = 0 V, VIN = 0.7 V to VBIAS, VEN = 0 V to VIL
µA
7
3
10
3
VIN = 3.3 V
VIN = 1.8 V
VEN = 0 V to VIL, VOUT
= 0 V
10
µA
2
ISD, IN
VIN = 1.2 V
8
2
8
VIN = 0.7 V
IEN
EN pin leakage current
SNS pin leakage current
VEN = 0 V to 5.7 V
VSNS ≤ VBIAS
0.1
0.1
µA
µA
ISNS
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7.6 Electrical Characteristics – VBIAS = 3.3 V (continued)
Unless otherwise noted, the specification in the following table applies over the operating ambient temperature –40 °C ≤ TA ≤
+125 °C and VBIAS = 3.3 V. Typical values are for TA = 25°C.
PARAMETER
TEST CONDITIONS
TA
MIN
TYP
MAX UNIT
25°C
15
21
24
25
20
23
24
20
VIN = 3.3 V
–40°C to +85°C
–40°C to +125°C
25°C
14
14
14
14
13
VIN = 1.8 V
–40°C to +85°C
–40°C to +125°C
25°C
RON
ON-resistance
IOUT = –200 mA
VIN = 1.5 V
VIN = 1.2 V
VIN = 0.7 V
–40°C to +85°C
–40°C to +125°C
25°C
23
24
20
23
24
20
23
24
28
mΩ
–40°C to +85°C
–40°C to +125°C
25°C
–40°C to +85°C
–40°C to +125°C
25°C
Output pull down
resistance (TPS22954
only)
Ω
Ω
RPD
VIN = VOUT = VBIAS, VEN = 0 V
–40°C to +125°C
30
7.7 Electrical Characteristics – VBIAS = 2.5 V
Unless otherwise noted, the specification in the following table applies over the operating ambient temperature –40 °C ≤ TA ≤
+125 °C and VBIAS = 2.5 V. Typical values are for TA = 25°C.
PARAMETER
TEST CONDITIONS
TA
MIN
TYP
MAX UNIT
–40°C to +85°C
–40°C to +125°C
–40°C to +85°C
–40°C to +125°C
–40°C to +85°C
–40°C to +125°C
–40°C to +85°C
–40°C to +125°C
–40°C to +85°C
–40°C to +125°C
–40°C to +85°C
–40°C to +125°C
–40°C to +125°C
–40°C to +125°C
16
25
µA
27
IQ, BIAS
BIAS quiescent current
IOUT = 0, VIN = 0.7 V to VBIAS, VEN = 2.5 V
4
0.01
0.01
0.01
0.01
5
ISD,BIAS
BIAS shutdown current
Input shutdown current
VOUT = 0 V, VIN = 0.7 V to VBIAS, VEN = 0 V to VIL
µA
6
3
10
3
VIN = 2.5 V
VIN = 1.8 V
VEN = 0 V to VIL, VOUT
= 0 V
10
µA
2
ISD, IN
VIN = 1.2 V
8
2
8
VIN = 0.7 V
IEN
EN pin leakage current
SNS pin leakage current
VEN = 0 V to 5.7V
VSNS ≤ VBIAS
0.1
0.1
µA
µA
ISNS
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7.7 Electrical Characteristics – VBIAS = 2.5 V (continued)
Unless otherwise noted, the specification in the following table applies over the operating ambient temperature –40 °C ≤ TA ≤
+125 °C and VBIAS = 2.5 V. Typical values are for TA = 25°C.
PARAMETER
TEST CONDITIONS
TA
MIN
TYP
MAX UNIT
25°C
16
23
26
27
22
25
26
22
VIN = 2.5 V
–40°C to +85°C
–40°C to +125°C
25°C
15
15
15
14
12
VIN = 1.8 V
–40°C to +85°C
–40°C to +125°C
25°C
RON
ON-resistance
IOUT = –200 mA
VIN = 1.5 V
VIN = 1.2 V
VIN = 0.7 V
–40°C to +85°C
–40°C to +125°C
25°C
25
26
22
24
25
21
24
25
28
mΩ
–40°C to +85°C
–40°C to +125°C
25°C
–40°C to +85°C
–40°C to +125°C
25°C
Output pull down
resistance (TPS22954
only)
Ω
Ω
RPD
VIN = VOUT = VBIAS, VEN = 0 V
–40°C to +125°C
30
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7.8 Switching Characteristics – CT = 1000 pF
All typical values are at 25°C unless otherwise noted
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
VIN = 5 V, VEN = VBIAS = 2.5 V, TA = 25°C
tON
tOFF
tR
Turn-On time
Turn-Off time
VOUT Rise time
VOUT Fall time
Delay time
RL = 10 Ω, CL = 0.1 µF, CT = 1000 pF
RL = 10 Ω, CL = 0.1 µF, CT = 1000 pF
RL = 10 Ω, CL = 0.1 µF, CT = 1000 pF
RL = 10 Ω, CL = 0.1 µF, CT = 1000 pF
RL = 10 Ω, CL = 0.1 µF, CT = 1000 pF
1265
6
µs
µs
µs
µs
µs
1492
2.2
tF
tD
519
VIN = 2.5 V, VEN = VBIAS = 5 V, TA = 25°C
tON
tOFF
tR
Turn-On time
Turn-Off time
VOUT Rise time
VOUT Fall time
Delay time
RL = 10 Ω, CL = 0.1 µF, CT = 1000 pF
RL = 10 Ω, CL = 0.1 µF, CT = 1000 pF
RL = 10 Ω, CL = 0.1 µF, CT = 1000 pF
RL = 10 Ω, CL = 0.1 µF, CT = 1000 pF
RL = 10 Ω, CL = 0.1 µF, CT = 1000 pF
813
6.1
µs
µs
µs
µs
µs
765
2.2
tF
tD
430
VIN = 0.7 V, VEN = 5 V, VBIAS = 5 V, TA = 25°C
tON
tOFF
tR
Turn-On time
Turn-Off time
VOUT Rise time
VOUT Fall time
Delay time
RL = 10 Ω, CL = 0.1 µF, CT = 1000 pF
RL = 10 Ω, CL = 0.1 µF, CT = 1000 pF
RL = 10 Ω, CL = 0.1 µF, CT = 1000 pF
RL = 10 Ω, CL = 0.1 µF, CT = 1000 pF
RL = 10 Ω, CL = 0.1 µF, CT = 1000 pF
476
6.2
µs
µs
µs
µs
µs
245
2.1
tF
tD
353
VIN = 2.5 V, VEN = 5 V, VBIAS = 2.5 V, TA = 25°C
tON
tOFF
tR
Turn-On time
Turn-Off time
VOUT Rise time
VOUT Fall time
Delay time
RL = 10 Ω, CL = 0.1 µF, CT = 1000 pF
RL = 10 Ω, CL = 0.1 µF, CT = 1000 pF
RL = 10 Ω, CL = 0.1 µF, CT = 1000 pF
RL = 10 Ω, CL = 0.1 µF, CT = 1000 pF
RL = 10 Ω, CL = 0.1 µF, CT = 1000 pF
813
4.9
µs
µs
µs
µs
µs
765
2.2
tF
tD
430
VIN = 0.7 V, VEN = 5 V, VBIAS = 2.5 V, TA = 25°C
tON
tOFF
tR
Turn-On time
Turn-Off time
VOUT Rise time
VOUT Fall time
Delay time
RL = 10 Ω, CL = 0.1 µF, CT = 1000 pF
RL = 10 Ω, CL = 0.1 µF, CT = 1000 pF
RL = 10 Ω, CL = 0.1 µF, CT = 1000 pF
RL = 10 Ω, CL = 0.1 µF, CT = 1000 pF
RL = 10 Ω, CL = 0.1 µF, CT = 1000 pF
476
6.1
µs
µs
µs
µs
µs
245
2.1
tF
tD
353
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UNIT
SLVSGK4 – NOVEMBER 2021
7.9 Switching Characteristics – CT = 0 pF
All typical values are at 25°C unless otherwise noted
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
VIN = 5 V, VEN = VBIAS = 2.5 V, TA = 25°C
tON
tOFF
tR
Turn-On time
Turn-Off time
VOUT Rise time
VOUT Fall time
Delay time
RL = 10 Ω, CL = 0.1 µF, CT = 0 pF
RL = 10 Ω, CL = 0.1 µF, CT = 0 pF
RL = 10 Ω, CL = 0.1 µF, CT = 0 pF
RL = 10 Ω, CL = 0.1 µF, CT = 0 pF
RL = 10 Ω, CL = 0.1 µF, CT = 0 pF
235
6
µs
µs
µs
µs
µs
140
2.2
165
tF
tD
VIN = 2.5 V, VEN = VBIAS = 5 V, TA = 25°C
tON
tOFF
tR
Turn-On time
Turn-Off time
VOUT Rise time
VOUT Fall time
Delay time
RL = 10 Ω, CL = 0.1 µF, CT = 0 pF
RL = 10 Ω, CL = 0.1 µF, CT = 0 pF
RL = 10 Ω, CL = 0.1 µF, CT = 0 pF
RL = 10 Ω, CL = 0.1 µF, CT = 0 pF
RL = 10 Ω, CL = 0.1 µF, CT = 0 pF
200
6
µs
µs
µs
µs
µs
79
tF
2.1
160
tD
VIN = 0.7 V, VEN = 5 V, VBIAS = 5 V, TA = 25°C
tON
tOFF
tR
Turn-On time
Turn-Off time
VOUT Rise time
VOUT Fall time
Delay time
RL = 10 Ω, CL = 0.1 µF, CT = 0 pF
RL = 10 Ω, CL = 0.1 µF, CT = 0 pF
RL = 10 Ω, CL = 0.1 µF, CT = 0 pF
RL = 10 Ω, CL = 0.1 µF, CT = 0 pF
RL = 10 Ω, CL = 0.1 µF, CT = 0 pF
170
6
µs
µs
µs
µs
µs
32
2
tF
tD
154
VIN = 2.5 V, VEN = 5 V, VBIAS = 2.5 V, TA = 25°C
tON
tOFF
tR
Turn-On time
Turn-Off time
VOUT Rise time
VOUT Fall time
Delay time
RL = 10 Ω, CL = 0.1 µF, CT = 0 pF
RL = 10 Ω, CL = 0.1 µF, CT = 0 pF
RL = 10 Ω, CL = 0.1 µF, CT = 0 pF
RL = 10 Ω, CL = 0.1 µF, CT = 0 pF
RL = 10 Ω, CL = 0.1 µF, CT = 0 pF
200
6
µs
µs
µs
µs
µs
79
tF
2.1
160
tD
VIN = 0.7 V, VEN = 5 V, VBIAS = 2.5 V, TA = 25°C
tON
tOFF
tR
Turn-On time
Turn-Off time
VOUT Rise time
VOUT Fall time
Delay time
RL = 10 Ω, CL = 0.1 µF, CT = 0 pF
RL = 10 Ω, CL = 0.1 µF, CT = 0 pF
RL = 10 Ω, CL = 0.1 µF, CT = 0 pF
RL = 10 Ω, CL = 0.1 µF, CT = 0 pF
RL = 10 Ω, CL = 0.1 µF, CT = 0 pF
170
6
µs
µs
µs
µs
µs
32
2
tF
tD
154
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SLVSGK4 – NOVEMBER 2021
7.10 Typical DC Characteristics
40
36
35
34
33
32
31
30
29
28
27
26
25
24
105°C
85°C
25°C
35
30
25
20
15
10
-40°C
105°C
85°C
25°C
-40°C
2.5
3
3.5
4
4.5
5
5.5
6
D001
0.5
1
1.5
2
2.5
VIN (V)
3
3.5
4
4.5
5
VBIAS (V)
D002
VIN = 1.8 V
VEN = 5.7 V
VOUT = 0 V
VBIAS = 5 V
VEN = 5.7 V
VOUT = 0 V
Figure 7-1. IQ,BIAS vs VBIAS
Figure 7-2. IQ,BIAS vs VIN
6
5.5
5
2.5
2.25
2
105°C
105°C
85°C
25°C
-40°C
85°C
25°C
-40°C
1.75
1.5
1.25
1
4.5
4
0.75
0.5
0.25
0
3.5
-0.25
-0.5
0.5
3
2.5
1
1.5
2
2.5
VIN (V)
3
3.5
4
4.5
5
D004
3
3.5
4
4.5
5
5.5
6
D003
VBIAS (V)
VBIAS = 5 V
VEN = 0 V
VOUT = 0 V
VIN = 1.8 V
VEN = 0 V
VOUT = 0 V
Figure 7-4. ISD,IN vs VIN
Figure 7-3. ISD,BIAS vs VBIAS
0.01
0.009
0.008
0.007
0.006
0.005
0.004
0.003
0.002
0.001
0
2.4
2.2
2
25°C
-40°C
105°C
85°C
25°C
-40°C
1.8
1.6
1.4
1.2
1
0.8
0.6
0.4
0.2
0
0.5
1
1.5
2
2.5
3 3.5
VOUT (V)
4
4.5
5
5.5
6
0.5
1
1.5
2
2.5
3 3.5
VOUT (V)
4
4.5
5
5.5
6
D036
D035
VBIAS = 0 V to 5.7 V
VEN = 0 V
VIN = 0 V
VBIAS = 0 V to 5.7 V
VEN = 0 V
VIN = 0 V
Figure 7-6. IRCB,IN vs VOUT
Figure 7-5. IRCB,IN vs VOUT
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7.10 Typical DC Characteristics (continued)
22
19
18
17
16
15
14
13
12
11
10
VIN = 2.5V
VIN = 1.8V
VIN = 0.7V
VIN = 3.3V
VIN = 2.5V
VIN = 1.8V
VIN = 0.7V
20
18
16
14
12
10
-40
-20
0
20
40
60
80
100
120
-40
-20
0
20
40
60
80
100
120
Ambient Temperature (èC)
Ambient Temperature (èC)
D005
D006
VBIAS = 2.5 V
Iout = –200 mA
VEN = 5 V
VBIAS = 3.3 V
Iout = –200 mA
VEN = 5 V
Figure 7-7. RON vs Temperature, VBIAS = 2.5 V
Figure 7-8. RON vs Temperature, VBIAS = 3.3 V
24
22
20
18
16
14
12
10
22
20
18
16
14
12
10
105°C
85°C
25°C
-40°C
105°C
85°C
25°C
-40°C
0.6 0.8
1
1.2 1.4 1.6 1.8
VIN (V)
2
2.2 2.4 2.6
0.6 0.8 1 1.2 1.4 1.6 1.8 2 2.2 2.4 2.6 2.8 3 3.2 3.4
VIN (V)
D008
D009
VBIAS = 2.5 V
Iout = –200 mA
VEN = 5 V
VBIAS = 3.3 V
Iout = –200 mA
VEN = 5 V
Figure 7-9. RON vs VIN, VBIAS = 2.5 V
Figure 7-10. RON vs VIN, VBIAS = 3.3 V
22
20
18
16
14
12
10
16
VBIAS = 2.5V
VBIAS = 3.3V
VBIAS = 5V
105°C
85°C
25°C
-40°C
15.75
15.5
15.25
15
VBIAS = 5.7V
14.75
14.5
14.25
14
13.75
13.5
13.25
0.5
1
1.5
2
2.5
3 3.5
VIN (V)
4
4.5
5
5.5
6
0.6
1
1.4 1.8 2.2 2.6
3
VIN (V)
3.4 3.8 4.2 4.6
5
D011
D010
TA = 25°C
Iout = –200 mA
VEN = 5 V
VBIAS = 5 V
Iout = –200 mA
VEN = 5 V
Figure 7-12. RON vs VIN
Figure 7-11. RON vs VIN, VBIAS = 5 V
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SLVSGK4 – NOVEMBER 2021
7.10 Typical DC Characteristics (continued)
17.5
15.4
15.2
15
VIN = 2.5V
VIN = 1.8V
VIN = 0.7V
VIN = 3.3V
VIN = 2.5V
VIN = 1.8V
VIN = 0.7V
17
16.5
16
14.8
14.6
14.4
14.2
14
15.5
15
13.8
13.6
13.4
13.2
14.5
14
13.5
0
0.5
1
1.5
2
2.5
IOUT (A)
3
3.5
4
4.5
5
0
0.5
1
1.5
2
2.5
IOUT (A)
3
3.5
4
4.5
5
D032
D033
VBIAS = 2.5 V
VEN = 5 V
VBIAS = 3.3 V
VEN = 5 V
Figure 7-13. RON vs IOUT, VBIAS = 2.5 V
Figure 7-14. RON vs IOUT, VBIAS = 3.3 V
14.3
14.2
14.1
14
22
20
18
16
14
12
10
8
VIN = 5V
105°C
25°C
-40°C
VIN = 3.3V
VIN = 2.5V
VIN = 1.8V
VIN = 0.7V
13.9
13.8
13.7
13.6
13.5
13.4
13.3
13.2
6
4
2
0
0.5
1
1.5
2
2.5
IOUT (A)
3
3.5
4
4.5
5
0.6 0.8
1
1.2 1.4 1.6 1.8
VOUT (V)
2
2.2 2.4 2.6
D034
D012
VBIAS = 5 V
VEN = 5 V
VBIAS = 2.5 V
VIN = VOUT
VEN = 0 V
Figure 7-15. RON vs IOUT, VBIAS = 5 V
Figure 7-16. RPD vs VOUT, VBIAS = 2.5 V
18
16
14
12
10
8
18
16
14
12
10
8
105°C
25°C
-40°C
105°C
25°C
-40°C
6
6
4
4
2
2
0.6
0.9
1.2
1.5
1.8 2.1
VOUT (V)
2.4
2.7
3
3.3
0.5
1
1.5
2
2.5
VOUT (V)
3
3.5
4
4.5
5
D016
D014
VBIAS = 3.3 V
VIN = VOUT
VEN = 0 V
VBIAS = 5 V
VIN = VOUT
VEN = 0 V
Figure 7-17. RPD vs VOUT, VBIAS = 3.3 V
Figure 7-18. RPD vs VOUT, VBIAS = 5 V
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7.11 Typical Switching Characteristics
800
1600
1400
1200
1000
800
105°C
85°C
25°C
-40°C
105°C
85°C
25°C
-40°C
750
700
650
600
550
500
450
400
350
300
250
200
600
400
200
0.5
1
1.5
2
2.5
VIN (V)
3
3.5
4
4.5
5
0.6 0.8
1
1.2 1.4 1.6 1.8
VIN (V)
2
2.2 2.4 2.6
D021
D020
VBIAS = 5 V
CT = 1000 pF VEN = Low to High
VBIAS = 2.5 V
CT = 1000 pF VEN = Low to High
Figure 7-20. tR vs VIN, VBIAS = 5 V
Figure 7-19. tR vs VIN, VBIAS = 2.5 V
2.2
2.18
2.16
2.14
2.12
2.1
2.25
2.22
2.19
2.16
2.13
2.1
105°C
85°C
25°C
-40°C
2.08
2.06
2.04
2.02
2.07
2.04
2.01
1.98
105°C
85°C
25°C
-40°C
0.6 0.8
1
1.2 1.4 1.6 1.8
VIN (V)
2
2.2 2.4 2.6
0.5
1
1.5
2
2.5
VIN (V)
3
3.5
4
4.5
5
D022
D023
VBIAS = 2.5 V
CT = 1000 pF VEN = High to Low
VBIAS = 5 V
CT = 1000 pF VEN = High to Low
Figure 7-21. tF vs VIN, VBIAS = 2.5 V
Figure 7-22. tF vs VIN, VBIAS = 5 V
900
850
800
750
700
650
600
550
500
450
400
1400
1300
1200
1100
1000
900
105°C
85°C
25°C
-40°C
105°C
85°C
25°C
-40°C
800
700
600
500
400
0.5
1
1.5
2
2.5
3
3.5
4
4.5
5
0.6 0.8
1
1.2 1.4 1.6 1.8
VIN (V)
2
2.2 2.4 2.6
VIN (V)
D025
D024
VBIAS = 5 V
CT = 1000 pF VEN = Low to High
VBIAS = 2.5 V
CT = 1000 pF VEN = Low to High
Figure 7-24. tON vs VIN, VBIAS = 5 V
Figure 7-23. tON vs VIN, VBIAS = 2.5 V
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SLVSGK4 – NOVEMBER 2021
7.11 Typical Switching Characteristics
7.25
7
6.4
6.35
6.3
105°C
85°C
25°C
-40°C
105°C
85°C
25°C
-40°C
6.75
6.5
6.25
6
6.25
6.2
6.15
6.1
5.75
5.5
5.25
5
6.05
6
4.75
5.95
0.6 0.8
1
1.2 1.4 1.6 1.8
VIN (V)
2
2.2 2.4 2.6
0.5
1
1.5
2
2.5
VIN (V)
3
3.5
4
4.5
5
D02351
D027
VBIAS = 2.5 V
CT = 1000 pF VEN = High to Low
VBIAS = 5 V
CT = 1000 pF VEN = High to Low
Figure 7-25. tOFF vs VIN, VBIAS = 2.5 V
Figure 7-26. tOFF vs VIN, VBIAS = 5 V
480
460
440
420
400
380
360
340
320
300
280
570
540
510
480
450
420
390
360
330
300
270
105°C
85°C
25°C
-40°C
105°C
85°C
25°C
-40°C
0.6 0.8
1
1.2 1.4 1.6 1.8
VIN (V)
2
2.2 2.4 2.6
0.5
1
1.5
2
2.5
VIN (V)
3
3.5
4
4.5
5
D028
D029
VBIAS = 2.5 V
CT = 1000 pF VEN = Low to High
VBIAS = 5 V
CT = 1000 pF
VEN =Low to High
Figure 7-27. tD vs VIN, VBIAS = 2.5 V
Figure 7-28. tD vs VIN, VBIAS= 5 V
810
800
790
780
770
760
750
740
730
720
710
700
690
105°C
85°C
25°C
-40°C
2.5
3
3.5
4
4.5
5
5.5
6
VBIAS (V)
D030
VIN = 2.5 V CT = 1000 pF
Figure 7-29. tR vs VBIAS
VEN = Low to High
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7.11 Typical Switching Characteristics (continued)
VIN = 0.7 V
CIN = 1 µF
VBIAS = 2.5 V
CL = 0.1 µF
CT = 1000 pF
RL = 10 Ω
VIN = 0.7 V
CIN = 1 µF
VBIAS = 2.5 V
CL = 0.1 µF
CT = 1000 pF
RL = 10 Ω
Figure 7-30. Turn-on Waveform, VBIAS = 2.5 V
Figure 7-31. Turn-off Waveform, VBIAS = 2.5 V
VIN = 0.7 V
CIN = 1 µF
VBIAS = 5 V
CL = 0.1 µF
CT = 1000 pF
RL = 10 Ω
VIN = 0.7 V
CIN = 1 µF
VBIAS = 5 V
CL = 0.1 µF
CT = 1000 pF
RL = 10 Ω
Figure 7-32. Turn-on Waveform, VBIAS = 5 V
Figure 7-33. Turn-off Waveform, VBIAS = 5 V
VIN = 2.5 V
CIN = 1 µF
VBIAS = 2.5 V
CL = 0.1 µF
CT = 1000 pF
RL = 10 Ω
VIN = 2.5 V
CIN = 1 µF
VBIAS = 2.5 V
CL = 0.1 µF
CT = 1000 pF
RL = 10 Ω
Figure 7-34. Turn-on Waveform, VBIAS = 2.5 V
Figure 7-35. Turn-off Waveform, VBIAS = 2.5 V
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SLVSGK4 – NOVEMBER 2021
7.11 Typical Switching Characteristics (continued)
VIN = 2.5 V
CIN = 1 µF
VBIAS = 5 V
CL = 0.1 µF
CT = 1000 pF
RL = 10 Ω
VIN = 2.5 V
CIN = 1 µF
VBIAS = 5 V
CL = 0.1 µF
CT = 1000 pF
RL = 10 Ω
Figure 7-36. Turn-on Waveform, VBIAS = 5 V
Figure 7-37. Turn-off Waveform, VBIAS = 5 V
VIN = 3.3 V
CIN = 1 µF
VBIAS = 5 V
CL = 0.1 µF
CT = 1000 pF
RL = 10 Ω
VIN = 3.3 V
CIN = 1 µF
VBIAS = 5 V
CL = 0.1 µF
CT = 1000 pF
RL = 10 Ω
Figure 7-38. Turn-on Waveform, VBIAS = 5 V
Figure 7-39. Turn-off Waveform, VBIAS = 5 V
VIN = 5 V
VBIAS = 5 V
CL = 0.1 µF
CT = 1000 pF
RL = 10 Ω
VIN = 5 V
VBIAS = 5 V
CL = 0.1 µF
CT = 1000 pF
RL = 10 Ω
CIN = 1 µF
CIN = 1 µF
Figure 7-40. Turn-on Waveform, VBIAS = 5 V
Figure 7-41. Turn-off Waveform, VBIAS = 5 V
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7.11 Typical Switching Characteristics (continued)
VIN = 3.3 V
CIN = 1 µF
VBIAS = 5 V
CL = 0.1 µF
CT = 1000 pF
RL = Open
VIN = 5 V
VBIAS = 5 V
CL = 0.1 µF
CT = 1000 pF
RL = Open
CIN = 1 µF
Figure 7-42. Turn-on Waveform, No Load
Figure 7-43. Turn-on Waveform, No Load
VIN = 3.3 V
CIN = 1 µF
VBIAS = 5 V
CL = 0.1 µF
CT = 1000 pF
RL = 1 Ω
VIN = 5 V
VBIAS = 5 V
CL = 0.1 µF
CT = 1000 pF
RL = 1 Ω
CIN = 1 µF
Figure 7-44. Turn-on Waveform, Heavy Load
Figure 7-45. Turn-on Waveform, Heavy Load
VIN = 5 V
VBIAS = 5 V
CL = 100 µF
CT = 1000 pF
RL = 10 Ω
VIN = 5 V
VBIAS = 5 V
CL = 100 µF
CT = 1000 pF
RL = 10 Ω
CIN = 1 µF
CIN = 1 µF
Figure 7-46. PG Response to EN Falling (tDEGLITCH
)
Figure 7-47. PG Response to SNS Falling With Auto-Restart
(tDEGLITCH and tRESTART
)
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SLVSGK4 – NOVEMBER 2021
7.11 Typical Switching Characteristics (continued)
VIN = 5 V
VBIAS = 5 V
CL = 100 µF
CT = 1000 pF
RL = 10 Ω
VIN = 5 V
VBIAS = 5 V
CL = 100 µF
CT = 1000 pF
RL = None
CIN = 1 µF
CIN = 1 µF
Figure 7-48. PG Response to SNS Rising (tBLANK
)
Figure 7-49. Quick Output Discharge of 100-µF Load (tDIS
)
VIN = 10 Ω to GND
CIN = 0.2 µF
VBIAS = 5 V
VOUT = 5 V
Figure 7-50. Reverse Current Blocking Response Time (tRCB
)
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8 Parameter Measurement Information
A. Rise and fall times of the control signal is 100 ns.
Figure 8-1. Timing Test Circuit
tDEGLITCH
tDEGLITCH
VEN
50%
50%
50%
50%
tON
tOFF
90%
90%
tD
VOUT
50%
50%
10%
10%
tBLANK
tBLANK
tR
tF
Figure 8-2. Timing Waveforms
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9 Detailed Description
9.1 Overview
The TPS2295x-Q1 are 5.7-V, 5-A load switches in 10-pin SON packages. To reduce voltage drop for low
voltage, high current rails the device implements a low-resistance N-channel MOSFET, which reduces the drop
out voltage through the device at high currents. The integrated adjustable Undervoltage Lockout (UVLO) and
adjustable Power Good (PG) threshold provides voltage monitoring as well as robust power sequencing.
The adjustable rise time control of the device greatly reduces inrush current for a wide variety of bulk load
capacitances, thereby reducing or eliminating power supply droop. The switch is independently controlled by an
on and off input (EN), which is capable of interfacing directly with low-voltage control signals. A 15-Ω on-chip
load resistor integrates into the device for output quick discharge when the switch turns off.
During shutdown, the device has very low leakage currents, thereby reducing unnecessary leakages for
downstream modules during standby. Integrated power monitoring functionality, control logic, driver, power
supply, and output discharge FET eliminates the need for any external components, which reduces solution size
and BOM count.
9.2 Functional Block Diagram
Reverse Current
Blocking*
(TPS22953 Only)
IN
Power
supply
module
BIAS
PG
EN
Control
Logic
Driver
VEN
OUT
CT
Thermal
Shutdown
QOD Resistance*
(TPS22954 Only)
SNS
VSNS
GND
(*) Only active when the switch is disabled.
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9.3 Feature Description
9.3.1 On and Off Control (EN pin)
The EN pin controls the state of the switch. When the voltage on EN exceeds VIH,EN the switch enables. When
EN goes below VIL,EN the switch disables.
The EN pin has a blanking time of tBLANK on the rising edge once the VIH,EN threshold has been exceeded. The
EN pin also has a de-glitch time of tDEGLITCH when the voltage has gone below VIL,EN
.
The EN pin can also be configured through an external resistor divider to monitor a voltage signal for input
UVLO. See Equation 1 and Figure 9-1 on how to configure the EN pin for input UVLO.
REN2
V
= V ´
IN
IH,EN
R
EN1 + REN2
(1)
where
•
•
•
VIH,EN is the rising threshold of the EN pin (see the Electrical Characteristics table)
VIN is the input voltage being monitored (this could be VIN, VBIAS, or an external power supply)
REN1, REN2 are the resistor divider values
VIN or VBIAS
REN1
EN
REN2
Figure 9-1. Resistor Divider (EN Pin)
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9.3.2 Voltage Monitoring (SNS Pin)
The SNS pin of the device can be used to monitor the output voltage of the device or another voltage rail. The
pin can be configured with an external resistor divider to set the desired trip point for the voltage being monitored
or be tied to OUT directly. If the voltage on the SNS pin exceeds VIH,SNS, the voltage being monitored on the
SNS pin is considered to be valid high. The voltage on the SNS pin must be greater than VIH,SNS for at least
tBLANK before PG is asserted high. If the voltage on the SNS pin goes below VIL,SNS, then the switch powers
cycle (that is, the switch is disabled and re-enabled). For proper functionality of the device, this pin must not be
left floating. If a resistor divider is not being used for voltage sensing, this pin can be tied directly to VOUT
.
The SNS pin has a blanking time of tBLANK on the rising edge once the VIH,SNS threshold has been exceeded.
The SNS pin has a de-glitch time of tDEGLITCH when the voltage has gone below VIL,SNS
See Equation 2 and Figure 9-2 on how to configure the SNS pin for voltage monitoring.
.
RSNS2
V
= VOUT
´
IH,SNS
R
SNS1 + RSNS2
(2)
where
•
•
•
VIH,SNS is the the rising threshold of the SNS pin (see Electrical Characteristics table)
VOUT is the voltage on the OUTpin
RSNS1, RSNS2 are the resistor divider values
VOUT
RSNS1
SNS
RSNS2
Figure 9-2. Voltage Divdier (SNS Pin)
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9.3.3 Power Good (PG Pin)
The PG pin is only asserted high when the voltage on EN exceeds VIH,EN and the voltage on SNS exceeds
VIH,SNS. There is a tBLANK time, typically 100 µs, between the SNS voltage exceeding VIH,SNS and PG being
asserted high. If the voltage on EN goes below VIL,EN or the voltage on SNS goes below VIL,SNS, PG is
de-asserted. There is a tDEGLITCH time, typically 5µs, between the EN voltage or SNS voltage going below their
respective VIL levels and PG being pulled low.
PG is an open drain pin and must be pulled up with a pull-up resistor. Be sure to never exceed the maximum
operating voltage on this pin. If PG is not being used in the application, tie it to GND for proper device
functionality.
For proper PG operation, the BIAS voltage must be within the recommended operating range. In systems that
are very sensitive to noise or have long PG traces, TI recommends to add a small capacitance from PG to GND
for decoupling.
9.3.4 Supervisor Fault Detection and Automatic Restart
The falling edge of the SNS pin below VIL,SNS is considered a fault case and causes the load switch to be
disabled for tRESTART (typically 2 ms). After the tRESTART time, the switch is automatically re-enabled as long as
EN is still above VIH,EN. In the case the SNS pin is being used to monitor VOUT or a downstream voltage, the
restart helps to protect against excessive overcurrent if there is a quick short to GND. See Figure 9-3.
VIN
IN
0
VBIAS
BIAS
0
VEN
EN
tR
0
tD
VOUT
90%
Voltage
Pulled
Down
OUT
SNS
10%
0
tRESTART
VSNS
0
VIL,SNS
VIH,SNS
tBLANK
tDEGLITCH
VPG
0
PG
Time
Figure 9-3. Automatic Restart After Quick Short to GND
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9.3.5 Manual Restart
The falling edge of the SNS pin below VIL,SNS is considered a fault case and causes the load switch to be
disabled for tRESTART (typically 2 ms). The SNS pin can be driven by an MCU to manually reset the load switch.
After the tRESTART time, the switch is automatically re-enabled as long as EN is still above VIH,EN, even is SNS is
held low. The PG pin stays low until the switch is re-enabled and the SNS pin rises above VIH,SNS. See Figure
9-4.
VIN
IN
0
VBIAS
BIAS
0
VEN
EN
tR
0
tD
VOUT
90%
OUT
SNS
10%
0
tRESTART
VSNS
0
VIL,SNS
tDEGLITCH
VPG
0
PG
Time
Figure 9-4. Manual Restart (SNS Held Low)
If the SNS pin is brought above VIH,SNS within the tRESTART time, the switch still waits to re-enable. The PG pin
also stays low until tBLANK after switch is re-enabled. In this case, PG indicates when the switch is enabled and
capable of being reset again. See Figure 9-5.
VIN
IN
0
VBIAS
BIAS
0
VEN
EN
tR
0
tD
VOUT
90%
OUT
SNS
10%
0
tRESTART
VSNS
0
VIL,SNS
tBLANK
tDEGLITCH
VPG
PG
0
Time
Figure 9-5. Manual Restart (SNS Toggled Low to High)
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9.3.6 Thermal Shutdown
If the junction temperature of the device exceeds TSD, the switch disables. The device enables after the junction
temperature drops by TSDHYS as long as EN is still greater than VIH,EN
.
9.3.7 Reverse Current Blocking (TPS22953-Q1 Only)
When the switch disables (either by de-asserting EN or SNS, triggering thermal shutdown, or losing power),
the reverse current blocking (RCB) feature of the device engages within tRCB, typically 10 μs. After the RCB
engages, the reverse current from the OUT pin to the IN pin is limited to IRCB,IN, typically 0.01 μA.
9.3.8 Quick Output Discharge (QOD) (TPS22954-Q1 Only)
The Quick Output Discharge (QOD) transistor is engaged indefinitely whenever the switch is disabled and the
recommended VBIAS voltage is met. During this state, the QOD resistance (RPD) discharges VOUT to GND. TI
does not recommend to apply a continuous DC voltage to OUT when the device is disabled.
The QOD transistor can remain active for a short period of time even after VBIAS loses power. This brief period
of time is defined as tDIS. For best results, TI recommends the device get disabled before VBIAS goes below the
minimum recommended voltage. The waveform in Figure 9-6 shows the behavior when power is applied and
then removed in a typical application.
VIN
IN
0
VBIAS
BIAS
0
VEN
EN
VIH,EN
VIL,EN
0
tDEGLITCH
tBLANK
VOUT
OUT
VOUT < 100mV
0
tDIS
VSNS
VIH,SNS
tBLANK
VIL,SNS
tDEGLITCH
SNS
PG
0
VPG
0
Time
Figure 9-6. Power Applied and Then Removed in a Typical Application
At the end of the tDIS time, it is not guaranteed that VOUT will be 0 V because the final voltage is dependent upon
the initial voltage and the CL capacitor. The final VOUT can be calculated with Equation 3 for a given initial voltage
and CL capacitor.
-t
Vƒ = Vo ´ eRC
(3)
where
•
•
•
•
Vf is the final VOUT voltage
Vo is the initial VOUT voltage
R is the the value of the output discharge resistor, RPD (see the Electrical Characteristics table)
C is the output bulk capacitance on OUT
9.3.9 VIN and VBIAS Voltage Range
For optimal RON performance, make sure VIN ≤ VBIAS. The device is still functional if VIN > VBIAS but it exhibits
RON greater than what is listed in the Electrical Characteristics table. See Figure 9-7 for an example of a typical
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device. Notice the increasing RON as VIN increases. Be sure to never exceed the maximum voltage rating for VIN
and VBIAS
.
55
50
45
40
35
30
25
20
15
10
VBIAS = 2.5V
VBIAS = 3.3V
VBIAS = 5V
VBIAS = 5.7V
0.5
1
1.5
2
2.5
3 3.5
VIN (V)
4
4.5
5
5.5
6
D031
Figure 9-7. RON When VIN > VBIAS
9.3.10 Adjustable Rise Time (CT Pin)
A capacitor to GND on the CT pin sets the slew rate for VOUT. An appropriate capacitance value must be placed
on CT such that the IMAX and IPLS specifications of the device are not violated. The capacitor to GND on the CT
pin must be rated for 25 V or higher. Equation 4 shows an approximate formula for the relationship between CT
(except for CT = open) and the slew rate for any VBIAS
.
SR = 0.35 × CT + 20
where
(4)
•
•
•
•
SR is the slew rate (in μs/V)
CT is the the capacitance value on the CT terminal (in pF)
The units for the constant 20 are μs/V.
The units for the constant 0.35 are μs/(V*pF).
Rise time can be calculated by multiplying the input voltage (typically 10% to 90%) by the slew rate. Table 9-1
contains rise time values measured on a typical device.
Table 9-1. Rise Time
RISE TIME (µs) 10%–90%, CL = 0.1 µF, VBIAS = 2.5 V to 5.7 V, RL = 10-Ω LOAD.
TYPICAL VALUES AT 25°C, 25 V X7R 10% CERAMIC CAP
CTx (pF)
5 V
140
3.3 V
98
1.8 V
62
1.5 V
54
1.2 V
46
0.7 V
32
Open
220
444
301
175
150
255
474
961
1980
4331
124
210
387
787
1612
3533
81
470
767
518
299
133
245
490
998
2197
1000
2200
4700
10000
1492
3105
6420
14059
994
562
2050
4246
9339
1151
2365
5183
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9.3.11 Power Sequencing
The TPS2295x-Q1 operates regardless of power-on and power-off sequencing order. The order in which
voltages are applied to IN, BIAS, and EN does not damage the device as long as the voltages do not exceed the
absolute maximum operating conditions. If voltage is applied to EN before IN and BIAS, the slew rate of VOUT is
not controlled. Also, turning off IN or BIAS while EN is high does not damage the device.
9.4 Device Functional Modes
Table 9-2 describes what the OUT pin is connected to for a particular device as determined by the EN pin.
Table 9-2. Function Table
EN
L
TPS22953-Q1
TPS22954-Q1
RPD to GND
IN
OPEN
IN
H
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10 Application and Implementation
Note
Information in the following applications sections is not part of the TI component specification,
and TI does not warrant its accuracy or completeness. TI’s customers are responsible for
determining suitability of components for their purposes, as well as validating and testing their design
implementation to confirm system functionality.
10.1 Application Information
This section highlights some of the design considerations when implementing this device in various applications.
A PSPICE model for this device is also available on www.ti.com for further aid.
10.1.1 Input to Output Voltage Drop
The input to output voltage drop in the device is determined by the RON of the device and the load current. The
RON of the device depends upon the VIN and VBIAS conditions of the device. Refer to the RON specification of the
device in the Electrical Characteristics table of this data sheet. After the RON of the device is determined based
upon the VIN and VBIAS voltage conditions, use Equation 5 to calculate the input to output voltage drop.
DV = ILOAD ´RON
(5)
where
•
•
•
ΔV is the voltage drop from IN to OUT
ILOAD is the load current
RON is the On-Resistance of the device for a specific VIN and VBIAS
An appropriate ILOAD must be chosen such that the IMAX specification of the device is not violated.
10.1.2 Thermal Considerations
The maximum IC junction temperature must be restricted to just under the thermal shutdown (TSD) limit of the
device. Use Equation 6 to calculate the maximum allowable dissipation, PD(max) for a given output current and
ambient temperature.
TJ(max) - TA
PD(max)
=
qJA
(6)
where
•
•
PD(max) is the maximum allowable power dissipation
TJ(max) is the maximum allowable junction temperature before hitting thermal shutdown (see the Electrical
Characteristics table)
•
•
TA is the ambient temperature of the device
θJA is the junction to air thermal impedance. See the thermal Information section. This parameter is highly
dependent upon board layout.
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10.1.3 Automatic Power Sequencing
The PG pin of the TPS2295x-Q1 allows for automatic sequencing of multiple system rails or loads. The accurate
SNS voltage monitoring ensures the first rail is up before the next starts to turn on. This approach provides
robust system sequencing and reduces the total inrush current by preventing overlap. Figure 10-1 shows how
two rails can be sequenced. There is no limit to the number of rails that can be sequenced in this way.
Figure 10-1. Power Sequencing With PG Control Schematic
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10.1.4 Monitoring a Downstream Voltage
The SNS pin can be used to monitor other system voltages in addition to VOUT. The status of the monitored
voltage are indicated by the PG pin which can be pulled up to VOUT or another voltage. Figure 10-2 shows an
example of the TPS2295x-Q1 monitoring the output of a downstream DC/DC regulator. In this case, the switch
turns on when the power supply is above the UVLO, but the PG is not asserted until the DC/DC regulator has
started up.
Figure 10-2. Monitoring a Downstream Voltage Schematic
In this application, if the DC/DC Regulator is shut down, the supervisor registers this as a fault case and resets
the load switch.
10.1.5 Monitoring the Input Voltage
The SNS pin can also be used to monitor VIN in the case a MCU GPIO is being used to control the EN. This
event allows PG to report on the status of the input voltage when the switch is enabled. See Figure 10-3.
Figure 10-3. Monitoring the Input Voltage Schematic
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10.1.6 Break-Before-Make Power MUX (TPS22953-Q1 Only)
The reverse current blocking feature of the TPS22953-Q1 makes it suitable for power multiplexing (MUXing)
between two power supplies with different voltages. The SNS and PG pin can be configured to implement
break-before-make logic. The circuit in Figure 10-4 shows how the detection of power supply 1 can be used to
disable the load switch for power supply 2. By tying the SNS of Load Switch 1 directly to the input, its PG pin is
pulled up as soon as the device is enabled.
Figure 10-4. Break-Before-Make Power MUX Schematic
The break-before-make logic ensures that power supply 2 is completely disconnected before power supply 1
is connected. This approach provides very robust reverse current blocking. However, in most cases, this also
results in a dip in the output voltage when switching between supplies.
The amount of voltage dip depends on the loading, the output capacitance, and the turn-on delay of the load
switch. In this application, leaving the CT pin open results in the shortest turn on delay and minimize the output
voltage dip.
Table 10-1 summarizes the logic of the PG Signal for Figure 10-4.
Table 10-1. Break-Before-Make PG Signal
PG Signal
Indication
H
L
Power supply 1 not present. System powered from power supply 2.
Power supply 1 present. System powered from power supply 1.
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10.1.7 Make-Before-Break Power MUX (TPS22953-Q1 Only)
The reverse current blocking feature of the TPS22953-Q1 makes it suitable for power multiplexing (MUXing)
between two power supplies with different voltages. The SNS and PG pin can be configured to implement
make-before-break logic. The circuit in Figure 10-5 shows how the detection of Load Switch 1 turning on can
be used to disable the load switch for power supply 2. By tying SNS to the Load, the PG is pulled up when the
output voltage starts to rise. This disables an active low load switch such as the TPS22910A.
Figure 10-5. Make-Before-Break Power MUX Schematic
The make-before-break logic ensures that power supply 2 is not disconnected until power supply 1 is connected.
Unlike break-before-make logic, this approach is ideal for preventing voltage dip on the output when switching
between supplies. However, in most cases, this also results in temporary reverse current flow.
The TPS22910A is well suited for this application because it can detect and block reverse current even before it
is disabled by the TPS22953-Q1 PG signal. Also, the active low enable of the TPS22910A eliminates the need
for an inverter as shown in the previous example.
In order to ensure correct logic, the SNS pin must be configured to toggle PG when the load voltage is between
the two supply voltages (3.6 V to 4.5 V). The SNS resistor values in Figure 10-5 are assuming a tolerance of
±1% or better.
Table 10-2 summarizes the logic of the PG Signal for Figure 10-5.
Table 10-2. Make-Before-Break PG Signal
PG Signal
Indication
H
L
Power supply 1 present. System powered from power supply 1.
Power supply 1 not present. System powered from power supply 2.
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10.2 Typical Application
This application demonstrates how the TPS2295x-Q1 can be used to limit inrush current to output capacitance.
Figure 10-6. Powering a Downstream Module Schematic
10.2.1 Design Requirements
For this design example, use the input parameters shown in Table 10-3.
Table 10-3. Design Parameters
DESIGN PARAMETER
EXAMPLE VALUE
VIN
3.3 V
5 V
VBIAS
CL
47 µF
150 mA
None
Maximum Acceptable Inrush Current
RL
10.2.2 Detailed Design Procedure
To begin the design process, the designer needs to know the following:
•
•
•
•
•
Input voltage
BIAS voltage
Load current
Load capacitance
Maximum acceptable inrush current
10.2.2.1 Inrush Current
Use Equation 7 to determine how much inrush current is caused by the CL capacitor.
dVOUT
I
= CL ´
INRUSH
dt
(7)
where
•
•
•
•
IINRUSH is the amount of inrush caused by CL
CL is the load capacitance on VOUT
dt is the VOUT rise time (typically 10% to 90%)
dVOUT is the change in VOUT Voltage (typically 10% to 90%)
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In this case, a Slew Rate slower than 314 μs/V is required to meet the maximum acceptable inrush requirement.
Equation 4 can be used to estimate the CT capacitance (as shown in Equation 8 and Equation 9) required for
this slew rate.
314 μs/V = 0.35 × CT + 20
CT = 840 pF
(8)
(9)
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10.2.3 Application Curves
The following Application Curves show the inrush with multiple different CT values. These curves show only a
CT capacitance greater than 840 pF results in the acceptable inrush current of 150 mA.
CT = 0 pF
CT = 220 pF
Figure 10-7. Inrush With CT = 0 pF
Figure 10-8. Inrush With CT = 220 pF
CT = 470 pF
CT = 1000 pF
Figure 10-9. Inrush With CT = 470 pF
Figure 10-10. Inrush With CT = 1000 pF
CT = 2200 pF
Figure 10-11. Inrush With CT = 2200 pF
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11 Power Supply Recommendations
The device is designed to operate from a VBIAS range of 2.5 V to 5.7 V and a VIN range of 0.7 V to 5.7 V. The
power supply must be well regulated and placed as close to the device terminals as possible. The power supply
must be able to withstand all transient and load current steps. In most situations, using an input capacitance
of 1 µF is sufficient to prevent the supply voltage from dipping when the switch is turned on. In cases where
the power supply is slow to respond to a large transient current or large load current step, additional bulk
capacitance can be required on the input.
The requirements for larger input capacitance can be mitigated by adding additional capacitance to the CT pin.
This action causes the load switch to turn on more slowly. Not only does this event reduce transient inrush
current, but it also gives the power supply more time to respond to the load current step.
12 Layout
12.1 Layout Guidelines
•
•
•
Input and Output traces must be as short and wide as possible to accommodate for high current.
Use vias under the exposed thermal pad for thermal relief for high current operation.
The CT Capacitor must be placed as close as possible to the device to minimize parasitic trace capacitance.
TI recommends to cutout copper on other layers directly below CT to minimize parasitic capacitance.
The IN terminal must be bypassed to ground with low ESR ceramic bypass capacitors. The typical
recommended bypass capacitance is ceramic with X5R or X7R dielectric. This capacitor must be placed
as close to the device pins as possible.
The OUT terminal must be bypassed to ground with low ESR ceramic bypass capacitors. The typical
recommended bypass capacitance is ceramic with X5R or X7R dielectric. This capacitor must be placed as
close to the device pins as possible.
•
•
•
The BIAS terminal must be bypassed to ground with low ESR ceramic bypass capacitors. The typical
recommended bypass capacitance is ceramic with X5R or X7R dielectric.
12.2 Layout Example
VIA to Power Ground Plane
VIA to PG pin
Input Bypass
Output Bypass
Capacitor
Capacitor
IN
OUT
OUT
SNS
PG
IN
To Bias Supply
BIAS
To µC
EN
GND
CT
To GPIO
control or
resistor
divider
Exposed Thermal
Pad Area
Figure 12-1. Recommended Board Layout
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13 Device and Documentation Support
13.1 Documentation Support
13.1.1 Related Documentation
For related documentation see the following:
•
•
•
•
•
Texas Instruments, TPS22953/54 5.7-V, 5-A, 14-mΩ On-Resistance Load Switch user's guide
Texas Instruments, Basics of Load Switches application report
Texas Instruments, Managing Inrush Current application report
Texas Instruments, Reverse Current Protection in Load Switches application report
Texas Instruments, Quiescent Current vs Shutdown Current for Load Switch Power Consumption application
report
•
Texas Instruments, Load Switch Thermal Considerations application report
13.2 Related Links
The table below lists quick access links. Categories include technical documents, support and community
resources, tools and software, and quick access to sample or buy.
Table 13-1. Related Links
TECHNICAL
DOCUMENTS
TOOLS &
SOFTWARE
SUPPORT &
COMMUNITY
PARTS
PRODUCT FOLDER
SAMPLE & BUY
TPS22953-Q1
TPS22954-Q1
Click here
Click here
Click here
Click here
Click here
Click here
Click here
Click here
Click here
Click here
13.3 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. Click on
Subscribe to updates to register and receive a weekly digest of any product information that has changed. For
change details, review the revision history included in any revised document.
13.4 Support Resources
TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help — straight
from the experts. Search existing answers or ask your own question to get the quick design help you need.
Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do
not necessarily reflect TI's views; see TI's Terms of Use.
13.5 Trademarks
TI E2E™ is a trademark of Texas Instruments.
All trademarks are the property of their respective owners.
13.6 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled
with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may
be more susceptible to damage because very small parametric changes could cause the device not to meet its published
specifications.
13.7 Glossary
TI Glossary
This glossary lists and explains terms, acronyms, and definitions.
14 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
Copyright © 2021 Texas Instruments Incorporated
38
Submit Document Feedback
Product Folder Links: TPS22953-Q1 TPS22954-Q1
TPS22953-Q1, TPS22954-Q1
www.ti.com
SLVSGK4 – NOVEMBER 2021
14.1 Tape and Reel Information
REEL DIMENSIONS
TAPE DIMENSIONS
K0
P1
W
B0
Reel
Diameter
Cavity
A0
A0 Dimension designed to accommodate the component width
B0 Dimension designed to accommodate the component length
K0 Dimension designed to accommodate the component thickness
Overall width of the carrier tape
W
P1 Pitch between successive cavity centers
Reel Width (W1)
QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE
Sprocket Holes
Q1 Q2
Q3 Q4
Q1 Q2
Q3 Q4
User Direction of Feed
Pocket Quadrants
Reel
Diameter
(mm)
Reel
Width W1
(mm)
Package
Type
Package
Drawing
A0
(mm)
B0
(mm)
K0
(mm)
P1
(mm)
W
(mm)
Pin1
Quadrant
Device
Pins
SPQ
TPS22953QDQCRQ1
TPS22953QDQCRQ1
WSON
WSON
WSON
WSON
DQC
DQC
DQC
DQC
10
10
10
10
3000
3000
3000
3000
180.0
180.0
180.0
180.0
8.4
8.4
8.4
8.4
2.25
2.3
3.25
3.2
1.05
1.0
4.0
4.0
4.0
4.0
8.0
8.0
8.0
8.0
Q1
Q1
Q1
Q1
TPS22954QDQCRQ1
TPS22954QDQCRQ1
2.25
2.3
3.25
3.2
1.05
1.0
Copyright © 2021 Texas Instruments Incorporated
Submit Document Feedback
39
Product Folder Links: TPS22953-Q1 TPS22954-Q1
TPS22953-Q1, TPS22954-Q1
SLVSGK4 – NOVEMBER 2021
www.ti.com
TAPE AND REEL BOX DIMENSIONS
Width (mm)
H
W
L
Device
Package Type
Package Drawing Pins
SPQ
Length (mm) Width (mm)
Height (mm)
TPS22953QDQCRQ1
TPS22953QDQCRQ1
WSON
DQC
DQC
DQC
DQC
10
10
10
10
3000
210.0
195.0
210.0
195.0
185.0
200.0
185.0
200.0
35.0
WSON
WSON
WSON
3000
3000
3000
45.0
35.0
45.0
TPS22954QDQCRQ1
TPS22954QDQCRQ1
Copyright © 2021 Texas Instruments Incorporated
40
Submit Document Feedback
Product Folder Links: TPS22953-Q1 TPS22954-Q1
TPS22953-Q1, TPS22954-Q1
www.ti.com
SLVSGK4 – NOVEMBER 2021
PACKAGE OUTLINE
DQC0010A
WSON - 0.8mm max height
S
C
A
L
E
4
.
5
0
0
PLASTIC SMALL OUTLINE - NO LEAD
2.1
1.9
B
A
PIN 1 INDEX AREA
3.1
2.9
0.3
0.2
0.35
0.25
OPTIONAL TERMINAL
TYPICAL
C
0.8 MAX
SEATING PLANE
0.08
0.84 0.1
SYMM
(0.2) TYP
0.05
0.00
5
6
8X 0.5
2X
2
SYMM
11
2.4 0.1
SEE OPTIONAL
TERMINAL
DETAIL
1
10
0.3
10X
0.2
0.1
0.05
PIN 1 ID
(45 X0.2)
C A B
C
0.35
10X
0.25
4218281/B 11/2016
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. The package thermal pad must be soldered to the printed circuit board for thermal and mechanical performance.
www.ti.com
Copyright © 2021 Texas Instruments Incorporated
Submit Document Feedback
41
Product Folder Links: TPS22953-Q1 TPS22954-Q1
TPS22953-Q1, TPS22954-Q1
SLVSGK4 – NOVEMBER 2021
www.ti.com
EXAMPLE BOARD LAYOUT
DQC0010A
WSON - 0.8mm max height
PLASTIC SMALL OUTLINE - NO LEAD
(0.84)
( 0.2) TYP
VIA
10X (0.5)
1
10
10X (0.25)
(0.95)
11
SYMM
(2.4)
8X (0.5)
5
6
(R0.05) TYP
SYMM
(1.9)
LAND PATTERN EXAMPLE
SCALE: 30X
0.07 MAX
ALL AROUND
0.07 MIN
ALL AROUND
SOLDER MASK
OPENING
METAL
SOLDER MASK
OPENING
METAL
NON SOLDER MASK
DEFINED
(PREFERRED)
SOLDER MASK
DEFINED
SOLDER MASK DETAILS
4218281/B 11/2016
NOTES: (continued)
4. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature
number SLUA271 (www.ti.com/lit/slua271).
5. Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to their locations shown
on this view. It is recommended that vias under paste be filled, plugged or tented.
www.ti.com
Copyright © 2021 Texas Instruments Incorporated
42
Submit Document Feedback
Product Folder Links: TPS22953-Q1 TPS22954-Q1
TPS22953-Q1, TPS22954-Q1
www.ti.com
SLVSGK4 – NOVEMBER 2021
EXAMPLE STENCIL DESIGN
DQC0010A
WSON - 0.8mm max height
PLASTIC SMALL OUTLINE - NO LEAD
(0.8)
10X (0.5)
10
10X (0.25)
1
(1.08)
11
SYMM
8X (0.5)
(0.64)
METAL
TYP
6
5
(R0.05) TYP
SYMM
(1.9)
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
EXPOSED PAD 11:
86% PRINTED SOLDER COVERAGE BY AREA UNDER PACKAGE
SCALE: 30X
4218281/B 11/2016
NOTES: (continued)
6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
www.ti.com
Copyright © 2021 Texas Instruments Incorporated
Submit Document Feedback
43
Product Folder Links: TPS22953-Q1 TPS22954-Q1
PACKAGE OPTION ADDENDUM
www.ti.com
21-Nov-2021
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
PTPS22953QDQCRQ1
PTPS22954QDQCRQ1
ACTIVE
ACTIVE
WSON
WSON
DQC
DQC
10
10
3000
3000
TBD
TBD
Call TI
Call TI
Call TI
-40 to 125
-40 to 125
Call TI
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
21-Nov-2021
OTHER QUALIFIED VERSIONS OF TPS22953-Q1, TPS22954-Q1 :
Catalog : TPS22953, TPS22954
•
NOTE: Qualified Version Definitions:
Catalog - TI's standard catalog product
•
Addendum-Page 2
IMPORTANT NOTICE AND DISCLAIMER
TI PROVIDES TECHNICAL AND RELIABILITY DATA (INCLUDING DATA SHEETS), DESIGN RESOURCES (INCLUDING REFERENCE
DESIGNS), APPLICATION OR OTHER DESIGN ADVICE, WEB TOOLS, SAFETY INFORMATION, AND OTHER RESOURCES “AS IS”
AND WITH ALL FAULTS, AND DISCLAIMS ALL WARRANTIES, EXPRESS AND IMPLIED, INCLUDING WITHOUT LIMITATION ANY
IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NON-INFRINGEMENT OF THIRD
PARTY INTELLECTUAL PROPERTY RIGHTS.
These resources are intended for skilled developers designing with TI products. You are solely responsible for (1) selecting the appropriate
TI products for your application, (2) designing, validating and testing your application, and (3) ensuring your application meets applicable
standards, and any other safety, security, regulatory or other requirements.
These resources are subject to change without notice. TI grants you permission to use these resources only for development of an
application that uses the TI products described in the resource. Other reproduction and display of these resources is prohibited. No license
is granted to any other TI intellectual property right or to any third party intellectual property right. TI disclaims responsibility for, and you
will fully indemnify TI and its representatives against, any claims, damages, costs, losses, and liabilities arising out of your use of these
resources.
TI’s products are provided subject to TI’s Terms of Sale or other applicable terms available either on ti.com or provided in conjunction with
such TI products. TI’s provision of these resources does not expand or otherwise alter TI’s applicable warranties or warranty disclaimers for
TI products.
TI objects to and rejects any additional or different terms you may have proposed. IMPORTANT NOTICE
Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265
Copyright © 2021, Texas Instruments Incorporated
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