TPS2117 [TI]
1.6-V to 5.5-V, 20-mΩ, 4-A low IQ power multiplexer with manual and priority switchover;![TPS2117](http://pdffile.icpdf.com/pdf2/p00358/img/icpdf/TPS2117_2197119_icpdf.jpg)
型号: | TPS2117 |
厂家: | ![]() |
描述: | 1.6-V to 5.5-V, 20-mΩ, 4-A low IQ power multiplexer with manual and priority switchover |
文件: | 总26页 (文件大小:1843K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
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TPS2117
ZHCSQV7 –MARCH 2023
TPS2117 具有手动和优先级切换功能的1.6V 至5.5V、4A 低IQ 电源多路复用器
1 特性
3 说明
• 输入电压范围:1.6V 至5.5V
• 最大持续电流:4A
• 导通电阻:20mΩ(典型值)
• VIN2 待机电流:50nA(典型值)
• 静态电流:1.32µA(典型值)
• 切换模式:
TPS2117 是一款电源多路复用器,具有 1.6V 至 5.5V
的额定电压和 4A 的最大额定电流。该器件使用 N 沟
道 MOSFET 在电源之间切换,同时在第一次施加电压
时提供受控的压摆率。
凭借 1.32μA(典型值)的低静态电流和 50nA(典型
值)的低待机电流,TPS2117 适用于其中一个输入由
电池供电的系统。这些低电流延长了电池的使用寿命和
续航时间。
– 优先级模式
– 手动模式
– 二极管模式
TPS2117 可根据应用配置用于两种不同的切换操作。
自动优先级模式优先选择连接到 VIN1 的电源,在
VIN1 下降时将切换到次级电源 (VIN2)。手动模式允许
用户切换GPIO 或使信号能够在通道之间切换。
• 受控输出压摆率:
– 电压为3.3V 时为1.3ms(典型值)
• VOUT 大于VINx 时实现反向电流阻断
• 热关断
封装信息
封装(1)
2 应用
封装尺寸(标称值)
器件型号
TPS2117
• 备用电池系统
• 电表
DRL (SOT, 8)
2.10 mm × 1.60 mm
• 电机驱动
• 楼宇自动化
(1) 如需了解所有可用封装,请参阅数据表末尾的可订购产品附
录。
Input Supply 1
(Primary)
VIN1
PR1
Output Load
VOUT
VIN1
RST
IN1
IN2
ST
MODE
VIN2
Input Supply 2
(Secondary)
GND
GND
基本应用
本文档旨在为方便起见,提供有关TI 产品中文版本的信息,以确认产品的概要。有关适用的官方英文版本的最新信息,请访问
www.ti.com,其内容始终优先。TI 不保证翻译的准确性和有效性。在实际设计之前,请务必参考最新版本的英文版本。
English Data Sheet: SLVSGZ5
TPS2117
ZHCSQV7 –MARCH 2023
www.ti.com.cn
Table of Contents
7.5 Fast Switchover Behavior......................................... 10
7.6 Output Voltage Drop................................................. 10
7.7 Device Functional Modes..........................................10
8 Application and Implementation..................................13
8.1 Application Information............................................. 13
8.2 Typical Application.................................................... 13
8.3 Power Supply Recommendations.............................14
8.4 Layout....................................................................... 14
9 Device and Documentation Support............................16
9.1 Documentation Support............................................ 16
9.2 接收文档更新通知..................................................... 16
9.3 Trademarks...............................................................16
9.4 静电放电警告............................................................ 16
9.5 术语表....................................................................... 16
10 Mechanical, Packaging, and Orderable
1 特性................................................................................... 1
2 应用................................................................................... 1
3 说明................................................................................... 1
4 Revision History.............................................................. 2
5 Pin Configuration and Functions...................................3
6 Specifications.................................................................. 4
6.1 绝对最大额定值...........................................................4
6.2 ESD Ratings............................................................... 4
6.3 Recommended Operating Conditions.........................4
6.4 Thermal Information....................................................5
6.5 Electrical Characteristics.............................................5
6.6 Switching Characteristics............................................7
6.7 Timing Diagrams ........................................................7
7 Detailed Description........................................................8
7.1 Overview.....................................................................8
7.2 Functional Block Diagram...........................................8
7.3 Feature Description.....................................................8
7.4 VINx Collapse Rate...................................................10
Information.................................................................... 16
10.1 Tape and Reel Information......................................17
4 Revision History
注:以前版本的页码可能与当前版本的页码不同
DATE
REVISION
NOTES
March 2023
*
Initial Release
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5 Pin Configuration and Functions
图5-1. DRL Package, 8-Pin SOT (Top View)
表5-1. Pin Functions
PIN
I/O
DESCRIPTION
NAME
GND
NO.
1
Device ground.
—
O
I
VOUT
VIN1
2, 7
3
Output power.
Channel 1 input power.
Selects between VIN1 and VIN2. When PR1 is high VIN1 is
selected, and when PR1 is low VIN2 is selected.
PR1
4
5
I
I
Device is put into Priority mode when MODE is tied to VIN1 and
manual mode when MODE is pulled up to an external voltage.
MODE
VIN2
ST
6
8
I
Channel 2 input power.
O
Open drain status pin. Pulled low when VIN1 is not being used.
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6 Specifications
6.1 绝对最大额定值
在自然通风条件下的工作温度范围内测得(除非另有说明)(1)
最小值
–0.3
–0.3
最大值
单位
6
V
VIN1、VIN2
输入电压
输出电压
VOUT
6
6
V
V
A
A
VST、VPR1
VMODE
、
–0.3
控制引脚电压
最大电流
IMAX
4
最大脉冲电流
最大持续时间1ms,占空比为2%
IMAX,PLS
6.4
TJ
°C
°C
结温
受内部限制
Tstg
150
–65
贮存温度
(1) 超出绝对最大额定值下列出的压力可能会对器件造成损坏。这些仅是压力额定值,并不意味着器件在这些条件下以及在建议运行条件以
外的任何其他条件下能够正常运行。长时间处于绝对最大额定条件下可能会影响器件的可靠性。
6.2 ESD Ratings
VALUE
UNIT
Human body model (HBM), per ANSI/ESDA/
JEDEC JS-001, all pins(1)
±2000
V(ESD)
Electrostatic discharge
V
Charged device model (CDM), per JEDEC
specification JESD22-C101, all pins(2)
±500
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
6.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
MIN
1.6
0
NOM
MAX
5.5
UNIT
V
VIN1, VIN2
VOUT
VST
Input Voltage
Output Voltage
5.5
V
,
VMODE
VPR1
,
Control Pin Voltage
0
5.5
V
TA
Ambient Temperature
105
°C
–40
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6.4 Thermal Information
TPS2116
DRL (SOT)
8-PINS
111.7
THERMAL METRIC(1)
UNIT
RθJA
Junction-to-ambient thermal resistance
Junction-to-case (top) thermal resistance
Junction-to-board thermal resistance
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
RθJC(top)
RθJB
36.4
18.1
Junction-to-top characterization parameter
Junction-to-board characterization parameter
Junction-to-case (bottom) thermal resistance
1.1
ΨJT
17.9
ΨJB
RθJC(bot)
N/A
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
6.5 Electrical Characteristics
Over operating free-air temperature range and operating voltage range of 1.6V to 5.5V (unless otherwise noted). Typical
specifications are at an input voltage of 3.3V and ambient temperature of 25°C.
PARAMETER
TEST CONDITIONS
TA
MIN
TYP
MAX UNIT
Power Consumption
25°C
1.1
uA
VIN2 powers VOUT
VIN1 > VIN2 + 0.1V
-40°C to 85°C
-40°C to 105°C
25°C
1.9
2
uA
uA
uA
uA
uA
uA
uA
uA
uA
uA
uA
uA
uA
uA
uA
uA
uA
uA
uA
uA
uA
uA
uA
ISTBY,
VIN1 Standby Current
VIN1
0.22
1.2
VIN2 powers VOUT
VIN2 > VIN1 + 0.2V
-40°C to 85°C
-40°C to 105°C
25°C
0.31
0.32
VIN1 powers VOUT
VIN2 > VIN1 + 0.2V
-40°C to 85°C
-40°C to 105°C
25°C
2
2.1
ISTBY,
VIN2 Standby Current
VIN2
0.05
1.32
0.3
VIN1 powers VOUT
VIN1 > VIN2 + 0.1V
-40°C to 85°C
-40°C to 105°C
25°C
0.06
0.08
VIN1 powers VOUT
VIN1 > VIN2 + 0.1V
-40°C to 85°C
-40°C to 105°C
25°C
3.6
4.4
IQ, VIN1 VIN1 Quiescent Current
VIN1 powers VOUT
VIN2 > VIN1 + 0.2V
-40°C to 85°C
-40°C to 105°C
25°C
0.46
0.50
1.35
0.1
VIN2 powers VOUT
VIN2 > VIN1 + 0.2V
-40°C to 85°C
-40°C to 105°C
25°C
3.7
4.5
IQ, VIN2 VIN2 Quiescent Current
VIN2 powers VOUT
VIN1 > VIN2 + 0.1V
-40°C to 85°C
-40°C to 105°C
0.22
0.27
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6.5 Electrical Characteristics (continued)
Over operating free-air temperature range and operating voltage range of 1.6V to 5.5V (unless otherwise noted). Typical
specifications are at an input voltage of 3.3V and ambient temperature of 25°C.
PARAMETER
TEST CONDITIONS
TA
MIN
TYP
MAX UNIT
25°C
0.1
uA
MODE = 0V, PR1 = 5V
VIN1 > VIN2
VOUT = 0V
-40°C to 85°C
-40°C to 105°C
25°C
1.9
5.3
uA
uA
uA
uA
uA
uA
uA
uA
uA
uA
uA
uA
uA
uA
uA
uA
uA
uA
uA
uA
ISD,VIN1 VIN1 Shutdown Current
0.05
0.05
0.05
MODE = 0V, PR1 = 5V
VIN1 < VIN2
VOUT = 0V
-40°C to 85°C
-40°C to 105°C
25°C
1.6
4.5
MODE = 0V, PR1 = 5V
VIN2 > VIN1
VOUT = 0V
-40°C to 85°C
-40°C to 105°C
25°C
1.8
4.5
ISD,VIN2 VIN2 Shutdown Current
MODE = 0V, PR1 = 5V
VIN2 < VIN1
VOUT = 0V
-40°C to 85°C
-40°C to 105°C
25°C
1.4
3.8
0.04
0.2
0.5
0.1
0.3
1
Reverse leakage current out of
VINx
VOUT = 5.5V
VINx = 0V, VINy = Open
85°C
105°C
IREV
25°C
VOUT = 5.5V
VINx = 0V, VINy = Open
Reverse leakage current into VOUT
85°C
105°C
IPR1
IMODE
IST
PR1 pin leakage
MODE pin leakage
ST pin leakage
-40°C to 105°C
-40°C to 105°C
-40°C to 105°C
0.05
0.05
0.03
Performance
25°C
18.5
20
25
31
33
25
31
33
27
34
38
28
37
40
0.1
mΩ
mΩ
mΩ
mΩ
mΩ
mΩ
mΩ
mΩ
mΩ
mΩ
mΩ
mΩ
V
VINx = 5V
IOUT = 200mA
-40°C to 85°C
-40°C to 105°C
25°C
VINx = 3.3V
IOUT = 200mA
-40°C to 85°C
-40°C to 105°C
25°C
RON
On-Resistance
20.5
21
VINx = 1.8V
IOUT = 200mA
-40°C to 85°C
-40°C to 105°C
25°C
VINx = 1.6V
IOUT = 200mA
-40°C to 85°C
-40°C to 105°C
-40°C to 105°C
VOL,ST Status pin VOL
IST = 1mA
ST pin pulled high to low
RST = 10kΩ
tST
Status pin response time
-40°C to 105°C
-40°C to 105°C
-40°C to 105°C
5
1
us
V
VREF
PR1 reference voltage
0.92
1
1.08
5.5
VIH,
MODE logic high threshold
V
MODE
VIL,
MODE logic low threshold
-40°C to 105°C
0
0.35
V
MODE
Protection
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English Data Sheet: SLVSGZ5
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6.5 Electrical Characteristics (continued)
Over operating free-air temperature range and operating voltage range of 1.6V to 5.5V (unless otherwise noted). Typical
specifications are at an input voltage of 3.3V and ambient temperature of 25°C.
PARAMETER
TEST CONDITIONS
TA
MIN
TYP
MAX UNIT
Reverse current blocking response
time
tRCB
VOUT > Selected VIN + 1V
-40°C to 105°C
2
us
Reverse current blocking rising
VRCB,R
VRCB,F
-40°C to 105°C
-40°C to 105°C
-40°C to 105°C
42
17
70
40
4
mV
mV
A
threshold (VOUT - VIN
Reverse current blocking falling
threshold (VOUT - VIN
)
)
Reverse current blocking activation
current
IRCB
TSD
1.4
Thermal shutdown
VIN1=VIN2
VIN1=VIN2
-
-
170
20
°C
°C
TSDHYS Thermal shutdown hysteresis
6.6 Switching Characteristics
Typical switching characteristics are defined at an ambient temperature of 25°C
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
Switchover
tSW
tSW
tSW
tD
Switchover time, VINx = 5V
Switchover time, VINx = 3.3V
Switchover time, VINx = 1.8V
Delay time, VINx = 5V
16
15
us
us
RL = 10Ω, CL = 10uF
RL = 10Ω, CL = 10uF
RL = 10Ω, CL = 10uF
RL = 100Ω, CL = 10uF
RL = 100Ω, CL = 10uF
RL = 100Ω, CL = 10uF
RL = 100Ω, CL = 10uF
RL = 100Ω, CL = 10uF
RL = 100Ω, CL = 10uF
12
us
1
ms
ms
ms
ms
ms
ms
tD
Delay time, VINx = 3.3V
Delay time, VINx = 1.8V
Soft-start time, VINx = 5V
Soft-start time, VINx = 3.3V
Soft-start time, VINx = 1.8V
1.2
1.4
1.7
1.3
0.9
tD
tSS
tSS
tSS
图6-1. TPS2117 Timing Diagram
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7 Detailed Description
7.1 Overview
The TPS2117 is a power mux device with a voltage rating of 1.6 V to 5.5 V and a maximum current rating of 4 A.
The device uses N-channel MOSFETs to switch between supplies while providing a controlled slew rate when
voltage is first applied.
The TPS2117 can be configured for two different switchover behaviors depending on the application. Automatic
priority mode prioritizes the supply connected to VIN1 and switches over to the secondary supply (VIN2) when
VIN1 drops. Manual mode allows the user to toggle a GPIO or enable signal to switch between channels.
Due to its low quiescent of 1.32 µA (typical) and standby current of 50 nA (typical), the TPS2117 is ideal for
systems where a battery is connected to one of the inputs. These low currents extend the life and operation of
the battery when in use.
7.2 Functional Block Diagram
7.3 Feature Description
The following sections detail the features of the TPS2117.
7.3.1 Truth Table
表 7-1 shows the expected behavior of the TPS2117. Manual mode and priority mode require MODE pin to be
connected to source that is within the specification for VIH,MODE. This can be either one of the VINx sources or an
external bias. For manual mode switching, PR1 is to be controlled via an external source to select between the
channels. For priority mode, PR1 voltage is set via a resistor divider from VINx sources. For diode mode, voltage
on the MODE pin must be within the specification for VIL,MODE
.
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表7-1. TPS2117 Truth Table
MODE
VIN1
VIN2
PR1
ST
VOUT
VIN1
VIN2
Hi-Z
X(1)
High
Low
Low
Low
Low
High
Low
Low
Low
≥1.6 V
≥1.6 V
< 1.6 V
< 1.6 V
X(1)
≥VREF
< VREF
X(1)
≥1.6 V
< 1.6 V
X(1)
VIN1 or external bias ≥1 V
(Priority/manual mode)
Hi-Z
≥VREF
< VREF
VIN2
VIN1
Hi-Z
≥1.6 V
≥1.6 V
< 1.6 V
< 1.6 V
X(1)
≥1.6 V
< 1.6 V
X(1)
≥VREF
X(1)
VIN2 or external bias ≥1 V
(Priority/manual mode)
< VREF
≥VREF
Hi-Z
X(1)
Hi-Z
> VIN2 and ≥1.6
X(1)
< VREF
< VREF
High
Low
VIN1
VIN2
External bias ≤0.35 V
V
(Diode mode)
> VIN1 and ≥1.6
X(1)
V
(1) X = do not care
7.3.2 Soft Start
When an input voltage is applied to the TPS2117 and the output voltage is lower than 1 V, the output will be
brought up with soft start to minimize the inrush current due to output capacitance. However, when the device
switches from one power supply to another (switchover) and VOUT > 1 V, soft start is not used to minimize the
output voltage drop. For linear soft start behavior, it is recommended to have an output capacitance of at least
0.1 µF.
7.3.3 Status Indication
The ST pin is an open drain output that should be pulled up to an external voltage for proper operation. When
the TPS2117 is powering the output using VIN1, the ST pin will be pulled high by the external voltage source.
Even if the device is blocking reverse current from VOUT to VIN1, selection of VIN1 will keep the ST pin pulled
high. When the TPS2117 is powering the output using VIN2 or both channels are disabled, the ST pin will be
pulled low. During thermal shutdown, the ST pin will be pulled low regardless of the channel being used.
7.3.4 Reverse Current Blocking
The TPS2117 initiates reverse current blocking (RCB) when the VOUT voltage is externally biased and exceeds
the input voltage supply being used. Once the output voltage is higher than the input voltage by 42 mV (VRCB,R),
the device will shutoff. During this state, the leakage into VOUT and out of VIN is defined by IREV. Once the
voltage difference between the output and input lowers to 17 mV (VRCB,F), the channel will turn back on.
图7-1. Reverse Current Blocking Behavior
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If RCB is expected to occur, it is recommended to clamp the output or use a high output capacitance (about 100
µF). This will prevent voltage spikes from damaging the device due to output inductance. Reverse current is not
a concern during normal switchover from one channel to another. This is because the device implements a
break-before-make switching methodology that prevents cross conduction and will not complete switchover until
the output voltage is less than the chosen input voltage.
7.4 VINx Collapse Rate
The TPS2117 uses the highest voltage supply to power the device. When one supply drops below the other, the
device changes the supply used to power the device. If the supply powering the device drops at a rate faster
than 1 V/10 μs, the other supply must be at 2.5 V or higher to prevent the device from resetting. If the other
supply is lower than 2.5 V, then the device may not be able to switch to the supply quickly enough, and the
device will reset and turn on with soft start timing if VOUT < 1 V.
7.5 Fast Switchover Behavior
The TPS2117 transitions between a primary and secondary supply with a fast switchover time of tSW. After the
secondary input is connected to the output, like tSW, the device heavily drives the channel of the secondary
supply to ramp up the output voltage as fast as possible. This is performed to keep the driven load in a stable
operating condition and to minimize the voltage dip. The duration of this channel boost is typically 11 µs. In the
case of a heavy load, the output voltage may not reach the final value after 11 µs and in this case the device
reverts back to the soft start output ramp rate. This behavior reduces the amount of time a large pulse of current
can flow through the enabled channel and into the load.
7.6 Output Voltage Drop
The output voltage drop during switchover from one supply to another is based on the load capacitance and load
resistance. The stronger the resistive load, the faster the output will discharge. The higher the capacitance on
the output, the less the voltage will drop during switchover.
7.7 Device Functional Modes
TPS2117 can be used in many operating modes depending on the application requirements. The device will
always be powered from the highest voltage rail that is connected to the VINx pins. The below sections detail the
two different configuraiton options for the device.
7.7.1 Priority and Manual Mode
When MODE is tied high, PR1 determines the channel selected. To configure VIN1 as the priority supply,
connect MODE to VIN1 and set the proper threshold through a resistor divider from VIN1 to PR1. To configure
manual selection, pull up MODE to an external supply and follow the truth table (表 7-1). When PR1 is pulled
above VREF, the voltage on VIN1 is used to power the output, and when it is pulled below VREF, VIN2 is used to
power the output. The expected behavior for the device is shown in 图7-2.
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图7-2. Priority and Manual Mode Switching
When PR1 is toggled, the device implements a break-before-make switchover which shuts off both channels
before turning on the new channel to power the output. This means that for time tSW, the output is unpowered
and will dip depending on the load current and output capacitance. If the output voltage is greater than the input
supply being switched to, then the device will not turn on the new channel until the output has discharged down
to VIN + VRCB to prevent reverse current flow.
When MODE is pulled low and PR1 is pulled high, the device enters shutdown. Both channels are turned off and
the output is high impedance. When the PR1 pin is pulled low, the higher voltage supply between VIN1 and VIN2
is passed to the output.
7.7.1.1 Priority Switching
In the case where VIN1 takes priority over VIN2, a resistor divider can be used to set the switchover voltage
threshold. When VIN1 is first applied, PR1 is brought high and VOUT is powered by that input. As VIN1 begins
to drop, the voltage on PR1 is lowered until it crosses the VREF threshold. At this point, the device switches over
to VIN2.
7.7.1.2 Manual Switching
For applications where a GPIO pin is used to select which input passes to the output, the GPIO pin can be
directly connected to the PR1 pin when MODE is tied high (≥1 V). When the GPIO is pulled high, VIN1 is used.
When the GPIO pin is pulled low, VIN2 is used.
Manual mode can also disable both channels by pulling the MODE pin low and keeping PR1 high. In this state,
the output of the device is high impedance and the leakage on each input is the shutdown current, ISD,VINx
.
7.7.2 Diode Mode
When the MODE pin is pulled below 0.35 V, the device enters a diode mode of operation. When both inputs are
applied to the device, the highest voltage is used to power the output. The PR1 pin is used as an active low
device enable, turning off the device when it is pulled high. When the device is turned back on, soft start is used
to power the output. The expected behavior for the device is shown in 图 7-3. It is not recommended to use
diode operation for two inputs of the same voltage, that is when the device is to multiplex and to connect one
input channel to the output. In the event that the input voltage sources are prone to droop in voltage when
loaded, it is also recommended to use input capacitance to stabilize the rails. This can especially aid in providing
stable input rails during switchover in diode mode.
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VIN 2 High
VUVLO
VIN1
VIN2
tD
tSS
tD
tSS
VIN1
VIN1
90%
VIN1
90%
tSW
tSW
VIN2
VOUT
Hi-Z
Hi-Z
10%
50%
10%
50%
tST
tST
tST
tST
tST
ST
50%
50%
50%
VREF
PR1
Time
图7-3. Diode Mode Switching
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8 Application and Implementation
备注
Information in the following applications sections is not part of the TI component specification, and TI
does not warrant its accuracy or completeness. TI’s customers are responsible for determining
suitability of components for their purposes, as well as validating and testing their design
implementation to confirm system functionality.
8.1 Application Information
This section highlights some of the design considerations when implementing this device in various applications.
8.2 Typical Application
This typical application demonstrates how the TPS2117 device can be used to control inrush current for high
output capacitances.
Input Supply 1
(Primary)
VIN1
PR1
Output Load
VOUT
VIN1
RST
IN1
IN2
ST
MODE
VIN2
Input Supply 2
(Secondary)
GND
GND
图8-1. TPS2117 Typical Application Diagram
8.2.1 Design Requirements
For this example, the values below are used as the design parameters.
表8-1. Design Parameters
PARAMETER
VALUE
VIN1 input voltage
Mode
5 V
Priority
100 µF
500 mA
Output capacitance
Maximum inrush current
8.2.2 Detailed Design Procedure
To determine how much inrush current is caused by the output capacitor, use 方程式1.
IINRUSH = COUT × VOUT / tSS
(1)
where
• IINRUSH = amount of inrush current caused by COUT
• COUT = capacitance on VOUT
• tSS = output voltage soft start time
• VOUT = final value of the output voltage
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With a final output voltage of 5 V, the expected rise time is 1.7 ms. Using the inrush current equation, the inrush
current caused by a 100-µF capacitance would be 294 mA, well below the 500-mA target.
8.2.3 Application Curves
图8-2 shows 5 V being applied to VIN1. The output comes up with slew rate control and limits the inrush current
to below 500 mA.
图8-2. TPS2117 Inrush Current Control
8.3 Power Supply Recommendations
The device is designed to operate with a VIN range of 1.6 V to 5.5 V. The VIN power supplies must be well
regulated and placed as close to the device terminals as possible. The power supplies must be able to withstand
all transient load current steps. In most situations, using an input capacitance (CIN) of 1 μF is sufficient to
prevent the supply voltage from dipping when the switch is turned on. In cases where the power supply is slow to
respond to a large transient current or large load current step, additional bulk capacitance may be required on
the input.
8.4 Layout
8.4.1 Layout Guidelines
For best performance, all traces must be as short as possible. To be most effective, the input and output
capacitors must be placed close to the device to minimize the effects that parasitic trace inductances may have
on normal operation. Using wide traces for VIN1, VIN2, VOUT, and GND helps minimize the parasitic electrical
effects.
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8.4.2 Layout Example
图8-3. TPS2117 Layout Example
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9 Device and Documentation Support
9.1 Documentation Support
9.1.1 Related Documentation
For related documentation see the following:
• Basics of Power MUX
• 11 Ways to Protect Your Power Path
9.2 接收文档更新通知
要接收文档更新通知,请导航至 ti.com 上的器件产品文件夹。点击订阅更新 进行注册,即可每周接收产品信息更
改摘要。有关更改的详细信息,请查看任何已修订文档中包含的修订历史记录。
9.3 Trademarks
所有商标均为其各自所有者的财产。
9.4 静电放电警告
静电放电(ESD) 会损坏这个集成电路。德州仪器(TI) 建议通过适当的预防措施处理所有集成电路。如果不遵守正确的处理
和安装程序,可能会损坏集成电路。
ESD 的损坏小至导致微小的性能降级,大至整个器件故障。精密的集成电路可能更容易受到损坏,这是因为非常细微的参
数更改都可能会导致器件与其发布的规格不相符。
9.5 术语表
TI 术语表
本术语表列出并解释了术语、首字母缩略词和定义。
10 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
Copyright © 2023 Texas Instruments Incorporated
English Data Sheet: SLVSGZ5
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10.1 Tape and Reel Information
REEL DIMENSIONS
TAPE DIMENSIONS
K0
P1
W
B0
Reel
Diameter
Cavity
A0
A0 Dimension designed to accommodate the component width
B0 Dimension designed to accommodate the component length
K0 Dimension designed to accommodate the component thickness
Overall width of the carrier tape
W
P1 Pitch between successive cavity centers
Reel Width (W1)
QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE
Sprocket Holes
Q1 Q2
Q3 Q4
Q1 Q2
Q3 Q4
User Direction of Feed
Pocket Quadrants
Reel
Diameter
(mm)
Reel
Width W1
(mm)
Package
Type
Package
Drawing
A0
(mm)
B0
(mm)
K0
(mm)
P1
(mm)
W
(mm)
Pin1
Quadrant
Device
Pins
SPQ
TPS2117
SOT
DRL
8
4000
180.0
8.4
2.75
1.9
0.8
4.0
8.0
Q3
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TAPE AND REEL BOX DIMENSIONS
Width (mm)
H
W
L
Device
Package Type
SOT
Package Drawing Pins
DRL
SPQ
Length (mm) Width (mm)
210.0 185.0
Height (mm)
TPS2117
8
4000
35.0
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PACKAGE OPTION ADDENDUM
www.ti.com
7-Apr-2023
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
PTPS2117DRLR
ACTIVE
SOT-5X3
DRL
8
4000
TBD
Call TI
Call TI
-40 to 125
Samples
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
PACKAGE OUTLINE
DRL0008A
SOT-5X3 - 0.6 mm max height
S
C
A
L
E
8
.
0
0
0
PLASTIC SMALL OUTLINE
1.3
1.1
B
A
PIN 1
ID AREA
1
8
6X 0.5
2.2
2.0
2X 1.5
NOTE 3
5
4
0.27
0.17
8X
1.7
1.5
0.05
0.00
0.1
C A B
0.05
C
0.6 MAX
SEATING PLANE
0.05 C
0.18
0.08
SYMM
0.4
0.2
8X
SYMM
4224486/E 12/2021
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, interlead flash, protrusions, or gate burrs shall not
exceed 0.15 mm per side.
4.Reference JEDEC Registration MO-293, Variation UDAD
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EXAMPLE BOARD LAYOUT
DRL0008A
SOT-5X3 - 0.6 mm max height
PLASTIC SMALL OUTLINE
8X (0.67)
SYMM
8
8X (0.3)
1
SYMM
6X (0.5)
5
4
(R0.05) TYP
(1.48)
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE:30X
0.05 MIN
AROUND
0.05 MAX
AROUND
EXPOSED
METAL
EXPOSED
METAL
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
METAL
SOLDER MASK
OPENING
NON SOLDER MASK
DEFINED
SOLDER MASK
DEFINED
(PREFERRED)
SOLDERMASK DETAILS
4224486/E 12/2021
NOTES: (continued)
5. Publication IPC-7351 may have alternate designs.
6. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
7. Land pattern design aligns to IPC-610, Bottom Termination Component (BTC) solder joint inspection criteria.
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EXAMPLE STENCIL DESIGN
DRL0008A
SOT-5X3 - 0.6 mm max height
PLASTIC SMALL OUTLINE
8X (0.67)
SYMM
8
8X (0.3)
1
SYMM
6X (0.5)
5
4
(R0.05) TYP
(1.48)
SOLDER PASTE EXAMPLE
BASED ON 0.1 mm THICK STENCIL
SCALE:30X
4224486/E 12/2021
NOTES: (continued)
8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
9. Board assembly site may have different recommendations for stencil design.
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