TPD1E1B04DPYR [TI]
采用 0402 封装、具有 6A 8/20us 浪涌和低钳位的 1pF、±3.6V、±30kV ESD 保护二极管 | DPY | 2 | -40 to 125;
| 型号： | TPD1E1B04DPYR |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 采用 0402 封装、具有 6A 8/20us 浪涌和低钳位的 1pF、±3.6V、±30kV ESD 保护二极管 | DPY | 2 | -40 to 125 二极管 |
| 文件： | 总22页 (文件大小：756K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
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TPD1E1B04
ZHCSF88A –MAY 2016–REVISED JULY 2016
TPD1E1B04 具有低 RDYN 和低钳位电压的单通道 ESD 保护二极管
1 特性
3 说明
1
•
IEC 61000-4-2 4 级静电放电 (ESD) 保护
TPD1E1B04 是一款双向 TVS ESD 保护二极管，特有
低 RDYN 和低钳位电压。TPD1E1B04 的额定 ESD 冲
击消散值等于 IEC 61000-4-2（4 级）国际标准中规定
的最高水平。
–
–
±30kV 接触放电
±30kV 气隙放电
•
•
IEC 61000-4-4 瞬态放电 (EFT) 保护
80A (5/50ns)
IEC 61000-4-5 浪涌保护
6.3A (8/20µs)
–
超低动态电阻 (0.15Ω) 和极低钳位电压（16A TLP 时
为 8.5V）可针对瞬变事件提供系统级保护。该器件 特
有 一个 1pF IO 电容，非常适合用于保护 USB 2.0 等
接口。
–
•
•
•
•
IO 电容值：1pF（典型值）
直流击穿电压：6.4V（典型值）
低泄漏电流：100nA（最大值）
极低 ESD 钳位电压
TPD1E1B04 采用符合行业标准的 0402 (DPY) 封装。
器件信息(1)
–
–
8.5V（±16A TLP 时）
DYN：0.15Ω
器件型号
TPD1E1B04
封装
X1SON (2)
封装尺寸（标称值）
R
0.60mm x 1.00mm
•
•
工业温度范围：-40°C 至 +125°C
行业标准的 0402 封装
(1) 要了解所有可用封装，请参见数据表末尾的可订购产品附录。
典型的 USB 2.0 应用原理图
5-V Source
2 应用
•
终端设备
–
–
–
–
–
可穿戴产品
便携式计算机和台式机
手机和平板电脑
机顶盒
VBUS
D-
D+
USB Transceiver
GND
1
2
1
数字视频录像机 (DVR) 和网络视频录像机
(NVR)
–
–
电视和监视器
2
EPOS（电子销售终端）
•
接口
Copyright © 2016, Texas Instruments Incorporated
–
–
–
–
USB 2.0/1.1
通用输入/输出 (GPIO)
按钮
音频
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
English Data Sheet: SLVSDL0
TPD1E1B04
ZHCSF88A –MAY 2016–REVISED JULY 2016
www.ti.com.cn
目录
7.4 Device Functional Modes.......................................... 9
Application and Implementation ........................ 10
8.1 Application Information............................................ 10
8.2 Typical Application ................................................. 10
Power Supply Recommendations...................... 12
1
2
3
4
5
6
特性.......................................................................... 1
应用.......................................................................... 1
说明.......................................................................... 1
修订历史记录 ........................................................... 2
Pin Configuration and Functions......................... 3
Specifications......................................................... 4
6.1 Absolute Maximum Ratings ...................................... 4
6.2 ESD Ratings.............................................................. 4
6.3 ESD Ratings—IEC Specification .............................. 4
6.4 Recommended Operating Conditions....................... 4
6.5 Thermal Information.................................................. 4
6.6 Electrical Characteristics........................................... 5
6.7 Typical Characteristics.............................................. 6
Detailed Description .............................................. 8
7.1 Overview ................................................................... 8
7.2 Functional Block Diagram ......................................... 8
7.3 Feature Description................................................... 8
8
9
10 Layout................................................................... 12
10.1 Layout Guidelines ................................................. 12
10.2 Layout Example .................................................... 12
11 器件和文档支持 ..................................................... 13
11.1 文档支持................................................................ 13
11.2 接收文档更新通知 ................................................. 13
11.3 社区资源................................................................ 13
11.4 商标....................................................................... 13
11.5 静电放电警告......................................................... 13
11.6 Glossary................................................................ 13
12 机械、封装和可订购信息....................................... 13
7
4 修订历史记录
注：之前版本的页码可能与当前版本有所不同。
Changes from Original (May 2016) to Revision A
Page
•
已将器件状态从产品预览更改为量产数据 .............................................................................................................................. 1
2
Copyright © 2016, Texas Instruments Incorporated
TPD1E1B04
www.ti.com.cn
ZHCSF88A –MAY 2016–REVISED JULY 2016
5 Pin Configuration and Functions
DPY Package
2-Pin X1SON
Top View
1
2
Pin Functions
PIN
I/O
DESCRIPTION
NO.
NAME
IO
1
2
I/O
I/O
ESD Protected Channel. If used as ESD IO, connect pin 2 to ground
ESD Protected Channel. If used as ESD IO, connect pin 1 to ground
IO
Copyright © 2016, Texas Instruments Incorporated
3
TPD1E1B04
ZHCSF88A –MAY 2016–REVISED JULY 2016
www.ti.com.cn
6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)(1)
MIN
MAX
80
UNIT
A
Electrical fast transient
Peak pulse
IEC 61000-4-4 (5/50 ns)
IEC 61000-4-5 Power (tp - 8/20 µs)
IEC 61000-4-5 Current (tp - 8/20 µs)
Operating free-air temperature
Storage temperature
50
W
6.3
A
TA
–40
–65
125
155
°C
°C
Tstg
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
6.2 ESD Ratings
VALUE
±4000
±1500
UNIT
Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1)
Charged-device model (CDM), per JEDEC specification JESD22-C101(2)
V(ESD)
Electrostatic discharge
V
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
6.3 ESD Ratings—IEC Specification
VALUE
UNIT
IEC 61000-4-2 contact discharge
IEC 61000-4-2 air-gap discharge
±30000
±30000
V(ESD)
Electrostatic discharge
V
6.4 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
MIN
–3.6
–40
MAX
3.6
UNIT
VIO
TA
Input pin voltage
V
Operating free-air temperature
125
°C
6.5 Thermal Information
TPD1E1B04
THERMAL METRIC(1)
DPY (X1SON)
2 PINS
420
UNIT
RθJA
Junction-to-ambient thermal resistance
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
RθJC(top)
RθJB
Junction-to-case (top) thermal resistance
Junction-to-board thermal resistance
169.3
276.1
ψJT
Junction-to-top characterization parameter
Junction-to-board characterization parameter
Junction-to-case (bottom) thermal resistance
122.1
ψJB
157.3
RθJC(bot)
N/A
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
4
Copyright © 2016, Texas Instruments Incorporated
TPD1E1B04
www.ti.com.cn
ZHCSF88A –MAY 2016–REVISED JULY 2016
6.6 Electrical Characteristics
over operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
VRWM
VBRF
Reverse stand-off voltage
IIO < 100 nA
–3.6
3.6
V
Measured as the maximum voltage
before device snaps back into VHOLD
voltage
Breakdown voltage, any IO pin to
GND
6.4
V
Measured as the maximum voltage
before device snaps back into VHOLD
voltage
Breakdown voltage, GND to any IO
pin
VBRR
–6.4
V
V
VHOLD
Holding voltage
IIO = 1 mA, TA = 25°C
5
6
6.3
6.6
IPP = 1 A, TLP, from IO to GND
IPP = 5 A, TLP, from IO to GND
IPP = 16 A, TLP, from IO to GND
IPP = 1 A, TLP, from GND to IO
IPP = 5 A, TLP, from GND to IO
IPP = 16 A, TLP, from GND to IO
VIO = ±2.5 V
6.8
8.5
VCLAMP
Clamping voltage
V
6.3
6.8
8.5
ILEAK
RDYN
Leakage current, IO to GND
Dynamic resistance
0.2
100
1.3
nA
IO to GND
0.15
0.15
Ω
GND to IO
VIO = 0 V, f = 1 MHz, IO to GND, TA
= 25°C
CL
Line capacitance
1
pF
Copyright © 2016, Texas Instruments Incorporated
5
TPD1E1B04
ZHCSF88A –MAY 2016–REVISED JULY 2016
www.ti.com.cn
6.7 Typical Characteristics
30
25
20
15
10
5
30
25
20
15
10
5
0
0
-5
-5
0
1
2
3
4
5
6
7
8
9
10 11 12
0
1
2
3
4
5
6
7
8
9
10 11 12
Voltage (V)
Voltage (V)
D001
D002
Figure 1. Positive TLP Curve
Figure 2. Negative TLP Curve
70
60
50
40
30
20
10
0
10
0
-10
-20
-30
-40
-50
-60
-70
-10
-10
0
10
20
30
40
50
60
70
80
90
-10
0
10
20
30
40
50
60
70
80
90
Time (ns)
Time (ns)
D003
D004
Figure 3. 8-kV IEC Waveform
Figure 4. –8-kV IEC Waveform
3.2
7
6
5
4
3
2
1
0
56
-40èC
25èC
85èC
125èC
Current
Power
2.8
2.4
2
48
40
32
24
16
8
1.6
1.2
0.8
0.4
0
0
-10 -5
0
5
10 15 20 25 30 35 40 45 50 55
0
0.3 0.6 0.9 1.2 1.5 1.8 2.1 2.4 2.7
Bias Voltage (V)
3
3.3 3.6
Time (ms)
D001
D006
Figure 5. Surge Curve (tp = 8/20 µs), Any IO Pin to GND
Figure 6. Capacitance vs. Bias Voltage
6
Copyright © 2016, Texas Instruments Incorporated
TPD1E1B04
www.ti.com.cn
ZHCSF88A –MAY 2016–REVISED JULY 2016
Typical Characteristics (continued)
2000
1800
1600
1400
1200
1000
800
1
0.8
0.6
0.4
0.2
0
-0.2
-0.4
-0.6
-0.8
-1
600
400
200
0
-40 -25 -10
5
20 35 50 65 80 95 110 125
-7 -6 -5 -4 -3 -2 -1
0
1
2
3
4
5
6
7
Temperature (èC)
Voltage (V)
D007
D008
Figure 7. Leakage Current vs. Temperature
Figure 8. DC Voltage Sweep I-V Curve
2
1.8
1.6
1.4
1.2
1
0
-1
-2
-3
-4
-5
-6
-7
-8
0.8
0.6
0.4
0.2
0
-9
1E+9
2.5E+9
4E+9
5.5E+9
7E+9
8.5E+9 1E+10
1000000
1E+7
1E+8
1E+9
1E+10
Frequency (Hz)
Frequency (Hz)
D009
D010
Figure 9. Capacitance vs. Frequency
Figure 10. Insertion Loss
Copyright © 2016, Texas Instruments Incorporated
7
TPD1E1B04
ZHCSF88A –MAY 2016–REVISED JULY 2016
www.ti.com.cn
7 Detailed Description
7.1 Overview
The TPD1E1B04 is a bidirectional ESD Protection Diode with ultra-low clamping voltage. This device can
dissipate ESD strikes above the maximum level specified by the IEC 61000-4-2 International Standard. The ultra-
low clamping makes this device ideal for protecting any sensitive signal pins.
7.2 Functional Block Diagram
IO
GND
Copyright © 2016, Texas Instruments Incorporated
7.3 Feature Description
7.3.1 IEC 61000-4-2 ESD Protection
The I/O pins can withstand ESD events up to ±30-kV contact and ±30-kV air gap. An ESD-surge clamp diverts
the current to ground.
7.3.2 IEC 61000-4-4 EFT Protection
The I/O pins can withstand an electrical fast transient burst of up to 80 A (5/50 ns waveform, 4 kV with 50-Ω
impedance). An ESD-surge clamp diverts the current to ground.
7.3.3 IEC 61000-4-5 Surge Protection
The I/O pins can withstand surge events up to 6.3 A and 50 W (8/20 µs waveform). An ESD-surge clamp diverts
this current to ground.
7.3.4 IO Capacitance
The capacitance between each I/O pin to ground is 1 pF (typical) and 1.3 pF (maximum).
7.3.5 DC Breakdown Voltage
The DC breakdown voltage of each I/O pin is ±6.4 V typical. This ensures that sensitive equipment is protected
from surges above the reverse standoff voltage of ±3.6 V.
7.3.6 Low Leakage Current
The I/O pins feature an low leakage current of 100 nA (maximum) with a bias of ±2.5 V.
7.3.7 Extremely Low ESD Clamping Voltage
The I/O pins feature an ESD clamp that is capable of clamping the voltage to 8.5 V (IPP = 16 A).
7.3.8 Industrial Temperature Range
This device features an industrial operating range of –40°C to +125°C.
7.3.9 Industry Standard Footprint
The layout of this device makes it simple and easy to add protection to an existing layout. The packages offers
flow-through routing, requiring minimal modification to an existing layout.
8
Copyright © 2016, Texas Instruments Incorporated
TPD1E1B04
www.ti.com.cn
ZHCSF88A –MAY 2016–REVISED JULY 2016
7.4 Device Functional Modes
The TPD1E1B04 is a passive integrated circuit that triggers when voltages are above VBRF or below VBRR. During
ESD events, voltages as high as ±30 kV (contact or air) can be directed to ground via the internal diode network.
When the voltages on the protected line fall below the trigger levels of TPD1E1B04 (usually within 10s of nano-
seconds) the device reverts to passive.
Copyright © 2016, Texas Instruments Incorporated
9
TPD1E1B04
ZHCSF88A –MAY 2016–REVISED JULY 2016
www.ti.com.cn
8 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
8.1 Application Information
The TPD1E1B04 is a diode type TVS which is used to provide a path to ground for dissipating ESD events on
high-speed signal lines between a human interface connector and a system. As the current from ESD passes
through the TVS, only a small voltage drop is present across the diode. This is the voltage presented to the
protected IC. The low RDYN of the triggered TVS holds this voltage, VCLAMP, to a safe level for the protected IC.
8.2 Typical Application
5-V Source
VBUS
D-
D+
USB Transceiver
GND
1
2
1
2
Copyright © 2016, Texas Instruments Incorporated
Figure 11. USB 2.0 ESD Schematic
8.2.1 Design Requirements
For this design example, two TPD1E1B04 devices are being used in a USB 2.0 application. This provides a
complete ESD protection scheme.
Given the USB 2.0 application, the parameters listed in Table 1 are known.
Table 1. Design Parameters
DESIGN PARAMETER
Signal range on DP-DM lines
VALUE
0 V to 3.6 V
up to 240 MHz
Operating frequency on DP-DM lines
8.2.2 Detailed Design Procedure
8.2.2.1 Signal Range
The TPD1E1B04 supports signal ranges between –3.6 V and 3.6 V, which supports the USB 2.0 signal pair on
the USB 2.0 application.
10
Copyright © 2016, Texas Instruments Incorporated
TPD1E1B04
www.ti.com.cn
ZHCSF88A –MAY 2016–REVISED JULY 2016
8.2.2.2 Operating Frequency
The TPD1E1B04 has a 1-pF (typical) capacitance, which supports the USB 2.0 data rates of 480 Mbps.
8.2.3 Application Curve
0
-1
-2
-3
-4
-5
-6
-7
-8
-9
1000000
1E+7
1E+8
1E+9
1E+10
Frequency (Hz)
D010
Figure 12. Insertion Loss
Copyright © 2016, Texas Instruments Incorporated
11
TPD1E1B04
ZHCSF88A –MAY 2016–REVISED JULY 2016
www.ti.com.cn
9 Power Supply Recommendations
The TPD1E1B04 is a passive ESD device so there is no need to power it. Take care not to violate the
recommended I/O specification (–3.6 V to 3.6 V) to ensure the device functions properly.
10 Layout
10.1 Layout Guidelines
•
The optimum placement is as close to the connector as possible.
–
EMI during an ESD event can couple from the trace being struck to other nearby unprotected traces,
resulting in early system failures.
–
The PCB designer must minimize the possibility of EMI coupling by keeping any unprotected traces away
from the protected traces which are between the TVS and the connector.
•
•
Route the protected traces as straight as possible.
Eliminate any sharp corners on the protected traces between the TVS and the connector by using rounded
corners with the largest radii possible.
–
Electric fields tend to build up on corners, increasing EMI coupling.
10.2 Layout Example
ë.Ü{
Ço power supply
Çꢁ5191.04
5-
Ço Ü{. transceiver
5+
Çꢁ5191.04
[egend
Db5
ꢁin to Db5
Ü{.2ꢀ0 /onnector
Figure 13. USB 2.0 ESD Layout
12
版权 © 2016, Texas Instruments Incorporated
TPD1E1B04
www.ti.com.cn
ZHCSF88A –MAY 2016–REVISED JULY 2016
11 器件和文档支持
11.1 文档支持
11.1.1 相关文档ꢀ
相关文档请参见以下部分：
《TPD1E1B04 评估模块》，SLVUAN7
11.2 接收文档更新通知
如需接收文档更新通知，请访问 ti.com 上的器件产品文件夹。点击右上角的提醒我 (Alert me) 注册后，即可每周定
期收到已更改的产品信息。有关更改的详细信息，请查阅已修订文档中包含的修订历史记录。
11.3 社区资源
The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.
11.4 商标
E2E is a trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
11.5 静电放电警告
ESD 可能会损坏该集成电路。德州仪器 (TI) 建议通过适当的预防措施处理所有集成电路。如果不遵守正确的处理措施和安装程序 , 可
能会损坏集成电路。
ESD 的损坏小至导致微小的性能降级 , 大至整个器件故障。 精密的集成电路可能更容易受到损坏 , 这是因为非常细微的参数更改都可
能会导致器件与其发布的规格不相符。
11.6 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
12 机械、封装和可订购信息
以下页中包括机械、封装和可订购信息。这些信息是针对指定器件可提供的最新数据。这些数据会在无通知且不对
本文档进行修订的情况下发生改变。欲获得该数据表的浏览器版本，请查阅左侧的导航栏。
版权 © 2016, Texas Instruments Incorporated
13
PACKAGE OPTION ADDENDUM
www.ti.com
1-Jul-2023
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
TPD1E1B04DPYR
TPD1E1B04DPYT
ACTIVE
ACTIVE
X1SON
X1SON
DPY
DPY
2
2
10000 RoHS & Green NIPDAU | NIPDAUAG Level-1-260C-UNLIM
250 RoHS & Green NIPDAU | NIPDAUAG Level-1-260C-UNLIM
-40 to 125
-40 to 125
(4X, A5)
4X
Samples
Samples
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
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Addendum-Page 1
PACKAGE OPTION ADDENDUM
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1-Jul-2023
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
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1-Jul-2023
TAPE AND REEL INFORMATION
REEL DIMENSIONS
TAPE DIMENSIONS
K0
P1
W
B0
Reel
Diameter
Cavity
A0
A0 Dimension designed to accommodate the component width
B0 Dimension designed to accommodate the component length
K0 Dimension designed to accommodate the component thickness
Overall width of the carrier tape
W
P1 Pitch between successive cavity centers
Reel Width (W1)
QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE
Sprocket Holes
Q1 Q2
Q3 Q4
Q1 Q2
Q3 Q4
User Direction of Feed
Pocket Quadrants
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
TPD1E1B04DPYT
TPD1E1B04DPYT
X1SON
X1SON
DPY
DPY
2
2
250
250
180.0
180.0
9.5
9.5
0.73
0.66
1.13
1.15
0.5
2.0
2.0
8.0
8.0
Q1
Q1
0.66
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
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1-Jul-2023
TAPE AND REEL BOX DIMENSIONS
Width (mm)
H
W
L
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SPQ
Length (mm) Width (mm) Height (mm)
TPD1E1B04DPYT
TPD1E1B04DPYT
X1SON
X1SON
DPY
DPY
2
2
250
250
189.0
184.0
185.0
184.0
36.0
19.0
Pack Materials-Page 2
PACKAGE OUTLINE
DPY0002A
X1SON - 0.45 mm max height
S
C
A
L
E
1
1
.
0
0
0
PLASTIC SMALL OUTLINE - NO LEAD
1.1
0.9
B
A
PIN 1 INDEX AREA
0.7
0.5
0.45
0.30
C
SEATING PLANE
0.08 C
0.05
0.00
0.65
1
2
SYMM
0.55
0.45
2X
0.1
C A B
SYMM
0.3
0.2
2X
0.05
C A B
4224561/B 03/2021
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M
2. This drawing is subject to change without notice.
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EXAMPLE BOARD LAYOUT
DPY0002A
X1SON - 0.45 mm max height
PLASTIC SMALL OUTLINE - NO LEAD
2X (0.3)
SYMM
1
2
SYMM
2X (0.5)
(R0.05) TYP
(0.7)
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE:60X
0.07 MIN
ALL AROUND
0.07 MAX
ALL AROUND
METAL EDGE
METAL UNDER
SOLDER MASK
EXPOSED
METAL
EXPOSED
METAL
SOLDER MASK
OPENING
SOLDER MASK
OPENING
SOLDER MASK
DEFINED
(PREFERRED)
NON SOLDER MASK
DEFINED
SOLDER MASK DETAILS
4224561/B 03/2021
NOTES: (continued)
3. For more information, see Texas Instruments literature number SLUA271 (www.ti.com/lit/slua271).
4. Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to their locations shown on this view.
It is recommended that vias under paste be filled, plugged or tented.
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EXAMPLE STENCIL DESIGN
DPY0002A
X1SON - 0.45 mm max height
PLASTIC SMALL OUTLINE - NO LEAD
(0)
2X (0.3)
2X (0.5)
SYMM
PCB PAD METAL
UNDER SOLDER PASTE
SYMM
2
1
(R0.05) TYP
(0.7)
SOLDER PASTE EXAMPLE
BASED ON 0.1 mm THICK STENCIL
SCALE:60X
4224561/B 03/2021
NOTES: (continued)
5. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
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