TPD1S514-3YZR [TI]
USB 充电器、过压、浪涌和 ESD 保护 | YZ | 12 | -40 to 85;
| 型号： | TPD1S514-3YZR |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | USB 充电器、过压、浪涌和 ESD 保护 | YZ | 12 | -40 to 85 |
| 文件： | 总26页 (文件大小：1900K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
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TPD1S514x
ZHCSCE8F –APRIL 2014–REVISED MAY 2019
适用于 VBUS 引脚的 TPD1S514x 系列 USB 充电器过压、浪涌和 ESD 保护
1 特性
3 说明
1
•
在 VBUS_CON
TPD1S514 系列包含适用于 5V、9V 或 12V USB
高达 30V 直流时提供过压保护
V
BUS 线路或其他电源总线的单芯片保护解决方案。此
双向 nFET 开关在保护内部系统电路不受任何
BUS_CON 引脚上过压情况影响的同时，可确保充电和
•
•
•
精密 OVP（容差小于 ± 1%）
低 RON nFET 开关支持主机和充电模式
V
专用 VBUS_POWER 引脚可在电池耗尽情况下提供灵
活的加电选项
主机模式下的安全电流流量。在 VBUS_CON 引脚上，这
款器件能够处理高达 30V 直流电压的过压保护。在
EN 引脚切换至低位后，TPD1S514 系列中的任何器件
均会在通过软启动延迟打开 nFET 之前等待 20ms。
•
针对 VBUS 线路的瞬态保护：
–
–
–
IEC 61000-4-2 接触放电 ±15kV
IEC 61000-4-2 空气间隙放电 ±15kV
IEC 61000-4-5 开路电压 100V
TPD1S514 系列的典型应用接口是 USB 连接器中的
VBUS 线路，该连接器通常用于手机、平板电脑、电子
–
精密钳位电路将 VBUS_SYS 电压限制为小于
书和便携式媒体播放器中。TPD1S514 系列还可应用
于任何使用 5V、9V、或 12V 电源轨接口的系统中。
VOVP
•
•
适应 USB 涌入电流
热关断 (TSD) 特性
器件信息(1)
器件名称
封装
封装尺寸（标称值）
2 应用
TPD1S514x
WCSP (12)
1.29mm × 1.99mm
•
•
•
•
•
手机
(1) 如需了解所有可用封装，请参阅数据表末尾的可订购产品附
录。
平板电脑
电子书
空白
便携式媒体播放器
5V、9V 和 12V 电源轨
空白
空白
空白
空白
TPD1S514 系列电路保护方案
TPD1S514 系列方框图
USB Port
PMIC/System
TPD1S514x
VBUS
D–
VBUS_CON
VBUS_SYS
VBUS_POWER
VIN
VBUS_CON
VOUT
LDO
POR
Oscillator
VBUS_POWER
Q-Pump
Gate Drive
Surge
Clamp
D+
GND
EN
VBUS_SYS
ID
TSD
GND
BG
Reference
EN Buffer
Digital
Core
GND
EN
OVP
+
-
VREF
TPD4E110
1
本文档旨在为方便起见，提供有关 TI 产品中文版本的信息，以确认产品的概要。 有关适用的官方英文版本的最新信息，请访问 www.ti.com，其内容始终优先。 TI 不保证翻译的准确
性和有效性。 在实际设计之前，请务必参考最新版本的英文版本。
English Data Sheet: SLVSCF6
TPD1S514x
ZHCSCE8F –APRIL 2014–REVISED MAY 2019
www.ti.com.cn
目录
1
2
3
4
5
6
7
特性.......................................................................... 1
应用.......................................................................... 1
说明.......................................................................... 1
修订历史记录 ........................................................... 2
Device Comparison Table..................................... 3
Pin Configuration and Functions......................... 3
Specifications......................................................... 4
7.1 Absolute Maximum Ratings ...................................... 4
7.2 ESD Ratings.............................................................. 4
7.3 Recommended Operating Conditions....................... 5
7.4 Thermal Information.................................................. 5
7.5 Supply Current Consumption.................................... 5
7.6 Electrical Characteristics EN Pin .............................. 6
7.7 Thermal Shutdown Feature ...................................... 6
7.8 Electrical Characteristics nFET Switch ..................... 6
7.9 Electrical Characteristics OVP Circuit....................... 7
7.10 Electrical Characteristics VBUS_POWER Circuit......... 7
7.11 Timing Requirements.............................................. 8
7.12 TPD1S514-1 Typical Characteristics ...................... 9
8
9
Detailed Description ............................................ 11
8.1 Overview ................................................................. 11
8.2 Functional Block Diagram ....................................... 11
8.3 Feature Description................................................. 11
8.4 Device Functional Modes........................................ 13
Application and Implementation ........................ 14
9.1 Application Information............................................ 14
9.2 Typical Applications ................................................ 14
10 Power Supply Recommendations ..................... 18
11 Layout................................................................... 19
11.1 Layout Guidelines ................................................. 19
11.2 Layout Example .................................................... 19
12 器件和文档支持 ..................................................... 20
12.1 社区资源................................................................ 20
12.2 商标....................................................................... 20
12.3 静电放电警告......................................................... 20
12.4 Glossary................................................................ 20
13 机械、封装和可订购信息....................................... 20
4 修订历史记录
注：之前版本的页码可能与当前版本有所不同。
Changes from Revision E (October 2015) to Revision F
Page
•
Changed IPOWER from 1 mA to 10 mA in the Absolute Maximum Ratings table..................................................................... 4
Changes from Revision D (July 2015) to Revision E
Page
•
•
•
删除了 TPD1S514-3 的“预览”状态。 ...................................................................................................................................... 1
Changed Max value of IVBUS_SLEEP PARAMETER for TPD1S514-3 (Preview) from 308 µA to 335 µA. ............................... 5
Updated TEST CONDITIONS for TOFF_DELAY PARAMETER. ................................................................................................ 8
Changes from Revision C (July 2015) to Revision D
Page
•
已添加 TPD1S514 和 TPD1S514-3（预览） ......................................................................................................................... 1
Changes from Revision B (September 2014) to Revision C
Page
•
删除了已预览的 TPD1S514-3 和可编程 特性。 ..................................................................................................................... 1
Changes from Revision A (July 2014) to Revision B
Page
•
已更改 更改了封装尺寸以修正舍入误差。.............................................................................................................................. 1
Changes from Original (April 2014) to Revision A
Page
•
•
•
删除了 TPD1S514-2 的“预览”状态。 ...................................................................................................................................... 1
Updated Device Comparison table. ....................................................................................................................................... 3
Updated Electrical Characteristics OVP Circuit table............................................................................................................. 7
2
Copyright © 2014–2019, Texas Instruments Incorporated
TPD1S514x
www.ti.com.cn
ZHCSCE8F –APRIL 2014–REVISED MAY 2019
5 Device Comparison Table
VOVP_HYS
(mV)
T_Startup delay (ms)
options
T_Soft Start (ms)
options
VOVP (V)
VBUS_POWER (V)(1)
TPD1S514 Family
MIN
5.9
TYP
5.95
9.98
13.75
5.95
MAX
5.99
10.05
14
TYP
100
100
100
20
MIN
4.7
4.7
4.7
6.2
TYP
4.95
4.95
4.95
6.48
TYP
TYP
TPD1S514-1
TPD1S514-2
TPD1S514-3
TPD1S514
9.9
20
3.5
13.5
5.9
5.99
(1) With VBUS_CON > 6.5V. See Sections VBUS_POWER, TPD1S514-1, TPD1S514-2, TPD1S514-3 and VBUS_POWER, TPD1S514 for full
description.
6 Pin Configuration and Functions
YZ Package
12-Pin WCSP
Top Side, See Through View
1
2
3
4
VBUS_SYS
VBUS_SYS
GND
EN
A
B
C
VBUS_SYS
VBUS_CON
VBUS_POWER
GND
VBUS_CON
VBUS_CON
GND
GND
Pin Functions
PIN
I/O
DESCRIPTION
NAME
NO.
Enable Active-Low Input. Drive EN low to enable the switch. Drive EN high to disable the
switch.
EN
A1
I
VBUS_POWER
VBUS_SYS
B1
O
5-V Power source controlled by VBUS_CON
Connect to internal VBUS plane.
.
A2, A3, B2
I/O
Connect to USB connector VBUS pin; IEC 61000-4-2 ESD protection and IEC 61000-4-5
Surge protection.
VBUS_CON
GND
B3, C2, C3
I/O
G
A4, B4, C1, C4
Connect to PCB ground plane.
Copyright © 2014–2019, Texas Instruments Incorporated
3
TPD1S514x
ZHCSCE8F –APRIL 2014–REVISED MAY 2019
www.ti.com.cn
7 Specifications
7.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)(1)(2)
MIN
–0.3
–0.3
MAX
30
20
3.5
3.5
8
UNIT
V
VBUS_CON
VBUS_SYS
IBUS
Supply voltage from USB connector
Internal Supply DC voltage Rail on the PCB
Continuous input current on VBUS_CON pin(3)
Continuous output current on VBUS_CON pin(3)
Peak Input and Output Current on VBUS_CON, VBUS_SYS pin (10 ms)
Continuous forward current through the FET body diode
Continuous current through VBUS_POWER
V
A
IOUT
A
IPEAK
A
IDIODE
IPOWER
VEN
1
A
10
mA
V
Voltage on Input pin (EN)
7
VBUS_POWER Continuous Voltage at VBUS_POWER
TPD1S514-1
TPD1S514-2
TPD1S514-3
TPD1S514
See(4)
See(4)
See(4)
See(4)
100
V
IEC 61000-4-5 open circuit voltage (tp = 1.2/50 µs)
VBUS_CON pin
VBUS_CON pin
VBUS_CON pin
VBUS_SYS pin
VBUS_CON pin
VBUS_POWER pin
V
IEC 61000-4-5 peak pulse current (tp = 8/20μs)
IEC 61000-4-5 peak pulse power (tp = 8/20μs)
Output load capacitance
30
A
900
W
CLOAD
CCON
CPOW
TA
0.1
0.1
0.1
–40
–65
100
µF
µF
µF
°C
°C
Input capacitance
50
VBUS_POWER capacitance
4.7
Operating free air temperature
Storage temperature
85
Tstg
150
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) The algebraic convention, whereby the most negative value is a minimum and the most positive value is a maximum.
(3) Thermal limits and power dissipation limits must be observed.
(4) 6.9 V or VBUS_CON + 0.3 V, whichever is smaller.
7.2 ESD Ratings
VALUE
±2000
±500
UNIT
Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1)
Charged-device model (CDM), per JEDEC specification JESD22-C101(2)
V(ESD)
Electrostatic discharge
V
IEC 61000-4-2 Contact Discharge
IEC 61000-4-2 Air-gap Discharge
VBUS_CON pin
VBUS_CON pin
±15000
±15000
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process. Manufacturing with
less than 500-V HBM is possible with the necessary precautions.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process. Manufacturing with
less than 250-V CDM is possible with the necessary precautions.
4
Copyright © 2014–2019, Texas Instruments Incorporated
TPD1S514x
www.ti.com.cn
ZHCSCE8F –APRIL 2014–REVISED MAY 2019
7.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
MIN
3.5
3.5
3.5
3.5
3.9
3.9
3.9
3.9
NOM
5
MAX
5.9
UNIT
VBUS_CON
Supply voltage from USB
connector
TPD1S514-1
TPD1S514-2
TPD1S514-3
TPD1S514
V
9
9.9
12
5
13.5
5.9
VBUS_SYS
Internal Supply DC voltage Rail
on the PCB
TPD1S514-1
TPD1S514-2
TPD1S514-3
TPD1S514
5
5.9
V
9
9.9
12
5
13.5
5.9
CLOAD
CCON
CPOWER
TA
Output load capacitance
Input capacitance
VBUS_SYS pin
VBUS_CON pin
VBUS_POWER pin
2.2
1
µF
µF
µF
°C
Capacitance on VBUS_POWER
Operating free-air temperature
1
–40
85
7.4 Thermal Information
TPD1S514 Family
THERMAL METRIC(1)
YZ (WCSP)
12 PINS
89
UNIT
RθJA
RθJC(top)
RθJB
ψJT
Junction-to-ambient thermal resistance
°C/W
°C/W
°C/W
°C/W
°C/W
Junction-to-case (top) thermal resistance
Junction-to-board thermal resistance
0.6
16.3
Junction-to-top characterization parameter
Junction-to-board characterization parameter
2.7
ψJB
16.2
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report, SPRA953.
7.5 Supply Current Consumption
over operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
DEVICE NAME
TPD1S514-1
TPD1S514-2
TPD1S514-3
TPD1S514
TYP
150
176
195
150
228
250
270
228
210
250
333
210
90
MAX UNIT
VBUS_CON = 5 V
245
VBUS_CON = 9 V
VBUS_CON = 12 V
VBUS_CON = 5 V
VBUS_CON = 5 V
VBUS_CON = 9 V
VBUS_CON = 12 V
VBUS_CON = 5 V
VBUS_SYS = 5 V
VBUS_SYS = 9 V
VBUS_SYS = 12 V
VBUS_SYS = 5 V
VBUS_SYS = 5 V
VBUS_SYS = 9 V
VBUS_SYS = 12 V
VBUS_SYS = 5 V
281
µA
335
Measured at VBUS_CON pin,
EN = 5 V
IVBUS_SLEEP
245
354
VBUS_CON Operating
Current Consumption
TPD1S514-1
TPD1S514-2
TPD1S514-3
TPD1S514
413
µA
456
Measured at VBUS_CON pin,
EN = 0 V and no load
IVBUS
354
354
TPD1S514-1
TPD1S514-2
TPD1S514-3
TPD1S514
424
µA
461
VBUS_SYS operating current Measured at VBUS_SYS pin,
consumption
IVBUS_SYS
VBUS_CON = Hi-Z, EN = 0 V
354
218
TPD1S514-1
TPD1S514-2
TPD1S514-3
TPD1S514
290
506
90
491
µA
696
Measured at VBUS_SYS pin,
VBUS_CON = Hi-Z, EN = 5 V
IHOST_LEAK
Host mode leakage current
218
Copyright © 2014–2019, Texas Instruments Incorporated
5
TPD1S514x
ZHCSCE8F –APRIL 2014–REVISED MAY 2019
www.ti.com.cn
7.6 Electrical Characteristics EN Pin
over operating free-air temperature range (unless otherwise noted)
PARAMETER
High-level input voltage
Low-level input voltage
Input leakage current
Input leakage current
TEST CONDITIONS
MIN
1.2
0
TYP
MAX
UNIT
V
VIH
VIL
IIL
EN
EN
EN
EN
VBUS_CON = 5 V
6
0.8
1
VBUS_CON = 5 V
V
VEN = 0 V, VBUS_CON = 5 V
VEN = 5 V, VBUS_CON = 5 V
µA
µA
IIH
10
7.7 Thermal Shutdown Feature
over operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX UNIT
VBUS_CON = 5 V, EN = 0 V, Junction temperature
TSHDN
Thermal shutdown
decreases from thermal shutdown level until the nFET
switch turns off.
145
°C
VBUS_CON = 5 V, EN = 0 V, Junction temperature
decreases from thermal shutdown level until the nFET
switch turns on.
Thermal shutdown hysteresis
25
°C
7.8 Electrical Characteristics nFET Switch
T = 25°C
PARAMETER
TEST CONDITIONS
MIN TYP MAX
UNIT
VBUS_CON = 5 V, IOUT = 1 A
TPD1S514-1
TPD1S514-2
TPD1S514-3
TPD1S514
39
39
39
39
50
50
50
50
VBUS_CON = 9 V, IOUT = 1 A
VBUS_CON = 12 V, IOUT = 1 A
VBUS_CON = 5 V, IOUT = 1 A
RON
Switch ON resistance
mΩ
6
Copyright © 2014–2019, Texas Instruments Incorporated
TPD1S514x
www.ti.com.cn
ZHCSCE8F –APRIL 2014–REVISED MAY 2019
7.9 Electrical Characteristics OVP Circuit
T = 25°C
PARAMETER
TEST CONDITIONS
TPD1S514-1
MIN
5.90
9.9
TYP
5.95
9.98
MAX
5.99
10.05
14
UNIT
TPD1S514-2
TPD1S514-3
TPD1S514
Input voltage protection
threshold
VBUS_CON increasing
from 0 V to 20 V
VOVP
VBUS_CON
V
13.5 13.75
5.90
5.95
100
100
100
20
5.99
TPD1S514-1
TPD1S514-2
TPD1S514-3
TPD1S514
VBUS_CON decreasing
from 20 V to 0 V
VHYS_OVP
Hysteresis on OVP
VBUS_CON
mV
VUVLO
Input under voltage lockout
Hysteresis on UVLO
VBUS_CON
VBUS_CON
VBUS_CON voltage rising from 0 V to 5 V
2.7
3.1
3.5
V
Difference between rising and falling UVLO
thresholds
VHYS_UVLO
80
mV
VUVLO_FALLING
VUVLO_SYS
Input undervoltage lockout
VBUS_CON
VBUS_SYS
VBUS_CON voltage falling from 5 V to 0 V
VBUS_SYS voltage rising from 0 V to 5 V
2.6
2.8
3.0
3.7
3.4
4.3
V
V
VBUS_SYS undervoltage lockout
Difference between rising and falling UVLO
thresholds on VBUS_SYS
VHYS_UVLO_SYS
VBUS_SYS UVLO Hysteresis
VBUS_SYS
VBUS_SYS
500
3.0
mV
V
VUVLO_SYS_FALLING
VBUS_SYS undervoltage lockout
VBUS_SYS voltage falling from 5 V to 0 V
2.6
3.4
7.10 Electrical Characteristics VBUS_POWER Circuit
over operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
TPD1S514-1
TPD1S514-2
TPD1S514-3
TPD1S514
MIN
TYP MAX
UNIT
5.0
5.0
5.5
5.5
VCLAMP
Output voltage on VBUS_POWER during OVP
VBUS_CON = 20 V
V
5.0
5.5
6.48
4.95
4.95
4.95
4.98
6.68
TPD1S514-1
TPD1S514-2
4.7
4.7
4.7
4.7
VBUS_CON = 5 V,
Output voltage on VBUS_POWER during normal
operation
VBUS_POWER
V
IBUS_POWER = 1 mA;
TPD1S514-3
TPD1S514
IBUS_POWER_MAX
Output current on VBUS_POWER
VBUS_CON = 5 V – 15 V
3
mA
Copyright © 2014–2019, Texas Instruments Incorporated
7
TPD1S514x
ZHCSCE8F –APRIL 2014–REVISED MAY 2019
www.ti.com.cn
7.11 Timing Requirements
over operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN TYP
MAX UNIT
TPD1S514-1
TPD1S514-2
TPD1S514-3
TPD1S514
USB charging turn-ON
Delay
Measured from EN asserted LOW to nFET
begins to Turn ON, excludes soft-start time
tDELAY
20
ms
TPD1S514-1
TPD1S514-2
TPD1S514-3
TPD1S514
Force 5 V on VBUS_CON, measured from
VBUS_SYS rises from 10% to 90% (with 1 MΩ
USB charging rise time
(soft-start delay)
tSS
3.5
5.5
ms
µs
load/ NO CLOAD
)
TPD1S514-1
TPD1S514-2
TPD1S514-3
TPD1S514
Measured from EN asserted High to VBUS_SYS
falling to 10% with RLOAD = 10 Ω and No CLOAD
on VBUS_SYS
USB charging turn-OFF
time
tOFF_DELAY
OVER VOLTAGE PROTECTION
tOVP_response OVP response time
Measured from OVP Condition to FET Turn OFF(1)
100
ns
(1) Specified by design, not production tested
6
4
2
0
/EN
VBUS_SYS
VBUS_Power
-2
-5E-3
000E+0
5E-3
10E-3
15E-3
20E-3
25E-3 30E-3
Time (s)
C002
Figure 1. TPD1S514-1 Response to Set EN Low
8
Copyright © 2014–2019, Texas Instruments Incorporated
TPD1S514x
www.ti.com.cn
ZHCSCE8F –APRIL 2014–REVISED MAY 2019
7.12 TPD1S514-1 Typical Characteristics
400
300
200
1.060
1.040
1.020
1.000
0.980
0.960
0.940
95C
100
0
25C
-50C
VOVP
5
10
15
20
25
30
-50
-25
0
25
50
75
100
VBUS_CON (V)
C006
Temperature (°C)
C013
Figure 2. In Supply Current vs Supply Voltage
Figure 3. Normalized VOVP vs Temperature
2.00
1.80
1.60
1.40
1.20
1.00
0.80
0.60
0.40
0.20
0.00
1.10
1.05
1.00
0.95
0.90
3A
2A
1.5A
-50
0
50
Temperature (ºC)
100
0.0
1.0
2.0
3.0
Current (A)
C004
C005
Figure 4. Normalized RON vs Temperature
Figure 5. Normalized RON vs Output
5.1
5.0
4.9
4.8
4.7
4.6
4.5
5.1
5.0
4.9
4.8
4.7
4.6
4.5
0 mA Load
3 mA Load
0
3
6
9
12
0
3
6
9
12
VBUS_CON (V)
VBUS_CON (V)
C008
C009
Figure 6. VBUS_POWER vs VBUS_CON With No Load
Figure 7. VBUS_POWER vs VBUS_CON With 3 mA Load
Copyright © 2014–2019, Texas Instruments Incorporated
9
TPD1S514x
ZHCSCE8F –APRIL 2014–REVISED MAY 2019
www.ti.com.cn
TPD1S514-1 Typical Characteristics (continued)
40
120
100
80
60
40
20
0
Open Circuit
Voltage
30
VBUS_CON (V)
20
VBUS_CON (I)
VBUS_SYS (V)
10
0
-40E-6
000E+0
40E-6
Time (s)
80E-6
120E-6
-25E-6
25E-6
75E-6
125E-6
175E-6
Time (s)
C011
C010
Figure 8. 100 V Surge With Device
Figure 9. 100 V Surge Without Device
10
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8 Detailed Description
8.1 Overview
The TPD1S514 Family provides single-chip ESD, surge, and over voltage protection solutions for portable USB
Charging and Host interfaces. Each device offers over voltage protection at the VBUS_CON pin up to 30-V DC. The
TPD1S514 Family offers an ESD and Precision Clamp for the VBUS_CON pin, thus eliminating the need for
external TVS clamp circuits in the application.
Each device has an internal oscillator and charge pump which controls turning ON the internal nFET switch. The
internal oscillator controls the timers which enable the charge pump. If VBUS_CON is less than VOVP, the internal
charge pump is enabled. After a 20 ms internal delay, the charge-pump starts-up, and turns ON the internal
nFET switch through a soft start. If at any time VBUS_CON rises above VOVP, the nFET switch is turned OFF within
100 ns.
The TPD1S514 Family of devices also have a VBUS_POWER pin which follows VBUS_CON up to 4.9 V at 3 mA
(except for TPD1S514, which follows VBUS_CON up to 6.48 V, after which it is regulated to that voltage) to power
the system from VBUS_CON. In the case where the system battery state cannot power the system, voltage from an
external charger can be provided to power the system. VBUS_POWER is supplied by an always on LDO regulator
supplied by VBUS_CON. VBUS_POWER output voltage remains regulated to 4.9 V (except for TPD1S514, which
follows VBUS_CON up to 6.48 V, after which it is regulated to that voltage) at up to 30-V DC on VBUS_CON and
during IEC 61000-4-5 surge events of up to 100 V open circuit voltage on VBUS_CON
.
8.2 Functional Block Diagram
VBUS_CON
VBUS_POWER
VIN
VOUT
LDO
POR
Oscillator
Q-Pump
Gate Drive
Surge
Clamp
VBUS_SYS
TSD
GND
BG
Reference
EN Buffer
Digital
Core
EN
OVP
+
-
VREF
8.3 Feature Description
8.3.1 Over Voltage Protection on VBUS_CON up to 30 V DC
When the VBUS_CON voltage rises above VOVP, the internal nFET switch is turned OFF, removing power from the
system side. VBUS_CON can tolerate up to 30-V DC. The response to over voltage is very rapid, with the nFET
switch turning off in less than 100 ns. When the VBUS_CON voltage returns back to below VOVP – VHYS_OVP, the
nFET switch is turned ON again after an internal delay of tOVP_RECOV (tDELAY). This time delay ensures that the
VBUS_CON supply has stabilized before turning the switch back on. After tOVP_RECOV, the TPD1S514 Family device
turns on the nFET through a soft start. Once the OVP condition is cleared the nFET is turned completely ON.
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Feature Description (continued)
8.3.2 Precision OVP (< ±1% Tolerance)
1% OVP trip threshold accuracy allows use of the entire input charging range while protecting sensitive system-
side components from over voltage conditions.
8.3.3 Low RON nFET Switch Supports Host and Charging Mode
The nFET switch has a total on resistance (RON) of 39 mΩ. This equates to a voltage drop of less than 140 mV
when charging at the maximum 3.5 A current level. Such low RON helps provide maximum potential to the
system as provided by an external charger or by the system when in Host Mode.
8.3.4 VBUS_POWER, TPD1S514-1, TPD1S514-2, TPD1S514-3
The VBUS_POWER pin provides up to 3 mA and 5 V for powering the system using VBUS_CON. VBUS_POWER follows
VBUS_CON after 3.5 V and up to the regulated 5 V. In the case where the system battery state cannot power the
system, voltage from an external charger can power the system. VBUS_POWER is supplied by an always on LDO
regulator supplied by VBUS_CON. The VBUS_POWER output voltage remains regulated to 5 V at up to 30-V DC on
VBUS_CON and during IEC 61000-4-5 surge events of up to 100 V.
8.3.5 VBUS_POWER, TPD1S514
The VBUS_POWER pin provides up to 3 mA and 6.48 V for powering the system using VBUS_CON. VBUS_POWER follows
VBUS_CON after 3.5 V and up to the regulated 6.48 V. In the case where the system battery state cannot power
the system, voltage from an external charger can be provided to power the system. VBUS_POWER is supplied by an
always on LDO regulator supplied by VBUS_CON. The VBUS_POWER output voltage remains regulated to 6.48 V at up
to 30-V DC on VBUS_CON and during IEC 61000-4-5 surge events of up to 100 V.
8.3.6 Powering the System When Battery is Discharged
There are two methods for powering the system under a dead battery condition. Case 1: The EN pin can be tied
to ground so that the nFET is always ON (when VUVLO < VBUS_CON < VOVP) and an external charger can power
VBUS. Case 2: If EN is controlled by a Power Management Unit (PMIC) or other logic, VBUS_POWER can be used to
power the PMIC. In Case 2, once the device is enabled, tDELAY + tSS, work together to meet the USB Inrush
Current compliance.
8.3.7 ±15 kV IEC 61000-4-2 Level 4 ESD Protection
The VBUS_CON pin can withstand ESD events up to ±15 kV Contact and Air-Gap. An ESD clamp diverts the
current to ground.
8.3.8 100 V IEC 61000-4-5 µs Surge Protection
The VBUS_CON pin can withstand surge events up to 100 V open circuit voltage (VPP), or 900 W. A Precision
Clamp diverts the current to ground and active circuitry switches OFF the nFET earlier than 100 ns before an
over voltage can get through to VBYS_SYS. The ultra-fast response time of the TPD1S514 Family holds the voltage
on VBUS_SYS to less than VOVP during surge events of up to 100 VPP
.
8.3.9 Startup and OVP Recovery Delay
Upon startup or recovering from an over voltage, the TPD1S514 Family of devices have a built in startup delay.
An internal oscillator controls a charge pump to control the delay. Once a manufactured pre-programmed time,
tDELAY, has elapsed, the charge pump is enabled which turns ON the nFET. A manufactured pre-programmed
soft start, tSS, is used when turning ON the nFET. Once the device is enabled, these start delays, tDELAY + tSS
,
work together to meet the USB Inrush Current compliance.
8.3.10 Thermal Shutdown
The TPD1S514 Family has an over-temperature protection circuit to protect against system faults or improper
use. The basic function of the thermal shutdown (TSD) circuit is to sense when the junction temperature has
exceeded the absolute maximum rating and shuts down the device until the junction temperature has cooled to a
safe level.
12
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8.4 Device Functional Modes
8.4.1 Operation With VBUS_CON < 3.5 V (Minimum VBUS_CON
)
The TPD1S514 Family operates normally (nFET ON) with input voltages above 3.5 V. The maximum UVLO
voltage is 3.5 V and the device will operate at input voltages above 3.5 V. The typical UVLO voltage is 3.1 V and
the device may operate at input voltages above that point. The device may also operate at input voltages as low
as 2.7 V, the minimum UVLO. At input voltages between 0.6 V and 1.2 V, the state of output pins may not be
controlled internally.
8.4.2 Operation With VBUS_CON > VOVP
The TPD1S514 Family operates normally (nFET ON) with input voltages below VOVP_min. The typical OVP
voltage is VOVP_TYP and the device may operate at input voltages below that point. The device may also operate
at input voltages as high as VOVP_MAX
.
Table 1. VOVP Values
VOVP
TYP
5.95
9.98
13.75
5.95
DEVICE NAME
MIN
5.9
MAX
5.99
10.05
14
TPD1S514-1
TPD1S514-2
TPD1S514-3
TPD1S514
9.9
13.5
5.9
5.99
8.4.3 OTG Mode
The TPD1S514 Family of devices UVLO and OVP voltages are referenced to VBUS_CON voltage. In OTG mode,
VBUS_SYS is driving the VBUS_CON. Under this situation, initially VBUS_CON is powered through the body diode of the
nFET by VBUS_SYS. Once the UVLO threshold on VBUS_CON is met, the nFET turns ON. If there is a short to
ground on VBUS_CON the OTG supply is expected to limit the current.
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9 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
9.1 Application Information
The TPD1S514 Family of devices offer VBUS port protection implementing UVLO and OVP, with an LDO supplied
VBUS_POWER pin to regulate an output supply pin of 3 mA at 5 V (except for TPD1S514, which follows VBUS_CON up
to 6.48 V, after which it is regulated to that voltage). The VBUS_POWER pin can be used to power the system from
an external source on VBUS_CON in case the system’s battery state cannot power the system.
9.2 Typical Applications
9.2.1 TPD1S514-1 USB 2.0/3.0 Case 1: Always Enabled
The EN pin can be tied to ground so that the nFET is ON when VUVLO < VBUS_CON < VOVP and an external
charger can power VBUS. VBUS_POWER should be tied to ground with a 1-μF capacitor for LDO stability. USB Inrush
Current compliance tests will need to be handled by the rest of the system since the start delays tDELAY and tSS
implement only after the device changes from disabled to enabled, or after any UVLO or OVP event.
TPD1S514x
VBUS_POWER
USB
connector
VBUS
VBUS
VOUT
VBUS_CON
VBUS_SYS
System load
D-
D+
EN
GND
2.2 μF
1 μF
BAT
1 μF
ID
GND
Battery
+
D-
D+
ID
PMIC
TPD4E110
Figure 10. Always on, TPD1S514-1
9.2.1.1 Design Requirements
For this example, use the following input parameters from Table 2.
Table 2. Design Parameters
DESIGN PARAMETERS
Signal range on VBUS_CON
Signal range on VBUS_SYS
Signal on EN
EXAMPLE VALUE
3.5 V – 5.9 V
3.9 V – 5.9 V
Tie to system ground plane
14
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9.2.1.2 Detailed Design Procedure
To begin the design process the designer needs to know the VBUS voltage range.
9.2.1.2.1 VBUS Voltage Range
The UVLO trip-point is a maximum 3.5 V and the OVP trip-point is a minimum 5.9 V. This provides some
headroom for the USB 2.0 specified minimum 4.4 V (Low-power) or 4.75 V (Full-power) and 5.25 V maximum; or
the USB 3.0 specified minimum 4.45 V and 5.25 V maximum.
9.2.1.2.2 Discharged Battery
Connecting EN to ground sets the part active at all times. OVP and UVLO are always active, even when the
system battery is fully discharged. In the case of a discharged system battery, VBUS_SYS can be used to power
the system when a source with voltage between VUVLO and VOVP is attached to VBUS_CON
.
9.2.1.3 Application Curves
8
6
4
2
0
VBUS_CON_Voltage (V)
VBUS_SYS_Voltage (S)
/EN_Voltage (S)
-2
-20E-3
-10E-3
000E+0
10E-3
20E-3
30E-3
40E-3
50E-3
Time (s)
C001
Figure 11. VBUS_SYS Recovery Time From Over Voltage on VBUS_CON
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9
6
3
0
VBUS_CON
VBUS_SYS
-3
-100E-9
000E+0
100E-9
200E-9
300E-9
400E-9
500E-9
Time (s)
C003
Figure 12. OVP Response
16
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9.2.2 TPD1S514-1 USB 2.0/3.0 Case 2: PMIC Controlled EN
The TPD1S514 Family offers more flexibility to system designers to power up the system during a dead battery
condition. Refer to Figure 13, the VBUS_POWER pin supplies 4.95 V and 3 mA to power the PMIC in a dead battery
condition. Regardless of EN state, VBUS_POWER is available to the PMIC. Utilizing this power, the PMIC can
enable the TPD1S514 Family of devices when a valid VBUS_CON voltage is present.
TPD1S514x
VBUS_POWER
EN
USB
Conenctor
Power
VOUT
EN out
VBUS
System load
VBUS
VBUS_CON
VBUS_SYS
D-
D+
GND
2.2 μF
1 μF
BAT
1 μF
ID
GND
Battery
+
D-
D+
ID
PMIC
TPD4E110
Figure 13. PMIC Controlled EN, TPD1S514-1
9.2.2.1 Design Requirements
For this example, use the following table as input parameters:
Table 3. Design Parameters
DESIGN PARAMETERS
Signal range on VBUS_CON
Signal range on VBUS_SYS
Drive EN low (enabled)
EXAMPLE VALUE
3.5 V – 5.9 V
3.9 V – 5.9 V
0 V – 0.8 V
Drive EN high (disabled)
1.2 V – 6.0 V
9.2.2.2 Detailed Design Procedure
To begin the design process, some parameters must be decided upon. The designer needs to know the
following:
•
•
VBUS voltage range
PMIC power requirement
9.2.2.2.1 VBUS Voltage Range
The UVLO trip-point is a maximum 3.5 V and the OVP trip-point is a minimum 5.9 V. This provides some
headroom for the USB 2.0 specified minimum 4.4 V (Low-power) or 4.75 V (Full-power) and 5.25 V maximum; or
the USB 3.0 specified minimum 4.45 V and 5.25 V maximum.
9.2.2.2.2 PMIC Power Requirement
The VBUS_POWER pin can source up to 3 mA of current and maintain a minimum 4.8 V, 4.95 V typical.
TPD1S514-1 design provides an LDO regulator supplied voltage source which can be used to provide power to a
PMIC when its internal battery supplied power is unavailable. When selecting a matching PMIC, ensure its power
requirement can be met by the VBUS_POWER pin if designing for this scenario.
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9.2.2.2.3 Discharged Battery
Powering the PMIC from VBUS_POWER allows logic control of the EN pin to set TPD1S514-1 active and begin
charging the battery and powering up the rest of the system.
9.2.2.3 Application Curve
8
6
4
2
0
VBUS_CON_Voltage (V)
VBUS_SYS_Voltage (S)
/EN_Voltage (S)
-2
-20E-3
-10E-3
000E+0
10E-3
20E-3
30E-3
40E-3
50E-3
Time (s)
C001
Figure 14. VBUS_SYS Recovery Time From Over Voltage on VBUS_CON
10 Power Supply Recommendations
The TPD1S514 Family is designed to receive power from a USB 3.0 (or lower) VBUS source. It can operate
normally (nFET ON) between a minimum 3.5 V and a maximum VOVP_MIN V. Thus, the power supply (with a
ripple of VRIPPLE) requirement for the TPD1S514 Family of devices to be able to switch the nFET ON is between
3.5 V + VRIPPLE and VOVP_MIN – VRIPPLE, where VOVP_MIN is:
Table 4. VOP_MIN Values
DEVICE NAME
TPD1S514-1
VOVP_MIN
5.90 V
9.9 V
TPD1S514-2
TPD1S514-3
TPD1S514
13.5 V
5.90 V
18
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11 Layout
11.1 Layout Guidelines
•
The optimum placement is as close to the connector as possible.
–
EMI during an ESD event can couple from the trace being struck to other nearby unprotected traces,
resulting in early system failures.
–
The PCB designer needs to minimize the possibility of EMI coupling by keeping any unprotected traces
away from the protected traces which are between the TVS and the connector.
•
•
Route the protected traces as straight as possible.
Eliminate any sharp corners on the protected traces between the TVS and the connector by using rounded
corners with the largest radii possible.
–
Electric fields tend to build up on corners, increasing EMI coupling.
11.2 Layout Example
VIA to Power Ground Plane
Power Ground
Power Ground
When designing layout for the TPD1S514 Family, note that VBUS_CON and VBUS_SYS pins allow extra wide traces for
good power delivery. In the example shown, these pins are routed with 50 mil (1.27 mm) wide traces. Place the
VBUS_CON, VBUS_SYS, and VBUS_POWER capacitors as close to the pins as possible. Use external and internal ground
planes and stitch them together with VIAs as close to the GND pins of TPD1S514 as possible. This allows for a low
impedance path to ground so that the device can properly dissipate any surge or ESD events.
Figure 15. Layout Recommendation
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12 器件和文档支持
12.1 社区资源
The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.
12.2 商标
E2E is a trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
12.3 静电放电警告
ESD 可能会损坏该集成电路。德州仪器 (TI) 建议通过适当的预防措施处理所有集成电路。如果不遵守正确的处理措施和安装程序 , 可
能会损坏集成电路。
ESD 的损坏小至导致微小的性能降级 , 大至整个器件故障。 精密的集成电路可能更容易受到损坏 , 这是因为非常细微的参数更改都可
能会导致器件与其发布的规格不相符。
12.4 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
13 机械、封装和可订购信息
以下页面包含机械、封装和可订购信息。这些信息是指定器件的最新可用数据。数据如有变更，恕不另行通知，且
不会对此文档进行修订。如需获取此数据表的浏览器版本，请查阅左侧的导航栏。
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PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
TPD1S514-1YZR
TPD1S514-2YZR
TPD1S514-3YZR
ACTIVE
ACTIVE
ACTIVE
DSBGA
DSBGA
DSBGA
YZ
YZ
YZ
12
12
12
3000 RoHS & Green
3000 RoHS & Green
3000 RoHS & Green
SNAGCU
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
-40 to 85
-40 to 85
-40 to 85
RH5141
SNAGCU
SNAGCU
RH5142
RH5143
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
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In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
9-May-2019
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
TPD1S514-1YZR
TPD1S514-2YZR
TPD1S514-3YZR
DSBGA
DSBGA
DSBGA
YZ
YZ
YZ
12
12
12
3000
3000
3000
180.0
180.0
180.0
8.4
8.4
8.4
1.39
1.39
1.39
2.09
2.09
2.09
0.75
0.75
0.75
4.0
4.0
4.0
8.0
8.0
8.0
Q2
Q2
Q2
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
9-May-2019
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SPQ
Length (mm) Width (mm) Height (mm)
TPD1S514-1YZR
TPD1S514-2YZR
TPD1S514-3YZR
DSBGA
DSBGA
DSBGA
YZ
YZ
YZ
12
12
12
3000
3000
3000
182.0
182.0
182.0
182.0
182.0
182.0
20.0
20.0
20.0
Pack Materials-Page 2
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