TPA6166A2 [TI]
具有附件检测的 43mW 立体声模拟输入耳机放大器;
| 型号： | TPA6166A2 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 具有附件检测的 43mW 立体声模拟输入耳机放大器 放大器 |
| 文件： | 总51页 (文件大小：1602K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
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TPA6166A2
ZHCSDD5B –MARCH 2014–REVISED JANUARY 2015
TPA6166A2 3.5mm 插孔检测和耳机接口 IC
1 特性
3 说明
1
•
超低功耗、高性能 DirectPath™ G 类耳机放大器
TPA6166A2这款单芯片耳机接口 IC 可轻松检测最终用
户插入到耳机插孔的设备型号，同时提供出色的音质。
此器件将高性能的低功耗 DirectPath 可变衰减 G 类立
体声耳机放大器、具有偏置电路的可变增益麦克风前置
放大器以及高级附件检测电路全部集成在一个微型
5mm × 5mm 引脚、0.4mm 间距 WCSP 封装上，因此
有助于减小最终产品的尺寸。
–
–
中央接地输出免除了对隔直电容的需求
1% 总谐波失真+噪声 (THD+N) 时，每通道
30mW（32Ω/通道）
–
–
–
–
–42dB 至 +6dB 音量控制
–42dB 增益下的输出噪声为 2.0μV
91dB 电源抑制比 (PSRR)
接地环路抑制电路，用于减少串扰
G 类耳机放大器可根据音频信号电平调整耳机放大器
的供电电压，从而以最大程度延长电池使用寿命。 凭
借 8µV 输出噪声（0dB 时）和 91dB 的 PSRR，该耳
机放大器可提供出色的音频性能。 DirectPath 免除了
对隔直电容的需求。 耳机前置放大器具有两种可编程
增益（12dB 和 24dB），以及 3.4µV 输入参考噪声。
•
•
全差分麦克风前置放大器，具有可变增益和 3.4µV
低噪声
–
–
集成了交流耦合电容
接地环路抑制电路，用于减少耳机与麦克风间的
串扰
两种麦克风偏置电压可供选择：2.0V 和 2.6V
耳机偏置电压有两种可编程设置：2V 和 2.6V。偏置输
出最高可驱动 1.2mA 的电流，并且兼具 2µV 的低输出
噪声和 92dB PSRR，可为无线耳机提供出色的电源噪
声抑制效果。
–
–
92dB 电源抑制比 (PSRR)
集成了可编程的麦克风偏置电阻
•
•
高级的附件插入、移除和型号检测功能
采用 10 位逐次逼近寄存器 (SAR) 模数转换器
(ADC) 提供无源多按钮支持
高级附件检测算法可自动对 6 种支持的附件进行检
测，并且能够使能或禁止内部元件。
–
实现了专有方案，可减少耳机接地返回路径上存
在有限电阻时音频播放信号所导致的错误
器件信息(1)
•
在（EVM 上的）插孔连接引脚上集成了 4 级 IEC
静电放电 (ESD) 保护
器件型号
TPA6166A2
封装
WSCP (25)
封装尺寸（标称值）
•
•
•
•
超低功耗芯片关断模式
I2C 接口
2.50mm x 2.50mm
(1) 要了解所有可用封装，请见数据表末尾的可订购产品附录。
短路保护功能
简化电路原理图
0.4mm 间距 25 焊球晶圆级芯片封装 (WCSP)
CPVDD CPVSS C1P C1N VDD MICVDD
2 应用
Class-G
RING1
Stereo Headphone
INL
INR
•
•
•
智能手机和无线耳机
Amplifier
TIP
ESD
Prot.
便携式平板电脑
Mic
Bias
JACK_SENSE
RING2
笔记本电脑和扩展坞
Switch
Matrix
and
SLEEVE
MOUTP
MOUTN
Detection
Circuit
SDA
SCL
IRQ
Digital
SAR
ADC
Interface
and
Control
GND1
PGND
GND2
1
PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not necessarily include testing of all parameters.
English Data Sheet: SLAS997
TPA6166A2
ZHCSDD5B –MARCH 2014–REVISED JANUARY 2015
www.ti.com.cn
目录
7.3 Feature Description................................................. 13
7.4 Device Functional Modes........................................ 19
7.5 Register Maps......................................................... 23
Application and Implementation ........................ 38
8.1 Application Information............................................ 38
8.2 Typical Application .................................................. 38
Power Supply Recommendations...................... 40
9.1 Decoupling Capacitors............................................ 40
1
2
3
4
5
6
特性.......................................................................... 1
应用.......................................................................... 1
说明.......................................................................... 1
修订历史记录 ........................................................... 2
Pin Configuration and Functions......................... 3
Specifications......................................................... 4
6.1 Absolute Maximum Ratings ...................................... 4
6.2 ESD Ratings.............................................................. 4
6.3 Recommended Operating Conditions....................... 4
6.4 Thermal Information.................................................. 4
6.5 Electrical Characteristics........................................... 5
6.6 Electrical Characteristics, Audio Amplifiers............... 6
6.7 Electrical Characteristics, Mic Preamplifier and Bias 7
6.8 Timing Requirements................................................ 8
6.9 Typical Characteristics.............................................. 9
Detailed Description ............................................ 13
7.1 Overview ................................................................. 13
7.2 Functional Block Diagram ....................................... 13
8
9
10 Layout................................................................... 41
10.1 Layout Guidelines ................................................. 41
10.2 Layout Example .................................................... 42
11 器件和文档支持 ..................................................... 43
11.1 开发支持................................................................ 43
11.2 商标....................................................................... 43
11.3 静电放电警告......................................................... 43
11.4 术语表 ................................................................... 43
12 机械封装和可订购信息 .......................................... 43
7
4 修订历史记录
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision A (June 2014) to Revision B
Page
•
已添加 引脚配置和功能部分，ESD 额定值表，特性描述部分，器件功能模式，应用和实施部分，电源相关建议部分，
布局部分，器件和文档支持部分以及机械、封装和可订购信息部分........................................................................................ 1
Changes from Original (January 2014) to Revision A
Page
•
•
•
已更改 至最新数据表格式 ....................................................................................................................................................... 1
已添加 规范和应用信息........................................................................................................................................................... 1
已更改 状态至量产数据........................................................................................................................................................... 1
2
Copyright © 2014–2015, Texas Instruments Incorporated
TPA6166A2
www.ti.com.cn
ZHCSDD5B –MARCH 2014–REVISED JANUARY 2015
5 Pin Configuration and Functions
YFF Package
Top View
A1
GND1
B1
A2
INR
A3
A4
A5
INL
B3
IRQ
CPVDD JACK_SENSE
B2
B4
B5
NC*
GND2
MOUTN
TIP
C1
CPVSS
D1
C2
SCL
D2
C3
GND
D3
C4
MOUTP
D4
C5
RING1
D5
C1N
E1
SDA
E2
PGND
E3
NC*
MICVDD
E5
E4
C1P
PGND
VDD
RING2
SLEEVE
All NC pins should be left floating. Do not connect them to GND.
Pin Functions
PIN
I/O / TYPE
DESCRIPTION
NAME
GND1
INR
NO.
A1
A2
A3
A4
P
I
Analog / digital ground 1
Headphone right channel input
Headphone left channel input
INL
I
CPVDD
I
Headphone charge-pump positive supply (internally generated). Connect a 1-µF capacitor
to ground.
JACK_SENSE
A5
I/O
Connect to headset jack terminal 5 (for mechanical switch). If mechanical switch is not
available, then this terminal can be kept floating.
NC (Floating)
GND2
B1
B2
B3
B4
B5
C1
O
I
Leave floating (no connection)
Ground 2 - Connect to ground 1 on board.
Active low interrupt output
IRQ
O
O
O
I
MOUTN
TIP
Microphone preamplifier negative output
Left headphone / line output. Connect to headset jack TIP (terminal 1).
CPVSS
Headphone charge-pump negative supply (internally generated). Connect a 1-µF capacitor
to ground.
SCL
C2
C3
I
I
I2C clock line
GND
Connect to ground
MOUTP
RING1
C1N
C4
O
O
P
Microphone preamplifier positive output
Right headphone / line output. Connect to headset jack RING1 (terminal 2).
Charge pump flying capacitor positive terminal
I2C data line
C5
D1
SDA
D2
I/O
P
PGND
NC (Floating)
MICVDD
C1P
D3, E2
D4
Power ground
O
P
Leave floating (no connection)
Analog supply
D5
E1
P
Charge pump flying capacitor negative terminal
Analog / digital supply
VDD
E3
P
RING2
SLEEVE
E4
I/O
I/O
Connect to headset jack RING2 (terminal 3)
Connect to headset jack SLEEVE (terminal 4)
E5
Copyright © 2014–2015, Texas Instruments Incorporated
3
TPA6166A2
ZHCSDD5B –MARCH 2014–REVISED JANUARY 2015
www.ti.com.cn
6 Specifications
6.1 Absolute Maximum Ratings
over operating temperature range, TA = 25°C (unless otherwise noted)
(1)
MIN
–0.3
–0.3
MAX
2
UNIT
V
Supply voltage, VDD
Microphone supply voltage, MICVDD
Output continuous total power dissipation
Storage temperature, Tstg
3.9
V
See Thermal Information
–65 85
°C
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
6.2 ESD Ratings
VALUE
±2000
±500
UNIT
Human body model (HBM), per ANSI/ESDA/JEDEC JS-001(1)
V(ESD)
Electrostatic discharge
V
Charged-device model (CDM), per JEDEC specification JESD22-
C101(2)
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
6.3 Recommended Operating Conditions
MIN
MAX UNIT
VDD
Supply voltage
1.7
2.4
1.9
3.6
85
V
V
MICVDD
TA
Microphone supply voltage
Operating temperature
–25
°C
pF
Line Driver Application, RL = 10 kΩ, AV ≥ 0 dB, specified by design
470
470
Maximum load
capacitance
Line Driver Application, RL = 10 kΩ, AV ≤ 0 dB, LO_EXT_STAB = 1,
specified by design
CL,Max
Headphone Application, RL = 32 Ω, specified by design
200
150
TJ
Operating junction temperature
–25
°C
6.4 Thermal Information
TPA6166A2
THERMAL METRIC(1)
YFF (WSCP)
UNIT
25 PINS
67
RθJA
RθJC(top)
RθJB
ψJT
Junction-to-ambient thermal resistance
Junction-to-case (top) thermal resistance
Junction-to-board thermal resistance
18
38
°C/W
Junction-to-top characterization parameter
Junction-to-board characterization parameter
0.1
ψJB
36
(1) For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.
4
Copyright © 2014–2015, Texas Instruments Incorporated
TPA6166A2
www.ti.com.cn
ZHCSDD5B –MARCH 2014–REVISED JANUARY 2015
6.5 Electrical Characteristics
VDD =00 1.8 V, MICVDD = 3.0 V, AV = 0 dB, CIN = 0.47 µF, CFLY = 1.0 μF, CCPVDD = CCPVSS = 1.0 μF, RHP = 32 Ω, outputs in
phase, TA = 25°C (unless otherwise noted).
PARAMETER
Input logic high
Input logic low
Output logic low
TEST CONDITIONS
MIN
TYP
MAX
UNIT
VIH
VIL
SDA, SCL
SDA, SCL
IRQ
1.4
0.4
V
VOL
IOL = 3 mA pullup current
0.2×VDD
Logic high input
leakage current
|IIH
|
SDA, SCL
SDA, SCL
IRQ
1
1
1
Logic low input
leakage current
|IIL|
µA
Logic high output
leakage current
|IOH
|
VIRQ = 3.3 V
IVDD
2.38
0.21
4.91
3.74
0.21
7.35
2.36
0.96
6.35
3.68
0.96
8.74
10.84
1.05
22.7
150.9
1.05
278.3
108.1
1.06
197.8
mA
mA
mW
mA
mA
mW
mA
mA
mW
mA
mA
mW
µA
Audio playback (both
channels), no signal into 32 Ω
IMICVDD
(1)
PCONS
IVDD
Audio playback (both
channels), 100-µW output into
32 Ω
IMICVDD
(1)
PCONS
IVDD
2-way call, no signal into 32 Ω
IMICVDD
(1)
PCONS
IVDD
2-way call, 100-µW output into
32 Ω
Power consumption
IMICVDD
(1)
PCONS
IVDD
Accessory not inserted
IMICVDD
µA
(1)
PCONS
µW
µA
IVDD
Accessory not inserted,
mechanical switch is open
(JACK_SENSE=1)
IMICVDD
µA
(1)
PCONS
µW
µA
IVDD
Accessory inserted and in sleep
mode
IMICVDD
µA
(1)
PCONS
µW
(1) Total power consumption from VDD and MICVDD.
Copyright © 2014–2015, Texas Instruments Incorporated
5
TPA6166A2
ZHCSDD5B –MARCH 2014–REVISED JANUARY 2015
www.ti.com.cn
6.6 Electrical Characteristics, Audio Amplifiers
VDD = 1.8 V, MICVDD = 3.0 V, AV = 0 dB, CIN = 0.47 µF, CFLY = 1.0 μF, CCPVDD = CCPVSS = 1.0 μF, RL = 32 Ω, outputs in
phase, TA = 25°C (unless otherwise noted).
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX UNIT
HEADPHONE AND LINE-OUT AMPLIFIERS
Programmable gain range
-42
5.0
-43
6
7.0
-41
dB
dB
dB
dB
dB
dB
AV,Max
AV = 6 dB
6.0
-42
1
AV,Min
AV = -42 dB
Gain step size
-42 dB ≤ AV ≤ 6 dB
ΔAV
Gain matching
Between left and right channels
–0.5
0.5
Mute attenuation
103.7
29.1
THD+N = 1%, f = 1 kHz, RL = 32 Ω, single
channel on
THD+N = 1%, f = 1 kHz, RL = 32 Ω,
C both channels on
23.2
43.0
THD+N = 1%, f = 1 kHz, RL = 16 Ω, single
channel on
PO
Output power
mW
THD+N = 1%, f = 1 kHz, RL = 16 Ω, The
processing of Request 596221 was completed at
10:19 on 28 Jan 2015. Click here to access the
data Click here to access the HTML data both
channels on
30.2
RL = 16 Ω, PO = 10 mW, f = 1 kHz
RL = 16 Ω, PO = 0.1 mW, f = 1 kHz
RL = 10 kΩ, VOUT = 1 VRMS, f = 1 kHz
f = dc, VDD = 1.7 V to 1.9 V, AV = 0 dB
f = 217 Hz, 100 mVP-P ripple on VDD
f = 10 kHz, 100 mVP-P ripple on VDD
AV = 0 dB
0.021%
0.057%
0.014%
91
Total harmonic distortion plus
noise
THD+N
PSRR
EN
70
Power supply rejection ratio
Output noise(1)
88
dB
71
8.0
AV = -30 dB
2.0
µVRMS
AV = -42 dB
2.0
RL = 16 Ω, f = 1 kHz, PO = 5 mW
RL = 32 Ω, f = 1 kHz, PO = 25 mW
–56
Crosstalk between left and right
channels
dB
–62
RIN
Amplifier input resistance
Output offset voltage
20
kΩ
mV
VOOS
AV = 0 dB
RL = 10 kΩ
AV = 0 dB
–0.5
0.5
VOUT,Max Max line output voltage
1
VRMS
Input low-pass filter 3-dB cutoff
fC,LPF
45.1
kHz
dB
frequency(2)
f = 10 Hz to 15 kHz, dc-coupled inputs with
VCM = 0 V
Low-pass filter passband gain(2)
–0.4
Low-pass filter stopband gain(2)
Charge pump frequency
f = 145 kHz
–16
1.3
dB
fCP
MHz
AV = 0 dB, Volume Slewing
Enabled, RL = 32 Ω, peak
voltage, 32 samples / second
Into shutdown
–83
–69
Click and pop(1)
dBV
Out of
shutdown
PO = 0.5 mW, RL = 32 Ω
6.2
13.3
56.9
32
Power consumption(3)
PO = 5 mW, RL = 32 Ω, THRH = 1
PO = 30 mW, RL = 32 Ω, THRH = 0
mW
RL
Minimum headphone load
7.8
Ω
(1) A-weighted
(2) Measured with respect to gain at 997 Hz
(3) Per output channel
6
Copyright © 2014–2015, Texas Instruments Incorporated
TPA6166A2
www.ti.com.cn
ZHCSDD5B –MARCH 2014–REVISED JANUARY 2015
6.7 Electrical Characteristics, Mic Preamplifier and Bias
VDD = 1.8 V, MICVDD = 3.0 V, TA = 25°C (unless otherwise noted).
PARAMETER
MICROPHONE BIAS
TEST CONDITIONS
MIN
TYP
MAX UNIT
Programmed for high value, MICVDD ≥ 2.8 V
Programmed for low value
Internal bias resistor bypassed (MICR = 011)
MICR = 000
2.45
1.88
2.6
2.0
2.75
V
VBIAS
IOUT
Microphone bias voltage
Max bias output current
2.12
1.2
mA
2.09
2.47
2.85
2.2
2.31
MICR = 001
2.6
2.73
kΩ
RBIAS
Bias output resistance
Bias output noise(1)
MICR = 010
3.0
3.15
MICR = 011
0.13
2.0
Between SLEEVE and RING2, BW = 100 Hz to 7 kHz,
2.2 kΩ load between SLEEVE and RING2, MICR = 000,
VBIAS = 2.0 V
EN
µVRMS
f = dc,
MICVDD = 2.8 V to
3.6 V
92
73
73
Measured between SLEEVE and
f = 2 kHz, 100 mVP-P
RING2, 2.2 kΩ load between
ripple,
PSRR
MicZ
Power supply rejection ratio
dB
SLEEVE and RING2,
MICVDD = 3.0 V
MICR = 000, VBIAS = 2.6 V
f = 2 kHz, 100 mVP-P
ripple,
MICVDD = 2.8 V
Measured between Mic and GND
before insertion
1500
20000
Microphone Capsule Impedance
Ω
MICROPHONE PREAMPLIFIER
Programmed for high value, f = 997 Hz
Programmed for low value, f = 997 Hz
23
11
24
12
25
dB
13
AV
EN
Preamplifier gain
Input referred noise(1)
f = 100 Hz to 7 kHz, AV = 24 dB, Mic on SLEEVE, 2.2 kΩ
load between SLEEVE and RING2, MICR = 000,
VBIAS = 2.0 V
3.4
µVRMS
THD+N
Total harmonic distortion plus
noise
VOUT = 1 VRMS
0.095
%
Measured between MOUTP-MOUTN, 6.04 kΩ between
SLEEVE and RING2, MICR = 010, VBIAS = 2.0 V, f = dc,
MICVDD = 2.4 V to 3.6 V
74
Measured between MOUTP-
MOUTN, 2.2 kΩ between
SLEEVE and RING2,
f = dc,
MICVDD = 2.8 V to
3.6 V
109.5
78
PSRR
Power supply rejection ratio
dB
MICR = 000, VBIAS = 2.6 V
f = 2 kHz, 100 mVP-P
ripple on MICVDD
VCMO
fC,LO
fC,HI
Output Common Mode
Lower -3 dB frequency of HPF(2)
MICVDD = 2.4 V – 3.6V
0.4×MICVDD
V
20
Hz
Upper -3 dB frequency of
amplifier(2)
260
kHz
(1) A-weighted
(2) Measured with respect to gain at 997 Hz
Copyright © 2014–2015, Texas Instruments Incorporated
7
TPA6166A2
ZHCSDD5B –MARCH 2014–REVISED JANUARY 2015
www.ti.com.cn
6.8 Timing Requirements
For I2C interface signals and voltage power-up sequence, over recommended operating conditions (unless otherwise noted).
Timing is specified by design.
MIN MAX
400
0.6
UNIT
kHz
μs
fSCL
tw(H)
tw(L)
tsu1
th1
Frequency, SCL
No wait states
Pulse duration, SCL high
Pulse duration, SCL low
Setup time, SDA to SCL
Hold time, SCL to SDA
1.3
μs
100
10
ns
ns
t(buf)
tsu2
th2
Bus free time between stop and start condition
Setup time, SCL to start condition
Hold time, start condition to SCL
Setup time, SCL to stop condition
Pulse width of surpressed spike
1.3
μs
0.6
μs
0.6
μs
tsu3
tSP
0.6
μs
0
50
ns
tw(H)
tw(L)
SCL
tsu1
th1
SDA
T0027-02
Figure 1. SCL and SDA Timing
SCL
t(buf)
th2
tsu2
tsu3
SDA
Start
Condition
Stop
Condition
T0028-01
Figure 2. Start and Stop Conditions Timing
8
Copyright © 2014–2015, Texas Instruments Incorporated
TPA6166A2
www.ti.com.cn
ZHCSDD5B –MARCH 2014–REVISED JANUARY 2015
6.9 Typical Characteristics
VDD = 1.8 V, MICVDD = 3.0 V, AV = 0 dB, CIN = 0.47 µF, CFLY = 1.0 μF, CCPVDD = CCPVSS = 1.0 μF, RHP = 32 Ω, outputs in
phase, TA = 25°C (unless otherwise noted).
10
10
In Phase
Out of Phase
In Phase
Out of Phase
1
1
0.1
0.1
0.01
0.1
0.01
0.1
1
10
50
1
10
50
PO − Output Power per Channel − mW
PO − Output Power per Channel − mW
VDD = 1.8 V
f - 1 kHz
RL = 16 Ω
Gain = 0 dB
VDD = 1.8 V
f - 1 kHz
RL = 32 Ω
Gain = 0 dB
Figure 3. Headphone Total Harmonic Distortion + Noise vs
Output Power
Figure 4. Headphone Total Harmonic Distortion + Noise vs
Output Power
40
10
PO = 100 uW per Channel
PO = 10 mW per Channel
10
1
0.1
1
0.01
0.001
Both Channels On − In phase
0.1
10
100
1000
10000
20
100
1k
10k 20k
f − Frequency − Hz
RL − Load Resistance − W
VDD = 1.8 V
RL = 16 Ω
Gain = 0 dB
VDD = 1.8 V
f = 1 kHz
Gain = 0 dB
THD+N = 1%
Figure 5. Headphone Total Harmonic Distortion + Noise vs
Figure 6. Headphone Output Power vs Load Resistance
Frequency
100
200
100
80
60
40
20
0
10
Both Channels On − In phase
1
0.001
20
100
1k
10k 20k
0.01
0.1
1
10
50
f − Frequency − Hz
PO − Output Power per Channel− mW
VDD = 1.8 V
RL = 16 Ω
Gain = 0 dB
VDD = 1.8 V
f = 1kHz
RL = 16 Ω
Gain = 0 dB
THRH = 0
Figure 7. Headphone Psrr vs Frequency
Figure 8. Headphone Supply Current vs Total Output Power
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Typical Characteristics (continued)
VDD = 1.8 V, MICVDD = 3.0 V, AV = 0 dB, CIN = 0.47 µF, CFLY = 1.0 μF, CCPVDD = CCPVSS = 1.0 μF, RHP = 32 Ω, outputs in
phase, TA = 25°C (unless otherwise noted).
100
10
1
2
1
0
−1
−2
Both Channels On − In phase
10
0.001
0.01
0.1
1
40
−100
0
100
200
300
400
500
600
700
PO − Output Power per Channel− mW
t − Time − ms
VIN = 0.5 VRMS
RL = 16 Ω
VDD = 1.8 V
f = 1kHz
RL = 32 Ω
Gain = 0 dB
Volume slewing enabled
Device enabled at 0 ms
THRH = 0
Figure 10. Headphone Start-up Waveforms vs Time
Figure 9. Headphone Supply Current vs Total Output Power
2
−20
−40
−60
1
0
−80
−100
−120
−140
−160
−180
−1
−2
−50
0
50
100
150
200
250
0
5k
10k
15k
20k
t − Time − ms
f − Frequency − Hz
VIN = 0.5 VRMS
RL = 16 Ω
VDD = 1.8 V
RL = 16 Ω
Gain = 0 dB
Volume slewing enabled
Device enabled at 0 ms
A weighted
Figure 11. Headphone Shutdown Waveforms vs Time
Figure 12. Headphone Output Spectrum vs Frequency
−20
10
−40
−60
0
−10
−20
−30
−40
−50
−60
−80
−100
−120
−140
−160
−180
0
5k
10k
15k
20k
10
100
1k
10k
100k
500k
f − Frequency − Hz
f − Frequency − Hz
VDD = 1.8 V
RL = 16 Ω
Gain = –30 dB
VDD = 1.8 V
RL = 16 Ω
Gain = 0 dB
A weighted
Figure 13. Headphone Output Spectrum vs Frequency
Figure 14. Audio Filter Frequency Response
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Typical Characteristics (continued)
VDD = 1.8 V, MICVDD = 3.0 V, AV = 0 dB, CIN = 0.47 µF, CFLY = 1.0 μF, CCPVDD = CCPVSS = 1.0 μF, RHP = 32 Ω, outputs in
phase, TA = 25°C (unless otherwise noted).
1
1
MICVDD = 2.4 V
MICVDD = 3.0 V
MICVDD = 3.6 V
VDD = 1.8 V
MICVDD = 2.4 V
MICVDD = 3.0 V
MICVDD = 3.6 V
Gain = 24 dB
VOUT = 1 VRMS
0.1
0.1
0.01
0.01
0.001
0.001
20
100
1k
10k 20k
20
100
1k
10k 20k
f − Frequency − Hz
f − Frequency − Hz
VDD = 1.8 V
VOUT = 1 VRMS
Gain = 12 dB
VDD = 1.8 V
VOUT = 1 VRMS
Gain = 24 dB
Figure 15. Mic Preamplifier Total Harmonic Distortion +
Figure 16. Mic Preamplifier Total Harmonic Distortion +
Noise vs Frequency
Noise vs Frequency
16
28
14
12
10
8
24
20
16
12
8
6
4
4
2
0
0
10
100
1k
10k
100k
500k
10
100
1k
10k
100k
500k
f − Frequency − Hz
f − Frequency − Hz
MIC VDD = 3.0 V
Gain = 12 dB
MIC VDD = 3.0 V
Gain = 24 dB
Figure 17. Mic Preamplifier Frequency Response
Figure 18. Mic Preamplifier Frequency Response
0
100
−20
−40
80
60
40
20
−60
−80
−100
−120
−140
−160
Gain = 12 dB
Gain = 24 dB
0
100
1k
7k
0
5k
10k
15k
20k
f − Frequency − Hz
f − Frequency − Hz
VDD = 1.8 V
MIC VDD = 3.0 V
MIC VDD = 3.0 V
Gain = 12 dB
No signal input
Figure 19. Mic Preamplifier + Micbias PSRR vs Frequency
Figure 20. Mic Preamplifier + Micbias Output Frequency
Spectrum
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Typical Characteristics (continued)
VDD = 1.8 V, MICVDD = 3.0 V, AV = 0 dB, CIN = 0.47 µF, CFLY = 1.0 μF, CCPVDD = CCPVSS = 1.0 μF, RHP = 32 Ω, outputs in
phase, TA = 25°C (unless otherwise noted).
0
−20
−40
−60
−80
−100
−120
−140
−160
0
5k
10k
15k
20k
f − Frequency − Hz
MIC VDD = 3.0 V
Gain = 24 dB
No signal input
Figure 21. Mic Preamplifier + Micbias Output Frequency Spectrum
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7 Detailed Description
7.1 Overview
The TPA6166A2 is a small device that serves a large number of complex functions in a portable audio device. It
identifies an accessory plugged into the jack, and configures the internal subsystems to take full advantage of its
capabilities.
•
•
•
•
•
•
•
Headphone-jack accessory detection and identification
Switch matrix
Class-G ground-centered stereo headphone amplifier
Mic preamplifier and bias
SAR ADC for various analog sense functions
ESD protection
Convenient I2C host interface
7.2 Functional Block Diagram
CPVDD CPVSS C1P C1N VDD MICVDD
Class-G
Stereo Headphone
RING1
TIP
INL
INR
Amplifier
ESD
Prot.
Mic
JACK_SENSE
RING2
Switch
Bias
Matrix
SLEEVE
and
Detection
Circuit
MOUTP
MOUTN
SDA
SCL
IRQ
Digital
SAR
ADC
Interface
and
Control
GND1
PGND
GND2
7.3 Feature Description
7.3.1 I2C Interface
The TPA6166A2 I2C address is 0x40 (7-bit).
The I2C bus employs two signals, SDA (data) and SCL (clock), to communicate between integrated circuits in a
system. The bus transfers data serially, one bit at a time. The most significant bit (MSB) is transferred first for the
8-bit address and data bytes. In addition, each byte transferred on the bus is acknowledged by the receiving
device with an acknowledge bit. Each transfer operation begins with the master device driving a start condition
on the bus and ends with the master device driving a stop condition on the bus. The bus uses transitions on the
data terminal (SDA) while the clock is at logic high to indicate start and stop conditions. A high-to-low transition
on SDA indicates a start and a low-to-high transition indicates a stop. Normal data-bit transitions must occur
within the low time of the clock period.
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Feature Description (continued)
Figure 22 shows a typical sequence. The master generates the 7-bit slave address and the read/write (R/W) bit
to open communication with another device, and then waits for an acknowledge condition. The TPA6166A2
holds SDA low during the acknowledge clock period to indicate acknowledgment. When acknowledgment occurs,
the master transmits the next byte of the sequence. Each device is addressed by a unique 7-bit slave address
plus R/W bit (1 byte). All compatible devices share the same signals via a bidirectional bus using a wired-AND
connection.
An external pullup resistor must be used for the SDA and SCL signals to set the logic high level for the bus.
When the bus level is 3.3 V, use pullup resistors between 1 kΩ and 2 kΩ.
There is no limit on the number of bytes that can be transmitted between start and stop conditions. When the last
word transfers, the master generates a stop condition to release the bus. A generic data transfer sequence is
shown in Figure 22.
8-Bit Register Data For
Address (N)
8-Bit Register Data For
Address (N)
R/
W
8-Bit Register Address (N)
7-Bit Slave Address
A
A
A
A
SDA
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
SCL
Start
Stop
T0035-01
Figure 22. Typical I2C Sequence
7.3.1.1 Single and Multiple Byte Transfers
The serial control interface supports both single-byte and multiple byte read/write operations for all registers.
During multiple-byte read operations, the TPA6166A2 responds with data, 1 byte at a time, starting at the register
assigned, as long as the master device continues to respond with acknowledgments.
The TPA6166A2 supports sequential I2C addressing. For write transactions, if a register is issued followed by
data for that register and all the remaining registers that follow, a sequential I2C write transaction has occurred.
For I2C sequential write transactions, the register issued then serves as the starting point, and the amount of
data subsequently transmitted, before a stop or start is transmitted, determines the number of registers written.
7.3.1.2 Single-Byte Write
As Figure 23 shows, a single-byte data write transfer begins with the master device transmitting a start condition
followed by the I2C device address and the read/write bit. The read/write bit determines the direction of the data
transfer. For a write data transfer, the read/write bit must be set to 0. After receiving the correct I2C device
address and the read/write bit, the TPA6166A2 responds with an acknowledge bit. Next, the master transmits the
register byte corresponding to the TPA6166A2 internal memory address being accessed. After receiving the
register byte, the TPA6166A2 again responds with an acknowledge bit. Next, the master device transmits the
data byte to be written to the memory address being accessed. After receiving the register byte, the TPA6166A2
again responds with an acknowledge bit. Finally, the master device transmits a stop condition to complete the
single-byte data write transfer.
Start
Condition
Acknowledge
Acknowledge
Acknowledge
R/W
A6 A5 A4 A3 A2 A1 A0
ACK A7 A6 A5 A4 A3 A2 A1 A0 ACK D7 D6 D5 D4 D3 D2 D1 D0 ACK
I2C Device Address and
Read/Write Bit
Subaddress
Data Byte
Stop
Condition
T0481-01
Figure 23. Single-Byte Write Transfer
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Feature Description (continued)
7.3.1.3 Multiple-Byte Write and Incremental Multiple-Byte Write
A multiple-byte data write transfer is identical to a single-byte data write transfer except that multiple data bytes
are transmitted by the master device to the TPA6166A2 as shown in Figure 24. After receiving each data byte,
the TPA6166A2 responds with an acknowledge bit.
Start
Condition
Acknowledge
Acknowledge
Acknowledge
D0 ACK D7
Acknowledge
D0 ACK D7
Acknowledge
D0 ACK
A6 A5
A1 A0 R/W ACK A7 A6 A5 A4 A3
A1 A0 ACK D7
I2C Device Address and
Read/Write Bit
Subaddress
First Data Byte
Last Data Byte
Stop
Condition
Other Data Bytes
T0482-01
Figure 24. Multiple-Byte Write Transfer
7.3.1.4 Single-Byte Read
As Figure 25 shows, a single-byte data read transfer begins with the master device transmitting a start condition
followed by the I2C device address and the read/write bit. For the data read transfer, both a write followed by a
read are actually executed. Initially, a write is executed to transfer the address byte of the internal memory
address to be read. As a result, the read/write bit is set to a 0.
After receiving the TPA6166A2 address and the read/write bit, the TPA6166A2 responds with an acknowledge
bit. The master then sends the internal memory address byte, after which the TPA6166A2 issues an
acknowledge bit. The master device transmits another start condition followed by the TPA6166A2 address and
the read/write bit again. This time the read/write bit is set to 1, indicating a read transfer. Next, the TPA6166A2
transmits the data byte from the memory address being read. After receiving the data byte, the master device
transmits a not-acknowledge followed by a stop condition to complete the single-byte data read transfer.
Repeat Start
Condition
Not
Acknowledge
Start
Condition
Acknowledge
Acknowledge
A0 ACK
Acknowledge
A6 A5
A1 A0 R/W ACK A7 A6 A5 A4
A6 A5
A1 A0 R/W ACK D7 D6
D1 D0 ACK
I2C Device Address and
Read/Write Bit
Subaddress
I2C Device Address and
Read/Write Bit
Data Byte
Stop
Condition
T0483-01
Figure 25. Single-Byte Read Transfer
7.3.1.5 Multiple-Byte Read
A multiple-byte data read transfer is identical to a single-byte data read transfer except that multiple data bytes
are transmitted by the TPA6166A2 to the master device as shown in Figure 26. With the exception of the last
data byte, the master device responds with an acknowledge bit after receiving each data byte.
Repeat Start
Condition
Not
Acknowledge
Start
Condition
Acknowledge
Acknowledge
Acknowledge
Acknowledge
Acknowledge
D0 ACK D7
A6
A0 R/W ACK A7 A6 A5
A0 ACK
A6
A0 R/W ACK D7
D0 ACK D7
D0 ACK
I2C Device Address and
Read/Write Bit
Subaddress
I2C Device Address and First Data Byte
Read/Write Bit
Other Data Bytes
Last Data Byte
Stop
Condition
T0484-01
Figure 26. Multiple-Byte Read Transfer
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Feature Description (continued)
7.3.2 Accessory Detection
The TPA6166A2 has an advanced accessory jack detection circuitry which determines insertion, removal, as well
as type detection of accessories with a 3.5-mm headset jack. The jack and its internal connections are shown in
Figure 27.
2 (RING1)
1 (TIP)
1
2
3
4
5 (JACK_SENSE,
Normally Closed)
3 (RING2)
4 (SLEEVE)
Figure 27. Connecting to a 3.5-mm Headset Jack
When the insertion of a jack is detected, the accessory type detection algorithm runs until two consecutive type
detections produce the same result. In general, the type detection algorithm is not run again after this point of
time. Hence, on-the-fly change of accessory type is not detected. The following accessories can be detected.
Table 6 has specific detection details.
•
•
•
•
•
Stereo Headset (HP with mic)
Line Out Audio Cable
Mono Headset
Stereo Headphone
Line Out Audio Cable
The limits of detection are shown in Table 1.
Table 1. Limits of Detection
PARAMETER
SYMBOL
CCABLE
RHP
MIN
MAX
500
UNIT
pF
Cable Shield Capacitance
Headphone Load Resistance
Audio Line Load Resistance
Microphone Load Resistance
Open/Float
150
8
700/1500*
50
Ω
RLINE
RMIC
10
1.5
kΩ
kΩ
kΩ
20
200K || 70 pF
10 G || 5 pF
As a result of accessory detection, appropriate blocks are automatically turned on ensuring lower possible power
consumption. When accessory is removed, all blocks are turned off ensuring ultra low power. The TPA6166A2
achieves 22.7 µW when no accessory is inserted.
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7.3.3 Audio Playback Channel
The TPA6166A2 includes stereo audio channel with integrated low pass filter and class-G headphone amplifier.
Figure 28 shows the block diagram for the Audio Channel. The channel includes volume control block. The
volume level can be varied from +6 dB to –42 dB in 1-dB steps, in addition to a mute bit, independently for each
channel. The volume level of both channels can also be changed simultaneously by the master volume control,
which can be achieved by setting Register 0x07, Bit 7 (L=R) to 1. Gain changes are implemented with a soft-
stepping algorithm, which only changes the actual volume by one step in every 3.25 ms, either up or down, until
the desired volume is reached.
0 to -30dB (steps of -6dB)
+6 to -12dB (steps of -1dB)
-
INL
LPF
+
16 dB Attenuation
at 145 kHz
-
TIP
+
RING2
SLEEVE
RING1
+
-
+
-
INR
+6 to -12dB (steps of -1dB)
LPF
16 dB Attenuation
at 145 kHz
0 to -30dB (steps of -6dB)
Figure 28. Audio Playback Channel
Because of soft-stepping, the system does not know when the audio channel has been actually muted. This may
be important if the system wishes to mute the channel before making a significant change. To help with this
situation, the device provides a flag back to the system through a read-only register bit that alerts the system
when the part has completed the soft-stepping and the actual volume has reached the desired volume level.
Soft-stepping feature can be disabled by setting Register 0x1E, Bit 5 (VSEN) to 1.
The TPA6166A2 integrates switches on RING2 (terminal 3) and SLEEVE (terminal 4) to ground. Based on
accessory detection result, either RING2 or SLEEVE is selected as accessory ground, and appropriate switch is
turned on. As switches have finite resistance, it can give rise to crosstalk between left and right channel. The
TPA6166A2 integrates ground loop rejection circuitry, which reduces crosstalk to a great extent.
The left channel audio output can be routed to TIP. For right channel, audio output is routed to RING1.
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7.3.3.1 Class-G Headphone Amplifier
Class-G is a linear amplifier using a modulating supply voltage. A high-efficiency step-down converter regulates
the headphone amplifier supply voltage. The headphone amplifier supply voltage increases as the audio output
voltage increases. This prevents signal clipping and distortion. The headphone amplifier supply voltage
decreases during softer audio periods, reducing battery current and improving overall efficiency. The class-G
amplifier has more than twice the efficiency of an equivalent class-AB amplifier. This increases battery life during
audio playback.
Figure 29 shows the block diagram for the class-G headphone amplifier. The class-G control examines the
amplifier output voltage and determines the optimum headphone supply voltage. CPVDD and CPVSS voltages
increase fast enough to avoid any output clipping or distortion. The class-G control operates automatically and
does not require programming.
VDD
CPVDD
IDD
IDD/2
IOUT
VOUT
Charge
Pump
Audio Input
RL
IDD/2
CPVSS
Class G
Control
Figure 29. Class-G Headphone Block Diagram
7.3.3.1.1 Headphone Charge Pump
The TPA6166A2 includes a high-efficiency step-down charge pump and an inverting charge pump to generate
power supplies for the headphone amplifier. These charge pumps use a common flying capacitor, thus
minimizing components. The step-down charge pump regulates CPVDD; the inverting charge pump regulates
CPVSS. These are designed to only drive the TPA6166A2 headphone amplifier. Do not use CPVDD or CPVSS
as a voltage supply to drive an external device.
7.3.3.2 Out-of-Band and Input RF Noise Rejection
When using amplifiers with CODECs and DACs, sometimes there is an increase in the output noise floor from
the audio amplifier. This occurs when the output out-of-band noise of the CODEC/DAC folds back into the audio
frequency due to the limited gain bandwidth product of the audio amplifier. Single-ended RF noise can also fold
back into the audio band thus degrading the audio signal even further.
The TPA6166A2 has a built-in low-pass filter to reduce CODEC/DAC out-of-band noise and RF noise, that could
fold back into the audio frequency.
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7.3.4 Mic Channel
The TPA6166A2 includes microphone preamplifier with selectable gain of 12 dB and 24 dB. The device uses
architecture, which removes requirement of external AC coupling capacitor by integrating it inside. The
TPA6166A2 also includes Mic-bias with integrated bias resistor. A mic bias voltage can be programmed to 2.0 V
or 2.6 V. Mic-bias resistor can be programmed to 2.2 kΩ, 2.6 kΩ, 3.0 kΩ or bypass. Based on accessory
detection result, either RING2 (terminal 3 of jack) or SLEEVE (terminal 4 of jack) is selected as Mic input, and
appropriate switch is turned on. Figure 30 shows the block diagram for the Mic Channel. Note that Bias resistor
bypass mode, accessory detection, removal detection, and mic amp will not function.
Micbias
(2.0 V / 2.6 V)
2.2 / 2.6 / 3.0 k
RING2
MOUTP
MOUTN
12/24 dB
Mic Pre-
Amplifier
SLEEVE
Figure 30. Mic Channel
7.3.5 Button Press Detection
The TPA6166A2 supports button press detection of different types:
•
Single button press/release: When pressed, this typically creates an equivalent resistance of 1 Ω between
RING2 and SLEEVE.
•
Passive button press/release: When pressed, this creates an equivalent resistance between RING2 and
SLEEVE. The TPA6166A2 reports press and release event along with resistance value (KEYDATA_DIV and
KEYDATA in Register 0x17).
The impedance seen by the ADC is calculated using the following data
•
•
•
Bias voltage
Bias resistor
Parallel impedance of the switch pressed and the microphone capsule impedance
The button press detection is done in a two-stage process. The device remains in a low power mode until a
comparator is tripped. The comparator threshold is set to <1500Ω. Upon detection, the ADC is started to
calculate the impedance pressed.
NOTE
The ADC will support impedances up to 375 Ω. Higher values are supported, but are
much more susceptible to capacitance in the mic capsule, and could potentially provide
erronious readings. At 375 Ω, Mic Capsule capacitances supported can be up to 50 nF.
For more details on configuring the device for Button Press Detection, see Button Detection.
7.4 Device Functional Modes
7.4.1 I2C Options
The TPA6166A2 I2C address is 0x40 (7-bit).
•
•
•
•
•
Single-Byte Write
Multiple-Byte Write
Incremental Multiple-Byte Write
Single-Byte Read
Multiple-Byte Read
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Device Functional Modes (continued)
7.4.2 System in Shutdown Mode
Shutdown mode enables lowest power consumption from device. During this mode, accessory insertion, removal
and type detection are not supported, but as soon as system comes out of shutdown, detection will work fine.
This mode can be programmed by programming /SHDN, register 0x1D (bit-7) to 0 For coming out of shutdown,
/SHDN bit should be set to 1.
This will also rerun accessory detection algorithm.
7.4.3 System in Sleep Mode
This mode is enabled by programming SLEEP, register 0x1D (bit-6) to 1. During this mode, accessory insertion,
removal, type and single-button press/release detection are supported.
7.4.3.1 Accessory Not Inserted
When the device is in AUTO mode (register 0x1E, bit 1-0 = 01), the device automatically configures itself in
lowest possible power mode.
If accessory was previously inserted and is then removed, interrupt gets generated. Upon interrupt following
sequence can be used to determine accessory removal and take appropriate action:
•
•
Read control registers 0x00 to 0x02
If JKIN, register 0x00, bit-7 = 0, then infer that accessory has been removed. Program SLEEP, register 0x1D,
bit-6 = 1.
7.4.3.2 Accessory Inserted
When the device is in AUTO (register 0x1E, bit 1-0 = 01) and SLEEP (register 0x1D, bit-6 = 1) mode, the device
automatically configures itself to minimize power consumption. For example: the mic preamplifier and headphone
amplifiers are turned off, but removal and button-press detection continue to operate.
If the accessory was previously not inserted and is then inserted, interrupt gets generated. Upon interrupt
following sequence can be used to determine accessory insertion and take appropriate action:
•
•
•
Read control registers 0x00 to 0x02
If JKIN, register 0x00, bit 7 = 1, then infer that accessory has been inserted.
Read control register 0x19 to determine type of accessory
When the system wakes up and programs the device out of SLEEP mode, appropriate blocks will automatically
turn on based on the type of accessory. System can also use accessory type to configure different routings
(example: mix left and right channel for mono headset) and signal swing (depending on whether it is headphone
or line-out load).
If the system was previously not in sleep mode and enters sleep mode, the following sequence should be
followed to avoid pop noise on the headphone output:
•
•
Enable interrupt due to volume slewing. This can be done by programming register 0x04, bit-5 (IVOL) = 1.
If register 0x07, bit-7 (L=R) is 1, then program register 0x1E, bits 7-6 (left and right headphone control) = 00
and bits 1-0 (AUTO) = 00. Wait for interrupt due to volume slewing complete (VOL, register 0x00, bit-5).
•
If register 0x07, bit-7 (L=R) is 0, then execute following steps:
–
If register 0x1E, bit-7=1, then program register 0x1E, bit-7 = 0 and bits 1-0 = 00. Wait for interrupt due to
volume slewing complete (VOL, register 0x00, bit-5)
–
If register 0x1E, bit-6=1, then program register 0x1E, bit-6 = 0 and bits 1-0 = 00. Wait for interrupt due to
volume slewing complete (VOL, register 0x00, bit-5).
•
•
Program device in sleep mode (register 0x1D, bit-6, SLEEP = 1).
Program device back in Auto mode (register 0x1E, bits 1-0, AUTO = 01.
20
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Device Functional Modes (continued)
7.4.3.3 Button Detection During Sleep Mode
During Sleep mode, single-button press/release detection is supported. Remaining buttons of passive multi-
button headset (resistance of button higher than 0 Ω) are also detected as single button (resistance ≈ 0 Ω). For a
button press, the system can use this event to wake up the system, and then program the device (details in
Button Detection) to detect the second button press correctly.
Upon interrupt, the following sequence needs to be followed for button detection:
•
•
Read control registers 0x00 to 0x02
If MCSW, register 0x00, bit 1 = 1, then infer that button has been pressed/released. As long as button is
pressed, MCSW continues to remain set.
7.4.4 System in Wake-Up Mode
This mode is enabled by programming SLEEP, register 0x1D (bit-6) to 0. During this mode, accessory insertion,
removal, type, single button press/release and passive multi-button detection are supported.
7.4.4.1 Accessory Not Inserted
When the device is in AUTO mode (register 0x1E, bit 1-0 = 01), the device automatically configures itself in
lowest possible power mode.
If accessory was previously inserted and is then removed, interrupt gets generated. Upon interrupt following
sequence can be used to determine accessory removal and take appropriate action:
•
•
Read control registers 0x00 to 0x02
If JKIN, register 0x00, bit 7 = 0, then infer that accessory has been removed. Program SLEEP, register 0x1D,
bit-6 = 1.
If a voice call is in progress, the system can use removal information to change from headset to handset mode. If
audio is playing, the system can use the removal information to route audio to the speaker amplifier.
7.4.4.2 Accessory Inserted
When the device is in AUTO mode (register 0x1E, bit 1-0 = 01), the device automatically configures itself to turn
on appropriate blocks. For example: for mono, only left headphone amp is turned on, whereas for stereo both left
and right headphone amps are turned on).
If accessory was previously not inserted and is then inserted, an interrupt is generated. Upon an interrupt, the
following sequence can be used to determine that an accessory insertion has occurred and take appropriate
action:
•
•
•
Read control registers 0x00 to 0x02
If JKIN, register 0x00, bit-7 = 1, then infer that accessory has been inserted.
Read control register 0x19 (bit 6-0, STATE) to determine type of accessory. Program SLEEP, register 0x1D,
bit-6 = 0 (if audio is playing or in voice call).
If a voice call is in progress, the system can use the insertion information to change from handset to headset
mode. If audio is playing on speaker, the system can use the insertion information to route audio to headset
(accessory).
Accessory type detection can be used to configure different routings (example: for mono headset, mix left and
right channel and route it on INL of the TPA6166A2) and signal swing (depending on headphone or line-out
load).
7.4.4.3 Audio Not Playing or Not in Voice Call
During this mode, lowest power option is to program the device in SLEEP mode (register 0x1D, bit 6 = 1). This
will power down mic preamplifier and headphone amplifiers. If audio starts playing or a voice call starts, SLEEP
can be programmed to 0. To minimize pop and clock, headphone amplifiers go through power up sequencing
where it first powers up in MUTE and then soft step volume to set gain with slew rate of 3.25 ms/dB. Volume
slewing can be disabled by programming register 0x1E, bit-5 to 1.
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Device Functional Modes (continued)
7.4.4.4 High Impedance Line Out Load
The TPA6166A2 detects 50-kΩ max impedance as a line-level output. A value above 50 kΩ is treated as float
and the corresponding amplifier is kept powered down. If higher value line-out load must be supported, the
following sequence can be used, when accessory insertion is detected:
•
Register 0x19 (bit 6-0, STATE) value is already available immediately after insertion detection (to determine
type of accessory). Check if STATE have one of following values
–
–
–
0x1B
0x1C
0x1F
•
If value matches one of the above, the following register writes should be done
–
–
Register 0x19 (bits 7-0) = 0x1A
Register 0x19 (bits 7-0) = 0x9A
The preceding sequence will power up both left and right headphone amplifiers. After this step, the device will
again go into automatic mode, where blocks will be powered up and down based on detection result.
7.4.4.5 Button Detection
If only single-button detection is required, following sequence can be used when interrupt is generated:
•
•
Read control registers 0x00 to 0x02
If MCSW, register 0x00, bit 1 = 1, then infer that button has been pressed (PRESS, register 0x01, bit-1 = 1)
or released (PRESS, register 0x01, bit-1 = 0)
If both single-button and passive multi-button detection are required, the following sequence can be used:
•
As soon as the device is in wake-up mode (SLEEP = 0), following register writes should be done
–
–
–
–
Register 0x1C (bit-7) = 1
Register 0x66 (bits 7-0) = 0xF1
Register 0x6F (bits 7-0) = 0x01
Register 0x66 (bits 7-0) = 0x00
•
Upon interrupt, following sequence can be used:
–
–
Read control registers 0x00 to 0x02
If MCSW (register 0x00, bit-1) = 1, then infer that single-button has been pressed (PRESS, register 0x01,
bit-1 = 1) or released (PRESS, register 0x01, bit-1 = 0).
–
–
If MCSW = 0 and KEY (register 0x01, bit-2) = 1, then infer that passive multi-button has been pressed
(PRESS, register 0x01, bit-1 = 1) or released (PRESS, register 0x01, bit-1 = 0).
If passive multi-button press is detected, value of button resistance can be known by reading register 0x17
(KEYDATA_DIV and KEYDATA). Equation for resistance calculation is shown in description of control
register 0x17
•
When device needs to be taken to Sleep or Shutdown mode or accessory removal gets detected, the
following additional registers should be programmed to minimize power consumption
–
–
–
–
Register 0x1C (bit-7) = 0
Register 0x66 (bits 7-0) = 0xF1
Register 0x6F (bits 7-0) = 0x00
Register 0x66 (bits 7-0) = 0x00
22
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7.5 Register Maps
7.5.1 Register Functional Overview
The TPA6166A2 when configured in fully automated mode (bits 1-0, register 0x1E set to 01) automatically
enables and disables relevant blocks (headphone, mic preamplifier, mic bias, and so forth) based on result of
accessory detection.
Table 2. Register Descriptions for Software Developers
Registers
Read/Write
Function
Configuration and device status registers. These registers are used to report the makeup of the
inserted jack as well as report when a microphone switch has been pressed or the jack has been
removed. The TPA6166A2 uses the status registers and IRQ to report the status of various device
functions. The status registers bits are set when their respective event occurs and cleared upon
reading the register. Device status can be determined either by polling the registers or configuring the
IRQ to go low when specific events occur and then reading these registers on IRQ.
0x00, 0x01,
0x02
R
Interrupt mask registers. These registers determine which bits in the status registers (0x00 – 0x02)
will trigger IRQ to go low. Once IRQ goes low, it becomes high when status register responsible for
IRQ generation gets read.
0x04, 0x05
0x07, 0x08
R/W
R/W
Headphone volume setting registers. These registers independently control and report the gain of the
left and right headphone amplifiers. There is an option to have right channel gain track left channel
gain setting. This can be done by setting bit 7 in control register 0x07.
Microphone bias and preamplifier setting register. This register is used to program different settings
related to microphone preamplifier and microphone bias.
0x09
0x0B
R/W
R
Revision ID register
Passive multi-button debounce and delay settings. Debounce helps in filtering any unwanted
noise/glitches in system which can cause wrong button detection. The delay register sets the time-out
that the mic button press is masked from the system. At the end of the delay time, the TPA6166A2
checks to see if accessory is still present. If accessory is not present, then it does not generate
interrupt corresponding to button press. This prevents accessory removal from being detected as a
button press (due to RING2 and SLEEVE getting shorted during removal).
0x15, 0x16
R/W
Passive multi-button data register. For resistance calculations, refer to control register description in
data sheet
0x17
0x19
R
State Register. Indicates type of accessory (headset with/without mic, headphone, line-out, no
accessory inserted, and so forth). If AUTO mode (default) is turned on, relevant blocks are
automatically turned on/off based on type of accessory.
R/W
0x18, 0x1A
0x1C
R/W
R/W
Accessory detection test hardware settings. Provides fine-tuning for accessory detection algorithm.
Clock control for passive multi button. Needed to be configured along with few other registers for
passive multi-button to work. Refer to control register description in data sheet for details.
Enable settings register. This contains all of the bits that control the separate functional blocks. The
system can either directly control these bits, or it can allow device to automatically configure itself and
report which blocks are enabled. When the AUTO bits (B1-B0) are set to 01 or 10, this register is
read only. The block enable bits do not need to be set to detect accessory insertion/removal.
0x1D, 0x1E
R/W
R/W
0x03, 0x06,
0x0A, 0x0C,
0x0D – 0x14,
0x1B, 0x1F
Reserved. Always write recommended values to these registers.
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7.5.2 Initialization
7.5.2.1 Reserved Registers
Always program values based on Table 3 (registers in bold must be programmed).
Table 3. Initialization of Reserved Registers
Register Address
0x03
Value (Hex)
Comments
00
00
00
1C
00
00
00
00
00
01
45
00
00
00
Same as default
Same as default
Same as default
Same as default
Same as default
Same as default
Same as default
Same as default
Same as default
Default is 00
0x06
0x0A
0x0C
0x0D
0x0E
0x0F
0x10
0x11
0x12
0x13
Default is 00
0x14
Same as default
Default is not defined
Same as default
01B
0x1F
7.5.2.2 Fixed Registers
Values for these registers will likely remain same all the time. Table below have recommended settings for
registers. Based on system requirement, it is possible that slightly different values need to be programmed.
Table 4. Typically Fixed Registers
Register Address
Value (Binary)
1100 0010
Comments
0x04
0x05
Same as default
Same as default
0000 0100
Bits 1-0 must be programmed to 00. Bits 7-2 values based on system need (Example: 0100
01 for 24-dB mic preamplifier gain, 2.2-kΩ bias resistor and 2.6-V bias voltage )
0x09
0x15
0x16
B7B6B5B4B3B200
1111 1111
Debounce time of ~64 ms. If this causes too much delay for button press detection, then
lower value can be considered.
Debounce time of ~256 ms. If this causes too much delay for button press detection, then
lower value can be considered.
1111 1111
0x18
0x1A
1100 0000
1001 0101
Same as default
Same as default
7.5.2.3 Other Registers
Values for these registers will likely be changed by system on-the-fly depending on mode of operation
Table 5. Commonly Used Registers
Register Address
Value (Binary)
Comments
0x1E
0001 10001
TI recommends programming this register first before anything else in this table
Bits 6-0 values based on system need (Example: 011 1001 for 0dB gain). These bits can be
changed on-the-fly for controlling volume.
0x07
0000 0100
0x08
0x1C
0x1D
1B6B5B4B3B2B1B0 Bits 6-0 are don’t care if bit 7 of register 0x1E is set to 1
0000 0000
1100 0000
Bit-7 will likely change based on mode, if passive multi-button needs to be supported.
24
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7.5.3 Typical Use Case Modes
After initialization, registers described in Section will need to be programmed during different modes. In addition,
the following registers will be used for checking status, configuration and measurement data:
•
•
•
•
•
0x00
0x01
0x02
0x17
0x19
Upon interrupt, the system host should read registers 0x00, 0x01 and 0x02 to determine the interrupt source and
respond appropriately.
•
•
System In Shutdown Mode
System In Sleep Mode
–
–
–
Accessory Not Inserted
Accessory Inserted
Button Detection During Sleep Mode
•
System In Wake-Up Mode
–
–
–
–
–
Accessory Not Inserted
Accessory Inserted
Audio Not Playing Or Not In Voice Call
High Impedance Line-Out Load
Button Detection
•
•
Accessory Insertion/Removal Detection Without Using Jack_sense
–
–
Scheme 1
Scheme 2
Special Headset Detection
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7.5.4 Recommended Software Flow Chart
The flow chart in Figure 31 gives a conceptual view of how software can be organized for different modes.
System Power-Up
(Battery connected)
Initialize the
TPA6166A2
System Mode
(Shutdown, Sleep,
Shutdown
Wake-up
Wake-up)
Sleep
Program/SHDN = 1and
SLEEP= 1
Program /SHDN= 0
Program /SHDN= 1
Accessory Inserted
(determined based on
interrupt and status in register
0x00-0x02, 0x19)?
Accessory Inserted
(determined based on
interrupt and status in register
0x00-0x02, 0x19)?
Removed
Removed
Inserted
Inserted
Follow steps in“Sleep
Mode – Accessory
Inserted”
No
Follow steps in
“Sleep Mode– Accessory
Not Inserted”
Is audio playing or voice
?
call going on
Yes
Follow steps in
“Wake-Up Mode –
Accessory Not Inserted”
Program SLEEP= 0
Program SLEEP= 1
Figure 31. Recommended Software Flow Chart
7.5.5 Register Map Summary
The TPA6166A2 I2C address is 0x40 (7-bit). See I2C Interface for more details.
REGISTER
DEC HEX
READ /
WRITE
DEFAULT
FUNCTION
0
0x00
0x01
0x02
0x03
0x04
0x05
0x06
0x07
0x08
0x09
0x0A
0x0B
0x0C
0x0D
R
R
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0xC0
0x40
0x03
0x00
0x30
0x1C
0x00
Configuration and Device Status Register 1
Configuration and Device Status Register 2
Configuration and Device Status Register 3
Reserved. Always write 0x00
Interrupt Mask Register 1
1
2
R
3
R
4
R/W
R/W
R/W
R/W
R/W
R/W
R
5
Interrupt Mask Register 2
6
Reserved. Always write 0x00
Headphone Volume Control Register 1
Headphone Volume Control Register 2
Microphone Bias Control Register
Reserved
7
8
9
10
11
12
13
R
Revision ID Register
R/W
R/W
Reserved.
Reserved. Always write 0x00
26
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REGISTER
ZHCSDD5B –MARCH 2014–REVISED JANUARY 2015
READ /
WRITE
DEFAULT
FUNCTION
DEC
HEX
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
0x0E
0x0F
0x10
0x11
0x12
0x13
0x14
0x15
0x16
0x17
0x18
0x19
0x1A
0x1B
0x1C
0x1D
0x1E
0x1F
R/W
R/W
R/W
R/W
R/W
R/W
R
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x80
0x15
Reserved. Always write 0x00
Reserved. Always write 0x00
Reserved. Always write 0x00
Reserved. Always write 0x00
Reserved. Always write 0x01
Reserved. Always write 0x45
Reserved.
R/W
R/W
R
Keyscan Debounce Register
Keyscan Delay Register
Passive Multi Button Keyscan Data Register
Jack Detect Test Hardware Settings
State Register
R/W
R/W
R/W
R
Jack Detect Test Hardware Settings
Reserved
R/W
R/W
R/W
R
0x01
0x00
0x01
0x00
Clock control. Initiialize it to 0x00
Enable Register 1
Enable Register 2
Reserved
Registers 0x00, 0x01, and 0x02 are used to report the makeup of the inserted jack as well as report when a
microphone switch has been pressed or the jack has been removed. The TPA6166A2 uses the status registers
and IRQ to report the status of various device functions. The status registers bits are set when their respective
event occurs and cleared upon reading the register. Device status can be determined either by polling the
registers or configuring the IRQ to go low when specific events occur. Registers 0x04 and 0x05 determine which
bits in the status register will trigger IRQ to go low. Once IRQ goes low, it becomes high when status register
responsible for IRQ generation gets read.
Use a minimum 2-ms wait time after TPA6166A2 power supplies are stable before reading or writing to any
register.
7.5.6 Detailed Register Descriptions
7.5.6.1 Register 0x00: Config and Device Status Register 1
READ /
BIT
NAME
DEFAULT DESCRIPTION
WRITE
Jack Detected.
JKIN changes state when the jack detect circuit senses any valid accessory
inserted.
0 = No valid accessory detected.
7
JKIN
R
0
1 = Valid accessory detected.
Set the IJKIN interrupt mask to alert the system when the JKIN value has
changed. During shutdown mode (SHDN = 0), JKIN will report whether
mechanical switch (JACK_SENSE) is open or closed. STATE value will continue
to remain 0x00.
Jack Configuration Detect Done.
DDONE changes state when the jack detect algorithm is done running and the
jack config is known and reported in the Config and Status1 registers. “RESET
WHEN READ”.
6
DDONE
R
0
0 = Jack detect algorithm is not complete.
1 = Jack detection algorithm is complete.
When change in configuration happens, it is set again. Set the IDDONE interrupt
mask to alert the system when the DDONE is set.
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READ /
WRITE
BIT
NAME
DEFAULT DESCRIPTION
Volume Slew Complete
VOL goes high after the headphone volume has slewed to its final programmed
value. VOL will set every time a gain change is complete whether the gain
change is positive or negative. Ramp the volume down and wait for VOL to set
to ensure clickless turnoff. It is also generated during power down/up and
mute/unmute, where gain changes from/to present value to/from minimum value.
RESET WHEN READ.
5
VOL
R
0
0 = No volume slewing sequences have completed since the status register was
last read.
1 = Volume slewing complete.
4
3
R
R
0
0
Reserved. Write only default value.
Microphone Connected/Disconnected
MIC_IN reports when a microphone is connected or removed. Set the IMIC
interrupt mask to alert the system when the mic load status has changed.
0 = Microphone is removed.
MIC_IN
1 = Microphone is connected.
JACK_SENSE (terminal 5) Status
JACK_SENSE reports the mechanical jack switch status. For an operational
mechanical jack switch, JACK_SENSE and JKIN will flag at the same time. If the
switch is broken, or if the jack is not plugged in all the way, JACK_SENSE and
JKIN will not report the same value. The JACK_SENSE bit also reports when a
jack has been removed. Set the IJACK_SENSE interrupt mask bit to signal the
system when the status of JACK_SENSE changes.
2
JACK_SENSE
R
0
0 = Mechanical jack switch shows removed.
1 = Mechanical jack switch shows connected.
Microphone Switch Status
MCSW goes high when the microphone bias goes to low for the debounce
period plus the delay period. This happens when a switch shorts across the
microphone, pulling the micbias node down, indicating a keypress from a hook
switch, ADC ≤ 9 LSB (Calculated assuming 2.6 kΩ bias resistor). Also during
sleep mode, but without delay time. RESET WHEN READ.
MCSW is also used when a button is pressed while in sleep mode.
0 = No change in mic bias, no switch press.
1
0
MCSW
R
R
0
0
1 = Mic bias has been pulled to ground and debounced since the last status
read. Debounce time set by KEY_DEB. Delay time set by KEY_DEL.
Reserved. Write only default value.
7.5.6.2 Register 0x01: Config and Device Status Register 2
READ /
WRITE
BIT
NAME
DEFAULT DESCRIPTION
Line-Level Audio on TIP Detected
7
LINE_L
R
0
0
0
0 = Line audio load on TIP not detected.
1 = Line audio load on TIP detected.
Line Level Audio on RING1 Detected
0 = Line audio load on RING1 not detected.
1 = Line audio load on RING1 detected.
6
5
LINE_R
HP_L
R
R
Headphone on TIP Detected
0 = Headphone load on TIP not detected.
1 = Headphone load on TIP detected.
Headphone on RING1 Detected
4
3
HP_R
R
R
0
0
0 = Headphone load on RING1 not detected.
1 = Headphone load on RING1 detected.
Reserved. Write only default value.
Passive Multi Button Headset KEY Status
KEY reports when the passive multibutton or single button has been pressed.
Data is available in KEYDATA. RESET WHEN READ.
0 = No button pressed.
2
KEY
R
0
1 = Button has been pressed/released.
Debounce and delay times have occurred.
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BIT
ZHCSDD5B –MARCH 2014–REVISED JANUARY 2015
READ /
WRITE
NAME
DEFAULT DESCRIPTION
Key Press/Release Event
This bit reports whether the current interrupt caused by the KEY or MCSW
status bits, is the result of a press or release.
1 = Current interrupt caused by a press.
0 = Current interrupt caused by a release.
When interrupt is caused by release, there is a delay of 0.5 ms in resetting this
bit from time interrupt is generated and KEY status bit is set. This bit is not set
when device is in Sleep Mode.
1
0
PRESS
R
R
0
0
Reserved. Write only default value.
7.5.6.3 Register 0x02: Config and Device Status Register 2
READ /
WRITE
BIT
NAME
DEFAULT DESCRIPTION
7-4
R
0000
Reserved. Write only default values.
Device Reset Status
Reports whether TPA6166A2 got reset after last register read. It can be used to
restore control register values, if device gets reset due to ESD strike. Interrupt is
generated to alert the system when this situation occurs. Interrupt is cleared
when this register bit is read. RESET WHEN READ.
0 = TPA6166A2 has not reset since last register read.
1 = TPA6166A2 has been reset since last register read.
3
2
RESET
R
R
0
0
Reserved. Write only default value.
Jack Common Location Identifier
The two GND bits tell the system whether the jack’s common connection is at
RING2 or SLEEVE. GND is also used to indicate when a jack has been
removed.
1-0
GND
R
00
00 = No common connection sensed, jack has been removed or nothing has
been inserted yet.
01 = The common jack connection is RING2.
10 = The common jack connection is SLEEVE.
11 = Common on both RING2 and SLEEVE.
7.5.6.4 Register 0x03: Reserved Register
READ /
WRITE
BIT
NAME
DEFAULT DESCRIPTION
0000 0000 Reserved.
7-0
R/W
7.5.6.5 Register 0x04: Interrupt Mask Register 1
The interrupt mask registers control which status bits will flag a system interrupt. Setting an interrupt mask bit will
cause IRQ to pull low whenever the target status bits set.
READ /
WRITE
BIT
NAME
DEFAULT DESCRIPTION
Jack Detect Interrupt Enable
0 = Disabled
1 = Enabled
7
IJKIN
R/W
0
0
Jack Configuration Detect Done Interrupt Enable
0 = Disabled
1 = Enabled
6
IDDONE
IVOL
R/W
Volume Slew Interrupt Enable
0 = Disabled
1 = Enabled
5
4
3
R/W
R
0
0
0
Reserved. Write only default value.
Microphone Interrupt Enable
0 = Disabled
IMIC
R/W
1 = Enabled
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READ /
WRITE
BIT
NAME
DEFAULT DESCRIPTION
JACK_SENSE Status Interrupt Enable
0 = Disabled
2
IJACK_SENSE
R/W
0
1 = Enabled
Mic Switch Interrupt Enable
0 = Disabled
1 = Enabled
1
0
IMCSW
R/W
R/W
0
0
Reserved. Always write 0.
7.5.6.6 Register 0x05: Interrupt Mask Register 2
READ /
WRITE
BIT
NAME
DEFAULT DESCRIPTION
Line Level Audio Load TIP Interrupt Enable
0 = Disabled
1 = Enabled
7
ILINE_L
R/W
0
0
0
Line Level Audio Load RING1 Interrupt Enable
0 = Disabled
1 = Enabled
6
5
ILINE_R
IHP_L
R/W
R/W
Headphone Audio Load TIP Interrupt Enable
0 = Disabled
1 = Enabled
Headphone Audio Load RING1 Interrupt Enable
4
3
2
IHP_R
R/W
R
0
0
0
0 = Disabled
1 = Enabled
Reserved. Write only default value.
KEY Interrupt Enable
0 = Disabled
IKEY
R/W
1 = Enabled
1
0
R/W
R/W
0
0
Reserved. Write only default value.
Reserved. Always write 0.
7.5.6.7 Register 0x06: Reserved Register
READ /
WRITE
BIT
NAME
DEFAULT DESCRIPTION
0000 0000 Reserved.
7-0
R/W
7.5.6.8 Register 0x07: Headphone Volume Register 1
The headphone volume registers independently control and report the gain of the left and right headphone
amplifiers. Set Bit 7 in register 0x07 to have the right channel gain track the left.
READ /
WRITE
BIT
NAME
DEFAULT DESCRIPTION
Left/Right Tracking
0 = The right channel volume control is independent of the left.
7
L=R
R/W
1
1
1 = The left and right volume controls track each other allowing for only one
register to be written to change both channel volumes. Control both volume
controls by writing to LVOL.
Left Headphone Mute
0 = Disable.
6
MUTEL
R/W
1 = Enable, output is muted.
30
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TPA6166A2
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BIT
ZHCSDD5B –MARCH 2014–REVISED JANUARY 2015
READ /
WRITE
NAME
DEFAULT DESCRIPTION
Left Headphone Volume Control
00 xxxx = –42 dB
01 0000 = –41 dB
01 0001 = –40 dB
01 0010 = –39 dB
...
5-0
LVOL
R/W
00 0000
11 1001 = 0 dB
...
11 1111 = +6 dB
7.5.6.9 Register 0x08: Headphone Volume Control Register 2
READ /
WRITE
BIT
NAME
DEFAULT DESCRIPTION
Extended Line-Out Stability
0 = Audio Channel does not support gain less than 0 dB for line-out load with
large capacitive load (>100 pF).
7
LO_EXT_STAB
R/W
0
1 = Audio Channel supports all gains for line-out load with max capacitive load of
470 pF.
Right Headphone Mute
0 = Disable.
1 = Enable, output is muted.
6
MUTER
RVOL
R/W
R/W
1
Right Headphone Volume Control
00 xxxx = –42 dB
01 0000 = –41 dB
01 0001 = –40 dB
01 0010 = –39 dB
...
5-0
00 0000
11 1001 = 0 dB
...
11 1111 = +6 dB
7.5.6.10 Register 0x09: Microphone Bias Control Register
The microphone bias register controls which microphone bias voltage and bias resistors are used, as well as the
debounce time when a key press is detected.
READ /
WRITE
BIT
NAME
DEFAULT DESCRIPTION
Mic preamplifier Mute Control during button press
Enable/Disable of Mic preamplifier Mute, when button (active/passive multi-
button headset) is pressed.
7
DIS_MIC_MUTE
R/W
0
0 – Mic Preamplifier is muted during button press. (Default)
1 – Mic Preamplifier is not muted during button press.
Microphone Preamplifier Gain Select
6
GAIN
MICR
BIAS
R/W
R/W
0
0 = 12dB
1 = 24dB
Microphone Bias Resistor Select
000 = 2.2 kΩ
001 = 2.6 kΩ
010 = 3.0 kΩ
011 = Bypassed
1xx = Invalid
5-3
000
Microphone Bias Voltage Select
0 = 2.0 V
1 = 2.6 V
2
R/W
R/W
0
1-0
11
Reserved. Always write 00. Needs to be initialized to 00 after device power up.
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TPA6166A2
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www.ti.com.cn
7.5.6.11 Register 0x0a: Reserved
READ /
WRITE
BIT
NAME
DEFAULT DESCRIPTION
7-0
R
0000 0000 Reserved.
7.5.6.12 Register 0x0b: Revision ID Register
READ /
WRITE
BIT
NAME
DEFAULT DESCRIPTION
7-4
3-0
REV
R
R
0011
Revision ID
Reserved.
7.5.6.13 Register 0x0c: Reserved Register
READ /
WRITE
BIT
NAME
DEFAULT DESCRIPTION
7-0
R/W
0001 1100 Reserved.
7.5.6.14 Registers 0x0d to 0x10: Reserved Registers
READ /
WRITE
BIT
NAME
DEFAULT DESCRIPTION
7-0
R/W
0000 0000 Reserved.
7.5.6.15 Register 0x11: Reserved
READ /
WRITE
BIT
NAME
DEFAULT DESCRIPTION
7-0
R/W
0000 0000 Reserved. Always write 0 to this register.
7.5.6.16 Register 0x12: Reserved
READ /
WRITE
BIT
NAME
DEFAULT DESCRIPTION
7-0
R/W
0000 0000 Reserved. Always write 0x01.
7.5.6.17 Register 0x13: Reserved
READ /
WRITE
BIT
NAME
DEFAULT DESCRIPTION
7-0
R/W
0000 0000 Reserved. Always write 0x45.
7.5.6.18 Register 0x14: Reserved Register
READ /
WRITE
BIT
NAME
DEFAULT DESCRIPTION
7-0
R
0000 0000 Reserved.
32
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ZHCSDD5B –MARCH 2014–REVISED JANUARY 2015
7.5.6.19 Register 0x15: Keyscan Debounce Register
The keyscan debounce register controls the debounce time when a keypress is detected.
READ /
WRITE
BIT
NAME
DEFAULT DESCRIPTION
Keyscan Debounce Register
Debounce time set from 0.25 ms to 63.75 ms in 0.25 ms increments. The
programmed code plus 0.25 represents the debounce time directly, i.e. code
0x4F represents 20 ms of debounce.
7-0
KEY_DEB
R/W
0000 0000
7.5.6.20 Register 0x16: Keyscan Delay Register
The keyscan delay register sets the timeout that the mic button press is masked from the system. At the end of
the delay time, the TPA6166A2 checks to see if a microphone is still present. If the mic is present, the system is
alerted by setting the MCSW bit in the status register, flagging an interrupt if IMCSW is set. If the mic is not
present after the delay time, then the system is flagged with an interrupt by setting MIC_IN, which signifies the
mic has been removed and no keypress was made. This prevents accessory removal from being detected as a
button press (due to RING2 and SLEEVE getting shorted during removal).
READ /
WRITE
BIT
NAME
DEFAULT DESCRIPTION
Keyscan Delay Register
Delay time set from 1 ms to 256 ms in 1-ms increments. The programmed code
plus one multiplied by 1 ms represents the delay time, that is, code 0xC7
represents 200 ms of delay.
7-0
KEY_DEL
R/W
0000 0000
7.5.6.21 Register 0x17: Passive Multi Button Keyscan Data Register
The keyscan data register contains the data read from a keypress after the 10-bit ADC encodes the input voltage
level. The read keypress could come from a single switch or a passive multi-button device.
READ /
WRITE
BIT
NAME
DEFAULT DESCRIPTION
Keyscan Data Divider
Keyscan data should be inferred based on Equation 1. When the 10-bit ADC
output is less than 128 (that is, 3 MSBs will be equal to 0), KEYDATA_DIV is set
to 0 and 7 LSBs are reported in KEYDATA.
When 10-bit ADC output is more than or equal to 128, KEYDATA_DIV is set to 1
and 9 LSBs of ADC Data divided by 4 (and rounded off) are reported in
KEYDATA. This loses resolution for high value of Rswitch||Rmic, which is
acceptable.
7
KEYDATA_DIV
R
0
Keyscan Data
6-0
KEYDATA
R
000 0000 B6-B0 are read only bits that contain the data read from a passive keypress that
shorts the microphone to ground.
æ
ö
÷
÷
ç
ç
R
BIAS
R
R
|| R
=
=
(If KEYDATA_DIV = 0)
(If KEYDATA_DIV = 1)
SWITCH
SWITCH
MIC
MIC
3072
ç
÷
-1
-1
ç
÷
KEYDATA
è
ø
æ
ç
ç
ö
÷
÷
R
BIAS
|| R
768
ç
÷
ç
÷
KEYDATA
è
ø
(1)
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7.5.6.22 Register 0x18: Jack Detect Test Hardware Settings
READ /
WRITE
BIT
NAME
DEFAULT DESCRIPTION
Maximum Impedance During Short
Defines maximum impedance below which terminal is considered short. This
7
SHORT_Z
R/W
0
information is used while detecting whether RING1 (terminal 2) is ground.
0 = 4 Ω
1 = 7 Ω
Threshold Impedance to Distinguish Between Headphone and line-out Load
Defines impedance below which load is Headphone and above is line-out.
0 = 700 Ω
1 = 1.5 kΩ
6
HP_LO_TH
R/W
R
0
5-0
00 0000
Reserved.
7.5.6.23 Register 0x19:State Register
READ /
WRITE
BIT
NAME
DEFAULT DESCRIPTION
Load State Force Enable
0 = Force configuration of the load into the state programmed by B6-B0.
1 = State forcing disabled. B6-B0 reports the configuration reported by the jack
configuration algorithm.
When FORCE bit is changed from 0 to 1, the TPA6166A2 will not re-un
accessory detection algorithm and configuration will continue to set to value
already written in STATE bits. System will need to reset and then set SHDN to
rerun accessory detection algorithm.
7
FORCE
R/W
1
Accessory State
6-0
STATE
R/W
000 0000 Bits B6-B0 represents accessory type
Refer to Table 6 for the state table.
Table 6. State Lookup for Register 0x19, Bits 6-0
B6-B0
BIN
COMMENTS
TIP
RING1
RING2
SLEEVE
JACK_SEN
SE
HEX
0x00
0x01
0x02
0x0A
0x0B
0x0C
0x0D
0x0E
0x0F
0x10
0x11
0x12
0x1A
0x1B
0x1C
0x1F
000 0000
000 0001
000 0010
000 1010
000 1011
000 1100
000 1101
000 1110
000 1111
001 0000
001 0001
001 0010
001 1010
001 1011
001 1100
001 1111
Nothing
Float
HPL
HPL
HPL
HPL
HPL
HPL
HPL
HPL
HPL
HPL
Float
LOL
Float
HPR
HPR
Ground
Ground
HPL
Float
Float
Short
Open
Open
Open
Open
Open
Open
Open
Open
Open
Open
Open
Open
Open
Open
Open
Stereo Headset (HP with mic)
Ground
Mic
Mic
Ground
Mic
Mono Headset
Ground
Mic
Ground
Mic
Ground
Mic
HPL
Ground
Mic
Float
Float
HPR
Float
HPR
LOR
Ground
Mic
Ground
Ground
Ground
Ground
Ground
Ground
Ground
Ground
Stereo Headphone
Stereo Line Out Audio Cable
Unsupported
Ground
Ground
Ground
Ground
Ground
Cap / Float LOR
LOL
Cap / Float Cap / Float Ground
Cap / Float Ground
34
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TPA6166A2
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ZHCSDD5B –MARCH 2014–REVISED JANUARY 2015
7.5.6.24 Register 0x1a: Jack Detect Test Hardware Settings
READ /
BIT
NAME
DEFAULT DESCRIPTION
Debounce Time during Jack Insertion/Removal Detection
WRITE
R/W
R
Controls debounce time on comparators output during Jack Insertion / Removal
Detection
7
6
JACK_DEB
0
0 = 3 ms (insertion and Sleep mode button press); 12 ms (removal detection)
1 = 20 ms (insertion and Sleep mode button press); 80 ms (removal detection)
0
Reserved.
Pulse Test Repeat
Control the number of times the pulse test is repeated. The more times the test
is repeated, the more accurate the results will be. The final result is the average
of all the tests.
5-4
AC_REPEAT
R/W
01
00 = Test runs once
01 = Test runs 2 times
10 = Test runs 4 times
11 = Test runs 8 times
Pulse Width Control
00 = 50 µs
3-2
1-0
PULSE_WIDTH
PULSE_AMP
R/W
R/W
01
01
01 = 25 µs
10 = 100 µs
11 = 200 µs
Pulse Amplitude Control
00 = VDD / 36 (50 mV)
01 = VDD / 72 (25 mV)
10 = VDD / 18 (100 mV)
11 = VDD / 9 (200 mV)
7.5.6.25 Registers 0x1b: Reserved
READ /
WRITE
BIT
NAME
DEFAULT DESCRIPTION
7-0
R/W
0000 0000 Reserved.
7.5.6.26 Register 0x1c: Clock Control
Write 0x00 to this register at power-up. This ensures best performance from the TPA6166A2.
READ /
WRITE
BIT
NAME
DEFAULT DESCRIPTION
Clock control for passive multi-button headset
0 = Clock is not turned on.
1 = Clock is turned on. Write this bit when passive multi-button functionality is
required with headset inserted and device is not in Sleep/Shutdown mode.
Along-with this bit, also write following sequence:
Register: 0x66, Value: 0xF1
Register: 0x6F, Value: 0x01
Register: 0x66, Value: 0x00
CLOCK_CONTRO
L
7
R/W
0
When CLOCK_CONTROL is set to 0 (due to device going into Sleep/Shutdown
mode), write following sequence:
Register: 0x66, Value: 0xF1
Register: 0x6F, Value: 0x00
Register: 0x66, Value: 0x00
7-0
R/W
000 0001 Reserved. Always write 000 0000
7.5.6.27 Register 0x1d: Enable Register 1
The Enable registers contain all of the bits that control the separate functional blocks for the TPA6166A2. The
system can either directly control these bits, or it can allow TPA6166A2 to automatically configure itself and
report in the Enable register which blocks are enabled. When the AUTO bits (B1-B0) are set to 01 or 10, the
Enable Registers are read only. The block enable bits do not need to be set to sense a jack removal. The jack
removal circuitry is active as soon as an inserted jack is detected.
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READ /
WRITE
BIT
NAME
DEFAULT DESCRIPTION
Full Device Shutdown Control
SHDN turns TPA6166A2 on and off. When SHDN is low, the device is in low
power mode and the jack insertion detect circuitry is active. Pull SHDN high to
turn on the device and run the jack configuration detect algorithm. Typically
SHDN will be held low until the system gets an interrupt from the indicating that
a jack has been inserted. The system will then pull SHDN high.
0 = TPA6166A2 in lowest power shutdown mode. During this mode, accessory
insertion/removal detection works only if jack switch not broken. If switch is
broken, status will be reported as if accessory is inserted (even if accessory is
not inserted or it is removed). SLEEP setting is ignored during this mode.
1 = TPA6166A2 is active. The jack configuration algorithm runs immediately
after SHDN is pulled high.
7
SHDN
R/W
0
Sleep Mode Enable
Pull SLEEP high to enable the circuitry that looks for accessory insertion/removal
and button press (for headset with Mic) when TPA6166A2 is shutdown. When a
button press (for headset with Mic) is sensed, the MCSW bit in the status
register is set, generating an interrupt if IMCSW is set.
0 = TPA6166A2 is in normal mode as long as SHDN is set.
1 = TPA6166A2 is in sleep mode. During this mode, accessory insertion and
removal detection works even for broken Jack switch. For Headset with Mic
cases, button press will generate an interrupt, which can be used for system
wakeup.
6
SLEEP
R/W
0
When device is programmed in Sleep mode (SLEEP=1), following sequence
must to used to ensure best performance:
Disable Auto mode and headphone amplifiers by programming register 0x1E,
bits D1D0 to 00 and bits D7D6 to 00
Enable Auto mode by programming register 0x1E, bit D1D0 to 01
5
4
R
0
0
Reserved.
Microphone Bias Enable/Status
Set MIC_BIAS to enable the mic bias block. This bit is read only when AUTO
(B1-B0) is set to 01 or 10.
0 = Microphone bias is disabled.
1 = Microphone bias is active.
MIC_BIAS
MIC_AMP
R/W
Microphone Amplifier Enable/Status
Set MIC_AMP to enable the mic amp. This bit is read only when AUTO (B1-B0)
is set to 01 or 10.
0 = Microphone amp is disabled.
1 = Microphone amp is active.
3
2
R/W
0
0
Keyscan Enable/Status
KS enables the circuitry that decodes passive multi-button keypad or simple
microphone switch.
KS
R
0 = Keyscan ADC is disabled.
1 = Keyscan ADC is enabled.
This bit is always Read Only (regardless of AUTO bits setting).
1
0
R
R
0
0
Reserved.
Reserved.
7.5.6.28 Register 0x1e: Enable Register 2
Set Register 0x1E, Bit 4 to 1 to ensure the best performance from the TPA6166A2.
READ /
WRITE
BIT
NAME
DEFAULT DESCRIPTION
Left Headphone Enable/Status
Set LFTEN to enable the left channel of the DirectDrive headphone amplifier.
This bit is read only when AUTO (B1-B0) is set to 01 or 10.
0 = Headphone amp left channel disabled
7
LFTEN
R/W
0
1 = Headphone amp left channel enabled
Right Headphone Enable/Status
Set RGHEN to enable the right channel of the DirectDrive headphone amplifier.
This bit is read only when AUTO (B1-B0) is set to 01 or 10.
0 = Headphone amp right channel disabled
6
RGHEN
R/W
0
1 = Headphone amp right channel enabled
36
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TPA6166A2
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BIT
ZHCSDD5B –MARCH 2014–REVISED JANUARY 2015
READ /
WRITE
NAME
DEFAULT DESCRIPTION
Volume Adjustment Slewing
Volume changes are smoothed by stepping through intermediate steps. VSEN
also ensures that the volume automatically ramps from the minimum setting to
the programmed value at turnon and back to the minimum value at turnoff.
0 = Enabled
5
4
VSEN
R/W
R/W
0
0
1 = Disabled
Reserved. Always write 1.
Jack Insertion Polling Speed
A fast polling speed tests for a jack insertion 3 times per second while a slow
polling speed tests for jack insertion every 2 seconds. This setting is valid only
when mechanical TERMINAL5 switch is not operational. When mechanical
TERMINAL5 switch is operational, detection is instantaneous (excluding
debounce time and detection time).
3
2
FAST
THRH
R/W
R/W
0
0
0 = Slow polling mode, 2-sec delay between polls
1 = Fast polling mode, 333-ms delay between polls
Class-G Threshold
Select THRH selects the threshold at which the power supplies switch from
±0.9 V to ±1.8 V. A higher threshold allows the TPA6166A2 output stage to be
powered from ±0.9 V for a higher percentage of the audio waveform, decreasing
power dissipation at the expense of dynamic distortion.
0 = Low Threshold
1 = High Threshold
Automatic Mode
Select Set AUTO to allow the TPA6166A2 to enable functional blocks depending
on the load. In auto mode the system merely reads the status of registers 0x1D
and 0x1E to find out what blocks are enabled. Setting AUTO makes bits register
0x1D and 0x01E read only. Clear AUTO to give the system control of what
functional blocks are active. The system would need to allow the jack
configuration detect algorithm to complete before enabling functional blocks.
00 = System controls which functional blocks are on. Registers 0x1D and 0x1E
are R/W. SHDN and SLEEP settings are ignored.
1-0
AUTO
R/W
01
01 = TPA6166A2 enables functional blocks automatically depending on the
results of the jack configuration detect algorithm provided that SLEEP is set to 0
(SHDN must be set to 1, otherwise device will go into low power state).
10 = TPA6166A2 enables functional blocks automatically depending on the
results of the jack configuration detect algorithm regardless of settings of SHDN
and SLEEP.
11 = Invalid.
7.5.6.29 Register 0x1F: Reserved
READ /
WRITE
BIT
NAME
DEFAULT DESCRIPTION
7-0
R
0000 0000 Reserved.
7.5.6.30 Register 0x66: Clock Flex Register
READ /
WRITE
BIT
NAME
DEFAULT DESCRIPTION
7-0
CLOCK_FLEX
R/W
0000 0000 Reserved. Write 0xF1 to use Register 0x6F, then set back to zero.
7.5.6.31 Register 0x6F: Clock Set Register
READ /
WRITE
BIT
NAME
DEFAULT DESCRIPTION
Write 0x01 when passive button detection is needed in Active mode. (accessory
7-0
CLOCK_SET
R/W
0000 0000 is inserted, and device is not in Sleep/Shutdown mode). Reset to 0x00 when the
device is going to sleep to save power.
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www.ti.com.cn
8 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
8.1 Application Information
This section describes a typical application of TPA6166A2 with a standard audio jack with battery voltage level
supply. The circuit detects what kind of device is plugged into the jack and delivers excellent audio quality.
8.2 Typical Application
Figure 32 shows a typical application circuit for the TPA6166A2 with a 5-terminal audio jack. Accessory
Detection describes all the accessory jack configurations the TPA6166A2 automatically detects.
1.8 V Supply
1.0 pF 1.0 pF
1.0 pF
2.4 - 3.6 V Supply
CPVDD CPVSS
C1P C1N
VDD
MICVDD
0.47 pF
0.47 pF
RING1
TIP
Class-G
Stereo Headphone
Amplifier
INL
EMI
Filter
2
1
5
INR
ESD
Prot.
1
2
3
4
Analog
Baseband
GND1
GND2
JACK_SENSE
Switch
Matrix
and
Mic
Bias
RING2
EMI
Filter
3
4
Detection
Circuit
SLEEVE
MOUTP
MOUTN
10 kW 10 kW
SDA
SAR
ADC
SCL
IRQ
Digital
Interface
and
Digital
Baseband
Control
PGND
Figure 32. Typical Application Circuit
8.2.1 Design Requirements
Table 7. Design Parameters
DESIGN PARAMETERS
VALUE
VDD Supply voltage
1.7 V to 1.9 V
2.4 V to 3.6 V
MICVDD Microphone supply voltage
8.2.2 Detailed Design Procedure
8.2.2.1 Charge Pump Capacitors
The CPVDD and CPVSS capacitor must be at least equal in value to the flying capacitor to allow maximum
charge transfer. Use low ESR (example: < 20 mΩ at 1.3 MHz) ceramic capacitors to maximize charge pump
efficiency. X5R-type capacitors or better are required for best performance. Typical values are 1 µF to 2.2 µF for
the charge pump capacitors.
38
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TPA6166A2
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Charge pump capacitors should be able to handle up to 2 V during normal operation. During IEC ESD strike on
jack terminals, voltage on these capacitors can go as high as 12 V for 30 to 40 ns. Capacitors rated for 6.3 V or
higher can typically handle such voltages for short durations without getting damaged.
8.2.2.2 Audio Input ac Coupling Capacitors
Input coupling capacitors block any dc bias from the audio source and ensure maximum dynamic range. Input
coupling capacitors also minimize TPA6166A2 turnon pop to an inaudible level. The input capacitors are in series
with TPA6166A2 internal input resistors, creating a high-pass filter. Equation 2 calculates the high-pass filter
corner frequency. The TPA6166A2 typical input impedance, RIN, is 20 kΩ.
1
fC =
2pRINCIN
(2)
For a given high-pass cutoff frequency, the minimum input coupling capacitor is:
1
CIN
=
2pfCRIN
(3)
Example: Select input coupling capacitor values to achieve a 20 Hz high-pass corner frequency. Equation 3
shows the input coupling capacitors must be at least 0.4 μF. Choose a 0.47-μF standard value capacitor for each
TPA6166A2 input. Use X5R-type or better capacitors for best performance.
8.2.2.3 Suggested Output EMI Filter
To prevent noise getting radiated from headphone, EMI filters are often included on terminals connected to the
Jack. Figure 33 illustrates typical connection diagram of EMI filter implemented using ‘pi’ configuration.
120W 1.2A (such as BLM18BB220SN1)
Jack Connector
Pin1/2/3/4 from IC
33pF
33pF
Figure 33. EMI Filter
High-frequency impedance of RF beads in range of 100 MHz can impact IEC ESD performance on TPA6166A2
jack outputs (LOUT, PIN2_ROUT, PIN3, and PIN4). Higher impedances change the waveform during IEC strike
to make it wider, which subjects internal circuit to stress for longer duration. Use RF beads which are equal to or
less than 22-Ω impedance at 100 MHz.
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8.2.3 Application Curve
The high quality and low distortion of the TPA6166A2 mic preamplifier is shown in Figure 34.
1
MICVDD = 2.4 V
MICVDD = 3.0 V
MICVDD = 3.6 V
0.1
0.01
0.001
20
100
1k
10k 20k
f − Frequency − Hz
Figure 34. Mic Preamplifier Total Harmonic Distortion + Noise vs Frequency
9 Power Supply Recommendations
The TPA6166A2 has two power-supply domains, VDD and MICVDD. The TPA6166A2 allows VDD and MICVDD
supplies to come up in any order. The Internal circuit of the TPA6166A2 has diodes between VDD and MICVDD
supply domain, which are reversed bias during normal operation. If MICVDD voltage is less than VDD, these
diodes can get forward bias and drive MICVDD. If the application requires that the MICVDD terminal not be
driven in such a condition, an external switch on MICVDD can be used. I2C read/write and the accessory-
detection algorithm is disabled until both VDD and MICVDD supplies are up. During operation, if the MICVDD
supply goes below its normal operating voltage, the control-register contents are still preserved. Once the supply
comes up again, the accessory detection algorithm runs again to ensure the correct state. If the MICVDD supply
is not powered up, the SDA line can be clamped by TPA6166A2. This is due to the internal ESD protection
structure on SDA being biased based on MICVDD.
9.1 Decoupling Capacitors
The TPA6166A2 requires adequate power supply decoupling to ensure that output noise and total harmonic
distortion (THD) remain low. Use quality low equivalent-series-resistance (ESR) ceramic capacitors (X5R
material or better is required for best performance). Place a 1-μF capacitor within 5 mm of the VDD and MICVDD
terminal. Reducing the distance between the decoupling capacitor and VDD/MICVDD minimizes parasitic
inductance and resistance, improving TPA6166A2 supply rejection performance. Use 0402 or smaller size
capacitors if possible. Ensure that the ground connection of each of the capacitors has a minimum-length return
path to the device. Failure to properly decouple the TPA6166A2 may degrade audio or EMC performance.
40
Copyright © 2014–2015, Texas Instruments Incorporated
TPA6166A2
www.ti.com.cn
ZHCSDD5B –MARCH 2014–REVISED JANUARY 2015
10 Layout
10.1 Layout Guidelines
The ground terminal must be connected to the ground plane as close as possible to the TPA6166A2, to minimize
any inductance in the path. Place the decoupling capacitor as close as possible to the supply terminal,
minimizing trace length (and thus the inductance) on the decoupling capacitor connection to ground.
Because INL and INR are single-ended inputs, take care to minimize noise on INL and INR with respect to
TPA6166A2 ground. This is best achieved by using then same ground plane for the signal source and the
TPA6166A2 with a minimum inductance between them.
The accessory-detection algorithm requires trace capacitance to be minimized between TPA6166A2 and the
jack. Depending upon headphone impedance, trace resistance between TPA6166A2 and the jack impacts power
delivered to load. If trace resistance is much smaller than headphone impedance, power loss is given by
Equation 4. Trace resistance should be minimized based on acceptable power loss.
Trace Resistance
Power Loss =
Headphone Resistance
(4)
To minimize crosstalk, trace resistance on RING2 (terminal 3) and SLEEVE (terminal 4) should be minimized.
This can be achieved by placing TPA6166A2 close to the jack. For cases where trace resistance is not small,
crosstalk is given by Equation 5. In such scenarios, best balance can be achieved by increasing trace width of
SLEEVE. RING2 has no constraint on maximum capacitance, and its trace width can be maximized to achieve
desired crosstalk performance.
æ
ç
è
ö
÷
ø
Trace Resistance
Crosstalk (dB) = 20log
10
Headphone Resistance + Trace Resistance
(5)
Copyright © 2014–2015, Texas Instruments Incorporated
41
TPA6166A2
ZHCSDD5B –MARCH 2014–REVISED JANUARY 2015
www.ti.com.cn
10.2 Layout Example
10.2.1 Pad Sizing
When determining the pad size for the WCSP terminals, use nonsolder mask defined (NSMD) land. With this
method, the solder mask opening is made larger than the desired land area, and the opening size is defined by
the copper pad width. Figure 35 and Table 8 show the appropriate diameters for a WCSP layout.
Copper Trace Width
Solder Pad Width
Solder Mask Opening
Copper Trace Thickness
Solder Mask Thickness
M0200-01
Figure 35. Land Pattern Dimensions
(1)(2)(3)(4)
Table 8. Land Pattern Dimensions
SOLDER PAD
DEFINITION
SOLDER MASK(5)
OPENING
COPPER
THICKNESS
STENCIL(6) (7)
OPENING
STENCIL
THICKNESS
COPPER PAD
Nonsolder mask
defined (NSMD)
275 μm × 275 μm sq.
(rounded corners)
230 μm
310 μm
1 oz. max. (32 μm)
100 μm thick
(1) Circuit traces from NSMD-defined PWB lands should be 75 μm to 100 μm wide in the exposed area inside the solder mask opening.
Wider trace widths reduce device standoff and impact reliability.
(2) Best reliability results are achieved when the PWB laminate glass transition temperature is above the operating range of the intended
application.
(3) Recommended solder paste is type 3 or type 4.
(4) For a PWB using a Ni/Au surface finish, the gold thickness should be less 0.5 mm to avoid a reduction in thermal fatigue performance.
(5) Solder mask thickness should be less than 20 µm on top of the copper circuit pattern.
(6) Best solder stencil performance is achieved using laser-cut stencils with electro polishing. Use of chemically etched stencils results in
inferior solder paste volume control.
(7) Trace routing away from WCSP device should be balanced in X and Y directions to avoid unintentional component movement due to
solder wetting forces.
Table 9. Package Dimensions
D
E
Max. = 2470 µm
Typ. = 2440 µm
Min. = 2410 µm
Max. = 2470 µm
Typ. = 2440 µm
Min. = 2410 µm
42
Copyright © 2014–2015, Texas Instruments Incorporated
TPA6166A2
www.ti.com.cn
ZHCSDD5B –MARCH 2014–REVISED JANUARY 2015
11 器件和文档支持
11.1 开发支持
请参见《TPA6166A2EVM 用户指南》，SLOU381。
11.2 商标
DirectPath is a trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
11.3 静电放电警告
这些装置包含有限的内置 ESD 保护。 存储或装卸时，应将导线一起截短或将装置放置于导电泡棉中，以防止 MOS 门极遭受静电损
伤。
11.4 术语表
SLYZ022 — TI 术语表。
这份术语表列出并解释术语、首字母缩略词和定义。
12 机械封装和可订购信息
以下页中包括机械封装和可订购信息。 这些信息是针对指定器件可提供的最新数据。 这些数据会在无通知且不对
本文档进行修订的情况下发生改变。 欲获得该数据表的浏览器版本，请查阅左侧的导航栏。
版权 © 2014–2015, Texas Instruments Incorporated
43
PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
TPA6166A2YFFR
TPA6166A2YFFT
ACTIVE
ACTIVE
DSBGA
DSBGA
YFF
YFF
25
25
3000 RoHS & Green
250 RoHS & Green
SNAGCU
Level-1-260C-UNLIM
Level-1-260C-UNLIM
-40 to 85
-40 to 85
SMB
SMB
SNAGCU
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
17-Jun-2015
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
TPA6166A2YFFR
TPA6166A2YFFT
DSBGA
DSBGA
YFF
YFF
25
25
3000
250
180.0
180.0
8.4
8.4
2.54
2.54
2.54
2.54
0.76
0.76
4.0
4.0
8.0
8.0
Q1
Q1
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
17-Jun-2015
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SPQ
Length (mm) Width (mm) Height (mm)
TPA6166A2YFFR
TPA6166A2YFFT
DSBGA
DSBGA
YFF
YFF
25
25
3000
250
182.0
182.0
182.0
182.0
20.0
20.0
Pack Materials-Page 2
PACKAGE OUTLINE
YFF0025
DSBGA - 0.625 mm max height
S
C
A
L
E
6
.
0
0
0
DIE SIZE BALL GRID ARRAY
B
E
A
BUMP A1
CORNER
D
C
0.625 MAX
SEATING PLANE
0.05 C
BALL TYP
0.30
0.12
1.6 TYP
SYMM
E
D
D: Max = 2.47 mm, Min = 2.41 mm
E: Max = 2.47 mm, Min = 2.41 mm
SYMM
1.6
C
B
A
TYP
0.4 TYP
3
4
5
1
2
0.3
0.2
25X
0.4 TYP
0.015
C A B
4223786/A 06/2017
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
www.ti.com
EXAMPLE BOARD LAYOUT
YFF0025
DSBGA - 0.625 mm max height
DIE SIZE BALL GRID ARRAY
(0.4) TYP
3
25X ( 0.23)
(0.4) TYP
1
2
4
5
A
B
SYMM
C
D
E
SYMM
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE:25X
0.05 MAX
(
0.23)
0.05 MIN
(
0.23)
METAL
SOLDER MASK
OPENING
EXPOSED METAL
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
EXPOSED METAL
NON-SOLDER MASK
DEFINED
SOLDER MASK
DEFINED
(PREFERRED)
SOLDER MASK DETAILS
NOT TO SCALE
4223786/A 06/2017
NOTES: (continued)
3. Final dimensions may vary due to manufacturing tolerance considerations and also routing constraints.
For more information, see Texas Instruments literature number SNVA009 (www.ti.com/lit/snva009).
www.ti.com
EXAMPLE STENCIL DESIGN
YFF0025
DSBGA - 0.625 mm max height
DIE SIZE BALL GRID ARRAY
(0.4) TYP
25X ( 0.25)
(R0.05) TYP
3
1
2
4
5
A
B
C
(0.4) TYP
METAL
TYP
SYMM
D
E
SYMM
SOLDER PASTE EXAMPLE
BASED ON 0.1 mm THICK STENCIL
SCALE:30X
4223786/A 06/2017
NOTES: (continued)
4. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release.
www.ti.com
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