TP3056BDW [TI]
MONOLITHIC SERIAL INTERFACE COMBINED PCM CODEC AND FILTER; 整体式串行接口联合PCM编解码器和过滤器
| 型号： | TP3056BDW |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | MONOLITHIC SERIAL INTERFACE COMBINED PCM CODEC AND FILTER |
| 文件： | 总19页 (文件大小：288K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
TP3056B
MONOLITHIC SERIAL INTERFACE
COMBINED PCM CODEC AND FILTER
SLWS072A – MAY 1998 – REVISED AUGUST 1998
Complete PCM Codec and Filtering
Systems Include:
– Transmit High-Pass and Low-Pass
Filtering
– Receive Low-Pass Filter With (sin x)/x
Correction
µ-Law/A-Law Operation Pin-Selectable
±5-V Operation
Low Operating Power . . . 60 mW Typ
Power-Down Mode . . . 5 mW Typ
Automatic Power Down
– Active RC Noise Filters
– µ-Law and A-Law Compatible Coder and
Decoder
– Internal Precision Voltage Reference
– Serial I/O Interface
TTL- or CMOS-Compatible Digital Interface
Maximizes Line Interface Card Circuit
Density
– Internal Autozero Circuitry
DW OR N PACKAGE
(TOP VIEW)
description
VFXI+
VFXI–
GSX
TSX
FSX
DX
BCLK
MCLK
V
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
BB
The TP3056B monolithic serial interface
combined PCM codec and filter device is
comprised of a single-chip PCM codec (pulse
code-modulated encoder and decoder) and
analog filters. This device provides all the
functions required to interface a full-duplex
(2-wire) voice telephone circuit with a TDM
(time-division-multiplexed) system. Primary
applications include:
ANLG GND
VFRO
V
CC
FSR
DR
ASEL
PDN
•
Line interface for digital transmission and
switching of T1/E1 carrier, PABX, and central
office telephone systems
•
•
•
•
Subscriber line concentrators
Digital-encryption systems
Digital voice-band data-storage systems
Digital signal processing
The TP3056B is designed to perform the transmit encoding (A/D conversion) and receive decoding (D/A
conversion), and the appropriate filtering of analog signals in a PCM system. This device is intended to be used
at the analog termination of a PCM line or trunk. It requires a master clock of 2.048 MHz, a transmit/receive data
clock that is synchronous with the master clock (but can vary from 64 kHz to 2.048 MHz), and transmit and
receive frame-sync pulses. The TP3056B contains patented circuitry to achieve low transmit channel idle noise
and is not recommended for applications in which the composite signals on the transmit side are below
–55 dBm0.
This device, available in 16-pin N PDIP (plastic dual-in-line package) and 16-pin DW SOIC (small outline IC)
packages, is characterized for operation from 0°C to 70°C.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
Copyright 1998, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TP3056B
MONOLITHIC SERIAL INTERFACE
COMBINED PCM CODEC AND FILTER
SLWS072A – MAY 1998 – REVISED AUGUST 1998
functional block diagram
14
GSX
15
–
Switched-
Capacitor
Band-Pass Filter
RC
Active Filter
VFXI–
16
S/H
DAC
Analog
Input
Transmit
Regulator
11
Digital
Output
+
DX
VFXI+
OE
Voltage
Reference
Receive
Regulator
6
Digital
Input
Switched-
Capacitor
Low-Pass Filter
3
Analog
Output
S/H
DAC
RC Active
Filter
DR
VFRO
CLK
Power
Amplifier
13
Timing and Control
TSX
5 V
–5 V
1
9
8
10
7
5
12
4
2
MCLK
PDN
BCLK
ASEL FSR FSX
V
CC
V
BB
ANLG GND
2
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TP3056B
MONOLITHIC SERIAL INTERFACE
COMBINED PCM CODEC AND FILTER
SLWS072A – MAY 1998 – REVISED AUGUST 1998
Terminal Functions
TERMINAL
NAME
I/O
DESCRIPTION
NO.
2
ANLG GND
Analog ground. All signals are referenced to ANLG GND.
ASEL
7
I
I
A-law/µ-law select. When ASEL is connected to V , A-law is selected. When ASEL is connected to GND or V
µ-law is selected.
,
CC
BB
BCLK
10
Transmit/receive bit clock. BCLK shifts PCM data out on DX during transmit and shifts PCM data in through DR
during receive. BCLK can vary from 64 kHz to 2.048 MHz, but must be synchronous with MCLK.
DR
6
11
5
I
O
I
Receive data input. PCM data is shifted into DR at the trailing edge of the BCLK following the FSR leading edge.
DX is the 3-state PCM data output that is enabled by FSX. Data is shifted out on the rising edge of BCLK.
DX
FSR
Receive-frame sync pulse input. FSR enables BCLK to shift PCM data in DR. FSR is an 8-kHz pulse train (see
Figures 1 and 2 for timing details).
FSX
12
I
Transmit-frame sync pulse. FSX enables BCLK to shift out the PCM data on DX. FSX is an 8-kHz pulse train (see
Figures 1 and 2 for timing details).
GSX
14
9
O
I
Analog output of the transmit input amplifier. GSX is used to set gain externally.
Transmit/receive master clock. MCLK must be 2.048 MHz.
MCLK
PDN
8
I
Power down. When PDN is connected high, the device is powered down. When PDN is connected low or left
floating, the device is powered up. PDN is internally tied low.
TSX
13
1
O
Transmit channel time-slot strobe. TSX is an open-drain output that pulses low during the encoder time slot.
V
V
Negative power supply. V
= –5 V ±5%
= 5 V ±5%
BB
BB
4
Positive power supply. V
CC
CC
VFRO
VFXI+
VFXI–
3
O
I
Analog output of the receive channel power amplifier
Noninverting input of the transmit input amplifier
Inverting input of the transmit input amplifier
16
15
I
3
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TP3056B
MONOLITHIC SERIAL INTERFACE
COMBINED PCM CODEC AND FILTER
SLWS072A – MAY 1998 – REVISED AUGUST 1998
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)†
Supply voltage, V
(see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 V
CC
BB
Supply voltage, V (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –7 V
Voltage range at any analog input or output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . V
Voltage range at any digital input or output . . . . . . . . . . . . . . . . . . . . . . . . . . V
Continuous total dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Dissipation Rating Table
+0.3 V to V –0.3 V
CC
BB
+0.3 V to ANLG GND –0.3 V
CC
Operating free-air temperature range: TP3056B . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0°C to 70°C
Storage temperature range, T
Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds: DW or N package . . . . . . . . . . . . . . . 260°C
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150°C
stg
†
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTE 1: All voltages are with respect to GND.
DISSIPATION RATING TABLE
DERATING FACTOR
T
≤ 25°C
T
A
= 70°C
T = 85°C
A
A
PACKAGE
POWER RATING
ABOVE T = 25°C
POWER RATING POWER RATING
A
DW
N
1025 mW
8.2 mW/°C
9.2 mW/°C
656 mW
736 mW
533 mW
598 mW
1150 mW
recommended operating conditions (see Note 2)
MIN NOM
MAX
UNIT
V
Supply voltage, V
Supply voltage, V
4.75
–4.75
2.2
5
5.25
CC
–5 –5.25
V
BB
High-level input voltage, V
IH
V
Low-level input voltage, V
IL
Common-mode input voltage range, V
0.6
V
‡
±2.5
V
ICR
Load resistance, GSX, R
10
0
kΩ
pF
°C
L
Load capacitance, GSX, C
50
70
L
Operating free-air temperature, T
A
‡
Measured with CMRR > 60 dB
NOTE 2: To avoid possible damage to these CMOS devices and resulting reliability problems, the power-up procedure described in the device
power-up sequence paragraphs later in this document should be followed.
electrical characteristics over recommended ranges of supply voltage operating free-air
temperature range, in A-law and µ-law modes (unless otherwise noted)
supply current
TP3056B
PARAMETER
TEST CONDITIONS
No load
UNIT
mA
§
MIN TYP
MAX
Power down
Operating
0.5
6
1
9
1
9
I
I
Supply current from V
Supply current from V
CC
CC
Power down
Operating
0.5
6
No load
mA
BB
BB
§
All typical values are at V
= 5 V, V
= –5 V, and T = 25°C.
BB A
CC
4
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TP3056B
MONOLITHIC SERIAL INTERFACE
COMBINED PCM CODEC AND FILTER
SLWS072A – MAY 1998 – REVISED AUGUST 1998
electrical characteristics at V
otherwise noted)
= 5 V ±5%, V
= –5 V ±5%, GND at 0 V, T = 25°C (unless
BB A
CC
digital interface
PARAMETER
High-level output voltage
TEST CONDITIONS
= -3.2 mA
MIN
MAX
UNIT
V
V
DX
I
H
I
L
I
L
2.4
V
OH
DX
= 3.2 mA
= 3.2 mA,
0.4
0.4
Low-level output voltage
V
OL
TSX
Drain open
I
I
I
High-level input current
V = V to V
IH
±10
±10
±10
µA
µA
µA
IH
I
CC
Low-level input current
All digital inputs
DX
V = GND to V
IL
I
IL
= GND to V
CC
Output current in high-impedance state
V
O
OZ
analog interface with transmit amplifier input
†
PARAMETER
TEST CONDITIONS
MIN TYP
MAX
±2.5
±200
UNIT
V
‡
V
Common-mode input voltage range
Input current
ICR
I
I
VFXI+ or VFXI –
VFXI+ or VFXI –
VFXI+ to GSX
GSX
V = –2.5 V to 2.5 V
I
nA
r
Input resistance
V = –2.5 V to 2.5 V
I
10
5000
1
MΩ
i
A
V
Open-loop voltage amplification
Unity-gain bandwidth
Input offset voltage
B
I
2
MHz
mV
dB
V
IO
VFXI+ or VFXI –
±20
CMRR Common-mode rejection ratio
Supply-voltage rejection ratio
All typical values are at V = 5 V, V
60
60
K
dB
SVR
†
‡
= –5 V, and T = 25°C.
CC
Measured with CMRR > 60 dB.
BB
A
analog interface with receive amplifier output
PARAMETER
†
TEST CONDITIONS
MIN TYP
MAX
±2.5
3
UNIT
V
Receive output drive voltage
R = 10 kΩ
L
Output resistance
Load resistance
VFRO
1
Ω
VFRO = ±2.5 V
600
Ω
Load capacitance
Output dc offset voltage
VFRO to GND
VFRO to GND
500
pF
mV
±200
†
All typical values are at V
= 5 V, V
= –5 V, and T = 25°C.
BB A
CC
5
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TP3056B
MONOLITHIC SERIAL INTERFACE
COMBINED PCM CODEC AND FILTER
SLWS072A – MAY 1998 – REVISED AUGUST 1998
operating characteristics, over operating free-air temperature range, V
= 5 V ±5%,
CC
V
= –5 V ±5%, GND at 0 V, V = 1.2276 V, f = 1.02 kHz, transmit input amplifier connected for unity
BB
I
gain, noninverting, in A-law and µ-law modes, (unless otherwise noted)
filter gains and tracking errors
†
PARAMETER
TEST CONDITIONS
MIN TYP
MAX
UNIT
V
µ-law
3.17 dBm0
3.14 dBm0
2.501
2.492
Maximum peak transmit
overload level
A-law
‡
Transmit filter gain, absolute (at 0 dBm0)
T
= 25°C
– 0.15
0.15
–40
–30
–26
–0.1
0.15
0.05
0
dB
A
f = 16 Hz
f = 50 Hz
f = 60 Hz
f = 200 Hz
–1.8
–0.15
–0.35
–0.8
f = 300 Hz to 3000 Hz
f = 3300 Hz
‡
Transmit filter gain, relative to absolute
dB
f = 3400 Hz
f = 4000 Hz
–14
f ≥ 4600 Hz
(measure response from 0 Hz to 4000 Hz)
–32
‡
Absolute transmit gain variation with
temperature and supply voltage relative to
absolute transmit gain
–0.1
0.1
dB
dB
3 dBm0 ≥ input level
≥ –40 dBm0
±0.2
±0.4
±0.8
0.15
Sinusoidal test method,
Reference level = –10 dBm0
–40 dBm0 > input
level ≥ –50 dBm0
Transmit gain tracking error with level
–50 dBm0 > input
level ≥ –55 dBm0
Input is digital code sequence for 0-dBm0 signal,
= 25°C
‡
Receive filter gain, absolute (at 0 dBm0)
–0.15
dB
dB
dB
T
A
f = 0 Hz to 3000 Hz,
f = 3300 Hz
T
A
= 25°c
–0.15
–0.35
–0.8
0.15
0.05
0
‡
Receive filter gain, relative to absolute
f = 3400 Hz
f = 4000 Hz
–14
‡
Absolute receive gain variation with temperature
and supply voltage
T
A
= full range,
See Note 3
–0.1
0.1
±0.2
3 dBm0 ≥ input level
≥ –40 dBm0
Sinusoidal test method;
reference input PCM code
corresponds to an ideally
encoded –10 dBm0 signal
–40 dBm0 > input
level ≥ –50 dBm0
±0.4
Receive gain tracking error with level
dB
dB
–50 dBm0 > input
level ≥ –55 dBm0
±0.8
3 dBm0 ≥ input level
≥ –40 dBm0
±0.25
±0.3
Pseudo-noise test method;
reference input PCM code
corresponds to an ideally
encoded –10 dBm0 signal
–40 dBm0 > input
level ≥ –50 dBm0
Transmit and receive gain tracking error with
level (A-law, CCITT G 712)
–50 dBm0 > input
level ≥ –55 dBm0
±0.45
†
‡
All typical values are at V
= 5 V, V
= –5 V, and T = 25°C.
A
CC
BB
Absolute rms signal levels are defined as follows: V = 1.2276 V = 0 dBm0 = 4 dBm at f = 1.02 kHz with R = 600 Ω.
I
L
NOTE 3: Full range for the TP3056B is 0°C to 70°C.
6
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TP3056B
MONOLITHIC SERIAL INTERFACE
COMBINED PCM CODEC AND FILTER
SLWS072A – MAY 1998 – REVISED AUGUST 1998
operating characteristics, over operating free-air temperature range, V
= 5 V ±5%,
CC
= –5 V ±5%, GND at 0 V, V = 1.2276 V, f = 1.02 kHz, transmit input amplifier connected for unity
V
BB
I
gain, noninverting, in A-law and µ-law modes, (unless otherwise noted) (continued)
envelope delay distortion with frequency
†
PARAMETER
TEST CONDITIONS
f = 1600 Hz
MIN TYP
MAX
315
220
145
75
UNIT
Transmit delay, absolute (at 0 dBm0)
290
195
120
50
µs
f = 500 Hz to 600 Hz
f = 600 Hz to 800 Hz
f = 800 Hz to 1000 Hz
f = 1000 Hz to 1600 Hz
f = 1600 Hz to 2600 Hz
f = 2600 Hz to 2800 Hz
f = 2800 Hz to 3000 Hz
f = 1600 Hz
‡
Transmit delay, relative to absolute
20
40
µs
55
75
80
105
155
200
130
180
–25
–20
70
Receive delay, absolute (at 0 dBm0)
µs
µs
f = 500 Hz to 1000 Hz
f = 1000 Hz to 1600 Hz
f = 1600 Hz to 2600 Hz
f = 2600 Hz to 2800 Hz
f = 2800 Hz to 3000 Hz
–40
–30
‡
Receive delay, relative to absolute
90
125
175
100
140
†
‡
All typical values are at V
= 5 V, V
= –5 V, and T = 25°C.
A
CC
BB
Absolute rms signal levels are defined as follows: V = 1.2276 V = 0 dBm0 = 4 dBm at f = 1.02 kHz with R = 600 Ω.
I
L
noise
†
PARAMETER
Transmit noise, C-message weighted
TEST CONDITIONS
µ-law VFXI = 0 V
A-law VFXI = 0 V
PCM code equals alternating positive
and negative zero.
A-law PCM code equals positive zero.
MIN TYP
MAX
UNIT
9
14 dBrnC0
–75 dBm0p
Transmit noise, psophometric weighted (see Note 4)
Receive noise, C-message weighted
Receive noise, psophometric weighted
Noise, single frequency
–78
µ-law
2
4
dBrnC0
–86
–83 dBm0p
–53 dBm0
VFXI+ = 0 V,
f = 0 kHz to 100 kHz,
Loop-around measurement
†
All typical values are at V
= 5 V, V
= –5 V, and T = 25°C.
BB A
CC
NOTE 4: Measured by extrapolation from the distortion test result. This parameter is achieved through use of patented circuitry and is not
recommended for applications in which the composite signals on the transmit side are below –55 dBm0.
crosstalk
†
PARAMETER
Crosstalk, transmit to receive
Crosstalk, receive to transmit (see Note 5)
TEST CONDITIONS
MIN TYP
MAX
–75
–75
UNIT
dB
f = 300 Hz to 3000 Hz, DR at steady PCM code
–90
–90
VFXI = 0 V,
f = 300 Hz to 3000 Hz
dB
†
All typical values are at V
= 5 V, V
BB
= –5 V, and T = 25°C.
CC
A
NOTE 5: Receive-to-transmit crosstalk is measured with a – 50 dBm0 activation signal applied at VFXI+.
power amplifiers
PARAMETER
TEST CONDITIONS
MIN
1.65
1.75
2
MAX
UNIT
R
R
R
= 600 Ω
= 1200 Ω
= 30 kΩ
L
L
L
Maximum 0 dBm0 rms level for better than ±0.1 dB linearity
over the range if –10 dBm0 to 3 dBm0
Balanced load,R , connected
L
between VFRO and Gnd
V
rms
Signal/distortion
R
= 600 Ω
50
dB
L
7
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TP3056B
MONOLITHIC SERIAL INTERFACE
COMBINED PCM CODEC AND FILTER
SLWS072A – MAY 1998 – REVISED AUGUST 1998
operating characteristics, over operating free-air temperature range, V
= 5 V ±5%,
CC
V
= –5 V ±5%, GND at 0 V, V = 1.2276 V, f = 1.02 kHz, transmit input amplifier connected for unity
BB
I
gain, noninverting, in A-law and µ-law modes, (unless otherwise noted) (continued)
power supply rejection
PARAMETER
TEST CONDITIONS
f = 0 Hz to 4 kHz
= 5 V + 100 mVrms,
MIN
38
38
40
35
35
40
40
40
40
38
38
40
MAX
UNIT
A-law
dB
V
CC
VFXI+ = –50 dBm0
†
†
†
†
Positive power-supply rejection, transmit
µ-law
dBC
f = 4 kHz to 50 kHz
f = 0 Hz to 4 kHz
f = 4 kHz to 50 kHz
f = 0 Hz to 4 kHz
f = 4 kHz to 50 kHz
f = 0 Hz to 4 kHz
f = 4 kHz to 50 kHz
dB
A-law
dB
V
BB
= –5 V + 100 mVrms,
VFXI+ = –50 dBm0
Negative power-supply rejection, transmit
Positive power-supply rejection, receive
Negative power-supply rejection, receive
µ-law
dBC
dB
A-law
dB
PCM code equals positive zero,
µ-law
dBC
dB
V
CC
= 5 V + 100 mVrms
A-law
dB
PCM code equals positive zero,
= –5 V + 100 mVrms
µ-law
dBC
dB
V
BB
0 dBm0, 300-Hz to 3400-Hz input applied to DR
(measure individual image signals at VFRO)
–30
dB
Spurious out-of-band signals at the
channel output (VFRO)
f = 4600 Hz to 7600 Hz
f = 7600 Hz to 8400 Hz
f = 8400 Hz to 100kHz
–33
–40
–40
dB
†
The unit dBC applies to C-message weighting.
8
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TP3056B
MONOLITHIC SERIAL INTERFACE
COMBINED PCM CODEC AND FILTER
SLWS072A – MAY 1998 – REVISED AUGUST 1998
operating characteristics, over operating free-air temperature range, V
= 5 V ±5%,
CC
= –5 V ±5%, GND at 0 V, V = 1.2276 V, f = 1.02 kHz, transmit input amplifier connected for unity
V
BB
I
gain, noninverting, in A-law and µ-law modes, (unless otherwise noted) (continued)
distortion
PARAMETER
TEST CONDITIONS
Level = 3 dBm0
MIN
33
36
29
30
14
15
MAX
UNIT
Level = 0 dBm0 to -30 dBm0
Transmit
Receive
Transmit
Receive
†
dBC
‡
Level = –40 dBm0
Signal-to-distortion ratio, transmit or receive half-channel
Level = –55 dBm0
Single-frequency distortion products, transmit
Single-frequency distortion products, receive
–46
–46
dB
dB
Loop-around measurement,
Intermodulation distortion
VFXI+ = –4 dBm0 to –21 dBm0,
–41
dB
Two frequencies in the range of 300 Hz to 3400 Hz
Level = –3 dBm0
33
36
Level = –6 dBm0 to –27 dBm0
Level = –34 dBm0
Signal-to-distortion ratio, transmit half-channel (A-law)
(CCITT G.714)
33.5
28.5
13.5
33
dB
§
Level = –40 dBm0
Level = –55 dBm0
Level = –3 dBm0
Level = –6 dBm0 to –27 dBm0
Level = –34 dBm0
36
Signal-to-distortion ratio, receive half-channel (A-law)
(CCITT G.714)
34.2
30
dB
§
Level = –40 dBm0
Level = –55 dBm0
15
†
‡
§
The unit dBC applies to C-message weighting.
Sinusoidal test method (see Note 6)
Pseudo-noise test method
NOTE 6: µ-law measurements are made using a C-message weighted filter, and A-law measurements are made using a psophometric weighted
filter.
9
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TP3056B
MONOLITHIC SERIAL INTERFACE
COMBINED PCM CODEC AND FILTER
SLWS072A – MAY 1998 – REVISED AUGUST 1998
timing requirements over recommended ranges of operating conditions (see Figures 1 and 2)
MIN NOM
2.048
64
MAX
UNIT
MHz
kHz
ns
f
f
t
t
t
t
t
t
Frequency of master clock
MCLK
BCLK
clock(M)
Frequency of bit clock, transmit
2048
clock(B)
Pulse duration, MCLK high
160
w1
w2
r1
Pulse duration, MCLK low
160
ns
Rise time of master clock (20% to 80%)
Fall time of master clock (80% to 20%)
Rise time of bit clock (20% to 80%), transmit
Fall time of bit clock (80% to 20%), transmit
50
50
50
50
ns
MCLK
BCLK
ns
f1
ns
r2
ns
f2
Setup time, BCLK high (and FSX in long-frame sync mode) before MCLK ↓ (first bit clock after
the leading edge of FSX)
t
100
ns
su1
t
t
t
t
t
t
t
Pulse duration, BCLK high, V = 2.2 V
IH
160
160
0
ns
ns
ns
ns
ns
ns
ns
w3
w4
h1
Pulse duration, BCLK low, V = 0.6 V
IL
Hold time, FSX or FSR low after BCLK low (long frame only)
Hold time, BCLK high after FSX or FSR ↑ (short frame only)
Setup time, FSX or FSR high before BCLK ↓ (long frame only)
Setup time, DR valid before BCLK ↓
0
h2
80
50
50
su2
su3
h3
Hold time, DR valid after BCLK ↓
Setup time, FSX or FSR high before BCLK ↓, short-frame sync pulse (1 or 2
bit-clock periods long) (see Note 7)
t
50
ns
ns
su4
h4
Hold time, FSX or FSR high after BCLK ↓, short-frame sync pulse (1 or 2
bit-clock periods long) (see Note 7)
t
100
Hold time, FSX or FSR high after BCLK ↓, long-frame sync pulse (from 3 to 8 bit-clock periods
long)
t
t
100
160
ns
ns
h5
Minimumpulse duration of FSX or FSR (frame syncpulse—lowlevel), 64-kbpsoperatingmode
w5
NOTE 7: For short-frame sync timing, FSR and FSX must go high while their respective bit clocks are high.
switching characteristics over recommended ranges of operating conditions (see Figures 1
and 2)
PARAMETER
TEST CONDITIONS
MIN
MAX
140
UNIT
ns
†
†
t
t
Delay time, BCLK high to data valid at DX
Delay time, BCLK high to TSX low
0
Load = 150 pF plus 2 LSTTL loads
Load = 150 pF plus 2 LSTTL loads
d1
140
ns
d2
Delay time, BCLK (or 8 clock FSX in long frame only) low to
data output (DX) disabled
t
50
20
165
165
ns
ns
d3
d4
Delay time, FSX or BCLK high to data valid at DX (long frame
only)
t
C
= 0 pF to 150 pF
L
†
Nominal input value for an LSTTL load is 18 kΩ.
10
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TP3056B
MONOLITHIC SERIAL INTERFACE
COMBINED PCM CODEC AND FILTER
SLWS072A – MAY 1998 – REVISED AUGUST 1998
PARAMETER MEASUREMENT INFORMATION
t
d2
t
d3
TSX
20%
20%
t
t
r1
w2
t
f
f1
clock(M)
80%
80%
80%
MCLK
BCLK
20%
20%
t
su1
t
w1
80%
80%
80%
20%
20%
1
2
3
4
5
6
7
8
t
h2
t
su4
t
h4
80%
80%
FSX
20%
t
t
d3
d1
80%
1
2
3
4
5
6
7
8
DX
20%
80%
20%
80%
BCLK
20%
20%
1
2
3
4
5
6
7
8
t
h2
t
su4
t
h4
80%
FSR
20%
t
su3
t
h3
7
t
h3
1
2
3
4
5
6
8
DR
Figure 1. Short Frame Sync Timing
11
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TP3056B
MONOLITHIC SERIAL INTERFACE
COMBINED PCM CODEC AND FILTER
SLWS072A – MAY 1998 – REVISED AUGUST 1998
PARAMETER MEASUREMENT INFORMATION
t
w1
t
f
clock(M)
t
r1
t
f1
w2
80%
20%
80%
20%
80%
20%
MCLK
t
r2
t
t
su1
su1
w3
t
t
t
f2
w4
80%
80%
80%
BCLK
FSX
20%
1
2
20%
3
20%
4
5
6
7
8
9
t
f
h1
clock(B)
t
t
h5
su2
80%
80%
20%
t
d4
t
d1
5
t
d4
t
d3
80%
20%
DX
1
2
3
4
6
7
8
t
w3
t
d3
t
w4
80%
20%
80%
80%
20%
BCLK
20%
20%
t
h1
t
su2
t
h5
80%
20%
80%
FSR
DR
t
su3
t
h3
5
t
h3
1
2
3
4
6
7
8
Figure 2. Long Frame Sync Timing
12
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TP3056B
MONOLITHIC SERIAL INTERFACE
COMBINED PCM CODEC AND FILTER
SLWS072A – MAY 1998 – REVISED AUGUST 1998
PRINCIPLES OF OPERATION
system reliability and design considerations
TP3056B system reliability and design considerations are described in the following paragraphs.
latch-up
Latch-up is possible in all CMOS devices. It is caused by the firing of a parasitic SCR that is present due to the
inherent nature of CMOS. When a latch-up occurs, the device draws excessive amounts of current and will
continue to draw heavy current until power is removed. Latch-up can result in permanent damage to the device
if supply current to the device is not limited.
Eventhough the TP3056B is heavily protected against latch-up, it is still possible to cause latch-up under certain
conditions in which excess current is forced into or out of one or more terminals. Latch-up can occur when the
positive supply voltage drops momentarily below ground, when the negative supply voltage rises momentarily
above ground, or possibly if a signal is applied to a terminal after power has been applied but before the ground
is connected. This can happen if the device is hot-inserted into a card with the power applied, or if the device
is mounted on a card that has an edge connector and the card is hot-inserted into a system with the power on.
To help ensure that latch-up does not occur, it is considered good design practice to connect a reverse-biased
Schottky diode with a forward voltage drop of less than or equal to 0.4 V (1N5711 or equivalent) between the
powersupplyandGND(seeFigure3). IfitispossiblethataTP3056B-equippedcardthathasanedgeconnector
could be hot-inserted into a powered-up system, it is also important to ensure that the ground edge connector
traces are longer than the power and signal traces so that the card ground is always the first to make contact.
V
CC
DGND
V
BB
Figure 3. Latch-Up Protection Diode Connection
13
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TP3056B
MONOLITHIC SERIAL INTERFACE
COMBINED PCM CODEC AND FILTER
SLWS072A – MAY 1998 – REVISED AUGUST 1998
PRINCIPLES OF OPERATION
system reliability and design considerations (continued)
device power-up sequence
Latch-up also can occur if a signal source is connected without the device being properly grounded. A signal
applied to one terminal could then find a ground through another signal terminal on the device. To ensure proper
operation of the device and as a safeguard against this sort of latch-up, it is recommended that the following
power-up sequence always be used:
1. Ensure that no signals are applied to the device before the power-up sequence is complete.
2. Connect GND.
3. Apply V (most negative voltage).
BB
4. Apply V
(most positive voltage).
CC
5. Force a power down condition in the device.
6. Connect clocks.
7. Release the power down condition.
8. Apply FS synchronization pulses.
9. Apply the signal inputs.
When powering down the device, this procedure should be followed in the reverse order.
internal sequencing
Power-on reset circuitry initializes the TP3056B device when power is first applied, placing it in the power-down
mode. The DX and VFRO outputs go into the high-impedance state and all nonessential circuitry is disabled.
A low level applied to the PDN terminal powers up the device and activates all internal circuits. The 3-state PCM
data output, DX, remains in the high-impedance state until the arrival of the second FSX pulse.
general operation
A 2.048-MHz clock signal applied to MCLK serves as the master clock for both the receive and the transmit
directions. BCLK must have a bit clock signal applied to it, which then serves as the bit clock for both the receive
and the transmit directions. BCLK can be in the range from 64 kHz to 2.048 MHz, but must be synchronous with
MCLK.
The encoding cycle begins with each FSX pulse, and the PCM data from the previous cycle is shifted out of the
enabled DX output on the rising edge of BCLK. After eight bit-clock periods, the 3-state DX output is returned
to the high-impedance state. With an FSR pulse, PCM data is latched in via DR on the falling edge of BCLK.
FSX and FSR must be synchronous with MCLK.
14
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TP3056B
MONOLITHIC SERIAL INTERFACE
COMBINED PCM CODEC AND FILTER
SLWS072A – MAY 1998 – REVISED AUGUST 1998
PRINCIPLES OF OPERATION
short-frame sync operation
Thedevicecanoperatewitheitherashort-framesyncpulseoralong-framesyncpulse. Onpowerup, thedevice
automatically goes into the short-frame mode where both FSX and FSR must be one bit-clock period long with
timing relationships specified in Figure 1. With FSX high during a falling edge of BCLK, the next rising edge of
BCLK enables the 3-state output buffer, outputting the sign bit at DX. The remaining seven bits are shifted out
on the following seven rising edges, with the next falling edge disabling DX. With FSR high during a falling edge
ofBCLK, thenextfallingedgeofBCLKlatchesinthesignbit. Thefollowingsevenfallingedgeslatchintheseven
remaining bits.
long-frame sync operation
Both FSX and FSR must be three or more bit-clock periods long to use the long-frame sync mode with timing
relationshipsas shown in Figure 2. Using the transmit frame sync (FSX), the device determines whether a short-
or long-frame sync pulse is being used. For 64-kHz operation, the frame-sync pulse must be kept low for a
minimum of 160 ns. The rising edge of FSX or BCLK, whichever occurs later, enables the 3-state output buffer,
outputting the sign bit at DX. The next seven rising edges of BCLK shift out the remaining seven bits. The falling
edge of BCLK following the eighth rising edge, or FSX going low, whichever occurs later, disables DX. A
rising edge on FSR, the receive-frame sync pulse, causes the PCM data at DR to be latched in on the next eight
falling edges of BCLK.
transmit section
The transmit section consists of an input amplifier, filters, and an encoding ADC. The input is an operational
amplifier with provision for gain adjustment using two external resistors. The low-noise and wide-bandwidth
characteristics of these devices provide gains in excess of 20 dB across the audio passband. The operational
amplifier drives a unity-gain filter consisting of an RC active prefilter followed by an eighth-order
switched-capacitor band-pass filter clocked at 256 kHz. The output of this filter is routed to the encoder
sample-and-hold circuit. The ADC is a compressing type and converts the analog signal to PCM data in
accordance with µ-law or A-law coding conventions, as selected. A precision voltage reference provides a
nominal input overload voltage of 2.5 V peak.
The sampling of the filter output is controlled by the FSX frame-sync pulse; then the successive-approximation
encoding cycle begins. The resulting 8-bit code is loaded into a buffer and shifted out through DX at the next
FSX pulse. The total encoding delay is approximately 290 µs. Any offset voltage due to the filters or comparator
is cancelled by sign-bit integration.
receive section
The receive section is unity gain and consists of an expanding DAC, filters, and a power amplifier. Decoding
is µ-law or A-law (as selected by the ASEL terminal), and the decoded analog output signal is routed to the input
of a fifth-order switched-capacitor low-pass filter. This filter is clocked at 256 kHz and corrects for the (sin x)/x
attenuation caused by the 8-kHz sample/hold of the DAC. Next is a second-order RC active post-filter/power
amplifier capable of driving an external 600-Ω load.
When FSR goes high, the data at DR is stepped in on the falling edge of the next eight BCLK clocks. At the
end of the decoder time slot, the decoding cycle begins and 10 µs later, the decoder DAC output is updated.
The decoder delay is about 10 µs (decoder update) plus 110 µs (filter delay) plus 62.5 µs (1/2 frame), or a total
of approximately 180 µs.
15
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TP3056B
MONOLITHIC SERIAL INTERFACE
COMBINED PCM CODEC AND FILTER
SLWS072A – MAY 1998 – REVISED AUGUST 1998
APPLICATION INFORMATION
power supplies
While the terminals of the TP3056B device is well protected against electrical misuse, it is recommended that
the standard CMOS practice be followed, ensuring that ground is connected to the device before any other
connections are made. In applications where the printed-circuit board can be plugged into a hot socket with
power and clocks already present, an extra long ground pin in the connector should be used.
All ground connections to each device should meet at a common point as close as possible to the device
ANLG GND terminal. This minimizes the interaction of ground return currents flowing through a common bus
impedance. V
and V supplies should be decoupled by connecting 0.1-µF decoupling capacitors to this
CC
BB
common point. These bypass capacitors must be connected as close as possible to the device V
terminals.
and V
BB
CC
For best performance, the ground point of each codec/filter on a card should be connected to a common card
ground in star formation rather than via a ground bus. This common ground point should be decoupled to V
CC
and V with 10-µF capacitors.
BB
Figure 4 shows a typical TP3056B application.
16
15
1
From SLIC
(Analog In)
–5 V
V
VFXI+
VFXI–
BB
0.1 µF
2
ANLG GND
R1
R2
14
GSX
0.1 µF
5 V
To SLIC
4
3
V
CC
Analog Interface
TP3056B
VFRO
FSR
(Analog Out)
5
12
11
13
FSX
DX
Digital
Interface
Data Out
6
7
8
Data In
5 V, GND, or –5 V
PDN
DR
TSX
10
9
ASEL
BCLK
MCLK
PDN
(2.048 MHz)
R1
R2
NOTE A: Transmit gain = 20 log
(
)
R2
,
R1
10 k
R2
Figure 4. Typical Synchronous Application
16
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TP3056B
MONOLITHIC SERIAL INTERFACE
COMBINED PCM CODEC AND FILTER
SLWS072A – MAY 1998 – REVISED AUGUST 1998
MECHANICAL DATA
DW (R-PDSO-G**)
PLASTIC SMALL-OUTLINE PACKAGE
16 PIN SHOWN
PINS **
0.050 (1,27)
16
20
24
28
DIM
0.020 (0,51)
0.014 (0,35)
0.010 (0,25)
M
0.410
0.510
0.610
0.710
A MAX
(10,41) (12,95) (15,49) (18,03)
16
9
0.400
0.500
0.600
0.700
A MIN
(10,16) (12,70) (15,24) (17,78)
0.419 (10,65)
0.400 (10,15)
0.010 (0,25) NOM
0.299 (7,59)
0.293 (7,45)
Gage Plane
0.010 (0,25)
1
8
0°–8°
0.050 (1,27)
0.016 (0,40)
A
Seating Plane
0.004 (0,10)
0.012 (0,30)
0.004 (0,10)
0.104 (2,65) MAX
4040000/B 03/95
NOTES: A. All linear dimensions are in inches (millimeters).
B. This drawing is subject to change without notice.
C. Body dimensions do not include mold flash or protrusion not to exceed 0.006 (0,15).
D. Falls within JEDEC MS-013
17
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TP3056B
MONOLITHIC SERIAL INTERFACE
COMBINED PCM CODEC AND FILTER
SLWS072A – MAY 1998 – REVISED AUGUST 1998
MECHANICAL DATA
N (R-PDIP-T**)
PLASTIC DUAL-IN-LINE PACKAGE
16 PIN SHOWN
PINS **
14
16
18
20
DIM
0.775
(19,69)
0.775
(19,69)
0.920
(23.37)
0.975
(24,77)
A MAX
A
16
9
0.745
(18,92)
0.745
(18,92)
0.850
(21.59)
0.940
(23,88)
A MIN
0.260 (6,60)
0.240 (6,10)
1
8
0.070 (1,78) MAX
0.020 (0,51) MIN
0.310 (7,87)
0.290 (7,37)
0.035 (0,89) MAX
0.200 (5,08) MAX
Seating Plane
0.125 (3,18) MIN
0.100 (2,54)
0°–15°
0.021 (0,53)
0.015 (0,38)
0.010 (0,25)
M
0.010 (0,25) NOM
14/18 PIN ONLY
4040049/C 08/95
NOTES: A. All linear dimensions are in inches (millimeters).
B. This drawing is subject to change without notice.
C. Falls within JEDEC MS-001 (20 pin package is shorter then MS-001.)
18
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
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Copyright 1998, Texas Instruments Incorporated
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