TP3057 [TI]
Enhanced Serial Interface CODEC/Filter COMBO Family; 增强型串行接口编解码器/滤波器COMBO系列
| 型号： | TP3057 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | Enhanced Serial Interface CODEC/Filter COMBO Family |
| 文件： | 总18页 (文件大小：299K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
TP3054. TP3057
Enhanced Serial Interface CODEC/Filter COMBO Family
Literature Number: SNAS569
August 1994
TP3054, TP3057
‘‘Enhanced’’ Serial Interface
CODEC/Filter COMBO Family
É
General Description
Features
Y
Complete CODEC and filtering system (COMBO)
including:
The TP3054, TP3057 family consists of m-law and A-law
monolithic PCM CODEC/filters utilizing the A/D and D/A
conversion architecture shown inFigure 1, and a serial PCM
interface. The devices are fabricated using National’s ad-
vanced double-poly CMOS process (microCMOS).
Ð Transmit high-pass and low-pass filtering
Ð Receive low-pass filter with sin x/x correction
Ð Active RC noise filters
Ð m-law or A-law compatible COder and DECoder
Ð Internal precision voltage reference
Ð Serial I/O interface
The encode portion of each device consists of an input gain
adjust amplifier, an active RC pre-filter which eliminates very
high frequency noise prior to entering a switched-capacitor
band-pass filter that rejects signals below 200 Hz and above
3400 Hz. Also included are auto-zero circuitry and a com-
panding coder which samples the filtered signal and en-
codes it in the companded m-law or A-law PCM format. The
decode portion of each device consists of an expanding
decoder, which reconstructs the analog signal from the
companded m-law or A-law code, a low-pass filter which
corrects for the sin x/x response of the decoder output and
rejects signals above 3400 Hz followed by a single-ended
power amplifier capable of driving low impedance loads.
The devices require two 1.536 MHz, 1.544 MHz or 2.048
MHz transmit and receive master clocks, which may be
asynchronous; transmit and receive bit clocks, which may
vary from 64 kHz to 2.048 MHz; and transmit and receive
frame sync pulses. The timing of the frame sync pulses and
PCM data is compatible with both industry standard formats.
Ð Internal auto-zero circuitry
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
m-law, 16-pinÐTP3054
A-law, 16-pinÐTP3057
Designed for D3/D4 and CCITT applications
g
5V operation
Low operating powerÐtypically 50 mW
Power-down standby modeÐtypically 3 mW
Automatic power-down
TTL or CMOS compatible digital interfaces
Maximizes line interface card circuit density
Dual-In-Line or surface mount packages
See also AN-370, ‘‘Techniques for Designing with
CODEC/Filter COMBO Circuits’’
Connection Diagrams
Dual-In-Line Package
Plastic Chip Carriers
TL/H/5510–1
Top View
TL/H/5510–10
Order Number TP3054J or TP3057J
See NS Package Number J16A
Top View
Order Number TP3057V
See NS Package Number V20A
Order Number TP3054N or TP3057N
See NS Package Number N16A
Order Number TP3054WM or TP3057WM
See NS Package Number M16B
COMBOÉ and TRI-STATEÉ are registered trademarks of National Semiconductor Corporation.
C
1995 National Semiconductor Corporation
TL/H/5510
RRD-B30M125/Printed in U. S. A.
Block Diagram
FIGURE 1
TL/H/5510–2
Pin Description
Symbol
Function
Negative power supply pin.
e b
Symbol
Function
should be synchronous with MCLK for best per-
V
BB
X
g
V
BB
5V 5%.
formance. When MCLK is connected continu-
R
ously low, MCLK is selected for all internal tim-
X
GNDA
Analog ground. All signals are referenced
to this pin.
ing. When MCLK is connected continuously
R
high, the device is powered down.
VF
O
Analog output of the receive power ampli-
fier.
R
MCLK
Transmit master clock. Must be 1.536 MHz,
1.544 MHz or 2.048 MHz. May be asynchronous
X
V
CC
Positive power supply pin.
with MCLK . Best performance is realized from
R
synchronous operation.
e a
g
V
5V 5%.
Receive frame sync pulse which enables
BCLK to shift PCM data into D . FS is
CC
FS
R
FS
Transmit frame sync pulse input which enables
BCLK to shift out the PCM data on D . FS is
X
R
R
R
X
X
X
an 8 kHz pulse train. See Figures 2 and 3
for timing details.
an 8 kHz pulse train, see Figures 2 and 3 for
timing details.
D
Receive data input. PCM data is shifted
into D following the FS leading edge.
R
BCLK
The bit clock which shifts out the PCM data on
D . May vary from 64 kHz to 2.048 MHz, but
X
R
R
X
BCLK /CLKSEL The bit clock which shifts data into D af-
R
R
must be synchronous with MCLK .
X
ter the FS leading edge. May vary from
R
64 kHz to 2.048 MHz. Alternatively, may
D
X
The TRI-STATE PCM data output which is en-
É
abled by FS .
X
be a logic input which selects either
1.536 MHz/1.544 MHz or 2.048 MHz for
master clock in synchronous mode and
TS
Open drain output which pulses low during the
encoder time slot.
X
BCLK is used for both transmit and re-
X
ceive directions (see Table I).
GS
X
Analog output of the transmit input amplifier.
Used to externally set gain.
MCLK /PDN
R
Receive master clock. Must be
1.536 MHz, 1.544 MHz or 2.048 MHz.
May be asynchronous with MCLK , but
VF Ib
X
Inverting input of the transmit input amplifier.
VF Ia
Non-inverting input of the transmit input amplifi-
er.
X
X
2
Functional Description
POWER-UP
ASYNCHRONOUS OPERATION
When power is first applied, power-on reset circuitry initializ-
es the COMBO and places it into a power-down state. All
For asynchronous operation, separate transmit and receive
clocks may be applied. MCLK and MCLK must be
X
R
non-essential circuits are deactivated and the D and VF
X
O
R
2.048 MHz for the TP3057, or 1.536 MHz, 1.544 MHz for the
TP3054, and need not be synchronous. For best transmis-
sion performance, however, MCLK should be synchronous
outputs are put in high impedance states. To power-up the
device, a logical low level or clock must be applied to the
MCLK /PDN pin and FS and/or FS pulses must be pres-
R
with MCLK , which is easily achieved by applying only static
X
R
X
R
ent. Thus, 2 power-down control modes are available. The
first is to pull the MCLK /PDN pin high; the alternative is to
hold both FS and FS inputs continuously lowÐthe device
logic levels to the MCLK /PDN pin. This will automatically
R
connect MCLK to all internal MCLK functions (see Pin
R
X
R
Description). For 1.544 MHz operation, the device automati-
cally compensates for the 193rd clock pulse each frame.
X
R
will power-down approximately 1 ms after the last FS or
X
FS pulse. Power-up will occur on the first FS or FS
FS starts each encoding cycle and must be synchronous
X
with MCLK and BCLK . FS starts each decoding cycle
X X R
R
X
R
pulse. The TRI-STATE PCM data output, D , will remain in
X
the high impedance state until the second FS pulse.
X
and must be synchronous with BCLK . BCLK must be a
R R
clock, the logic levels shown in Table 1 are not valid in
asynchronous mode. BCLK and BCLK may operate from
64 kHz to 2.048 MHz.
SYNCHRONOUS OPERATION
X
R
For synchronous operation, the same master clock and bit
clock should be used for both the transmit and receive di-
rections. In this mode, a clock must be applied to MCLK
SHORT FRAME SYNC OPERATION
X
and the MCLK /PDN pin can be used as a power-down
R
control. A low level on MCLK /PDN powers up the device
R
and a high level powers down the device. In either case,
The COMBO can utilize either a short frame sync pulse or a
long frame sync pulse. Upon power initialization, the device
assumes a short frame mode. In this mode, both frame sync
MCLK will be selected as the master clock for both the
X
transmit and receive circuits. A bit clock must also be ap-
pulses, FS and FS , must be one bit clock period long,
X R
with timing relationships specified in Figure 2. With FS high
X
plied to BCLK and the BCLK /CLKSEL can be used to
R
during a falling edge of BCLK , the next rising edge of
X
X
select the proper internal divider for a master clock of 1.536
MHz, 1.544 MHz or 2.048 MHz. For 1.544 MHz operation,
the device automatically compensates for the 193rd clock
pulse each frame.
BCLK enables the D TRI-STATE output buffer, which will
X X
output the sign bit. The following seven rising edges clock
out the remaining seven bits, and the next falling edge dis-
ables the D output. With FS high during a falling edge of
X
R
BCLK (BCLK in synchronous mode), the next falling edge
X
of BCLK latches in the sign bit. The following seven falling
R
edges latch in the seven remaining bits. All four devices
may utilize the short frame sync pulse in synchronous or
asynchronous operating mode.
R
With a fixed level on the BCLK /CLKSEL pin, BCLK will be
X
selected as the bit clock for both the transmit and receive
directions. Table 1 indicates the frequencies of operation
R
which can be selected, depending on the state of BCLK
/
R
CLKSEL. In this synchronous mode, the bit clock, BCLK ,
X
may be from 64 kHz to 2.048 MHz, but must be synchro-
LONG FRAME SYNC OPERATION
nous with MCLK .
X
To use the long frame mode, both the frame sync pulses,
FS and FS , must be three or more bit clock periods long,
Each FS pulse begins the encoding cycle and the PCM
X
data from the previous encode cycle is shifted out of the
X
R
with timing relationships specified in Figure 3. Based on the
enabled D output on the positive edge of BCLK . After 8
X
X
bit clock periods, the TRI-STATE D output is returned to a
transmit frame sync, FS , the COMBO will sense whether
X
X
high impedance state. With an FS pulse, PCM data is
short or long frame sync pulses are being used. For 64 kHz
operation, the frame sync pulse must be kept low for a mini-
mum of 160 ns. The D TRI-STATE output buffer is enabled
R
latched via the D input on the negative edge of BCLK (or
R
X
BCLK if running). FS and FS must be synchronous with
X
R
X
R
with the rising edge of FS or the rising edge of BCLK ,
X
X
MCLK
.
X/R
whichever comes later, and the first bit clocked out is the
sign bit. The following seven BCLK rising edges clock out
the remaining seven bits. The D output is disabled by the
X
TABLE I. Selection of Master Clock Frequencies
Master Clock
X
falling BCLK edge following the eighth rising edge, or by
X
FS going low, whichever comes later. A rising edge on the
X
receive frame sync pulse, FS , will cause the PCM data at
Frequency Selected
BCLK /CLKSEL
R
R
TP3057
TP3054
D
to be latched in on the next eight falling edges of BCLK
R
R
(BCLK in synchronous mode). All four devices may utilize
X
the long frame sync pulse in synchronous or asynchronous
mode.
Clocked
2.048 MHz
1.536 MHz or
1.544 MHz
2.048 MHz
0
1
1.536 MHz or
1.544 MHz
2.048 MHz
In applications where the LSB bit is used for signalling with
FS two bit clock periods long, the decoder will interpret the
R
lost LSB as ‘‘(/2’’ to minimize noise and distortion.
1.536 MHz or
1.544 MHz
3
Functional Description (Continued)
TRANSMIT SECTION
(due to encoding delay), which totals 290 ms. Any offset
voltage due to the filters or comparator is cancelled by sign
bit integration.
The transmit section input is an operational amplifier with
provision for gain adjustment using two external resistors,
see Figure 4. The low noise and wide bandwidth allow gains
in excess of 20 dB across the audio passband to be real-
ized. The op amp drives a unity-gain filter consisting of RC
active pre-filter, followed by an eighth order switched-ca-
pacitor bandpass filter clocked at 256 kHz. The output of
this filter directly drives the encoder sample-and-hold circuit.
The A/D is of companding type according to m-law
(TP3054) or A-law (TP3057) coding conventions. A preci-
sion voltage reference is trimmed in manufacturing to pro-
RECEIVE SECTION
The receive section consists of an expanding DAC which
a fifth order switched-capacitor low pass filter
drives
clocked at 256 kHz. The decoder is A-law (TP3057) or
m-law (TP3054) and the 5th order low pass filter corrects for
the sin x/x attenuation due to the 8 kHz sample/hold. The
filter is then followed by a 2nd order RC active post-filter/
power amplifer capable of driving a 600X load to a level of
7.2 dBm. The receive section is unity-gain. Upon the occur-
vide an input overload (t
) of nominally 2.5V peak (see
MAX
rence of FS , the data at the D input is clocked in on the
R
R
falling edge of the next eight BCLK (BCLK ) periods. At
table of Transmission Characteristics). The FS frame sync
X
R
X
the end of the decoder time slot, the decoding cycle begins,
pulse controls the sampling of the filter output, and then the
successive-approximation encoding cycle begins. The 8-bit
code is then loaded into a buffer and shifted out through D
and 10 ms later the decoder DAC output is updated. The
X
E
total decoder delay is
10 ms (decoder update) plus
at the next FS pulse. The total encoding delay will be ap-
X
proximately 165 ms (due to the transmit filter) plus 125 ms
110 ms (filter delay) plus 62.5 ms ((/2 frame), which gives
approximately 180 ms.
4
Absolute Maximum Ratings
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales
Office/Distributors for availability and specifications.
Voltage at any Digital Input or
Output
a
b
0.3V to GNDA 0.3V
V
CC
b
a
125 C
Operating Temperature Range
Storage Temperature Range
25 C to
§
§
§
V
V
to GNDA
to GNDA
7V
7V
b
a
65 C to 150 C
CC
§
b
BB
Lead Temperature (Soldering, 10 seconds)
ESD (Human Body Model)
300 C
§
2000V
Voltage at any Analog Input
or Output
a
b
0.3V
V
CC
0.3V to V
BB
e
Latch-Up Immunity
100 mA on any Pin
Electrical Characteristics Unless otherwise noted, limits printed in BOLD characters are guaranteed for V
CC
25 C. All other limits
e
e b
e
are assured by correlation with other production tests and/or product design and characterization. All signals referenced to
e
A
g
5.0V 5%, V
g
5.0V 5%; T
0 C to 70 C by correlation with 100% electrical testing at T
§
§
§
BB
A
e
e b
e
5.0V, T 25 C.
A
GNDA. Typicals specified at V
5.0V, V
§
CC
BB
Symbol
Parameter
Conditions
Min
Typ
Max
Units
DIGITAL INTERFACE
V
V
V
Input Low Voltage
0.6
V
V
IL
Input High Voltage
Output Low Voltage
2.2
IH
OL
e
L
D , I
X
SIG , I
3.2 mA
e
0.4
0.4
0.4
V
V
V
1.0 mA
3.2 mA, Open Drain
R
TS , I
L
e
X
L
eb
D , I
X H
SIG , I
R
V
OH
Output High Voltage
3.2 mA
eb
H
2.4
2.4
V
V
1.0 mA
s
s
V
IL
b
I
I
I
Input Low Current
Input High Current
GNDA
V
, All Digital Inputs
10
10
10
10
10
10
mA
mA
mA
IL
IN
s
s
V
CC
b
b
V
IH
V
IN
IH
s
s
V
CC
Output Current in High Impedance
State (TRI-STATE)
D , GNDA
X
V
O
OZ
ANALOG INTERFACE WITH TRANSMIT INPUT AMPLIFIER (ALL DEVICES)
a
s
s
s
s
b
b
a
a
b
200
I XA
I
Input Leakage Current
Input Resistance
2.5V
2.5V
V
V
2.5V, VF I or VF Ib
200
nA
MX
X
X
X
a
R XA
I
2.5V, VF I or VF Ib
10
X
X
R XA
O
Output Resistance
Closed Loop, Unity Gain
1
2
3
R XA
L
Load Resistance
GS
GS
10
kX
pF
X
C XA
L
Load Capacitance
50
X
t
L
b
V XA
O
Output Dynamic Range
Voltage Gain
GS , R 10 kX
2.8
2.8
V
X
A XA
V
VF Ia to GS
X
5000
V/V
MHz
mV
V
X
F XA
U
Unity Gain Bandwidth
Offset Voltage
1
b
b
V
XA
20
20
OS
CM
l
CMRRXA 60 dB
V
XA
Common-Mode Voltage
Common-Mode Rejection Ratio
Power Supply Rejection Ratio
2.5
2.5
CMRRXA
PSRRXA
DC Test
60
dB
dB
DC Test
60
ANALOG INTERFACE WITH RECEIVE FILTER (ALL DEVICES)
R
RF
Output Resistance
Load Resistance
Pin VF
O
1
3
X
X
O
R
e
VF O
R
g
R RF
L
2.5V
600
C RF
L
Load Capacitance
Output DC Offset Voltage
500
pF
mV
b
VOS
O
200
200
R
POWER DISSIPATION (ALL DEVICES)
I
I
I
I
0
Power-Down Current
Power-Down Current
Power-Up Active Current
Power-Up Active Current
No Load (Note)
No Load (Note)
No Load
0.5
0.05
5.0
1.5
0.3
9.0
9.0
mA
mA
mA
mA
CC
0
BB
1
CC
1
No Load
5.0
BB
Note: I
and I
are measured after first achieving a power-up state.
BB0
CC0
5
e
Timing Specifications Unless otherwise noted, limits printed in BOLD characters are guaranteed for V
CC
e
0 C to 70 C by correlation with 100% electrical testing at T 25 C. All other limits are
A
e b
e
g
g
5.0V 5%, V
5.0V 5%; T
§
§
§
BB
A
assured by correlation with other production tests and/or product design and characterization. All signals referenced to GNDA.
e
e
e b
e
0.7V. See Definitions and Timing Conventions section for test methods information.
e
Typicals specified at V
CC
5.0V, V
BB
5.0V, T
25 C. All timing parameters are measured at V
2.0V and V
§
A
OH
OL
Symbol
1/t
Parameter
Conditions
Min
Typ
Max
Units
Frequency of Master Clocks
Depends on the Device Used and the
1.536
1.544
MHz
MHz
MHz
PM
BCLK /CLKSEL Pin.
R
MCLK and MCLK
X
2.048
R
R
R
t
t
t
t
t
t
t
t
Rise Time of Master Clock
Fall Time of Master Clock
Period of Bit Clock
MCLK and MCLK
X
50
50
ns
ns
ns
ns
ns
ns
ns
ns
RM
MCLK and MCLK
X
FM
485
488
15725
50
PB
Rise Time of Bit Clock
Fall Time of Bit Clock
BCLK and BCLK
X R
RB
BCLK and BCLK
R
50
FB
X
Width of Master Clock High
Width of Master Clock Low
MCLK and MCLK
X
160
160
100
WMH
WML
SBFM
R
R
MCLK and MCLK
X
Set-Up Time from BCLK High
X
First Bit Clock after the Leading
Edge of FS
to MCLK Falling Edge
X
X
t
Set-Up Time from FS High
X
Long Frame Only
100
ns
SFFM
to MCLK Falling Edge
X
e
IH
t
t
t
Width of Bit Clock High
Width of Bit Clock Low
V
2.2V
160
160
0
ns
ns
ns
WBH
WBL
HBFL
e
V
IL
0.6V
Holding Time from Bit Clock
Low to Frame Sync
Long Frame Only
Short Frame Only
Long Frame Only
t
t
t
Holding Time from Bit Clock
High to Frame Sync
0
80
0
ns
ns
ns
HBFS
SFB
Set-Up Time from Frame Sync
to Bit Clock Low
e
Load 150 pF plus 2 LSTTL Loads
Delay Time from BCLK High
X
to Data Valid
140
DBD
e
Load 150 pF plus 2 LSTTL Loads
t
t
Delay Time to TS Low
X
140
165
ns
ns
DBTS
e
Delay Time from BCLK Low to
X
Data Output Disabled
C
L
0 pF to 150 pF
50
20
DZC
e
t
Delay Time to Valid Data from
C
L
0 pF to 150 pF
165
ns
DZF
FS or BCLK , Whichever
X X
Comes Later
t
t
t
t
t
Set-Up Time from D Valid to
R
50
50
ns
ns
ns
ns
ns
SDB
HBD
SF
BCLK
R/X
Low
Hold Time from BCLK
R/X
Low to
D
R
Invalid
Set-Up Time from FS
X/R
to
Short Frame Sync Pulse (1 Bit Clock
Period Long)
50
BCLK Low
X/R
Hold Time from BCLK
X/R
Low
Short Frame Sync Pulse (1 Bit Clock
Period Long)
100
100
HF
to FS
X/R
Low
Hold Time from 3rd Period of
Bit Clock Low to Frame Sync
Long Frame Sync Pulse (from 3 to 8 Bit
Clock Periods Long)
HBFl
(FS or FS
X
)
R
t
Minimum Width of the Frame
Sync Pulse (Low Level)
64k Bit/s Operating Mode
160
ns
WFL
6
Timing Diagrams
7
Timing Diagrams (Continued)
8
Transmission Characteristics Unless otherwise noted, limits printed in BOLD characters are guaranteed for
e
e b
e
limits are assured by correlation with other production tests and/or product design and characterization. GNDA
e
0 C to 70 C by correlation with 100% electrical testing at T 25 C. All other
g
5.0V 5%, V
g
5.0V 5%; T
V
§
§
§
CC
BB
A
A
e
e
0V, f
e
5.0V, V
e
e
1.02 kHz, V
IN
0 dBm0, transmit input amplifier connected for unity gain non-inverting. Typicals specified at V
25 C.
CC
BB
e b
5.0V, T
§
A
Symbol
Parameter
Conditions
Min
Typ
Max
Units
AMPLITUDE RESPONSE
Absolute Levels
Nominal 0 dBm0 Level is 4 dBm
(Definition of Nominal Gain)
(600X)
0 dBm0
1.2276
Vrms
t
Virtual Decision Valve Defined
Per CCITT Rec. G711
Max Overload Level
TP3054 (3.17 dBm0)
TP3057 (3.14 dBm0)
MAX
2.501
2.492
V
V
PK
PK
e
e
25 C, V
CC
eb
5V, V
BB
G
G
Transmit Gain, Absolute
T
5V
§
XA
XR
A
e
Input at GS
0 dBm0 at 1020 Hz
X
b
TP3054/57
0.15
0.15
dB
e
e
e
e
e
e
e
e
e
b
b
Transmit Gain, Relative to G
XA
f
f
f
f
f
f
f
f
f
16 Hz
50 Hz
60 Hz
200 Hz
b
300 Hz 3000 Hz
3300 Hz
40
30
dB
dB
dB
dB
dB
dB
dB
dB
dB
b
26
0.1
b
b
1.8
b
b
0.15
0.35
0.15
0.05
0
b
3400 Hz
0.7
b
b
4000 Hz
14
32
4600 Hz and Up, Measure
Response from 0 Hz to 4000 Hz
b
G
G
G
Absolute Transmit Gain Variation
with Temperature
Relative to G
Relative to G
0.1
0.1
dB
dB
XAT
XAV
XRL
XA
b
Absolute Transmit Gain Variation
with Supply Voltage
0.05
0.05
XA
Transmit Gain Variations with
Level
Sinusoidal Test Method
eb
40 dBm0 to 3 dBm0
Reference Level
10 dBm0
a
b
VF Ia
0.2
0.4
1.2
0.2
0.4
1.2
dB
dB
dB
eb
eb
eb
b
b
b
X
VF Ia
X
50 dBm0 to 40 dBm0
b
55 dBm0 to 50 dBm0
VF Ia
X
e
e
eb
5V, V 5V
BB
G
G
Receive Gain, Absolute
T
25 C, V
e
§
RA
RR
A
CC
Input Digital Code Sequence for
0 dBm0 Signal at 1020 Hz
TP3054/57
b
0.15
0.15
dB
e
e
e
e
b
b
b
Receive Gain, Relative to G
RA
f
f
f
f
0 Hz to 3000 Hz
3300 Hz
0.15
0.35
0.15
0.05
0
dB
dB
dB
dB
3400 Hz
0.7
b
4000 Hz
14
b
G
G
G
Absolute Receive Gain Variation
with Temperature
Relative to G
Relative to G
0.1
0.1
dB
RAT
RAV
RRL
RA
b
Absolute Receive Gain Variation
with Supply Voltage
0.05
0.05
dB
RA
Receive Gain Variations with
Level
Sinusoidal Test Method; Reference
Input PCM Code Corresponds to an
Ideally Encoded PCM Level
eb
eb
eb
a
b
b
b
40 dBm0 to 3 dBm0
0.2
0.4
1.2
0.2
0.4
1.2
dB
dB
dB
b
50 dBm0 to 40 dBm0
b
55 dBm0 to 50 dBm0
e
R
L
b
2.5
V
RO
Receive Output Drive Level
600X
2.5
V
9
Transmission Characteristics (Continued) Unless otherwise noted, limits printed in BOLD characters are
e
e b
e
e
0 C to 70 C by correlation with 100% electrical testing at T
A
g
g
guaranteed for V
CC
5.0V 5%, V
5.0V 5%; T
§
§
BB
A
25 C. All other limits are assured by correlation with other production tests and/or product design and characterization. GNDA
§
e
0V, f
5.0V, V
e
e
e
e
1.02 kHz, V
IN
0 dBm0, transmit input amplifier connected for unity gain non-inverting. Typicals specified at V
25 C.
CC
e b
5.0V, T
§
BB
A
Symbol
Parameter
Conditions
Min
Typ
Max
Units
ENVELOPE DELAY DISTORTION WITH FREQUENCY
e
D
D
Transmit Delay, Absolute
f
1600 Hz
290
315
ms
XA
XR
e
e
e
e
e
e
e
Transmit Delay, Relative to D
f
f
f
f
f
f
f
500 Hz–600 Hz
195
120
50
220
145
75
ms
ms
ms
ms
ms
ms
ms
XA
600 Hz–800 Hz
800 Hz–1000 Hz
1000 Hz–1600 Hz
1600 Hz–2600 Hz
2600 Hz–2800 Hz
2800 Hz–3000 Hz
20
40
55
75
80
105
155
130
e
D
D
Receive Delay, Absolute
f
1600 Hz
180
200
ms
RA
RR
e
e
e
e
e
b
b
b
b
Receive Delay, Relative to D
f
f
f
f
f
500 Hz–1000 Hz
1000 Hz–1600 Hz
1600 Hz–2600 Hz
2600 Hz–2800 Hz
2800 Hz–3000 Hz
40
30
25
20
ms
ms
ms
ms
ms
RA
70
90
100
145
125
175
NOISE
N
XC
N
XP
N
RC
N
RP
N
RS
Transmit Noise, C Message
Weighted
TP3054
TP3057
12
15
dBrnC0
dBm0p
b
b
Transmit Noise, P Message
Weighted
74
82
67
Receive Noise, C Message
Weighted
PCM Code is Alternating Positive
and Negative Zero Ð TP3054
8
11
dBrnC0
Receive Noise, P Message
Weighted
PCM Code Equals Positive
Zero Ð TP3057
b
b
79
dBm0p
dBm0
e
b
53
Noise, Single Frequency
f
0 kHz to 100 kHz, Loop Around
e
Measurement, VF Ia 0 Vrms
X
e b
50 dBm0
PPSR
Positive Power Supply Rejection,
Transmit
VF Ia
X
X
e
a
0 kHz–50 kHz (Note 2)
V
5.0 V
100 mVrms
CC
DC
e
f
40
dBC
dBC
VF Ia
e b
50 dBm0
NPSR
Negative Power Supply Rejection,
Transmit
X
X
eb
a
100 mVrms
V
5.0 V
BB
DC
e
f
0 kHz–50 kHz (Note 2)
40
PPSR
Positive Power Supply Rejection,
Receive
PCM Code Equals Positive Zero
a
100 mVrms
R
e
V
5.0 V
DC
CC
Measure VF
0
R
e
e
e
f
f
f
0 Hz–4000 Hz
4 kHz–25 kHz
25 kHz–50 kHz
40
40
36
dBC
dB
dB
NPSR
Negative Power Supply Rejection,
Receive
PCM Code Equals Positive Zero
R
eb
a
100 mVrms
V
5.0 V
BB
Measure VF
DC
0
R
e
e
e
f
f
f
0 Hz–4000 Hz
4 kHz–25 kHz
25 kHz–50 kHz
40
40
36
dBC
dB
dB
10
Transmission Characteristics (Continued) Unless otherwise noted, limits printed in BOLD characters are
e
e b
e
e
0 C to 70 C by correlation with 100% electrical testing at T
A
g
g
guaranteed for V
CC
5.0V 5%, V
5.0V 5%; T
§
§
BB
A
25 C. All other limits are assured by correlation with other production tests and/or product design and characterization. GNDA
§
e
0V, f
5.0V, V
e
e
e
e
1.02 kHz, V
IN
0 dBm0, transmit input amplifier connected for unity gain non-inverting. Typicals specified at V
25 C.
CC
e b
5.0V, T
§
BB
A
Symbol
Parameter
Conditions
Min
Typ
Max
Units
b
SOS
Spurious Out-of-Band Signals
at the Channel Output
Loop Around Measurement, 0 dBm0,
30
dB
300 Hz to 3400 Hz Input PCM Code Applied
at D .
R
b
b
b
4600 Hz–7600 Hz
7600 Hz–8400 Hz
8400 Hz–100,000 Hz
30
40
30
dB
dB
dB
DISTORTION
STD
STD
Signal to Total Distortion
Transmit or Receive
Half-Channel
Sinusoidal Test Method (Note 3)
e
X
Level 3.0 dBm0
e
33
36
29
30
14
15
dBC
dBC
dBC
dBC
dBC
dBC
R
b
0 dBm0 to 30 dBm0
eb
40 dBm0
XMT
RCV
XMT
RCV
eb
55 dBm0
b
b
b
SFD
SFD
IMD
Single Frequency Distortion,
Transmit
46
46
41
dB
dB
dB
X
Single Frequency Distortion,
Receive
R
Intermodulation Distortion
Loop Around Measurement,
a
eb
b
4 dBm0 to 21 dBm0, Two
VF
X
Frequencies in the Range
300 Hz–3400 Hz
CROSSTALK
e
300 Hz–3400 Hz
CT
X-R
Transmit to Receive Crosstalk,
0 dBm0 Transmit Level
f
e
b
b
b
b
D
R
Quiet PCM Code
90
90
75
70
dB
dB
e
f
e
300 Hz–3400 Hz, VF I Multitone
CT
R-X
Receive to Transmit Crosstalk,
0 dBm0 Receive Level
X
(Note 2)
ENCODING FORMAT AT D OUTPUT
X
TP3057
A-Law
TP3054
m-Law
(Includes Even Bit Inversion)
ea
X
V
IN
V
IN
V
IN
(at GS )
Full-Scale
1
0
0
0
0
0
0
0
1
0
1
0
1
0
1
0
1
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
e
(at GS ) 0V
X
Ð
eb
(at GS )
X
Full-Scale
0
0
0
0
0
0
0
0
0
0
1
0
1
0
1
0
b
Note 1: Measured by extrapolation from the distortion test result at 50 dBm0.
are measured with a 50 dBm0 activation signal applied to VF Ia
.
b
Note 2: PPSR , NPSR , and CT
X
X
R-X
X
Note 3: Devices are measured using C message weighted filter for m-Law and psophometric weighted filter for A-Law.
11
Applications Information
POWER SUPPLIES
While the pins of the TP305X family are well protected
against electrical misuse, it is recommended that the stan-
dard CMOS practice be followed, ensuring that ground is
connected to the device before any other connections are
made. In applications where the printed circuit board may be
plugged into a ‘‘hot’’ socket with power and clocks already
present, an extra long ground pin in the connector should
be used.
This common ground point should be decoupled to V and
CC
V
with 10 mF capacitors.
BB
RECEIVE GAIN ADJUSTMENT
For applications where a TP305X family CODEC/filter re-
ceive output must drive a 600X load, but a peak swing lower
g
than 2.5V is required, the receive gain can be easily ad-
justed by inserting a matched T-pad or q-pad at the output.
Table II lists the required resistor values for 600X termina-
tions. As these are generally non-standard values, the equa-
tions can be used to compute the attenuation of the closest
practical set of resistors. It may be necessary to use un-
equal values for the R1 or R4 arms of the attenuators to
achieve a precise attenuation. Generally it is tolerable to
allow a small deviation of the input impedance from nominal
while still maintaining a good return loss. For example a 30
dB return loss against 600X is obtained if the output imped-
ance of the attenuator is in the range 282X to 319X (as-
suming a perfect transformer).
All ground connections to each device should meet at a
common point as close as possible to the GNDA pin. This
minimizes the interaction of ground return currents flowing
through a common bus impedance. 0.1 mF supply decou-
pling capacitors should be connected from this common
ground point to V
possible.
and V , as close to the device as
BB
CC
For best performance, the ground point of each CODEC/
FILTER on a card should be connected to a common card
ground in star formation, rather than via a ground bus.
T-Pad Attenuator
TL/H/5510–5
2
b
1
Z1.Z2
2
N
e
e
R3
R3
N
0
#
J
2
b
N
1
Z1
2
b
a
N
2NS
1
#
J
Note: See Application Note 370 for further details.
12
Applications Information (Continued)
e
e
TABLE II. Attentuator Tables for Z1 Z2 300X
(All Values in X)
dB
R1
R2
R3
R4
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
0.9
1.0
2
1.7
3.5
26k
13k
8.7k
6.5k
5.2k
4.4k
3.7k
3.3k
2.9k
2.6l
1.3k
850
650
494
402
380
284
244
211
184
161
142
125
110
98
3.5
6.9
52k
26k
5.2
10.4
13.8
17.3
21.3
24.2
27.7
31.1
34.6
70
17.4k
13k
6.9
8.5
10.5k
8.7k
7.5k
6.5k
5.8k
5.2k
2.6k
1.8k
1.3k
1.1k
900
785
698
630
527
535
500
473
450
430
413
386
366
10.4
12.1
13.8
15.5
17.3
34.4
51.3
68
3
107
144
183
224
269
317
370
427
490
550
635
720
816
924
1.17k
1.5k
4
5
84
6
100
115
379
143
156
168
180
190
200
210
218
233
246
7
8
9
10
11
12
13
14
15
16
18
20
77
61
Typical Synchronous Application
TL/H/5510–6
a
R1 R2
l
a
where (R1 R2) 10 KX.
e
c
Note 1: XMIT gain 20 log
R2
#
J
FIGURE 4
13
Connection Diagrams (Continued)
Plastic Chip Carrier
TL/H/5510–7
Top View
Order Number TP3057V
See NS Package Number V20A
14
Physical Dimensions inches (millimeters)
Cavity Dual-In-Line Package (J)
Order Number TP3054J or TP3057J
NS Package Number J16A
Molded Small Outline Package (WM)
Order Number TP3054WM or TP3057WM
NS Package Number M16B
15
Physical Dimensions inches (millimeters) (Continued)
Molded Dual-In-Line Package (N)
Order Number TP3054N or TP3057N
NS Package Number N16A
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