TMUX6236 [TI]
具有闩锁效应抑制和 1.8V 逻辑电平的 36V、低导通电阻、2:1 (SPDT)、双通道精密开关;
| 型号： | TMUX6236 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 具有闩锁效应抑制和 1.8V 逻辑电平的 36V、低导通电阻、2:1 (SPDT)、双通道精密开关 开关 光电二极管 |
| 文件： | 总44页 (文件大小：2356K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
TMUX6236
ZHCSQE5A –APRIL 2022 –REVISED JULY 2022
TMUX6236 具有1.8V 逻辑电平的36V、低RON、2:1 (SPDT)、双通道精密开关
1 特性
3 说明
• 双电源电压范围：±4.5V 至±18V
• 单电源电压范围：4.5V 至36V
• 低导通电阻：2Ω
• 大电流支持：330mA（最大值）(WQFN)
• –40°C 至+125°C 工作温度
• 兼容1.8V 逻辑电平
TMUX6236 是一款具有两个 2:1 开关的互补金属氧化
物半导体 (CMOS) 开关。该器件在双电源（±4.5V 至
±18V）、单电源（4.5V 至 36V）或非对称电源（例如
VDD = 12V，VSS = –5V）供电时均能正常运行。
TMUX6236 可在源极 (Sx) 和漏极 (D) 引脚上支持从
VSS 到VDD 范围的双向模拟和数字信号。
• 逻辑引脚具有集成的下拉电阻器
• 失效防护逻辑
• 轨到轨运行
所有逻辑控制输入均支持1.8V 至VDD 的逻辑电平，因
此，当器件在有效电源电压范围内运行时，可确保
TTL 和 CMOS 逻辑兼容性。失效防护逻辑电路允许先
在控制引脚上施加电压，然后在电源引脚上施加电压，
从而保护器件免受潜在的损害。
• 双向运行
2 应用
器件信息(1)
• 工厂自动化和工业控制
• 可编程逻辑控制器(PLC)
• 模拟输入模块
• ATE 测试设备
• 电池监控系统
• 超声波扫描仪
• 患者监护和诊断
• 光纤网络
封装尺寸（标称值）
器件型号
TMUX6236
封装
WQFN (16) (RUM)
4.00mm × 4.00mm
(1) 如需了解所有可用封装，请参阅数据表末尾的封装选项附录。
• 光学测试设备
• 远程无线电单元
• 有线网络
• 数据采集系统
VSS
VDD
S1A
S1B
S2A
S2B
D1
D2
SEL1
SEL2
Logic
Decoder
EN
方框图
本文档旨在为方便起见，提供有关TI 产品中文版本的信息，以确认产品的概要。有关适用的官方英文版本的最新信息，请访问
www.ti.com，其内容始终优先。TI 不保证翻译的准确性和有效性。在实际设计之前，请务必参考最新版本的英文版本。
English Data Sheet: SCDS449
TMUX6236
ZHCSQE5A –APRIL 2022 –REVISED JULY 2022
www.ti.com.cn
Table of Contents
7.8 Propagation Delay.................................................... 26
7.9 Charge Injection........................................................27
7.10 Off Isolation.............................................................27
7.11 Crosstalk................................................................. 28
7.12 Bandwidth............................................................... 28
7.13 THD + Noise........................................................... 29
7.14 Power Supply Rejection Ratio (PSRR)...................29
8 Detailed Description......................................................30
8.1 Functional Block Diagram.........................................30
8.2 Feature Description...................................................30
8.3 Device Functional Modes..........................................32
8.4 Truth Tables.............................................................. 32
9 Application and Implementation..................................32
9.1 Application Information............................................. 32
9.2 Typical Application.................................................... 32
10 Power Supply Recommendations..............................34
11 Layout...........................................................................35
11.1 Layout Guidelines................................................... 35
11.2 Layout Example...................................................... 35
12 Device and Documentation Support..........................36
12.1 Documentation Support.......................................... 36
12.2 接收文档更新通知................................................... 36
12.3 支持资源..................................................................36
12.4 Trademarks.............................................................36
12.5 术语表..................................................................... 36
12.6 Electrostatic Discharge Caution..............................36
13 Mechanical, Packaging, and Orderable
1 特性................................................................................... 1
2 应用................................................................................... 1
3 说明................................................................................... 1
4 Revision History.............................................................. 2
5 Pin Configuration and Functions...................................3
6 Specifications.................................................................. 4
6.1 Absolute Maximum Ratings........................................ 4
6.2 ESD Ratings............................................................... 4
6.3 Thermal Information....................................................4
6.4 Recommended Operating Conditions.........................5
6.5 Source or Drain Continuous Current...........................5
6.6 ±15 V Dual Supply: Electrical Characteristics ............6
6.7 ±15 V Dual Supply: Switching Characteristics ...........7
6.8 36 V Single Supply: Electrical Characteristics ........... 9
6.9 36 V Single Supply: Switching Characteristics ........ 10
6.10 12 V Single Supply: Electrical Characteristics ....... 12
6.11 12 V Single Supply: Switching Characteristics .......13
6.12 ±5 V Dual Supply: Electrical Characteristics ..........15
6.13 ±5 V Dual Supply: Switching Characteristics .........16
6.14 Typical Characteristics............................................18
7 Parameter Measurement Information..........................23
7.1 On-Resistance.......................................................... 23
7.2 Off-Leakage Current................................................. 23
7.3 On-Leakage Current................................................. 24
7.4 Transition Time......................................................... 24
7.5 tON(EN) and tOFF(EN) .................................................. 25
7.6 Break-Before-Make...................................................25
7.7 tON (VDD) Time............................................................26
Information.................................................................... 36
4 Revision History
Changes from Revision * (April 2022) to Revision A (July 2022)
Page
• 将数据表的状态从预告信息更改为量产数据..................................................................................................... 1
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5 Pin Configuration and Functions
D1
S1B
1
2
3
4
12
11
10
9
EN
VDD
S2B
D2
Thermal
Pad
VSS
GND
Not to scale
图5-1. RUM Package, 16-Pin WQFN (Top View)
表5-1. Pin Functions
PIN
TYPE(1)
DESCRIPTION
NAME
D1
NO.
1
I/O
I/O
Drain pin. Can be an input or output.
Drain pin. Can be an input or output.
D2
9
Active high logic enable, has internal pull-up resistor. When this pin is low, all switches are turned off. When this pin
is high, the SEL logic input determine which switch is turned on.
EN
12
4
I
GND
NC
P
Ground (0 V) reference
5, 7, 13, 14
No internal connection. Can be shorted to GND or left floating.
Source pin 1A. Can be an input or output.
—
S1A
S1B
S2A
S2B
SEL1
SEL2
16
2
I/O
I/O
I/O
I/O
Source pin 1B. Can be an input or output.
8
Source pin 2A. Can be an input or output.
10
15
6
Source pin 2B. Can be an input or output.
I
I
Logic control input, has internal pull-down resistor. 表8-1 lists how to control the switch connection.
Logic control input, has internal pull-down resistor. 表8-1 lists how to control the switch connection.
Positive power supply. This pin is the most positive power-supply potential. For reliable operation, connect a
decoupling capacitor ranging from 0.1 µF to 10 µF between VDD and GND.
VDD
11
3
P
P
Negative power supply. This pin is the most negative power-supply potential. In single-supply applications, this pin
can be connected to ground. For reliable operation, connect a decoupling capacitor ranging from 0.1 µF to 10 µF
between VSS and GND.
VSS
The thermal pad is not connected internally. There is no requirement to electrically connect this pad. If connected,
however, it is recommended that the pad be left floating or tied to GND.
Thermal Pad
—
(1) I = input, O = output, P = power
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6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)(1) (2)
MIN
MAX
UNIT
V
38
VDD –VSS
VDD
Supply voltage
38
V
–0.5
–38
VSS
0.5
V
VSEL or VEN
Logic control input pin voltage (SELx)
Logic control input pin current (SELx)
Source or drain voltage (Sx, Dx)
Diode clamp current(3)
38
30
V
–0.5
ISEL or IEN
mA
V
–30
VS or VD
VDD+0.5
30
VSS–0.5
–30
IIK
mA
mA
°C
°C
°C
mW
IS or ID (CONT)
Source or drain continuous current (Sx, Dx)
Ambient temperature
IDC + 10 %(4)
150
TA
–55
–65
Tstg
TJ
Storage temperature
150
Junction temperature
150
Ptot
Total power dissipation (QFN)(5)
1650
(1) Operation outside the Absolute Maximum Ratings may cause permanent device damage. Absolute Maximum Ratings do not imply
functional operation of the device at these or any other conditions beyond those listed under Recommended Operating Conditions. If
used outside the Recommended Operating Conditions but within the Absolute Maximum Ratings, the device may not be fully
functional, and this may affect device reliability, functionality, performance, and shorten the device lifetime.
(2) All voltages are with respect to ground, unless otherwise specified.
(3) Pins are diode-clamped to the power-supply rails. Over voltage signals must be voltage and current limited to maximum ratings.
(4) Refer to Source or Drain Continuous Current table for IDC specifications.
(5) For QFN package: Ptot derates linearily above TA = 70°C by 24.2mW/°C.
6.2 ESD Ratings
VALUE
UNIT
Human body model (HBM), per ANSI/ESDA/
JEDEC JS-001, all pins(1)
±1000
V(ESD)
Electrostatic discharge
V
Charged device model (CDM), per ANSI/ESDA/
JEDEC JS-002, all pins(2)
±500
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
6.3 Thermal Information
TMUX6236
THERMAL METRIC(1)
RUM (WQFN)
16 PINS
41.5
UNIT
RθJA
Junction-to-ambient thermal resistance
Junction-to-case (top) thermal resistance
Junction-to-board thermal resistance
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
RθJC(top)
RθJB
25.1
16.5
Junction-to-top characterization parameter
Junction-to-board characterization parameter
Junction-to-case (bottom) thermal resistance
0.3
ΨJT
16.4
ΨJB
RθJC(bot)
2.9
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
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6.4 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
MIN
4.5
4.5
VSS
0
NOM
MAX
36
UNIT
V
(1)
Power supply voltage differential
VDD –VSS
VDD
Positive power supply voltage
36
V
VS or VD
VSEL or VEN
Signal path input/output voltage (source or drain pin) (Sx, D)
Address or enable pin voltage
VDD
36
V
V
(2)
IS or ID (CONT) Source or drain continuous current (Sx, D)
TA Ambient temperature
IDC
mA
°C
125
–40
(1) VDD and VSS can be any value as long as 4.5 V ≤(VDD –VSS) ≤36 V, and the minimum VDD is met.
(2) Refer to Source or Drain Continuous Current table for IDC specifications.
6.5 Source or Drain Continuous Current
at supply voltage of VDD ± 10%, VSS ± 10 % (unless otherwise noted)
(2)
CONTINUOUS CURRENT PER CHANNEL (IDC
PACKAGE TEST CONDITIONS
+36 V Single Supply(1)
)
TA = 25°C
TA = 85°C
220
TA = 125°C
UNIT
330
120
mA
mA
mA
mA
mA
±15 V Dual Supply
+12 V Single Supply
±5 V Dual Supply
+5 V Single Supply
330
260
240
180
220
180
160
120
120
110
100
80
RUM (WQFN)
(1) Specified for nominal supply voltage only.
(2) Refer to the total power dissipation (Ptot) limits in the Absolute Maximum Ratings table, which must be followed with the maximum
continuous current specification.
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MAX UNIT
6.6 ±15 V Dual Supply: Electrical Characteristics
VDD = +15 V ± 10%, VSS = –15 V ±10%, GND = 0 V (unless otherwise noted)
Typical at VDD = +15 V, VSS = –15 V, TA = 25℃ (unless otherwise noted)
PARAMETER
TEST CONDITIONS
TA
MIN
TYP
ANALOG SWITCH
25°C
2
2.7
3.4
Ω
Ω
Ω
Ω
Ω
Ω
Ω
Ω
Ω
VS = –10 V to +10 V
ID = –10 mA
Refer to On-Resistance
RON
On-resistance
–40°C to +85°C
–40°C to +125°C
25°C
4
0.1
0.2
0.18
0.19
0.21
0.46
0.65
0.7
VS = –10 V to +10 V
ID = –10 mA
Refer to On-Resistance
On-resistance mismatch between
channels
–40°C to +85°C
–40°C to +125°C
25°C
ΔRON
VS = –10 V to +10 V
IS = –10 mA
Refer to On-Resistance
RON FLAT On-resistance flatness
RON DRIFT On-resistance drift
–40°C to +85°C
–40°C to +125°C
VS = 0 V, IS = –10 mA
Refer to On-Resistance
0.008
0.05
–40°C to +125°C
Ω/°C
25°C
0.35
3
nA
nA
VDD = 16.5 V, VSS = –16.5 V
Switch state is off
VS = +10 V / –10 V
–0.35
–3
–40°C to +85°C
IS(OFF)
Source off leakage current(1)
VD = –10 V / + 10 V
Refer to Off-Leakage Current
20
nA
–40°C to +125°C
–20
25°C
0.1
0.6
7
nA
nA
VDD = 16.5 V, VSS = –16.5 V
Switch state is off
VS = +10 V / –10 V
–0.6
–7
–40°C to +85°C
ID(OFF)
Drain off leakage current(1)
VD = –10 V / + 10 V
Refer to Off-Leakage Current
45
nA
–40°C to +125°C
–45
25°C
0.05
0.5
3.5
25
nA
nA
nA
–0.5
–3.5
–25
VDD = 16.5 V, VSS = –16.5 V
Switch state is on
VS = VD = ±10 V
IS(ON)
ID(ON)
Channel on leakage current(2)
–40°C to +85°C
–40°C to +125°C
Refer to On-Leakage Current
LOGIC INPUTS (SEL / EN pins)
VIH
VIL
IIH
Logic voltage high
1.3
0
36
0.8
2
V
–40°C to +125°C
–40°C to +125°C
–40°C to +125°C
–40°C to +125°C
–40°C to +125°C
Logic voltage low
V
Input leakage current
Input leakage current
Logic input capacitance
0.4
µA
µA
pF
IIL
–1.5 –0.005
CIN
3.5
POWER SUPPLY
25°C
45
7
60
70
85
24
30
38
µA
µA
µA
µA
µA
µA
VDD = 16.5 V, VSS = –16.5 V
Logic inputs = 0 V, 5 V, or VDD
IDD
VDD supply current
–40°C to +85°C
–40°C to +125°C
25°C
VDD = 16.5 V, VSS = –16.5 V
Logic inputs = 0 V, 5 V, or VDD
ISS
VSS supply current
–40°C to +85°C
–40°C to +125°C
(1) When VS is positive, VD is negative, or when VS is negative, VD is positive.
(2) When VS is at a voltage potential, VD is floating, or when VD is at a voltage potential, VS is floating.
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6.7 ±15 V Dual Supply: Switching Characteristics
VDD = +15 V ± 10%, VSS = –15 V ± 10%, GND = 0 V (unless otherwise noted)
Typical at VDD = +15 V, VSS = –15 V, TA = 25℃ (unless otherwise noted)
PARAMETER
TEST CONDITIONS
TA
MIN
TYP
MAX UNIT
25°C
110
130
160
180
120
135
145
160
175
190
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ms
ms
ms
VS = 10 V
RL = 300 Ω, CL = 35 pF
Refer to Transition Time
tTRAN
Transition time from control input
–40°C to +85°C
–40°C to +125°C
25°C
VS = 10 V
95
125
27
RL = 300 Ω, CL = 35 pF
Refer to Turn-on and Turn-off
Time
tON
Turn-on time from control input
Turn-off time from control input
Break-before-make time delay
–40°C to +85°C
–40°C to +125°C
25°C
VS = 10 V
RL = 300 Ω, CL = 35 pF
Refer to Turn-on and Turn-off
Time
tOFF
–40°C to +85°C
–40°C to +125°C
25°C
VS = 10 V,
RL = 300 Ω, CL = 35 pF
Refer to Break-before-make Time
5
5
tBBM
–40°C to +85°C
–40°C to +125°C
25°C
0.17
0.18
0.18
VDD rise time = 1 µs
RL = 300 Ω, CL = 35 pF
Refer to Turn-on (VDD) Time
Device turn on time
(VDD to output)
tON (VDD)
–40°C to +85°C
–40°C to +125°C
RL = 50 Ω, CL = 5 pF
Refer to Propagation Delay
tPD
Propagation delay
Charge injection
25°C
25°C
720
30
ps
VS = 0 V, CL = 100 pF
Refer to Charge Injection
QINJ
pC
RL = 50 Ω, CL = 5 pF
VS = 0 V, f = 100 kHz
Refer to Off Isolation
OISO
Off-isolation
Off-isolation
Crosstalk
25°C
25°C
25°C
25°C
dB
dB
dB
dB
–70
–50
RL = 50 Ω, CL = 5 pF
VS = 0 V, f = 1 MHz
Refer to Off Isolation
OISO
RL = 50 Ω, CL = 5 pF
VS = 0 V, f = 100 kHz
Refer to Crosstalk
XTALK
–107
–93
RL = 50 Ω, CL = 5 pF
VS = 0 V, f = 1 MHz
Refer to Crosstalk
XTALK
Crosstalk
RL = 50 Ω, CL = 5 pF
VS = 0 V
Refer to Bandwidth
BW
IL
25°C
25°C
40
MHz
dB
–3dB Bandwidth
RL = 50 Ω, CL = 5 pF
VS = 0 V, f = 1 MHz
Insertion loss
–0.15
VPP = 0.62 V on VDD and VSS
RL = 50 Ω, CL = 5 pF,
f = 1 MHz
ACPSRR AC Power Supply Rejection Ratio
25°C
25°C
dB
%
–68
Refer to ACPSRR
VPP = 15 V, VBIAS = 0 V
RL = 10 kΩ, CL = 5 pF,
f = 20 Hz to 20 kHz
THD+N
Total Harmonic Distortion + Noise
0.0006
Refer to THD + Noise
CS(OFF)
CD(OFF)
Source off capacitance
Drain off capacitance
VS = 0 V, f = 1 MHz
VS = 0 V, f = 1 MHz
25°C
25°C
45
55
pF
pF
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VDD = +15 V ± 10%, VSS = –15 V ± 10%, GND = 0 V (unless otherwise noted)
Typical at VDD = +15 V, VSS = –15 V, TA = 25℃ (unless otherwise noted)
PARAMETER
TEST CONDITIONS
TA
MIN
TYP
MAX UNIT
CS(ON),
CD(ON)
On capacitance
VS = 0 V, f = 1 MHz
25°C
165
pF
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6.8 36 V Single Supply: Electrical Characteristics
VDD = +36 V ± 10%, VSS = 0 V, GND = 0 V (unless otherwise noted)
Typical at VDD = +36 V, VSS = 0 V, TA = 25℃ (unless otherwise noted)
PARAMETER
TEST CONDITIONS
TA
MIN
TYP
MAX UNIT
ANALOG SWITCH
25°C
2.1
3.1
3.5
Ω
Ω
Ω
Ω
Ω
Ω
Ω
Ω
Ω
VS = 0 V to 30 V
ID = –10 mA
Refer to On-Resistance
RON
On-resistance
–40°C to +85°C
–40°C to +125°C
25°C
4.4
0.1
0.7
0.18
0.19
0.21
1.25
1.3
VS = 0 V to 30 V
ID = –10 mA
Refer to On-Resistance
On-resistance mismatch between
channels
–40°C to +85°C
–40°C to +125°C
25°C
ΔRON
VS = 0 V to 30 V
ID = –10 mA
Refer to On-Resistance
RON FLAT On-resistance flatness
RON DRIFT On-resistance drift
–40°C to +85°C
–40°C to +125°C
1.35
VS = 18 V, IS = –10 mA
Refer to On-Resistance
0.008
0.05
–40°C to +125°C
Ω/°C
VDD = 39.6 V, VSS = 0 V
Switch state is off
VS = 30 V / 1 V
25°C
0.25
5
nA
nA
–0.25
–5
–40°C to +85°C
IS(OFF)
Source off leakage current(1)
VD = 1 V / 30 V
Refer to Off-Leakage Current
39
nA
–40°C to +125°C
–39
VDD = 39.6 V, VSS = 0 V
Switch state is off
VS = 30 V / 1 V
VD = 1 V / 30 V
Refer to Off-Leakage Current
25°C
0.12
0.05
0.6
12
nA
nA
–0.6
–12
–40°C to +85°C
ID(OFF)
Drain off leakage current(1)
80
nA
–40°C to +125°C
–80
25°C
0.25
5
nA
nA
nA
VDD = 39.6 V, VSS = 0 V
Switch state is on
VS = VD = 30 V or 1 V
Refer to On-Leakage Current
–0.25
–5
IS(ON)
ID(ON)
Channel on leakage current(2)
–40°C to +85°C
–40°C to +125°C
39
–39
LOGIC INPUTS (SEL / EN pins)
VIH
VIL
IIH
Logic voltage high
1.3
0
44
0.8
V
–40°C to +125°C
–40°C to +125°C
–40°C to +125°C
–40°C to +125°C
–40°C to +125°C
Logic voltage low
V
Input leakage current
Input leakage current
Logic input capacitance
1
2.75
µA
µA
pF
IIL
–1.25 –0.005
CIN
3.5
POWER SUPPLY
25°C
50
75
85
µA
µA
µA
VDD = 39.6 V, VSS = 0 V
Logic inputs = 0 V, 5 V, or VDD
IDD
VDD supply current
–40°C to +85°C
–40°C to +125°C
100
(1) When VS is positive, VD is negative, or when VS is negative, VD is positive.
(2) When VS is at a voltage potential, VD is floating, or when VD is at a voltage potential, VS is floating.
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MAX UNIT
6.9 36 V Single Supply: Switching Characteristics
VDD = +36 V ± 10%, VSS = 0 V, GND = 0 V (unless otherwise noted)
Typical at VDD = +36 V, VSS = 0 V, TA = 25℃ (unless otherwise noted)
PARAMETER
TEST CONDITIONS
TA
MIN
TYP
25°C
85
135
150
170
130
150
170
165
180
195
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ms
ms
ms
VS = 18 V
RL = 300 Ω, CL = 35 pF
Refer to Transition Time
tTRAN
Transition time from control input
–40°C to +85°C
–40°C to +125°C
25°C
VS = 18 V
90
120
30
RL = 300 Ω, CL = 35 pF
Refer to Turn-on and Turn-off
Time
tON
Turn-on time from control input
Turn-off time from control input
Break-before-make time delay
–40°C to +85°C
–40°C to +125°C
25°C
VS = 18 V
RL = 300 Ω, CL = 35 pF
Refer to Turn-on and Turn-off
Time
tOFF
–40°C to +85°C
–40°C to +125°C
25°C
VS = 18 V,
RL = 300 Ω, CL = 35 pF
Refer to Break-before-make Time
8
8
tBBM
–40°C to +85°C
–40°C to +125°C
25°C
0.16
0.17
0.17
VDD rise time = 1 µs
RL = 300 Ω, CL = 35 pF
Refer to Turn-on (VDD) Time
Device turn on time
(VDD to output)
tON (VDD)
–40°C to +85°C
–40°C to +125°C
RL = 50 Ω, CL = 5 pF
Refer to Propagation Delay
tPD
Propagation delay
Charge injection
25°C
25°C
900
78
ps
VS = 18 V, CL = 100 pF
Refer to Charge Injection
QINJ
pC
RL = 50 Ω, CL = 5 pF
VS = 6 V, f = 100 kHz
Refer to Off Isolation
OISO
Off-isolation
Off-isolation
Crosstalk
25°C
25°C
25°C
25°C
dB
dB
dB
dB
–70
–50
RL = 50 Ω, CL = 5 pF
VS = 6 V, f = 1 MHz
Refer to Off Isolation
OISO
RL = 50 Ω, CL = 5 pF
VS = 6 V, f = 100 kHz
Refer to Crosstalk
XTALK
–112
–93
RL = 50 Ω, CL = 5 pF
VS = 6 V, f = 1 MHz
Refer to Crosstalk
XTALK
Crosstalk
RL = 50 Ω, CL = 5 pF
VS = 6 V
Refer to Bandwidth
BW
IL
25°C
25°C
35
MHz
dB
–3dB Bandwidth
RL = 50 Ω, CL = 5 pF
VS = 6 V, f = 1 MHz
Insertion loss
–0.16
VPP = 0.62 V on VDD and VSS
RL = 50 Ω, CL = 5 pF,
f = 1 MHz
ACPSRR AC Power Supply Rejection Ratio
25°C
25°C
dB
%
–65
Refer to ACPSRR
VPP = 18 V, VBIAS = 6 V
RL = 10 kΩ, CL = 5 pF,
f = 20 Hz to 20 kHz
THD+N
Total Harmonic Distortion + Noise
0.0006
Refer to THD + Noise
CS(OFF)
CD(OFF)
Source off capacitance
Drain off capacitance
VS = 6 V, f = 1 MHz
VS = 6 V, f = 1 MHz
25°C
25°C
45
60
pF
pF
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6.9 36 V Single Supply: Switching Characteristics (continued)
VDD = +36 V ± 10%, VSS = 0 V, GND = 0 V (unless otherwise noted)
Typical at VDD = +36 V, VSS = 0 V, TA = 25℃ (unless otherwise noted)
PARAMETER
TEST CONDITIONS
TA
MIN
TYP
MAX UNIT
CS(ON),
CD(ON)
On capacitance
VS = 6 V, f = 1 MHz
25°C
165
pF
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MAX UNIT
6.10 12 V Single Supply: Electrical Characteristics
VDD = +12 V ± 10%, VSS = 0 V, GND = 0 V (unless otherwise noted)
Typical at VDD = +12 V, VSS = 0 V, TA = 25℃ (unless otherwise noted)
PARAMETER
TEST CONDITIONS
TA
MIN
TYP
ANALOG SWITCH
25°C
2.8
5.4
6.8
Ω
Ω
Ω
Ω
Ω
Ω
Ω
Ω
Ω
VS = 0 V to 10 V
ID = –10 mA
Refer to On-Resistance
RON
On-resistance
–40°C to +85°C
–40°C to +125°C
25°C
7.4
0.13
0.8
0.21
0.23
0.25
1.7
VS = 0 V to 10 V
ID = –10 mA
Refer to On-Resistance
On-resistance mismatch between
channels
–40°C to +85°C
–40°C to +125°C
25°C
ΔRON
VS = 0 V to 10 V
ID = –10 mA
Refer to On-Resistance
1.9
RON FLAT On-resistance flatness
RON DRIFT On-resistance drift
–40°C to +85°C
–40°C to +125°C
2
VS = 0 V, IS = –10 mA
Refer to On-Resistance
0.015
0.01
–40°C to +125°C
Ω/°C
VDD = 13.2 V, VSS = 0 V
Switch state is off
VS = 10 V / 1 V
25°C
0.25
2
nA
nA
–0.25
–2
–40°C to +85°C
IS(OFF)
Source off leakage current(1)
VD = 1 V / 10 V
Refer to Off-Leakage Current
16
nA
–40°C to +125°C
–16
VDD = 13.2 V, VSS = 0 V
Switch state is off
VS = 10 V / 1 V
VD = 1 V / 10 V
Refer to Off-Leakage Current
25°C
0.12
0.01
0.6
5
nA
nA
–0.6
–5
–40°C to +85°C
ID(OFF)
Drain off leakage current(1)
34
nA
–40°C to +125°C
–34
25°C
0.35
2
nA
nA
nA
VDD = 13.2 V, VSS = 0 V
Switch state is on
VS = VD = 10 V or 1 V
Refer to On-Leakage Current
–0.35
–2
IS(ON)
ID(ON)
Channel on leakage current(2)
–40°C to +85°C
–40°C to +125°C
16
–16
LOGIC INPUTS (SEL / EN pins)
VIH
VIL
IIH
Logic voltage high
1.3
0
44
0.8
V
–40°C to +125°C
–40°C to +125°C
–40°C to +125°C
–40°C to +125°C
–40°C to +125°C
Logic voltage low
V
Input leakage current
Input leakage current
Logic input capacitance
0.4
2.25
µA
µA
pF
IIL
–1.25 –0.005
CIN
3.5
POWER SUPPLY
25°C
30
44
52
62
µA
µA
µA
VDD = 13.2 V, VSS = 0 V
Logic inputs = 0 V, 5 V, or VDD
IDD
VDD supply current
–40°C to +85°C
–40°C to +125°C
(1) When VS is positive, VD is negative, or when VS is negative, VD is positive.
(2) When VS is at a voltage potential, VD is floating, or when VD is at a voltage potential, VS is floating.
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6.11 12 V Single Supply: Switching Characteristics
VDD = +12 V ± 10%, VSS = 0 V, GND = 0 V (unless otherwise noted)
Typical at VDD = +12 V, VSS = 0 V, TA = 25℃ (unless otherwise noted)
PARAMETER
TEST CONDITIONS
TA
MIN
TYP
MAX UNIT
25°C
100
180
220
245
235
260
280
200
220
245
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ms
ms
ms
VS = 8 V
RL = 300 Ω, CL = 35 pF
Refer to Transition Time
tTRAN
Transition time from control input
–40°C to +85°C
–40°C to +125°C
25°C
VS = 8 V
190
160
30
RL = 300 Ω, CL = 35 pF
Refer to Turn-on and Turn-off
Time
tON
Turn-on time from control input
Turn-off time from control input
Break-before-make time delay
–40°C to +85°C
–40°C to +125°C
25°C
VS = 8 V
RL = 300 Ω, CL = 35 pF
Refer to Turn-on and Turn-off
Time
tOFF
–40°C to +85°C
–40°C to +125°C
25°C
VS = 8 V,
RL = 300 Ω, CL = 35 pF
Refer to Break-before-make Time
9
9
tBBM
–40°C to +85°C
–40°C to +125°C
25°C
0.17
0.18
0.18
VDD rise time = 1 µs
RL = 300 Ω, CL = 35 pF
Refer to Turn-on (VDD) Time
Device turn on time
(VDD to output)
tON (VDD)
–40°C to +85°C
–40°C to +125°C
RL = 50 Ω, CL = 5 pF
Refer to Propagation Delay
tPD
Propagation delay
Charge injection
25°C
25°C
770
12
ps
VS = 6 V, CL = 100 pF
Refer to Charge Injection
QINJ
pC
RL = 50 Ω, CL = 5 pF
VS = 6 V, f = 100 kHz
Refer to Off Isolation
OISO
Off-isolation
Off-isolation
Crosstalk
25°C
25°C
25°C
25°C
dB
dB
dB
dB
–70
–50
RL = 50 Ω, CL = 5 pF
VS = 6 V, f = 1 MHz
Refer to Off Isolation
OISO
RL = 50 Ω, CL = 5 pF
VS = 6 V, f = 100 kHz
Refer to Crosstalk
XTALK
–112
–93
RL = 50 Ω, CL = 5 pF
VS = 6 V, f = 1 MHz
Refer to Crosstalk
XTALK
Crosstalk
RL = 50 Ω, CL = 5 pF
VS = 6 V
Refer to Bandwidth
BW
IL
25°C
25°C
50
MHz
dB
–3dB Bandwidth
RL = 50 Ω, CL = 5 pF
VS = 6 V, f = 1 MHz
Insertion loss
–0.25
VPP = 0.62 V on VDD and VSS
RL = 50 Ω, CL = 5 pF,
f = 1 MHz
ACPSRR AC Power Supply Rejection Ratio
25°C
25°C
dB
%
–70
Refer to ACPSRR
VPP = 6 V, VBIAS = 6 V
RL = 10 kΩ, CL = 5 pF,
f = 20 Hz to 20 kHz
THD+N
Total Harmonic Distortion + Noise
0.001
Refer to THD + Noise
CS(OFF)
CD(OFF)
Source off capacitance
Drain off capacitance
VS = 6 V, f = 1 MHz
VS = 6 V, f = 1 MHz
25°C
25°C
52
68
pF
pF
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6.11 12 V Single Supply: Switching Characteristics (continued)
VDD = +12 V ± 10%, VSS = 0 V, GND = 0 V (unless otherwise noted)
Typical at VDD = +12 V, VSS = 0 V, TA = 25℃ (unless otherwise noted)
PARAMETER
TEST CONDITIONS
TA
MIN
TYP
MAX UNIT
CS(ON)
CD(ON)
,
On capacitance
VS = 6 V, f = 1 MHz
25°C
170
pF
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6.12 ±5 V Dual Supply: Electrical Characteristics
VDD = +5 V ± 10%, VSS = –5 V ±10%, GND = 0 V (unless otherwise noted)
Typical at VDD = +5 V, VSS = –5 V, TA = 25℃ (unless otherwise noted)
PARAMETER
TEST CONDITIONS
TA
MIN
TYP
MAX UNIT
ANALOG SWITCH
25°C
3.3
6.3
7.6
Ω
Ω
Ω
Ω
Ω
Ω
Ω
Ω
Ω
VS = –4.5 V to +4.5 V
ID = –10 mA
Refer to On-Resistance
RON
On-resistance
–40°C to +85°C
–40°C to +125°C
25°C
8.5
0.07
1
0.22
0.23
0.25
2
VS = –4.5 V to +4.5 V
ID = –10 mA
Refer to On-Resistance
On-resistance mismatch between
channels
–40°C to +85°C
–40°C to +125°C
25°C
ΔRON
VS = –4.5 V to +4.5 V
ID = –10 mA
Refer to On-Resistance
2.1
RON FLAT On-resistance flatness
RON DRIFT On-resistance drift
–40°C to +85°C
–40°C to +125°C
2.2
VS = 0 V, IS = –10 mA
Refer to On-Resistance
0.015
0.05
–40°C to +125°C
Ω/°C
25°C
0.4
2
nA
nA
VDD = +5.5 V, VSS = –5.5 V
Switch state is off
VS = +4.5 V / –4.5 V
–0.4
–2
–40°C to +85°C
IS(OFF)
Source off leakage current(1)
VD = –4.5 V / + 4.5 V
Refer to Off-Leakage Current
16
nA
–40°C to +125°C
–16
25°C
0.12
0.05
1
5
nA
nA
VDD = +5.5 V, VSS = –5.5 V
Switch state is off
VS = +4.5 V / –4.5 V
VD = –4.5 V / + 4.5 V
Refer to Off-Leakage Current
–1
–5
–40°C to +85°C
ID(OFF)
Drain off leakage current(1)
35
nA
–40°C to +125°C
–35
25°C
0.4
2
nA
nA
nA
–0.4
–2
VDD = +5.5 V, VSS = –5.5 V
Switch state is on
VS = VD = ±4.5 V
IS(ON)
ID(ON)
Channel on leakage current(2)
–40°C to +85°C
–40°C to +125°C
Refer to On-Leakage Current
16
–16
LOGIC INPUTS (SEL / EN pins)
VIH
VIL
IIH
Logic voltage high
1.3
0
44
0.8
2
V
–40°C to +125°C
–40°C to +125°C
–40°C to +125°C
–40°C to +125°C
–40°C to +125°C
Logic voltage low
V
Input leakage current
Input leakage current
Logic input capacitance
0.4
µA
µA
pF
IIL
–1.2 –0.005
CIN
3.5
POWER SUPPLY
25°C
28
6
38
44
55
8.4
11
µA
µA
µA
µA
µA
µA
VDD = +5.5 V, VSS = –5.5 V
Logic inputs = 0 V, 5 V, or VDD
IDD
VDD supply current
–40°C to +85°C
–40°C to +125°C
25°C
VDD = +5.5 V, VSS = –5.5 V
Logic inputs = 0 V, 5 V, or VDD
ISS
VSS supply current
–40°C to +85°C
–40°C to +125°C
20
(1) When VS is positive, VD is negative, or when VS is negative, VD is positive.
(2) When VS is at a voltage potential, VD is floating, or when VD is at a voltage potential, VS is floating.
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6.13 ±5 V Dual Supply: Switching Characteristics
VDD = +5 V ± 10%, VSS = –5 V ±10%, GND = 0 V (unless otherwise noted)
Typical at VDD = +5 V, VSS = –5 V, TA = 25℃ (unless otherwise noted)
PARAMETER
TEST CONDITIONS
TA
MIN
TYP
25°C
135
210
250
285
290
315
340
250
270
295
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ms
ms
ms
VS = 3 V
RL = 300 Ω, CL = 35 pF
Refer to Transition Time
tTRAN
Transition time from control input
–40°C to +85°C
–40°C to +125°C
25°C
VS = 3 V
140
170
32
RL = 300 Ω, CL = 35 pF
Refer to Turn-on and Turn-off
Time
tON
Turn-on time from control input
Turn-off time from control input
Break-before-make time delay
–40°C to +85°C
–40°C to +125°C
25°C
VS = 3 V
RL = 300 Ω, CL = 35 pF
Refer to Turn-on and Turn-off
Time
tOFF
–40°C to +85°C
–40°C to +125°C
25°C
VS = 3 V,
RL = 300 Ω, CL = 35 pF
Refer to Break-before-make Time
7
7
tBBM
–40°C to +85°C
–40°C to +125°C
25°C
0.17
0.18
0.18
VDD rise time = 1 µs
RL = 300 Ω, CL = 35 pF
Refer to Turn-on (VDD) Time
Device turn on time
(VDD to output)
tON (VDD)
–40°C to +85°C
–40°C to +125°C
RL = 50 Ω, CL = 5 pF
Refer to Propagation Delay
tPD
Propagation delay
Charge injection
25°C
25°C
670
9
ps
VS = 0 V, CL = 100 pF
Refer to Charge Injection
QINJ
pC
RL = 50 Ω, CL = 5 pF
VS = 0 V, f = 100 kHz
Refer to Off Isolation
OISO
Off-isolation
Off-isolation
Crosstalk
25°C
25°C
25°C
25°C
dB
dB
dB
dB
–70
–50
RL = 50 Ω, CL = 5 pF
VS = 0 V, f = 1 MHz
Refer to Off Isolation
OISO
RL = 50 Ω, CL = 5 pF
VS = 0 V, f = 100 kHz
Refer to Crosstalk
XTALK
–117
–94
RL = 50 Ω, CL = 5 pF
VS = 0 V, f = 1 MHz
Refer to Crosstalk
XTALK
Crosstalk
RL = 50 Ω, CL = 5 pF
VS = 0 V
Refer to Bandwidth
BW
IL
25°C
25°C
55
MHz
dB
–3dB Bandwidth
RL = 50 Ω, CL = 5 pF
VS = 0 V, f = 1 MHz
Insertion loss
–0.28
VPP = 0.62 V on VDD and VSS
RL = 50 Ω, CL = 5 pF,
f = 1 MHz
ACPSRR AC Power Supply Rejection Ratio
25°C
25°C
dB
%
–70
Refer to ACPSRR
VPP = 5 V, VBIAS = 0 V
RL = 10 kΩ, CL = 5 pF,
f = 20 Hz to 20 kHz
THD+N
Total Harmonic Distortion + Noise
0.001
Refer to THD + Noise
CS(OFF)
CD(OFF)
Source off capacitance
Drain off capacitance
VS = 0 V, f = 1 MHz
VS = 0 V, f = 1 MHz
25°C
25°C
54
72
pF
pF
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VDD = +5 V ± 10%, VSS = –5 V ±10%, GND = 0 V (unless otherwise noted)
Typical at VDD = +5 V, VSS = –5 V, TA = 25℃ (unless otherwise noted)
PARAMETER
TEST CONDITIONS
TA
MIN
TYP
MAX UNIT
CS(ON),
CD(ON)
On capacitance
VS = 0 V, f = 1 MHz
25°C
170
pF
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6.14 Typical Characteristics
at TA = 25°C (unless otherwise noted)
3
7
6.5
6
VDD = 15 V, VSS = -15 V
VDD = 18 V, VSS = -18 V
VDD = 5 V, VSS = -5 V
VDD = 10 V, VSS = -10 V
VDD = 12 V, VSS = -12 V
VDD = 13.5 V, VSS = -13.5 V
2.7
2.4
2.1
1.8
1.5
5.5
5
4.5
4
3.5
3
2.5
2
1.5
1
-18
-14
-10
-6
-2
2
6
10
14
18
-15
-10
-5
0
5
10
15
VS or VD - Source or Drain Voltage (V)
VS or VD - Source or Drain Voltage (V)
.
.
图6-1. On-Resistance vs Source or Drain Voltage –Dual
图6-2. On-Resistance vs Source or Drain Voltage –Dual
Supply
Supply
4
10
VDD = 18 V, VSS = 0 V
VDD = 24 V, VSS = 0 V
VDD = 36 V, VSS = 0 V
VDD = 5 V, VSS = 0 V
VDD = 8 V, VSS = 0 V
VDD = 10.8 V, VSS = 0 V
VDD = 12 V, VSS = 0 V
VDD = 15 V, VSS = 0 V
9
8
7
6
5
4
3
2
3.5
3
2.5
2
1.5
0
.
5
10
15
0
5
10
15
20
25
30
35
VS or VD - Source or Drain Voltage (V)
VS or VD - Source or Drain Voltage (V)
.
图6-4. On-Resistance vs Source or Drain Voltage –Single
图6-3. On-Resistance vs Source or Drain Voltage –Single
Supply
Supply
5.6
10
TA = -40C
TA = 25C
TA = -40C
TA = 25C
4.8
8.5
TA = 85C
TA = 85C
TA = 125C
TA = 125C
4
7
3.2
2.4
1.6
0.8
5.5
4
2.5
1
-16
-12
-8
-4
0
4
8
12
16
0
1.5
3
4.5
6
7.5
9
10.5
12
VS or VD - Source or Drain Voltage (V)
VS or VD - Source or Drain Voltage (V)
VDD = 12 V, VSS = 0 V
VDD = 15 V, VSS = −15 V
图6-6. On-Resistance vs Temperature
图6-5. On-Resistance vs Temperature
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6.14 Typical Characteristics (continued)
at TA = 25°C (unless otherwise noted)
10.5
5.6
4.8
4
TA = -40C
TA = -40C
TA = 25C
TA = 85C
TA = 125C
TA = 25C
TA = 85C
TA = 125C
9
7.5
6
3.2
2.4
1.6
0.8
4.5
3
1.5
-5
-4
-3
-2
-1
0
1
2
3
4
5
125
125
0
6
12
18
24
30
36
VS or VD - Source or Drain Voltage (V)
VS or VD - Source or Drain Voltage (V)
VDD = 5 V, VSS = −5 V
VDD = 36 V, VSS = 0 V
图6-7. On-Resistance vs Temperature
图6-8. On-Resistance vs Temperature
30
24
18
12
6
20
16
12
8
IDOFF VS/VD = -10 V/10 V
IDOFF VS/VD = 10 V/-10 V
IDON -10 V
IDON 10 V
ISOFF VS/VD = -10 V/10 V
ISOFF VS/VD = 10 V/-10 V
IDOFF VS/VD = 1 V/10 V
IDOFF VS/VD = 10 V/1 V
IDON 1 V
IDON 10 V
ISOFF VS/VD = 1 V/10 V
ISOFF VS/VD = 10 V/1 V
4
0
0
-4
-6
-8
-12
-18
-24
-30
-12
-16
-20
0
25
50
75
100
125
0
25
50
75
100
Temperature (C)
Temperature (C)
VDD = 12 V, VSS = 0 V
VDD = 15 V, VSS = −15 V
图6-10. On-Leakage vs Temperature
图6-9. On-Leakage vs Temperature
35
30
25
20
15
10
5
IDOFF VS/VD = 1 V/30 V
IDOFF VS/VD = 30 V/1 V
ION 1 V
ION 30 V
ISOFF VS/VD = 1 V/30 V
ISOFF VS/VD = 30 V/1 V
0
-5
-10
-15
-20
-25
-30
-35
0
25
50
75
100
Temperature (C)
VDD = 36 V, VSS = 0 V
VDD = 5 V, VSS = −5 V
图6-11. On-Leakage vs Temperature
图6-12. On-Leakage vs Temperature
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6.14 Typical Characteristics (continued)
at TA = 25°C (unless otherwise noted)
140
110
80
70
VDD = 15 V, VSS = -15 V
VDD = 5 V, VSS = -5 V
VDD = 15 V, VSS = -15 V
VDD = 12 V, VSS = 0 V
VDD = 5 V, VSS = -5 V
VDD = 5 V, VSS = 0 V
60
50
40
30
20
50
20
-10
-40
-70
-15
-10
-5
0
5
10
15
0
5
10
15
20
25
30
35
VS - Source Voltage (V)
Logic Voltage (V)
.
All channels on
图6-14. Charge Injection vs Source Voltage –Dual Supply
图6-13. Supply Current vs Logic Voltage
130
100
70
180
VDD = 5 V, VSS = -5 V
VDD = 15 V, VSS = -15 V
VDD = 36 V, VSS = 0 V
VDD = 20 V, VSS = 0 V
VDD = 15 V, VSS = 0 V
VDD = 12 V, VSS = 0 V
150
120
VDD = 5 V, VSS = 0 V
90
60
30
40
10
0
-30
-60
-90
-20
-50
-15
-10
-5
0
5
10
15
0
5
10
15
20
25
30
35
VD - Drain Voltage (V)
VS - Source Voltage (V)
.
.
图6-15. Charge Injection vs Drain Voltage –Dual Supply
图6-16. Charge Injection vs Source Voltage –Single Supply
180
250
VDD = 36 V, VSS = 0 V
VDD: 5 V, VSS: -5 V
VDD: 15 V, VSS: -15 V
150
120
90
VDD = 20 V, VSS = 0 V
VDD = 15 V, VSS = 0 V
VDD = 12 V, VSS = 0 V
VDD = 5 V, VSS = 0 V
225
200
175
150
125
100
75
60
30
0
-30
-60
-90
50
-50
0
5
10
15
20
25
30
35
-25
0
25
50
75
100
125
VD - Drain Voltage (V)
Temperature (C)
.
.
图6-17. Charge Injection vs Drain Voltage –Single Supply
图6-18. TTRANSITION vs Temperature
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6.14 Typical Characteristics (continued)
at TA = 25°C (unless otherwise noted)
360
180
165
150
135
120
105
90
VDD: 5 V, VSS: 0 V
VDD: 12 V, VSS: 0 V
VDD: 36 V, VSS: 0 V
T(OFF)
T(ON)
320
280
240
200
160
120
80
75
40
60
-50
-25
0
25
50
75
100
125
-50
-25
0
25
50
75
100
125
Temperature (C)
Temperature (C)
.
VDD = 15 V, VSS = −15 V
图6-20. TON (EN) and TOFF (EN) vs Temperature
图6-19. TTRANSITION vs Temperature
0
180
T(OFF)
T(ON)
165
150
135
120
105
90
-20
-40
-60
-80
-100
-120
-140
75
100
1k
10k
100k
Frequency(Hz)
1M
10M
100M
60
-50
-25
0
25
50
75
100
125
Temperature (C)
VDD = 15 V, VSS = −15 V
图6-22. Off-Isolation vs Frequency
VDD = 36 V, VSS = 0 V
图6-21. TON (EN) and TOFF (EN) vs Temperature
0
0
-1
-2
-3
-4
-5
-6
Adjacent Channel
Non-Adjacent Channel
-20
-40
-60
-80
-100
-120
-140
100
1k
10k
100k
1M
10M
100M
Frequency(Hz)
1k
10k
100k
1M
10M
100M
Frequency(Hz)
VDD = 15 V, VSS = −15 V
图6-23. Crosstalk vs Frequency
VDD = 15 V, VSS = −15 V
图6-24. On Response vs Frequency
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6.14 Typical Characteristics (continued)
at TA = 25°C (unless otherwise noted)
270
240
210
180
150
120
90
225
200
175
150
125
100
75
CDOFF
CON
CSOFF
CDOFF
CON
CSOFF
60
50
30
25
-15
-10
-5
0
5
10
15
0
2
4
6
8
10
12
VS or VD - Source or Drain Voltage (V)
VS or VD - Source or Drain Voltage (V)
VDD = 12 V, VSS = 0 V
VDD = 15 V, VSS = −15 V
图6-26. Capacitance vs Source or Drain Voltage
图6-25. Capacitance vs Source or Drain Voltage
0.002
0.002
VDD = 36 V, VSS = 0 V
VDD = 12 V, VSS = 0 V
VDD = 15 V, VSS = -15 V
0.001
0.001
0.0008
0.0007
0.0006
0.0008
0.0007
0.0006
0.0005
0.0004
0.0005
0.0004
0.0003
0.0003
0.0002
20
100
1k
Frequency (Hz)
10k 20k
0.0002
20
100
1k
Frequency (Hz)
10k 20k
.
.
图6-27. THD+N vs Frequency –Single Supply
图6-28. THD+N vs Frequency –Dual Supply
0
VDD with decoupling capacitors
VDD without decoupling capacitors
VSS with decoupling capacitors
VSS without decoupling capacitors
-20
-40
-60
-80
-100
-120
10
100
1k
10k
100k
1M
10M 50M
Frequency (Hz)
VDD = 15 V, VSS = −15 V
图6-29. ACPSRR vs Frequency
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7 Parameter Measurement Information
7.1 On-Resistance
The on-resistance of a device is the ohmic resistance between the source (Sx) and drain (D) pins of the device.
The on-resistance varies with input voltage and supply voltage. The symbol RON is used to denote on-
resistance. 图 7-1 shows the measurement setup used to measure RON. Voltage (V) and current (ISD) are
measured using this setup, and RON is computed with RON = V / ISD
.
V
ISD
Sx
Dx
VS
图7-1. On-Resistance Measurement Setup
7.2 Off-Leakage Current
There are two types of leakage currents associated with a switch during the off state:
• Source off-leakage current
• Drain off-leakage current
Source leakage current is defined as the leakage current flowing into or out of the source pin when the switch is
off. This current is denoted by the symbol IS(OFF)
Drain leakage current is defined as the leakage current flowing into or out of the drain pin when the switch is off.
This current is denoted by the symbol ID(OFF)
图7-2 shows the setup used to measure both off-leakage currents.
.
.
VDD
VSS
VDD
VSS
Is (OFF)
ID (OFF)
S1A
S1B
S1A
S1B
A
D1
D1
A
VS
VD
VD
VS
VD
Is (OFF)
ID (OFF)
S2A
S2B
S2A
S2B
D2
A
A
D2
VS
VD
VS
GND
GND
VD
VD
IS(OFF)
ID(OFF)
图7-2. Off-Leakage Measurement Setup
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7.3 On-Leakage Current
Source on-leakage current is defined as the leakage current flowing into or out of the source pin when the switch
is on. This current is denoted by the symbol IS(ON)
.
Drain on-leakage current is defined as the leakage current flowing into or out of the drain pin when the switch is
on. This current is denoted by the symbol ID(ON)
.
Either the source pin or drain pin is left floating during the measurement. 图 7-3 shows the circuit used for
measuring the on-leakage current, denoted by IS(ON) or ID(ON)
.
VDD
VSS
VDD
VSS
Is (ON)
A
ID (ON)
S1A
S1B
S1A
S1B
N.C.
N.C.
D1
D1
A
N.C.
VS
N.C.
VD
Is (ON)
A
S2A
S2B
S2A
S2B
N.C.
N.C.
D2
D2
N.C.
A
VS
N.C.
VD
GND
GND
IS(ON)
图7-3. On-Leakage Measurement Setup
ID(ON)
7.4 Transition Time
Transition time is defined as the time taken by the output of the device to rise or fall 90% after the address signal
has risen or fallen past the logic threshold. The 90% transition measurement is utilized to provide the timing of
the device. System level timing can then account for the time constant added from the load resistance and load
capacitance. 图7-4 shows the setup used to measure transition time, denoted by the symbol tTRANSITION
.
VDD
VSS
0.1 µF
0.1 µF
VS
3 V
0 V
VDD
S1A
VSS
VSEL
tr < 20 ns
tf < 20 ns
50%
50%
D1
Output
CL
S1B
tTRANSITION
tTRANSITION
RL
90%
Output
0 V
S2A
S2B
VS
D2
Output
CL
10%
RL
SELx
GND
VSEL
图7-4. Transition-Time Measurement Setup
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7.5 tON(EN) and tOFF(EN)
Turn-on time is defined as the time taken by the output of the device to rise to 90% after the enable has risen
past the logic threshold. The 90% measurement is utilized to provide the timing of the device. System level
timing can then account for the time constant added from the load resistance and load capacitance. 图 7-7
shows the setup used to measure turn-on time, denoted by the symbol tON(EN)
.
Turn-off time is defined as the time taken by the output of the device to fall to 10% after the enable has fallen
past the logic threshold. The 10% measurement is utilized to provide the timing of the device. System level
timing can then account for the time constant added from the load resistance and load capacitance. 图 7-7
shows the setup used to measure turn-off time, denoted by the symbol tOFF(EN)
.
VDD
VSS
0.1 µF
0.1 µF
3 V
VDD
VSS
VEN
tr < 20 ns
tf < 20 ns
50%
50%
S1A
S1B
0 V
VS
D1
D2
Output
CL
tON
tOFF
RL
90%
Output
0 V
S2A
S2B
VS
Output
CL
10%
RL
EN
GND
VEN
图7-5. Turn-On and Turn-Off Time Measurement Setup
7.6 Break-Before-Make
Break-before-make delay is a safety feature that prevents two inputs from connecting when the device is
switching. The output first breaks from the on-state switch before making the connection with the next on-state
switch. The time delay between the break and the make is known as break-before-make delay. 图7-6 shows the
setup used to measure break-before-make delay, denoted by the symbol tOPEN(BBM)
.
VDD
VSS
0.1 µF
0.1 µF
3 V
VDD
VSS
VSEL
tr < 20 ns
tf < 20 ns
S1A
S1B
VS
0 V
D1
D2
Output
CL
RL
80%
Output
0 V
S2A
S2B
VS
tBBM
1
tBBM 2
Output
CL
RL
tOPEN (BBM) = min ( tBBM 1, tBBM 2)
SELx
GND
VSEL
图7-6. Break-Before-Make Delay Measurement Setup
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7.7 tON (VDD) Time
The tON (VDD) time is defined as the time taken by the output of the device to rise to 90% after the supply has
risen past the supply threshold. The 90% measurement is used to provide the timing of the device turning on in
the system. 图7-7 shows the setup used to measure turn on time, denoted by the symbol tON (VDD)
.
VSS
0.1 µF
0.1 µF
VDD
Supply
VDD
VDD
S1A
VSS
tr = 10 µs
4.5 V
Ramp
VS
0 V
Output
D1
D2
S1B
tON
RL
CL
90%
Output
0 V
VS
S2A
S2B
Output
CL
RL
EN
3 V
SELx
GND
图7-7. tON (VDD) Time Measurement Setup
7.8 Propagation Delay
Propagation delay is defined as the time taken by the output of the device to rise or fall 50% after the input signal
has risen or fallen past the 50% threshold. 图 7-8 shows the setup used to measure propagation delay, denoted
by the symbol tPD
.
VDD
VSS
250 mV
0.1 µF
0.1 µF
VDD
S1A
VSS
Input
(VS)
50%
50%
tr < 40 ps
tf < 40 ps
50
VS
0 V
D1
Output
CL
tPD
1
tPD 2
S1B
RL
Output
0 V
50%
50%
50
S2A
S2B
VS
D2
Output
CL
tProp Delay = max ( tPD 1, tPD 2)
RL
GND
图7-8. Propagation Delay Measurement Setup
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7.9 Charge Injection
The TMUX6236 has a transmission-gate topology. Any mismatch in capacitance between the NMOS and PMOS
transistors results in a charge injected into the drain or source during the falling or rising edge of the gate signal.
The amount of charge injected into the source or drain of the device is known as charge injection, and is
denoted by the symbol QINJ. 图 7-9 shows the setup used to measure charge injection from source (Sx) to drain
(D).
VDD
VSS
0.1 µF
0.1 µF
3 V
VEN
VDD
S1A
VSS
tr < 20 ns
tf < 20 ns
VS
D1 Output
CL
0 V
S1B
N.C.
Output
VD
VOUT
QINJ = CL
×
VOUT
S2A
S2B
VS
D2 Output
CL
N.C.
EN
VEN
GND
图7-9. Charge-Injection Measurement Setup
7.10 Off Isolation
Off isolation is defined as the ratio of the signal at the drain pin (D) of the device when a signal is applied to the
source pin (Sx) of an off-channel. 图 7-10 shows the setup used to measure, and the equation used to calculate
off isolation.
VDD
VSS
0.1 µF
0.1 µF
VDD
VSS
Network Analyzer
VS
S
D
50
VOUT
VSIG
50
SxA / SxB / Dx
GND
50
图7-10. Off Isolation Measurement Setup
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7.11 Crosstalk
Crosstalk is defined as the ratio of the signal at the drain pin (D) of a different channel, when a signal is applied
at the source pin (Sx) of an on-channel. 图 7-11 shows the setup used to measure and the equation used to
calculate crosstalk.
VDD
VSS
0.1 µF
0.1 µF
VDD
VSS
Network Analyzer
VS
S1A
S2A
D
50
VOUT
50
VSIG
50
SxA / SxB / Dx
GND
50
图7-11. Crosstalk Measurement Setup
7.12 Bandwidth
Bandwidth is defined as the range of frequencies that are attenuated by less than 3 dB when the input is applied
to the source pin (Sx) of an on-channel, and the output is measured at the drain pin (D) of the device. 图 7-12
shows the setup used to measure bandwidth.
VDD
VSS
0.1 µF
0.1 µF
VDD
VSS
Network Analyzer
VS
S
D
50
VOUT
VSIG
50
SxA / SxB / Dx
GND
50
图7-12. Bandwidth Measurement Setup
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7.13 THD + Noise
The total harmonic distortion (THD) of a signal is a measurement of the harmonic distortion, and is defined as
the ratio of the sum of the powers of all harmonic components to the power of the fundamental frequency at the
mux output. The on-resistance of the device varies with the amplitude of the input signal and results in distortion
when the drain pin is connected to a low-impedance load. Total harmonic distortion plus noise is denoted as
THD.
VDD
VSS
0.1 µF
0.1 µF
VDD
VSS
Audio Precision
S
D
40
VOUT
VS
RL
SxA / SxB / Dx
GND
50
图7-13. THD Measurement Setup
7.14 Power Supply Rejection Ratio (PSRR)
PSRR measures the ability of a device to prevent noise and spurious signals that appear on the supply voltage
pin from coupling to the output of the switch. The DC voltage on the device supply is modulated by a sine wave
of 620 mVPP. The ratio of the amplitude of signal on the output to the amplitude of the modulated signal is the
ACPSRR. A high ratio represents a high degree of tolerance to supply rail variation.
图 7-14 shows how the decoupling capacitors reduce high frequency noise on the supply pins. This helps
stabilize the supply and immediately filter as much of the supply noise as possible.
VDD
Network Analyzer
VSS
DC Bias
Injector
With & Without
Capacitor
50 Ω
0.1 µF
0.1 µF
VDD
VSS
620 mVPP
VIN
S
VBIAS
50 Ω
SxA / SxB / Dx
50 Ω
VOUT
D
RL
GND
CL
图7-14. ACPSRR Measurement Setup
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8 Detailed Description
8.1 Functional Block Diagram
The TMUX6236 is a 2:1, 2-channel multiplexer or demultiplexer. Each input is turned on or turned off based on
the state of the select and enable pins.
VSS
VDD
S1A
S1B
S2A
S2B
D1
D2
SEL1
SEL2
Logic
Decoder
EN
8.2 Feature Description
8.2.1 Bidirectional Operation
The TMUX6236 conducts equally well from source (Sx) to drain (Dx) or from drain (Dx) to source (Sx). Each
channel has very similar characteristics in both directions and supports both analog and digital signals.
8.2.2 Rail to Rail Operation
The valid signal path input or output voltage for TMUX6236 ranges from VSS to VDD
.
8.2.3 1.8 V Logic Compatible Inputs
The TMUX6236 has 1.8-V logic compatible control for all logic control inputs. 1.8-V logic level inputs allows the
TMUX6236 to interface with processors that have lower logic I/O rails and eliminates the need for an external
translator, which saves both space and bill of materials (BOM) cost. For more information on 1.8 V logic
implementations, refer to Simplifying Design with 1.8 V logic Muxes and Switches.
8.2.4 Integrated Pull-Down Resistor on Logic Pins
The TMUX6236 has internal weak pull-down resistors to GND to ensure the logic pins are not left floating. The
value of this pull-down resistor is approximately 4 MΩ, but is clamped to about 1 µA at higher voltages. This
feature integrates up to three external components and reduces system size and cost.
8.2.5 Fail-Safe Logic
The TMUX6236 supports Fail-Safe Logic on the control input pins (EN and SEL) allowing for operation up to 36
V above VSS, regardless of the state of the supply pins. This feature allows voltages on the control pins to be
applied before the supply pin, protecting the device from potential damage. Fail-Safe Logic minimizes system
complexity by removing the need for power supply sequencing on the logic control pins. For example, the Fail-
Safe Logic feature allows the logic input pins of the TMUX6236 to be ramped to +36 V while VDD and VSS = 0 V.
The logic control inputs are protected against positive faults of up to +36 V in the powered-off condition, but does
not offer protection against negative overvoltage conditions.
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8.2.6 Latch-Up Immune
Latch-up is a condition where a low impedance path is created between a supply pin and ground. This condition
is caused by a trigger (current injection or overvoltage), but once activated, the low impedance path remains
even after the trigger is no longer present. This low impedance path may cause system upset or catastrophic
damage due to excessive current levels. The latch-up condition typically requires a power cycle to eliminate the
low impedance path.
The TMUX6236 is constructed on silicon on insulator (SOI) based process where an oxide layer is added
between the PMOS and NMOS transistor of each CMOS switch to prevent parasitic structures from forming. The
oxide layer is also known as an insulating trench and prevents triggering of latch up events due to overvoltage or
current injections. The latch-up immunity feature allows the TMUX6236 to be used in harsh environments. For
more information on latch-up immunity refer to Using Latch Up Immune Multiplexers to Help Improve System
Reliability.
8.2.7 Ultra-Low Charge Injection
图 8-1 shows how the TMUX6236 device has a transmission gate topology. Any mismatch in the stray
capacitance associated with the NMOS and PMOS causes an output level change whenever the switch is
opened or closed.
OFF ON
CGDN
CGSN
D
S
CGSP
CGDP
OFF ON
图8-1. Transmission Gate Topology
The TMUX6236 contains specialized architecture to reduce charge injection on the Drain (Dx). To further reduce
charge injection in a sensitive application, a compensation capacitor (Cp) can be added on the Source (Sx). This
will ensure that excess charge from the switch transition will be pushed into the compensation capacitor on the
Source (Sx) instead of the Drain (Dx). As a general rule, Cp should be 20x larger than the equivalent load
capacitance on the Drain (Dx). 图8-2 shows charge injection variation with different compensation capacitors on
the Source side. This plot was captured on the TMUX6219 as part of the TMUX62xx family with a 100 pF load
capacitance.
图8-2. Charge Injection Compensation
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8.3 Device Functional Modes
When the EN pin of the TMUX6236 is pulled high, one of the switches is closed based on the state of the SEL
pin. When the EN pin is pulled low, both of the switches are in an open state regardless of the state of the SEL
pin. The control pins can be as high as 36 V.
8.4 Truth Tables
表8-1 provides the truth tables for the TMUX6236.
表8-1. TMUX6236 Truth Table
EN SELx
Selected Input Connected To Drain (D) Pin
0
1
1
X(1)
All channels are off (Hi-Z)
0
SxB
SxA
1
(1) X denotes do not care.
9 Application and Implementation
备注
Information in the following applications sections is not part of the TI component specification, and TI
does not warrant its accuracy or completeness. TI’s customers are responsible for determining
suitability of components for their purposes. Customers should validate and test their design
implementation to confirm system functionality.
9.1 Application Information
The TMUX6236 is part of the precision switches and multiplexers family of devices. This device operates with
dual supplies (±4.5 V to ±18 V), a single supply (4.5 V and 36 V), or asymmetric supplies (such as, VDD = 5 V
and VSS = −8 V), and offers rail-to-rail input and output. The TMUX6236 offers low RON, low on and off leakage
currents and ultra-low charge injection performance. These features make the TMUX6236 a precision, robust,
high-performance analog multiplexer for high-voltage, industrial applications.
9.2 Typical Application
Differential reference signal switching is one application for the TMUX6236. AC reference signals are utilized in a
variety of use cases as a stable reference in signal processing. Often times a differential signal is needed to
reduce noise and keep signal integrity. To easily swap the direction and frequency of this reference signal, a 2:1,
2 channel precision multiplexer like the TMUX6236 can be used. 图 9-1 shows a circuit example utilizing the
TMUX6236 to control the AC reference signals. The switch can easily be configured for a differential signal on
either X1 or X2. Additionally, if both SEL pins are low, then the output will be set to ground to ensure there is no
active operation and reduce power consumption. The break-before-make feature allows transferring of a signal
from one port to another, without shorting the inputs together. This device also offers low charge injection, which
makes this device suitable for high precision systems.
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15 V -15 V
–
+
X1
–
S1A
S1B
F1
D1
D2
+
Vref
Vref
1.8 V
MCU
MCU
–
+
X2
–
S2A
S2B
F2
+
1.8 V
图9-1. Differential Reference Switching
9.2.1 Design Requirements
For this design example, use the parameters listed in 表9-1.
表9-1. Design Parameters
PARAMETERS
Supply (VDD
Supply (VSS
VALUES
)
15 V
−15 V
)
MUX I/O signal range
Control logic thresholds
EN
−15 V to 15 V (Rail-to-Rail)
1.8 V compatiable (up to VDD
)
EN pulled high to enable the switch
9.2.2 Detailed Design Procedure
The TMUX6236 can operate without any external components except for the supply decoupling capacitors. All
inputs passing through the switch must fall within the recommended operating conditions of the TMUX6236,
including signal range and continuous current. The signal range for this design can be −15 V to +15 V and the
maximum continuous current can be up to 330 mA for wide-range current measurement with a positive supply of
15 V on VDD and negative supply of −15 V on VSS (for more information, see 节6.4). The TMUX6236 device are
bidirectional, single-pole double-throw (SPDT) switches that offer low on-resistance, low leakage, and low power.
These features make these devices suitable for precision and power sensitive applications.
9.2.3 Application Curve
The low on-resistance of TMUX6236 and ultra-low charge injection performance make this device ideal for
implementing high precision industrial systems. The TMUX6236 contains specialized architecture to reduce
charge injection on the Drain side (D) (for more details, see 节 8.2.7). 图 9-2 shows the plot for the charge
injection versus source voltage for the TMUX6236.
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130
100
70
VDD = 5 V, VSS = -5 V
VDD = 15 V, VSS = -15 V
40
10
-20
-50
-15
-10
-5
0
5
10
15
VD - Drain Voltage (V)
TA = 25°C
图9-2. Charge Injection vs Drain Voltage
10 Power Supply Recommendations
The TMUX6236 operates across a wide supply range of ±4.5 V to ±18 V (4.5 V to 36 V in single-supply mode).
The device also performs well with asymmetrical supplies such as VDD = 12 V and VSS= –5 V.
Power-supply bypassing improves noise margin and prevents switching noise propagation from the supply rails
to other components. Good power-supply decoupling is important to achieve optimum performance. For
improved supply noise immunity, use a supply decoupling capacitor ranging from 0.1 μF to 10 μF at both the
VDD and VSS pins to ground. Place the bypass capacitors as close to the power supply pins of the device as
possible using low-impedance connections. TI recommends using multi-layer ceramic chip capacitors (MLCCs)
that offer low equivalent series resistance (ESR) and inductance (ESL) characteristics for power-supply
decoupling purposes. For very sensitive systems or systems in harsh noise environments, avoiding the use of
vias for connecting the capacitors to the device pins may offer superior noise immunity. The use of multiple vias
in parallel lowers the overall inductance and is beneficial for connections to ground planes. Always ensure the
ground (GND) connection is established before supplies are ramped.
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11 Layout
11.1 Layout Guidelines
When a PCB trace turns a corner at a 90° angle, a reflection can occur. A reflection occurs primarily because of
the change of width of the trace. At the apex of the turn, the trace width increases to 1.414 times the width. This
increase upsets the transmission-line characteristics, especially the distributed capacitance and self–inductance
of the trace which results in the reflection. Not all PCB traces can be straight and therefore some traces must
turn corners. 图 11-1 shows progressively better techniques of rounding corners. Only the last example (BEST)
maintains constant trace width and minimizes reflections.
WORST
BETTER
BEST
2W
1W min.
W
图11-1. Trace Example
Route high-speed signals using a minimum of vias and corners which reduces signal reflections and impedance
changes. When a via must be used, increase the clearance size around it to minimize its capacitance. Each via
introduces discontinuities in the signal’s transmission line and increases the chance of picking up interference
from the other layers of the board. Be careful when designing test points; through-hole pins are not
recommended at high frequencies.
Some key considerations are:
• For reliable operation, connect a decoupling capacitor ranging from 0.1 µF to 10 µF between VDD/VSS and
GND. TI recommends a 0.1-µF and 1 µF capacitor, placing the lowest value capacitor as close to the pin as
possible. Make sure that the capacitor voltage rating is sufficient for the supply voltage.
• Keep the input lines as short as possible.
• Use a solid ground plane to help reduce electromagnetic interference (EMI) noise pickup.
• Do not run sensitive analog traces in parallel with digital traces. Avoid crossing digital and analog traces if
possible, and only make perpendicular crossings when necessary.
• Using multiple vias in parallel will lower the overall inductance and is beneficial for connection to ground
planes.
11.2 Layout Example
Wide (low inductance)
trace for power
EN
VDD
S2B
D2
D1
S1B
VSS
GND
Wide (low inductance)
trace for power
Via to ground plane
图11-2. TMUX6236 Layout Example
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12 Device and Documentation Support
12.1 Documentation Support
12.1.1 Related Documentation
For related documenation, see the following:
• Texas Instruments, Eliminate Power Sequencing with Powered-off Protection Signal Switches application
brief
• Texas Instruments, Improve Stability Issues with Low CON Multiplexers application brief
• Texas Instruments, QFN/SON PCB Attachment application report
• Texas Instruments, Quad Flatpack No-Lead Logic Packages application report
• Texas Instruments, Simplifying Design with 1.8 V logic Muxes and Switches application brief
• Texas Instruments, System-Level Protection for High-Voltage Analog Multiplexers application reports
• Texas Instruments, True Differential, 4 x 2 MUX, Analog Front End, Simultaneous-Sampling ADC Circuit
circuit design
12.2 接收文档更新通知
要接收文档更新通知，请导航至 ti.com 上的器件产品文件夹。点击订阅更新 进行注册，即可每周接收产品信息更
改摘要。有关更改的详细信息，请查看任何已修订文档中包含的修订历史记录。
12.3 支持资源
TI E2E™ 支持论坛是工程师的重要参考资料，可直接从专家获得快速、经过验证的解答和设计帮助。搜索现有解
答或提出自己的问题可获得所需的快速设计帮助。
链接的内容由各个贡献者“按原样”提供。这些内容并不构成 TI 技术规范，并且不一定反映 TI 的观点；请参阅
TI 的《使用条款》。
12.4 Trademarks
TI E2E™ is a trademark of Texas Instruments.
所有商标均为其各自所有者的财产。
12.5 术语表
TI 术语表
本术语表列出并解释了术语、首字母缩略词和定义。
12.6 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled
with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may
be more susceptible to damage because very small parametric changes could cause the device not to meet its published
specifications.
13 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
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PACKAGE OPTION ADDENDUM
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7-Oct-2022
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
TMUX6236RUMR
ACTIVE
WQFN
RUM
16
3000 RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
TMUX
T236
Samples
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
9-Sep-2022
TAPE AND REEL INFORMATION
REEL DIMENSIONS
TAPE DIMENSIONS
K0
P1
W
B0
Reel
Diameter
Cavity
A0
A0 Dimension designed to accommodate the component width
B0 Dimension designed to accommodate the component length
K0 Dimension designed to accommodate the component thickness
Overall width of the carrier tape
W
P1 Pitch between successive cavity centers
Reel Width (W1)
QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE
Sprocket Holes
Q1 Q2
Q3 Q4
Q1 Q2
Q3 Q4
User Direction of Feed
Pocket Quadrants
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
TMUX6236RUMR
WQFN
RUM
16
3000
330.0
12.4
4.25
4.25
1.15
8.0
12.0
Q2
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
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9-Sep-2022
TAPE AND REEL BOX DIMENSIONS
Width (mm)
H
W
L
*All dimensions are nominal
Device
Package Type Package Drawing Pins
WQFN RUM 16
SPQ
Length (mm) Width (mm) Height (mm)
367.0 367.0 35.0
TMUX6236RUMR
3000
Pack Materials-Page 2
GENERIC PACKAGE VIEW
RUM 16
4 x 4, 0.65 mm pitch
WQFN - 0.8 mm max height
PLASTIC QUAD FLATPACK - NO LEAD
This image is a representation of the package family, actual package may vary.
Refer to the product data sheet for package details.
4224843/A
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PACKAGE OUTLINE
RUM0016E
WQFN - 0.8 mm max height
S
C
A
L
E
3
.
0
0
0
PLASTIC QUAD FLATPACK - NO LEAD
4.1
3.9
A
B
PIN 1 INDEX AREA
4.1
3.9
0.8
0.7
C
SEATING PLANE
0.08 C
0.05
0.00
2X 1.95
SYMM
(0.2) TYP
5
8
EXPOSED
THERMAL PAD
4
9
2X 1.95
SYMM
17
2.5 0.1
12X 0.65
1
12
0.35
16X
PIN 1 ID
0.25
13
16
0.1
C A B
0.5
0.3
0.05
16X
4224815/A 02/2019
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. The package thermal pad must be soldered to the printed circuit board for thermal and mechanical performance.
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EXAMPLE BOARD LAYOUT
RUM0016E
WQFN - 0.8 mm max height
PLASTIC QUAD FLATPACK - NO LEAD
(
2.5)
SYMM
SEE SOLDER MASK
DETAIL
13
16
16X (0.6)
1
12
16X (0.3)
17
SYMM
12X (0.65)
(3.8)
(1)
4
9
(R0.05) TYP
(
0.2) TYP
VIA
5
8
(1)
(3.8)
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE: 20X
0.07 MIN
ALL AROUND
0.07 MAX
ALL AROUND
METAL UNDER
SOLDER MASK
METAL EDGE
EXPOSED METAL
SOLDER MASK
OPENING
EXPOSED
METAL
SOLDER MASK
OPENING
NON SOLDER MASK
SOLDER MASK DEFINED
DEFINED
(PREFERRED)
SOLDER MASK DETAILS
4224815/A 02/2019
NOTES: (continued)
4. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature
number SLUA271 (www.ti.com/lit/slua271).
5. Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to their locations shown
on this view. It is recommended that vias under paste be filled, plugged or tented.
www.ti.com
EXAMPLE STENCIL DESIGN
RUM0016E
WQFN - 0.8 mm max height
PLASTIC QUAD FLATPACK - NO LEAD
(0.65) TYP
13
16
16X (0.6)
1
12
16X (0.3)
(0.65) TYP
(3.8)
17
SYMM
12X (0.65)
4X ( 1.1)
9
4
(R0.05) TYP
8
5
SYMM
(3.8)
SOLDER PASTE EXAMPLE
BASED ON 0.125 MM THICK STENCIL
SCALE: 20X
EXPOSED PAD 17
77% PRINTED SOLDER COVERAGE BY AREA UNDER PACKAGE
4224815/A 02/2019
NOTES: (continued)
6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
www.ti.com
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Copyright © 2022，德州仪器 (TI) 公司
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