TMUX1511PWR [TI]
具有断电保护功能和 1.8V 输入逻辑的 5V、1:1 (SPST)、4 通道模拟开关 | PW | 14 | -40 to 125;
| 型号： | TMUX1511PWR |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 具有断电保护功能和 1.8V 输入逻辑的 5V、1:1 (SPST)、4 通道模拟开关 | PW | 14 | -40 to 125 开关 光电二极管 输出元件 |
| 文件： | 总36页 (文件大小：1720K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
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TMUX1511
ZHCSIR9A –SEPTEMBER 2018–REVISED DECEMBER 2018
具有1.8V 逻辑的 TMUX1511 低电容、1:1 (SPST) 4 通道
关断保护开关
1 特性
3 说明
1
•
宽电源电压范围：1.5V 至 5.5V
低导通电容：3.3pF
TMUX1511 是一款互补金属氧化物半导体 (CMOS) 开
关。TMUX1511 提供具有 4 个独立控制通道的 1:1
SPST 开关配置。1.5V 至 5.5V 的宽运行电源电压范围
使其 可用于从服务器和通信设备到工业应用的各种 应
用的需求。该器件可在源极 (Sx) 和漏极 (Dx) 引脚上支
持双向模拟和数字信号，并且可以传递高于电源的信号
（高达 VDD x 2），最大输入/输出电压为 5.5V。
•
•
•
•
•
•
•
•
•
•
低导通电阻：2Ω
高带宽：3GHz
-40°C 至 +125°C 运行温度
兼容 1.8V 逻辑
支持超出电源的输入电压
逻辑引脚上的集成下拉电阻器
双向信号路径
TMUX1511 的信号路径上高达 3.6V 的关断保护可在
移除电源电压 (VDD = 0V) 时提供隔离。如果没有该保
护功能，开关可通过内部 ESD 二极管为电源轨进行反
向供电，从而对系统造成潜在损坏。
失效防护逻辑
关断保护 高达 3.6V
–
–
与 SN74CBTLV3126 引脚兼容
失效防护逻辑 电路允许在施加电源引脚上的电压之
前，先施加逻辑控制引脚上的电压，从而保护器件免受
潜在的损害。所有逻辑控制输入都具有 兼容 1.8V 逻辑
的阈值，当器件在有效电源电压范围内运行时，这些阈
值可确保 TTL 和 CMOS 逻辑兼容性。
与 SN74CBTLV3125 引脚兼容（逻辑型号）
2 应用
•
•
•
•
•
•
•
•
•
•
•
•
服务器
有线网络
无线基础设施
数据中心交换机和路由器
PC/笔记本电脑
楼宇自动化
ePOS
器件信息(1)
器件型号
TMUX1511
封装
TSSOP (14)
QFN (16)
封装尺寸（标称值）
5.00mm × 4.40mm
2.60mm x 1.80mm
(1) 如需了解所有可用封装，请参阅产品数据表末尾的封装选项附
录。
电机驱动器
电器
电池供电类设备
JTAG 隔离
SPI 隔离
应用示例
方框图
VDD
VI/O
TMUX1511
VDD
0.1µF
SEL1
S1
SEL4
S4
Processor
JTAG, SPI, GPIO
Port
FLASH
TDI / MISO / GPIO
TDO / MOSI / GPIO
TCK / SCLK / GPIO
TMS / SS / GPIO
S1
S2
S3
S4
D1
D2
D3
D4
JTAG
DEBUG,
D1
D4
RAM
CPU
SPI, GPIO
SEL2
S2
SEL3
S3
SEL1
SEL2
SEL3
SEL4
1.8V Logic
I/O
Peripherals
D2
D3
GND
GND
*Internal 6MO Pull-Down on Logic Pins
1
本文档旨在为方便起见，提供有关 TI 产品中文版本的信息，以确认产品的概要。 有关适用的官方英文版本的最新信息，请访问 www.ti.com，其内容始终优先。 TI 不保证翻译的准确
性和有效性。 在实际设计之前，请务必参考最新版本的英文版本。
English Data Sheet: SCDS390
TMUX1511
ZHCSIR9A –SEPTEMBER 2018–REVISED DECEMBER 2018
www.ti.com.cn
目录
7.11 Off Isolation........................................................... 17
7.12 Channel-to-Channel Crosstalk.............................. 17
7.13 Bandwidth ............................................................. 18
Detailed Description ............................................ 19
8.1 Overview ................................................................. 19
8.2 Functional Block Diagram ....................................... 19
8.3 Feature Description................................................. 19
8.4 Device Functional Modes........................................ 20
8.5 Truth Tables............................................................ 20
Application and Implementation ........................ 21
9.1 Application Information............................................ 21
9.2 Typical Application ................................................. 21
1
2
3
4
5
6
特性.......................................................................... 1
应用.......................................................................... 1
说明.......................................................................... 1
修订历史记录 ........................................................... 2
Pin Configuration and Functions......................... 3
Specifications......................................................... 4
6.1 Absolute Maximum Ratings ...................................... 4
6.2 ESD Ratings.............................................................. 4
6.3 Recommended Operating Conditions....................... 4
6.4 Thermal Information.................................................. 4
6.5 Electrical Characteristics........................................... 5
6.6 Dynamic Characteristics ........................................... 6
6.7 Timing Requirements................................................ 6
6.8 Typical Characteristics.............................................. 7
Parameter Measurement Information ................ 12
7.1 On-Resistance ........................................................ 12
7.2 Off-Leakage Current ............................................... 12
7.3 On-Leakage Current ............................................... 13
7.4 IPOFF Leakage Current.......................................... 13
7.5 Transition Time ....................................................... 14
7.6 TON (VDD) and TOFF (VDD) Time ................................ 14
7.7 Propagation Delay................................................... 15
7.8 Skew ....................................................................... 15
7.9 Charge Injection...................................................... 16
7.10 Capacitance .......................................................... 16
8
9
10 Power Supply Recommendations ..................... 23
11 Layout................................................................... 24
11.1 Layout Guidelines ................................................. 24
11.2 Layout Example .................................................... 25
12 器件和文档支持 ..................................................... 26
12.1 文档支持................................................................ 26
12.2 接收文档更新通知 ................................................. 26
12.3 社区资源................................................................ 26
12.4 商标....................................................................... 26
12.5 静电放电警告......................................................... 26
12.6 术语表 ................................................................... 26
13 机械、封装和可订购信息....................................... 26
7
4 修订历史记录
注：之前版本的页码可能与当前版本有所不同。
Changes from Original (September 2018) to Revision A
Page
•
更改了产品说明书状态：将“预告信息”更改成了“生产数据”..................................................................................................... 1
2
Copyright © 2018, Texas Instruments Incorporated
TMUX1511
www.ti.com.cn
ZHCSIR9A –SEPTEMBER 2018–REVISED DECEMBER 2018
5 Pin Configuration and Functions
PW Package
14-Pin TSSOP
Top View
RSV Package
16-Pin QFN
Top View
SEL1
S1
1
2
3
4
5
6
7
14
13
12
11
10
9
VDD
SEL4
S4
D1
SEL1
S1
1
12
11
10
9
N.C.
SEL3
S3
SEL2
S2
D4
SEL3
S3
2
3
4
D2
D1
GND
8
D3
SEL2
D3
Not to scale
Not to scale
Pin Functions
PIN
TYPE(1)
DESCRIPTION
NAME
TSSOP
UQFN
Select pin 1: controls state of switch #1 (logic low = OFF, logic high = ON). Internal 6 MΩ
pull-down to GND.
SEL1
1
1
I
S1
D1
2
3
2
3
I/O
I/O
Source pin 1. Can be an input or output.
Drain pin 1. Can be an input or output.
Select pin 2: controls state of switch #2 (logic low = OFF, logic high = ON). Internal 6 MΩ
pull-down to GND.
SEL2
4
4
I
S2
5
6
-
5
6
I/O
Source pin 2. Can be an input or output.
Drain pin 2. Can be an input or output.
Not Connected - Can be shorted to GND or left floating
Ground (0 V) reference
D2
I/O
N.C.
GND
D3
7
Not Connected
7
8
9
8
P
9
I/O
I/O
Drain pin 3. Can be an input or output.
Source pin 3. Can be an input or output.
S3
10
Select pin 3: controls state of switch #3 (logic low = OFF, logic high = ON). Internal 6 MΩ
pull-down to GND.
SEL3
10
11
I
N.C.
D4
-
12
13
14
Not Connected
Not Connected - Can be shorted to GND or left floating
Drain pin 4. Can be an input or output.
11
12
I/O
I/O
S4
Source pin 4. Can be an input or output.
Select pin 4: controls state of switch #4 (logic low = OFF, logic high = ON). Internal 6 MΩ
pull-down to GND.
SEL4
VDD
13
14
15
16
I
Positive power supply. This pin is the most positive power-supply potential. For reliable
operation, connect a decoupling capacitor ranging from 0.1 µF to 10 µF between VDD and
GND.
P
(1) I = input, O = output, I/O = input and output, P = power
Copyright © 2018, Texas Instruments Incorporated
3
TMUX1511
ZHCSIR9A –SEPTEMBER 2018–REVISED DECEMBER 2018
www.ti.com.cn
6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)(1)
(2) (3)
MIN
–0.5
–0.5
–30
–0.5
–25
–65
MAX
UNIT
V
VDD
Supply voltage
6
6
VSEL
Logic control input pin voltage (SEL1, SEL2, SEL3, SEL4)
Logic control input pin current (SEL1, SEL2, SEL3, SEL4)
Source or drain pin voltage
V
ISEL
30
6
mA
V
VS or VD
IS or ID (CONT)
Tstg
Source and drain pin continuous current: (S1 to S4, D1 to D4)
Storage temperature
25
150
150
mA
°C
°C
TJ
Junction temperature
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) The algebraic convention, whereby the most negative value is a minimum and the most positive value is a maximum.
(3) All voltages are with respect to ground, unless otherwise specified.
6.2 ESD Ratings
VALUE
UNIT
Human body model (HBM), per
ANSI/ESDA/JEDEC JS-001(1)
±2000
V(ESD)
Electrostatic discharge
V
Charged-device model (CDM), per JEDEC
specification JESD22-C101(2)
±750
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
6.3 Recommended Operating Conditions
MIN
MAX
5.5
UNIT
V
VDD
Supply voltage
1.5
0
VS or VD
VS_off or VD_off
VSEL
Signal path input/output voltage (source or drain pin), VDD ≥ 1.5 V(1)
Signal path input/output voltage (source or drain pin), VDD < 1.5 V(2)
Logic control input voltage (SELx)
VDD x 2
3.6
V
0
V
0
5.5
V
TA
Ambient temperature
–40
125
ºC
(1) Device input/output can operate up to VDD x 2, with a maximum input/output voltage of 5.5 V.
(2) VS_off and VD_off refers to the voltage at the source or drain pins when supply is less than 1.5 V
6.4 Thermal Information
DEVICE
DEVICE
RSV (UQFN)
16 PINS
141.5
THERMAL METRIC(1)
PW (TSSOP)
14 PINS
129.4
58.8
UNIT
RθJA
Junction-to-ambient thermal resistance
Junction-to-case (top) thermal resistance
Junction-to-board thermal resistance
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
RθJC(top)
RθJB
77.9
72.4
67.6
ΨJT
Junction-to-top characterization parameter
Junction-to-board characterization parameter
Junction-to-case (bottom) thermal resistance
11.6
5.1
ΨJB
71.9
65.5
RθJC(bot)
N/A
N/A
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
4
Copyright © 2018, Texas Instruments Incorporated
TMUX1511
www.ti.com.cn
ZHCSIR9A –SEPTEMBER 2018–REVISED DECEMBER 2018
6.5 Electrical Characteristics
VDD = 1.5 V to 5.5 V, GND = 0 V, TA = –40°C to +125°C,
Typical values are at VDD = 3.3 V, TA = 25°C, (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
POWER SUPPLY
VDD
Power supply voltage
1.5
5.5
70
V
VSEL = 0 V, 1.4 V or VDD
VS = 0 V to 5.5 V
IDD
Supply current
37
μA
DC CHARACTERISTICS
VS = 0 V to VDD*2
VS(max) = 5.5 V
ISD = 8 mA
RON
On-resistance
2
4.5
Ω
Refer to ON-State Resistance Figure
VS = VDD
ΔRON
On-resistance match between channels
On-resistance flatness
ISD = 8 mA
Refer to ON-State Resistance Figure
0.07
1
0.28
1.8
Ω
Ω
VS = 0 V to VDD
ISD = 8 mA
Refer to ON-State Resistance Figure
RON
(FLAT)
VDD = 0 V
VS = 0 V to 3 V
VD = 0 V
IPOFF
Powered-off I/O pin leakage current
–10
0.01
10
nA
TA = 25℃
Refer to Ipoff Leakage Figure
VDD = 0 V
VS = 0 V to 3.6 V
VD = 0 V
Refer to Ipoff Leakage Figure
IPOFF
Powered-off I/O pin leakage current
OFF leakage current
–2
0.01
0.03
2
µA
nA
Switch Off
IS(OFF)
ID(OFF)
VD = 0.8*VDD / 0.2*VDD
VS = 0.2*VDD / 0.8*VDD
Refer to Off Leakage Figure
–100
100
Switch On
VD = 0.8*VDD / 0.2*VDD, S pins floating
or
VS = 0.8*VDD / 0.2*VDD, D pins floating
Refer to On Leakage Figure
ID(ON)
IS(ON)
ON leakage current
–50
0.01
50
nA
LOGIC INPUTS
VIH
VIL
IIH
Input logic high
1.2
0
5.5
0.45
±2
V
V
Input logic low
Input high leakage current
Input low leakage current
VSEL = 1.8 V, VDD
VSEL = 0 V
1
μA
μA
IIL
0.2
±2
Internal pull-down resistor on logic input
pins
RPD
CI
6
3
MΩ
VSEL = 0 V, 1.8 V or VDD
f = 1 MHz
Logic input capacitance
pF
Copyright © 2018, Texas Instruments Incorporated
5
TMUX1511
ZHCSIR9A –SEPTEMBER 2018–REVISED DECEMBER 2018
www.ti.com.cn
6.6 Dynamic Characteristics
VDD = 1.5 V to 5.5 V, GND = 0 V, TA = –40°C to +125°C,
Typical values are at VDD = 3.3 V, TA = 25°C, (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX UNIT
VS = VDD / 2
VSEL= 0 V
f = 1 MHz
Refer to Capacitance Figure
Switch
OFF
COFF
Source and drain off capacitance
2.5
4
6
pF
pF
VS = VDD / 2
VSEL = VDD
f = 1 MHz
Refer to Capacitance Figure
Switch
ON
CON
Source and drain on capacitance
Charge Injection
3.3
VS = VDD / 2
RS = 0 Ω, CL = 100 pF
Refer to Charge Injection Figure
Switch
ON
QC
2
–90
–75
pC
dB
dB
RL = 50 Ω
f = 100 kHz
Refer to Off Isolation Figure
Switch
OFF
OISO
Off isolation
RL = 50 Ω
f = 1 MHz
Refer to Off Isolation Figure
Switch
OFF
RL = 50 Ω
f = 100 kHz
Refer to Crosstalk Figure
Switch
ON
XTALK
BW
Channel to Channel crosstalk
Bandwidth
–90
3
dB
GHz
dB
RL = 50 Ω
Refer to Bandwidth Figure
Switch
ON
RL = 50 Ω
f = 1 MHz
Refer to Bandwidth Figure
Switch
ON
ILOSS
Insertion loss
–0.12
6.7 Timing Requirements
VDD = 1.5 V to 5.5 V, GND = 0 V, TA = –40°C to +125°C,
Typical values are at VDD = 3.3 V, TA = 25°C, (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
VS = 3.6 V
VDD rise time = 1us
RL = 200 Ω, CL = 15pF
Refer to Ton(vdd) & Toff(vdd) Figure
tON(VDD) Device turn on time (VDD to output)
20
60
4
µs
VS = 3.6 V
VDD fall time = 1us
RL = 200 Ω, CL = 15pF
Refer to Ton(vdd) & Toff(vdd) Figure
tOFF(VDD) Device turn off time (VDD to output)
1.2
25
50
µs
ns
ns
VDD = 2.5 V to 5.5 V
VS = VDD
RL = 200 Ω, CL = 15pF
Refer to Transition Time Figure
tTRAN
Transition time from control input
Transition time from control input
55
80
VDD < 2.5 V
VS = VDD
RL = 200 Ω, CL = 15pF
Refer to Transition Time Figure
tTRAN
tSK(P)
tPD
Inter - channel skew
Propagation delay
Refer to Tsk Figure
Refer to Tpd Figure
10
67
ps
ps
6
版权 © 2018, Texas Instruments Incorporated
TMUX1511
www.ti.com.cn
ZHCSIR9A –SEPTEMBER 2018–REVISED DECEMBER 2018
6.8 Typical Characteristics
at TA = 25°C, VDD = 5 V (unless otherwise noted)
5
4
3
5
4
3
2
1
0
TA = 125èC
TA = 85èC
VDD = 1.5 V
VDD = 5.5 V
2
1
TA = 25èC
TA = -40èC
VDD = 3.3 V
0
0
1
2
3
4
5
5.5
0
1
2
3
4
5
5.5
Source or Drain Voltage (V)
Source or Drain Voltage (V)
D001
D002
TA = 25°C
VDD = 5.5 V
图 1. On-Resistance vs Source or Drain Voltage
图 2. On-Resistance vs Source or Drain Voltage
4
3
2
1
0
4
3
2
1
0
TA = 85èC
TA = 125èC
TA = 85èC
TA = 125èC
TA = 25èC
TA = -40èC
TA = 25èC
TA = -40èC
1.5
0
0.5
1
2
2.5
3
3.5
0
0.5
1
1.5
Source or Drain Voltage (V)
Source or Drain Voltage (V)
D003
D004
VDD = 3.3 V
VDD = 1.5 V
图 3. On-Resistance vs Source or Drain Voltage
图 4. On-Resistance vs Source or Drain Voltage
70
65
60
55
50
45
40
35
30
60
55
50
45
40
35
30
TA = 125èC
TA = 85èC
VDD = 3.3 V
VDD = 5.5 V
TA = 25èC
VDD = 1.5 V
TA = -40èC
2.5
0
0.5
1
1.5
2
2.5
3
3.5
4
4.5
5
5.5
1.5
2
3
3.5
4
4.5
5
5.5
6
Logic Voltage (V)
D005
Supply Voltage (V)
D006
TA = 25°C
图 5. Supply Current vs Logic Voltage
图 6. Supply Current vs Supply Voltage
版权 © 2018, Texas Instruments Incorporated
7
TMUX1511
ZHCSIR9A –SEPTEMBER 2018–REVISED DECEMBER 2018
www.ti.com.cn
Typical Characteristics (接下页)
10
30
25
20
15
10
5
VDD = 5.5 V
VDD = 3.3 V
VDD = 1.5 V
8
6
VDD = 5.5 V
4
2
0
-2
-4
-6
-8
-10
VDD = 3.3 V
VDD = 1.5 V
0
-50
-25
0
25
50
75
100
125
150
0
0.5
1
1.5
2
2.5
3
3.5
4
4.5
5
5.5
Temperature (èC)
D008
Source or Drain Voltage (V)
D007
TA = 25°C
图 8. On-Leakage vs Temperature
图 7. On-Leakage vs Source or Drain Voltage
0.1
0.05
0
0.9
0.8
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0
VDD = 5.5 V
VDD = 3.3 V
VDD = 1.5 V
-0.05
-0.1
-0.15
VDD = 5.5 V
VDD = 3.3 V
VDD = 1.5 V
-0.1
-40
-20
0
20
40
60
80
100 120 140
0
1
2
3
4
5
Temperature (èC)
D010
Source or Drain Voltage (V)
D009
TA = 25°C
图 10. Off-Leakage vs Temperature
图 9. Off-Leakage vs Source or Drain Voltage
1
0.9
0.8
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0
10
8
6
4
2
0
-2
0
0.5
1
1.5
2
2.5
3
3.5
4
-40 -30 -20 -10
0
10
20
30
40
50
60
Source or Drain Voltage (V)
Temperature (èC)
D011
D012
TA = 25°C
VSource = 3 V
图 11. IPOFF Leakage vs Source or Drain Voltage
图 12. IPOFF Leakage vs Temperature
8
版权 © 2018, Texas Instruments Incorporated
TMUX1511
www.ti.com.cn
ZHCSIR9A –SEPTEMBER 2018–REVISED DECEMBER 2018
Typical Characteristics (接下页)
700
600
500
400
300
200
100
0
-100
-40
-20
0
20
40
60
80
100 120 140
Temperature (èC)
D013
TA = 25°C
VSource = 3.6 V
VDrain = 0 V
RL= 200 Ω
图 14. IPOFF Leakage vs Source or Drain Voltage
图 13. IPOFF Leakage vs Temperature
50
45
40
35
30
25
20
15
10
25
20
15
10
5
Transiton_Rising
Transiton_Falling
Transiton_Rising
Transiton_Falling
1.5
2
2.5
3
3.5
4
4.5
5
5.5
6
-40
-20
0
20
40
60
80
100 120 140
Supply Voltage (V)
Temperature (èC)
D015
D016
TA = 25°C
VDD = 5.5 V
图 15. TTRANSITION vs Supply Voltage
图 16. TTRANSITION vs Temperature
22.5
20
70
60
50
40
30
20
10
0
Propagation Delay
17.5
15
12.5
10
TON(VDD)
TOFF(VDD)
Skew
7.5
5
2.5
0
1.5
1.5
2
2.5
3
3.5
4
4.5
5
5.5
6
2
2.5
3
3.5
4
4.5
5
5.5
6
Supply Voltage (V)
D018
Supply Voltage (V)
D017
TA = 25°C
TA = 25°C
图 18. Skew and Propagation Delay vs Supply Voltage
图 17. TON (VDD) and TOFF (VDD) vs Supply Voltage
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Typical Characteristics (接下页)
10
9
8
6
4
2
0
COFF
CON
8
VDD = 5.5 V
7
6
VDD = 3.3 V
5
4
VDD = 1.5 V
3
2
1
0
0
1
2
3
4
5
6
1M
10M
100M
Frequency (Hz)
1G
Source Voltage (V)
D019
D020
TA = 25°C
TA = 25°C
图 20. Capacitance vs Frequency
图 19. Charge Injection vs Source or Drain Voltage
0
-10
-20
-30
-40
-50
-60
-70
-80
-90
-100
0
-1
-2
-3
-4
-5
-6
1M
10M
100M
1G
1M
10M
100M
1G
Frequency (Hz)
Frequency (Hz)
D021
D022
TA = 25°C
TA = 25°C
VDD = 1.5 V to 5.5 V
图 21. Off Isolation vs Frequency
图 22. On-Response vs Frequency
10
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6.8.1 Eye Diagrams
TA = 25°C
Bias = 1.5 V
TA = 25°C
Bias = 1.5 V
50 Ω Termination
50 Ω Termination
图 24. Eye Pattern: 2.4 Gbps Through Path
图 23. Eye Pattern: 2.4 Gbps
TA = 25°C
Bias = 1.5 V
TA = 25°C
Bias = 1.5 V
50 Ω Termination
50 Ω Termination
图 26. Eye Pattern: 3 Gbps Through Path
图 25. Eye Pattern: 3 Gbps
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7 Parameter Measurement Information
7.1 On-Resistance
The on-resistance of a device is the ohmic resistance between the source (Sx) and drain (Dx) pins of the device.
The on-resistance varies with input voltage and supply voltage. The symbol RON is used to denote on-resistance.
The measurement setup used to measure RON is shown in 图 27 . Voltage (V) and current (IDS) are measured
using this setup, and RON is computed as shown below with RON = V / ISD
:
V
ISD
Sx
Dx
VS
图 27. On-Resistance Measurement Setup
7.2 Off-Leakage Current
Source off-leakage current is defined as the leakage current flowing into or out of the source pin when the switch
is off. This current is denoted by the symbol IS(OFF)
.
Drain off-leakage current is defined as the leakage current flowing into or out of the drain pin when the switch is
off. This current is denoted by the symbol ID(OFF)
.
The setup used to measure both off-leakage currents is shown in 图 28.
VDD
VDD
VDD
VDD
IS (OFF)
A
ID (OFF)
A
S1
S4
D1
D4
D1
D4
S1
S4
VS
VD
VD
VS
IS (OFF)
A
ID (OFF)
A
VS
VD
VD
VS
GND
GND
图 28. Off-Leakage Measurement Setup
12
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7.3 On-Leakage Current
Source on-leakage current is defined as the leakage current flowing into or out of the source pin when the switch
is on. This current is denoted by the symbol IS(ON)
.
Drain on-leakage current is defined as the leakage current flowing into or out of the drain pin when the switch is
on. This current is denoted by the symbol ID(ON)
.
Either the source pin or drain pin is left floating during the measurement. 图 29 shows the circuit used for
measuring the on-leakage current, denoted by IS(ON) or ID(ON)
.
VDD
VDD
VDD
VDD
IS (ON)
A
ID (ON)
S1
S4
D1
D4
D1
D4
S1
S4
N.C.
N.C.
N.C.
N.C.
A
VS
VD
IS (ON)
A
ID (ON)
A
VS
VD
GND
GND
图 29. On-Leakage Measurement Setup
7.4 IPOFF Leakage Current
IPOFF leakage current is defined as the leakage current flowing into or out of the source pin when the device is
powered off. This current is denoted by the symbol IPOFF.
The setup used to measure both IPOFF leakage current is shown in 图 30.
VDD = 0 V
VDD
IPOFF
S1
S4
D1
D4
A
VS
VD
IPOFF
A
VS
VD
GND
图 30. IPOFF Leakage Measurement Setup
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7.5 Transition Time
Transition time is defined as the time taken by the output of the device to rise or fall 10% after the control select
signal has risen or fallen past the logic threshold. The 10% transition measurement is utilized to provide the
timing of the device. The time constant from the load resistance and load capacitance can be added to the
transition time to calculate system level timing. 图 31 shows the setup used to measure transition time, denoted
by the symbol tTRANSITION
.
VDD
0.1ꢀF
VDD
VDD
ADDRESS
DRIVE
tf < 5ns
tr < 5ns
VIH
(VSEL
)
VIL
OUTPUT
RL
S1
S4
D1
D4
0 V
VS
CL
tTRANSITION
tTRANSITION
OUTPUT
RL
VS
90%
CL
SEL1 - SEL4
GND
OUTPUT
0 V
VSEL
10%
图 31. Transition-Time Measurement Setup
7.6 TON (VDD) and TOFF (VDD) Time
TON (VDD) time is defined as the time taken by the output of the device to rise to 90% after the supply has risen
past the supply threshold. The 90% measurement is utilized to provide the timing of the device turning on in the
system. The time constant from the load resistance and load capacitance can be added to the turn-on-VDD time
to calculate system level timing. 图 32 shows the setup used to measure transition time, denoted by the symbol
tON (VDD)
.
TOFF (VDD) time is defined as the time taken by the output of the device to fall to 90% after the enable has fallen
past the supply threshold. The 90% measurement is utilized to provide the timing of the device turning off in the
system. The time constant from the load resistance and load capacitance can be added to the turn-off-VDD time
to calculate system level timing. 图 32 shows the setup used to measure transition time, denoted by the symbol
tOFF (VDD)
.
VDD
0.1ꢀF
VDD
VDD
VDD
Supply
Ramp
1.5 V
1.5 V
(VDD
)
OUTPUT
S1
S4
D1
D4
VS
0 V
CL
RL
tON
tOFF
(VDD)
(VDD)
90%
90%
OUTPUT
RL
VS
OUTPUT
0 V
CL
VDD
SEL1 - SEL4
GND
图 32. Turn-On-VDD and Turn-Off-VDD Time Measurement Setup
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7.7 Propagation Delay
Propagation delay is defined as the time taken by the output of the device to rise or fall 50% after the input signal
has risen or fallen past the 50% threshold. 图 33 shows the setup used to measure propagation delay, denoted
by the symbol tPD
.
VDD
0.1ꢁF
VDD
250 mV
Input
(VS)
50%
50%
OUTPUT
S1
S4
D1
D4
VS
0 V
RL
50ꢀ
tPD 1
tPD 2
OUTPUT
VS
RL
50ꢀ
Output
0 V
50%
50%
GND
tProp Delay = max ( tPD 1, tPD
)
2
图 33. Propagation Delay Measurement Setup
7.8 Skew
Skew is defined as the difference between propagation delays of any two outputs of the same device. The skew
measurement is taken from the output of one channel rising or falling past 50% to a second channel rising or
falling past the 50% threshold when the input signals are switched at the same time. 图 34 shows the setup used
to measure skew, denoted by the symbol tSK
.
VDD
0.1ꢁF
VDD
Output 1
50%
50%
OUTPUT
S1
S4
D1
D4
VS
0 V
RL
50ꢀ
tSK 1
tSK 2
OUTPUT
VS
RL
50ꢀ
Output 2
0 V
50%
50%
GND
tSKEW = max ( tSK 1, tSK
)
2
图 34. Skew Measurement Setup
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7.9 Charge Injection
The amount of charge injected into the source or drain of the device during the falling or rising edge of the gate
signal is known as charge injection, and is denoted by the symbol QC. 图 35 shows the setup used to measure
charge injection from source (Sx) to drain (Dx).
VDD
0.1ꢀF
VDD
VDD
VSEL
OUTPUT
S1
D1
D4
VOUT
CL
VS
0 V
Output
VS
OUTPUT
VOUT
S4
VOUT
CL
VS
QC = CL
×
VOUT
SEL1 - SEL4
VSEL
GND
图 35. Charge-Injection Measurement Setup
7.10 Capacitance
The parasitic capacitance of the device is captured at the source (Sx), drain (Dx), and select (SELx) pins. The
capacitance is measured in both the on and off state and is denoted by the symbol CON and COFF. 图 36 shows
the setup used to measure capacitance.
VDD
VDD
SEL1
S1
1 MHz
Capacitance
Capacitance is measured at SX, DX,
and SELX pins during ON and OFF
conditions
D1
Meter
SEL4
S4
D4
GND
图 36. Capacitance Measurement Setup
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7.11 Off Isolation
Off isolation is defined as the ratio of the signal at the drain pin (Dx) of the device when a signal is applied to the
source pin (Sx) of an off-channel. The characteristic impedance, Z0, for the measurement is 50 Ω. 图 37 shows
the setup used to measure off isolation. Use off isolation equation to compute off isolation.
0.1µF
NETWORK
VDD
ANALYZER
VS
S
D
50Ω
VSIG
VOUT
RL
50Ω
SX/DX
GND
RL
50Ω
图 37. Off Isolation Measurement Setup
≈
∆
«
’
÷
◊
VOUT
VS
Off Isolation = 20 ∂ Log
(1)
7.12 Channel-to-Channel Crosstalk
Crosstalk is defined as the ratio of the signal at the drain pin (Dx) of a different channel, when a signal is applied
at the source pin (Sx) of an on-channel. The characteristic impedance, Z0, for the measurement is 50 Ω. 图 38
shows the setup used to measure, and the equation used to compute crosstalk.
VDD
0.1µF
NETWORK
VDD
ANALYZER
D1
D2
S1
S2
VOUT
RL
RL
50Ω
50Ω
VS
RL
50Ω
50Ω
SX / DX
VSIG = 200 mVpp
VBIAS = VDD / 2
RL
50Ω
GND
图 38. Channel-to-Channel Crosstalk Measurement Setup
≈
∆
«
’
÷
◊
VOUT
VS
Channel-to-Channel Crosstalk = 20 ∂ Log
(2)
17
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7.13 Bandwidth
Bandwidth is defined as the range of frequencies that are attenuated by less than 3 dB when the input is applied
to the source pin (Sx) of an on-channel, and the output is measured at the drain pin (Dx) of the device. The
characteristic impedance, Z0, for the measurement is 50 Ω. 图 39 shows the setup used to measure bandwidth.
VDD
0.1µF
NETWORK
VDD
ANALYZER
VS
50Ω
S
D
VSIG
VOUT
RL
50Ω
GND
图 39. Bandwidth Measurement Setup
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8 Detailed Description
8.1 Overview
The TMUX1511 is a high speed 1:1 (SPST) 4-channel switch with powered-off protection up to 3.6 V. Wide
operating supply of 1.5 V to 5.5 V allows for use in a broad array of applications from servers and
communication equipment to industrial applications. The device supports bidirectional analog and digital
signals on the source (Sx) and drain (Dx) pins. The wide bandwidth of this switch allows little or no
attenuation of the high-speed signals at the outputs to pass with minimum edge and phase distortion as well
as propagation delay.
The select (SELx) pins are active-high logic pins that control the connection between the source (Sx) and
drain (Dx) pins of the device. Each channel of the TMUX1511 can be controlled independently through the
associated select pin, or all four select pins can be tied together for simultaneous control of all channels with
a single GPIO. Fail-Safe Logic circuitry allows voltages on the logic control pins to be applied before the
supply pin, protecting the device from potential damage. All logic control inputs have 1.8V logic compatible
thresholds, ensuring both TTL and CMOS logic compatibility when operating in the valid supply voltage
range.
Powered-off protection up to 3.6 V on the signal path of the TMUX1511 provides isolation when the supply
voltage is removed (VDD = 0 V). Without this protection feature, the system can back-power the supply rail
through an internal ESD diode and cause potential damage to the system.
8.2 Functional Block Diagram
TMUX1511
SEL1
S1
SEL4
S4
D1
D4
SEL2
S2
SEL3
S3
D2
D3
*Internal 6MO Pull-Down on Logic Pins
8.3 Feature Description
8.3.1 Bidirectional Operation
The TMUX1511 conducts equally well from source (Sx) to drain (Dx) or from drain (Dx) to source (Sx). Each
channel has very similar characteristics in both directions and supports both analog and digital signals.
8.3.2 Beyond Supply Operation
When the TMUX1511 is powered from 1.5 V to 5.5 V, the valid signal path input/output voltage ranges from
GND to VDD x 2, with a maximum input/output voltage of 5.5 V.
Example 1: If the TMUX1511 is powered at 1.5V, the signal range is 0 V to 3 V.
Example 2: If the TMUX1511 is powered at 3V, the signal range is 0 V to 5.5 V.
Example 3: If the TMUX1511 is powered at 5.5V, the signal range is 0 V to 5.5 V.
Other voltage levels not mentioned in the examples will support Beyond Supply Operation as long as the supply
voltage falls within the recommended operation conditions of 1.5 V to 5.5 V.
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Feature Description (接下页)
8.3.3 1.8 V Logic Compatible Inputs
The TMUX1511 has 1.8-V logic compatible control inputs. Regardless of the VDD voltage, the control input
thresholds remain fixed, allowing a 1.8-V processor GPIO to control the TMUX1511 without the need for an
external translator. This saves both space and BOM cost. For more information on 1.8 V logic implementations
refer to Simplifying Design with 1.8 V logic Muxes and Switches.
8.3.4 Powered-off Protection
Powered-off protection up to 3.6 V on the signal path of the TMUX1511 provides isolation when the supply
voltage is removed (VDD = 0 V). When the TMUX1511 is powered-off, the I/Os of the device remain in a high-Z
state. Powered-off protection minimizes system complexity by removing the need for power supply sequencing
on the signal path. The device performance remains within the leakage performance mentioned in the Electrical
Specifications. For more information on powered-off protection refer to Eliminate Power Sequencing with
Powered-off Protection Signal Switches
8.3.5 Fail-Safe Logic
The TMUX1511 has Fail-Safe Logic on the control input pins (SELx) which allows for operation up to 5.5 V,
regardless of the state of the supply pin. This feature allows voltages on the control pins to be applied before the
supply pin, protecting the device from potential damage. Fail-Safe Logic minimizes system complexity by
removing the need for power supply sequencing on the logic control pins. For example, the Fail-Safe Logic
feature allows the select pins of the TMUX1511 to be ramped to 5.5 V while VDD = 0 V. Additionally, the feature
enables operation of the TMUX1511 with VDD = 1.5 V while allowing the select pins to interface with a logic level
of another device up to 5.5 V.
8.3.6 Low Capacitance
The TMUX1511 has very low capacitance in both the ON and OFF states on the source and drain pins. The low
capacitance specification allows the TMUX1511 to be used in applications such as sample & hold circuits, and in
the feedback path of an operation amplifier. Low capacitance helps to reduce large overshoots and ringing of an
amplifier circuit when the switch is connected to the feedback network. Additionally, low capacitance improves
system settling time by reducing the switch time constant formed by the On-resistance and On-capacitance. For
more information on the benefits of low capacitance refer to Improve Stability Issues with Low CON Multiplexers.
8.3.7 Integrated Pull-Down Resistors
The TMUX1511 has internal weak pull-down resistors (6 MΩ) to GND to ensure the logic pins are not left
floating. This feature integrates up to four external components and reduces system size and cost.
8.4 Device Functional Modes
The select (SELx) pins are active-high logic pins that control the connection between the source (Sx) and drain
(Dx) pins of the device. The TMUX1511 has internal weak pull-down resistors (6 MΩ) to GND so that it powers-
on with the switches disabled. When a given select pin of the TMUX1511 is pulled high, the corresponding switch
conducts from the source to drain. When any of the select pins are pulled low, the corresponding switch is in an
open state (HI-Z). Each channel of the TMUX1511 can be controlled independently through the associated select
pin, or all four select pins can be tied together for simultaneous control of all channels with a single GPIO.
8.5 Truth Tables
表 1 shows the truth table for the TMUX1511.
表 1. TMUX1511 Truth Table
SELx
Sx / Dx: STATE
Hi-Z (OFF)
0
1
Conducting (ON)
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9 Application and Implementation
注
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
9.1 Application Information
The TMUX15xx family offers high-speed system performance across a wide operating supply (1.5 V to 5.5 V)
and operating temperature (-40°C to +125°C). The TMUX1511 supports a number of features that improve
system performance such as 1.8 V logic compatibility, input voltages beyond supply, Fail-Safe Logic, and
Powered-off Protection up to 3.6 V. These features make the TMUX15xx a family of protection multiplexers and
switches that can reduce system complexity, board size, and overall system cost.
9.2 Typical Application
9.2.1 Protocol / Signal Isolation
One useful application to take advantage of the TMUX1511 features is isolating various protocols from a
possessor or MCU such as JTAG, SPI, or standard GPIO signals. The device provides excellent isolation
performance when the device is powered. The added benefit of powered-off protection allows a system to
minimize complexity by eliminating the need for power sequencing in hot-swap and live insertion applications.
VDD
VI/O
VDD
0.1µF
Processor
JTAG, SPI, GPIO
Port
FLASH
TDI / MISO / GPIO
TDO / MOSI / GPIO
TCK / SCLK / GPIO
TMS / SS / GPIO
S1
S2
S3
S4
D1
D2
D3
D4
JTAG
DEBUG,
SPI, GPIO
RAM
CPU
SEL1
SEL2
SEL3
SEL4
1.8V Logic
I/O
Peripherals
GND
GND
图 40. Isolation of JTAG, SPI, and GPIO Signals
9.2.1.1 Design Requirements
For this design example, use the parameters listed in Table 2.
表 2. Design Parameters
PARAMETERS
Supply (VDD
VALUES
3.3 V
)
Input / Output signal range
Control logic thresholds
0 V to 3.3 V
1.8 V compatible
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9.2.1.2 Detailed Design Procedure
The TMUX1511 can be operated without any external components except for the supply decoupling capacitors.
The device has internal weak pull-down resistors (6 MΩ) to GND so that it powers-on with the switches disabled.
All inputs signals passing through the switch must fall within the recommend operating conditions of the
TMUX1511 including signal range and continuous current. For this design example, with a supply of 3.3 V, the
signals can range from 0 V to 3.3 V when the device is powered. This example can also utilize the Powered-off
Protection feature and the inputs can range from 0 V to 3.3 V when VDD = 0 V. The max continuous current can
be 25 mA. Due to the voltage range and high speed capability, the TMUX1511example is suitable for use in
JTAG and SPI applications beyond the 100 MHz maximum in a typical application.
9.2.1.3 Application Curves
Two important specifications when using a switch or multiplexer to pass signals are the device propagation delay
and skew.
70
60
Propagation Delay
50
40
30
Skew
20
10
0
1.5
2
2.5
3
3.5
4
4.5
5
5.5
6
Supply Voltage (V)
D018
图 41. Propagation Delay and Skew Measurement
9.2.2 Transimpedance Amplifier Feedback Control
Switches and multiplexers are commonly used in the feedback path of amplifier circuits to provide configurable
gain control. By using various resistor values on each switch path the TMUX1511 allows the system to have
multiple gain settings. An external resistor, or utilizing 1 channel always being closed, ensures the amplifier isn't
operating in an open loop configuration. A transimpedance amplifier (TIA) for photodiodes is a common circuit
that requires gain control using a multi-channel switch to convert the output current of the photodiode into a
voltage for the MCU or processor. The leakage current, capacitance, and charge injection performance of the
TMUX1511 are key specifications to evaluate when selecting a device for gain control.
VI/O
VDD
VDD
0.1µF
Processor
SEL1
SEL2
SEL3
SEL4
1.8V Logic I/O
RF_1
Digital Processing
RF_2
RF_3
RF_4
VDD
VDD
-
OP
AMP
Gain / Filter
Network
ADC
IPD
+
图 42. Multiplexing Gain for a TIA Circuit
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9.2.2.1 Design Requirements
For this design example, use the parameters listed in Table 3.
表 3. Design Parameters
PARAMETERS
VALUES
5 V
Supply (VDD
)
Input / Output signal range
Control logic thresholds
0 µA to 10 µA
1.8 V compatible
9.2.2.2 Detailed Design Procedure
Photodiodes commonly have a current output that ranges from a few hundred picoamps to tens of microamps
based on the amount of light being absorbed. The TMUX1511 has a typical On-leakage current of less than 10
pA which would lead to an accuracy well within 1% of a full scale 10 µA signal. The low ON and OFF
capacitance of the TMUX1511 improves system stability by minimizing the total capacitance on the output of the
amplifier. Lower capacitance leads to less overshoot and ringing in the system which can cause the amplifier
circuit to go unstable if the phase margin is not at least 45°. Refer to Improve Stability Issues with Low CON
Multiplexers for more information on calculating the phase margin vs. percent overshoot.
9.2.2.3 Application Curves
8
6
4
2
0
10
8
COFF
CON
VDD = 5.5 V
VDD = 3.3 V
VDD = 1.5 V
6
4
2
0
-2
-4
-6
-8
-10
1M
10M
100M
Frequency (Hz)
1G
D020
TA = 25°C
图 44. Capacitance vs Frequency
0
0.5
1
1.5
2
2.5
3
3.5
4
4.5
5
5.5
Source or Drain Voltage (V)
D007
TA = 25°C
图 43. On-Leakage vs Source or Drain Voltage
10 Power Supply Recommendations
The TMUX1511 operates across a wide supply range of 1.5 V to 5.5 V. Do not exceed the absolute maximum
ratings because stresses beyond the listed ratings can cause permanent damage to the devices.
Power-supply bypassing improves noise margin and prevents switching noise propagation from the VDD supply to
other components. Good power-supply decoupling is important to achieve optimum performance. For improved
supply noise immunity, use a supply decoupling capacitor ranging from 0.1 μF to 10 μF from VDD to ground.
Place the bypass capacitors as close to the power supply pins of the device as possible using low-impedance
connections. TI recommends using multi-layer ceramic chip capacitors (MLCCs) that offer low equivalent series
resistance (ESR) and inductance (ESL) characteristics for power-supply decoupling purposes. For very sensitive
systems, or for systems in harsh noise environments, avoiding the use of vias for connecting the capacitors to
the device pins may offer superior noise immunity. The use of multiple vias in parallel lowers the overall
inductance and is beneficial for connections to ground planes.
版权 © 2018, Texas Instruments Incorporated
23
TMUX1511
ZHCSIR9A –SEPTEMBER 2018–REVISED DECEMBER 2018
www.ti.com.cn
11 Layout
11.1 Layout Guidelines
When a PCB trace turns a corner at a 90° angle, a reflection can occur. A reflection occurs primarily because of
the change of width of the trace. At the apex of the turn, the trace width increases to 1.414 times the width. This
increase upsets the transmission-line characteristics, especially the distributed capacitance and self–inductance
of the trace which results in the reflection. Not all PCB traces can be straight and therefore some traces must
turn corners. 图 45 shows progressively better techniques of rounding corners. Only the last example (BEST)
maintains constant trace width and minimizes reflections.
WORST
BETTER
BEST
1W min.
W
图 45. Trace Example
Route the high-speed signals using a minimum of vias and corners which reduces signal reflections and
impedance changes. When a via must be used, increase the clearance size around it to minimize its
capacitance. Each via introduces discontinuities in the signal’s transmission line and increases the chance of
picking up interference from the other layers of the board. Be careful when designing test points, through-
hole pins are not recommended at high frequencies.
Do not route high speed signal traces under or near crystals, oscillators, clock signal generators, switching
regulators, mounting holes, magnetic devices or ICs that use or duplicate clock signals.
Avoid stubs on the high-speed signals traces because they cause signal reflections.
Route all high-speed signal traces over continuous GND planes, with no interruptions.
Avoid crossing over anti-etch, commonly found with plane splits.
When working with high frequencies, a printed circuit board with at least four layers is recommended; two
signal layers separated by a ground and power layer as shown in 图 46.
Signal 1
GND Plane
Power Plane
Signal 2
图 46. Example Layout
The majority of signal traces must run on a single layer, preferably Signal 1. Immediately next to this layer must
be the GND plane, which is solid with no cuts. Avoid running signal traces across a split in the ground or power
plane. When running across split planes is unavoidable, sufficient decoupling must be used. Minimizing the
number of signal vias reduces EMI by reducing inductance at high frequencies.
图 47 illustrates an example of a PCB layout with the TMUX1511. Some key considerations are:
24
版权 © 2018, Texas Instruments Incorporated
TMUX1511
www.ti.com.cn
ZHCSIR9A –SEPTEMBER 2018–REVISED DECEMBER 2018
Layout Guidelines (接下页)
Decouple the VDD pin with a 0.1-μF capacitor, placed as close to the pin as possible. Make sure that the
capacitor voltage rating is sufficient for the VDD supply.
High-speed switches require proper layout and design procedures for optimum performance.
Keep the input lines as short as possible.
Use a solid ground plane to help reduce electromagnetic interference (EMI) noise pickup.
Do not run sensitive analog traces in parallel with digital traces. Avoid crossing digital and analog traces if
possible, and only make perpendicular crossings when necessary.
11.2 Layout Example
Wide (low inductance)
trace for power
Via to GND plane
C
SEL1
VDD
SEL4
S4
S1
D1
TMUX1511
SEL2
S2
D4
SEL3
S3
D2
GND
D3
图 47. Example Layout
版权 © 2018, Texas Instruments Incorporated
25
TMUX1511
ZHCSIR9A –SEPTEMBER 2018–REVISED DECEMBER 2018
www.ti.com.cn
12 器件和文档支持
12.1 文档支持
12.1.1 相关文档
德州仪器 (TI)，《使用低 CON 多路复用器改善稳定性问题》。
德州仪器 (TI)，《使用 1.8V 逻辑多路复用器和开关简化设计》。
德州仪器 (TI)，《利用关断保护信号开关消除电源排序》。
德州仪器 (TI)，《高速接口布局指南》。
德州仪器 (TI)，《高速布局指南》。
德州仪器 (TI)，《QFN/SON PCB 连接》。
Texas Instruments, 《四方扁平封装无引线逻辑封装》。
12.2 接收文档更新通知
要接收文档更新通知，请导航至 TI.com.cn 上的器件产品文件夹。单击右上角的通知我进行注册，即可每周接收产
品信息更改摘要。有关更改的详细信息，请查看任何已修订文档中包含的修订历史记录。
12.3 社区资源
下列链接提供到 TI 社区资源的连接。链接的内容由各个分销商“按照原样”提供。这些内容并不构成 TI 技术规范，
并且不一定反映 TI 的观点；请参阅 TI 的 《使用条款》。
TI E2E™ 在线社区 TI 的工程师对工程师 (E2E) 社区。此社区的创建目的在于促进工程师之间的协作。在
e2e.ti.com 中，您可以咨询问题、分享知识、拓展思路并与同行工程师一道帮助解决问题。
设计支持
TI 参考设计支持 可帮助您快速查找有帮助的 E2E 论坛、设计支持工具以及技术支持的联系信息。
12.4 商标
E2E is a trademark of Texas Instruments.
12.5 静电放电警告
ESD 可能会损坏该集成电路。德州仪器 (TI) 建议通过适当的预防措施处理所有集成电路。如果不遵守正确的处理措施和安装程序 , 可
能会损坏集成电路。
ESD 的损坏小至导致微小的性能降级 , 大至整个器件故障。 精密的集成电路可能更容易受到损坏 , 这是因为非常细微的参数更改都可
能会导致器件与其发布的规格不相符。
12.6 术语表
SLYZ022 — TI 术语表。
这份术语表列出并解释术语、缩写和定义。
13 机械、封装和可订购信息
以下页面包含机械、封装和可订购信息。这些信息是指定器件的最新可用数据。数据如有变更，恕不另行通知，且
不会对此文档进行修订。如需获取此数据表的浏览器版本，请查阅左侧的导航栏。
26
版权 © 2018, Texas Instruments Incorporated
PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
TMUX1511PWR
TMUX1511RSVR
ACTIVE
ACTIVE
TSSOP
UQFN
PW
14
16
2000 RoHS & Green
3000 RoHS & Green
NIPDAU
Level-1-260C-UNLIM
Level-1-260C-UNLIM
-40 to 125
-40 to 125
MUX1511
1511
RSV
NIPDAUAG
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
16-Jun-2023
TAPE AND REEL INFORMATION
REEL DIMENSIONS
TAPE DIMENSIONS
K0
P1
W
B0
Reel
Diameter
Cavity
A0
A0 Dimension designed to accommodate the component width
B0 Dimension designed to accommodate the component length
K0 Dimension designed to accommodate the component thickness
Overall width of the carrier tape
W
P1 Pitch between successive cavity centers
Reel Width (W1)
QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE
Sprocket Holes
Q1 Q2
Q3 Q4
Q1 Q2
Q3 Q4
User Direction of Feed
Pocket Quadrants
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
TMUX1511PWR
TMUX1511RSVR
TSSOP
UQFN
PW
14
16
2000
3000
330.0
178.0
12.4
13.5
6.9
2.1
5.6
2.9
1.6
8.0
4.0
12.0
12.0
Q1
Q1
RSV
0.75
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
16-Jun-2023
TAPE AND REEL BOX DIMENSIONS
Width (mm)
H
W
L
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SPQ
Length (mm) Width (mm) Height (mm)
TMUX1511PWR
TMUX1511RSVR
TSSOP
UQFN
PW
14
16
2000
3000
356.0
189.0
356.0
185.0
35.0
36.0
RSV
Pack Materials-Page 2
PACKAGE OUTLINE
RSV0016A
UQFN - 0.55 mm max height
S
C
A
L
E
5
.
0
0
0
ULTRA THIN QUAD FLATPACK - NO LEAD
1.85
1.75
A
B
PIN 1 INDEX AREA
2.65
2.55
C
0.55
0.45
SEATING PLANE
0.05 C
0.05
0.00
2X 1.2
SYMM
℄
(0.13) TYP
5
8
0.45
0.35
15X
4
9
SYMM
℄
2X 1.2
12X 0.4
1
0.25
16X
12
0.15
0.07
0.05
C A B
13
16
0.55
0.45
PIN 1 ID
(45° X 0.1)
4220314/C 02/2020
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
www.ti.com
EXAMPLE BOARD LAYOUT
RSV0016A
UQFN - 0.55 mm max height
ULTRA THIN QUAD FLATPACK - NO LEAD
SYMM
℄
(0.7)
16
SEE SOLDER MASK
DETAIL
13
12
16X (0.2)
1
SYMM
℄
12X (0.4)
(2.4)
(R0.05) TYP
9
4
15X (0.6)
5
8
(1.6)
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE: 25X
0.05 MIN
ALL AROUND
0.05 MAX
ALL AROUND
METAL UNDER
SOLDER MASK
METAL EDGE
EXPOSED METAL
SOLDER MASK
OPENING
EXPOSED
METAL
SOLDER MASK
OPENING
NON SOLDER MASK
DEFINED
SOLDER MASK DEFINED
(PREFERRED)
SOLDER MASK DETAILS
4220314/C 02/2020
NOTES: (continued)
3. For more information, see Texas Instruments literature number SLUA271 (www.ti.com/lit/slua271).
www.ti.com
EXAMPLE STENCIL DESIGN
RSV0016A
UQFN - 0.55 mm max height
ULTRA THIN QUAD FLATPACK - NO LEAD
(0.7)
16
13
16X (0.2)
1
12
SYMM
℄
12X (0.4)
(2.4)
(R0.05) TYP
4
9
15X (0.6)
5
8
SYMM
℄
(1.6)
SOLDER PASTE EXAMPLE
BASED ON 0.125 MM THICK STENCIL
SCALE: 25X
4220314/C 02/2020
NOTES: (continued)
4. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
www.ti.com
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