TMUX1574DYYR [TI]
具有断电保护功能和 1.8V 输入逻辑的 5V、2:1 (SPDT)、4 通道模拟开关 | DYY | 16 | -40 to 125;
| 型号： | TMUX1574DYYR |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 具有断电保护功能和 1.8V 输入逻辑的 5V、2:1 (SPDT)、4 通道模拟开关 | DYY | 16 | -40 to 125 开关 光电二极管 |
| 文件： | 总44页 (文件大小：1999K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
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TMUX1574
ZHCSIX6B –OCTOBER 2018–REVISED SEPT 2019
具有1.8V 逻辑电平的 TMUX1574 低电容、2:1 (SPDT) 4 通道
断电保护开关
1 特性
3 说明
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宽电源电压范围：1.5V 至 5.5V
TMUX1574 是一款互补金属氧化物半导体 (CMOS) 开
关。TMUX1574 提供具有 4 个通道的 2:1 SPDT 开关
配置。1.5V 至 5.5V 的宽运行电源电压范围 使其 可用
于从服务器和通信设备到工业应用的各种 应用理想之
选。该器件可在源极 (SxA, SxB) 和漏极 (Dx) 引脚上支
持双向模拟和数字信号，并且可以传递高于电源的信号
（高达 VDD x 2），最大输入/输出电压为 5.5V。
低导通电容：7.5pF
低导通电阻：2Ω
高带宽：2GHz
工作温度范围：-40°C 至 +125°C
兼容 1.8V 逻辑电平
支持超出电源电压范围的输入电压
逻辑引脚上的集成下拉电阻器
双向信号路径
TMUX1574 的信号路径上高达 3.6V 的关断保护可在
移除电源电压 (VDD = 0V) 时提供隔离。如果没有该保
护功能，开关可通过内部 ESD 二极管为电源轨进行反
向供电，从而对系统造成潜在损坏。
失效防护逻辑
高达 3.6V 信号的关断保护
–
引脚排布与 SN74CBTLV3257 兼容
失效防护逻辑 电路允许在施加电源引脚上的电压之
前，先施加逻辑控制引脚上的电压，从而保护器件免受
潜在的损害。所有控制输入都具有兼容 1.8V 逻辑电平
的阈值，当器件在有效电源电压范围内运行时，这些阈
值可确保 TTL 和 CMOS 逻辑兼容性。逻辑引脚上带有
集成下拉电阻 无需外部组件，可减少系统尺寸与成
本。
2 应用
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服务器
数据中心交换机和路由器
无线基础设施
PC 和笔记本电脑
楼宇自动化
电网基础设施
电子销售点 (ePOS)
电器
器件信息(1)
器件型号
封装
TSSOP (16)
封装尺寸（标称值）
5.00mm × 4.40mm
2.60mm x 1.80mm
4.20mm x 2.00mm
闪存存储器共享
JTAG 多路复用
SPI 多路复用
TMUX1574
UQFN (16)
SOT-23-THIN (16)
(1) 如需了解所有可用封装，请参阅数据表末尾的封装选项附录。
应用示例
方框图
VDD
VI/O
TMUX1574
VDD
0.1µF
S1A
SPI / JTAG / UART
Device #1
D1
S1B
Processor
S1A
S2A
S3A
S4A
MISO / TDI / GPIO
MOSI / TDO / GPIO
SCLK / TCK / GPIO
SS / TMS / GPIO
S2A
D2
D1
D2
D3
D4
RAM
CPU
S2B
JTAG
DEBUG,
SPI, GPIO
S3A
D3
SPI / JTAG / UART
Device #2
S3B
S1B
S2B
S3B
S4B
S4A
MISO / TDI / GPIO
MOSI / TDO / GPIO
SCLK / TCK / GPIO
SS / TMS / GPIO
D4
Peripherals
S4B
SEL
EN
1.8V Logic
I/O
LOGIC CONTROL*
GND
GND
SEL
EN
*Internal 6MO Pull-Down on Logic Pins
1
本文档旨在为方便起见，提供有关 TI 产品中文版本的信息，以确认产品的概要。 有关适用的官方英文版本的最新信息，请访问 www.ti.com，其内容始终优先。 TI 不保证翻译的准确
性和有效性。 在实际设计之前，请务必参考最新版本的英文版本。
English Data Sheet: SCDS391
TMUX1574
ZHCSIX6B –OCTOBER 2018–REVISED SEPT 2019
www.ti.com.cn
目录
7.12 Capacitance .......................................................... 19
7.13 Off Isolation........................................................... 20
7.14 Channel-to-Channel Crosstalk.............................. 20
7.15 Bandwidth ............................................................. 21
Detailed Description ............................................ 22
8.1 Overview ................................................................. 22
8.2 Functional Block Diagram ....................................... 22
8.3 Feature Description................................................. 22
8.4 Device Functional Modes........................................ 24
8.5 Truth Tables............................................................ 24
Application and Implementation ........................ 25
9.1 Application Information............................................ 25
9.2 Typical Application ................................................. 25
1
2
3
4
5
6
特性.......................................................................... 1
应用.......................................................................... 1
说明.......................................................................... 1
修订历史记录 ........................................................... 2
Pin Configuration and Functions......................... 3
Specifications......................................................... 5
6.1 Absolute Maximum Ratings ...................................... 5
6.2 ESD Ratings.............................................................. 5
6.3 Recommended Operating Conditions....................... 5
6.4 Thermal Information.................................................. 5
6.5 Electrical Characteristics........................................... 6
6.6 Dynamic Characteristics ........................................... 7
6.7 Timing Requirements................................................ 8
6.8 Typical Characteristics.............................................. 9
Parameter Measurement Information ................ 14
7.1 On-Resistance ........................................................ 14
7.2 Off-Leakage Current ............................................... 14
7.3 On-Leakage Current ............................................... 15
7.4 IPOFF Leakage Current............................................ 15
7.5 Transition Time ....................................................... 16
7.6 tON (EN) and tOFF (EN) Time....................................... 16
7.7 tON (VDD) and tOFF (VDD) Time................................... 17
7.8 Break-Before-Make Delay....................................... 17
7.9 Propagation Delay................................................... 18
7.10 Skew ..................................................................... 18
7.11 Charge Injection.................................................... 19
8
9
10 Power Supply Recommendations ..................... 26
11 Layout................................................................... 27
11.1 Layout Guidelines ................................................. 27
11.2 Layout Example .................................................... 28
12 器件和文档支持 ..................................................... 29
12.1 文档支持................................................................ 29
12.2 接收文档更新通知 ................................................. 29
12.3 社区资源................................................................ 29
12.4 商标....................................................................... 29
12.5 静电放电警告......................................................... 29
12.6 Glossary................................................................ 29
13 机械、封装和可订购信息....................................... 30
7
4 修订历史记录
注：之前版本的页码可能与当前版本有所不同。
Changes from Revision A (December 2018) to Revision B
Page
•
•
向数据表添加了 SOT-23-THIN (DYY) 封装 ............................................................................................................................ 1
Added thermal information for DYY package......................................................................................................................... 5
Changes from Original (October 2018) to Revision A
Page
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将文档状态从预告信息 更改为生产 数据................................................................................................................................. 1
2
Copyright © 2018–2019, Texas Instruments Incorporated
TMUX1574
www.ti.com.cn
ZHCSIX6B –OCTOBER 2018–REVISED SEPT 2019
5 Pin Configuration and Functions
PW Package
16-Pin TSSOP
Top View
DYY Package
16-Pin SOT-23-THIN
Top View
SEL
S1A
S1B
D1
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
VDD
EN
SEL
S1A
S1B
D1
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
VDD
EN
S4A
S4B
D4
S4A
S4B
D4
S2A
S2B
D2
S2A
S2B
D2
S3A
S3B
D3
S3A
S3B
D3
GND
GND
Not to scale
RSV Package
16-Pin UQFN
Top View
S1B
D1
1
12
11
10
9
S4A
S4B
D4
2
3
4
S2A
S2B
S3A
Not to scale
Copyright © 2018–2019, Texas Instruments Incorporated
3
TMUX1574
ZHCSIX6B –OCTOBER 2018–REVISED SEPT 2019
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Pin Functions
PIN
TYPE(1)
DESCRIPTION(2)
TSSOP /
SOT-23-THIN
NAME
UQFN
SEL
S1A
S1B
D1
1
2
15
16
1
I
Select pin: controls state of switches according to 表 1. Internal 6 MΩ pull-down to GND.
Source pin 1A. Can be an input or output.
Source pin 1B. Can be an input or output.
Drain pin 1. Can be an input or output.
I/O
I/O
I/O
I/O
I/O
I/O
P
3
4
2
S2A
S2B
D2
5
3
Source pin 2A. Can be an input or output.
Source pin 2B. Can be an input or output.
Drain pin 2. Can be an input or output.
6
4
7
5
GND
D3
8
6
Ground (0 V) reference
9
7
I/O
I/O
I/O
I/O
I/O
I/O
Drain pin 3. Can be an input or output.
S3B
S3A
D4
10
11
12
13
14
8
Source pin 3B. Can be an input or output.
Source pin 3A. Can be an input or output.
Drain pin 4. Can be an input or output.
9
10
11
12
S4B
S4A
Source pin 4B. Can be an input or output.
Source pin 4A. Can be an input or output.
Active low enable: When this pin is high, all switches are turned off. When this pin is low,
SEL pin controls the signal path selection. Internal 6 MΩ pull-down to GND.
EN
15
16
13
14
I
Positive power supply. This pin is the most positive power-supply potential. For reliable
operation, connect a decoupling capacitor ranging from 0.1 µF to 10 µF between VDD and
GND.
VDD
P
(1) I = input, O = output, I/O = input and output, P = power
(2) Refer to Device Functional Modes for what to do with unused pins.
4
Copyright © 2018–2019, Texas Instruments Incorporated
TMUX1574
www.ti.com.cn
ZHCSIX6B –OCTOBER 2018–REVISED SEPT 2019
6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)(1)(2)(3)
MIN
–0.5
–0.5
–30
–0.5
–25
–65
MAX
6
UNIT
V
VDD
Supply voltage
VSEL or VEN
ISEL or IEN
VS or VD
IS or ID (CONT)
Tstg
Logic control input pin voltage (SEL or EN)
Logic control input pin current (SEL or EN)
Source or drain pin voltage
6
V
30
6
mA
V
Source and drain pin continuous current: (SxA, SxB, Dx)
Storage temperature
25
150
150
mA
°C
°C
TJ
Junction temperature
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) The algebraic convention, whereby the most negative value is a minimum and the most positive value is a maximum.
(3) All voltages are with respect to ground, unless otherwise specified.
6.2 ESD Ratings
VALUE
UNIT
Human body model (HBM), per ANSI/ESDA/JEDEC JS-
001(1)
±2000
V(ESD)
Electrostatic discharge
V
Charged-device model (CDM), per JEDEC specification
JESD22-C101(2)
±750
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
6.3 Recommended Operating Conditions
MIN
MAX
5.5
UNIT
V
VDD
Supply voltage
1.5
0
VS or VD
VS_off or VD_off
VSEL or VEN
TA
Signal path input/output voltage (source or drain pin), VDD ≥ 1.5 V(1)
Signal path input/output voltage (source or drain pin), VDD < 1.5 V(2)
Logic control input voltage (EN, SEL)
VDD x 2
3.6
V
0
V
0
5.5
V
Ambient temperature
–40
125
ºC
(1) Device input/output can operate up to VDD x 2, with a maximum input/output voltage of 5.5 V.
(2) VS_off and VD_off refers to the voltage at the source or drain pins when supply is less than 1.5 V.
6.4 Thermal Information
DEVICE
PW (TSSOP)
16 PINS
117.4
DEVICE
DYY (SOT-23)
16 PINS
123.0
DEVICE
THERMAL METRIC(1)
RSV (UQFN)
16 PINS
129.2
69.7
UNIT
RθJA
Junction-to-ambient thermal resistance
Junction-to-case (top) thermal resistance
Junction-to-board thermal resistance
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
RθJC(top)
RθJB
47.9
70.5
63.7
50.4
58.7
ΨJT
Junction-to-top characterization parameter
Junction-to-board characterization parameter
Junction-to-case (bottom) thermal resistance
6.9
5.0
3.6
ΨJB
63.1
50.3
56.8
RθJC(bot)
N/A
N/A
N/A
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
Copyright © 2018–2019, Texas Instruments Incorporated
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ZHCSIX6B –OCTOBER 2018–REVISED SEPT 2019
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6.5 Electrical Characteristics
VDD = 1.5 V to 5.5 V, GND = 0V, TA = –40°C to +125°C
Typical values are at VDD = 3.3 V, TA = 25°C, (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
POWER SUPPLY
VDD
Power supply voltage
1.5
5.5
68
V
VSEL = 0 V, 1.4V or VDD
VS = 0 V to 5.5 V
IDD
Active supply current
40
μA
VEN = 1.4V or VDD
VS = 0 V to 5.5 V
IDD_STANDB
Supply current when disabled
7.5
15
µA
Y
DC CHARACTERISTICS
VS = 0 V to VDD*2
VS(max) = 5.5 V
ISD = 8 mA
RON
On-resistance
2
4.5
Ω
Refer to ON-State Resistance Figure
VS = VDD
ΔRON
On-resistance match between channels
ISD = 8 mA
Refer to ON-State Resistance Figure
0.07
1
0.28
1.8
Ω
Ω
VS = 0 V to VDD
ISD = 8 mA
RON (FLAT) On-resistance flatness
Refer to ON-State Resistance Figure
VDD = 0 V
VS = 0 V to 3 V
VD = 0 V
IPOFF
Powered-off I/O pin leakage current
–10
0.01
10
nA
TA = 25℃
Refer to Ipoff Leakage Figure
VDD = 0 V
VS = 0 V to 3.6 V
VD = 0 V
Refer to Ipoff Leakage Figure
IPOFF
Powered-off I/O pin leakage current
OFF leakage current
–2
0.01
0.03
2
µA
nA
Switch Off
IS(OFF)
ID(OFF)
VD = 0.8*VDD / 0.2*VDD
VS = 0.2*VDD / 0.8*VDD
Refer to Off Leakage Figure
–100
100
Switch On
VD = 0.8*VDD / 0.2*VDD, S pins floating
or
VS = 0.8*VDD / 0.2*VDD, D pins floating
Refer to On Leakage Figure
ID(ON)
IS(ON)
ON leakage current
–50
0.01
50
nA
LOGIC INPUTS
VIH
VIL
IIH
Input logic high
1.2
0
5.5
0.45
±2
V
V
Input logic low
Input high leakage current
Input low leakage current
Internal pull-down resistor on logic pins
VSEL = 1.8 V, VDD
VSEL = 0 V
1
0.2
6
μA
μA
MΩ
IIL
±2
RPD
VSEL = 0 V, 1.8 V or VDD
f = 1 MHz
CI
Logic input capacitance
3
pF
6
Copyright © 2018–2019, Texas Instruments Incorporated
TMUX1574
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ZHCSIX6B –OCTOBER 2018–REVISED SEPT 2019
6.6 Dynamic Characteristics
VDD = 1.5 V to 5.5 V, GND = 0V, TA = –40°C to +125°C
Typical values are at VDD = 3.3 V, TA = 25°C, (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
VS = 2.5 V
VSEL= 0 V
f = 1 MHz
Switch
OFF
COFF
Source and drain off capacitance
3.5
6
pF
Refer to Capacitance Figure
VS = 2.5 V
VSEL= 0 V
f = 1 MHz
Refer to Capacitance Figure
Switch
ON
CON
Source and drain on capacitance
Charge Injection
7.5
12
pF
VS = VDD/2
RS = 0 Ω, CL =1 nF
Refer to Charge Injection Figure
Switch
ON
QC
3.5
–90
–75
pC
dB
dB
RL = 50 Ω
f = 100 kHz
Refer to Off Isolation Figure
Switch
OFF
OISO
Off isolation
RL = 50 Ω
f = 1 MHz
Refer to Off Isolation Figure
Switch
OFF
RL = 50 Ω
f = 100 kHz
Refer to Crosstalk Figure
Switch
ON
XTALK
BW
Channel to Channel crosstalk
Bandwidth
–90
2
dB
GHz
dB
RL = 50 Ω
Refer to Bandwidth Figure
Switch
ON
RL = 50 Ω
f = 1 MHz
Refer to Bandwidth Figure
Switch
ON
ILOSS
Insertion loss
–0.12
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ZHCSIX6B –OCTOBER 2018–REVISED SEPT 2019
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6.7 Timing Requirements
VDD = 1.5 V to 5.5 V, GND = 0V, TA = –40°C to +125°C
Typical values are at VDD = 3.3 V, TA = 25°C, (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
NOM
MAX
UNIT
VDD = 2.5 V to 5.5 V
VS = VDD
RL = 200 Ω, CL = 15pF
Refer to Transition Timing Figure
tTRAN
Transition time from control input
160
350
580
ns
VDD < 2.5 V
VS = VDD
RL = 200 Ω, CL = 15pF
Refer to Transition Timing Figure
tTRAN
Transition time from control input
180
ns
VS = VDD
tON(EN)
Device turn on time from enable pin
Device turn off time from enable pin
RL = 200 Ω, CL = 15pF
Refer to Ton(EN) & Toff(EN) Figure
12
50
35
95
µs
ns
VS = VDD
RL = 200 Ω, CL = 15pF
Refer to Ton(EN) & Toff(EN) Figure
tOFF(EN)
VS = 3.6 V
VDD rise time = 1us
RL = 200 Ω, CL = 15pF
Refer to Ton(vdd) & Toff(vdd) Figure
tON(VDD)
Device turn on time (VDD to output)
Device turn off time (VDD to output)
20
60
µs
VS = 3.6 V
VDD fall time = 1us
RL = 200 Ω, CL = 15pF
Refer to Ton(vdd) & Toff(vdd) Figure
tOFF(VDD)
1.2
2.7
µs
ns
VS = 1 V
RL = 200 Ω, CL = 15pF
Refer to Topen(BBM) Figure
tOPEN (BBM) Break before make time
0.5
tSK(P)
tSK(P)
tSK(P)
tPD
Inter - channel skew - QFN (RSV)
Refer to Tsk Figure
Refer to Tsk Figure
Refer to Tsk Figure
Refer to Tpd Figure
Refer to Tpd Figure
Refer to Tpd Figure
5
10
18
50
70
95
ps
ps
ps
ps
ps
ps
Inter - channel skew - DYY (SOT-23)
Inter - channel skew - TSSOP (PW)
Propagation delay - QFN (RSV)
Propagation delay - DYY (SOT-23)
Propagation delay - TSSOP (PW)
tPD
tPD
8
版权 © 2018–2019, Texas Instruments Incorporated
TMUX1574
www.ti.com.cn
ZHCSIX6B –OCTOBER 2018–REVISED SEPT 2019
6.8 Typical Characteristics
at TA = 25°C, VDD = 5 V (unless otherwise noted)
5
4
3
5
4
3
2
1
0
TA = 125èC
TA = 85èC
VDD = 1.5 V
VDD = 5.5 V
2
1
0
TA = 25èC
VDD = 3.3 V
TA = -40èC
0
1
2
Source or Drain Voltage (V)
3
4
5
5.5
0
1
2
Source or Drain Voltage (V)
3
4
5
5.5
D001
D002
TA = 25°C
VDD = 5.5 V
图 1. On-Resistance vs Source or Drain Voltage
图 2. On-Resistance vs Source or Drain Voltage
4
3
2
1
0
4
3
2
1
0
TA = 125èC
TA = 85èC
TA = 125èC
TA = 85èC
TA = 25èC
TA = -40èC
TA = 25èC
TA = -40èC
1.5
Source or Drain Voltage (V)
0
0.5
1
2
2.5
3
3.5
0
0.5 1
Source or Drain Voltage (V)
1.5
D003
D004
VDD = 3.3 V
VDD = 1.5 V
图 3. On-Resistance vs Source or Drain Voltage
图 4. On-Resistance vs Source or Drain Voltage
65
60
55
50
45
40
35
30
25
60
55
50
45
40
35
30
TA = 125èC
TA = 85èC
VDD = 3.3 V
VDD = 5.5 V
TA = 25èC
VDD = 1.5 V
TA = -40èC
2.5
0
0.5
1
1.5
2
2.5
Logic Voltage (V)
3
3.5
4
4.5
5
5.5
1.5
2
3
3.5
Supply Voltage (V)
4
4.5
5
5.5
6
D005
D006
TA = 25°C
图 5. Supply Current vs Logic Voltage
图 6. Supply Current vs Supply Voltage
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ZHCSIX6B –OCTOBER 2018–REVISED SEPT 2019
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Typical Characteristics (接下页)
2
1.5
1
30
25
20
15
10
5
VDD = 5.5 V
VDD = 3.3 V
VDD = 1.5 V
0.5
0
0
VDD = 5.5 V
VDD = 3.3 V
VDD = 1.5 V
-5
-0.5
-10
0
0.5
1
1.5
2
Source or Drain Voltage (V)
2.5
3
3.5
4
4.5
5
5.5
-50
-25
0
25
50
75
100
125
150
Temperature (èC)
D007
D008
TA = 25°C
图 7. On-Leakage vs Source or Drain Voltage
图 8. On-Leakage vs Temperature
3
2.7
2.4
2.1
1.8
1.5
1.2
0.9
0.6
0.3
0
0.1
0.05
0
VDD = 5.5 V
VDD = 3.3 V
VDD = 1.5 V
-0.05
-0.1
-0.15
VDD = 5.5 V
VDD = 3.3 V
VDD = 1.5 V
-0.3
0
1
2
Source Voltage (V)
3
4
5
5.5
-40
-20
0
20
40
60
80
100 120 140
Temperature (èC)
D009
D010
TA = 25°C
图 9. Off-Leakage vs Source or Drain Voltage
图 10. Off-Leakage vs Temperature
1
0.9
0.8
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0
10
8
6
4
2
0
-2
0
0.5
1
1.5
Source Voltage (V)
2
2.5
3
3.5
4
-40 -30 -20 -10
0
10
20
30
40
50
60
Temperature (èC)
D011
D012
TA = 25°C
VSource = 3 V
图 11. IPOFF Leakage vs Source or Drain Voltage
图 12. IPOFF Leakage vs Temperature
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Typical Characteristics (接下页)
700
600
500
400
300
200
100
0
-100
-40
-20
0
20
40
60
80
100 120 140
Temperature (èC)
D013
TA = 25°C
VSource = 3.6 V
VDrain = 0 V
RL= 200 Ω
图 14. IPOFF Leakage vs Source or Drain Voltage
图 13. IPOFF Leakage vs Temperature
180
220
195
170
145
120
95
Transiton_Falling
Transiton_Rising
160
140
120
100
80
Transiton_Falling
Transiton_Rising
60
70
40
45
20
20
1.5
2
2.5
3
3.5
Supply Voltage (V)
4
4.5
5
5.5
6
-40
-20
0
20
40
60
80
100 120 140
Temperature (èC)
D015
D016
TA = 25°C
VDD = 5.5 V
图 16. TTRANSITION vs Temperature
图 15. TTRANSITION vs Supply Voltage
25
20
15
10
5
25
20
15
10
5
TON(VDD)
TOFF(VDD)
0
0
1.5
2
2.5
3
Supply Voltage (V)
3.5
4
4.5
5
5.5
1.5
2
2.5
3
Supply Voltage (V)
3.5
4
4.5
5
5.5
D017
D018
TA = 25°C
TA = 25°C
图 17. TON (VDD) and TOFF (VDD) vs Supply Voltage
图 18. TON (EN) vs Supply Voltage
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Typical Characteristics (接下页)
100
90
80
70
60
50
40
30
20
10
0
80
70
60
50
40
30
20
10
0
Propagation Delay - PW
Propagation Delay - RSV
Skew - PW
Skew - RSV
1.5
2
2.5
3
3.5
4
Supply Voltage (V)
4.5
5
5.5
D019
1.5
2
2.5
3
3.5
4
Supply Voltage (V)
4.5
5
5.5
6
TA = 25°C
D020
图 19. TOFF (EN) vs Supply Voltage
TA = 25°C
图 20. Skew and Propagation Delay vs Supply Voltage
10
10
CSOFF
CSON
9
8
7
6
5
4
3
2
1
0
8
6
4
2
0
VDD = 5.5 V
VDD = 3.3 V
VDD = 1.5 V
0
1
2
3
Source Voltage (V)
4
5
6
1M
10M
100M
Frequency (Hz)
1G
D021
D022
TA = 25°C
TA = 25°C
VDD = 1.5 V to 5.5 V
图 21. Charge Injection vs Source Voltage
图 22. Capacitance vs Frequency
0
0
Off Isolation
Crosstalk
-10
-20
-1
-2
-3
-4
-5
-6
-30
-40
-50
-60
-70
-80
-90
-100
-110
-120
100k
1M
10M
Frequency (Hz)
100M
1G
1M
10M 100M
Frequency (Hz)
1G
D023
D024
TA = 25°C
TA = 25°C
VDD = 3.3 V
VDD = 1.5 V to 5.5 V
图 23. Off Isolation and Crosstalk vs Frequency
图 24. On-Response vs Frequency
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6.8.1 Eye Diagrams
TA = 25°C
Bias = 1.5 V
TA = 25°C
Bias = 1.5 V
50 Ω Termination
50 Ω Termination
图 26. Eye Pattern: 2.4 Gbps Through Path
图 25. Eye Pattern: 2.4 Gbps
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7 Parameter Measurement Information
7.1 On-Resistance
The on-resistance of a device is the ohmic resistance between the source (Sx) and drain (Dx) pins of the device.
The on-resistance varies with input voltage and supply voltage. The symbol RON is used to denote on-resistance.
The measurement setup used to measure RON is shown in 图 27. Voltage (V) and current (ISD) are measured
using this setup, and RON is computed as shown below with RON = V / ISD
:
V
ISD
Sx
Dx
VS
图 27. On-Resistance Measurement Setup
7.2 Off-Leakage Current
Source leakage current is defined as the leakage current flowing into or out of the source pin when the switch is
off. This current is denoted by the symbol IS (OFF)
.
Drain leakage current is defined as the leakage current flowing into or out of the drain pin when the switch is off.
This current is denoted by the symbol ID (OFF)
.
The setup used to measure both off-leakage currents is shown in 图 28.
VDD
VDD
IS (OFF)
VDD
VDD
ID (OFF)
A
S1A
S1B
S1A
S1B
A
D1
D1
VS
VD
VD
VD
VS
ID (OFF)
A
IS (OFF)
A
S4A
S4B
D4
S1A
S1B
D1
VD
VS
VS
VD
GND
GND
VD
图 28. Off-Leakage Measurement Setup
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7.3 On-Leakage Current
Source on-leakage current is defined as the leakage current flowing into or out of the source pin when the switch
is on. This current is denoted by the symbol IS (ON)
.
Drain on-leakage current is defined as the leakage current flowing into or out of the drain pin when the switch is
on. This current is denoted by the symbol ID (ON)
.
Either the source pin or drain pin is left floating during the measurement. 图 29 shows the circuit used for
measuring the on-leakage current, denoted by IS(ON) or ID(ON)
.
VDD
VDD
IS (ON)
VDD
VDD
ID (ON)
S1A
S1A
S1B
A
N.C.
D1
D1
A
N.C.
S1B
N.C.
N.C.
VS
VD
IS (ON)
ID (ON)
A
S4A
S4B
S4A
S4B
N.C.
N.C.
A
D4
D4
N.C.
N.C.
VS
VD
GND
GND
图 29. On-Leakage Measurement Setup
7.4 IPOFF Leakage Current
IPOFF leakage current is defined as the leakage current flowing into or out of the source pin when the device is
powered off. This current is denoted by the symbol IPOFF
.
The setup used to measure both IPOFF leakage current is shown in 图 30.
VDD
IPOFF
VDD
S1A
A
D1
S1B
N.C.
VS
VD
IPOFF
S4A
S4B
A
D4
N.C.
VS
VD
GND
图 30. IPOFF Leakage Measurement Setup
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7.5 Transition Time
Transition time is defined as the time taken by the output of the device to rise or fall 10% after the select signal
has risen or fallen past the logic threshold. The 10% transition measurement is utilized to provide the timing of
the device. The time constant from the load resistance and load capacitance can be added to the transition time
to calculate system level timing. 图 31 shows the setup used to measure transition time, denoted by the symbol
tTRANSITION
.
VDD
0.1ꢀF
VDD
VDD
ADDRESS
DRIVE
tf < 5ns
tr < 5ns
VIH
S1A
S1B
(VSEL
)
VS
VIL
OUTPUT
RL
D1
D4
0 V
CL
tTRANSITION
tTRANSITION
S4A
S4B
VS
OUTPUT
RL
CL
90%
OUTPUT
SEL
GND
VSEL
10%
0 V
图 31. Transition-Time Measurement Setup
7.6 tON (EN) and tOFF (EN) Time
The tON (EN) time is defined as the time taken by the output of the device to rise to 90% after the enable has fallen
past the logic threshold. The 90% measurement is used to provide the timing of the device being enabled in the
system. 图 32 shows the setup used to measure the enable time, denoted by the symbol tON (EN)
.
The tOFF (EN) time is defined as the time taken by the output of the device to fall to 90% after the enable has fallen
past the logic threshold. The 90% measurement is used to provide the timing of the device being disabled in the
system. 图 32 shows the setup used to measure enable time, denoted by the symbol tOFF (EN)
.
VDD
0.1ꢀF
VDD
VDD
VIH
ENABLE
VIL
DRIVE
(VEN)
S1A
S1B
VS
OUTPUT
RL
D1
D4
tr < 5ns
tf < 5ns
CL
0 V
S4A
S4B
VS
tOFF
tON
(EN)
(EN)
OUTPUT
RL
CL
90%
90%
OUTPUT
0 V
EN
VEN
GND
图 32. tON (EN) and tOFF (EN) Time Measurement Setup
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7.7 tON (VDD) and tOFF (VDD) Time
The tON (VDD) time is defined as the time taken by the output of the device to rise to 90% after the supply has
risen past the supply threshold. The 90% measurement is used to provide the timing of the device turning on in
the system. 图 33 shows the setup used to measure turn on time, denoted by the symbol tON (VDD)
.
the tOFF (VDD) time is defined as the time taken by the output of the device to fall to 90% after the supply has fallen
past the supply threshold. The 90% measurement is used to provide the timing of the device turning off in the
system. 图 33 shows the setup used to measure turn off time, denoted by the symbol tOFF (VDD)
.
VDD
0.1ꢀF
VDD
VDD
VDD
Supply
Ramp
1.5 V
1.5 V
(VDD
)
S1A
S1B
VS
OUTPUT
D1
D4
0 V
CL
RL
tON
tOFF
(VDD)
(VDD)
S4A
S4B
90%
90%
VS
OUTPUT
RL
OUTPUT
0 V
CL
EN
GND
图 33. tON (VDD) and tOFF (VDD)Time Measurement Setup
7.8 Break-Before-Make Delay
Break-before-make delay is a safety feature that prevents two inputs from connecting when the device is
switching. The output first breaks from the on-state switch before making the connection with the next on-state
switch. The time delay between the break and the make is known as break-before-make delay. 图 34 shows the
setup used to measure break-before-make delay, denoted by the symbol tOPEN(BBM)
.
VDD
0.1ꢀF
VDD
VDD
VSEL
0 V
S1A
VS
OUTPUT
RL
D1
D4
tr < 5ns
tf < 5ns
S1B
CL
S4A
S4B
VS
OUTPUT
RL
90%
Output
0 V
tBBM
1
tBBM
2
CL
tOPEN (BBM) = min ( tBBM 1, tBBM 2)
SEL
VSEL
GND
图 34. Break-Before-Make Delay Measurement Setup
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7.9 Propagation Delay
Propagation delay is defined as the time taken by the output of the device to rise or fall 50% after the input signal
has risen or fallen past the 50% threshold. 图 35 shows the setup used to measure propagation delay, denoted
by the symbol tPD
.
VDD
0.1ꢀF
VDD
250 mV
Input
(VS)
S1A
S1B
50%
50%
VS
VS
OUTPUT
D1
0 V
RL
50ꢁ
tPD 1
tPD 2
S4A
S4B
VS
VS
OUTPUT
D4
Output
0 V
50%
50%
RL
50ꢁ
GND
tProp Delay = max ( tPD 1, tPD 2
)
图 35. Propagation Delay Measurement Setup
7.10 Skew
Skew is defined as the difference between propagation delays of any two outputs of the same device. The skew
measurement is taken from the output of one channel rising or falling past 50% to a second channel rising or
falling past the 50% threshold when the input signals are switched at the same time. 图 36 shows the setup used
to measure skew, denoted by the symbol tSK
.
VDD
0.1ꢀF
VDD
S1A
S1B
Output 1
50%
50%
VS
VS
OUTPUT
D1
0 V
RL
50ꢁ
tSK 1
tSK 2
S4A
S4B
VS
VS
OUTPUT
D4
Output 2
0 V
50%
50%
RL
50ꢁ
GND
tSKEW = max ( tSK 1, tSK 2
)
图 36. Skew Measurement Setup
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7.11 Charge Injection
The amount of charge injected into the source or drain of the device during the falling or rising edge of the gate
signal is known as charge injection, and is denoted by the symbol QC. 图 37 shows the setup used to measure
charge injection from source (Sx) to drain (Dx).
VDD
0.1ꢀF
VDD
VDD
S1A
VS
OUTPUT
D1
VOUT
CL
VEN
0 V
S1B
S4A
S4B
VS
Output
VS
OUTPUT
D4
VOUT
CL
VOUT
QC = CL
×
VOUT
EN
VEN
GND
图 37. Charge-Injection Measurement Setup
7.12 Capacitance
The parasitic capacitance of the device is captured at the source (Sx), drain (Dx), and select (SELx) pins. The
capacitance is measured in both the on and off state and is denoted by the symbol CON and COFF. 图 38 shows
the setup used to measure capacitance.
VDD
VDD
S1A
S1B
D1
1 MHz
Capacitance
Meter
Capacitance is measured at SX, DX,
and logic pins during ON and OFF
conditions
S4A
D4
S4B
LOGIC CONTROL
SEL
EN
GND
图 38. Capacitance Measurement Setup
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7.13 Off Isolation
Off isolation is defined as the ratio of the signal at the drain pin (Dx) of the device when a signal is applied to the
source pin (Sx) of an off-channel. The characteristic impedance, Z0, for the measurement is 50 Ω. 图 39 shows
the setup used to measure off isolation. Use off isolation equation to compute off isolation.
0.1µF
NETWORK
VDD
ANALYZER
VS
S
D
50Ω
VSIG
VOUT
RL
SxA / SxB / Dx
50Ω
RL
GND
50Ω
图 39. Off Isolation Measurement Setup
≈
∆
«
’
÷
◊
VOUT
VS
Off Isolation = 20 ∂ Log
(1)
7.14 Channel-to-Channel Crosstalk
Crosstalk is defined as the ratio of the signal at the drain pin (Dx) of a different channel, when a signal is applied
at the source pin (Sx) of an on-channel. The characteristic impedance, Z0, for the measurement is 50 Ω. 图 40
shows the setup used to measure, and the equation used to compute crosstalk.
VDD
0.1µF
NETWORK
VDD
ANALYZER
D1
D4
S1A
VOUT
RL
RL
50Ω
50Ω
VS
S4A
RL
50Ω
50Ω
SxA / SxB / Dx
VSIG = 200 mVpp
VBIAS = VDD / 2
RL
50Ω
GND
图 40. Channel-to-Channel Crosstalk Measurement Setup
≈
∆
«
’
÷
◊
VOUT
VS
Channel-to-Channel Crosstalk = 20 ∂ Log
(2)
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7.15 Bandwidth
Bandwidth is defined as the range of frequencies that are attenuated by less than 3 dB when the input is applied
to the source pin (Sx) of an on-channel, and the output is measured at the drain pin (Dx) of the device. The
characteristic impedance, Z0, for the measurement is 50 Ω. 图 41 shows the setup used to measure bandwidth.
VDD
0.1µF
NETWORK
VDD
ANALYZER
VS
50Ω
S
D
VSIG
VOUT
RL
50Ω
SxA / SxB / Dx
RL
GND
50Ω
图 41. Bandwidth Measurement Setup
#PPAJQ=PEKJ = 20 × .KC (8
)
176
8
5
(3)
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8 Detailed Description
8.1 Overview
The TMUX1574 is a high speed 2:1 (SPDT) 4-ch. switch with powered-off protection up to 3.6 V. Wide
operating supply of 1.5 V to 5.5 V allows for use in a wide array of applications from servers and
communication equipment to industrial applications. The device supports bidirectional analog and digital
signals on the source (SxA, SxB) and drain (Dx) pins. The wide bandwidth of this switch allows little or no
attenuation of high-speed signals at the outputs to pass with minimum edge and phase distortion as well as
propagation delay.
The enable (EN) pin is an active-low logic pin that controls the connection between the source (SxA, SxB)
and drain (Dx) pins of the device. The select pin (SEL) controls the state of all four channels of the
TMUX1574 and determines which source pin is connected to the drain. Fail-Safe Logic circuitry allows
voltages on the logic control pins to be applied before the supply pin, protecting the device from potential
damage. All logic control inputs have 1.8V logic compatible thresholds, ensuring both TTL and CMOS logic
compatibility when operating in the valid supply voltage range.
Powered-off protection up to 3.6 V on the signal path of the TMUX1574 provides isolation when the supply
voltage is removed (VDD = 0 V). Without this protection feature, the system can back-power the supply rail
through an internal ESD diode and cause potential damage to the system.
8.2 Functional Block Diagram
TMUX1574
S1A
D1
S1B
S2A
D2
S2B
S3A
D3
S3B
S4A
D4
S4B
LOGIC CONTROL*
SEL
EN
*Internal 6MO Pull-Down on Logic Pins
8.3 Feature Description
8.3.1 Bidirectional Operation
The TMUX1574 conducts equally well from source (SxA, SxB) to drain (Dx) or from drain (Dx) to source (SxA,
SxB). Each channel has very similar characteristics in both directions and supports both analog and digital
signals.
8.3.2 Beyond Supply Operation
When the TMUX1574 is powered from 1.5 V to 5.5 V, the valid signal path input/output voltage ranges from
GND to VDD x 2, with a maximum input/output voltage of 5.5 V.
Example 1: If the TMUX1574 is powered at 1.5V, the signal range is 0 V to 3 V.
Example 2: If the TMUX1574 is powered at 3V, the signal range is 0 V to 5.5 V.
Example 3: If the TMUX1574 is powered at 5.5V, the signal range is 0 V to 5.5 V.
Other voltage levels not mentioned in the examples support Beyond Supply Operation as long as the supply
voltage falls within the recommended operation conditions of 1.5 V to 5.5 V.
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Feature Description (接下页)
8.3.3 1.8 V Logic Compatible Inputs
The TMUX1574 has 1.8-V logic compatible control inputs. Regardless of the VDD voltage, the control input
thresholds remain fixed, allowing a 1.8-V processor GPIO to control the TMUX1574 without the need for an
external translator. This saves both space and BOM cost. For more information on 1.8 V logic implementations,
refer to Simplifying Design with 1.8 V logic Muxes and Switches.
8.3.4 Powered-off Protection
Powered-off protection up to 3.6 V on the signal path of the TMUX1574 provides isolation when the supply
voltage is removed (VDD = 0 V). When the TMUX1574 is powered-off, the I/Os of the device remain in a high-Z
state. Powered-off protection minimizes system complexity by removing the need for power supply sequencing
on the signal path. The device performance remains within the leakage performance mentioned in the Electrical
Specifications. For more information on powered-off protection, refer to Eliminate Power Sequencing with
Powered-off Protection Signal Switches.
8.3.5 Fail-Safe Logic
The TMUX1574 has Fail-Safe Logic on the control input pins (SELx) which allows for operation up to 5.5 V,
regardless of the state of the supply pin. This feature allows voltages on the control pins to be applied before the
supply pin, protecting the device from potential damage. Fail-Safe Logic minimizes system complexity by
removing the need for power supply sequencing on the logic control pins. For example, the Fail-Safe Logic
feature allows the select pins of the TMUX1574 to be ramped to 5.5 V while VDD = 0 V. Additionally, the feature
enables operation of the TMUX1574 with VDD = 1.5 V while allowing the select pins to interface with a logic level
of another device up to 5.5 V.
8.3.6 Low Capacitance
The TMUX1574 has very low capacitance in both the ON and OFF states on the source and drain pins. Low
capacitance helps to reduce large overshoots and ringing of an amplifier circuit when the switch is connected to
the feedback network. Additionally, low capacitance improves system settling time by reducing the switch time
constant formed by the On-resistance and On-capacitance. For more information on the benefits of low
capacitance refer to Improve Stability Issues with Low CON Multiplexers.
8.3.7 Integrated Pull-Down Resistors
The TMUX1574 has internal weak pull-down resistors (6 MΩ) to GND to ensure the logic pins are not left
floating. This feature integrates up to four external components and reduces system size and cost.
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8.4 Device Functional Modes
The enable (EN) pin is an active-low logic pin that controls the connection between the source (SxA, SxB) and
drain (Dx) pins of the device. When the enable pin is pulled high, all switches are turned off. When the enable is
pulled low, the select pin controls the signal path selection. The select pin (SEL) controls the state of all four
channels of the TMUX1574 and determines which source pin is connected to the drain pins. When the select pin
is pulled low, the SxA pin conducts to the corresponding Dx pins. When the select pin is pulled high, the SxB pin
conducts to the corresponding Dx pins. The TMUX1574 logic pins have internal weak pull-down resistors (6 MΩ)
to GND so that it powers-on in a known state.
The TMUX1574 can be operated without any external components except for the supply decoupling capacitors.
Unused logic control pins should be tied to GND or VDD in order to ensure the device does not consume
additional current as highlighted in Implications of Slow or Floating CMOS Inputs. Unused signal path inputs
(SxA, SxB, or Dx) should be connected to GND.
8.5 Truth Tables
表 1. TMUX1574 Truth Table
INPUTS
Selected Source Pins Connected To Drain Pins (Dx)
EN
SEL
S1A connected to D1
S2A connected to D2
S3A connected to D3
S4A connected to D4
0
0
S1B connected to D1
S2B connected to D2
S3B connected to D3
S4B connected to D4
0
1
1
X(1)
Hi-Z (OFF)
(1) X denotes don't care.
24
版权 © 2018–2019, Texas Instruments Incorporated
TMUX1574
www.ti.com.cn
ZHCSIX6B –OCTOBER 2018–REVISED SEPT 2019
9 Application and Implementation
注
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
9.1 Application Information
The TMUX15xx family offers high-speed system performance across a wide operating supply (1.5 V to 5.5 V)
and operating temperature (-40°C to +125°C). The TMUX1574 supports a number of features that improve
system performance such as 1.8 V logic compatibility, supports input voltages beyond supply, Fail-Safe Logic,
and Powered-off Protection up to 3.6 V. These features make the TMUX15xx a family of protection multiplexers
and switches that can reduce system complexity, board size, and overall system cost.
9.2 Typical Application
Common applications that require the features of the TMUX1574 include multiplexing various protocols from a
possessor or MCU such as SPI, JTAG, or standard GPIO signals. The TMUX1574 provides superior isolation
performance when the device is powered. The added benefit of powered-off protection allows a system to
minimize complexity by eliminating the need for power sequencing in hot-swap and live insertion applications.
The example shown in 图 42 illustrates the use of the TMUX1574 to multiplex an SPI bus to multiple flash
memory devices.
1.8 V
3.3 V
3.3 V
VDD
0.1µF
FLASH Device #1
VI/O
VDD
Processor
S1A
S2A
S3A
S4A
MISO
MOSI
SCLK
SS
D1
D2
D3
D4
RAM
CPU
SPI PORT
FLASH Device #2
S1B
S2B
S3B
S4B
MISO
MOSI
SCLK
SS
Peripherals
1.8V Logic
I/O
SEL
EN
GND
GND
图 42. Multiplexing Flash Memory
9.2.1 Design Requirements
For this design example, use the parameters listed in 表 2.
表 2. Design Parameters
PARAMETERS
Supply (VDD
VALUES
3.3 V
)
Input / Output signal range
Control logic thresholds
0 V to 3.3 V
1.8 V compatible
版权 © 2018–2019, Texas Instruments Incorporated
25
TMUX1574
ZHCSIX6B –OCTOBER 2018–REVISED SEPT 2019
www.ti.com.cn
9.2.2 Detailed Design Procedure
The TMUX1574 can be operated without any external components except for the supply decoupling capacitors.
The TMUX1574 has internal weak pull-down resistors (6 MΩ) to GND so that it powers-on with the switches in a
known state. All inputs signals passing through the switch must fall within the recommend operating conditions of
the TMUX1574 including signal range and continuous current. For this design example, with a supply of 3.3 V,
the signals can range from 0 V to 3.3 V when the device is powered. This example can also utilize the Powered-
off Protection feature and the inputs can range from 0 V to 3.6 V when VDD = 0 V. The max continuous current
can be 25 mA. Due to the voltage range and high speed capability, the TMUX1574 example is suitable for use in
SPI, JTAG, and I2S applications. Refer to Enabling SPI-based flash memory expansion by using multiplexers for
more information on using switches and multiplexers for SPI protocol expansion.
9.2.3 Application Curves
Two important specifications when using a switch or multiplexer to pass signals are the device propagation delay
and skew.
100
90
Propagation Delay - PW
80
70
Propagation Delay - RSV
60
50
40
Skew - PW
Skew - RSV
30
20
10
0
1.5
2
2.5
3
3.5
4
Supply Voltage (V)
4.5
5
5.5
6
D020
图 43. Propagation Delay and Skew Measurement
10 Power Supply Recommendations
The TMUX1574 operates across a wide supply range of 1.5 V to 5.5 V. Do not exceed the absolute maximum
ratings because stresses beyond the listed ratings can cause permanent damage to the devices.
Power-supply bypassing improves noise margin and prevents switching noise propagation from the VDD supply to
other components. Good power-supply decoupling is important to achieve optimum performance. For improved
supply noise immunity, use a supply decoupling capacitor ranging from 0.1 μF to 10 μF from VDD to ground.
Place the bypass capacitors as close to the power supply pins of the device as possible using low-impedance
connections. TI recommends using multi-layer ceramic chip capacitors (MLCCs) that offer low equivalent series
resistance (ESR) and inductance (ESL) characteristics for power-supply decoupling purposes. For very sensitive
systems, or for systems in harsh noise environments, avoiding the use of vias for connecting the capacitors to
the device pins may offer superior noise immunity. The use of multiple vias in parallel lowers the overall
inductance and is beneficial for connections to ground planes.
26
版权 © 2018–2019, Texas Instruments Incorporated
TMUX1574
www.ti.com.cn
ZHCSIX6B –OCTOBER 2018–REVISED SEPT 2019
11 Layout
11.1 Layout Guidelines
When a PCB trace turns a corner at a 90° angle, a reflection can occur. A reflection occurs primarily because of
the change of width of the trace. At the apex of the turn, the trace width increases to 1.414 times the width. This
increase upsets the transmission-line characteristics, especially the distributed capacitance and self–inductance
of the trace which results in the reflection. Not all PCB traces can be straight and therefore some traces must
turn corners.图 44 shows progressively better techniques of rounding corners. Only the last example (BEST)
maintains constant trace width and minimizes reflections.
WORST
BETTER
BEST
1W min.
W
图 44. Trace Example
Route the high-speed signals using a minimum of vias and corners which reduces signal reflections and
impedance changes. When a via must be used, increase the clearance size around it to minimize its
capacitance. Each via introduces discontinuities in the signal’s transmission line and increases the chance of
picking up interference from the other layers of the board. Be careful when designing test points, through-
hole pins are not recommended at high frequencies.
Do not route high speed signal traces under or near crystals, oscillators, clock signal generators, switching
regulators, mounting holes, magnetic devices or ICs that use or duplicate clock signals.
Avoid stubs on the high-speed signals traces because they cause signal reflections.
Route all high-speed signal traces over continuous GND planes, with no interruptions.
Avoid crossing over anti-etch, commonly found with plane splits.
When working with high frequencies, a printed circuit board with at least four layers is recommended; two
signal layers separated by a ground and power layer as shown in 图 45.
Signal 1
GND Plane
Power Plane
Signal 2
图 45. Example Layout
The majority of signal traces must run on a single layer, preferably Signal 1. Immediately next to this layer must
be the GND plane, which is solid with no cuts. Avoid running signal traces across a split in the ground or power
plane. When running across split planes is unavoidable, sufficient decoupling must be used. Minimizing the
number of signal vias reduces EMI by reducing inductance at high frequencies.
图 46 illustrates an example of a PCB layout with the TMUX1574. Some key considerations are:
版权 © 2018–2019, Texas Instruments Incorporated
27
TMUX1574
ZHCSIX6B –OCTOBER 2018–REVISED SEPT 2019
www.ti.com.cn
Layout Guidelines (接下页)
Decouple the VDD pin with a 0.1-μF capacitor, placed as close to the pin as possible. Make sure that the
capacitor voltage rating is sufficient for the VDD supply.
High-speed switches require proper layout and design procedures for optimum performance.
Keep the input lines as short as possible.
Use a solid ground plane to help reduce electromagnetic interference (EMI) noise pickup.
Do not run sensitive analog traces in parallel with digital traces. Avoid crossing digital and analog traces if
possible, and only make perpendicular crossings when necessary.
11.2 Layout Example
Wide (low inductance)
trace for power
Via to GND plane
C
SEL
VDD
EN
S1A
S1B
D1
S4A
S4B
TMUX1574
S2A
D4
S3A
S3B
D3
S2B
D2
GND
图 46. Example Layout
28
版权 © 2018–2019, Texas Instruments Incorporated
TMUX1574
www.ti.com.cn
ZHCSIX6B –OCTOBER 2018–REVISED SEPT 2019
12 器件和文档支持
12.1 文档支持
12.1.1 相关文档
德州仪器 (TI)，《使用低 CON 多路复用器改善稳定性问题》。
德州仪器 (TI)，《通过使用多路复用器实现基于 SPI 的闪存扩展》。
德州仪器 (TI)，《使用 1.8V 逻辑多路复用器和开关简化设计》。
德州仪器 (TI)，《利用关断保护信号开关消除电源排序》。
德州仪器 (TI)，《高电压模拟多路复用器的系统级保护》。
德州仪器 (TI)，《高速接口布局指南》。
德州仪器 (TI)，《高速布局指南》。
德州仪器 (TI)，《QFN/SON PCB 连接》。
德州仪器 (TI)，《四方扁平封装无引线逻辑封装》。
12.2 接收文档更新通知
要接收文档更新通知，请导航至 TI.com.cn 上的器件产品文件夹。单击右上角的通知我 进行注册，即可每周接收产
品信息更改摘要。有关更改的详细信息，请查看任何已修订文档中包含的修订历史记录。
12.3 社区资源
TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help — straight
from the experts. Search existing answers or ask your own question to get the quick design help you need.
Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do
not necessarily reflect TI's views; see TI's Terms of Use.
12.4 商标
E2E is a trademark of Texas Instruments.
12.5 静电放电警告
ESD 可能会损坏该集成电路。德州仪器 (TI) 建议通过适当的预防措施处理所有集成电路。如果不遵守正确的处理措施和安装程序 , 可
能会损坏集成电路。
ESD 的损坏小至导致微小的性能降级 , 大至整个器件故障。 精密的集成电路可能更容易受到损坏 , 这是因为非常细微的参数更改都可
能会导致器件与其发布的规格不相符。
12.6 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
版权 © 2018–2019, Texas Instruments Incorporated
29
TMUX1574
ZHCSIX6B –OCTOBER 2018–REVISED SEPT 2019
www.ti.com.cn
13 机械、封装和可订购信息
以下页面包含机械、封装和可订购信息。这些信息是指定器件的最新可用数据。数据如有变更，恕不另行通知，且
不会对此文档进行修订。如需获取此数据表的浏览器版本，请查阅左侧的导航栏。
30
版权 © 2018–2019, Texas Instruments Incorporated
PACKAGE OPTION ADDENDUM
www.ti.com
4-Oct-2021
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
TMUX1574DYYR
TMUX1574PWR
TMUX1574RSVR
ACTIVE SOT-23-THIN
DYY
PW
16
16
16
3000 RoHS & Green
2000 RoHS & Green
3000 RoHS & Green
NIPDAU
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
-40 to 125
-40 to 125
-40 to 125
TMUX1574
ACTIVE
ACTIVE
TSSOP
UQFN
NIPDAU
MUX1574
1574
RSV
NIPDAUAG
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
4-Oct-2021
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
16-Jun-2023
TAPE AND REEL INFORMATION
REEL DIMENSIONS
TAPE DIMENSIONS
K0
P1
W
B0
Reel
Diameter
Cavity
A0
A0 Dimension designed to accommodate the component width
B0 Dimension designed to accommodate the component length
K0 Dimension designed to accommodate the component thickness
Overall width of the carrier tape
W
P1 Pitch between successive cavity centers
Reel Width (W1)
QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE
Sprocket Holes
Q1 Q2
Q3 Q4
Q1 Q2
Q3 Q4
User Direction of Feed
Pocket Quadrants
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
TMUX1574DYYR
SOT-23-
THIN
DYY
16
3000
330.0
12.4
4.8
3.6
1.6
8.0
12.0
Q3
TMUX1574PWR
TMUX1574RSVR
TSSOP
UQFN
PW
16
16
2000
3000
330.0
178.0
12.4
13.5
6.9
2.1
5.6
2.9
1.6
8.0
4.0
12.0
12.0
Q1
Q1
RSV
0.75
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
16-Jun-2023
TAPE AND REEL BOX DIMENSIONS
Width (mm)
H
W
L
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SPQ
Length (mm) Width (mm) Height (mm)
TMUX1574DYYR
TMUX1574PWR
TMUX1574RSVR
SOT-23-THIN
TSSOP
DYY
PW
16
16
16
3000
2000
3000
336.6
356.0
189.0
336.6
356.0
185.0
31.8
35.0
36.0
UQFN
RSV
Pack Materials-Page 2
PACKAGE OUTLINE
RSV0016A
UQFN - 0.55 mm max height
S
C
A
L
E
5
.
0
0
0
ULTRA THIN QUAD FLATPACK - NO LEAD
1.85
1.75
A
B
PIN 1 INDEX AREA
2.65
2.55
C
0.55
0.45
SEATING PLANE
0.05 C
0.05
0.00
2X 1.2
SYMM
℄
(0.13) TYP
5
8
0.45
0.35
15X
4
9
SYMM
℄
2X 1.2
12X 0.4
1
0.25
16X
12
0.15
0.07
0.05
C A B
13
16
0.55
0.45
PIN 1 ID
(45° X 0.1)
4220314/C 02/2020
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
www.ti.com
EXAMPLE BOARD LAYOUT
RSV0016A
UQFN - 0.55 mm max height
ULTRA THIN QUAD FLATPACK - NO LEAD
SYMM
℄
(0.7)
16
SEE SOLDER MASK
DETAIL
13
12
16X (0.2)
1
SYMM
℄
12X (0.4)
(2.4)
(R0.05) TYP
9
4
15X (0.6)
5
8
(1.6)
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE: 25X
0.05 MIN
ALL AROUND
0.05 MAX
ALL AROUND
METAL UNDER
SOLDER MASK
METAL EDGE
EXPOSED METAL
SOLDER MASK
OPENING
EXPOSED
METAL
SOLDER MASK
OPENING
NON SOLDER MASK
DEFINED
SOLDER MASK DEFINED
(PREFERRED)
SOLDER MASK DETAILS
4220314/C 02/2020
NOTES: (continued)
3. For more information, see Texas Instruments literature number SLUA271 (www.ti.com/lit/slua271).
www.ti.com
EXAMPLE STENCIL DESIGN
RSV0016A
UQFN - 0.55 mm max height
ULTRA THIN QUAD FLATPACK - NO LEAD
(0.7)
16
13
16X (0.2)
1
12
SYMM
℄
12X (0.4)
(2.4)
(R0.05) TYP
4
9
15X (0.6)
5
8
SYMM
℄
(1.6)
SOLDER PASTE EXAMPLE
BASED ON 0.125 MM THICK STENCIL
SCALE: 25X
4220314/C 02/2020
NOTES: (continued)
4. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
www.ti.com
PACKAGE OUTLINE
SOT-23-THIN - 1.1 mm max height
PLASTIC SMALL OUTLINE
DYY0016A
C
3.36
3.16
SEATING PLANE
PIN 1 INDEX
AREA
A
0.1 C
14X 0.5
16
1
4.3
4.1
NOTE 3
2X
3.5
8
9
0.31
16X
0.11
0.1
C A
B
1.1 MAX
2.1
1.9
B
0.2
0.08
TYP
SEE DETAIL A
0.25
GAUGE PLANE
0°- 8°
0.1
0.0
0.63
0.33
DETAIL A
TYP
4224642/B 07/2021
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not exceed
0.15 per side.
4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.50 per side.
5. Reference JEDEC Registration MO-345, Variation AA
www.ti.com
EXAMPLE BOARD LAYOUT
SOT-23-THIN - 1.1 mm max height
PLASTIC SMALL OUTLINE
DYY0016A
16X (1.05)
SYMM
16
1
16X (0.3)
SYMM
14X (0.5)
9
8
(R0.05) TYP
(3)
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE: 20X
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
SOLDER MASK
OPENING
METAL
NON- SOLDER MASK
DEFINED
SOLDER MASK
DEFINED
(PREFERRED)
SOLDER MASK DETAILS
4224642/B 07/2021
NOTES: (continued)
6. Publication IPC-7351 may have alternate designs.
7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
www.ti.com
EXAMPLE STENCIL DESIGN
SOT-23-THIN - 1.1 mm max height
PLASTIC SMALL OUTLINE
DYY0016A
16X (1.05)
SYMM
16
1
16X (0.3)
SYMM
14X (0.5)
9
8
(R0.05) TYP
(3)
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
SCALE: 20X
4224642/B 07/2021
NOTES: (continued)
8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
9. Board assembly site may have different recommendations for stencil design.
www.ti.com
PACKAGE OUTLINE
PW0016A
TSSOP - 1.2 mm max height
S
C
A
L
E
2
.
5
0
0
SMALL OUTLINE PACKAGE
SEATING
PLANE
C
6.6
6.2
TYP
A
0.1 C
PIN 1 INDEX AREA
14X 0.65
16
1
2X
5.1
4.9
4.55
NOTE 3
8
9
0.30
16X
4.5
4.3
NOTE 4
1.2 MAX
0.19
B
0.1
C A B
(0.15) TYP
SEE DETAIL A
0.25
GAGE PLANE
0.15
0.05
0.75
0.50
A
20
0 -8
DETAIL A
TYPICAL
4220204/A 02/2017
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed 0.15 mm per side.
4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.25 mm per side.
5. Reference JEDEC registration MO-153.
www.ti.com
EXAMPLE BOARD LAYOUT
PW0016A
TSSOP - 1.2 mm max height
SMALL OUTLINE PACKAGE
SYMM
16X (1.5)
(R0.05) TYP
16
1
16X (0.45)
SYMM
14X (0.65)
8
9
(5.8)
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE: 10X
METAL UNDER
SOLDER MASK
SOLDER MASK
OPENING
SOLDER MASK
OPENING
METAL
EXPOSED METAL
EXPOSED METAL
0.05 MAX
ALL AROUND
0.05 MIN
ALL AROUND
NON-SOLDER MASK
DEFINED
SOLDER MASK
DEFINED
15.000
(PREFERRED)
SOLDER MASK DETAILS
4220204/A 02/2017
NOTES: (continued)
6. Publication IPC-7351 may have alternate designs.
7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
www.ti.com
EXAMPLE STENCIL DESIGN
PW0016A
TSSOP - 1.2 mm max height
SMALL OUTLINE PACKAGE
16X (1.5)
SYMM
(R0.05) TYP
16
1
16X (0.45)
SYMM
14X (0.65)
8
9
(5.8)
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
SCALE: 10X
4220204/A 02/2017
NOTES: (continued)
8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
9. Board assembly site may have different recommendations for stencil design.
www.ti.com
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