TMUX1134 [TI]
3pA 导通状态泄漏电流、2:1 (SPDT)、4 通道精密模拟开关;
| 型号： | TMUX1134 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 3pA 导通状态泄漏电流、2:1 (SPDT)、4 通道精密模拟开关 开关 光电二极管 |
| 文件： | 总43页 (文件大小：1378K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
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TMUX1133, TMUX1134
ZHCSK01A –JUNE 2019–REVISED AUGUST 2019
TMUX113x 5V、低泄漏电流、2:1 (SPDT)、3 通道或 4 通道精密开关
1 特性
3 说明
1
•
单电源电压范围：1.08V 至 5.5V
双电源电压范围：±2.75V
低泄漏电流：3pA
低电荷注入：-1pC
低导通电阻：2Ω
TMUX113x 器件是具有多个通道的精密互补金属氧化
物半导体 (CMOS) 开关。TMUX1133 是 2:1 单极双投
(SPDT) 开关，具有三个独立控制的通道和一个 EN 引
脚，用于启用或禁用全部三个开关。TMUX1134 包含
四个独立控制的 SPDT 开关。1.08V 至 5.5V 或
±2.75V 双电源的宽电源电压工作范围 可支持 医疗设
备到工业系统的大量应用。该器件可支持源极 (Sx) 和
漏极 (Dx) 引脚上 VSS 到 VDD 范围的双向模拟和数字信
号。对于单电源 应用， VSS 必须连接至 GND。
•
•
•
•
•
•
•
•
•
•
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-40°C 至 +125°C 工作温度
兼容 1.8V 逻辑
失效防护逻辑
轨至轨运行
双向信号路径
所有逻辑输入均具有兼容 1.8V 逻辑的阈值，当器件在
有效电源电压范围内运行时，这些阈值可确保 TTL 和
CMOS 逻辑兼容性。失效防护逻辑 电路允许在电源引
脚之前的控制引脚上施加电压，从而保护器件免受潜在
的损害。
先断后合开关
ESD 保护 HBM：2000V
2 应用
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
现场变送器
TMUX113x 器件是精密开关和多路复用器器件系列中
的一部分。这些器件具有非常低的导通和关断泄漏电流
以及较低的电荷注入，因此可用于高精度测量 应用理
想之选。8nA 的低电源电流
可编程逻辑控制器 (PLC)
工厂自动化和控制
超声波扫描仪
患者监护和诊断
可用于便携式 应用的。
心电图 (ECG)
数据采集系统 (DAQ)
ATE 测试设备
器件信息(1)
器件型号
TMUX1133
TMUX1134
封装
封装尺寸（标称值）
5.00mm × 4.40mm
6.50mm × 4.40mm
电池测试设备
TSSOP (16) (PW)
TSSOP (20) (PW)
仪表：实验室、分析、便携
智能仪表：水表和燃气表
光纤网络
(1) 如需了解所有可用封装，请参阅产品说明书末尾的封装选项附
录。
光学测试设备
便携式 POS
远程无线电单元
有源天线系统 (mMIMIO)
TMUX113x 方框图
TMUX1133
TMUX1134
S1A
S1B
S1A
S1B
D1
D1
SEL1
SEL1
S2A
S2B
D2
S2A
S2B
SEL2
D2
SEL2
S3A
S3B
D3
SEL3
S3A
S3B
D3
S4A
S4B
SEL3
D4
SEL4
EN
1
本文档旨在为方便起见，提供有关 TI 产品中文版本的信息，以确认产品的概要。 有关适用的官方英文版本的最新信息，请访问 www.ti.com，其内容始终优先。 TI 不保证翻译的准确
性和有效性。 在实际设计之前，请务必参考最新版本的英文版本。
English Data Sheet: SCDS412
TMUX1133, TMUX1134
ZHCSK01A –JUNE 2019–REVISED AUGUST 2019
www.ti.com.cn
目录
8.9 Crosstalk ................................................................. 23
8.10 Bandwidth ............................................................. 23
Detailed Description ............................................ 24
9.1 Overview ................................................................. 24
9.2 Functional Block Diagram ....................................... 24
9.3 Feature Description................................................. 24
9.4 Device Functional Modes........................................ 26
9.5 Truth Tables............................................................ 26
1
2
3
4
5
6
7
特性.......................................................................... 1
应用.......................................................................... 1
说明.......................................................................... 1
修订历史记录 ........................................................... 2
Device Comparison Table..................................... 3
Pin Configuration and Functions......................... 3
Specifications......................................................... 5
7.1 Absolute Maximum Ratings ...................................... 5
7.2 ESD Ratings.............................................................. 5
7.3 Recommended Operating Conditions....................... 5
7.4 Thermal Information.................................................. 5
7.5 Electrical Characteristics (VDD = 5 V ±10 %)............ 6
7.6 Electrical Characteristics (VDD = 3.3 V ±10 %)......... 8
9
10 Application and Implementation........................ 27
10.1 Application Information.......................................... 27
10.2 Typical Application ............................................... 27
10.3 Design Requirements............................................ 27
10.4 Detailed Design Procedure ................................... 28
10.5 Application Curve.................................................. 28
11 Power Supply Recommendations ..................... 29
12 Layout................................................................... 29
12.1 Layout Guidelines ................................................. 29
12.2 Layout Example .................................................... 30
13 器件和文档支持 ..................................................... 31
13.1 文档支持................................................................ 31
13.2 相关链接................................................................ 31
13.3 接收文档更新通知 ................................................. 31
13.4 社区资源................................................................ 31
13.5 商标....................................................................... 31
13.6 静电放电警告......................................................... 31
13.7 Glossary................................................................ 31
14 机械、封装和可订购信息....................................... 31
7.7 Electrical Characteristics (VDD = 2.5 V ±10 %), (VSS
=
–2.5 V ±10 %) .......................................................... 10
7.8 Electrical Characteristics (VDD = 1.8 V ±10 %)....... 12
7.9 Electrical Characteristics (VDD = 1.2 V ±10 %)....... 14
7.10 Typical Characteristics.......................................... 16
Parameter Measurement Information ................ 19
8.1 On-Resistance ........................................................ 19
8.2 Off-Leakage Current ............................................... 19
8.3 On-Leakage Current ............................................... 20
8.4 Transition Time ....................................................... 20
8.5 Break-Before-Make................................................. 21
8.6 tON(EN) and tOFF(EN).................................................. 21
8.7 Charge Injection...................................................... 22
8.8 Off Isolation............................................................. 22
8
4 修订历史记录
注：之前版本的页码可能与当前版本有所不同。
Changes from Original (June 2019) to Revision A
Page
•
将器件从预告信息 更改为生产 数据........................................................................................................................................ 1
2
Copyright © 2019, Texas Instruments Incorporated
TMUX1133, TMUX1134
www.ti.com.cn
ZHCSK01A –JUNE 2019–REVISED AUGUST 2019
5 Device Comparison Table
PRODUCT
TMUX1133
TMUX1134
DESCRIPTION
2:1 (SPDT), 3-Channel Switch
2:1 (SPDT), 4-Channel Switch
6 Pin Configuration and Functions
TMUX1133: PW Package
16-Pin TSSOP
Top View
S2B
S2A
S3B
D3
1
2
3
4
5
6
7
8
16
V
DD
15
14
13
12
11
10
9
D2
D1
S1B
S1A
SEL1
SEL2
SEL3
S3A
V
SS
GND
Not to scale
Pin Functions TMUX1133
PIN
TYPE(1)
DESCRIPTION(2)
NAME
S2B
S2A
S3B
D3
NO.
1
I/O
I/O
I/O
I/O
I/O
Source pin 2B. Can be an input or output.
Source pin 2A. Can be an input or output.
Source pin 3B. Can be an input or output.
Drain pin 3. Can be an input or output.
Source pin 3A. Can be an input or output.
2
3
4
S3A
5
Active low logic enable. When this pin is high, all switches are turned off. When this pin is low, the
SELx inputs determine switch connection as shown in 表 1.
EN
6
7
I
Negative power supply. This pin is the most negative power-supply potential. For reliable operation,
connect a decoupling capacitor ranging from 0.1 µF to 10 µF between VSS and GND. VSS must be
connected to ground for single supply voltage applications.
VSS
P
GND
SEL3
SEL2
SEL1
S1A
S1B
D1
8
P
I
Ground (0 V) reference
9
Logic control select pin 3. Controls switch 3 connection as shown in 表 1.
Logic control select pin 2. Controls switch 2connection as shown in 表 1.
Logic control select pin 1. Controls switch 1 connection as shown in 表 1.
Source pin 1A. Can be an input or output.
10
11
12
13
14
15
I
I
I/O
I/O
I/O
I/O
Source pin 1B. Can be an input or output.
Drain pin 1. Can be an input or output.
D2
Drain pin 2. Can be an input or output.
Positive power supply. This pin is the most positive power-supply potential. For reliable operation,
connect a decoupling capacitor ranging from 0.1 µF to 10 µF between VDD and GND.
VDD
16
P
(1) I = input, O = output, I/O = input and output, P = power
(2) Refer to Device Functional Modes for what to do with unused pins
Copyright © 2019, Texas Instruments Incorporated
3
TMUX1133, TMUX1134
ZHCSK01A –JUNE 2019–REVISED AUGUST 2019
www.ti.com.cn
TMUX1134: PW Package
20-Pin TSSOP
Top View
SEL1
S1A
D1
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
SEL4
S4A
D4
S1B
S4B
V
V
SS
DD
GND
S2B
D2
N.C.
S3B
D3
S2A
SEL2
S3A
SEL3
Not to scale
Pin Functions TMUX1134
PIN
TYPE(1)
DESCRIPTION(2)
NAME
SEL1
S1A
NO.
1
I
Logic control select pin 1. Controls switch 1 connection as shown in 表 2.
Source pin 1A. Can be an input or output.
2
I/O
I/O
I/O
D1
3
Drain pin 1. Can be an input or output.
S1B
4
Source pin 1B. Can be an input or output.
Negative power supply. This pin is the most negative power-supply potential. For reliable operation,
connect a decoupling capacitor ranging from 0.1 µF to 10 µF between VSS and GND. VSS must be
connected to ground for single supply voltage applications.
VSS
5
P
GND
S2B
D2
6
7
P
.Ground (0 V) reference.
I/O
Source pin 2B. Can be an input or output.
8
I/O
Drain pin 2. Can be an input or output.
S2A
SEL2
SEL3
S3A
D3
9
I/O
Source pin 2A. Can be an input or output.
10
11
12
13
14
15
I
Logic control select pin 2. Controls switch 2 connection as shown in 表 2.
Logic control select pin 3. Controls switch 3 connection as shown in 表 2.
Source pin 3A. Can be an input or output.
I
I/O
I/O
I/O
Drain pin 3. Can be an input or output.
S3B
N.C.
Source pin 3B. Can be an input or output.
Not Connected
Not Connected. Can be shorted to GND or left floating.
Positive power supply. This pin is the most positive power-supply potential. For reliable operation,
connect a decoupling capacitor ranging from 0.1 µF to 10 µF between VDD and GND.
VDD
16
P
S4B
D4
17
18
19
20
I/O
I/O
I/O
I
Source pin 4B. Can be an input or output.
Drain pin 4. Can be an input or output.
S4A
SEL4
Source pin 4A. Can be an input or output.
Logic control select pin 4. Controls switch 4 connection as shown in 表 2.
(1) I = input, O = output, I/O = input and output, P = power
(2) Refer to Device Functional Modes for what to do with unused pins
4
Copyright © 2019, Texas Instruments Incorporated
TMUX1133, TMUX1134
www.ti.com.cn
ZHCSK01A –JUNE 2019–REVISED AUGUST 2019
7 Specifications
7.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)(1)(2)(3)
MIN
–0.5
–0.5
–3.0
–0.5
–30
MAX
UNIT
V
VDD–VSS
6
VDD
Supply voltage
6
V
VSS
0.3
V
VSEL or VEN
ISEL or IEN
VS or VD
IS or ID (CONT)
Tstg
Logic control input pin voltage (EN, SELx)
Logic control input pin current (EN, SELx)
Source or drain voltage (SxA, SxB, Dx)
Source or drain continuous current (SxA, SxB, Dx)
Storage temperature
6
30
V
mA
V
–0.5
–30
VDD + 0.5
30
mA
°C
°C
–65
150
TJ
Junction temperature
150
(1) Stresses beyond those listed under Absolute Maximum Rating may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Condition. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) The algebraic convention, whereby the most negative value is a minimum and the most positive value is a maximum.
(3) All voltages are with respect to ground, unless otherwise specified.
7.2 ESD Ratings
VALUE
UNIT
Human body model (HBM), per ANSI/ESDA/JEDEC JS-001, all pins(1)
±2000
V(ESD)
Electrostatic discharge
V
Charged device model (CDM), per JEDEC specification JESD22-C101
or ANSI/ESDA/JEDEC JS-002, all pins(2)
±750
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
7.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
MIN
1.08
–2.75
1.08
VSS
NOM
MAX
5.5
0
UNIT
VDD
VSS
Positive power supply voltage (single)
Negative power supply voltage (dual)
V
V
V
V
VDD - VSS Supply rail voltage difference
5.5
VDD
VS or VD
Signal path input/output voltage (source or drain pin) (SxA, SxB, Dx)
VSEL or
VEN
Logic control input pin voltage (EN, SELx)
Ambient temperature
0
5.5
V
TA
–40
125
°C
7.4 Thermal Information
TMUX1133
PW (TSSOP)
16 PINS
120.6
TMUX1134
PW (TSSOP)
16 PINS
102.2
THERMAL METRIC(1)
UNIT
RθJA
Junction-to-ambient thermal resistance
Junction-to-case (top) thermal resistance
Junction-to-board thermal resistance
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
RθJC(top)
RθJB
51.0
43.1
66.8
53.6
ΨJT
Junction-to-top characterization parameter
Junction-to-board characterization parameter
Junction-to-case (bottom) thermal resistance
8.7
6.6
ΨJB
66.2
53.1
RθJC(bot)
N/A
N/A
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
Copyright © 2019, Texas Instruments Incorporated
5
TMUX1133, TMUX1134
ZHCSK01A –JUNE 2019–REVISED AUGUST 2019
www.ti.com.cn
MAX UNIT
7.5 Electrical Characteristics (VDD = 5 V ±10 %)
at TA = 25°C, VDD = 5 V (unless otherwise noted)
PARAMETER
ANALOG SWITCH
TEST CONDITIONS
TA
MIN
TYP
25°C
2
4
4.5
4.9
Ω
Ω
VS = 0 V to VDD
ISD = 10 mA
Refer to On-Resistance
RON
On-resistance
–40°C to +85°C
–40°C to +125°C
25°C
Ω
0.18
0.85
Ω
VS = 0 V to VDD
ISD = 10 mA
Refer to On-Resistance
On-resistance matching between
channels
ΔRON
–40°C to +85°C
–40°C to +125°C
25°C
0.4
0.5
Ω
Ω
Ω
VS = 0 V to VDD
ISD = 10 mA
Refer to On-Resistance
RON
FLAT
On-resistance flatness
–40°C to +85°C
–40°C to +125°C
25°C
1.6
1.6
Ω
Ω
VDD = 5 V
Switch Off
VD = 4.5 V / 1.5 V
VS = 1.5 V / 4.5 V
Refer to Off-Leakage Current
–0.08 ±0.003
–0.3
0.08
0.3
nA
nA
–40°C to +85°C
IS(OFF)
Source off leakage current(1)
–40°C to +125°C
–0.9
0.9
nA
VDD = 5 V
Switch Off
VD = 4.5 V / 1.5 V
VS = 1.5 V / 4.5 V
Refer to Off-Leakage Current
25°C
–0.1 ±0.003
–0.35
0.1
nA
nA
–40°C to +85°C
0.35
ID(OFF) Drain off leakage current(1)
–40°C to +125°C
–2
2
nA
VDD = 5 V
Switch On
VD = VS = 4.5 V / 1.5 V
Refer to On-Leakage Current
25°C
–0.1 ±0.003
–0.35
0.1
nA
nA
ID(ON)
–40°C to +85°C
0.35
Channel on leakage current
IS(ON)
–40°C to +125°C
–2
2
nA
LOGIC INPUTS (EN, SELx)
VIH
VIL
Input logic high
Input logic low
1.49
0
5.5
V
V
–40°C to +125°C
0.87
IIH
IIL
Input leakage current
Input leakage current
25°C
±0.005
µA
µA
IIH
IIL
–40°C to +125°C
±0.05
2
25°C
1
pF
pF
CIN
Logic input capacitance
–40°C to +125°C
POWER SUPPLY
IDD VDD supply current
25°C
0.008
µA
µA
Logic inputs = 0 V or 5.5 V
–40°C to +125°C
1
(1) When VS is 4.5 V, VD is 1.5 V or when VS is 1.5 V, VD is 4.5 V.
6
Copyright © 2019, Texas Instruments Incorporated
TMUX1133, TMUX1134
www.ti.com.cn
ZHCSK01A –JUNE 2019–REVISED AUGUST 2019
Electrical Characteristics (VDD = 5 V ±10 %) (continued)
at TA = 25°C, VDD = 5 V (unless otherwise noted)
PARAMETER
TEST CONDITIONS
TA
MIN
TYP
MAX UNIT
DYNAMIC CHARACTERISTICS
25°C
12
ns
VS = 3 V
tTRAN
Transition time between channels RL = 200 Ω, CL = 15 pF
–40°C to +85°C
–40°C to +125°C
25°C
18
19
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Refer to Transition Time
8
12
6
VS = 3 V
tOPEN
(BBM)
Break before make time
RL = 200 Ω, CL = 15 pF
–40°C to +85°C
–40°C to +125°C
25°C
1
1
Refer to Break-Before-Make
VS = 3 V
RL = 200 Ω, CL = 15 pF
Refer to tON(EN) and tOFF(EN)
Enable turn-on time
(TMUX1133 Only)
tON(EN)
–40°C to +85°C
–40°C to +125°C
25°C
21
22
VS = 3 V
RL = 200 Ω, CL = 15 pF
Refer to tON(EN) and tOFF(EN)
Enable turn-off time
(TMUX1133 Only)
tOFF(EN)
–40°C to +85°C
–40°C to +125°C
11
12
VS = 1 V
QC
Charge Injection
Off Isolation
RS = 0 Ω, CL = 1 nF
Refer to Charge Injection
25°C
25°C
25°C
25°C
–1
–65
pC
dB
dB
dB
RL = 50 Ω, CL = 5 pF
f = 1 MHz
Refer to Off Isolation
OISO
RL = 50 Ω, CL = 5 pF
f = 10 MHz
Refer to Off Isolation
–45
RL = 50 Ω, CL = 5 pF
f = 1 MHz
–100
Refer to Crosstalk
XTALK
Crosstalk
RL = 50 Ω, CL = 5 pF
f = 10 MHz
25°C
25°C
–90
220
dB
Refer to Crosstalk
RL = 50 Ω, CL = 5 pF
Refer to Bandwidth
BW
Bandwidth
MHz
CSOFF
CDOFF
Source off capacitance
Drain off capacitance
f = 1 MHz
f = 1 MHz
25°C
25°C
6
pF
pF
17
CSON
CDON
On capacitance
f = 1 MHz
25°C
20
pF
Copyright © 2019, Texas Instruments Incorporated
7
TMUX1133, TMUX1134
ZHCSK01A –JUNE 2019–REVISED AUGUST 2019
www.ti.com.cn
MAX UNIT
7.6 Electrical Characteristics (VDD = 3.3 V ±10 %)
at TA = 25°C, VDD = 3.3 V (unless otherwise noted)
PARAMETER
ANALOG SWITCH
TEST CONDITIONS
TA
MIN
TYP
25°C
3.7
8.8
9.5
9.8
Ω
Ω
VS = 0 V to VDD
ISD = 10 mA
Refer to On-Resistance
RON
On-resistance
–40°C to +85°C
–40°C to +125°C
25°C
Ω
0.13
Ω
VS = 0 V to VDD
ISD = 10 mA
Refer to On-Resistance
On-resistance matching between
channels
ΔRON
–40°C to +85°C
–40°C to +125°C
25°C
0.4
0.5
Ω
Ω
1.9
2
Ω
VS = 0 V to VDD
ISD = 10 mA
Refer to On-Resistance
RON
FLAT
On-resistance flatness
–40°C to +85°C
–40°C to +125°C
25°C
Ω
2.2
Ω
VDD = 3.3 V
Switch Off
VD = 3 V / 1 V
–0.05 ±0.001
–0.1
0.05
0.1
nA
nA
–40°C to +85°C
IS(OFF)
Source off leakage current(1)
VS = 1 V / 3 V
Refer to Off-Leakage Current
–40°C to +125°C
–0.7
0.7
nA
VDD = 3.3 V
Switch Off
VD = 3 V / 1 V
25°C
–0.1 ±0.005
–0.35
0.1
nA
nA
Drain off leakage current(1)
(TMUX1133 Only)
–40°C to +85°C
0.35
ID(OFF)
VS = 1 V / 3 V
Refer to Off-Leakage Current
–40°C to +125°C
–2
2
nA
VDD = 3.3 V
Switch On
VD = VS = 3 V / 1 V
Refer to On-Leakage Current
25°C
–0.1 ±0.005
–0.35
0.1
nA
nA
ID(ON)
IS(ON)
–40°C to +85°C
0.35
Channel on leakage current
–40°C to +125°C
–2
2
nA
LOGIC INPUTS (EN, SELx)
VIH
VIL
Input logic high
Input logic low
1.35
0
5.5
0.8
V
V
–40°C to +125°C
IIH
IIL
Input leakage current
Input leakage current
25°C
±0.005
µA
µA
IIH
IIL
–40°C to +125°C
±0.05
2
25°C
1
pF
pF
CIN
Logic input capacitance
–40°C to +125°C
POWER SUPPLY
IDD VDD supply current
25°C
0.006
µA
µA
Logic inputs = 0 V or 5.5 V
–40°C to +125°C
1
(1) When VS is 3 V, VD is 1 V or when VS is 1 V, VD is 3 V.
8
Copyright © 2019, Texas Instruments Incorporated
TMUX1133, TMUX1134
www.ti.com.cn
ZHCSK01A –JUNE 2019–REVISED AUGUST 2019
Electrical Characteristics (VDD = 3.3 V ±10 %) (continued)
at TA = 25°C, VDD = 3.3 V (unless otherwise noted)
PARAMETER
TEST CONDITIONS
TA
MIN
TYP
MAX UNIT
DYNAMIC CHARACTERISTICS
25°C
14
ns
VS = 2 V
tTRAN
Transition time between channels RL = 200 Ω, CL = 15 pF
–40°C to +85°C
–40°C to +125°C
25°C
22
22
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Refer to Transition Time
9
15
8
VS = 2 V
tOPEN
(BBM)
Break before make time
RL = 200 Ω, CL = 15 pF
–40°C to +85°C
–40°C to +125°C
25°C
1
1
Refer to Break-Before-Make
VS = 2 V
RL = 200 Ω, CL = 15 pF
Refer to tON(EN) and tOFF(EN)
Enable turn-on time
(TMUX1133 Only)
tON(EN)
–40°C to +85°C
–40°C to +125°C
25°C
22
23
VS = 2 V
RL = 200 Ω, CL = 15 pF
Refer to tON(EN) and tOFF(EN)
Enable turn-off time
(TMUX1133 Only)
tOFF(EN)
–40°C to +85°C
–40°C to +125°C
13
14
VS = 1 V
QC
Charge Injection
Off Isolation
RS = 0 Ω, CL = 1 nF
Refer to Charge Injection
25°C
25°C
25°C
25°C
–1
–65
pC
dB
dB
dB
RL = 50 Ω, CL = 5 pF
f = 1 MHz
Refer to Off Isolation
OISO
RL = 50 Ω, CL = 5 pF
f = 10 MHz
Refer to Off Isolation
–45
RL = 50 Ω, CL = 5 pF
f = 1 MHz
–100
Refer to Crosstalk
XTALK
Crosstalk
RL = 50 Ω, CL = 5 pF
f = 10 MHz
25°C
25°C
–90
220
dB
Refer to Crosstalk
RL = 50 Ω, CL = 5 pF
Refer to Bandwidth
BW
Bandwidth
MHz
CSOFF
CDOFF
Source off capacitance
Drain off capacitance
f = 1 MHz
f = 1 MHz
25°C
25°C
6
pF
pF
17
CSON
CDON
On capacitance
f = 1 MHz
25°C
20
pF
Copyright © 2019, Texas Instruments Incorporated
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MAX UNIT
7.7 Electrical Characteristics (VDD = 2.5 V ±10 %), (VSS = –2.5 V ±10 %)
at TA = 25°C, VDD = +2.5 V, VSS = –2.5 V (unless otherwise noted)
PARAMETER
ANALOG SWITCH
TEST CONDITIONS
TA
MIN
TYP
25°C
2
4
4.5
4.9
Ω
Ω
VS = VSS to VDD
ISD = 10 mA
Refer to On-Resistance
RON
On-resistance
–40°C to +85°C
–40°C to +125°C
25°C
Ω
0.18
0.85
Ω
VS = VSS to VDD
ISD = 10 mA
Refer to On-Resistance
On-resistance matching between
channels
ΔRON
–40°C to +85°C
–40°C to +125°C
25°C
0.4
0.5
Ω
Ω
Ω
VS = VSS to VDD
ISD = 10 mA
Refer to On-Resistance
RON
FLAT
On-resistance flatness
–40°C to +85°C
–40°C to +125°C
25°C
1.6
1.6
Ω
Ω
VDD = +2.5 V, VSS = –2.5 V
Switch Off
VD = +2 V / –1 V
–0.08 ±0.005
–0.3
0.08
0.3
nA
nA
–40°C to +85°C
IS(OFF)
Source off leakage current(1)
VS = –1 V / +2 V
Refer to Off-Leakage Current
–40°C to +125°C
–0.9
0.9
nA
VDD = +2.5 V, VSS = –2.5 V
Switch Off
VD = +2 V / –1 V
VS = –1 V / +2 V
Refer to Off-Leakage Current
25°C
–0.1
±0.01
±0.01
0.1
nA
nA
–40°C to +85°C
–0.35
0.35
ID(OFF) Drain off leakage current(1)
–40°C to +125°C
–2
2
nA
VDD = +2.5 V, VSS = –2.5 V
Switch On
VD = VS = +2 V / –1 V
Refer to On-Leakage Current
25°C
–0.1
0.1
nA
nA
ID(ON)
–40°C to +85°C
–0.35
0.35
Channel on leakage current
IS(ON)
–40°C to +125°C
–2
2
nA
LOGIC INPUTS (EN, SELx)
VIH
VIL
Input logic high
Input logic low
1.2
0
2.75
0.73
V
V
–40°C to +125°C
IIH
IIL
Input leakage current
Input leakage current
25°C
±0.005
1
µA
µA
IIH
IIL
–40°C to +125°C
±0.05
2
25°C
pF
pF
CIN
Logic input capacitance
–40°C to +125°C
POWER SUPPLY
IDD VDD supply current
25°C
0.008
0.008
µA
µA
µA
µA
Logic inputs = 0 V or 2.75 V
Logic inputs = 0 V or 2.75 V
–40°C to +125°C
25°C
1
1
ISS
VSS supply current
–40°C to +125°C
(1) When VS is positive, VD is negative or when VS is negative, VD is positive.
10
Copyright © 2019, Texas Instruments Incorporated
TMUX1133, TMUX1134
www.ti.com.cn
ZHCSK01A –JUNE 2019–REVISED AUGUST 2019
Electrical Characteristics (VDD = 2.5 V ±10 %), (VSS = –2.5 V ±10 %) (continued)
at TA = 25°C, VDD = +2.5 V, VSS = –2.5 V (unless otherwise noted)
PARAMETER
TEST CONDITIONS
TA
MIN
TYP
MAX UNIT
DYNAMIC CHARACTERISTICS
25°C
12
ns
VS = 1.5 V
tTRAN
Transition time between channels RL = 200 Ω, CL = 15 pF
–40°C to +85°C
–40°C to +125°C
25°C
20
21
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Refer to Transition Time
8
12
6
VS = 1.5 V
tOPEN
(BBM)
Break before make time
RL = 200 Ω, CL = 15 pF
–40°C to +85°C
–40°C to +125°C
25°C
1
1
Refer to Break-Before-Make
VS = 1.5 V
RL = 200 Ω, CL = 15 pF
Refer to tON(EN) and tOFF(EN)
Enable turn-on time
(TMUX1133 Only)
tON(EN)
–40°C to +85°C
–40°C to +125°C
25°C
21
22
VS = 1.5 V
RL = 200 Ω, CL = 15 pF
Refer to tON(EN) and tOFF(EN)
Enable turn-off time
(TMUX1133 Only)
tOFF(EN)
–40°C to +85°C
–40°C to +125°C
14
15
VS = –1 V
QC
Charge Injection
Off Isolation
RS = 0 Ω, CL = 1 nF
Refer to Charge Injection
25°C
25°C
25°C
25°C
–1
–65
pC
dB
dB
dB
RL = 50 Ω, CL = 5 pF
f = 1 MHz
Refer to Off Isolation
OISO
RL = 50 Ω, CL = 5 pF
f = 10 MHz
Refer to Off Isolation
–45
RL = 50 Ω, CL = 5 pF
f = 1 MHz
–100
Refer to Crosstalk
XTALK
Crosstalk
RL = 50 Ω, CL = 5 pF
f = 10 MHz
25°C
25°C
–90
220
dB
Refer to Crosstalk
RL = 50 Ω, CL = 5 pF
Refer to Bandwidth
BW
Bandwidth
MHz
CSOFF
CDOFF
Source off capacitance
Drain off capacitance
f = 1 MHz
f = 1 MHz
25°C
25°C
6
pF
pF
17
CSON
CDON
On capacitance
f = 1 MHz
25°C
20
pF
Copyright © 2019, Texas Instruments Incorporated
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7.8 Electrical Characteristics (VDD = 1.8 V ±10 %)
at TA = 25°C, VDD = 1.8 V (unless otherwise noted)
PARAMETER
ANALOG SWITCH
TEST CONDITIONS
TA
MIN
TYP
MAX UNIT
25°C
40
Ω
VS = 0 V to VDD
RON
On-resistance
ISD = 10 mA
Refer to On-Resistance
–40°C to +85°C
–40°C to +125°C
25°C
80
80
Ω
Ω
0.4
Ω
VS = 0 V to VDD
ISD = 10 mA
Refer to On-Resistance
On-resistance matching between
channels
ΔRON
–40°C to +85°C
–40°C to +125°C
25°C
1.5
1.5
Ω
Ω
VDD = 1.98 V
Switch Off
VD = 1.62 V / 1 V
VS = 1 V / 1.62 V
Refer to Off-Leakage Current
–0.05 ±0.003
–0.1
0.05
0.1
nA
nA
–40°C to +85°C
IS(OFF)
Source off leakage current(1)
–40°C to +125°C
–0.5
0.5
nA
VDD = 1.98 V
Switch Off
VD = 1.62 V / 1 V
VS = 1 V / 1.62 V
Refer to Off-Leakage Current
25°C
–0.1 ±0.005
–0.5
0.1
0.5
nA
nA
–40°C to +85°C
ID(OFF) Drain off leakage current(1)
–40°C to +125°C
–2
2
nA
VDD = 1.98 V
Switch On
VD = VS = 1.62 V / 1 V
Refer to On-Leakage Current
25°C
–0.1 ±0.005
–0.5
0.1
0.5
nA
nA
ID(ON)
–40°C to +85°C
Channel on leakage current
IS(ON)
–40°C to +125°C
–2
2
nA
LOGIC INPUTS (EN, SELx)
VIH
VIL
Input logic high
Input logic low
1.07
0
5.5
V
V
–40°C to +125°C
0.68
IIH
IIL
Input leakage current
Input leakage current
25°C
±0.005
µA
µA
IIH
IIL
–40°C to +125°C
±0.05
2
25°C
1
pF
pF
CIN
Logic input capacitance
–40°C to +125°C
POWER SUPPLY
IDD VDD supply current
25°C
0.001
µA
µA
Logic inputs = 0 V or 5.5 V
–40°C to +125°C
0.85
(1) When VS is 1.62 V, VD is 1 V or when VS is 1 V, VD is 1.62 V.
12
Copyright © 2019, Texas Instruments Incorporated
TMUX1133, TMUX1134
www.ti.com.cn
ZHCSK01A –JUNE 2019–REVISED AUGUST 2019
Electrical Characteristics (VDD = 1.8 V ±10 %) (continued)
at TA = 25°C, VDD = 1.8 V (unless otherwise noted)
PARAMETER
TEST CONDITIONS
TA
MIN
TYP
MAX UNIT
DYNAMIC CHARACTERISTICS
25°C
28
ns
VS = 1 V
tTRAN
Transition time between channels RL = 200 Ω, CL = 15 pF
–40°C to +85°C
–40°C to +125°C
25°C
48
48
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Refer to Transition Time
16
28
16
VS = 1 V
tOPEN
(BBM)
Break before make time
RL = 200 Ω, CL = 15 pF
–40°C to +85°C
–40°C to +125°C
25°C
1
1
Refer to Break-Before-Make
VS = 1 V
RL = 200 Ω, CL = 15 pF
Refer to tON(EN) and tOFF(EN)
Enable turn-on time
(TMUX1133 Only)
tON(EN)
–40°C to +85°C
–40°C to +125°C
25°C
48
48
VS = 1 V
RL = 200 Ω, CL = 15 pF
Refer to tON(EN) and tOFF(EN)
Enable turn-off time
(TMUX1133 Only)
tOFF(EN)
–40°C to +85°C
–40°C to +125°C
27
27
VS = 1 V
QC
Charge Injection
Off Isolation
RS = 0 Ω, CL = 1 nF
Refer to Charge Injection
25°C
25°C
25°C
25°C
–1
–65
pC
dB
dB
dB
RL = 50 Ω, CL = 5 pF
f = 1 MHz
Refer to Off Isolation
OISO
RL = 50 Ω, CL = 5 pF
f = 10 MHz
Refer to Off Isolation
–45
RL = 50 Ω, CL = 5 pF
f = 1 MHz
–100
Refer to Crosstalk
XTALK
Crosstalk
RL = 50 Ω, CL = 5 pF
f = 10 MHz
25°C
25°C
–90
220
dB
Refer to Crosstalk
RL = 50 Ω, CL = 5 pF
Refer to Bandwidth
BW
Bandwidth
MHz
CSOFF
CDOFF
Source off capacitance
Drain off capacitance
f = 1 MHz
f = 1 MHz
25°C
25°C
6
pF
pF
17
CSON
CDON
On capacitance
f = 1 MHz
25°C
20
pF
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www.ti.com.cn
7.9 Electrical Characteristics (VDD = 1.2 V ±10 %)
PARAMETER
TEST CONDITIONS
TA
MIN
TYP
MAX UNIT
ANALOG SWITCH
25°C
70
Ω
VS = 0 V to VDD
RON
On-resistance
ISD = 10 mA
Refer to On-Resistance
–40°C to +85°C
–40°C to +125°C
25°C
105
105
Ω
Ω
0.4
Ω
VS = 0 V to VDD
ISD = 10 mA
Refer to On-Resistance
On-resistance matching between
channels
ΔRON
–40°C to +85°C
–40°C to +125°C
25°C
1.5
1.5
Ω
Ω
VDD = 1.32 V
Switch Off
VD = 1 V / 0.8 V
VS = 0.8 V / 1 V
Refer to Off-Leakage Current
–0.05 ±0.003
–0.1
0.05
0.1
nA
nA
–40°C to +85°C
IS(OFF)
Source off leakage current(1)
–40°C to +125°C
–0.5
0.5
nA
VDD = 1.32 V
Switch Off
VD = 1 V / 0.8 V
VS = 0.8 V / 1 V
Refer to Off-Leakage Current
25°C
–0.1 ±0.005
–0.5
0.1
0.5
nA
nA
–40°C to +85°C
ID(OFF) Drain off leakage current(1)
–40°C to +125°C
–2
2
nA
VDD = 1.32 V
Switch On
VD = VS = 1 V / 0.8 V
Refer to On-Leakage Current
25°C
–0.1 ±0.005
–0.5
0.1
0.5
nA
nA
ID(ON)
–40°C to +85°C
Channel on leakage current
IS(ON)
–40°C to +125°C
–2
2
nA
LOGIC INPUTS (EN, SELx)
VIH
VIL
Input logic high
Input logic low
0.96
0
5.5
V
V
–40°C to +125°C
0.36
IIH
IIL
Input leakage current
Input leakage current
25°C
±0.005
µA
µA
IIH
IIL
–40°C to +125°C
±0.05
2
25°C
1
pF
pF
CIN
Logic input capacitance
–40°C to +125°C
POWER SUPPLY
IDD VDD supply current
25°C
0.001
µA
µA
Logic inputs = 0 V or 5.5 V
–40°C to +125°C
0.7
(1) When VS is 1 V, VD is 0.8 V or when VS is 0.8 V, VD is 1 V.
14
Copyright © 2019, Texas Instruments Incorporated
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ZHCSK01A –JUNE 2019–REVISED AUGUST 2019
Electrical Characteristics (VDD = 1.2 V ±10 %) (continued)
PARAMETER
TEST CONDITIONS
TA
MIN
TYP
MAX UNIT
DYNAMIC CHARACTERISTICS
25°C
55
ns
VS = 1 V
tTRAN
Transition time between channels RL = 200 Ω, CL = 15 pF
–40°C to +85°C
–40°C to +125°C
25°C
201
201
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Refer to Transition Time
28
60
45
VS = 1 V
tOPEN
(BBM)
Break before make time
RL = 200 Ω, CL = 15 pF
–40°C to +85°C
–40°C to +125°C
25°C
1
1
Refer to Break-Before-Make
VS = 1 V
RL = 200 Ω, CL = 15 pF
Refer to tON(EN) and tOFF(EN)
Enable turn-on time
(TMUX1133 Only)
tON(EN)
–40°C to +85°C
–40°C to +125°C
25°C
201
201
VS = 1 V
RL = 200 Ω, CL = 15 pF
Refer to tON(EN) and tOFF(EN)
Enable turn-off time
(TMUX1133 Only)
tOFF(EN)
–40°C to +85°C
–40°C to +125°C
150
150
VS = 1 V
QC
Charge Injection
Off Isolation
RS = 0 Ω, CL = 1 nF
Refer to Charge Injection
25°C
25°C
25°C
25°C
–1
–65
pC
dB
dB
dB
RL = 50 Ω, CL = 5 pF
f = 1 MHz
Refer to Off Isolation
OISO
RL = 50 Ω, CL = 5 pF
f = 10 MHz
Refer to Off Isolation
–45
RL = 50 Ω, CL = 5 pF
f = 1 MHz
–100
Refer to Crosstalk
XTALK
Crosstalk
RL = 50 Ω, CL = 5 pF
f = 10 MHz
25°C
25°C
–90
220
dB
Refer to Crosstalk
RL = 50 Ω, CL = 5 pF
Refer to Bandwidth
BW
Bandwidth
MHz
CSOFF
CDOFF
Source off capacitance
Drain off capacitance
f = 1 MHz
f = 1 MHz
25°C
25°C
6
pF
pF
17
CSON
CDON
On capacitance
f = 1 MHz
25°C
20
pF
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www.ti.com.cn
7.10 Typical Characteristics
at TA = 25°C, VDD = 5 V (unless otherwise noted)
6
5
4.5
4
VDD = 3 V
5
TA = 85èC
TA = 125èC
VDD = 3.63 V
3.5
3
4
VDD = 4.5 V
3
2.5
2
VDD = 5.5 V
2
1
0
1.5
1
TA = -40èC
TA = 25èC
0.5
0
0
1
2
VS or VD - Source or Drain Voltage (V)
3
4
5
5.5
0
1
2
VS or VD - Source or Drain Voltage (V)
3
4
5
D001
D002
TA = 25°C
VDD = 5 V
图 1. On-Resistance vs Source or Drain Voltage
图 2. On-Resistance vs Temperature
TA = 85èC TA = 125èC
4.5
8
7
6
5
4
3
2
1
0
4
3.5
3
VDD = 2.25V
VSS = -2.25V
VDD = 2.5V
VSS = -2.5V
2.5
2
1.5
1
VDD = 2.75V
VSS = -2.75V
0.5
TA = 25èC
2.5
VS or VD - Source or Drain Voltage (V)
TA = -40èC
0
-3
-2
-1
VS or VD - Source or Drain Voltage (V)
0
1
2
3
0
0.5
1
1.5
2
3
3.5
D003
D004
VDD = ±2.5 V
VDD = 3.3 V
图 3. On-Resistance vs Temperature
图 4. On-Resistance vs Temperature
80
70
60
50
40
30
20
10
0
40
30
VDD = 1.08 V
VDD = 1.32 V
20
VDD = 1.32 V
VDD = 1.98 V
VDD = 3.63 V
10
VDD = 1.62 V
0
-10
-20
-30
-40
VDD = 1.98 V
0
0.2 0.4 0.6 0.8
1
VS or VD - Source or Drain Voltage (V)
1.2 1.4 1.6 1.8
2
0
0.5
1
1.5
2
VS or VD - Source or Drain Voltage (V)
2.5
3
3.5
4
D005
D006
TA = 25°C
TA = 25°C
图 5. On-Resistance vs Source or Drain Voltage
图 6. On-Leakage vs Source or Drain Voltage
16
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ZHCSK01A –JUNE 2019–REVISED AUGUST 2019
Typical Characteristics (接下页)
100
3
2
80
60
IS(OFF)
VDD = 2.5V
SS = -2.5V
VDD = 5V
SS = 0V
40
20
1
V
V
0
0
-20
-40
-60
-80
-100
-1
-2
-3
IS(ON)
-3
-2
-1
0
1
2
3
VS or VD - Source or Drain Voltage (V)
4
5
-40
-20
0
20
40
60
80
100
120
Temperature (èC)
D007
D008
VDD = 5 V
VDD = 3.3 V
图 7. On-Leakage vs Source or Drain Voltage
图 8. Leakage Current vs Temperature
3
2
0.6
0.5
0.4
0.3
0.2
0.1
0
VDD = 5 V
IS(OFF)
1
VDD = 3.3 V
VDD = 1.8 V
0
-1
-2
-3
IS(ON)
VDD = 1.2 V
-0.1
-40
-20
0
20
40
60
80
100
120
-40
-20
0
20
40
60
80
100 120 140
Temperature (èC)
Temperature (èC)
D009
D010
VDD = 5 V
VSEL = VDD
图 9. Leakage Current vs Temperature
图 10. Supply Current vs Temperature
1600
1400
1200
1000
800
600
400
200
0
20
15
10
5
VDD = 5 V
VDD = 3.3 V
VDD 2.5 V
VDD = 1.8 V
=
VDD = 3.3 V
VSS = 0 V
0
-5
VDD = +2.5 V
VSS = -2.5 V
-10
-15
-20
VDD = 5 V
VSS = 0 V
0
0.5
1
1.5
2
Logic Voltage (V)
2.5
3
3.5
4
4.5
5
-3
-2
-1
0
Source Voltage (V)
1
2
3
4
5
D011
D012
TA = 25°C
TA = -40°C to 125°C
图 11. Supply Current vs Logic Voltage
图 12. Charge Injection vs Source Voltage
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Typical Characteristics (接下页)
10
10
0
8
-10
-20
-30
-40
-50
-60
-70
-80
-90
-100
-110
-120
-130
Off-Isolation
6
4
VDD = 1.2V
2
0
-2
-4
VDD = 1.8 V
Crosstalk
-6
-8
-10
0
0.25
0.5
0.75
1
1.25
Source Voltage (V)
1.5
1.75
2
100k
1M
10M
Frequency (Hz)
100M
D013
D014
TA = -40°C to 125°C
TA = -40°C to +125°C
图 13. Charge Injection vs Source Voltage
图 14. Xtalk and Off-Isolation vs Frequency
0
-1
-2
-3
-4
-5
-6
1M
10M
Frequency (Hz)
100M
D015
TA = -40°C to +125°C
图 15. On Response vs Frequency
18
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8 Parameter Measurement Information
8.1 On-Resistance
The on-resistance of a device is the ohmic resistance between the source (Sx) and drain (Dx) pins of the device.
The on-resistance varies with input voltage and supply voltage. The symbol RON is used to denote on-resistance.
The measurement setup used to measure RON is shown in 图 16. Voltage (V) and current (ISD) are measured
using this setup, and RON is computed with RON = V / ISD
:
V
ISD
Sx
D
VS
图 16. On-Resistance Measurement Setup
8.2 Off-Leakage Current
There are two types of leakage currents associated with a switch during the off state:
1. Source off-leakage current
2. Drain off-leakage current
Source leakage current is defined as the leakage current flowing into or out of the source pin when the switch is
off. This current is denoted by the symbol IS(OFF)
.
Drain leakage current is defined as the leakage current flowing into or out of the drain pin when the switch is off.
This current is denoted by the symbol ID(OFF)
.
The setup used to measure both off-leakage currents is shown in 图 17.
VDD
VSS
VDD
VSS
0.1…F
0.1…F
0.1…F
0.1…F
Is (OFF)
ID (OFF)
S1A
S1B
S1A
S1B
A
D1
D1
A
VS
VD
VD
VS
VD
Is (OFF)
ID (OFF)
A
S4A
S4B
S4A
S4B
A
D4
D4
VS
VD
VD
VD
VS
GND
GND
图 17. Off-Leakage Measurement Setup
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8.3 On-Leakage Current
Source on-leakage current is defined as the leakage current flowing into or out of the source pin when the switch
is on. This current is denoted by the symbol IS(ON)
.
Drain on-leakage current is defined as the leakage current flowing into or out of the drain pin when the switch is
on. This current is denoted by the symbol ID(ON)
.
Either the source pin or drain pin is left floating during the measurement. 图 18 shows the circuit used for
measuring the on-leakage current, denoted by IS(ON) or ID(ON)
.
VDD
VSS
VDD
VSS
0.1…F
0.1…F
0.1…F
IS (ON)
0.1…F
ID (ON)
S1A
S1B
S1A
A
N.C.
N.C.
D1
D1
A
N.C.
S1B
N.C.
VS
VD
IS (ON)
ID (ON)
A
S4A
S4B
S4A
S4B
N.C.
N.C.
A
D4
D4
N.C.
N.C.
VS
VD
GND
GND
图 18. On-Leakage Measurement Setup
8.4 Transition Time
Transition time is defined as the time taken by the output of the device to rise or fall 10% after the address signal
has risen or fallen past the logic threshold. The 10% transition measurement is utilized to provide the timing of
the device. System level timing can then account for the time constant added from the load resistance and load
capacitance. 图 19 shows the setup used to measure transition time, denoted by the symbol tTRANSITION
.
VDD
VSS
0.1…F
0.1…F
VDD
Logic
Control
(VSEL
tf < 5ns
tr < 5ns
VIH
S1A
)
VS
VIL
OUTPUT
D1
0 V
S1B
CL
RL
tTRANSITION
tTRANSITION
S4A
S4B
VS
OUTPUT
RL
D4
CL
90%
OUTPUT
SELx
GND
VSEL
10%
0 V
图 19. Transition-Time Measurement Setup
20
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8.5 Break-Before-Make
Break-before-make delay is a safety feature that prevents two inputs from connecting when the device is
switching. The output first breaks from the on-state switch before making the connection with the next on-state
switch. The time delay between the break and the make is known as break-before-make delay. 图 20 shows the
setup used to measure break-before-make delay, denoted by the symbol tOPEN(BBM)
.
VDD
VSS
0.1…F
0.1…F
VDD
VSEL
0 V
S1A
VS
OUTPUT
D1
D4
tr < 5ns
tf < 5ns
S1B
CL
RL
S4A
S4B
VS
OUTPUT
RL
90%
Output
0 V
tBBM
1
tBBM
2
CL
tOPEN (BBM) = min ( tBBM 1, tBBM 2)
SELx
VSEL
GND
图 20. Break-Before-Make Delay Measurement Setup
8.6 tON(EN) and tOFF(EN)
Turn-on time is defined as the time taken by the output of the device to rise to 10% after the enable has risen
past the logic threshold. The 10% measurement is utilized to provide the timing of the device. System level
timing can then account for the time constant added from the load resistance and load capacitance. 图 21 shows
the setup used to measure turn-on time, denoted by the symbol tON(EN)
.
Turn-off time is defined as the time taken by the output of the device to fall to 90% after the enable has fallen
past the logic threshold. The 90% measurement is utilized to provide the timing of the device. System level
timing can then account for the time constant added from the load resistance and load capacitance. 图 21 shows
the setup used to measure turn-off time, denoted by the symbol tOFF(EN)
.
VDD
VSS
0.1…F
0.1…F
VDD
VIH
Enable
Control
VIL
S1A
S1B
VS
OUTPUT
D1
D4
(VEN
)
tr < 5ns
tf < 5ns
CL
RL
0 V
S4A
S4B
VS
tOFF
tON
(EN)
(EN)
OUTPUT
RL
CL
90%
90%
OUTPUT
0 V
EN
VEN
GND
图 21. Turn-On and Turn-Off Time Measurement Setup
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8.7 Charge Injection
The TMUX1133 has a transmission-gate topology. Any mismatch in capacitance between the NMOS and PMOS
transistors results in a charge injected into the drain or source during the falling or rising edge of the gate signal.
The amount of charge injected into the source or drain of the device is known as charge injection, and is denoted
by the symbol QC. 图 22 shows the setup used to measure charge injection from source (Sx) to drain (D).
VDD
VSS
0.1…F
0.1…F
VDD
VEN
0 V
S1A
VS
OUTPUT
D1
D4
VOUT
CL
S1B
S4A
S4B
VS
Output
VS
OUTPUT
VOUT
CL
VOUT
QC = CL
×
VOUT
EN
VEN
GND
图 22. Charge-Injection Measurement Setup
8.8 Off Isolation
Off isolation is defined as the ratio of the signal at the drain pin (D) of the device when a signal is applied to the
source pin (Sx) of an off-channel. 图 23 shows the setup used to measure, and the equation used to calculate off
isolation.
VDD
VSS
0.1µF
0.1µF
NETWORK
ANALYZER
VS
S
D
50Ω
VSIG
VOUT
RL
SxA / SxB / Dx
50Ω
RL
GND
50Ω
图 23. Off Isolation Measurement Setup
≈
∆
«
’
÷
◊
VOUT
VS
Off Isolation = 20 ∂ Log
(1)
22
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8.9 Crosstalk
Crosstalk is defined as the ratio of the signal at the drain pin (D) of a different channel, when a signal is applied
at the source pin (Sx) of an on-channel. 图 24 shows the setup used to measure, and the equation used to
calculate crosstalk.
VDD
VSS
0.1µF
0.1µF
NETWORK
ANALYZER
D1
D4
S1A
S4A
VOUT
RL
RL
50Ω
50Ω
VS
RL
50Ω
50Ω
SxA / SxB / Dx
VSIG = 200 mVpp
VBIAS = VDD / 2
RL
50Ω
GND
图 24. Crosstalk Measurement Setup
≈
∆
«
’
÷
◊
VOUT
VS
Channel-to-Channel Crosstalk = 20 ∂ Log
(2)
8.10 Bandwidth
Bandwidth is defined as the range of frequencies that are attenuated by less than 3 dB when the input is applied
to the source pin (Sx) of an on-channel, and the output is measured at the drain pin (D) of the device. 图 25
shows the setup used to measure bandwidth.
VDD
VSS
0.1µF
0.1µF
NETWORK
ANALYZER
VS
S
D
50Ω
VSIG
VOUT
RL
SxA / SxB / Dx
50Ω
RL
GND
50Ω
图 25. Bandwidth Measurement Setup
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9 Detailed Description
9.1 Overview
The TMUX1133 contains three independently controlled single-pole double-throw (SPDT) switches and has an
active low EN pin to enable or disable all three switches simultaneously. The TMUX1134 contains four
independently controlled SPDT switches.
9.2 Functional Block Diagram
TMUX1133
TMUX1134
S1A
S1B
S1A
S1B
D1
D1
SEL1
SEL1
S2A
S2B
D2
S2A
S2B
SEL2
D2
SEL2
S3A
S3B
D3
SEL3
S3A
S3B
D3
S4A
S4B
SEL3
D4
SEL4
EN
图 26. TMUX1133 Functional Block Diagram
9.3 Feature Description
9.3.1 Bidirectional Operation
The TMUX113x devices conduct equally well from source (Sx) to drain (Dx) or from drain (Dx) to source (Sx).
Each channel has very similar characteristics in both directions and supports both analog and digital signals.
9.3.2 Rail to Rail Operation
The valid signal path input/output voltage for TMUX113x ranges from VSS to VDD. For single supply applications
VSS can be connected to GND.
9.3.3 1.8 V Logic Compatible Inputs
The TMUX113x devices have 1.8-V logic compatible control for all logic control inputs. The logic input thresholds
scale with supply but still provide 1.8-V logic control when operating at 5.5 V supply voltage. 1.8-V logic level
inputs allows the TMUX113x devices to interface with processors that have lower logic I/O rails and eliminates
the need for an external translator, which saves both space and BOM cost. The current consumption of the
TMUX113x devices increase when using 1.8V logic with higher supply voltage as shown in 图 11. For more
information on 1.8 V logic implementations refer to Simplifying Design with 1.8 V logic Muxes and Switches
9.3.4 Fail-Safe Logic
The TMUX113x devices support Fail-Safe Logic on the control input pins (SELx and EN) allowing for operation
up to 5.5 V, regardless of the state of the supply pins. This feature allows voltages on the control pins to be
applied before the supply pins, protecting the device from potential damage. Fail-Safe Logic minimizes system
complexity by removing the need for power supply sequencing on the logic control pins. For example, the Fail-
Safe Logic feature allows the select pins of the TMUX113x devices to be ramped to 5.5 V while VDD = 0 V.
Additionally, the feature enables operation of the TMUX113x devices with VDD = 1.2 V while allowing the select
pins to interface with a logic level of another device up to 5.5 V.
24
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Feature Description (接下页)
9.3.5 Ultra-low Leakage Current
The TMUX1133 and TMUX1134 provide extremely low on-leakage and off-leakage currents. The TMUX113x
devices are capable of switching signals from high source-impedance inputs into a high input-impedance op amp
with minimal offset error because of the ultra-low leakage currents. 图 27 shows typical leakage currents of the
TMUX113x devices versus input voltage.
40
30
20
VDD = 1.32 V
VDD = 1.98 V
VDD = 3.63 V
10
0
-10
-20
-30
-40
0
0.5
1
1.5
2
2.5
3
VS or VD - Source or Drain Voltage (V)
3.5
4
D006
图 27. Leakage Current vs Input Voltage
9.3.6 Ultra-low Charge Injection
The TMUX113x devices have a transmission gate topology, as shown in 图 28. Any mismatch in the stray
capacitance associated with the NMOS and PMOS causes an output level change whenever the switch is
opened or closed.
The TMUX113x devices have special charge-injection cancellation circuitry that reduces the source-to-drain
charge injection to -1 pC at VS = 1 V as shown in 图 29.
20
OFF ON
15
VDD = 3.3 V
VSS = 0 V
CGDN
10
5
CGSN
0
D
S
-5
VDD = +2.5 V
VSS = -2.5 V
-10
-15
-20
VDD = 5 V
VSS = 0 V
CGSP
CGDP
-3
-2
-1
0
1
2
Source Voltage (V)
3
4
5
OFF ON
D012
图 28. Transmission Gate Topology
图 29. Charge Injection vs Source Voltage
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9.4 Device Functional Modes
The select (SELx) pins are logic pins that control the connection between the source (SxA, SxB) and drain (Dx)
pins of the TMUX113x devices. When a source pin is not selected that pin is in an open state (HI-Z). When a
source pin is selected the switch conducts to drain. The logic control pins can be as high as 5.5 V.
When the EN pin of the TMUX1133 is pulled low the SELx logic control inputs determine which source input is
selected. When the EN pin is pulled high, all of the switches are in an open state regardless of the state of the
SELx logic control inputs. The TMUX1134 SELx logic control inputs determine which source pin is connected to
the drain pin for each channel.
The TMUX113x devices can be operated without any external components except for the supply decoupling
capacitors. Unused logic control pins must be tied to GND or VDD in order to ensure the device does not
consume additional current as highlighted in Implications of Slow or Floating CMOS Inputs. Unused signal path
inputs (SxA, SxB or Dx) should be connected to GND.
9.5 Truth Tables
表 1 and 表 2 show the truth tables for the TMUX1133 and TMUX1134 respectively.
表 1. TMUX1133 Truth table(1)
Selected Source Pins Connected To Drain
EN
SEL1
SEL2
SEL3
Pins
0
0
0
0
0
0
1
0
1
X
X
0
X
X
X
X
0
S1A to D1
S1B to D1
S2A to D2
S2B to D2
S3A to D3
S3B to D3
Hi-Z (OFF)
X
X
X
X
X
1
X
X
X
1
X
(1) X denotes don't care.
表 2. TMUX1134 Truth table(1)
Selected Source Pins Connected To Drain
Pins
SEL1
SEL2
SEL3
SEL4
0
1
X
X
0
X
X
X
X
0
X
X
X
X
X
X
0
S1B to D1
S1A to D1
S2B to D2
S2A to D2
S3B to D3
S3A to D3
S4B to D4
S4A to D4
X
X
X
X
X
X
1
X
X
X
X
1
X
X
1
(1) X denotes don't care.
26
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ZHCSK01A –JUNE 2019–REVISED AUGUST 2019
10 Application and Implementation
注
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
10.1 Application Information
The TMUX11xx family offers ultra-low input/output leakage currents and low charge injection. These devices
operate up to 5.5 V, and offer true rail-to-rail input and output switching of both analog and digital signals. The
TMUX113x devices have low on-capacitance which allows faster settling time when switching between inputs in
the time domain. These features make the TMUX11xx devices a family of precision, high-performance switches
and multiplexers for low-voltage applications.
10.2 Typical Application
图 30 shows an example circuit where the TMUX1133 or TMUX1134 can be used to minimize board space by
integrating various applications into a multi-channel 2:1 (SPDT) switch. The application uses a 3-channel, or 4-
channel SPDT switch in order to optimize the tradeoffs of system flexibility and board space.
VDD
VSS
0.1µF
0.1µF
System
0 V-5 V
Voltage Input
S1A
S1B
D1
SEL1
+
Calibration Path
To µC
Op Amp
-
Precision
ADC
Precision
DAC
RPD
10 kꢀ
0 V-5 V
Voltage Input
S2A
S2B
D2
+
4-20 mA
Current Input
To µC
Op Amp
-
SEL2
Precision
ADC
250 ꢀ
RPD
10 kꢀ
Voltage Input
Voltage Ouput
Precision
ADC
S4A
S4B
0 V-5 V
0 V-5 V
D4
Analog Input / Output
To µC
SEL4
Precision
DAC
RPD
10 kꢀ
图 30. Multi-channel 2:1, Switching Applications
10.3 Design Requirements
For this design example, use the parameters listed in 表 3.
表 3. Design Parameters
PARAMETERS
Supply (VDD
VALUES
)
5 V
Input / Output Voltage range
Input / Output Current range
Control logic thresholds
0 V to 5V
4 mA to 20 mA
1.8 V compatible
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10.4 Detailed Design Procedure
The TMUX113x devices can be operated without any external components except for the supply decoupling
capacitors, however pull-down or pull-up resistors are recommended on the logic control inputs to ensure each
channel is in a known state. All inputs passing through the switch must fall within the recommend operating
conditions, including signal range and continuous current. For this design with a single supply of 5 V the signal
range can be 0 V to 5 V, and the max continuous current can be 30 mA.
Industrial applications such as in Factory Automation & Control and Test & Measurement benefit from using a
multi-channel
2:1
switch
because
it
allows
additional
flexibility
in
the
design.
A single 2:1 switch has numerous applications such as:
1. Switching between an analog signal path and a calibration path in order to ensure the system is calibrated
across the life of a product or after installation.
2. Configuring a single channel to accept either a voltage or current input through software - allowing for system
flexibility across applications where the end users input signals may differ.
3. Allowing a single channel to be configured as either an analog input or analog output. Providing additional
control to a system while minimizing the number of physical connectors
图 30 shows how to configure a multi-channel analog switch to address these design implementations for
additional control and flexibility in the system. The on-resistance of the TMUX113x devices is very low, 2Ω
typical, and has a max on-leakage current of 2nA which allows the devices to be used in precision measurement
applications. A system with a 4mA to 20mA signal can achieve >20bits of precision due to the extremely low
leakage current of the TMUX113x devices.
10.5 Application Curve
The TMUX113x devices are capable of switching signals with minimal distortion because of the ultra-low leakage
currents and low on-resistance. 图 31 shows how the leakage current of the TMUX113x varies with different input
voltages.
100
80
60
VDD = 2.5V
SS = -2.5V
VDD = 5V
SS = 0V
40
20
V
V
0
-20
-40
-60
-80
-100
-3
-2
-1
0
1
2
3
VS or VD - Source or Drain Voltage (V)
4
5
D007
TA = 25°C
图 31. On-Leakage vs Source or Drain Voltage
28
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ZHCSK01A –JUNE 2019–REVISED AUGUST 2019
11 Power Supply Recommendations
The TMUX113x devices operate across a wide supply range of 1.08 V to 5.5 V single supply, or ±2.75 V for dual
supply applications. For single supply voltage applications VSS must be connected to GND. Do not exceed the
absolute maximum ratings because stresses beyond the listed ratings can cause permanent damage to the
devices.
Power-supply bypassing improves noise margin and prevents switching noise propagation from the VDD and VSS
supplies to other components. Good power-supply decoupling is important to achieve optimum performance. For
improved supply noise immunity, use a supply decoupling capacitor ranging from 0.1 μF to 10 μF from VDD and
VSS to ground. Place the bypass capacitors as close to the power supply pins of the device as possible using
low-impedance connections. TI recommends using multi-layer ceramic chip capacitors (MLCCs) that offer low
equivalent series resistance (ESR) and inductance (ESL) characteristics for power-supply decoupling purposes.
For very sensitive systems, or for systems in harsh noise environments, avoiding the use of vias for connecting
the capacitors to the device pins may offer superior noise immunity. The use of multiple vias in parallel lowers
the overall inductance and is beneficial for connections to ground planes.
12 Layout
12.1 Layout Guidelines
12.1.1 Layout Information
When a PCB trace turns a corner at a 90° angle, a reflection can occur. A reflection occurs primarily because of
the change of width of the trace. At the apex of the turn, the trace width increases to 1.414 times the width. This
increase upsets the transmission-line characteristics, especially the distributed capacitance and self–inductance
of the trace which results in the reflection. Not all PCB traces can be straight and therefore some traces must
turn corners.图 32 shows progressively better techniques of rounding corners. Only the last example (BEST)
maintains constant trace width and minimizes reflections.
WORST
BETTER
BEST
1W min.
W
图 32. Trace Example
Route high-speed signals using a minimum of vias and corners which reduces signal reflections and
impedance changes. When a via must be used, increase the clearance size around it to minimize its
capacitance. Each via introduces discontinuities in the signal’s transmission line and increases the chance of
picking up interference from the other layers of the board. Be careful when designing test points, through-
hole pins are not recommended at high frequencies.
图 33 and 图 34 illustrate examples of a PCB layout with the TMUX1133 and TMUX1134 respectively. Some key
considerations are:
•
Decouple the VDD and VSS pins with a 0.1-µF capacitor, placed as close to the pin as possible. Make sure
that the capacitor voltage rating is sufficient for the supply voltage.
•
•
•
Keep the input lines as short as possible.
Use a solid ground plane to help reduce electromagnetic interference (EMI) noise pickup.
Do not run sensitive analog traces in parallel with digital traces. Avoid crossing digital and analog traces if
possible, and only make perpendicular crossings when necessary.
版权 © 2019, Texas Instruments Incorporated
29
TMUX1133, TMUX1134
ZHCSK01A –JUNE 2019–REVISED AUGUST 2019
www.ti.com.cn
12.2 Layout Example
图 33 shows an example board layout for the TMUX1133.
Via to GND plane
C
Wide (low inductance)
trace for power
S2B
VDD
D2
S2A
S3B
D3
D1
S1B
S1A
SEL1
SEL2
SEL3
TMUX1133
S3A
EN
VSS
Wide (low inductance)
trace for power
GND
C
图 33. TMUX1133 Layout Example
图 34 shows an example board layout for the TMUX1134.
Via to GND plane
SEL1
SEL4
S4A
D4
S1A
D1
TMUX1134
S1B
VSS
S4B
VDD
N.C.
S3B
D3
C
C
GND
S2B
Wide (low inductance)
trace for power
Wide (low inductance)
trace for power
D2
S2A
SEL2
S3A
SEL3
图 34. TMUX1134 Layout Example
30
版权 © 2019, Texas Instruments Incorporated
TMUX1133, TMUX1134
www.ti.com.cn
ZHCSK01A –JUNE 2019–REVISED AUGUST 2019
13 器件和文档支持
13.1 文档支持
13.1.1 相关文档
德州仪器 (TI)，《采用 MSP430™ 的超声波燃气表前端参考设计》。
德州仪器 (TI)，《真差分 4 x 2 多路复用器、模拟前端、同步采样 ADC 电路》。
德州仪器 (TI)，《使用低 CON 多路复用器改善稳定性问题》。
德州仪器 (TI)，《使用 1.8V 逻辑多路复用器和开关简化设计》。
德州仪器 (TI)，《利用关断保护信号开关消除电源排序》。
德州仪器 (TI)，《高电压模拟多路复用器的系统级保护》。
德州仪器 (TI)，《QFN/SON PCB 连接》。
德州仪器 (TI)，《四方扁平封装无引线逻辑封装》。
13.2 相关链接
下表列出了快速访问链接。类别包括技术文档、支持和社区资源、工具和软件，以及立即订购快速访问。
表 4. 相关链接
器件
产品文件夹
单击此处
单击此处
立即订购
单击此处
单击此处
技术文档
单击此处
单击此处
工具与软件
单击此处
单击此处
支持和社区
单击此处
单击此处
TMUX1133
TMUX1134
13.3 接收文档更新通知
要接收文档更新通知，请导航至 TI.com.cn 上的器件产品文件夹。单击右上角的通知我 进行注册，即可每周接收产
品信息更改摘要。有关更改的详细信息，请查看任何已修订文档中包含的修订历史记录。
13.4 社区资源
TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help — straight
from the experts. Search existing answers or ask your own question to get the quick design help you need.
Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do
not necessarily reflect TI's views; see TI's Terms of Use.
13.5 商标
E2E is a trademark of Texas Instruments.
13.6 静电放电警告
ESD 可能会损坏该集成电路。德州仪器 (TI) 建议通过适当的预防措施处理所有集成电路。如果不遵守正确的处理措施和安装程序 , 可
能会损坏集成电路。
ESD 的损坏小至导致微小的性能降级 , 大至整个器件故障。 精密的集成电路可能更容易受到损坏 , 这是因为非常细微的参数更改都可
能会导致器件与其发布的规格不相符。
13.7 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
14 机械、封装和可订购信息
以下页面包含机械、封装和可订购信息。这些信息是指定器件的最新可用数据。数据如有变更，恕不另行通知，且
不会对此文档进行修订。如需获取此数据表的浏览器版本，请查阅左侧的导航栏。
版权 © 2019, Texas Instruments Incorporated
31
PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
TMUX1133PWR
TMUX1134PWR
ACTIVE
ACTIVE
TSSOP
TSSOP
PW
PW
16
20
2000 RoHS & Green
2000 RoHS & Green
NIPDAU
Level-1-260C-UNLIM
Level-1-260C-UNLIM
-40 to 125
-40 to 125
TM1133
TM1134
NIPDAU
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
3-Jun-2022
TAPE AND REEL INFORMATION
REEL DIMENSIONS
TAPE DIMENSIONS
K0
P1
W
B0
Reel
Diameter
Cavity
A0
A0 Dimension designed to accommodate the component width
B0 Dimension designed to accommodate the component length
K0 Dimension designed to accommodate the component thickness
Overall width of the carrier tape
W
P1 Pitch between successive cavity centers
Reel Width (W1)
QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE
Sprocket Holes
Q1 Q2
Q3 Q4
Q1 Q2
Q3 Q4
User Direction of Feed
Pocket Quadrants
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
TMUX1133PWR
TMUX1134PWR
TSSOP
TSSOP
PW
PW
16
20
2000
2000
330.0
330.0
12.4
16.4
6.9
5.6
7.0
1.6
1.4
8.0
8.0
12.0
16.0
Q1
Q1
6.95
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
3-Jun-2022
TAPE AND REEL BOX DIMENSIONS
Width (mm)
H
W
L
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SPQ
Length (mm) Width (mm) Height (mm)
TMUX1133PWR
TMUX1134PWR
TSSOP
TSSOP
PW
PW
16
20
2000
2000
356.0
356.0
356.0
356.0
35.0
35.0
Pack Materials-Page 2
PACKAGE OUTLINE
PW0020A
TSSOP - 1.2 mm max height
S
C
A
L
E
2
.
5
0
0
SMALL OUTLINE PACKAGE
SEATING
PLANE
C
6.6
6.2
TYP
A
0.1 C
PIN 1 INDEX AREA
18X 0.65
20
1
2X
5.85
6.6
6.4
NOTE 3
10
B
11
0.30
20X
4.5
4.3
NOTE 4
0.19
1.2 MAX
0.1
C A B
(0.15) TYP
SEE DETAIL A
0.25
GAGE PLANE
0.15
0.05
0.75
0.50
A
20
0 -8
DETAIL A
TYPICAL
4220206/A 02/2017
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed 0.15 mm per side.
4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.25 mm per side.
5. Reference JEDEC registration MO-153.
www.ti.com
EXAMPLE BOARD LAYOUT
PW0020A
TSSOP - 1.2 mm max height
SMALL OUTLINE PACKAGE
SYMM
20X (1.5)
(R0.05) TYP
20
1
20X (0.45)
SYMM
18X (0.65)
11
10
(5.8)
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE: 10X
METAL UNDER
SOLDER MASK
SOLDER MASK
OPENING
SOLDER MASK
OPENING
METAL
EXPOSED METAL
EXPOSED METAL
0.05 MAX
ALL AROUND
0.05 MIN
ALL AROUND
NON-SOLDER MASK
DEFINED
SOLDER MASK
DEFINED
15.000
(PREFERRED)
SOLDER MASK DETAILS
4220206/A 02/2017
NOTES: (continued)
6. Publication IPC-7351 may have alternate designs.
7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
www.ti.com
EXAMPLE STENCIL DESIGN
PW0020A
TSSOP - 1.2 mm max height
SMALL OUTLINE PACKAGE
20X (1.5)
SYMM
(R0.05) TYP
20
1
20X (0.45)
SYMM
18X (0.65)
10
11
(5.8)
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
SCALE: 10X
4220206/A 02/2017
NOTES: (continued)
8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
9. Board assembly site may have different recommendations for stencil design.
www.ti.com
PACKAGE OUTLINE
PW0016A
TSSOP - 1.2 mm max height
S
C
A
L
E
2
.
5
0
0
SMALL OUTLINE PACKAGE
SEATING
PLANE
C
6.6
6.2
TYP
A
0.1 C
PIN 1 INDEX AREA
14X 0.65
16
1
2X
5.1
4.9
4.55
NOTE 3
8
9
0.30
16X
4.5
4.3
NOTE 4
1.2 MAX
0.19
B
0.1
C A B
(0.15) TYP
SEE DETAIL A
0.25
GAGE PLANE
0.15
0.05
0.75
0.50
A
20
0 -8
DETAIL A
TYPICAL
4220204/A 02/2017
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed 0.15 mm per side.
4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.25 mm per side.
5. Reference JEDEC registration MO-153.
www.ti.com
EXAMPLE BOARD LAYOUT
PW0016A
TSSOP - 1.2 mm max height
SMALL OUTLINE PACKAGE
SYMM
16X (1.5)
(R0.05) TYP
16
1
16X (0.45)
SYMM
14X (0.65)
8
9
(5.8)
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE: 10X
METAL UNDER
SOLDER MASK
SOLDER MASK
OPENING
SOLDER MASK
OPENING
METAL
EXPOSED METAL
EXPOSED METAL
0.05 MAX
ALL AROUND
0.05 MIN
ALL AROUND
NON-SOLDER MASK
DEFINED
SOLDER MASK
DEFINED
15.000
(PREFERRED)
SOLDER MASK DETAILS
4220204/A 02/2017
NOTES: (continued)
6. Publication IPC-7351 may have alternate designs.
7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
www.ti.com
EXAMPLE STENCIL DESIGN
PW0016A
TSSOP - 1.2 mm max height
SMALL OUTLINE PACKAGE
16X (1.5)
SYMM
(R0.05) TYP
16
1
16X (0.45)
SYMM
14X (0.65)
8
9
(5.8)
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
SCALE: 10X
4220204/A 02/2017
NOTES: (continued)
8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
9. Board assembly site may have different recommendations for stencil design.
www.ti.com
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