TMUX1204 [TI]

5V、4:1、单通道通用模拟多路复用器;


型号：	TMUX1204
厂家：	TEXAS INSTRUMENTS
描述：	5V、4:1、单通道通用模拟多路复用器复用器
文件：	总35页 (文件大小：1624K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

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TMUX1204

ZHCSJM4A –APRIL 2019–REVISED OCTOBER 2019

TMUX1204 5V 4:1 通用型模拟多路复用器

1 特性

3 说明

•

轨至轨运行

TMUX1204 是一款现代互补金属氧化物半导体

(CMOS) 模拟多路复用器 (MUX)，可提供 4:1 单端（1

通道）配置。TMUX1204 由单电源供电（1.08V 至

5.5V），适用于从个人电子设备到楼宇自动化系统的

各种应用。低电源电流为 10nA，可用于便携式应用。

双向信号路径

1.8V 逻辑兼容

失效防护逻辑

低导通电阻：5Ω

宽电源电压范围：1.08V 至 5.5V

-40°C 至 +125°C 工作温度

低电源电流：10nA

转换时间：14ns

所有逻辑输入均具有兼容 1.8V 逻辑电平的阈值，当器

件在有效电源电压范围内运行时，这些阈值可确保

TTL 和 CMOS 逻辑兼容性。失效防护逻辑电路允许在

电源引脚之前的控制引脚上施加电压，从而保护器件免

受潜在的损害。

先断后合开关

ESD 保护 HBM：2000V

器件信息⁽¹⁾

2 应用

器件型号

TMUX1204

封装

VSSOP (10) (DGS) 3.00mm × 3.00mm

USON (10) (DQA) 2.50mm x 1.00mm

封装尺寸（标称值）

•

模拟和数字多路复用或多路信号分离

电机驱动器

伺服驱动器控制模块

楼宇自动化

条形码扫描仪

模拟输入模块

电力输送

(1) 如需了解所有可用封装，请参阅数据表末尾的封装选项附录。

SPACER

烟雾探测器

视频监控

热成像摄像机

电子销售终端

电器

消费类音频

应用示例

TMUX1204 方框图

V_DD

V_I/O

V_DD

TMUX1204

MCU

LDO #1

LDO #2

RAM

FLASH

Integrated

12-bit ADC

LM20

Analog Temp.

Sensor

Port I/O

TIMERS

1-of-4

LM20

Analog Temp.

Sensor

Decoder

GND

1.8V Logic

I/O

System Inputs

and Sensors

EN A1 A0

本文档旨在为方便起见，提供有关 TI 产品中文版本的信息，以确认产品的概要。有关适用的官方英文版本的最新信息，请访问 www.ti.com，其内容始终优先。 TI 不保证翻译的准确

性和有效性。在实际设计之前，请务必参考最新版本的英文版本。

English Data Sheet: SCDS393

TMUX1204

ZHCSJM4A –APRIL 2019–REVISED OCTOBER 2019

www.ti.com.cn

7.10 Bandwidth ............................................................. 18

Detailed Description ............................................ 19

8.1 Functional Block Diagram ....................................... 19

8.2 Feature Description................................................. 19

8.3 Device Functional Modes........................................ 20

8.4 Truth Tables............................................................ 20

Application and Implementation ........................ 21

9.1 Application Information............................................ 21

9.2 Typical Application ................................................. 21

9.3 Design Requirements.............................................. 21

9.4 Detailed Design Procedure ..................................... 22

9.5 Application Curve.................................................... 22

特性.......................................................................... 1

应用.......................................................................... 1

说明.......................................................................... 1

修订历史记录 ........................................................... 2

Pin Configuration and Functions......................... 3

Specifications......................................................... 4

6.1 Absolute Maximum Ratings ...................................... 4

6.2 ESD Ratings.............................................................. 4

6.3 Recommended Operating Conditions....................... 4

6.4 Thermal Information.................................................. 4

6.5 Electrical Characteristics (V_DD= 5 V ±10 %)............ 5

6.6 Electrical Characteristics (V_DD= 3.3 V ±10 %)......... 7

6.7 Electrical Characteristics (V_DD= 1.8 V ±10 %)......... 9

6.8 Electrical Characteristics (V_DD= 1.2 V ±10 %)....... 11

6.9 Typical Characteristics............................................ 13

Parameter Measurement Information ................ 14

7.1 On-Resistance ........................................................ 14

7.2 Off-Leakage Current ............................................... 14

7.3 On-Leakage Current ............................................... 15

7.4 Transition Time ....................................................... 15

7.5 Break-Before-Make................................................. 16

7.6 t_ON(EN)and t_OFF(EN).................................................. 16

7.7 Charge Injection...................................................... 17

7.8 Off Isolation............................................................. 17

7.9 Crosstalk ................................................................. 18

10 Power Supply Recommendations ..................... 22

11 Layout................................................................... 23

11.1 Layout Guidelines ................................................. 23

11.2 Layout Example .................................................... 23

12 器件和文档支持 ..................................................... 24

12.1 文档支持................................................................ 24

12.2 接收文档更新通知 ................................................. 24

12.3 社区资源................................................................ 24

12.4 商标....................................................................... 24

12.5 静电放电警告......................................................... 24

12.6 Glossary................................................................ 24

13 机械、封装和可订购信息....................................... 24

4 修订历史记录

注：之前版本的页码可能与当前版本有所不同。

Changes from Original (April 2019) to Revision A

Page

•

删除了器件信息表中 DQA 封装的产品预览 ........................................................................................................................... 1

Deleted Product preview from the DQA package in the Pin Configuration and Functions section........................................ 3

Added Note 2 to the Pin Functions table ............................................................................................................................... 3

TMUX1204

www.ti.com.cn

ZHCSJM4A –APRIL 2019–REVISED OCTOBER 2019

5 Pin Configuration and Functions

DGS Package

10-Pin VSSOP

Top View

DQA Package

10-Pin USON

Top View

GND

VDD

Not to scale

Pin Functions

TYPE⁽¹⁾

DESCRIPTION⁽²⁾

NAME

DGS, DQA

Address line 0. Controls the switch configuration as shown in 表 1.

Source pin 1. Can be an input or output.

Ground (0 V) reference

I/O

GND

I/O

Source pin 3. Can be an input or output.

Active high logic enable. When this pin is low, all switches are turned off. When this pin is high, the

A[1:0] logic inputs determine which switch is turned on.

Positive power supply. This pin is the most positive power-supply potential. For reliable operation,

connect a decoupling capacitor ranging from 0.1 µF to 10 µF between V_DDand GND.

VDD

I/O

Source pin 4. Can be an input or output.

Drain pin. Can be an input or output.

Source pin 2. Can be an input or output.

Address line 1. Controls the switch configuration as shown in 表 1.

(1) I = input, O = output, I/O = input and output, P = power

(2) For unused pins, refer to the Device Functional Modes

TMUX1204

ZHCSJM4A –APRIL 2019–REVISED OCTOBER 2019

www.ti.com.cn

6 Specifications

6.1 Absolute Maximum Ratings

over operating free-air temperature range (unless otherwise noted)

(1) (2) (3)

MIN

–0.5

–30

–0.5

–30

–65

MAX

UNIT

V_DD

Supply voltage

V_SELor V_EN

I_SELor I_EN

V_Sor V_D

I_Sor I_{D (CONT)}

T_stg

Logic control input pin voltage (EN, A0, A1)

Logic control input pin current (EN, A0, A1)

Source or drain voltage (Sx, D)

Source or drain continuous current (Sx, D)

Storage temperature

V_DD+0.5

°C

150

T_J

Junction temperature

150

(1) Stresses beyond those listed under Absolute Maximum Rating may cause permanent damage to the device. These are stress ratings

only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended

Operating Condition. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

(2) The algebraic convention, whereby the most negative value is a minimum and the most positive value is a maximum.

(3) All voltages are with respect to ground, unless otherwise specified.

6.2 ESD Ratings

VALUE

UNIT

Human body model (HBM), per ANSI/ESDA/JEDEC JS-001, all pins⁽¹⁾

±2000

V_(ESD)

Electrostatic discharge

Charged device model (CDM), per JEDEC specification JESD22-C101

or ANSI/ESDA/JEDEC JS-002, all pins⁽²⁾

±750

(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.

(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

6.3 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted)

MIN

1.08

NOM

MAX

5.5

UNIT

V_DD

Positive power supply voltage

V_Sor V_D

Signal path input/output voltage (source or drain pin) (Sx, D)

V_DD

V_SELor

V_EN

Logic control input pin voltage (EN, A0, A1)

Ambient temperature

5.5

T_A

–40

125

°C

6.4 Thermal Information

TMUX1204

THERMAL METRIC⁽¹⁾

DGS (VSSOP)

10 PINS

193.9

DQA (USON)

10 PINS

173.0

99.7

UNIT

R_θJA

Junction-to-ambient thermal resistance

Junction-to-case (top) thermal resistance

Junction-to-board thermal resistance

°C/W

R_θJC(top)

R_θJB

83.1

116.5

73.5

Ψ_JT

Junction-to-top characterization parameter

Junction-to-board characterization parameter

Junction-to-case (bottom) thermal resistance

22.0

8.9

Ψ_JB

114.6

73.0

R_θJC(bot)

N/A

(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application

report.

TMUX1204

www.ti.com.cn

ZHCSJM4A –APRIL 2019–REVISED OCTOBER 2019

6.5 Electrical Characteristics (V_DD= 5 V ±10 %)

at T_A= 25°C, V_DD= 5 V (unless otherwise noted)

PARAMETER

ANALOG SWITCH

TEST CONDITIONS

MIN

TYP

MAX UNIT

25°C

V_S= 0 V to V_DD

R_ON

On-resistance

I_SD= 10 mA

Refer to On-Resistance

–40°C to +85°C

–40°C to +125°C

25°C

0.15

V_S= 0 V to V_DD

I_SD= 10 mA

Refer to On-Resistance

On-resistance matching between

channels

ΔR_ON

–40°C to +85°C

–40°C to +125°C

25°C

1.5

V_S= 0 V to V_DD

I_SD= 10 mA

Refer to On-Resistance

R_ON

FLAT

On-resistance flatness

–40°C to +85°C

–40°C to +125°C

25°C

V_DD= 5 V

Switch Off

V_D= 4.5 V / 1.5 V

V_S= 1.5 V / 4.5 V

Refer to Off-Leakage Current

±75

–40°C to +85°C

–150

–175

150

175

I_S(OFF)

Source off leakage current⁽¹⁾

–40°C to +125°C

V_DD= 5 V

Switch Off

V_D= 4.5 V / 1.5 V

V_S= 1.5 V / 4.5 V

Refer to Off-Leakage Current

25°C

±200

–40°C to +85°C

–500

–750

500

750

I_D(OFF)Drain off leakage current⁽¹⁾

–40°C to +125°C

V_DD= 5 V

Switch On

V_D= V_S= 4.5 V / 1.5 V

Refer to On-Leakage Current

25°C

I_D(ON)

–40°C to +85°C

–500

–750

500

750

Channel on leakage current

I_S(ON)

–40°C to +125°C

LOGIC INPUTS (EN, A0, A1)

V_IH

V_IL

Input logic high

Input logic low

–40°C to +125°C

1.49

5.5

0.87

I_IH

I_IL

Input leakage current

25°C

±0.005

µA

I_IH

I_IL

–40°C to +125°C

±0.10

C_IN

Logic input capacitance

25°C

–40°C to +125°C

POWER SUPPLY

25°C

0.01

µA

I_DDV_DDsupply current

Logic inputs = 0 V or 5.5 V

–40°C to +125°C

(1) When V_Sis 4.5 V, V_Dis 1.5 V or when V_Sis 1.5 V, V_Dis 4.5 V.

TMUX1204

ZHCSJM4A –APRIL 2019–REVISED OCTOBER 2019

www.ti.com.cn

Electrical Characteristics (V_DD= 5 V ±10 %) (continued)

at T_A= 25°C, V_DD= 5 V (unless otherwise noted)

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX UNIT

DYNAMIC CHARACTERISTICS

25°C

V_S= 3 V

t_TRAN

Transition time between channels R_L= 200 Ω, C_L= 15 pF

–40°C to +85°C

–40°C to +125°C

25°C

Refer to Transition Time

V_S= 3 V

t_OPEN

(BBM)

Break before make time

R_L= 200 Ω, C_L= 15 pF

–40°C to +85°C

–40°C to +125°C

25°C

Refer to Break-Before-Make

V_S= 3 V

R_L= 200 Ω, C_L= 15 pF

Refer to t_ON(EN)and t_OFF(EN)

t_ON(EN)Enable turn-on time

t_OFF(EN)Enable turn-off time

–40°C to +85°C

–40°C to +125°C

25°C

V_S= 3 V

R_L= 200 Ω, C_L= 15 pF

Refer to t_ON(EN)and t_OFF(EN)

–40°C to +85°C

–40°C to +125°C

V_S= 1 V

Q_C

Charge Injection

Off Isolation

R_S= 0 Ω, C_L= 1 nF

Refer to Charge Injection

25°C

±9

–62

–42

–62

R_L= 50 Ω, C_L= 5 pF

f = 1 MHz

Refer to Off Isolation

O_ISO

R_L= 50 Ω, C_L= 5 pF

f = 10 MHz

Refer to Off Isolation

R_L= 50 Ω, C_L= 5 pF

f = 1 MHz

Refer to Crosstalk

X_TALK

Crosstalk

R_L= 50 Ω, C_L= 5 pF

f = 10 MHz

25°C

–42

125

Refer to Crosstalk

R_L= 50 Ω, C_L= 5 pF

Refer to Bandwidth

Bandwidth

MHz

C_SOFF

C_DOFF

Source off capacitance

Drain off capacitance

f = 1 MHz

25°C

C_SON

C_DON

On capacitance

f = 1 MHz

25°C

TMUX1204

www.ti.com.cn

ZHCSJM4A –APRIL 2019–REVISED OCTOBER 2019

6.6 Electrical Characteristics (V_DD= 3.3 V ±10 %)

at T_A= 25°C, V_DD= 3.3 V (unless otherwise noted)

PARAMETER

ANALOG SWITCH

TEST CONDITIONS

MIN

TYP

MAX UNIT

25°C

V_S= 0 V to V_DD

R_ON

On-resistance

I_SD= 10 mA

Refer to On-Resistance

–40°C to +85°C

–40°C to +125°C

25°C

0.15

V_S= 0 V to V_DD

I_SD= 10 mA

Refer to On-Resistance

On-resistance matching between

channels

ΔR_ON

–40°C to +85°C

–40°C to +125°C

25°C

V_S= 0 V to V_DD

I_SD= 10 mA

Refer to On-Resistance

R_ON

FLAT

On-resistance flatness

–40°C to +85°C

–40°C to +125°C

25°C

V_DD= 3.3 V

Switch Off

V_D= 3 V / 1 V

V_S= 1 V / 3 V

±75

–40°C to +85°C

–150

–175

150

175

I_S(OFF)

Source off leakage current⁽¹⁾

–40°C to +125°C

Refer to Off-Leakage Current

V_DD= 3.3 V

Switch Off

V_D= 3 V / 1 V

V_S= 1 V / 3 V

25°C

±200

–40°C to +85°C

–500

–750

500

750

I_D(OFF)Drain off leakage current⁽¹⁾

–40°C to +125°C

Refer to Off-Leakage Current

V_DD= 3.3 V

Switch On

V_D= V_S= 3 V / 1 V

Refer to On-Leakage Current

25°C

I_D(ON)

–40°C to +85°C

–500

–750

500

750

Channel on leakage current

I_S(ON)

–40°C to +125°C

LOGIC INPUTS (EN, A0, A1)

V_IH

V_IL

Input logic high

Input logic low

–40°C to +125°C

1.35

5.5

0.8

I_IH

I_IL

Input leakage current

25°C

±0.005

µA

I_IH

I_IL

–40°C to +125°C

±0.10

C_IN

Logic input capacitance

25°C

–40°C to +125°C

POWER SUPPLY

25°C

0.01

µA

I_DDV_DDsupply current

Logic inputs = 0 V or 5.5 V

–40°C to +125°C

1.3

(1) When V_Sis 3 V, V_Dis 1 V or when V_Sis 1 V, V_Dis 3 V.

TMUX1204

ZHCSJM4A –APRIL 2019–REVISED OCTOBER 2019

www.ti.com.cn

Electrical Characteristics (V_DD= 3.3 V ±10 %) (continued)

at T_A= 25°C, V_DD= 3.3 V (unless otherwise noted)

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX UNIT

DYNAMIC CHARACTERISTICS

25°C

V_S= 2 V

t_TRAN

Transition time between channels R_L= 200 Ω, C_L= 15 pF

–40°C to +85°C

–40°C to +125°C

25°C

Refer to Transition Time

V_S= 2 V

t_OPEN

(BBM)

Break before make time

R_L= 200 Ω, C_L= 15 pF

–40°C to +85°C

–40°C to +125°C

25°C

Refer to Break-Before-Make

V_S= 2 V

R_L= 200 Ω, C_L= 15 pF

Refer to t_ON(EN)and t_OFF(EN)

t_ON(EN)Enable turn-on time

t_OFF(EN)Enable turn-off time

–40°C to +85°C

–40°C to +125°C

25°C

V_S= 2 V

R_L= 200 Ω, C_L= 15 pF

Refer to t_ON(EN)and t_OFF(EN)

–40°C to +85°C

–40°C to +125°C

V_S= 1 V

Q_C

Charge Injection

Off Isolation

R_S= 0 Ω, C_L= 1 nF

Refer to Charge Injection

25°C

±7

–62

–42

–62

R_L= 50 Ω, C_L= 5 pF

f = 1 MHz

Refer to Off Isolation

O_ISO

R_L= 50 Ω, C_L= 5 pF

f = 10 MHz

Refer to Off Isolation

R_L= 50 Ω, C_L= 5 pF

f = 1 MHz

Refer to Crosstalk

X_TALK

Crosstalk

R_L= 50 Ω, C_L= 5 pF

f = 10 MHz

25°C

–42

125

Refer to Crosstalk

R_L= 50 Ω, C_L= 5 pF

Refer to Bandwidth

Bandwidth

MHz

C_SOFF

C_DOFF

Source off capacitance

Drain off capacitance

f = 1 MHz

25°C

C_SON

C_DON

On capacitance

f = 1 MHz

25°C

TMUX1204

www.ti.com.cn

ZHCSJM4A –APRIL 2019–REVISED OCTOBER 2019

6.7 Electrical Characteristics (V_DD= 1.8 V ±10 %)

at T_A= 25°C, V_DD= 1.8 V (unless otherwise noted)

PARAMETER

ANALOG SWITCH

TEST CONDITIONS

MIN

TYP

MAX UNIT

25°C

V_S= 0 V to V_DD

R_ON

On-resistance

I_SD= 10 mA

Refer to On-Resistance

–40°C to +85°C

–40°C to +125°C

25°C

0.15

±75

V_S= 0 V to V_DD

I_SD= 10 mA

Refer to On-Resistance

On-resistance matching between

channels

ΔR_ON

–40°C to +85°C

–40°C to +125°C

25°C

1.5

V_DD= 1.98 V

Switch Off

V_D= 1.8 V / 1 V

V_S= 1 V / 1.8 V

Refer to Off-Leakage Current

–40°C to +85°C

-150

-175

150

175

I_S(OFF)

Source off leakage current⁽¹⁾

–40°C to +125°C

V_DD= 1.98 V

Switch Off

V_D= 1.8 V / 1 V

V_S= 1 V / 1.8 V

Refer to Off-Leakage Current

25°C

±200

–40°C to +85°C

–500

–750

500

750

I_D(OFF)Drain off leakage current⁽¹⁾

–40°C to +125°C

V_DD= 1.98 V

Switch On

V_D= V_S= 1.8 V / 1 V

Refer to On-Leakage Current

25°C

I_D(ON)

–40°C to +85°C

–500

–750

500

750

Channel on leakage current

I_S(ON)

–40°C to +125°C

LOGIC INPUTS (EN, A0, A1)

V_IH

V_IL

Input logic high

Input logic low

–40°C to +125°C

1.07

5.5

0.68

I_IH

I_IL

Input leakage current

25°C

±0.005

µA

I_IH

I_IL

–40°C to +125°C

±0.10

C_IN

Logic input capacitance

25°C

–40°C to +125°C

POWER SUPPLY

25°C

0.005

µA

I_DDV_DDsupply current

Logic inputs = 0 V or 5.5 V

–40°C to +125°C

0.95

(1) When V_Sis 1.8 V, V_Dis 1 V or when V_Sis 1 V, V_Dis 1.8 V.

TMUX1204

ZHCSJM4A –APRIL 2019–REVISED OCTOBER 2019

www.ti.com.cn

Electrical Characteristics (V_DD= 1.8 V ±10 %) (continued)

at T_A= 25°C, V_DD= 1.8 V (unless otherwise noted)

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX UNIT

DYNAMIC CHARACTERISTICS

25°C

V_S= 1 V

t_TRAN

Transition time between channels R_L= 200 Ω, C_L= 15 pF

–40°C to +85°C

–40°C to +125°C

25°C

Refer to Transition Time

V_S= 1 V

t_OPEN

(BBM)

Break before make time

R_L= 200 Ω, C_L= 15 pF

–40°C to +85°C

–40°C to +125°C

25°C

Refer to Break-Before-Make

V_S= 1 V

R_L= 200 Ω, C_L= 15 pF

Refer to t_ON(EN)and t_OFF(EN)

t_ON(EN)Enable turn-on time

t_OFF(EN)Enable turn-off time

–40°C to +85°C

–40°C to +125°C

25°C

V_S= 1 V

R_L= 200 Ω, C_L= 15 pF

Refer to t_ON(EN)and t_OFF(EN)

–40°C to +85°C

–40°C to +125°C

V_S= 1 V

Q_C

Charge Injection

Off Isolation

R_S= 0 Ω, C_L= 1 nF

Refer to Charge Injection

25°C

–2

–62

–42

–62

R_L= 50 Ω, C_L= 5 pF

f = 1 MHz

Refer to Off Isolation

O_ISO

R_L= 50 Ω, C_L= 5 pF

f = 10 MHz

Refer to Off Isolation

R_L= 50 Ω, C_L= 5 pF

f = 1 MHz

Refer to Crosstalk

X_TALK

Crosstalk

R_L= 50 Ω, C_L= 5 pF

f = 10 MHz

25°C

–42

125

Refer to Crosstalk

R_L= 50 Ω, C_L= 5 pF

Refer to Bandwidth

Bandwidth

MHz

C_SOFF

C_DOFF

Source off capacitance

Drain off capacitance

f = 1 MHz

25°C

C_SON

C_DON

On capacitance

f = 1 MHz

25°C

TMUX1204

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6.8 Electrical Characteristics (V_DD= 1.2 V ±10 %)

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX UNIT

ANALOG SWITCH

25°C

V_S= 0 V to V_DD

R_ON

On-resistance

I_SD= 10 mA

Refer to On-Resistance

–40°C to +85°C

–40°C to +125°C

25°C

105

0.15

±75

V_S= 0 V to V_DD

I_SD= 10 mA

Refer to On-Resistance

On-resistance matching between

channels

ΔR_ON

–40°C to +85°C

–40°C to +125°C

25°C

1.5

V_DD= 1.32 V

Switch Off

V_D= 1.2 V / 1 V

V_S= 1 V / 1.2 V

Refer to Off-Leakage Current

–40°C to +85°C

–150

–175

150

175

I_S(OFF)

Source off leakage current⁽¹⁾

–40°C to +125°C

V_DD= 1.32 V

Switch Off

V_D= 1.2 V / 1 V

V_S= 1 V / 1.2 V

Refer to Off-Leakage Current

25°C

±200

–40°C to +85°C

–500

–750

500

750

I_D(OFF)Drain off leakage current⁽¹⁾

–40°C to +125°C

V_DD= 1.32 V

Switch On

V_D= V_S= 1.2 V / 1 V

Refer to On-Leakage Current

25°C

I_D(ON)

–40°C to +85°C

–500

–750

500

750

Channel on leakage current

I_S(ON)

–40°C to +125°C

LOGIC INPUTS (EN, A0, A1)

V_IH

V_IL

Input logic high

Input logic low

–40°C to +125°C

0.96

5.5

0.36

I_IH

I_IL

Input leakage current

25°C

±0.005

µA

I_IH

I_IL

–40°C to +125°C

±0.10

C_IN

Logic input capacitance

25°C

–40°C to +125°C

POWER SUPPLY

25°C

0.005

µA

I_DDV_DDsupply current

Logic inputs = 0 V or 5.5 V

–40°C to +125°C

0.8

(1) When V_Sis 1 V, V_Dis 1.2 V or when V_Sis 1.2 V, V_Dis 1 V.

TMUX1204

ZHCSJM4A –APRIL 2019–REVISED OCTOBER 2019

www.ti.com.cn

Electrical Characteristics (V_DD= 1.2 V ±10 %) (continued)

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX UNIT

DYNAMIC CHARACTERISTICS

25°C

V_S= 1 V

t_TRAN

Transition time between channels R_L= 200 Ω, C_L= 15 pF

–40°C to +85°C

–40°C to +125°C

25°C

210

Refer to Transition Time

V_S= 1 V

t_OPEN

(BBM)

Break before make time

R_L= 200 Ω, C_L= 15 pF

–40°C to +85°C

–40°C to +125°C

25°C

Refer to Break-Before-Make

V_S= 1 V

R_L= 200 Ω, C_L= 15 pF

Refer to t_ON(EN)and t_OFF(EN)

t_ON(EN)Enable turn-on time

t_OFF(EN)Enable turn-off time

–40°C to +85°C

–40°C to +125°C

25°C

190

V_S= 1 V

R_L= 200 Ω, C_L= 15 pF

Refer to t_ON(EN)and t_OFF(EN)

–40°C to +85°C

–40°C to +125°C

150

V_S= 1 V

Q_C

Charge Injection

Off Isolation

R_S= 0 Ω, C_L= 1 nF

Refer to Charge Injection

25°C

±2

–62

–42

–62

R_L= 50 Ω, C_L= 5 pF

f = 1 MHz

Refer to Off Isolation

O_ISO

R_L= 50 Ω, C_L= 5 pF

f = 10 MHz

Refer to Off Isolation

R_L= 50 Ω, C_L= 5 pF

f = 1 MHz

Refer to Crosstalk

X_TALK

Crosstalk

R_L= 50 Ω, C_L= 5 pF

f = 10 MHz

25°C

–42

125

Refer to Crosstalk

R_L= 50 Ω, C_L= 5 pF

Refer to Bandwidth

Bandwidth

MHz

C_SOFF

C_DOFF

Source off capacitance

Drain off capacitance

f = 1 MHz

25°C

C_SON

C_DON

On capacitance

f = 1 MHz

25°C

TMUX1204

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ZHCSJM4A –APRIL 2019–REVISED OCTOBER 2019

6.9 Typical Characteristics

at T_A= 25°C, V_DD= 5 V (unless otherwise noted)

V_DD= 1.08V

T_A= +85èC

T_A= +125èC

V_DD= 1.62V

V_DD= 3V

V_DD= 4.5V

T_A= +25èC

T_A= -40èC

1.5

Source or Drain Voltage (V)

0.5

1.5

2.5

3.5

Source or Drain Voltage (V)

4.5

0.5

2.5

3.5

D001

D002

T_A= 25°C

V_DD= 3 V

图 1. On-Resistance vs Source or Drain Voltage

图 2. On-Resistance vs Source or Drain Voltage

T_ON

T_OFF

1.5

2.5

V_DD- Supply Voltage (V)

3.5

4.5

5.5

-60

-30

120

150

T_A- Temperature (èC)

D003

D004

T_A= 25°C

V_DD= 3.3 V

图 3. T_{ON (EN)}and T_{OFF (EN)}vs Supply Voltage

图 4. T_{ON (EN)}and T_{OFF (EN)}vs Temperature

1400

1200

1000

800

600

400

200

-1

-2

-3

-4

-5

-6

V_DD= 3.3 V

V_DD= 5 V

0.5

1.5

2.5

Logic Voltage (V)

3.5

4.5

10M

Frequency (Hz)

100M

D005

D006

T_A= 25°C

图 5. Supply Current vs Logic Voltage

图 6. Frequency Response

TMUX1204

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www.ti.com.cn

7 Parameter Measurement Information

7.1 On-Resistance

The on-resistance of a device is the ohmic resistance between the source (Sx) and drain (D) pins of the device.

The on-resistance varies with input voltage and supply voltage. The symbol R_ONis used to denote on-resistance.

The measurement setup used to measure R_ONis shown in 图 7. Voltage (V) and current (I_SD) are measured

using this setup, and R_ONis computed with R_ON= V / I_SD

I_SD

V_S

图 7. On-Resistance Measurement Setup

7.2 Off-Leakage Current

There are two types of leakage currents associated with a switch during the off state:

1. Source off-leakage current

2. Drain off-leakage current

Source leakage current is defined as the leakage current flowing into or out of the source pin when the switch is

off. This current is denoted by the symbol I_S(OFF)

Drain leakage current is defined as the leakage current flowing into or out of the drain pin when the switch is off.

This current is denoted by the symbol I_D(OFF)

The setup used to measure both off-leakage currents is shown in 图 8.

V_DD

I_{s (OFF)}

I_{D (OFF)}

V_S

V_D

GND

图 8. Off-Leakage Measurement Setup

TMUX1204

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ZHCSJM4A –APRIL 2019–REVISED OCTOBER 2019

7.3 On-Leakage Current

Source on-leakage current is defined as the leakage current flowing into or out of the source pin when the switch

is on. This current is denoted by the symbol I_S(ON)

Drain on-leakage current is defined as the leakage current flowing into or out of the drain pin when the switch is

on. This current is denoted by the symbol I_D(ON)

Either the source pin or drain pin is left floating during the measurement. 图 9 shows the circuit used for

measuring the on-leakage current, denoted by I_S(ON)or I_D(ON)

V_DD

I_{S (ON)}

N.C.

I_{D (ON)}

N.C.

V_S

V_D

GND

图 9. On-Leakage Measurement Setup

7.4 Transition Time

Transition time is defined as the time taken by the output of the device to rise or fall 10% after the address signal

has risen or fallen past the logic threshold. The 10% transition measurement is utilized to provide the timing of

the device. System level timing can then account for the time constant added from the load resistance and load

capacitance. 图 10 shows the setup used to measure transition time, denoted by the symbol t_TRANSITION

V_DD

0.1…F

V_DD

ADDRESS

DRIVE

(V_SEL

t_f< 5ns

t_r< 5ns

V_S

V_IH

)

V_IL

OUTPUT

0 V

R_L

C_L

t_TRANSITION

90%

OUTPUT

V_SEL

10%

GND

0 V

图 10. Transition-Time Measurement Setup

TMUX1204

ZHCSJM4A –APRIL 2019–REVISED OCTOBER 2019

www.ti.com.cn

7.5 Break-Before-Make

Break-before-make delay is a safety feature that prevents two inputs from connecting when the device is

switching. The output first breaks from the on-state switch before making the connection with the next on-state

switch. The time delay between the break and the make is known as break-before-make delay. 图 11 shows the

setup used to measure break-before-make delay, denoted by the symbol t_OPEN(BBM)

V_DD

0.1…F

V_DD

V_S

ADDRESS

DRIVE

t_r< 5ns

t_f< 5ns

OUTPUT

(V_SEL

)

0 V

R_L

C_L

90%

Output

t_BBM

t_BBM2

0 V

V_SEL

t_{OPEN (BBM)}= min ( t_BBM1, t_BBM2)

GND

图 11. Break-Before-Make Delay Measurement Setup

7.6 t_ON(EN)and t_OFF(EN)

Turn-on time is defined as the time taken by the output of the device to rise to 10% after the enable has risen

past the logic threshold. The 10% measurement is utilized to provide the timing of the device. System level

timing can then account for the time constant added from the load resistance and load capacitance. 图 12 shows

the setup used to measure turn-on time, denoted by the symbol t_ON(EN)

Turn-off time is defined as the time taken by the output of the device to fall to 90% after the enable has fallen

past the logic threshold. The 90% measurement is utilized to provide the timing of the device. System level

timing can then account for the time constant added from the load resistance and load capacitance. 图 12 shows

the setup used to measure turn-off time, denoted by the symbol t_OFF(EN)

V_DD

0.1…F

V_DD

t_f< 5ns

t_r< 5ns

ENABLE

DRIVE

V_S

V_IH

(V_EN

)

V_IL

OUTPUT

0 V

R_L

C_L

t_{OFF (EN)}

t_ON

(EN)

90%

OUTPUT

0 V

V_EN

10%

GND

图 12. Turn-On and Turn-Off Time Measurement Setup

TMUX1204

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ZHCSJM4A –APRIL 2019–REVISED OCTOBER 2019

7.7 Charge Injection

The TMUX1204 has a transmission-gate topology. Any mismatch in capacitance between the NMOS and PMOS

transistors results in a charge injected into the drain or source during the falling or rising edge of the gate signal.

The amount of charge injected into the source or drain of the device is known as charge injection, and is denoted

by the symbol Q_C. 图 13 shows the setup used to measure charge injection from source (Sx) to drain (D).

V_DD

0.1…F

V_DD

V_S

V_EN

OUTPUT

0 V

V_OUT

C_L

Output

V_OUT

V_S

Q_C= C_L

V_OUT

V_EN

GND

图 13. Charge-Injection Measurement Setup

7.8 Off Isolation

Off isolation is defined as the ratio of the signal at the drain pin (D) of the device when a signal is applied to the

source pin (Sx) of an off-channel. 图 14 shows the setup used to measure, and the equation used to calculate off

isolation.

0.1µF

NETWORK

V_DD

ANALYZER

V_S

50Q

V_SIG

V_OUT

R_L

S_X

50Q

GND

R_L

50Q

图 14. Off Isolation Measurement Setup

≈

∆

’

◊

V_OUT

V_S

Off Isolation = 20 ∂ Log

(1)

TMUX1204

ZHCSJM4A –APRIL 2019–REVISED OCTOBER 2019

www.ti.com.cn

7.9 Crosstalk

Crosstalk is defined as the ratio of the signal at the drain pin (D) of a different channel, when a signal is applied

at the source pin (Sx) of an on-channel. 图 15 shows the setup used to measure, and the equation used to

calculate crosstalk.

0.1µF

NETWORK

V_DD

ANALYZER

V_OUT

R_L

50Q

V_S

R_L

50Q

V_SIG

S_X

R_L

GND

50Q

图 15. Crosstalk Measurement Setup

≈

∆

’

◊

V_OUT

V_S

Channel-to-Channel Crosstalk = 20 ∂ Log

(2)

7.10 Bandwidth

Bandwidth is defined as the range of frequencies that are attenuated by less than 3 dB when the input is applied

to the source pin (Sx) of an on-channel, and the output is measured at the drain pin (D) of the device. 图 16

shows the setup used to measure bandwidth.

0.1µF

NETWORK

V_DD

ANALYZER

V_S

50Q

V_SIG

V_OUT

R_L

50Q

S_X

GND

R_L

50Q

图 16. Bandwidth Measurement Setup

TMUX1204

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ZHCSJM4A –APRIL 2019–REVISED OCTOBER 2019

8 Detailed Description

8.1 Functional Block Diagram

The TMUX1204 is a 4:1, single-ended (1-ch.), mux. Each channel is turned on or turned off based on the state of

the address lines and the enable pin.

TMUX1204

1-of-4

Decoder

EN A1 A0

图 17. TMUX1204 Functional Block Diagrams

8.2 Feature Description

8.2.1 Bidirectional Operation

The TMUX1204 conducts equally well from source (Sx) to drain (D) or from drain (D) to source (Sx). Each

channel has very similar characteristics in both directions and supports both analog and digital signals.

8.2.2 Rail to Rail Operation

The valid signal path input/output voltage for TMUX1204 ranges from GND to V_DD

8.2.3 1.8 V Logic Compatible Inputs

The TMUX1204 has 1.8-V logic compatible control for all logic control inputs. The logic input thresholds scale

with supply but still provide 1.8-V logic control when operating at 5.5 V supply voltage. 1.8-V logic level inputs

allows the TMUX1204 to interface with processors that have lower logic I/O rails and eliminates the need for an

external translator, which saves both space and BOM cost. For more information on 1.8 V logic implementations

refer to Simplifying Design with 1.8 V logic Muxes and Switches

8.2.4 Fail-Safe Logic

The TMUX1204 supports Fail-Safe Logic on the control input pins (EN, A0, A1) allowing for operation up to 5.5

V, regardless of the state of the supply pin. This feature allows voltages on the control pins to be applied before

the supply pin, protecting the device from potential damage. Fail-Safe Logic minimizes system complexity by

removing the need for power supply sequencing on the logic control pins. For example, the Fail-Safe Logic

feature allows the select pins of the TMUX1204 to be ramped to 5.5 V while V_DD= 0 V. Additionally, the feature

enables operation of the TMUX1204 with V_DD= 1.2 V while allowing the select pins to interface with a logic level

of another device up to 5.5 V.

TMUX1204

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www.ti.com.cn

8.3 Device Functional Modes

When the EN pin of the TMUX1204 is pulled high, one of the switches is closed based on the state of the

address lines. When the EN pin is pulled low, all the switches are in an open state irrespective of the state of the

address lines. The EN pin can be connected to V_DD(as high as 5.5 V).

The TMUX1204 can be operated without any external components except for the supply decoupling capacitors.

Unused logic control pins should be tied to GND or V_DDin order to ensure the device does not consume

additional current as highlighted in Implications of Slow or Floating CMOS Inputs. Unused signal path inputs (Sx

or D) should be connected to GND.

8.4 Truth Tables

and 表 1 show the truth tables for the TMUX1204, respectively.

表 1. TMUX1204 Truth Table

Selected Channel

Connected To Drain (D) Pin

All channels are off

Channel S1

X⁽¹⁾

Channel S2

Channel S3

Channel S4

(1) X denotes don't care.

TMUX1204

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ZHCSJM4A –APRIL 2019–REVISED OCTOBER 2019

9 Application and Implementation

注

Information in the following applications sections is not part of the TI component

specification, and TI does not warrant its accuracy or completeness. TI’s customers are

responsible for determining suitability of components for their purposes. Customers should

validate and test their design implementation to confirm system functionality.

9.1 Application Information

The TMUX12xx family offers good system performance across a wide operating supply (1.08V to 5.5V). These

devices include 1.8V logic compatible control input pins that enable operation in systems with 1.8V I/O rails.

Additionally, the control input pins support Fail-Safe Logic which allows for operation up to 5.5V, regardless of

the state of the supply pin. This protection stops the logic pins from back-powering the supply rail. These

features make the TMUX12xx a family of general purpose multiplexers and switches that can reduce system

complexity, board size, and overall system cost.

9.2 Typical Application

One useful application to take advantage of the TMUX1204 features is multiplexing various signals into an ADC

that is integrated into a MCU. Utilizing an integrated ADC in a MCU allows a system to minimize cost with a

potential tradeoff of system performance when compared to an external ADC. The multiplexer allows for multiple

inputs/sensors to be monitored with a single ADC pin of the device, which is critical in systems with limited I/O.

V_DD

V_I/O

V_DD

MCU

LDO #1

LDO #2

RAM

FLASH

Integrated

12-bit ADC

LM20

Analog Temp.

Sensor

Port I/O

TIMERS

LM20

Analog Temp.

Sensor

GND

1.8V Logic

I/O

System Inputs

and Sensors

图 18. Multiplexing Signals to Integrated ADC

9.3 Design Requirements

For this design example, use the parameters listed in 表 2.

表 2. Design Parameters

PARAMETERS

Supply (V_DD

VALUES

5.0 V

)

I/O signal range

0 V to V_DD(Rail to Rail)

1.8 V compatible

Control logic thresholds

TMUX1204

ZHCSJM4A –APRIL 2019–REVISED OCTOBER 2019

www.ti.com.cn

9.4 Detailed Design Procedure

The TMUX1204 can be operated without any external components except for the supply decoupling capacitors. If

the parts desired power-up state is disabled, the enable pin should have a weak pull-down resistor and be

controlled by the MCU via GPIO. All inputs being muxed to the ADC of the MCU must fall within the recommend

operating conditions of the TMUX1204 including signal range and continuous current. For this design with a

supply of 5 V the signal range can be 0 V to 5 V and the max continuous current can be 30 mA.

9.5 Application Curve

V_DD= 1.08V

V_DD= 1.62V

V_DD= 3V

V_DD= 4.5V

0.5

1.5

2.5

3.5

Source or Drain Voltage (V)

4.5

D001

T_A= 25°C

图 19. On-Resistance vs Source or Drain Voltage

10 Power Supply Recommendations

The TMUX1204 operates across a wide supply range of 1.08 V to 5.5 V. Do not exceed the absolute maximum

ratings because stresses beyond the listed ratings can cause permanent damage to the devices.

Power-supply bypassing improves noise margin and prevents switching noise propagation from the V_DDsupply to

other components. Good power-supply decoupling is important to achieve optimum performance. For improved

supply noise immunity, use a supply decoupling capacitor ranging from 0.1 μF to 10 μF from V_DDto ground.

Place the bypass capacitors as close to the power supply pins of the device as possible using low-impedance

connections. TI recommends using multi-layer ceramic chip capacitors (MLCCs) that offer low equivalent series

resistance (ESR) and inductance (ESL) characteristics for power-supply decoupling purposes. For very sensitive

systems, or for systems in harsh noise environments, avoiding the use of vias for connecting the capacitors to

the device pins may offer superior noise immunity. The use of multiple vias in parallel lowers the overall

inductance and is beneficial for connections to ground planes.

TMUX1204

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ZHCSJM4A –APRIL 2019–REVISED OCTOBER 2019

11 Layout

11.1 Layout Guidelines

11.1.1 Layout Information

When a PCB trace turns a corner at a 90° angle, a reflection can occur. A reflection occurs primarily because of

the change of width of the trace. At the apex of the turn, the trace width increases to 1.414 times the width. This

increase upsets the transmission-line characteristics, especially the distributed capacitance and self–inductance

of the trace which results in the reflection. Not all PCB traces can be straight and therefore some traces must

turn corners.图 20 shows progressively better techniques of rounding corners. Only the last example (BEST)

maintains constant trace width and minimizes reflections.

WORST

BETTER

BEST

1W min.

图 20. Trace Example

Route high-speed signals using a minimum of vias and corners which reduces signal reflections and

impedance changes. When a via must be used, increase the clearance size around it to minimize its

capacitance. Each via introduces discontinuities in the signal’s transmission line and increases the chance of

picking up interference from the other layers of the board. Be careful when designing test points, through-

hole pins are not recommended at high frequencies.

图 21 illustrates an example of a PCB layout with the TMUX1204. Some key considerations are:

•

Decouple the V_DDpin with a 0.1-µF capacitor, placed as close to the pin as possible. Make sure that the

capacitor voltage rating is sufficient for the V_DDsupply.

•

Keep the input lines as short as possible.

Use a solid ground plane to help reduce electromagnetic interference (EMI) noise pickup.

Do not run sensitive analog traces in parallel with digital traces. Avoid crossing digital and analog traces if

possible, and only make perpendicular crossings when necessary.

11.2 Layout Example

TMUX1204

GND

VDD

Via to

GND plane

Wide (low inductance)

trace for power

图 21. TMUX1204 Layout Example

TMUX1204

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www.ti.com.cn

12 器件和文档支持

12.1 文档支持

12.1.1 相关文档

德州仪器 (TI)，《使用 1.8V 逻辑多路复用器和开关简化设计》。

德州仪器 (TI)，《QFN/SON PCB 连接》。

德州仪器 (TI)，《四方扁平封装无引线逻辑封装》。

12.2 接收文档更新通知

要接收文档更新通知，请导航至 ti.com. 上的器件产品文件夹。单击右上角的通知我进行注册，即可每周接收产品

信息更改摘要。有关更改的详细信息，请查看任何已修订文档中包含的修订历史记录。

12.3 社区资源

TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help — straight

from the experts. Search existing answers or ask your own question to get the quick design help you need.

Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do

not necessarily reflect TI's views; see TI's Terms of Use.

12.4 商标

E2E is a trademark of Texas Instruments.

12.5 静电放电警告

ESD 可能会损坏该集成电路。德州仪器 (TI) 建议通过适当的预防措施处理所有集成电路。如果不遵守正确的处理措施和安装程序 , 可

能会损坏集成电路。

ESD 的损坏小至导致微小的性能降级 , 大至整个器件故障。精密的集成电路可能更容易受到损坏 , 这是因为非常细微的参数更改都可

能会导致器件与其发布的规格不相符。

12.6 Glossary

SLYZ022 — TI Glossary.

This glossary lists and explains terms, acronyms, and definitions.

13 机械、封装和可订购信息

以下页面包含机械、封装和可订购信息。这些信息是指定器件的最新可用数据。数据如有变更，恕不另行通知，且

不会对此文档进行修订。如需获取此数据表的浏览器版本，请查阅左侧的导航栏。

PACKAGE OPTION ADDENDUM

www.ti.com

10-Dec-2020

PACKAGING INFORMATION

Orderable Device

Status Package Type Package Pins Package

Eco Plan

Lead finish/

Ball material

MSL Peak Temp

Op Temp (°C)

Device Marking

Samples

Drawing

Qty

(1)

(2)

(3)

(4/5)

(6)

TMUX1204DGSR

TMUX1204DQAR

ACTIVE

VSSOP

USON

DGS

DQA

2500 RoHS & Green

3000 RoHS & Green

NIPDAUAG

Level-1-260C-UNLIM

-40 to 125

1F6

204

NIPDAU

⁽¹⁾The marketing status values are defined as follows:

ACTIVE: Product device recommended for new designs.

LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.

NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.

PREVIEW: Device has been announced but is not in production. Samples may or may not be available.

OBSOLETE: TI has discontinued the production of the device.

⁽²⁾RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance

do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may

reference these types of products as "Pb-Free".

RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.

Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based

flame retardants must also meet the <=1000ppm threshold requirement.

⁽³⁾MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.

⁽⁴⁾There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.

⁽⁵⁾Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation

of the previous line and the two combined represent the entire Device Marking for that device.

(6)

Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two

lines if the finish value exceeds the maximum column width.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information

provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and

continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.

TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

Addendum-Page 1

PACKAGE OPTION ADDENDUM

www.ti.com

10-Dec-2020

Addendum-Page 2

PACKAGE MATERIALS INFORMATION

www.ti.com

16-Jun-2023

TAPE AND REEL INFORMATION

REEL DIMENSIONS

TAPE DIMENSIONS

Reel

Diameter

Cavity

A0 Dimension designed to accommodate the component width

B0 Dimension designed to accommodate the component length

K0 Dimension designed to accommodate the component thickness

Overall width of the carrier tape

P1 Pitch between successive cavity centers

Reel Width (W1)

QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE

Sprocket Holes

Q1 Q2

Q3 Q4

Q1 Q2

Q3 Q4

User Direction of Feed

Pocket Quadrants

*All dimensions are nominal

Device

Package Package Pins

Type Drawing

SPQ

Reel

Pin1

Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant

(mm) W1 (mm)

TMUX1204DGSR

TMUX1204DQAR

VSSOP

USON

DGS

DQA

2500

3000

330.0

180.0

12.4

9.5

5.3

3.4

1.4

8.0

4.0

12.0

8.0

1.18

2.68

0.72

Pack Materials-Page 1

PACKAGE MATERIALS INFORMATION

www.ti.com

16-Jun-2023

TAPE AND REEL BOX DIMENSIONS

Width (mm)

*All dimensions are nominal

Device

Package Type Package Drawing Pins

SPQ

Length (mm) Width (mm) Height (mm)

TMUX1204DGSR

TMUX1204DQAR

VSSOP

USON

DGS

DQA

2500

3000

364.0

189.0

364.0

185.0

27.0

36.0

Pack Materials-Page 2

PACKAGE OUTLINE

DQA0010A

USON - 0.55 mm max height

SCALE 6.000

PLASTIC SMALL OUTLINE - NO LEAD

1.1

0.9

PIN 1 INDEX AREA

2.6

2.4

0.55 MAX

SEATING PLANE

(0.13) TYP

0.08 C

0.05

0.00

4X 0.5

(R0.125)

0.45

0.35

0.1

C A

0.05

0.25

0.15

PIN 1 ID

(OPTIONAL)

0.1

0.05

C A

0.43

0.30

10X

4220328/A 12/2015

NOTES:

1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing

per ASME Y14.5M.

2. This drawing is subject to change without notice.

www.ti.com

EXAMPLE BOARD LAYOUT

DQA0010A

USON - 0.55 mm max height

PLASTIC SMALL OUTLINE - NO LEAD

10X (0.565)

8X (0.2)

SYMM

2X (0.4)

4X (0.5)

(R0.05) TYP

SYMM

(0.835)

LAND PATTERN EXAMPLE

SCALE:30X

0.07 MIN

ALL AROUND

0.07 MAX

ALL AROUND

SOLDER MASK

OPENING

METAL UNDER

SOLDER MASK

METAL

SOLDER MASK

OPENING

NON SOLDER MASK

DEFINED

SOLDER MASK

DEFINED

(PREFERRED)

SOLDER MASK DETAILS

4220328/A 12/2015

NOTES: (continued)

3. For more information, see Texas Instruments literature number SLUA271 (www.ti.com/lit/slua271).

www.ti.com

EXAMPLE STENCIL DESIGN

DQA0010A

USON - 0.55 mm max height

PLASTIC SMALL OUTLINE - NO LEAD

10X (0.565)

8X (0.2)

METAL

TYP

SYMM

2X (0.36)

4X (0.5)

(R0.05) TYP

SYMM

(0.835)

SOLDER PASTE EXAMPLE

BASED ON 0.1 mm THICK STENCIL

EXPOSED PADS 3 & 8:

90% PRINTED SOLDER COVERAGE BY AREA UNDER PACKAGE

SCALE:40X

4220328/A 12/2015

NOTES: (continued)

4. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate

design recommendations.

www.ti.com

PACKAGE OUTLINE

DGS0010A

VSSOP - 1.1 mm max height

SMALL OUTLINE PACKAGE

SEATING PLANE

0.1 C

5.05

4.75

TYP

PIN 1 ID

AREA

8X 0.5

3.1

2.9

NOTE 3

0.27

0.17

10X

3.1

2.9

1.1 MAX

0.1

C A

NOTE 4

0.23

0.13

TYP

SEE DETAIL A

0.25

GAGE PLANE

0.15

0.05

0.7

0.4

0 - 8

DETAIL A

TYPICAL

4221984/A 05/2015

NOTES:

1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing

per ASME Y14.5M.

2. This drawing is subject to change without notice.

3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not

exceed 0.15 mm per side.

4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.25 mm per side.

5. Reference JEDEC registration MO-187, variation BA.

www.ti.com

EXAMPLE BOARD LAYOUT

DGS0010A

VSSOP - 1.1 mm max height

SMALL OUTLINE PACKAGE

10X (1.45)

(R0.05)

TYP

SYMM

10X (0.3)

SYMM

8X (0.5)

(4.4)

LAND PATTERN EXAMPLE

SCALE:10X

SOLDER MASK

OPENING

SOLDER MASK

OPENING

METAL UNDER

SOLDER MASK

METAL

0.05 MAX

ALL AROUND

0.05 MIN

ALL AROUND

SOLDER MASK

DEFINED

NON SOLDER MASK

DEFINED

SOLDER MASK DETAILS

NOT TO SCALE

4221984/A 05/2015

NOTES: (continued)

6. Publication IPC-7351 may have alternate designs.

7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.

www.ti.com

EXAMPLE STENCIL DESIGN

DGS0010A

VSSOP - 1.1 mm max height

SMALL OUTLINE PACKAGE

10X (1.45)

SYMM

(R0.05) TYP

10X (0.3)

8X (0.5)

SYMM

(4.4)

SOLDER PASTE EXAMPLE

BASED ON 0.125 mm THICK STENCIL

SCALE:10X

4221984/A 05/2015

NOTES: (continued)

8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate

design recommendations.

9. Board assembly site may have different recommendations for stencil design.

www.ti.com

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